From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-ppc/cache.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/asm-ppc/cache.h') diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 9d9b9717dde..3d5f3f7241a 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -19,10 +19,10 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* - * For compatibility reasons support the CFG_CACHELINE_SIZE too + * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too */ -#ifndef CFG_CACHELINE_SIZE -#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES #endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) @@ -44,9 +44,9 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); -#endif /* CFG_INIT_RAM_LOCK */ +#endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ /* prep registers for L2 */ -- cgit v1.3.1 From 54e091d3b603a3332c619199ca83a07e95960da4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 22 Sep 2008 14:11:10 -0500 Subject: 85xx: Export invalidate_{i,d}cache and add flush_dcache Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/cache.h | 1 + 2 files changed, 50 insertions(+) (limited to 'include/asm-ppc/cache.h') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 25d039056e8..fc3c3368afb 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -565,6 +565,7 @@ mck_return: /* Cache functions. */ +.globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 ori r0,r0,L1CSR1_ICFI @@ -574,6 +575,7 @@ invalidate_icache: isync blr /* entire I cache */ +.globl invalidate_dcache invalidate_dcache: mfspr r0,L1CSR0 ori r0,r0,L1CSR0_DCFI @@ -1019,3 +1021,50 @@ unlock_ram_in_cache: tlbivax 0,r3 isync blr + +.globl flush_dcache +flush_dcache: + mfspr r3,SPRN_L1CFG0 + + rlwinm r5,r3,9,3 /* Extract cache block size */ + twlgti r5,1 /* Only 32 and 64 byte cache blocks + * are currently defined. + */ + li r4,32 + subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - + * log2(number of ways) + */ + slw r5,r4,r5 /* r5 = cache block size */ + + rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ + mulli r7,r7,13 /* An 8-way cache will require 13 + * loads per set. + */ + slw r7,r7,r6 + + /* save off HID0 and set DCFA */ + mfspr r8,SPRN_HID0 + ori r9,r8,HID0_DCFA@l + mtspr SPRN_HID0,r9 + isync + + lis r4,0 + mtctr r7 + +1: lwz r3,0(r4) /* Load... */ + add r4,r4,r5 + bdnz 1b + + msync + lis r4,0 + mtctr r7 + +1: dcbf 0,r4 /* ...and flush. */ + add r4,r4,r5 + bdnz 1b + + /* restore HID0 */ + mtspr SPRN_HID0,r8 + isync + + blr diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 3d5f3f7241a..7252be7db2d 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -44,6 +44,7 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); +extern void invalidate_icache(void); #ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CONFIG_SYS_INIT_RAM_LOCK */ -- cgit v1.3.1 From 0f060c3bf82832331a509f2e5d2442539e7aad09 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 23 Oct 2008 01:47:38 -0500 Subject: 85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/release.S | 8 ++++++++ cpu/mpc85xx/start.S | 2 ++ include/asm-ppc/cache.h | 2 ++ 4 files changed, 16 insertions(+) (limited to 'include/asm-ppc/cache.h') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b8f9125c73b..c7806878665 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -134,6 +134,10 @@ int checkcpu (void) puts("Unknown"); break; } + + if (PVR_MEM(pvr) == 0x03) + puts("MC"); + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index ec5e4daf88f..7c3e8a1725a 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -24,14 +24,18 @@ __secondary_start_page: /* First do some preliminary setup */ lis r3, HID0_EMCP@h /* enable machine check */ +#ifndef CONFIG_E500MC ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#endif #ifdef CONFIG_PHYS_64BIT ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ #endif mtspr SPRN_HID0,r3 +#ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr SPRN_HID1,r3 +#endif /* Enable branch prediction */ li r3,0x201 @@ -64,7 +68,11 @@ __secondary_start_page: /* r10 has the base address for the entry */ mfspr r0,SPRN_PIR +#ifdef CONFIG_E500MC + rlwinm r4,r0,27,27,31 +#else mr r4,r0 +#endif slwi r8,r4,5 add r10,r3,r8 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index f16d4c0c405..651ff1c02c9 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -163,8 +163,10 @@ _start_e500: ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0 +#ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0 +#endif /* Enable Branch Prediction */ #if defined(CONFIG_BTB) diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 7252be7db2d..53e8d05f50b 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -12,6 +12,8 @@ #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 +#elif defined(CONFIG_E500MC) +#define L1_CACHE_SHIFT 6 #else #define L1_CACHE_SHIFT 5 #endif -- cgit v1.3.1