From 0e870980a64584a591af775bb9c9fe9450124df9 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 31 Jul 2009 12:08:14 +0530 Subject: 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 28411045151..a079b2d4cb5 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1065,13 +1065,14 @@ n: struct cpu_type { char name[15]; u32 soc_ver; + u32 num_cores; }; struct cpu_type *identify_cpu(u32 ver); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) -#define CPU_TYPE_ENTRY(n, v) \ - { .name = #n, .soc_ver = SVR_##v, } +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } #else #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} -- cgit v1.2.3 From 87c7661b42aa7672539b54b51d3d5c4013ec6f6c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 31 Jul 2009 12:08:27 +0530 Subject: 85xx: Added P1020 Processor Support. P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index a079b2d4cb5..5547245d5e7 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1011,6 +1011,8 @@ #define SVR_8572_E 0x80E800 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P1020 0x80E400 +#define SVR_P1020_E 0x80EC00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.2.3 From a713ba926b45da9a6f923f1ac9e60a66852e5f2d Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 20 Aug 2009 18:57:45 +0530 Subject: 85xx: Added single core members of FSL P1xx/P2xx processors series P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 5547245d5e7..dcaf8c030a3 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1009,10 +1009,14 @@ #define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 #define SVR_8572_E 0x80E800 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 +#define SVR_P1011 0x80E500 +#define SVR_P1011_E 0x80ED00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 +#define SVR_P2010 0x80E300 +#define SVR_P2010_E 0x80EB00 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.2.3