From 69bcf5bc80a47acbd62b8cfff932cb12d47997d7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 29 Mar 2010 13:50:31 -0500 Subject: 85xx: Add defines for BUCSR bits to make code more readable Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9b3d616a671..4134f189a44 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -533,6 +533,9 @@ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */ +#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ +#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ -- cgit v1.3.1 From 216082754f6da5359ea0db9b0cc03ad531ac6e45 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 30 Mar 2010 23:06:53 -0500 Subject: 85xx: Added various P1012/P1013/P1021/P1022 defines There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang Signed-off-by: Srikanth Srinivasan Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 4 ++++ cpu/mpc8xxx/cpu.c | 10 +++++++++- cpu/mpc8xxx/pci_cfg.c | 30 +++++++++++++++++++++++++++--- drivers/misc/fsl_law.c | 4 +++- include/asm-ppc/config.h | 3 ++- include/asm-ppc/processor.h | 8 ++++++++ 6 files changed, 53 insertions(+), 6 deletions(-) (limited to 'include/asm-ppc/processor.h') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 56de7eb3818..f064fee26b6 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -50,7 +50,11 @@ COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o COBJS-$(CONFIG_P1011) += ddr-gen3.o +COBJS-$(CONFIG_P1012) += ddr-gen3.o +COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o +COBJS-$(CONFIG_P1021) += ddr-gen3.o +COBJS-$(CONFIG_P1022) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index d191263f508..47842e98da7 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. * Basically this file contains cpu specific common code for 85xx/86xx @@ -66,8 +66,16 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(P1011, P1011, 1), CPU_TYPE_ENTRY(P1011, P1011_E, 1), + CPU_TYPE_ENTRY(P1012, P1012, 1), + CPU_TYPE_ENTRY(P1012, P1012_E, 1), + CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), + CPU_TYPE_ENTRY(P1021, P1021, 2), + CPU_TYPE_ENTRY(P1021, P1021_E, 2), + CPU_TYPE_ENTRY(P1022, P1022, 2), + CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c index d53781b62b3..9b7181d5b6f 100644 --- a/cpu/mpc8xxx/pci_cfg.c +++ b/cpu/mpc8xxx/pci_cfg.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,7 +25,7 @@ #include struct pci_info { - u16 cfg; + u32 cfg; }; /* The cfg field is a bit mask in which each bit represents the value of @@ -153,7 +153,8 @@ static struct pci_info pci_config_info[] = (1 << 7) | (1 << 0xe) | (1 << 0xf), }, }; -#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1012) || defined(CONFIG_P1021) static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { @@ -163,6 +164,29 @@ static struct pci_info pci_config_info[] = .cfg = (1 << 0xe), }, }; +#elif defined(CONFIG_P1013) || defined(CONFIG_P1022) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) | + (1 << 0xb) | (1 << 0xd) | (1 << 0xe) | + (1 << 0xf) | (1 << 0x15) | (1 << 0x16) | + (1 << 0x17) | (1 << 0x18) | (1 << 0x19) | + (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) | + (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | + (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | + (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | + (1 << 0x18) | (1 << 0x1c), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) | + (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | + (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b), + }, +}; #elif defined(CONFIG_P2010) || defined(CONFIG_P2020) static struct pci_info pci_config_info[] = { diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 287e5559005..8255175d2a0 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ + defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 #elif defined(CONFIG_PPC_P4080) diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 0d78aa400e5..fc3facb3076 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -41,6 +41,7 @@ #endif #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 #elif defined(CONFIG_PPC_P4080) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 4134f189a44..2b027747155 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1035,8 +1035,16 @@ #define SVR_8572_E 0x80E800 #define SVR_P1011 0x80E500 #define SVR_P1011_E 0x80ED00 +#define SVR_P1012 0x80E501 +#define SVR_P1012_E 0x80ED01 +#define SVR_P1013 0x80E700 +#define SVR_P1013_E 0x80EF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 +#define SVR_P1021 0x80E401 +#define SVR_P1021_E 0x80EC01 +#define SVR_P1022 0x80E600 +#define SVR_P1022_E 0x80EE00 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -- cgit v1.3.1 From ff8473e90a018c2bb19a196176c1f2e9602d6354 Mon Sep 17 00:00:00 2001 From: Sandeep Gopalpet Date: Fri, 12 Mar 2010 10:45:02 +0530 Subject: 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet --- cpu/mpc85xx/release.S | 7 +++++++ cpu/mpc85xx/start.S | 7 +++++++ include/asm-ppc/processor.h | 1 + 3 files changed, 15 insertions(+) (limited to 'include/asm-ppc/processor.h') diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 69fce927a6c..0b5b9da032a 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -57,6 +57,13 @@ __secondary_start_page: #ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: mtspr SPRN_HID1,r3 #endif diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 52ea9b34167..b3cb56a5b00 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -208,6 +208,13 @@ _start_e500: #ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: mtspr HID1,r0 #endif diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 2b027747155..9ec319ae170 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ -- cgit v1.3.1