From 4c52783b3d024e153c4972b97332e314bc3bdc46 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:49:51 +0800 Subject: General code modification for mpc7448hpc2 board support. 1. Add 7447A and 7448 processor support. 2. Add the following flags. CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically (such as by switch on board), this flag should be set. CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot relocates to RAM, this flag should be set. CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the system hang in exception, this flag should be set. There is a design issue for tsi108/109 pci configure read. When pci scan the slots, if there is no pci card, the tsi108/9 will cause a machine check exception for mpc7448 processor. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- include/asm-ppc/global_data.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index b73af96464a..166afbe87a1 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -49,6 +49,9 @@ typedef struct global_data { unsigned long scc_clk; unsigned long brg_clk; #endif +#if defined(CONFIG_MPC7448HPC2) + unsigned long mem_clk; +#endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -- cgit v1.3.1 From e080313c32322e15ab5a18eb896a252858c57284 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Thu, 7 Dec 2006 21:11:58 +0800 Subject: mpc83xx: streamline the 83xx immr head file For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu --- board/tqm834x/tqm834x.c | 4 +- cpu/mpc83xx/cpu_init.c | 8 +- cpu/mpc83xx/qe_io.c | 2 +- cpu/mpc83xx/speed.c | 14 +- include/asm-ppc/immap_83xx.h | 1892 +++++------------------------------------- include/mpc83xx.h | 1263 ++++++++++++++++++++-------- 6 files changed, 1122 insertions(+), 2061 deletions(-) (limited to 'include/asm-ppc') diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 36d901f0942..9c35e22c8e1 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -148,14 +148,14 @@ int checkboard (void) u32 w, f; immr = (immap_t *)CFG_IMMR; - if (!(immr->reset.rcwh & RCWH_PCIHOST)) { + if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { printf("PCI: NOT in host mode..?!\n"); return 0; } /* get bus width */ w = 32; - if (immr->reset.rcwh & RCWH_PCI64) + if (immr->reset.rcwh & HRCWH_64_BIT_PCI) w = 64; /* get clock */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e5725fb91d9..7574fabf864 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -202,12 +202,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; #endif #ifdef CFG_GPIO1_PRELIM - im->pgio[0].dir = CFG_GPIO1_DIR; - im->pgio[0].dat = CFG_GPIO1_DAT; + im->gpio[0].dir = CFG_GPIO1_DIR; + im->gpio[0].dat = CFG_GPIO1_DAT; #endif #ifdef CFG_GPIO2_PRELIM - im->pgio[1].dir = CFG_GPIO2_DIR; - im->pgio[1].dat = CFG_GPIO2_DAT; + im->gpio[1].dir = CFG_GPIO2_DIR; + im->gpio[1].dat = CFG_GPIO2_DAT; #endif } diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index ebe34871120..8b3937aa9b9 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -35,7 +35,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_1bit_mask; u32 tmp_val; volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 7e53b1e6061..40ba6b04a3b 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -139,7 +139,7 @@ int get_clocks(void) #endif } - spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); csb_clk = pci_sync_in * (1 + clkin_div) * spmf; sccr = im->clk.sccr; @@ -251,7 +251,7 @@ int get_clocks(void) } #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) lbiu_clk = csb_clk * - (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); + (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); #else #error Unknown MPC83xx chip #endif @@ -268,11 +268,11 @@ int get_clocks(void) } #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ddr_clk = csb_clk * - (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); - corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; + (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; #if defined (CONFIG_MPC8360) ddr_sec_clk = csb_clk * (1 + - ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); #endif #else #error Unknown MPC83xx chip @@ -307,8 +307,8 @@ int get_clocks(void) } #if defined (CONFIG_MPC8360) - qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT; - qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT; + qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; + qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); brg_clk = qe_clk / 2; #endif diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 43cde5e28ef..67b035c6140 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -3,20 +3,11 @@ * * MPC83xx Internal Memory Map * - * History : - * 20060601: Daveliu (daveliu@freescale.com) - * TanyaJiang (tanya.jiang@freescale.com) - * Unified variable names for mpc83xx - * 2005 : Mandy Lavi (mandy.lavi@freescale.com) - * support for mpc8360e - * 2004 : Eran Liberty (liberty@freescale.com) - * Initialized for mpc8349 - * based on: - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * MPC85xx Internal Memory Map - * Copyright(c) 2002,2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) + * Contributors: + * Dave Liu + * Tanya Jiang + * Mandy Lavi + * Eran Liberty * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -37,36 +28,24 @@ #ifndef __IMMAP_83xx__ #define __IMMAP_83xx__ -#include #include #include /* - * Local Access Window. + * Local Access Window */ typedef struct law83xx { u32 bar; /* LBIU local access window base address register */ -/* Identifies the 20 most-significant address bits of the base of local - * access window n. The specified base address should be aligned to the - * window size, as defined by LBLAWARn[SIZE]. - */ -#define LAWBAR_BAR 0xFFFFF000 -#define LAWBAR_RES ~(LAWBAR_BAR) u32 ar; /* LBIU local access window attribute register */ } law83xx_t; /* - * System configuration registers. + * System configuration registers */ typedef struct sysconf83xx { u32 immrbar; /* Internal memory map base address register */ u8 res0[0x04]; u32 altcbar; /* Alternate configuration base address register */ -/* Identifies the12 most significant address bits of an alternate base - * address used for boot sequencer configuration accesses. - */ -#define ALTCBAR_BASE_ADDR 0xFFF00000 -#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ u8 res1[0x14]; law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; @@ -77,115 +56,10 @@ typedef struct sysconf83xx { u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ u8 res5[0x04]; u32 spcr; /* System Priority Configuration Register */ -#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ -#define SPCR_PCIHPE_SHIFT (31-3) -#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ -#define SPCR_PCIPR_SHIFT (31-7) -#define SPCR_OPT 0x00800000 /* Optimize */ -#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ -#define SPCR_TBEN_SHIFT (31-9) -#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ -#define SPCR_COREPR_SHIFT (31-11) -#if defined (CONFIG_MPC8349) -#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ -#define SPCR_TSEC1DP_SHIFT (31-19) -#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ -#define SPCR_TSEC1BDP_SHIFT (31-21) -#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ -#define SPCR_TSEC1EP_SHIFT (31-23) -#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ -#define SPCR_TSEC2DP_SHIFT (31-27) -#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ -#define SPCR_TSEC2BDP_SHIFT (31-29) -#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ -#define SPCR_TSEC2EP_SHIFT (31-31) -#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ - | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ - | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) -#elif defined (CONFIG_MPC8360) -#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) -#endif - u32 sicrl; /* System General Purpose Register Low */ -#if defined (CONFIG_MPC8349) -#define SICRL_LDP_A 0x80000000 -#define SICRL_USB1 0x40000000 -#define SICRL_USB0 0x20000000 -#define SICRL_UART 0x0C000000 -#define SICRL_GPIO1_A 0x02000000 -#define SICRL_GPIO1_B 0x01000000 -#define SICRL_GPIO1_C 0x00800000 -#define SICRL_GPIO1_D 0x00400000 -#define SICRL_GPIO1_E 0x00200000 -#define SICRL_GPIO1_F 0x00180000 -#define SICRL_GPIO1_G 0x00040000 -#define SICRL_GPIO1_H 0x00020000 -#define SICRL_GPIO1_I 0x00010000 -#define SICRL_GPIO1_J 0x00008000 -#define SICRL_GPIO1_K 0x00004000 -#define SICRL_GPIO1_L 0x00003000 -#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \ - | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \ - | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ - | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ - | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) -#elif defined (CONFIG_MPC8360) -#define SICRL_LDP_A 0xC0000000 -#define SICRL_LCLK_1 0x10000000 -#define SICRL_LCLK_2 0x08000000 -#define SICRL_SRCID_A 0x03000000 -#define SICRL_IRQ_CKSTP_A 0x00C00000 -#define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \ - SICRL_SRCID_A | SICRL_IRQ_CKSTP_A) -#endif - u32 sicrh; /* System General Purpose Register High */ -#define SICRH_DDR 0x80000000 -#if defined (CONFIG_MPC8349) -#define SICRH_TSEC1_A 0x10000000 -#define SICRH_TSEC1_B 0x08000000 -#define SICRH_TSEC1_C 0x04000000 -#define SICRH_TSEC1_D 0x02000000 -#define SICRH_TSEC1_E 0x01000000 -#define SICRH_TSEC1_F 0x00800000 -#define SICRH_TSEC2_A 0x00400000 -#define SICRH_TSEC2_B 0x00200000 -#define SICRH_TSEC2_C 0x00100000 -#define SICRH_TSEC2_D 0x00080000 -#define SICRH_TSEC2_E 0x00040000 -#define SICRH_TSEC2_F 0x00020000 -#define SICRH_TSEC2_G 0x00010000 -#define SICRH_TSEC2_H 0x00008000 -#define SICRH_GPIO2_A 0x00004000 -#define SICRH_GPIO2_B 0x00002000 -#define SICRH_GPIO2_C 0x00001000 -#define SICRH_GPIO2_D 0x00000800 -#define SICRH_GPIO2_E 0x00000400 -#define SICRH_GPIO2_F 0x00000200 -#define SICRH_GPIO2_G 0x00000180 -#define SICRH_GPIO2_H 0x00000060 -#define SICRH_TSOBI1 0x00000002 -#define SICRH_TSOBI2 0x00000001 -#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ - | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ - | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ - | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ - | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \ - | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \ - | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ - | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ - | SICRH_TSOBI2) -#elif defined (CONFIG_MPC8360) -#define SICRH_SECONDARY_DDR 0x40000000 -#define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */ -#define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */ -#define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */ -#define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */ -#define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \ - SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) -#endif + u32 sicrl; /* System I/O Configuration Register Low */ + u32 sicrh; /* System I/O Configuration Register High */ u8 res6[0xE4]; } sysconf83xx_t; @@ -196,11 +70,8 @@ typedef struct wdt83xx { u8 res0[4]; u32 swcrr; /* System watchdog control register */ u32 swcnr; /* System watchdog count register */ -#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. -#define SWCNR_RES ~(SWCNR_SWCN) u8 res1[2]; u16 swsrr; /* System watchdog service register */ -#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */ u8 res2[0xF0]; } wdt83xx_t; @@ -209,91 +80,46 @@ typedef struct wdt83xx { */ typedef struct rtclk83xx { u32 cnr; /* control register */ -#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ -#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ -#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ -#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ -#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) u32 ldr; /* load register */ -#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be - * loaded in a 32-bit RTC counter.*/ u32 psr; /* prescale register */ -#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */ - u32 ctr; /* Counter value field register */ -#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */ + u32 ctr; /* counter value field register */ u32 evr; /* event register */ -#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ -#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ -#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF) -#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */ -#define PTEVR_RES ~(PTEVR_PIF) u32 alr; /* alarm register */ u8 res0[0xE8]; } rtclk83xx_t; /* - * Global timper module + * Global timer module */ - typedef struct gtm83xx { - u8 cfr1; /* Timer1/2 Configuration */ -#define CFR1_PCAS 0x80 /* Pair Cascade mode */ -#define CFR1_BCM 0x40 /* Backward compatible mode */ -#define CFR1_STP2 0x20 /* Stop timer */ -#define CFR1_RST2 0x10 /* Reset timer */ -#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ -#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ -#define CFR1_STP1 0x02 /* Stop timer */ -#define CFR1_RST1 0x01 /* Reset timer */ -#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\ - CFR1_GM1 | CFR1_STP1 | CFR1_RST1) + u8 cfr1; /* Timer1/2 Configuration */ u8 res0[3]; - u8 cfr2; /* Timer3/4 Configuration */ -#define CFR2_PCAS 0x80 /* Pair Cascade mode */ -#define CFR2_SCAS 0x40 /* Super Cascade mode */ -#define CFR2_STP4 0x20 /* Stop timer */ -#define CFR2_RST4 0x10 /* Reset timer */ -#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ -#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ -#define CFR2_STP3 0x02 /* Stop timer */ -#define CFR2_RST3 0x01 /* Reset timer */ + u8 cfr2; /* Timer3/4 Configuration */ u8 res1[10]; - u16 mdr1; /* Timer1 Mode Register */ -#define MDR_SPS 0xff00 /* Secondary Prescaler value */ -#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ -#define MDR_OM 0x0020 /* Output mode */ -#define MDR_ORI 0x0010 /* Output reference interrupt enable */ -#define MDR_FRR 0x0008 /* Free run/restart */ -#define MDR_ICLK 0x0006 /* Input clock source for the timer */ -#define MDR_GE 0x0001 /* Gate enable */ - u16 mdr2; /* Timer2 Mode Register */ - u16 rfr1; /* Timer1 Reference Register */ - u16 rfr2; /* Timer2 Reference Register */ - u16 cpr1; /* Timer1 Capture Register */ - u16 cpr2; /* Timer2 Capture Register */ - u16 cnr1; /* Timer1 Counter Register */ - u16 cnr2; /* Timer2 Counter Register */ - u16 mdr3; /* Timer3 Mode Register */ - u16 mdr4; /* Timer4 Mode Register */ - u16 rfr3; /* Timer3 Reference Register */ - u16 rfr4; /* Timer4 Reference Register */ - u16 cpr3; /* Timer3 Capture Register */ - u16 cpr4; /* Timer4 Capture Register */ - u16 cnr3; /* Timer3 Counter Register */ - u16 cnr4; /* Timer4 Counter Register */ - u16 evr1; /* Timer1 Event Register */ - u16 evr2; /* Timer2 Event Register */ - u16 evr3; /* Timer3 Event Register */ - u16 evr4; /* Timer4 Event Register */ -#define GTEVR_REF 0x0002 /* Output reference event */ -#define GTEVR_CAP 0x0001 /* Counter Capture event */ -#define GTEVR_RES ~(EVR_CAP|EVR_REF) - u16 psr1; /* Timer1 Prescaler Register */ - u16 psr2; /* Timer2 Prescaler Register */ - u16 psr3; /* Timer3 Prescaler Register */ - u16 psr4; /* Timer4 Prescaler Register */ -#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */ -#define GTPSR_RES ~(GTPSR_PPS) + u16 mdr1; /* Timer1 Mode Register */ + u16 mdr2; /* Timer2 Mode Register */ + u16 rfr1; /* Timer1 Reference Register */ + u16 rfr2; /* Timer2 Reference Register */ + u16 cpr1; /* Timer1 Capture Register */ + u16 cpr2; /* Timer2 Capture Register */ + u16 cnr1; /* Timer1 Counter Register */ + u16 cnr2; /* Timer2 Counter Register */ + u16 mdr3; /* Timer3 Mode Register */ + u16 mdr4; /* Timer4 Mode Register */ + u16 rfr3; /* Timer3 Reference Register */ + u16 rfr4; /* Timer4 Reference Register */ + u16 cpr3; /* Timer3 Capture Register */ + u16 cpr4; /* Timer4 Capture Register */ + u16 cnr3; /* Timer3 Counter Register */ + u16 cnr4; /* Timer4 Counter Register */ + u16 evr1; /* Timer1 Event Register */ + u16 evr2; /* Timer2 Event Register */ + u16 evr3; /* Timer3 Event Register */ + u16 evr4; /* Timer4 Event Register */ + u16 psr1; /* Timer1 Prescaler Register */ + u16 psr2; /* Timer2 Prescaler Register */ + u16 psr3; /* Timer3 Prescaler Register */ + u16 psr4; /* Timer4 Prescaler Register */ u8 res[0xC0]; } gtm83xx_t; @@ -301,188 +127,31 @@ typedef struct gtm83xx { * Integrated Programmable Interrupt Controller */ typedef struct ipic83xx { - u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ -#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ -#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ -#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ -#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ -#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ -#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ -#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) - u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ -#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ -#define SICVR_IVEC 0x0000007f /* Interrupt vector */ -#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) - u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ -#if defined (CONFIG_MPC8349) -#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ -#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ -#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ -#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ -#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ -#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ -#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ -#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ -#endif -#if defined (CONFIG_MPC8360) -#define SIIH_H_QE_H 0x80000000 /* QE high interrupt */ -#define SIIH_H_QE_L 0x40000000 /* QE low interrupt */ -#endif -#define SIIH_UART1 0x00000080 /* UART1 interrupt */ -#define SIIH_UART2 0x00000040 /* UART2 interrupt */ -#define SIIH_SEC 0x00000020 /* SEC interrupt */ -#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ -#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIH_SPI 0x00000001 /* SPI interrupt */ -#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ - | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ - | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ - | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ - | SIIH_I2C2 | SIIH_SPI) -#endif -#if defined (CONFIG_MPC8360) -#define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \ - SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2) -#endif - u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ -#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ -#define SIIL_PIT 0x40000000 /* PIT interrupt */ -#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ -#endif -#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ -#define SIIL_MU 0x04000000 /* Message Unit interrupt */ -#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ -#define SIIL_DMA 0x01000000 /* DMA interrupt */ -#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ -#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ -#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ -#endif -#if defined (CONFIG_MPC8360) -#define SIIL_QEP 0x00200000 /* QE ports interrupt */ -#define SIIL_SDDR 0x00100000 /* SDDR interrupt */ -#endif -#define SIIL_DDR 0x00080000 /* DDR interrupt */ -#define SIIL_LBC 0x00040000 /* LBC interrupt */ -#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ -#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ -#define SIIL_PMC 0x00008000 /* PMC interrupt */ -#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ -#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ -#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ -#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ -#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ -#if defined (CONFIG_MPC8349) -#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ - | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ - | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ - | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ - | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ - | SIIL_GTM5 |SIIL_DPTC ) -#endif -#if defined (CONFIG_MPC8360) -#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ - |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ - |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ - |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ - |SIIL_GTM5 ) -#endif - u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ + u32 sicfr; /* System Global Interrupt Configuration Register */ + u32 sivcr; /* System Global Interrupt Vector Register */ + u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ + u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ + u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ u8 res0[8]; - u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ - u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ - u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ + u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ + u32 simsr_h; /* System Internal Interrupt Mask Register - High */ + u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ u8 res1[4]; - u32 sepnr; /* System External Interrupt Pending Register (SEI) */ - u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ - u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ -#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ -#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ -#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ -#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ -#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ -#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ -#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ -#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ -#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) - u32 semsr; /* System External Interrupt Mask Register (SEI) */ -#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ -#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ -#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ -#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ -#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ -#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ -#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ -#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ -#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ -#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ - | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ - | SEI_SIRQ0) - u32 secnr; /* System External Interrupt Control Register (SECNR) */ -#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ -#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ -#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ -#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ -#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ -#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ -#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ -#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ -#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ -#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ -#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ -#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ -#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ - | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ - | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ - | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) - u32 sersr; /* System Error Status Register (SERR) */ - u32 sermr; /* System Error Mask Register (SERR) */ -#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ -#define SERR_WDT 0x40000000 /* WDT MCP request */ -#define SERR_SBA 0x20000000 /* SBA MCP request */ -#if defined (CONFIG_MPC8349) -#define SERR_DDR 0x10000000 /* DDR MCP request */ -#define SERR_LBC 0x08000000 /* LBC MCP request */ -#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ -#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ -#endif -#if defined (CONFIG_MPC8360) -#define SERR_CIEE 0x10000000 /* CIEE MCP request */ -#define SERR_CMEE 0x08000000 /* CMEEMCP request */ -#define SERR_PCI 0x04000000 /* PCI MCP request */ -#endif -#define SERR_MU 0x01000000 /* MU MCP request */ -#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ -#if defined (CONFIG_MPC8349) -#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ - |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ - |SERR_RNC ) -#elif defined (CONFIG_MPC8360) -#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ - |SERR_CMEE|SERR_PCI|SERR_MU) -#endif - u32 sercr; /* System Error Control Register (SERCR) */ -#define SERCR_MCPR 0x00000001 /* MCP Route */ -#define SERCR_RES ~(SERCR_MCPR) + u32 sepnr; /* System External Interrupt Pending Register */ + u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ + u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ + u32 semsr; /* System External Interrupt Mask Register */ + u32 secnr; /* System External Interrupt Control Register */ + u32 sersr; /* System Error Status Register */ + u32 sermr; /* System Error Mask Register */ + u32 sercr; /* System Error Control Register */ u8 res2[4]; - u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ - u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ - u32 sefcr; /* System External Interrupt Force Register (SEI) */ - u32 serfr; /* System Error Force Register (SERR) */ + u32 sifcr_h; /* System Internal Interrupt Force Register - High */ + u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ + u32 sefcr; /* System External Interrupt Force Register */ + u32 serfr; /* System Error Force Register */ u32 scvcr; /* System Critical Interrupt Vector Register */ -#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible - critical interrupt vector. */ -#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */ -#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC) u32 smvcr; /* System Management Interrupt Vector Register */ -#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible - critical interrupt vector. */ -#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */ -#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC) u8 res3[0x98]; } ipic83xx_t; @@ -491,43 +160,14 @@ typedef struct ipic83xx { */ typedef struct arbiter83xx { u32 acr; /* Arbiter Configuration Register */ -#define ACR_COREDIS 0x10000000 /* Core disable. */ -#define ACR_COREDIS_SHIFT (31-7) -#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ -#define ACR_PIPE_DEP_SHIFT (31-15) -#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ -#define ACR_PCI_RPTCNT_SHIFT (31-19) -#define ACR_RPTCNT 0x00000700 /* Repeat count. */ -#define ACR_RPTCNT_SHIFT (31-23) -#define ACR_APARK 0x00000030 /* Address parking. */ -#define ACR_APARK_SHIFT (31-27) -#define ACR_PARKM 0x0000000F /* Parking master. */ -#define ACR_PARKM_SHIFT (31-31) -#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) u32 atr; /* Arbiter Timers Register */ -#define ATR_DTO 0x00FF0000 /* Data time out. */ -#define ATR_ATO 0x000000FF /* Address time out. */ -#define ATR_RES ~(ATR_DTO|ATR_ATO) u8 res[4]; - u32 aer; /* Arbiter Event Register (AE) */ - u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ - u32 amr; /* Arbiter Mask Register (AE) */ + u32 aer; /* Arbiter Event Register */ + u32 aidr; /* Arbiter Interrupt Definition Register */ + u32 amr; /* Arbiter Mask Register */ u32 aeatr; /* Arbiter Event Attributes Register */ -#define AEATR_EVENT 0x07000000 /* Event type. */ -#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ -#define AEATR_TBST 0x00000800 /* Transfer burst. */ -#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ -#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ -#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register (AE) */ -#define AE_ETEA 0x00000020 /* Transfer error. */ -#define AE_RES_ 0x00000010 /* Reserved transfer type. */ -#define AE_ECW 0x00000008 /* External control word transfer type. */ -#define AE_AO 0x00000004 /* Address Only transfer type. */ -#define AE_DTO 0x00000002 /* Data time out. */ -#define AE_ATO 0x00000001 /* Address time out. */ -#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) + u32 aerr; /* Arbiter Event Response Register */ u8 res1[0xDC]; } arbiter83xx_t; @@ -535,184 +175,24 @@ typedef struct arbiter83xx { * Reset Module */ typedef struct reset83xx { - u32 rcwl; /* RCWL Register */ -#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ -#define RCWL_LBIUCM_SHIFT 31 -#define RCWL_DDRCM 0x40000000 /* DDRCM */ -#define RCWL_DDRCM_SHIFT 30 -#if defined (CONFIG_MPC8349) -#define RCWL_SVCOD 0x30000000 /* SVCOD */ -#endif -#define RCWL_SPMF 0x0f000000 /* SPMF */ -#define RCWL_SPMF_SHIFT 24 -#define RCWL_COREPLL 0x007F0000 /* COREPLL */ -#define RCWL_COREPLL_SHIFT 16 -#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ -#define RCWL_CEPDF 0x00000020 /* CEPDF */ -#define RCWL_CEPDF_SHIFT 5 -#define RCWL_CEPMF 0x0000001F /* CEPMF */ -#define RCWL_CEPMF_SHIFT 0 -#if defined (CONFIG_MPC8349) -#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) -#elif defined (CONFIG_MPC8360) -#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) -#endif - u32 rcwh; /* RCHL Register */ -#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#define RCWH_PCIHOST_SHIFT 31 -#if defined (CONFIG_MPC8349) -#define RCWH_PCI64 0x40000000 /* PCI64 */ -#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ -#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ -#elif defined (CONFIG_MPC8360) -#define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */ -#define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */ -#endif -#define RCWH_COREDIS 0x08000000 /* COREDIS */ -#define RCWH_BMS 0x04000000 /* BMS */ -#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ -#define RCWH_SWEN 0x00800000 /* SWEN */ -#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ -#if defined (CONFIG_MPC8349) -#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ -#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ -#define RCWH_TPR 0x00000100 /* TPR */ -#elif defined (CONFIG_MPC8360) -#define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */ -#endif -#define RCWH_TLE 0x00000008 /* TLE */ -#define RCWH_LALE 0x00000004 /* LALE */ -#if defined (CONFIG_MPC8349) -#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ - | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ - | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ - | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ - | RCWH_TLE | RCWH_LALE) -#elif defined (CONFIG_MPC8360) -#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \ - |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \ - |RCWH_SDDRIOE |RCWH_TLE) -#endif + u32 rcwl; /* Reset Configuration Word Low Register */ + u32 rcwh; /* Reset Configuration Word High Register */ u8 res0[8]; - u32 rsr; /* Reset status Register */ -#define RSR_RSTSRC 0xE0000000 /* Reset source */ -#define RSR_RSTSRC_SHIFT 29 -#define RSR_BSF 0x00010000 /* Boot seq. fail */ -#define RSR_BSF_SHIFT 16 -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWSR_SHIFT 13 -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_SWHR_SHIFT 12 -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JHRS_SHIFT 9 -#define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_JSRS_SHIFT 8 -#define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_CSHR_SHIFT 4 -#define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_SWRS_SHIFT 3 -#define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_BMRS_SHIFT 2 -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_SRS_SHIFT 1 -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_HRS_SHIFT 0 -#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) - u32 rmr; /* Reset mode Register */ -#define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 -#define RMR_RES ~(RMR_CSRE) - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ -#define RCR_RES ~(RCR_SWHR | RCR_SWSR) - u32 rcer; /* Reset Control Enable Register */ -#define RCER_CRE 0x00000001 /* software hard reset */ -#define RCER_RES ~(RCER_CRE) + u32 rsr; /* Reset Status Register */ + u32 rmr; /* Reset Mode Register */ + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ + u32 rcer; /* Reset Control Enable Register */ u8 res1[0xDC]; } reset83xx_t; +/* + * Clock Module + */ typedef struct clk83xx { - u32 spmr; /* system PLL mode Register */ -#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ -#define SPMR_DDRCM 0x40000000 /* DDRCM */ -#if defined (CONFIG_MPC8349) -#define SPMR_SVCOD 0x30000000 /* SVCOD */ -#endif -#define SPMR_SPMF 0x0F000000 /* SPMF */ -#define SPMR_CKID 0x00800000 /* CKID */ -#define SPMR_CKID_SHIFT 23 -#define SPMR_COREPLL 0x007F0000 /* COREPLL */ -#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ -#define SPMR_CEPDF 0x00000020 /* CEPDF */ -#define SPMR_CEPMF 0x0000001F /* CEPMF */ -#if defined (CONFIG_MPC8349) -#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ - | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ - | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) -#elif defined (CONFIG_MPC8360) -#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \ - | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \ - | SPMR_CEPDF | SPMR_CEPMF) -#endif - u32 occr; /* output clock control Register */ -#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ -#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ -#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ -#if defined (CONFIG_MPC8349) -#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ -#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ -#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ -#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ -#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ -#endif -#define OCCR_PCICD0 0x00800000 /* PCICD0 */ -#define OCCR_PCICD1 0x00400000 /* PCICD1 */ -#define OCCR_PCICD2 0x00200000 /* PCICD2 */ -#if defined (CONFIG_MPC8349) -#define OCCR_PCICD3 0x00100000 /* PCICD3 */ -#define OCCR_PCICD4 0x00080000 /* PCICD4 */ -#define OCCR_PCICD5 0x00040000 /* PCICD5 */ -#define OCCR_PCICD6 0x00020000 /* PCICD6 */ -#define OCCR_PCICD7 0x00010000 /* PCICD7 */ -#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ -#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ -#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ - | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ - | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ - | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ - | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ - | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) -#endif -#if defined (CONFIG_MPC8360) -#define OCCR_PCICR 0x00000002 /* PCI clock rate */ -#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \ - |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) -#endif - u32 sccr; /* system clock control Register */ -#if defined (CONFIG_MPC8349) -#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ -#define SCCR_TSEC1CM_SHIFT 30 -#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ -#define SCCR_TSEC2CM_SHIFT 28 -#endif -#define SCCR_ENCCM 0x03000000 /* ENCCM */ -#define SCCR_ENCCM_SHIFT 24 -#if defined (CONFIG_MPC8349) -#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ -#define SCCR_USBMPHCM_SHIFT 22 -#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ -#define SCCR_USBDRCM_SHIFT 20 -#endif -#define SCCR_PCICM 0x00010000 /* PCICM */ -#if defined (CONFIG_MPC8349) -#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ - | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) -#endif -#if defined (CONFIG_MPC8360) -#define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM) -#endif + u32 spmr; /* system PLL mode Register */ + u32 occr; /* output clock control Register */ + u32 sccr; /* system clock control Register */ u8 res0[0xF4]; } clk83xx_t; @@ -720,27 +200,14 @@ typedef struct clk83xx { * Power Management Control Module */ typedef struct pmc83xx { - u32 pmccr; /* PMC Configuration Register */ -#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ -#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ -#if defined (CONFIG_MPC8360) -#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ -#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) -#elif defined (CONFIG_MPC8349) -#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) -#endif - u32 pmcer; /* PMC Event Register */ -#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ -#define PMCER_RES ~(PMCER_PMCI) - u32 pmcmr; /* PMC Mask Register */ -#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ -#define PMCMR_RES ~(PMCMR_PMCIE) + u32 pmccr; /* PMC Configuration Register */ + u32 pmcer; /* PMC Event Register */ + u32 pmcmr; /* PMC Mask Register */ u8 res0[0xF4]; } pmc83xx_t; -#if defined (CONFIG_MPC8349) /* - * general purpose I/O module + * General purpose I/O module */ typedef struct gpio83xx { u32 dir; /* direction register */ @@ -751,124 +218,20 @@ typedef struct gpio83xx { u32 icr; /* external interrupt control register */ u8 res0[0xE8]; } gpio83xx_t; -#endif -#if defined (CONFIG_MPC8360) /* * QE Ports Interrupts Registers */ typedef struct qepi83xx { u8 res0[0xC]; u32 qepier; /* QE Ports Interrupt Event Register */ -#define QEPIER_PA15 0x80000000 -#define QEPIER_PA16 0x40000000 -#define QEPIER_PA29 0x20000000 -#define QEPIER_PA30 0x10000000 -#define QEPIER_PB3 0x08000000 -#define QEPIER_PB5 0x04000000 -#define QEPIER_PB12 0x02000000 -#define QEPIER_PB13 0x01000000 -#define QEPIER_PB26 0x00800000 -#define QEPIER_PB27 0x00400000 -#define QEPIER_PC27 0x00200000 -#define QEPIER_PC28 0x00100000 -#define QEPIER_PC29 0x00080000 -#define QEPIER_PD12 0x00040000 -#define QEPIER_PD13 0x00020000 -#define QEPIER_PD16 0x00010000 -#define QEPIER_PD17 0x00008000 -#define QEPIER_PD26 0x00004000 -#define QEPIER_PD27 0x00002000 -#define QEPIER_PE12 0x00001000 -#define QEPIER_PE13 0x00000800 -#define QEPIER_PE24 0x00000400 -#define QEPIER_PE25 0x00000200 -#define QEPIER_PE26 0x00000100 -#define QEPIER_PE27 0x00000080 -#define QEPIER_PE31 0x00000040 -#define QEPIER_PF20 0x00000020 -#define QEPIER_PG31 0x00000010 -#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \ - |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \ - |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \ - |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \ - |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \ - |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31) u32 qepimr; /* QE Ports Interrupt Mask Register */ -#define QEPIMR_PA15 0x80000000 -#define QEPIMR_PA16 0x40000000 -#define QEPIMR_PA29 0x20000000 -#define QEPIMR_PA30 0x10000000 -#define QEPIMR_PB3 0x08000000 -#define QEPIMR_PB5 0x04000000 -#define QEPIMR_PB12 0x02000000 -#define QEPIMR_PB13 0x01000000 -#define QEPIMR_PB26 0x00800000 -#define QEPIMR_PB27 0x00400000 -#define QEPIMR_PC27 0x00200000 -#define QEPIMR_PC28 0x00100000 -#define QEPIMR_PC29 0x00080000 -#define QEPIMR_PD12 0x00040000 -#define QEPIMR_PD13 0x00020000 -#define QEPIMR_PD16 0x00010000 -#define QEPIMR_PD17 0x00008000 -#define QEPIMR_PD26 0x00004000 -#define QEPIMR_PD27 0x00002000 -#define QEPIMR_PE12 0x00001000 -#define QEPIMR_PE13 0x00000800 -#define QEPIMR_PE24 0x00000400 -#define QEPIMR_PE25 0x00000200 -#define QEPIMR_PE26 0x00000100 -#define QEPIMR_PE27 0x00000080 -#define QEPIMR_PE31 0x00000040 -#define QEPIMR_PF20 0x00000020 -#define QEPIMR_PG31 0x00000010 -#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \ - |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \ - |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \ - |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \ - |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \ - |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31) u32 qepicr; /* QE Ports Interrupt Control Register */ -#define QEPICR_PA15 0x80000000 -#define QEPICR_PA16 0x40000000 -#define QEPICR_PA29 0x20000000 -#define QEPICR_PA30 0x10000000 -#define QEPICR_PB3 0x08000000 -#define QEPICR_PB5 0x04000000 -#define QEPICR_PB12 0x02000000 -#define QEPICR_PB13 0x01000000 -#define QEPICR_PB26 0x00800000 -#define QEPICR_PB27 0x00400000 -#define QEPICR_PC27 0x00200000 -#define QEPICR_PC28 0x00100000 -#define QEPICR_PC29 0x00080000 -#define QEPICR_PD12 0x00040000 -#define QEPICR_PD13 0x00020000 -#define QEPICR_PD16 0x00010000 -#define QEPICR_PD17 0x00008000 -#define QEPICR_PD26 0x00004000 -#define QEPICR_PD27 0x00002000 -#define QEPICR_PE12 0x00001000 -#define QEPICR_PE13 0x00000800 -#define QEPICR_PE24 0x00000400 -#define QEPICR_PE25 0x00000200 -#define QEPICR_PE26 0x00000100 -#define QEPICR_PE27 0x00000080 -#define QEPICR_PE31 0x00000040 -#define QEPICR_PF20 0x00000020 -#define QEPICR_PG31 0x00000010 -#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \ - |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \ - |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \ - |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \ - |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \ - |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31) u8 res1[0xE8]; } qepi83xx_t; /* - * general purpose I/O module + * QE Parallel I/O Ports */ typedef struct gpio_n { u32 podr; /* Open Drain Register */ @@ -879,238 +242,83 @@ typedef struct gpio_n { u32 ppar2; /* Pin Assignment Register 2 */ } gpio_n_t; -typedef struct gpio83xx { +typedef struct qegpio83xx { gpio_n_t ioport[0x7]; u8 res0[0x358]; -} gpio83xx_t; +} qepio83xx_t; /* * QE Secondary Bus Access Windows */ - typedef struct qesba83xx { u32 lbmcsar; /* Local bus memory controller start address */ -#define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ -#define LBMCSAR_RES ~(LBMCSAR_SA) u32 sdmcsar; /* Secondary DDR memory controller start address */ -#define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ -#define SDMCSAR_RES ~(SDMCSAR_SA) u8 res0[0x38]; u32 lbmcear; /* Local bus memory controller end address */ -#define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ -#define LBMCEAR_RES ~(LBMCEAR_EA) u32 sdmcear; /* Secondary DDR memory controller end address */ -#define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ -#define SDMCEAR_RES ~(SDMCEAR_EA) u8 res1[0x38]; - u32 lbmcar; /* Local bus memory controller attributes */ -#define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */ -#define LBMCAR_RES ~(LBMCAR_WEN) + u32 lbmcar; /* Local bus memory controller attributes */ u32 sdmcar; /* Secondary DDR memory controller attributes */ -#define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */ -#define SDMCAR_RES ~(SDMCAR_WEN) - u8 res2[0x778]; + u8 res2[0x378]; } qesba83xx_t; -#endif /* * DDR Memory Controller Memory Map */ typedef struct ddr_cs_bnds { u32 csbnds; -#define CSBNDS_SA 0x00FF0000 -#define CSBNDS_SA_SHIFT 8 -#define CSBNDS_EA 0x000000FF -#define CSBNDS_EA_SHIFT 24 u8 res0[4]; } ddr_cs_bnds_t; typedef struct ddr83xx { - ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ + ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ u8 res0[0x60]; - u32 cs_config[4]; /**< Chip Select x Configuration */ -#define CSCONFIG_EN 0x80000000 -#define CSCONFIG_AP 0x00800000 -#define CSCONFIG_ROW_BIT 0x00000700 -#define CSCONFIG_ROW_BIT_12 0x00000000 -#define CSCONFIG_ROW_BIT_13 0x00000100 -#define CSCONFIG_ROW_BIT_14 0x00000200 -#define CSCONFIG_COL_BIT 0x00000007 -#define CSCONFIG_COL_BIT_8 0x00000000 -#define CSCONFIG_COL_BIT_9 0x00000001 -#define CSCONFIG_COL_BIT_10 0x00000002 -#define CSCONFIG_COL_BIT_11 0x00000003 + u32 cs_config[4]; /* Chip Select x Configuration */ u8 res1[0x78]; - u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ -#define TIMING_CFG1_PRETOACT 0x70000000 -#define TIMING_CFG1_PRETOACT_SHIFT 28 -#define TIMING_CFG1_ACTTOPRE 0x0F000000 -#define TIMING_CFG1_ACTTOPRE_SHIFT 24 -#define TIMING_CFG1_ACTTORW 0x00700000 -#define TIMING_CFG1_ACTTORW_SHIFT 20 -#define TIMING_CFG1_CASLAT 0x00070000 -#define TIMING_CFG1_CASLAT_SHIFT 16 -#define TIMING_CFG1_REFREC 0x0000F000 -#define TIMING_CFG1_REFREC_SHIFT 12 -#define TIMING_CFG1_WRREC 0x00000700 -#define TIMING_CFG1_WRREC_SHIFT 8 -#define TIMING_CFG1_ACTTOACT 0x00000070 -#define TIMING_CFG1_ACTTOACT_SHIFT 4 -#define TIMING_CFG1_WRTORD 0x00000007 -#define TIMING_CFG1_WRTORD_SHIFT 0 -#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ -#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ - - u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ -#define TIMING_CFG2_CPO 0x0F000000 -#define TIMING_CFG2_CPO_SHIFT 24 -#define TIMING_CFG2_ACSM 0x00080000 -#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 -#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 -#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ - - u32 sdram_cfg; /**< SDRAM Control Configuration */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 - + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ u8 res2[4]; - u32 sdram_mode; /**< SDRAM Mode Configuration */ -#define SDRAM_MODE_ESD 0xFFFF0000 -#define SDRAM_MODE_ESD_SHIFT 16 -#define SDRAM_MODE_SD 0x0000FFFF -#define SDRAM_MODE_SD_SHIFT 0 -#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ -#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ -#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ -#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ -#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ -#define DDR_MODE_WEAK 0x0002 /* weak drivers */ -#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ -#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ -#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ -#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ -#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ -#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ -#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ -#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ -#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ -#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ -#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ -#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ -#define DDR_MODE_MODEREG 0x0000 /* select mode register */ - + u32 sdram_mode; /* SDRAM Mode Configuration */ u8 res3[8]; - u32 sdram_interval; /**< SDRAM Interval Configuration */ -#define SDRAM_INTERVAL_REFINT 0x3FFF0000 -#define SDRAM_INTERVAL_REFINT_SHIFT 16 -#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF -#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + u32 sdram_interval; /* SDRAM Interval Configuration */ u8 res9[8]; u32 sdram_clk_cntl; -#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 - u8 res4[0xCCC]; - u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ - u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ - u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ -#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ -#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ -#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ -#define ECC_ERR_INJECT_EEIM_SHIFT 0 + u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ + u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ u8 res5[0x14]; - u32 capture_data_hi; /**< Memory Data Path Read Capture High */ - u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ - u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ -#define CAPTURE_ECC_ECE (0xff000000>>24) -#define CAPTURE_ECC_ECE_SHIFT 0 + u32 capture_data_hi; /* Memory Data Path Read Capture High */ + u32 capture_data_lo; /* Memory Data Path Read Capture Low */ + u32 capture_ecc; /* Memory Data Path Read Capture ECC */ u8 res6[0x14]; - u32 err_detect; /**< Memory Error Detect */ -#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ -#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ -#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ -#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ - u32 err_disable; /**< Memory Error Disable */ -#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ -#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ -#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ -#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) - u32 err_int_en; /**< Memory Error Interrupt Enable */ -#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ -#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ -#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ -#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) - u32 capture_attributes; /**< Memory Error Attributes Capture */ -#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ -#define ECC_CAPT_ATTR_BNUM_SHIFT 28 -#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ -#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 -#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 -#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 -#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 -#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 -#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ -#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 -#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 -#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 -#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 -#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) -#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 -#define ECC_CAPT_ATTR_TSRC_I2C 0x9 -#define ECC_CAPT_ATTR_TSRC_JTAG 0xA -#define ECC_CAPT_ATTR_TSRC_PCI1 0xD -#define ECC_CAPT_ATTR_TSRC_PCI2 0xE -#define ECC_CAPT_ATTR_TSRC_DMA 0xF -#define ECC_CAPT_ATTR_TSRC_SHIFT 16 -#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ -#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 -#define ECC_CAPT_ATTR_TTYP_READ 0x2 -#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 -#define ECC_CAPT_ATTR_TTYP_SHIFT 12 -#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ - u32 capture_address; /**< Memory Error Address Capture */ - u32 capture_ext_address;/**< Memory Error Extended Address Capture */ - u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ -#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ -#define ECC_ERROR_MAN_SBET_SHIFT 16 -#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ -#define ECC_ERROR_MAN_SBEC_SHIFT 0 + u32 err_detect; /* Memory Error Detect */ + u32 err_disable; /* Memory Error Disable */ + u32 err_int_en; /* Memory Error Interrupt Enable */ + u32 capture_attributes; /* Memory Error Attributes Capture */ + u32 capture_address; /* Memory Error Address Capture */ + u32 capture_ext_address;/* Memory Error Extended Address Capture */ + u32 err_sbe; /* Memory Single-Bit ECC Error Management */ u8 res7[0xA4]; u32 debug_reg; u8 res8[0xFC]; } ddr83xx_t; -/* - * I2C1 Controller - */ - /* * DUART */ typedef struct duart83xx { - u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ - u8 uier_udmb; /**< combined register for UIER and UDMB */ - u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ - u8 ulcr; /**< line control register */ - u8 umcr; /**< MODEM control register */ - u8 ulsr; /**< line status register */ - u8 umsr; /**< MODEM status register */ - u8 uscr; /**< scratch register */ + u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ + u8 uier_udmb; /* combined register for UIER and UDMB */ + u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ + u8 ulcr; /* line control register */ + u8 umcr; /* MODEM control register */ + u8 ulsr; /* line status register */ + u8 umsr; /* MODEM status register */ + u8 uscr; /* scratch register */ u8 res0[8]; - u8 udsr; /**< DMA status register */ + u8 udsr; /* DMA status register */ u8 res1[3]; u8 res2[0xEC]; } duart83xx_t; @@ -1119,75 +327,52 @@ typedef struct duart83xx { * Local Bus Controller Registers */ typedef struct lbus_bank { - u32 br; /**< Base Register */ - u32 or; /**< Base Register */ + u32 br; /* Base Register */ + u32 or; /* Option Register */ } lbus_bank_t; typedef struct lbus83xx { lbus_bank_t bank[8]; u8 res0[0x28]; - u32 mar; /**< UPM Address Register */ + u32 mar; /* UPM Address Register */ u8 res1[0x4]; - u32 mamr; /**< UPMA Mode Register */ - u32 mbmr; /**< UPMB Mode Register */ - u32 mcmr; /**< UPMC Mode Register */ + u32 mamr; /* UPMA Mode Register */ + u32 mbmr; /* UPMB Mode Register */ + u32 mcmr; /* UPMC Mode Register */ u8 res2[0x8]; - u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ - u32 mdr; /**< UPM Data Register */ + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ + u32 mdr; /* UPM Data Register */ u8 res3[0x8]; - u32 lsdmr; /**< SDRAM Mode Register */ + u32 lsdmr; /* SDRAM Mode Register */ u8 res4[0x8]; - u32 lurt; /**< UPM Refresh Timer */ - u32 lsrt; /**< SDRAM Refresh Timer */ + u32 lurt; /* UPM Refresh Timer */ + u32 lsrt; /* SDRAM Refresh Timer */ u8 res5[0x8]; - u32 ltesr; /**< Transfer Error Status Register */ - u32 ltedr; /**< Transfer Error Disable Register */ - u32 lteir; /**< Transfer Error Interrupt Register */ - u32 lteatr; /**< Transfer Error Attributes Register */ - u32 ltear; /**< Transfer Error Address Register */ + u32 ltesr; /* Transfer Error Status Register */ + u32 ltedr; /* Transfer Error Disable Register */ + u32 lteir; /* Transfer Error Interrupt Register */ + u32 lteatr; /* Transfer Error Attributes Register */ + u32 ltear; /* Transfer Error Address Register */ u8 res6[0xC]; - u32 lbcr; /**< Configuration Register */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - u32 lcrr; /**< Clock Ratio Register */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_SHIFT 0 - + u32 lbcr; /* Configuration Register */ + u32 lcrr; /* Clock Ratio Register */ u8 res7[0x28]; u8 res8[0xF00]; } lbus83xx_t; -#if defined (CONFIG_MPC8349) /* * Serial Peripheral Interface */ typedef struct spi83xx { - u32 mode; /**< mode register */ - u32 event; /**< event register */ - u32 mask; /**< mask register */ - u32 com; /**< command register */ + u32 mode; /* mode register */ + u32 event; /* event register */ + u32 mask; /* mask register */ + u32 com; /* command register */ u8 res0[0x10]; - u32 tx; /**< transmit register */ - u32 rx; /**< receive register */ - u8 res1[0xD8]; + u32 tx; /* transmit register */ + u32 rx; /* receive register */ + u8 res1[0xFD8]; } spi83xx_t; -#endif /* * DMA/Messaging Unit @@ -1197,21 +382,17 @@ typedef struct dma83xx { u32 omisr; /* 0x30 Outbound message interrupt status register */ u32 omimr; /* 0x34 Outbound message interrupt mask register */ u32 res1[0x6]; /* 0x38-0x49 reserved */ - u32 imr0; /* 0x50 Inbound message register 0 */ u32 imr1; /* 0x54 Inbound message register 1 */ u32 omr0; /* 0x58 Outbound message register 0 */ u32 omr1; /* 0x5C Outbound message register 1 */ - u32 odr; /* 0x60 Outbound doorbell register */ u32 res2; /* 0x64-0x67 reserved */ u32 idr; /* 0x68 Inbound doorbell register */ u32 res3[0x5]; /* 0x6C-0x79 reserved */ - u32 imisr; /* 0x80 Inbound message interrupt status register */ u32 imimr; /* 0x84 Inbound message interrupt mask register */ u32 res4[0x1E]; /* 0x88-0x99 reserved */ - u32 dmamr0; /* 0x100 DMA 0 mode register */ u32 dmasr0; /* 0x104 DMA 0 status register */ u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ @@ -1223,7 +404,6 @@ typedef struct dma83xx { u32 dmabcr0; /* 0x120 DMA 0 byte count register */ u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ u32 res8[0x16]; /* 0x128-0x179 reserved */ - u32 dmamr1; /* 0x180 DMA 1 mode register */ u32 dmasr1; /* 0x184 DMA 1 status register */ u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ @@ -1235,7 +415,6 @@ typedef struct dma83xx { u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ u32 res12[0x16]; /* 0x1A8-0x199 reserved */ - u32 dmamr2; /* 0x200 DMA 2 mode register */ u32 dmasr2; /* 0x204 DMA 2 status register */ u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ @@ -1247,7 +426,6 @@ typedef struct dma83xx { u32 dmabcr2; /* 0x220 DMA 2 byte count register */ u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ u32 res16[0x16]; /* 0x228-0x279 reserved */ - u32 dmamr3; /* 0x280 DMA 3 mode register */ u32 dmasr3; /* 0x284 DMA 3 status register */ u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ @@ -1258,39 +436,15 @@ typedef struct dma83xx { u32 res19; /* 0x29C reserved */ u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ - u32 dmagsr; /* 0x2A8 DMA general status register */ u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ } dma83xx_t; -/* DMAMRn bits */ -#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ -#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ -#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ -#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ - -/* DMASRn bits */ -#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ -#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ - /* * PCI Software Configuration Registers */ typedef struct pciconf83xx { u32 config_address; -#define PCI_CONFIG_ADDRESS_EN 0x80000000 -#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 -#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 -#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 -#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 -#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 -#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 -#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 -#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc u32 config_data; u32 int_ack; u8 res[116]; @@ -1313,34 +467,6 @@ typedef struct pci_outbound_window { */ typedef struct ios83xx { pot83xx_t pot[6]; -#define POTAR_TA_MASK 0x000fffff -#define POBAR_BA_MASK 0x000fffff -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ -#define POCMR_SE 0x20000000 /* streaming enable */ -#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF u8 res0[0x60]; u32 pmcr; u8 res1[4]; @@ -1353,74 +479,13 @@ typedef struct ios83xx { */ typedef struct pcictrl83xx { u32 esr; -#define ESR_MERR 0x80000000 -#define ESR_APAR 0x00000400 -#define ESR_PCISERR 0x00000200 -#define ESR_MPERR 0x00000100 -#define ESR_TPERR 0x00000080 -#define ESR_NORSP 0x00000040 -#define ESR_TABT 0x00000020 u32 ecdr; -#define ECDR_APAR 0x00000400 -#define ECDR_PCISERR 0x00000200 -#define ECDR_MPERR 0x00000100 -#define ECDR_TPERR 0x00000080 -#define ECDR_NORSP 0x00000040 -#define ECDR_TABT 0x00000020 u32 eer; -#define EER_APAR 0x00000400 -#define EER_PCISERR 0x00000200 -#define EER_MPERR 0x00000100 -#define EER_TPERR 0x00000080 -#define EER_NORSP 0x00000040 -#define EER_TABT 0x00000020 u32 eatcr; -#define EATCR_ERRTYPR_MASK 0x70000000 -#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ -#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ -#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ -#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ -#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ -#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ -#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ -#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ -#define EATCR_BN_MASK 0x0f000000 /* beat number */ -#define EATCR_BN_1st 0x00000000 -#define EATCR_BN_2ed 0x01000000 -#define EATCR_BN_3rd 0x02000000 -#define EATCR_BN_4th 0x03000000 -#define EATCR_BN_5th 0x0400000 -#define EATCR_BN_6th 0x05000000 -#define EATCR_BN_7th 0x06000000 -#define EATCR_BN_8th 0x07000000 -#define EATCR_BN_9th 0x08000000 -#define EATCR_TS_MASK 0x00300000 /* transaction size */ -#define EATCR_TS_4 0x00000000 -#define EATCR_TS_1 0x00100000 -#define EATCR_TS_2 0x00200000 -#define EATCR_TS_3 0x00300000 -#define EATCR_ES_MASK 0x000f0000 /* error source */ -#define EATCR_ES_EM 0x00000000 /* external master */ -#define EATCR_ES_DMA 0x00050000 -#define EATCR_CMD_MASK 0x0000f000 -#if defined (CONFIG_MPC8349) -#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ -#endif -#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ -#if defined (CONFIG_MPC8349) -#define EATCR_HPB 0x00000004 /* high parity bit */ -#endif -#define EATCR_PB 0x00000002 /* parity bit */ -#define EATCR_VI 0x00000001 /* error information valid */ u32 eacr; u32 eeacr; -#if defined (CONFIG_MPC8349) u32 edlcr; u32 edhcr; -#elif defined (CONFIG_MPC8360) - u32 edcr; /* was edlcr */ - u8 res_edcr[0x4]; -#endif u32 gcr; u32 ecr; u32 gsr; @@ -1443,41 +508,8 @@ typedef struct pcictrl83xx { u8 res6[4]; u32 piwar0; u8 res7[132]; -#define PITAR_TA_MASK 0x000fffff -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 -#define PIWAR_IWS_MASK 0x0000003F -#define PIWAR_IWS_4K 0x0000000B -#define PIWAR_IWS_8K 0x0000000C -#define PIWAR_IWS_16K 0x0000000D -#define PIWAR_IWS_32K 0x0000000E -#define PIWAR_IWS_64K 0x0000000F -#define PIWAR_IWS_128K 0x00000010 -#define PIWAR_IWS_256K 0x00000011 -#define PIWAR_IWS_512K 0x00000012 -#define PIWAR_IWS_1M 0x00000013 -#define PIWAR_IWS_2M 0x00000014 -#define PIWAR_IWS_4M 0x00000015 -#define PIWAR_IWS_8M 0x00000016 -#define PIWAR_IWS_16M 0x00000017 -#define PIWAR_IWS_32M 0x00000018 -#define PIWAR_IWS_64M 0x00000019 -#define PIWAR_IWS_128M 0x0000001A -#define PIWAR_IWS_256M 0x0000001B -#define PIWAR_IWS_512M 0x0000001C -#define PIWAR_IWS_1G 0x0000001D -#define PIWAR_IWS_2G 0x0000001E } pcictrl83xx_t; -#if defined (CONFIG_MPC8349) /* * USB */ @@ -1491,7 +523,6 @@ typedef struct usb83xx { typedef struct tsec83xx { u8 fixme[0x1000]; } tsec83xx_t; -#endif /* * Security @@ -1500,581 +531,82 @@ typedef struct security83xx { u8 fixme[0x10000]; } security83xx_t; -#if defined (CONFIG_MPC8360) -/* - * iram - */ -typedef struct iram83xx { - u32 iadd; /* I-RAM address register */ - u32 idata; /* I-RAM data register */ - u8 res0[0x78]; -} iram83xx_t; - -/* - * Interrupt Controller - */ -typedef struct irq83xx { - u32 cicr; /* QE system interrupt configuration */ - u32 civec; /* QE system interrupt vector register */ - u32 cripnr; /* QE RISC interrupt pending register */ - u32 cipnr; /* QE system interrupt pending register */ - u32 cipxcc; /* QE interrupt priority register */ - u32 cipycc; /* QE interrupt priority register */ - u32 cipwcc; /* QE interrupt priority register */ - u32 cipzcc; /* QE interrupt priority register */ - u32 cimr; /* QE system interrupt mask register */ - u32 crimr; /* QE RISC interrupt mask register */ - u32 cicnr; /* QE system interrupt control register */ - u8 res0[0x4]; - u32 ciprta; /* QE system interrupt priority register for RISC tasks A */ - u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */ - u8 res1[0x4]; - u32 cricr; /* QE system RISC interrupt control */ - u8 res2[0x20]; - u32 chivec; /* QE high system interrupt vector */ - u8 res3[0x1C]; -} irq83xx_t; - -/* - * Communications Processor - */ -typedef struct cp83xx { - u32 cecr; /* QE command register */ - u32 ceccr; /* QE controller configuration register */ - u32 cecdr; /* QE command data register */ - u8 res0[0xA]; - u16 ceter; /* QE timer event register */ - u8 res1[0x2]; - u16 cetmr; /* QE timers mask register */ - u32 cetscr; /* QE time-stamp timer control register */ - u32 cetsr1; /* QE time-stamp register 1 */ - u32 cetsr2; /* QE time-stamp register 2 */ - u8 res2[0x8]; - u32 cevter; /* QE virtual tasks event register */ - u32 cevtmr; /* QE virtual tasks mask register */ - u16 cercr; /* QE RAM control register */ - u8 res3[0x2]; - u8 res4[0x24]; - u16 ceexe1; /* QE external request 1 event register */ - u8 res5[0x2]; - u16 ceexm1; /* QE external request 1 mask register */ - u8 res6[0x2]; - u16 ceexe2; /* QE external request 2 event register */ - u8 res7[0x2]; - u16 ceexm2; /* QE external request 2 mask register */ - u8 res8[0x2]; - u16 ceexe3; /* QE external request 3 event register */ - u8 res9[0x2]; - u16 ceexm3; /* QE external request 3 mask register */ - u8 res10[0x2]; - u16 ceexe4; /* QE external request 4 event register */ - u8 res11[0x2]; - u16 ceexm4; /* QE external request 4 mask register */ - u8 res12[0x2]; - u8 res13[0x280]; -} cp83xx_t; - -/* - * QE Multiplexer - */ - -typedef struct qmx83xx { - u32 cmxgcr; /* CMX general clock route register */ - u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ - u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ - u32 cmxsi1syr; /* CMX SI1 SYNC route register */ - u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ - u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ - u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ - u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ - u32 cmxupcr; /* CMX UPC clock route register */ - u8 res0[0x1C]; -} qmx83xx_t; - -/* -* QE Timers -*/ - -typedef struct qet83xx { - u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */ - u8 res0[0x3]; - u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */ - u8 res1[0xB]; - u16 gtmdr1; /* Timer 1 mode register */ - u16 gtmdr2; /* Timer 2 mode register */ - u16 gtrfr1; /* Timer 1 reference register */ - u16 gtrfr2; /* Timer 2 reference register */ - u16 gtcpr1; /* Timer 1 capture register */ - u16 gtcpr2; /* Timer 2 capture register */ - u16 gtcnr1; /* Timer 1 counter */ - u16 gtcnr2; /* Timer 2 counter */ - u16 gtmdr3; /* Timer 3 mode register */ - u16 gtmdr4; /* Timer 4 mode register */ - u16 gtrfr3; /* Timer 3 reference register */ - u16 gtrfr4; /* Timer 4 reference register */ - u16 gtcpr3; /* Timer 3 capture register */ - u16 gtcpr4; /* Timer 4 capture register */ - u16 gtcnr3; /* Timer 3 counter */ - u16 gtcnr4; /* Timer 4 counter */ - u16 gtevr1; /* Timer 1 event register */ - u16 gtevr2; /* Timer 2 event register */ - u16 gtevr3; /* Timer 3 event register */ - u16 gtevr4; /* Timer 4 event register */ - u16 gtps; /* Timer 1 prescale register */ - u8 res2[0x46]; -} qet83xx_t; - -/* -* spi -*/ - -typedef struct spi83xx { - u8 res0[0x20]; - u32 spmode; /* SPI mode register */ - u8 res1[0x2]; - u8 spie; /* SPI event register */ - u8 res2[0x1]; - u8 res3[0x2]; - u8 spim; /* SPI mask register */ - u8 res4[0x1]; - u8 res5[0x1]; - u8 spcom; /* SPI command register */ - u8 res6[0x2]; - u32 spitd; /* SPI transmit data register (cpu mode) */ - u32 spird; /* SPI receive data register (cpu mode) */ - u8 res7[0x8]; -} spi83xx_t; - -/* -* mcc -*/ - -typedef struct mcc83xx { - u32 mcce; /* MCC event register */ - u32 mccm; /* MCC mask register */ - u32 mccf; /* MCC configuration register */ - u32 merl; /* MCC emergency request level register */ - u8 res0[0xF0]; -} mcc83xx_t; - -/* -* brg -*/ - -typedef struct brg83xx { - u32 brgc1; /* BRG1 configuration register */ - u32 brgc2; /* BRG2 configuration register */ - u32 brgc3; /* BRG3 configuration register */ - u32 brgc4; /* BRG4 configuration register */ - u32 brgc5; /* BRG5 configuration register */ - u32 brgc6; /* BRG6 configuration register */ - u32 brgc7; /* BRG7 configuration register */ - u32 brgc8; /* BRG8 configuration register */ - u32 brgc9; /* BRG9 configuration register */ - u32 brgc10; /* BRG10 configuration register */ - u32 brgc11; /* BRG11 configuration register */ - u32 brgc12; /* BRG12 configuration register */ - u32 brgc13; /* BRG13 configuration register */ - u32 brgc14; /* BRG14 configuration register */ - u32 brgc15; /* BRG15 configuration register */ - u32 brgc16; /* BRG16 configuration register */ - u8 res0[0x40]; -} brg83xx_t; - -/* -* USB -*/ - -typedef struct usb83xx { - u8 usmod; /* USB mode register */ - u8 usadd; /* USB address register */ - u8 uscom; /* USB command register */ - u8 res0[0x1]; - u16 usep0; /* USB endpoint register 0 */ - u16 usep1; /* USB endpoint register 1 */ - u16 usep2; /* USB endpoint register 2 */ - u16 usep3; /* USB endpoint register 3 */ - u8 res1[0x4]; - u16 usber; /* USB event register */ - u8 res2[0x2]; - u16 usbmr; /* USB mask register */ - u8 res3[0x1]; - u8 usbs; /* USB status register */ - u32 ussft; /* USB start of frame timer */ - u8 res4[0x24]; -} usb83xx_t; - -/* -* SI -*/ - -typedef struct si1_83xx { - u16 siamr1; /* SI1 TDMA mode register */ - u16 sibmr1; /* SI1 TDMB mode register */ - u16 sicmr1; /* SI1 TDMC mode register */ - u16 sidmr1; /* SI1 TDMD mode register */ - u8 siglmr1_h; /* SI1 global mode register high */ - u8 res0[0x1]; - u8 sicmdr1_h; /* SI1 command register high */ - u8 res2[0x1]; - u8 sistr1_h; /* SI1 status register high */ - u8 res3[0x1]; - u16 sirsr1_h; /* SI1 RAM shadow address register high */ - u8 sitarc1; /* SI1 RAM counter Tx TDMA */ - u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ - u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ - u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ - u8 sirarc1; /* SI1 RAM counter Rx TDMA */ - u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ - u8 sircrc1; /* SI1 RAM counter Rx TDMC */ - u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ - u8 res4[0x8]; - u16 siemr1; /* SI1 TDME mode register 16 bits */ - u16 sifmr1; /* SI1 TDMF mode register 16 bits */ - u16 sigmr1; /* SI1 TDMG mode register 16 bits */ - u16 sihmr1; /* SI1 TDMH mode register 16 bits */ - u8 siglmg1_l; /* SI1 global mode register low 8 bits */ - u8 res5[0x1]; - u8 sicmdr1_l; /* SI1 command register low 8 bits */ - u8 res6[0x1]; - u8 sistr1_l; /* SI1 status register low 8 bits */ - u8 res7[0x1]; - u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ - u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ - u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ - u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ - u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ - u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ - u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ - u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ - u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ - u8 res8[0x8]; - u32 siml1; /* SI1 multiframe limit register */ - u8 siedm1; /* SI1 extended diagnostic mode register */ - u8 res9[0xBB]; -} si1_83xx_t; - -/* -* SI Routing Tables -*/ - -typedef struct sir83xx { - u8 tx[0x400]; - u8 rx[0x400]; - u8 res0[0x800]; -} sir83xx_t; - -/* -* ucc -*/ - -typedef struct uslow { - u32 gumr_l; /* UCCx general mode register (low) */ - u32 gumr_h; /* UCCx general mode register (high) */ - u16 upsmr; /* UCCx protocol-specific mode register */ - u8 res0[0x2]; - u16 utodr; /* UCCx transmit on demand register */ - u16 udsr; /* UCCx data synchronization register */ - u16 ucce; /* UCCx event register */ - u8 res1[0x2]; - u16 uccm; /* UCCx mask register */ - u8 res2[0x1]; - u8 uccs; /* UCCx status register */ - u8 res3[0x1E8]; -} uslow_t; - -typedef struct ufast { - u32 gumr; /* UCCx general mode register */ - u32 upsmr; /* UCCx protocol-specific mode register */ - u16 utodr; /* UCCx transmit on demand register */ - u8 res0[0x2]; - u16 udsr; /* UCCx data synchronization register */ - u8 res1[0x2]; - u32 ucce; /* UCCx event register */ - u32 uccm; /* UCCx mask register. */ - u8 uccs; /* UCCx status register */ - u8 res2[0x7]; - u32 urfb; /* UCC receive FIFO base */ - u16 urfs; /* UCC receive FIFO size */ - u8 res3[0x2]; - u16 urfet; /* UCC receive FIFO emergency threshold */ - u16 urfset; /* UCC receive FIFO special emergency threshold */ - u32 utfb; /* UCC transmit FIFO base */ - u16 utfs; /* UCC transmit FIFO size */ - u8 res4[0x2]; - u16 utfet; /* UCC transmit FIFO emergency threshold */ - u8 res5[0x2]; - u16 utftt; /* UCC transmit FIFO transmit threshold */ - u8 res6[0x2]; - u16 utpt; /* UCC transmit polling timer */ - u32 urtry; /* UCC retry counter register */ - u8 res7[0x4C]; - u8 guemr; /* UCC general extended mode register */ - u8 res8[0x3]; - u8 res9[0x6C]; - u32 maccfg1; /* Mac configuration register #1 */ - u32 maccfg2; /* Mac configuration register #2 */ - u16 ipgifg; /* Interframe gap register */ - u8 res10[0x2]; - u32 hafdup; /* Half-duplex register */ - u8 res11[0xC]; - u32 emtr; /* Ethernet MAC test register */ - u32 miimcfg; /* MII mgmt configuration register */ - u32 miimcom; /* MII mgmt command register */ - u32 miimadd; /* MII mgmt address register */ - u32 miimcon; /* MII mgmt control register */ - u32 miistat; /* MII mgmt status register */ - u32 miimnd; /* MII mgmt indication register */ - u32 ifctl; /* Interface control register */ - u32 ifstat; /* Interface status register */ - u32 macstnaddr1; /* Station address part 1 register */ - u32 macstnaddr2; /* Station address part 2 register */ - u8 res12[0x8]; - u32 uempr; /* UCC Ethernet MAC parameter register */ - u32 utbipa; /* UCC TBI address */ - u16 uescr; /* UCC Ethernet statistics control register */ - u8 res13[0x26]; - u32 tx64; /* Transmit and receive 64-byte frame counter */ - u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */ - u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */ - u32 rx64; /* Receive and receive 64-byte frame counter */ - u32 rx127; /* Receive and receive 65- to 127-byte frame counter */ - u32 rx255; /* Receive and receive 128- to 255-byte frame counter */ - u32 txok; /* Transmit good bytes counter */ - u32 txcf; /* Transmit control frame counter */ - u32 tmca; /* Transmit multicast control frame counter */ - u32 tbca; /* Transmit broadcast packet counter */ - u32 rxfok; /* Receive frame OK counter */ - u32 rbyt; /* Receive good and bad bytes counter */ - u32 rxbok; /* Receive bytes OK counter */ - u32 rmca; /* Receive multicast packet counter */ - u32 rbca; /* Receive broadcast packet counter */ - u32 scar; /* Statistics carry register */ - u32 scam; /* Statistics carry mask register */ - u8 res14[0x3C]; -} ufast_t; - -typedef struct ucc83xx { - union { - uslow_t slow; - ufast_t fast; - }; -} ucc83xx_t; - -/* -* MultiPHY UTOPIA POS Controllers -*/ - -typedef struct upc83xx { - u32 upgcr; /* UTOPIA/POS general configuration register */ -#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ -#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ -#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ -#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */ -#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ - u32 uplpa; /* UTOPIA/POS last PHY address */ - u32 uphec; /* ATM HEC register */ - u32 upuc; /* UTOPIA/POS UCC configuration */ - u32 updc1; /* UTOPIA/POS device 1 configuration */ - u32 updc2; /* UTOPIA/POS device 2 configuration */ - u32 updc3; /* UTOPIA/POS device 3 configuration */ - u32 updc4; /* UTOPIA/POS device 4 configuration */ - u32 upstpa; /* UTOPIA/POS STPA threshold */ - u8 res0[0xC]; - u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ - u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ - u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ - u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ - u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ - u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ - u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ - u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ - u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ - u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ - u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ - u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ - u32 upde1; /* UTOPIA/POS device 1 event */ - u32 upde2; /* UTOPIA/POS device 2 event */ - u32 upde3; /* UTOPIA/POS device 3 event */ - u32 upde4; /* UTOPIA/POS device 4 event */ - u16 uprp1; - u16 uprp2; - u16 uprp3; - u16 uprp4; - u8 res1[0x8]; - u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ - u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ - u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ - u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ - u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ - u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ - u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ - u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ - u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ - u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ - u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ - u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ - u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ - u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ - u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ - u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ - u32 uper1; /* Device 1 port enable register */ - u32 uper2; /* Device 2 port enable register */ - u32 uper3; /* Device 3 port enable register */ - u32 uper4; /* Device 4 port enable register */ - u8 res2[0x150]; -} upc83xx_t; - -/* -* SDMA -*/ - -typedef struct sdma83xx { - u32 sdsr; /* Serial DMA status register */ - u32 sdmr; /* Serial DMA mode register */ - u32 sdtr1; /* SDMA system bus threshold register */ - u32 sdtr2; /* SDMA secondary bus threshold register */ - u32 sdhy1; /* SDMA system bus hysteresis register */ - u32 sdhy2; /* SDMA secondary bus hysteresis register */ - u32 sdta1; /* SDMA system bus address register */ - u32 sdta2; /* SDMA secondary bus address register */ - u32 sdtm1; /* SDMA system bus MSNUM register */ - u32 sdtm2; /* SDMA secondary bus MSNUM register */ - u8 res0[0x10]; - u32 sdaqr; /* SDMA address bus qualify register */ - u32 sdaqmr; /* SDMA address bus qualify mask register */ - u8 res1[0x4]; - u32 sdwbcr; /* SDMA CAM entries base register */ - u8 res2[0x38]; -} sdma83xx_t; - -/* -* Debug Space -*/ - -typedef struct dbg83xx { - u32 bpdcr; /* Breakpoint debug command register */ - u32 bpdsr; /* Breakpoint debug status register */ - u32 bpdmr; /* Breakpoint debug mask register */ - u32 bprmrr0; /* Breakpoint request mode risc register 0 */ - u32 bprmrr1; /* Breakpoint request mode risc register 1 */ - u8 res0[0x8]; - u32 bprmtr0; /* Breakpoint request mode trb register 0 */ - u32 bprmtr1; /* Breakpoint request mode trb register 1 */ - u8 res1[0x8]; - u32 bprmir; /* Breakpoint request mode immediate register */ - u32 bprmsr; /* Breakpoint request mode serial register */ - u32 bpemr; /* Breakpoint exit mode register */ - u8 res2[0x48]; -} dbg83xx_t; - -/* -* RISC Special Registers (Trap and Breakpoint) -*/ - -typedef struct rsp83xx { - u8 fixme[0x100]; -} rsp83xx_t; -#endif +#if defined(CONFIG_MPC8349) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x200]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res1[0xE00]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res4[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ + u8 res5[0x19900]; + usb83xx_t usb; + tsec83xx_t tsec[2]; + u8 res6[0xA000]; + security83xx_t security; + u8 res7[0xC0000]; +} immap_t; +#elif defined(CONFIG_MPC8360) typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ -#if defined (CONFIG_MPC8349) - gpio83xx_t pgio[2]; /* general purpose I/O module */ -#elif defined (CONFIG_MPC8360) - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ -#endif - u8 res0[0x200]; -#if defined (CONFIG_MPC8360) - u8 DLL_LBDDR[0x100]; -#endif - u8 DDL_DDR[0x100]; - u8 DDL_LBIU[0x100]; -#if defined (CONFIG_MPC8349) - u8 res1[0xE00]; -#elif defined (CONFIG_MPC8360) - u8 res1[0x200]; - gpio83xx_t gpio; /* General purpose I/O module */ - qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ -#endif - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res2[0x1300]; - duart83xx_t duart[2]; /* DUART */ -#if defined (CONFIG_MPC8349) - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res4[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ - u8 res5[0xF00]; -#elif defined (CONFIG_MPC8360) - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller */ - u8 res4[0x2000]; -#endif - dma83xx_t dma; /* DMA */ -#if defined (CONFIG_MPC8349) - pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ - u8 res6[0x19900]; - usb83xx_t usb; - tsec83xx_t tsec[2]; - u8 res7[0xA000]; - security83xx_t security; -#elif defined (CONFIG_MPC8360) - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res_5[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res6[0x4A00]; - ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ - u8 res7[0x22000]; - security83xx_t security; - u8 res8[0xC0000]; - iram83xx_t iram; /* IRAM */ - irq83xx_t irq; /* Interrupt Controller */ - cp83xx_t cp; /* Communications Processor */ - qmx83xx_t qmx; /* QE Multiplexer */ - qet83xx_t qet; /* QE Timers */ - spi83xx_t spi[0x2]; /* spi */ - mcc83xx_t mcc; /* mcc */ - brg83xx_t brg; /* brg */ - usb83xx_t usb; /* USB */ - si1_83xx_t si1; /* SI */ - u8 res9[0x800]; - sir83xx_t sir; /* SI Routing Tables */ - ucc83xx_t ucc1; /* ucc1 */ - ucc83xx_t ucc3; /* ucc3 */ - ucc83xx_t ucc5; /* ucc5 */ - ucc83xx_t ucc7; /* ucc7 */ - u8 res10[0x600]; - upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ - ucc83xx_t ucc2; /* ucc2 */ - ucc83xx_t ucc4; /* ucc4 */ - ucc83xx_t ucc6; /* ucc6 */ - ucc83xx_t ucc8; /* ucc8 */ - u8 res11[0x600]; - upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ - sdma83xx_t sdma; /* SDMA */ - dbg83xx_t dbg; /* Debug Space */ - rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */ - u8 res12[0x300]; - u8 res13[0x3A00]; - u8 res14[0x8000]; /* 0x108000 - 0x110000 */ - u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res16[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res17[0xC0000]; /* 0x140000 - 0x200000 */ -#endif + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + u8 res0[0x200]; + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + u8 res1[0x300]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res2[0x200]; + qepio83xx_t qepio; /* QE Parallel I/O ports */ + qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ + u8 res3[0x400]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res4[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res5[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res6[0x2000]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res7[128]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res8[0x4A00]; + ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ + u8 res9[0x22000]; + security83xx_t security; + u8 res10[0xC0000]; + u8 qe[0x100000]; /* QE block */ } immap_t; +#endif #endif /* __IMMAP_83xx__ */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0cafd2d..504b6a97bc7 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -10,12 +10,6 @@ * the License, or (at your option) any later version. */ -/* - * mpc83xx.h - * - * MPC83xx specific definitions - */ - #ifndef __MPC83XX_H__ #define __MPC83XX_H__ @@ -24,406 +18,941 @@ #include #endif -/* - * MPC83xx cpu provide RCR register to do reset thing specially. easier - * to implement +/* MPC83xx cpu provide RCR register to do reset thing specially */ - #define MPC83xx_RESET -/* - * System reset offset (PowerPC standard) +/* System reset offset (PowerPC standard) */ -#define EXC_OFF_SYS_RESET 0x0100 +#define EXC_OFF_SYS_RESET 0x0100 -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* IMMRBAR - Internal Memory Register Base Address */ -#define CONFIG_DEFAULT_IMMR 0xFF400000 +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) -/* - * Watchdog +/* LAWBAR - Local Access Window Base Address Register */ -#define SWCRR 0x0204 -#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ -#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ -#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ -#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ -#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) +#define LBLAWBAR0 0x0020 /* Register offset to immr */ +#define LBLAWAR0 0x0024 +#define LBLAWBAR1 0x0028 +#define LBLAWAR1 0x002C +#define LBLAWBAR2 0x0030 +#define LBLAWAR2 0x0034 +#define LBLAWBAR3 0x0038 +#define LBLAWAR3 0x003C +#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ + +/* SPRIDR - System Part and Revision ID Register + */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ + +#define SPR_8349E_REV10 0x80300100 +#define SPR_8349_REV10 0x80310100 +#define SPR_8347E_REV10_TBGA 0x80320100 +#define SPR_8347_REV10_TBGA 0x80330100 +#define SPR_8347E_REV10_PBGA 0x80340100 +#define SPR_8347_REV10_PBGA 0x80350100 +#define SPR_8343E_REV10 0x80360100 +#define SPR_8343_REV10 0x80370100 + +#define SPR_8349E_REV11 0x80300101 +#define SPR_8349_REV11 0x80310101 +#define SPR_8347E_REV11_TBGA 0x80320101 +#define SPR_8347_REV11_TBGA 0x80330101 +#define SPR_8347E_REV11_PBGA 0x80340101 +#define SPR_8347_REV11_PBGA 0x80350101 +#define SPR_8343E_REV11 0x80360101 +#define SPR_8343_REV11 0x80370101 + +#define SPR_8360E_REV10 0x80480010 +#define SPR_8360_REV10 0x80490010 +#define SPR_8360E_REV11 0x80480011 +#define SPR_8360_REV11 0x80490011 +#define SPR_8360E_REV12 0x80480012 +#define SPR_8360_REV12 0x80490012 + +/* SPCR - System Priority Configuration Register + */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +#define SPCR_PCIHPE_SHIFT (31-3) +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ +#define SPCR_PCIPR_SHIFT (31-7) +#define SPCR_OPT 0x00800000 /* Optimize */ +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ +#define SPCR_TBEN_SHIFT (31-9) +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ +#define SPCR_COREPR_SHIFT (31-11) + +#if defined(CONFIG_MPC8349) +/* SPCR bits - MPC8349 specific */ +#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ +#define SPCR_TSEC1DP_SHIFT (31-19) +#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ +#define SPCR_TSEC1BDP_SHIFT (31-21) +#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ +#define SPCR_TSEC1EP_SHIFT (31-23) +#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ +#define SPCR_TSEC2DP_SHIFT (31-27) +#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ +#define SPCR_TSEC2BDP_SHIFT (31-29) +#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ +#define SPCR_TSEC2EP_SHIFT (31-31) +#endif -#define SWCNR 0x0208 -#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. -#define SWCNR_RES ~(SWCNR_SWCN) +/* SICRL/H - System I/O Configuration Register Low/High + */ +#if defined(CONFIG_MPC8349) +/* SICRL bits - MPC8349 specific */ +#define SICRL_LDP_A 0x80000000 +#define SICRL_USB1 0x40000000 +#define SICRL_USB0 0x20000000 +#define SICRL_UART 0x0C000000 +#define SICRL_GPIO1_A 0x02000000 +#define SICRL_GPIO1_B 0x01000000 +#define SICRL_GPIO1_C 0x00800000 +#define SICRL_GPIO1_D 0x00400000 +#define SICRL_GPIO1_E 0x00200000 +#define SICRL_GPIO1_F 0x00180000 +#define SICRL_GPIO1_G 0x00040000 +#define SICRL_GPIO1_H 0x00020000 +#define SICRL_GPIO1_I 0x00010000 +#define SICRL_GPIO1_J 0x00008000 +#define SICRL_GPIO1_K 0x00004000 +#define SICRL_GPIO1_L 0x00003000 + +/* SICRH bits - MPC8349 specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_TSEC1_A 0x10000000 +#define SICRH_TSEC1_B 0x08000000 +#define SICRH_TSEC1_C 0x04000000 +#define SICRH_TSEC1_D 0x02000000 +#define SICRH_TSEC1_E 0x01000000 +#define SICRH_TSEC1_F 0x00800000 +#define SICRH_TSEC2_A 0x00400000 +#define SICRH_TSEC2_B 0x00200000 +#define SICRH_TSEC2_C 0x00100000 +#define SICRH_TSEC2_D 0x00080000 +#define SICRH_TSEC2_E 0x00040000 +#define SICRH_TSEC2_F 0x00020000 +#define SICRH_TSEC2_G 0x00010000 +#define SICRH_TSEC2_H 0x00008000 +#define SICRH_GPIO2_A 0x00004000 +#define SICRH_GPIO2_B 0x00002000 +#define SICRH_GPIO2_C 0x00001000 +#define SICRH_GPIO2_D 0x00000800 +#define SICRH_GPIO2_E 0x00000400 +#define SICRH_GPIO2_F 0x00000200 +#define SICRH_GPIO2_G 0x00000180 +#define SICRH_GPIO2_H 0x00000060 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 + +#elif defined(CONFIG_MPC8360) +/* SICRL bits - MPC8360 specific */ +#define SICRL_LDP_A 0xC0000000 +#define SICRL_LCLK_1 0x10000000 +#define SICRL_LCLK_2 0x08000000 +#define SICRL_SRCID_A 0x03000000 +#define SICRL_IRQ_CKSTP_A 0x00C00000 + +/* SICRH bits - MPC8360 specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_SECONDARY_DDR 0x40000000 +#define SICRH_SDDROE 0x20000000 +#define SICRH_IRQ3 0x10000000 +#define SICRH_UC1EOBI 0x00000004 +#define SICRH_UC2E1OBI 0x00000002 +#define SICRH_UC2E2OBI 0x00000001 +#endif -#define SWSRR 0x020E +/* SWCRR - System Watchdog Control Register + */ +#define SWCRR 0x0204 /* Register offset to immr */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +/* SWCNR - System Watchdog Counter Register + */ +#define SWCNR 0x0208 /* Register offset to immr */ +#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ +#define SWCNR_RES ~(SWCNR_SWCN) -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* SWSRR - System Watchdog Service Register */ -#define IMMRBAR 0x0000 -#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ -#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) +#define SWSRR 0x020E /* Register offset to immr */ -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* ACR - Arbiter Configuration Register */ -#define LBLAWBAR0 0x0020 -#define LBLAWAR0 0x0024 -#define LBLAWBAR1 0x0028 -#define LBLAWAR1 0x002C -#define LBLAWBAR2 0x0030 -#define LBLAWAR2 0x0034 -#define LBLAWBAR3 0x0038 -#define LBLAWAR3 0x003C +#define ACR_COREDIS 0x10000000 /* Core disable */ +#define ACR_COREDIS_SHIFT (31-7) +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ +#define ACR_PIPE_DEP_SHIFT (31-15) +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) +#define ACR_RPTCNT 0x00000700 /* Repeat count */ +#define ACR_RPTCNT_SHIFT (31-23) +#define ACR_APARK 0x00000030 /* Address parking */ +#define ACR_APARK_SHIFT (31-27) +#define ACR_PARKM 0x0000000F /* Parking master */ +#define ACR_PARKM_SHIFT (31-31) + +/* ATR - Arbiter Timers Register + */ +#define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_ATO 0x000000FF /* Address time out */ -/* - * The device ID and revision numbers - */ -#define SPR_8349E_REV10 0x80300100 -#define SPR_8349_REV10 0x80310100 -#define SPR_8347E_REV10_TBGA 0x80320100 -#define SPR_8347_REV10_TBGA 0x80330100 -#define SPR_8347E_REV10_PBGA 0x80340100 -#define SPR_8347_REV10_PBGA 0x80350100 -#define SPR_8343E_REV10 0x80360100 -#define SPR_8343_REV10 0x80370100 - -#define SPR_8349E_REV11 0x80300101 -#define SPR_8349_REV11 0x80310101 -#define SPR_8347E_REV11_TBGA 0x80320101 -#define SPR_8347_REV11_TBGA 0x80330101 -#define SPR_8347E_REV11_PBGA 0x80340101 -#define SPR_8347_REV11_PBGA 0x80350101 -#define SPR_8343E_REV11 0x80360101 -#define SPR_8343_REV11 0x80370101 - -#define SPR_8360E_REV10 0x80480010 -#define SPR_8360_REV10 0x80490010 -#define SPR_8360E_REV11 0x80480011 -#define SPR_8360_REV11 0x80490011 -#define SPR_8360E_REV12 0x80480012 -#define SPR_8360_REV12 0x80490012 +/* AER - Arbiter Event Register + */ +#define AER_ETEA 0x00000020 /* Transfer error */ +#define AER_RES 0x00000010 /* Reserved transfer type */ +#define AER_ECW 0x00000008 /* External control word transfer type */ +#define AER_AO 0x00000004 /* Address Only transfer type */ +#define AER_DTO 0x00000002 /* Data time out */ +#define AER_ATO 0x00000001 /* Address time out */ + +/* AEATR - Arbiter Event Address Register + */ +#define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type */ -/* - * Base Registers & Option Registers - */ -#define BR0 0x5000 -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if defined (CONFIG_MPC8360) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 -#if defined (CONFIG_MPC8349) -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) -#elif defined (CONFIG_MPC8360) -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) +/* HRCWL - Hard Reset Configuration Word Low + */ +#define HRCWL_LBIUCM 0x80000000 +#define HRCWL_LBIUCM_SHIFT 31 +#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 + +#define HRCWL_DDRCM 0x40000000 +#define HRCWL_DDRCM_SHIFT 30 +#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 + +#define HRCWL_SPMF 0x0f000000 +#define HRCWL_SPMF_SHIFT 24 +#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 +#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 +#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 +#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 +#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 +#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 +#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 +#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 +#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 +#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 +#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 +#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 +#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 +#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 +#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 +#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 + +#define HRCWL_VCO_BYPASS 0x00000000 +#define HRCWL_VCO_1X2 0x00000000 +#define HRCWL_VCO_1X4 0x00200000 +#define HRCWL_VCO_1X8 0x00400000 + +#define HRCWL_COREPLL 0x007F0000 +#define HRCWL_COREPLL_SHIFT 16 +#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 +#define HRCWL_CORE_TO_CSB_1X1 0x00020000 +#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 +#define HRCWL_CORE_TO_CSB_2X1 0x00040000 +#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 +#define HRCWL_CORE_TO_CSB_3X1 0x00060000 + +#if defined(CONFIG_MPC8360) +#define HRCWL_CEVCOD 0x000000C0 +#define HRCWL_CEVCOD_SHIFT 6 +#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 +#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 +#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 + +#define HRCWL_CEPDF 0x00000020 +#define HRCWL_CEPDF_SHIFT 5 +#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +#define HRCWL_CE_PLL_DIV_2X1 0x00000020 + +#define HRCWL_CEPMF 0x0000001F +#define HRCWL_CEPMF_SHIFT 0 +#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +#define HRCWL_CE_TO_PLL_1X2 0x00000002 +#define HRCWL_CE_TO_PLL_1X3 0x00000003 +#define HRCWL_CE_TO_PLL_1X4 0x00000004 +#define HRCWL_CE_TO_PLL_1X5 0x00000005 +#define HRCWL_CE_TO_PLL_1X6 0x00000006 +#define HRCWL_CE_TO_PLL_1X7 0x00000007 +#define HRCWL_CE_TO_PLL_1X8 0x00000008 +#define HRCWL_CE_TO_PLL_1X9 0x00000009 +#define HRCWL_CE_TO_PLL_1X10 0x0000000A +#define HRCWL_CE_TO_PLL_1X11 0x0000000B +#define HRCWL_CE_TO_PLL_1X12 0x0000000C +#define HRCWL_CE_TO_PLL_1X13 0x0000000D +#define HRCWL_CE_TO_PLL_1X14 0x0000000E +#define HRCWL_CE_TO_PLL_1X15 0x0000000F +#define HRCWL_CE_TO_PLL_1X16 0x00000010 +#define HRCWL_CE_TO_PLL_1X17 0x00000011 +#define HRCWL_CE_TO_PLL_1X18 0x00000012 +#define HRCWL_CE_TO_PLL_1X19 0x00000013 +#define HRCWL_CE_TO_PLL_1X20 0x00000014 +#define HRCWL_CE_TO_PLL_1X21 0x00000015 +#define HRCWL_CE_TO_PLL_1X22 0x00000016 +#define HRCWL_CE_TO_PLL_1X23 0x00000017 +#define HRCWL_CE_TO_PLL_1X24 0x00000018 +#define HRCWL_CE_TO_PLL_1X25 0x00000019 +#define HRCWL_CE_TO_PLL_1X26 0x0000001A +#define HRCWL_CE_TO_PLL_1X27 0x0000001B +#define HRCWL_CE_TO_PLL_1X28 0x0000001C +#define HRCWL_CE_TO_PLL_1X29 0x0000001D +#define HRCWL_CE_TO_PLL_1X30 0x0000001E +#define HRCWL_CE_TO_PLL_1X31 0x0000001F #endif -#define OR0 0x5004 -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C - -#define OR_GPCM_AM 0xFFFF8000 -#define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_BCTLD 0x00001000 -#define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 -#define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 - -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 - -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 - -/* - * Hard Reset Configration Word - High +/* HRCWH - Hardware Reset Configuration Word High */ -#define HRCWH_PCI_AGENT 0x00000000 -#define HRCWH_PCI_HOST 0x80000000 +#define HRCWH_PCI_HOST 0x80000000 +#define HRCWH_PCI_HOST_SHIFT 31 +#define HRCWH_PCI_AGENT 0x00000000 -#if defined (CONFIG_MPC8349) -#define HRCWH_32_BIT_PCI 0x00000000 -#define HRCWH_64_BIT_PCI 0x40000000 +#if defined(CONFIG_MPC8349) +#define HRCWH_32_BIT_PCI 0x00000000 +#define HRCWH_64_BIT_PCI 0x40000000 #endif -#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 -#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 +#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 + +#define HRCWH_PCI_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined (CONFIG_MPC8349) -#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 -#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 -#elif defined (CONFIG_MPC8360) -#define HRCWH_PCICKDRV_DISABLE 0x00000000 -#define HRCWH_PCICKDRV_ENABLE 0x10000000 +#if defined(CONFIG_MPC8349) +#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 + +#elif defined(CONFIG_MPC8360) +#define HRCWH_PCICKDRV_DISABLE 0x00000000 +#define HRCWH_PCICKDRV_ENABLE 0x10000000 #endif -#define HRCWH_CORE_DISABLE 0x08000000 -#define HRCWH_CORE_ENABLE 0x00000000 +#define HRCWH_CORE_DISABLE 0x08000000 +#define HRCWH_CORE_ENABLE 0x00000000 -#define HRCWH_FROM_0X00000100 0x00000000 -#define HRCWH_FROM_0XFFF00100 0x04000000 +#define HRCWH_FROM_0X00000100 0x00000000 +#define HRCWH_FROM_0XFFF00100 0x04000000 -#define HRCWH_BOOTSEQ_DISABLE 0x00000000 -#define HRCWH_BOOTSEQ_NORMAL 0x01000000 -#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 +#define HRCWH_BOOTSEQ_DISABLE 0x00000000 +#define HRCWH_BOOTSEQ_NORMAL 0x01000000 +#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 -#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 -#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 +#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 +#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 -#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 -#define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined (CONFIG_MPC8349) -#define HRCWH_ROM_LOC_PCI2 0x00200000 +#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 +#define HRCWH_ROM_LOC_PCI1 0x00100000 +#if defined(CONFIG_MPC8349) +#define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 -#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 -#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 - -#if defined (CONFIG_MPC8349) -#define HRCWH_TSEC1M_IN_RGMII 0x00000000 -#define HRCWH_TSEC1M_IN_RTBI 0x00004000 -#define HRCWH_TSEC1M_IN_GMII 0x00008000 -#define HRCWH_TSEC1M_IN_TBI 0x0000C000 - -#define HRCWH_TSEC2M_IN_RGMII 0x00000000 -#define HRCWH_TSEC2M_IN_RTBI 0x00001000 -#define HRCWH_TSEC2M_IN_GMII 0x00002000 -#define HRCWH_TSEC2M_IN_TBI 0x00003000 +#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 +#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 +#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 + +#if defined(CONFIG_MPC8349) +#define HRCWH_TSEC1M_IN_RGMII 0x00000000 +#define HRCWH_TSEC1M_IN_RTBI 0x00004000 +#define HRCWH_TSEC1M_IN_GMII 0x00008000 +#define HRCWH_TSEC1M_IN_TBI 0x0000C000 +#define HRCWH_TSEC2M_IN_RGMII 0x00000000 +#define HRCWH_TSEC2M_IN_RTBI 0x00001000 +#define HRCWH_TSEC2M_IN_GMII 0x00002000 +#define HRCWH_TSEC2M_IN_TBI 0x00003000 #endif -#if defined (CONFIG_MPC8360) -#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 -#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 +#if defined(CONFIG_MPC8360) +#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 +#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 #endif -#define HRCWH_BIG_ENDIAN 0x00000000 -#define HRCWH_LITTLE_ENDIAN 0x00000008 +#define HRCWH_BIG_ENDIAN 0x00000000 +#define HRCWH_LITTLE_ENDIAN 0x00000008 -#define HRCWH_LALE_NORMAL 0x00000000 -#define HRCWH_LALE_EARLY 0x00000004 +#define HRCWH_LALE_NORMAL 0x00000000 +#define HRCWH_LALE_EARLY 0x00000004 -#define HRCWH_LDP_SET 0x00000000 -#define HRCWH_LDP_CLEAR 0x00000002 +#define HRCWH_LDP_SET 0x00000000 +#define HRCWH_LDP_CLEAR 0x00000002 -/* - * Hard Reset Configration Word - Low - */ -#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 -#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 - -#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 -#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 - -#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 -#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 -#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 -#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 -#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 -#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 -#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 -#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 -#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 -#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 -#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 -#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 -#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 -#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 -#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 -#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 - -#define HRCWL_VCO_BYPASS 0x00000000 -#define HRCWL_VCO_1X2 0x00000000 -#define HRCWL_VCO_1X4 0x00200000 -#define HRCWL_VCO_1X8 0x00400000 - -#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 -#define HRCWL_CORE_TO_CSB_1X1 0x00020000 -#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 -#define HRCWL_CORE_TO_CSB_2X1 0x00040000 -#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 -#define HRCWL_CORE_TO_CSB_3X1 0x00060000 - -#if defined (CONFIG_MPC8360) -#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 -#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 -#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 - -#define HRCWL_CE_PLL_DIV_1X1 0x00000000 -#define HRCWL_CE_PLL_DIV_2X1 0x00000020 - -#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 -#define HRCWL_CE_TO_PLL_1X2 0x00000002 -#define HRCWL_CE_TO_PLL_1X3 0x00000003 -#define HRCWL_CE_TO_PLL_1X4 0x00000004 -#define HRCWL_CE_TO_PLL_1X5 0x00000005 -#define HRCWL_CE_TO_PLL_1X6 0x00000006 -#define HRCWL_CE_TO_PLL_1X7 0x00000007 -#define HRCWL_CE_TO_PLL_1X8 0x00000008 -#define HRCWL_CE_TO_PLL_1X9 0x00000009 -#define HRCWL_CE_TO_PLL_1X10 0x0000000A -#define HRCWL_CE_TO_PLL_1X11 0x0000000B -#define HRCWL_CE_TO_PLL_1X12 0x0000000C -#define HRCWL_CE_TO_PLL_1X13 0x0000000D -#define HRCWL_CE_TO_PLL_1X14 0x0000000E -#define HRCWL_CE_TO_PLL_1X15 0x0000000F -#define HRCWL_CE_TO_PLL_1X16 0x00000010 -#define HRCWL_CE_TO_PLL_1X17 0x00000011 -#define HRCWL_CE_TO_PLL_1X18 0x00000012 -#define HRCWL_CE_TO_PLL_1X19 0x00000013 -#define HRCWL_CE_TO_PLL_1X20 0x00000014 -#define HRCWL_CE_TO_PLL_1X21 0x00000015 -#define HRCWL_CE_TO_PLL_1X22 0x00000016 -#define HRCWL_CE_TO_PLL_1X23 0x00000017 -#define HRCWL_CE_TO_PLL_1X24 0x00000018 -#define HRCWL_CE_TO_PLL_1X25 0x00000019 -#define HRCWL_CE_TO_PLL_1X26 0x0000001A -#define HRCWL_CE_TO_PLL_1X27 0x0000001B -#define HRCWL_CE_TO_PLL_1X28 0x0000001C -#define HRCWL_CE_TO_PLL_1X29 0x0000001D -#define HRCWL_CE_TO_PLL_1X30 0x0000001E -#define HRCWL_CE_TO_PLL_1X31 0x0000001F +/* RSR - Reset Status Register + */ +#define RSR_RSTSRC 0xE0000000 /* Reset source */ +#define RSR_RSTSRC_SHIFT 29 +#define RSR_BSF 0x00010000 /* Boot seq. fail */ +#define RSR_BSF_SHIFT 16 +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) +/* RMR - Reset Mode Register + */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + +/* RCR - Reset Control Register + */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + +/* RCER - Reset Control Enable Register + */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + +/* SPMR - System PLL Mode Register + */ +#define SPMR_LBIUCM 0x80000000 +#define SPMR_DDRCM 0x40000000 +#define SPMR_SPMF 0x0F000000 +#define SPMR_CKID 0x00800000 +#define SPMR_CKID_SHIFT 23 +#define SPMR_COREPLL 0x007F0000 +#define SPMR_CEVCOD 0x000000C0 +#define SPMR_CEPDF 0x00000020 +#define SPMR_CEPMF 0x0000001F + +/* OCCR - Output Clock Control Register + */ +#define OCCR_PCICOE0 0x80000000 +#define OCCR_PCICOE1 0x40000000 +#define OCCR_PCICOE2 0x20000000 +#define OCCR_PCICOE3 0x10000000 +#define OCCR_PCICOE4 0x08000000 +#define OCCR_PCICOE5 0x04000000 +#define OCCR_PCICOE6 0x02000000 +#define OCCR_PCICOE7 0x01000000 +#define OCCR_PCICD0 0x00800000 +#define OCCR_PCICD1 0x00400000 +#define OCCR_PCICD2 0x00200000 +#define OCCR_PCICD3 0x00100000 +#define OCCR_PCICD4 0x00080000 +#define OCCR_PCICD5 0x00040000 +#define OCCR_PCICD6 0x00020000 +#define OCCR_PCICD7 0x00010000 +#define OCCR_PCI1CR 0x00000002 +#define OCCR_PCI2CR 0x00000001 +#define OCCR_PCICR OCCR_PCI1CR + +/* SCCR - System Clock Control Register + */ +#define SCCR_ENCCM 0x03000000 +#define SCCR_ENCCM_SHIFT 24 +#define SCCR_ENCCM_0 0x00000000 +#define SCCR_ENCCM_1 0x01000000 +#define SCCR_ENCCM_2 0x02000000 +#define SCCR_ENCCM_3 0x03000000 + +#define SCCR_PCICM 0x00010000 +#define SCCR_PCICM_SHIFT 16 + +/* SCCR bits - MPC8349 specific */ +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 + +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 + +#define SCCR_USBMPHCM 0x00c00000 +#define SCCR_USBMPHCM_SHIFT 22 +#define SCCR_USBDRCM 0x00300000 +#define SCCR_USBDRCM_SHIFT 20 + +#define SCCR_USBCM_0 0x00000000 +#define SCCR_USBCM_1 0x00500000 +#define SCCR_USBCM_2 0x00A00000 +#define SCCR_USBCM_3 0x00F00000 + +#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ + | SCCR_TSEC2CM_3 \ + | SCCR_ENCCM_3 \ + | SCCR_USBCM_3 ) + +#define SCCR_DEFAULT 0xFFFFFFFF + +/* CSn_BDNS - Chip Select memory Bounds Register + */ +#define CSBNDS_SA 0x00FF0000 +#define CSBNDS_SA_SHIFT 8 +#define CSBNDS_EA 0x000000FF +#define CSBNDS_EA_SHIFT 24 + +/* CSn_CONFIG - Chip Select Configuration Register + */ +#define CSCONFIG_EN 0x80000000 +#define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ROW_BIT 0x00000700 +#define CSCONFIG_ROW_BIT_12 0x00000000 +#define CSCONFIG_ROW_BIT_13 0x00000100 +#define CSCONFIG_ROW_BIT_14 0x00000200 +#define CSCONFIG_COL_BIT 0x00000007 +#define CSCONFIG_COL_BIT_8 0x00000000 +#define CSCONFIG_COL_BIT_9 0x00000001 +#define CSCONFIG_COL_BIT_10 0x00000002 +#define CSCONFIG_COL_BIT_11 0x00000003 + +/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 + */ +#define TIMING_CFG1_PRETOACT 0x70000000 +#define TIMING_CFG1_PRETOACT_SHIFT 28 +#define TIMING_CFG1_ACTTOPRE 0x0F000000 +#define TIMING_CFG1_ACTTOPRE_SHIFT 24 +#define TIMING_CFG1_ACTTORW 0x00700000 +#define TIMING_CFG1_ACTTORW_SHIFT 20 +#define TIMING_CFG1_CASLAT 0x00070000 +#define TIMING_CFG1_CASLAT_SHIFT 16 +#define TIMING_CFG1_REFREC 0x0000F000 +#define TIMING_CFG1_REFREC_SHIFT 12 +#define TIMING_CFG1_WRREC 0x00000700 +#define TIMING_CFG1_WRREC_SHIFT 8 +#define TIMING_CFG1_ACTTOACT 0x00000070 +#define TIMING_CFG1_ACTTOACT_SHIFT 4 +#define TIMING_CFG1_WRTORD 0x00000007 +#define TIMING_CFG1_WRTORD_SHIFT 0 +#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ + +/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 + */ +#define TIMING_CFG2_CPO 0x0F000000 +#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_ACSM 0x00080000 +#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 + +/* DDR_SDRAM_MODE - DDR SDRAM Mode Register + */ +#define SDRAM_MODE_ESD 0xFFFF0000 +#define SDRAM_MODE_ESD_SHIFT 16 +#define SDRAM_MODE_SD 0x0000FFFF +#define SDRAM_MODE_SD_SHIFT 0 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +#define DDR_MODE_MODEREG 0x0000 /* select mode register */ + +/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register + */ +#define SDRAM_INTERVAL_REFINT 0x3FFF0000 +#define SDRAM_INTERVAL_REFINT_SHIFT 16 +#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + +/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register + */ +#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 + +/* ECC_ERR_INJECT - Memory data path error injection mask ECC + */ +#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ +#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ +#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ +#define ECC_ERR_INJECT_EEIM_SHIFT 0 + +/* CAPTURE_ECC - Memory data path read capture ECC + */ +#define CAPTURE_ECC_ECE (0xff000000>>24) +#define CAPTURE_ECC_ECE_SHIFT 0 + +/* ERR_DETECT - Memory error detect + */ +#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ +#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ +#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ + +/* ERR_DISABLE - Memory error disable + */ +#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ +#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ +#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ +#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ + ECC_ERROR_DISABLE_MBED) +/* ERR_INT_EN - Memory error interrupt enable + */ +#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ +#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ + ECC_ERR_INT_EN_MSEE) +/* CAPTURE_ATTRIBUTES - Memory error attributes capture + */ +#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ +#define ECC_CAPT_ATTR_BNUM_SHIFT 28 +#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 +#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 +#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 +#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 +#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ +#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 +#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 +#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 +#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 +#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) +#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 +#define ECC_CAPT_ATTR_TSRC_I2C 0x9 +#define ECC_CAPT_ATTR_TSRC_JTAG 0xA +#define ECC_CAPT_ATTR_TSRC_PCI1 0xD +#define ECC_CAPT_ATTR_TSRC_PCI2 0xE +#define ECC_CAPT_ATTR_TSRC_DMA 0xF +#define ECC_CAPT_ATTR_TSRC_SHIFT 16 +#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ +#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 +#define ECC_CAPT_ATTR_TTYP_READ 0x2 +#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 +#define ECC_CAPT_ATTR_TTYP_SHIFT 12 +#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ + +/* ERR_SBE - Single bit ECC memory error management + */ +#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ +#define ECC_ERROR_MAN_SBET_SHIFT 16 +#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ +#define ECC_ERROR_MAN_SBEC_SHIFT 0 + +/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#if defined(CONFIG_MPC8360) +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 #endif +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 -/* - * LCRR - Clock Ratio Register (10.3.1.16) - */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 -#define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC8349) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) +#elif defined(CONFIG_MPC8360) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) +#endif -/* - * SCCR-System Clock Control Register - */ -#define SCCR_TSEC1CM_0 0x00000000 -#define SCCR_TSEC1CM_1 0x40000000 -#define SCCR_TSEC1CM_2 0x80000000 -#define SCCR_TSEC1CM_3 0xC0000000 -#define SCCR_TSEC2CM_0 0x00000000 -#define SCCR_TSEC2CM_1 0x10000000 -#define SCCR_TSEC2CM_2 0x20000000 -#define SCCR_TSEC2CM_3 0x30000000 -#define SCCR_ENCCM_0 0x00000000 -#define SCCR_ENCCM_1 0x01000000 -#define SCCR_ENCCM_2 0x02000000 -#define SCCR_ENCCM_3 0x03000000 -#define SCCR_USBCM_0 0x00000000 -#define SCCR_USBCM_1 0x00500000 -#define SCCR_USBCM_2 0x00A00000 -#define SCCR_USBCM_3 0x00F00000 - -#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ - | SCCR_TSEC2CM_3 \ - | SCCR_ENCCM_3 \ - | SCCR_USBCM_3 ) - -#define SCCR_DEFAULT 0xFFFFFFFF +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_0b10 0x00000400 +#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +/* LBCR - Local Bus Configuration Register + */ +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 + +/* LCRR - Clock Ratio Register + */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_BUFCMDC_1 0x10000000 +#define LCRR_BUFCMDC_2 0x20000000 +#define LCRR_BUFCMDC_3 0x30000000 +#define LCRR_BUFCMDC_4 0x00000000 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_ECL_4 0x00000000 +#define LCRR_ECL_5 0x01000000 +#define LCRR_ECL_6 0x02000000 +#define LCRR_ECL_7 0x03000000 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_EADC_1 0x00010000 +#define LCRR_EADC_2 0x00020000 +#define LCRR_EADC_3 0x00030000 +#define LCRR_EADC_4 0x00000000 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 +#define LCRR_CLKDIV_2 0x00000002 +#define LCRR_CLKDIV_4 0x00000004 +#define LCRR_CLKDIV_8 0x00000008 + +/* DMAMR - DMA Mode Register + */ +#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ +#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ +#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ +#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ + +/* DMASR - DMA Status Register + */ +#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ +#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ + +/* CONFIG_ADDRESS - PCI Config Address Register + */ +#define PCI_CONFIG_ADDRESS_EN 0x80000000 +#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 +#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 +#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 +#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 +#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 +#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc + +/* POTAR - PCI Outbound Translation Address Register + */ +#define POTAR_TA_MASK 0x000fffff + +/* POBAR - PCI Outbound Base Address Register + */ +#define POBAR_BA_MASK 0x000fffff + +/* POCMR - PCI Outbound Comparision Mask Register + */ +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + +/* PITAR - PCI Inbound Translation Address Register + */ +#define PITAR_TA_MASK 0x000fffff + +/* PIBAR - PCI Inbound Base/Extended Address Register + */ +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff + +/* PIWAR - PCI Inbound Windows Attributes Register + */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E #endif /* __MPC83XX_H__ */ -- cgit v1.3.1 From 24c3aca3f1358b113d3215adb5433b156e99f72b Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Thu, 7 Dec 2006 21:13:15 +0800 Subject: mpc83xx: Add support for the MPC832XEMDS board This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu --- Makefile | 24 ++ board/mpc832xemds/Makefile | 50 ++++ board/mpc832xemds/config.mk | 28 ++ board/mpc832xemds/mpc832xemds.c | 176 +++++++++++ board/mpc832xemds/pci.c | 313 ++++++++++++++++++++ board/mpc832xemds/u-boot.lds | 123 ++++++++ cpu/mpc83xx/cpu.c | 16 + cpu/mpc83xx/cpu_init.c | 5 + cpu/mpc83xx/speed.c | 39 ++- drivers/qe/qe.h | 2 +- drivers/qe/uec.c | 11 +- include/asm-ppc/e300.h | 5 + include/asm-ppc/immap_83xx.h | 72 ++++- include/asm-ppc/immap_qe.h | 6 + include/configs/MPC832XEMDS.h | 629 ++++++++++++++++++++++++++++++++++++++++ include/mpc83xx.h | 21 +- 16 files changed, 1488 insertions(+), 32 deletions(-) create mode 100644 board/mpc832xemds/Makefile create mode 100644 board/mpc832xemds/config.mk create mode 100644 board/mpc832xemds/mpc832xemds.c create mode 100644 board/mpc832xemds/pci.c create mode 100644 board/mpc832xemds/u-boot.lds create mode 100644 include/configs/MPC832XEMDS.h (limited to 'include/asm-ppc') diff --git a/Makefile b/Makefile index 358d1817c94..af01a10753c 100644 --- a/Makefile +++ b/Makefile @@ -1648,6 +1648,30 @@ MPC8360EMDS_SLAVE_config: unconfig MPC8349ITX_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx +MPC832XEMDS_config \ +MPC832XEMDS_HOST_33_config \ +MPC832XEMDS_HOST_66_config \ +MPC832XEMDS_SLAVE_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _HOST_,$@)" ] ; then \ + echo -n "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _SLAVE_,$@)" ] ; then \ + echo "...PCI SLAVE 66M" ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "...33M ..." ; \ + echo "#define PCI_33M" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _66_,$@)" ] ; then \ + echo -n "...66M..." ; \ + echo "#define PCI_66M" >>include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds + ######################################################################### ## MPC85xx Systems ######################################################################### diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile new file mode 100644 index 00000000000..5ec7a871d4d --- /dev/null +++ b/board/mpc832xemds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc832xemds/config.mk b/board/mpc832xemds/config.mk new file mode 100644 index 00000000000..6c3eca75341 --- /dev/null +++ b/board/mpc832xemds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC832XEMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c new file mode 100644 index 00000000000..772da678f00 --- /dev/null +++ b/board/mpc832xemds/mpc832xemds.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#else +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* ETH3 */ + {1, 0, 1, 0, 1}, /* TxD0 */ + {1, 1, 1, 0, 1}, /* TxD1 */ + {1, 2, 1, 0, 1}, /* TxD2 */ + {1, 3, 1, 0, 1}, /* TxD3 */ + {1, 9, 1, 0, 1}, /* TxER */ + {1, 12, 1, 0, 1}, /* TxEN */ + {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1}, /* RxD0 */ + {1, 5, 2, 0, 1}, /* RxD1 */ + {1, 6, 2, 0, 1}, /* RxD2 */ + {1, 7, 2, 0, 1}, /* RxD3 */ + {1, 8, 2, 0, 1}, /* RxER */ + {1, 10, 2, 0, 1}, /* RxDV */ + {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1}, /* COL */ + {1, 13, 2, 0, 1}, /* CRS */ + + /* ETH4 */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 20, 1, 0, 1}, /* TxD2 */ + {1, 21, 1, 0, 1}, /* TxD3 */ + {1, 27, 1, 0, 1}, /* TxER */ + {1, 30, 1, 0, 1}, /* TxEN */ + {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 24, 2, 0, 1}, /* RxD2 */ + {1, 25, 2, 0, 1}, /* RxD3 */ + {1, 26, 1, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1}, /* COL */ + {1, 31, 2, 0, 1}, /* CRS */ + + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +int board_early_init_f(void) +{ + volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; + + /* Enable flash write */ + bcsr[9] &= ~0x08; + + return 0; +} + +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + + msize = fixed_sdram(); + + puts("\n DDR RAM: "); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 128) +#warning Currenly any ddr size other than 128 is not supported +#endif + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__ ("sync"); + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + __asm__ __volatile__ ("sync"); + return msize; +} + +int checkboard(void) +{ + puts("Board: Freescale MPC832XEMDS\n"); + return 0; +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c new file mode 100644 index 00000000000..09f3ac347c0 --- /dev/null +++ b/board/mpc832xemds/pci.c @@ -0,0 +1,313 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/* + * PCI Configuration space access support for MPC83xx PCI Bridge + */ +#include +#include +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +#define PCI_FUNCTION_CONFIG 0x44 +#define PCI_FUNCTION_CFG_LOCK 0x20 + +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxemds_config_table[] = { + { + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, + {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif +static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxemds_config_table, +#endif + }, +}; + +/********************************************************************** + * pci_init_board() + *********************************************************************/ +void pci_init_board(void) +#ifdef CONFIG_PCISLAVE +{ + u16 reg16; + volatile immap_t *immr; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + immr = (immap_t *) CFG_IMMR; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar0 = 0x0; + pci_ctrl[0].pibar0 = 0x0; + pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_4K; + + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 &= ~PIWAR_EN; + + pci_ctrl[0].pitar2 = 0x0; + pci_ctrl[0].pibar2 = 0x0; + pci_ctrl[0].piebar2 = 0x0; + pci_ctrl[0].piwar2 &= ~PIWAR_EN; + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + reg16 = 0xff; + + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), + PCI_LATENCY_TIMER, 0x80); + + /* + * Unlock configuration lock in PCI function configuration register. + */ + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, ®16); + reg16 &= ~(PCI_FUNCTION_CFG_LOCK); + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, reg16); + + printf("Enabled PCI 32bit Agent Mode\n"); +} +#else +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + u8 val8, orig_i2c_bus; + u16 reg16; + u32 val32; + u32 dev; + + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + val32 = clk->occr; + udelay(2000); +#if defined(PCI_66M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#elif defined(PCI_33M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | + OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; + printf("PCI clock is 33MHz\n"); +#else + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#endif + udelay(2000); + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = + POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI mmio - non-prefetch mem space */ + pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI IO space */ + pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + PIWAR_IWS_2G; + + /* + * Assign PIB PMC slot to desired PCI bus + */ + + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); + + val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + asm("eieio"); + + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); + + /* + * Release PCI RST Output signal + */ + udelay(2000); + pci_ctrl[0].gcr = 1; + udelay(2000); + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose[0].regions + 0, + CFG_PCI_MEM_BASE, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose[0].regions + 1, + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose[0].regions + 2, + CFG_PCI_IO_BASE, + CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose[0].regions + 3, + CFG_PCI_SLV_MEM_LOCAL, + CFG_PCI_SLV_MEM_BUS, + CFG_PCI_SLV_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose[0].region_count = 4; + + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write command register + */ + reg16 = 0xff; + dev = PCI_BDF(0, 0, 0); + pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); + + printf("PCI 32bit bus on PMC2 & PMC3\n"); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCISLAVE */ + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = hose[0].first_busno; + p[1] = hose[0].last_busno; + } +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc832xemds/u-boot.lds b/board/mpc832xemds/u-boot.lds new file mode 100644 index 00000000000..937c87a27cd --- /dev/null +++ b/board/mpc832xemds/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 1b5107881ed..bc61219337e 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -92,6 +92,22 @@ int checkcpu(void) case SPR_8360_REV12: puts("MPC8360, "); break; + case SPR_8323E_REV10: + case SPR_8323E_REV11: + puts("MPC8323E, "); + break; + case SPR_8323_REV10: + case SPR_8323_REV11: + puts("MPC8323, "); + break; + case SPR_8321E_REV10: + case SPR_8321E_REV11: + puts("MPC8321E, "); + break; + case SPR_8321_REV10: + case SPR_8321_REV11: + puts("MPC8321, "); + break; default: puts("Rev: Unknown\n"); return -1; /* Not sure what this is */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 7574fabf864..eb256e598d3 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -119,6 +119,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif + /* DDR control driver register */ +#ifdef CFG_DDRCDR + im->sysconf.ddrcdr = CFG_DDRCDR; +#endif + #ifdef CONFIG_QE /* Config QE ioports */ config_qe_ioports(); diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 40ba6b04a3b..9fd1bf1bae8 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -107,15 +107,19 @@ int get_clocks(void) #endif u32 core_clk; u32 i2c1_clk; +#if !defined(CONFIG_MPC832X) u32 i2c2_clk; +#endif u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; u32 ddr_clk; -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) + u32 ddr_sec_clk; +#endif +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) u32 qepmf; u32 qepdf; - u32 ddr_sec_clk; u32 qe_clk; u32 brg_clk; #endif @@ -227,10 +231,12 @@ int get_clocks(void) return -9; } #endif -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) i2c1_clk = csb_clk; #endif +#if !defined(CONFIG_MPC832X) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ +#endif switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: @@ -249,12 +255,9 @@ int get_clocks(void) /* unkown SCCR_ENCCM value */ return -6; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) + lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); -#else -#error Unknown MPC83xx chip -#endif lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: @@ -266,16 +269,13 @@ int get_clocks(void) /* unknown lcrr */ return -10; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) + ddr_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) ddr_sec_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); -#endif -#else -#error Unknown MPC83xx chip #endif corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); @@ -306,7 +306,7 @@ int get_clocks(void) return -12; } -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); @@ -322,13 +322,17 @@ int get_clocks(void) #endif gd->core_clk = core_clk; gd->i2c1_clk = i2c1_clk; +#if !defined(CONFIG_MPC832X) gd->i2c2_clk = i2c2_clk; +#endif gd->enc_clk = enc_clk; gd->lbiu_clk = lbiu_clk; gd->lclk_clk = lclk_clk; gd->ddr_clk = ddr_clk; -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) gd->ddr_sec_clk = ddr_sec_clk; +#endif +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif @@ -352,18 +356,21 @@ int print_clock_conf(void) printf("Clock configuration:\n"); printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); printf(" Core: %4d MHz\n", gd->core_clk / 1000000); -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); + printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000); #endif printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000); -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000); #endif printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); +#if !defined(CONFIG_MPC832X) printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); +#endif #if defined(CONFIG_MPC8349) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index f7f8ed0a724..0bcd0a9573e 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -30,7 +30,7 @@ #define UCC_MAX_NUM 8 #define QE_DATAONLY_BASE (uint)(128) -#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) /* QE threads SNUM */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index c44a5be9dac..aea455b8dc0 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -432,7 +432,12 @@ static int init_phy(struct eth_device *dev) } memset(mii_info, 0, sizeof(*mii_info)); - mii_info->speed = SPEED_1000; + if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { + mii_info->speed = SPEED_1000; + } else { + mii_info->speed = SPEED_100; + } + mii_info->duplex = DUPLEX_FULL; mii_info->pause = 0; mii_info->link = 1; @@ -508,7 +513,8 @@ static void adjust_link(struct eth_device *dev) } if (mii_info->speed != uec->oldspeed) { - switch (mii_info->speed) { + if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { + switch (mii_info->speed) { case 1000: break; case 100: @@ -531,6 +537,7 @@ static void adjust_link(struct eth_device *dev) printf("%s: Ack,Speed(%d)is illegal\n", dev->name, mii_info->speed); break; + } } printf("%s: Speed %dBT\n", dev->name, mii_info->speed); diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 79dcae416f9..ff9512f203c 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -15,6 +15,11 @@ #define PVR_8360_REV10 (PVR_83xx | 0x0020) #define PVR_8360_REV11 (PVR_83xx | 0x0020) +#if defined(CONFIG_MPC832X) +#undef PVR_83xx +#define PVR_83xx 0x80840000 +#endif + /* * Hardware Implementation-Dependent Register 0 (HID0) */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 67b035c6140..77a079f44e8 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -60,7 +60,10 @@ typedef struct sysconf83xx { u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0xE4]; + u8 res6[0x0C]; + u32 ddrcdr; /* DDR Control Driver Register */ + u32 ddrdsr; /* DDR Debug Status Register */ + u8 res7[0xD0]; } sysconf83xx_t; /* @@ -274,25 +277,35 @@ typedef struct ddr83xx { ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ u8 res0[0x60]; u32 cs_config[4]; /* Chip Select x Configuration */ - u8 res1[0x78]; + u8 res1[0x70]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ u32 sdram_cfg; /* SDRAM Control Configuration */ - u8 res2[4]; + u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ u32 sdram_mode; /* SDRAM Mode Configuration */ - u8 res3[8]; + u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ u32 sdram_interval; /* SDRAM Interval Configuration */ - u8 res9[8]; - u32 sdram_clk_cntl; - u8 res4[0xCCC]; + u32 ddr_data_init; /* SDRAM Data Initialization */ + u8 res2[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res3[0x14]; + u32 ddr_init_addr; /* DDR training initialization address */ + u32 ddr_init_ext_addr; /* DDR training initialization extended address */ + u8 res4[0xAA8]; + u32 ddr_ip_rev1; /* DDR IP block revision 1 */ + u32 ddr_ip_rev2; /* DDR IP block revision 2 */ + u8 res5[0x200]; u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ - u8 res5[0x14]; + u8 res6[0x14]; u32 capture_data_hi; /* Memory Data Path Read Capture High */ u32 capture_data_lo; /* Memory Data Path Read Capture Low */ u32 capture_ecc; /* Memory Data Path Read Capture ECC */ - u8 res6[0x14]; + u8 res7[0x14]; u32 err_detect; /* Memory Error Detect */ u32 err_disable; /* Memory Error Disable */ u32 err_int_en; /* Memory Error Interrupt Enable */ @@ -300,9 +313,9 @@ typedef struct ddr83xx { u32 capture_address; /* Memory Error Address Capture */ u32 capture_ext_address;/* Memory Error Extended Address Capture */ u32 err_sbe; /* Memory Single-Bit ECC Error Management */ - u8 res7[0xA4]; + u8 res8[0xA4]; u32 debug_reg; - u8 res8[0xFC]; + u8 res9[0xFC]; } ddr83xx_t; /* @@ -607,6 +620,43 @@ typedef struct immap { u8 res10[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; + +#elif defined(CONFIG_MPC832X) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + u8 res0[0x300]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res1[0x200]; + qepio83xx_t qepio; /* QE Parallel I/O ports */ + u8 res2[0x800]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res3[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res4[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res5[0x2000]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res6[128]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res7[0x27A00]; + security83xx_t security; + u8 res8[0xC0000]; + u8 qe[0x100000]; /* QE block */ +} immap_t; #endif #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index f38503206cc..950b9497f8a 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -547,4 +547,10 @@ typedef struct qe_immap { extern qe_map_t *qe_immr; +#if defined(CONFIG_MPC8360) +#define QE_MURAM_SIZE 0xc000UL +#elif defined(CONFIG_MPC832X) +#define QE_MURAM_SIZE 0x4000UL +#endif + #endif /* __IMMAP_QE_H__ */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h new file mode 100644 index 00000000000..b8bf00f861e --- /dev/null +++ b/include/configs/MPC832XEMDS.h @@ -0,0 +1,629 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83xx family */ +#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1 |\ + HRCWL_CE_PLL_VCO_DIV_2 |\ + HRCWL_CE_PLL_DIV_1X1 |\ + HRCWL_CE_TO_PLL_1X3) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#endif + +/* + * System IO Config + */ +#define CFG_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +#undef CONFIG_SPD_EEPROM +#if defined(CONFIG_SPD_EEPROM) +/* Determine DDR configuration from I2C interface + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ +#else +/* Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CS0_CONFIG 0x80840102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x3935d322 +#define CFG_DDR_TIMING_2 0x0f9048ca +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x44400232 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03200064 +#define CFG_DDR_CS0_BNDS 0x00000007 +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * SDRAM on the Local Bus + */ +#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ + +/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON 0x0063b723 + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + +#endif + +/* + * Windows to access PIB via local bus + */ +#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ + +/* + * CS2 on Local Bus, to PIB + */ +#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ +#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * CS3 on Local Bus, to PIB + */ +#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ +#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8323@0" +#define OF_SOC "soc8323@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + + +#ifdef CONFIG_PCI + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" + +#define CONFIG_UEC_ETH1 /* ETH3 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ +#define CFG_UEC1_RX_CLK QE_CLK9 +#define CFG_UEC1_TX_CLK QE_CLK10 +#define CFG_UEC1_ETH_TYPE FAST_ETH +#define CFG_UEC1_PHY_ADDR 3 +#define CFG_UEC1_INTERFACE_MODE ENET_100_MII +#endif + +#define CONFIG_UEC_ETH2 /* ETH4 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 3 /* UCC4 */ +#define CFG_UEC2_RX_CLK QE_CLK7 +#define CFG_UEC2_TX_CLK QE_CLK8 +#define CFG_UEC2_ETH_TYPE FAST_ETH +#define CFG_UEC2_PHY_ADDR 4 +#define CFG_UEC2_INTERFACE_MODE ENET_100_MII +#endif + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_ETHADDR 00:04:9f:ef:03:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc832xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 504b6a97bc7..52e43691513 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -75,6 +75,15 @@ #define SPR_8360E_REV12 0x80480012 #define SPR_8360_REV12 0x80490012 +#define SPR_8323E_REV10 0x80620010 +#define SPR_8323_REV10 0x80630010 +#define SPR_8321E_REV10 0x80660010 +#define SPR_8321_REV10 0x80670010 +#define SPR_8323E_REV11 0x80620011 +#define SPR_8323_REV11 0x80630011 +#define SPR_8321E_REV11 0x80660011 +#define SPR_8321_REV11 0x80670011 + /* SPCR - System Priority Configuration Register */ #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ @@ -167,6 +176,14 @@ #define SICRH_UC1EOBI 0x00000004 #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001 + +#elif defined(CONFIG_MPC832X) +/* SICRL bits - MPC832X specific */ +#define SICRL_LDP_LCS_A 0x80000000 +#define SICRL_IRQ_CKS 0x20000000 +#define SICRL_PCI_MSRC 0x10000000 +#define SICRL_URT_CTPR 0x06000000 +#define SICRL_IRQ_CTPR 0x00C00000 #endif /* SWCRR - System Watchdog Control Register @@ -270,7 +287,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -718,7 +735,7 @@ #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif -- cgit v1.3.1 From 3e78a31cfe3d3022f46f67eb88e1281d5cc2eb89 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 30 Jan 2007 14:08:30 -0600 Subject: mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala --- cpu/mpc83xx/cpu.c | 2 +- cpu/mpc83xx/speed.c | 8 ++++---- include/asm-ppc/global_data.h | 4 ++-- include/asm-ppc/immap_83xx.h | 2 +- include/mpc83xx.h | 14 +++++++------- 5 files changed, 15 insertions(+), 15 deletions(-) (limited to 'include/asm-ppc') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index bc61219337e..15e04ba5f74 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -113,7 +113,7 @@ int checkcpu(void) return -1; /* Not sure what this is */ } -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock)); #else printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock)); diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 9fd1bf1bae8..c75993059e0 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -99,7 +99,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; @@ -148,7 +148,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -314,7 +314,7 @@ int get_clocks(void) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbmph_clk = usbmph_clk; @@ -371,7 +371,7 @@ int print_clock_conf(void) #if !defined(CONFIG_MPC832X) printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); #endif -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 8bc61b63a85..c113b7ee0e4 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -52,12 +52,12 @@ typedef struct global_data { #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; u32 usbdr_clk; -#endif /* CONFIG_MPC8349 */ +#endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 77a079f44e8..5e088d67d24 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -544,7 +544,7 @@ typedef struct security83xx { u8 fixme[0x10000]; } security83xx_t; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 52e43691513..c1c6ad1e712 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -96,7 +96,7 @@ #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ #define SPCR_COREPR_SHIFT (31-11) -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) /* SPCR bits - MPC8349 specific */ #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ #define SPCR_TSEC1DP_SHIFT (31-19) @@ -114,7 +114,7 @@ /* SICRL/H - System I/O Configuration Register Low/High */ -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) /* SICRL bits - MPC8349 specific */ #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 @@ -340,7 +340,7 @@ #define HRCWH_PCI_HOST_SHIFT 31 #define HRCWH_PCI_AGENT 0x00000000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -351,7 +351,7 @@ #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 @@ -375,14 +375,14 @@ #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000 @@ -742,7 +742,7 @@ #define BR_V 0x00000001 #define BR_V_SHIFT 0 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) #elif defined(CONFIG_MPC8360) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) -- cgit v1.3.1 From e01bd218b00af73499331a1a701625a852cd286f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Mar 2007 13:38:59 +0100 Subject: [PATCH] Add AMCC PPC405EZ support This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 3 + cpu/ppc4xx/cpu.c | 18 +- cpu/ppc4xx/cpu_init.c | 3 +- cpu/ppc4xx/serial.c | 97 ++++++-- cpu/ppc4xx/speed.c | 114 +++++++++- cpu/ppc4xx/start.S | 77 ++++++- cpu/ppc4xx/usb_ohci.c | 6 +- cpu/ppc4xx/vecnum.h | 42 ++++ include/asm-ppc/processor.h | 9 + include/asm-ppc/u-boot.h | 4 +- include/ppc405.h | 540 ++++++++++++++++++++++++++++++++++++++++++++ include/ppc4xx_enet.h | 217 +++++++++--------- 12 files changed, 979 insertions(+), 151 deletions(-) (limited to 'include/asm-ppc') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 4f5558328a2..cf56581d845 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1333,6 +1333,9 @@ int enetInt (struct eth_device *dev) } } mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ +#if defined(CONFIG_405EZ) + mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ } while (serviced); diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index b02f6f4eefb..2d8740ccea4 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -47,6 +47,9 @@ void board_reset(void); #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) +#elif defined(CONFIG_405EZ) +#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \ + sys_info.pllExtBusDiv) #else #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) #endif @@ -209,7 +212,8 @@ int checkcpu (void) puts("AMCC PowerPC 4"); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) puts("05"); #endif #if defined(CONFIG_440) @@ -257,6 +261,10 @@ int checkcpu (void) puts("EP Rev. B"); break; + case PVR_405EZ_RA: + puts("EZ Rev. A"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -386,9 +394,9 @@ int checkcpu (void) } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - FREQ_EBC / 1000000); + sys_info.freqPLB / 1000000, + get_OPB_freq() / 1000000, + FREQ_EBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); @@ -418,7 +426,7 @@ int checkcpu (void) putc('\n'); #endif -#if defined(CONFIG_405EP) +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 82ae4434b0b..9d1cd1343d2 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -256,7 +256,8 @@ cpu_init_f (void) */ #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405)) + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index fab0d950063..e62dd9dac51 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -264,7 +264,8 @@ int serial_tstc () #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_440) #if defined(CONFIG_440) @@ -309,7 +310,7 @@ int serial_tstc () #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) #endif /* #if defined(CONFIG_440GP) */ -#elif defined(CONFIG_405EP) +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 #define UCR0_MASK 0x0000007f @@ -392,47 +393,95 @@ volatile static serial_buffer_t buf_info; #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv ) + unsigned short *pbdiv) { - sys_info_t sysinfo; + sys_info_t sysinfo; unsigned long div; /* total divisor udiv * bdiv */ unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ unsigned long i; - unsigned long est; /* current estimate */ + unsigned long est; /* current estimate */ - get_sys_info( &sysinfo ); + get_sys_info(&sysinfo); - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ /* i is the test udiv value -- start with the largest * possible (32) to minimize serial clock and constrain * search to umin. */ - for( i = 32; i > umin; i-- ){ - ibdiv = div/i; + for (i = 32; i > umin; i--) { + ibdiv = div / i; est = i * ibdiv; idiff = (est > div) ? (est-div) : (div-est); - if( idiff == 0 ){ + if (idiff == 0) { udiv = i; break; /* can't do better */ - } - else if( idiff < diff ){ + } else if (idiff < diff) { udiv = i; /* best so far */ diff = idiff; /* update lowest diff*/ } } *pudiv = udiv; - *pbdiv = div/udiv; + *pbdiv = div / udiv; +} + +#elif defined(CONFIG_405EZ) + +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + unsigned long plloutb; + u32 reg; + + get_sys_info(&sysinfo); + plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv) + / sysinfo.pllFwdDivB); + udiv = 256; /* Assume lowest possible serial clk */ + div = plloutb / (16 * baudrate); /* total divisor */ + umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ + diff = 256; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (256) to minimize serial clock and constrain + * search to umin. + */ + for (i = 256; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + mfcpr(cprperd0, reg); + reg &= ~0x0000ffff; + reg |= ((udiv - 0) << 8) | (udiv - 0); + mtcpr(cprperd0, reg); + *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ @@ -518,6 +567,10 @@ int serial_init (void) unsigned short bdiv; volatile char val; +#if defined(CONFIG_405EZ) + serial_divs(gd->baudrate, &udiv, &bdiv); + clk = tmp = reg = 0; +#else #ifdef CONFIG_405EP reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; @@ -548,9 +601,9 @@ int serial_init (void) reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (cntrl0, reg); #endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; +#endif /* CONFIG_405EZ */ out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 06220c34394..028b11af892 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -767,11 +767,119 @@ ulong get_PCI_freq (void) return val; } +#elif defined(CONFIG_405EZ) +void get_sys_info (PPC405_SYS_INFO * sysInfo) +{ + unsigned long cpr_plld; + unsigned long cpr_primad; + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); + unsigned long primad_cpudv; + unsigned long m; + + /* + * Read PLL Mode registers + */ + mfcpr(cprplld, cpr_plld); + + /* + * Determine forward divider A + */ + sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); + + /* + * Determine forward divider B (should be equal to A) + */ + sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); + if (sysInfo->pllFwdDivB == 0) { + sysInfo->pllFwdDivB = 8; + } + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (sysInfo->pllFbkDiv == 0) { + sysInfo->pllFbkDiv = 256; + } + + /* + * Read CPR_PRIMAD register + */ + mfcpr(cprprimad, cpr_primad); + /* + * Determine PLB_DIV. + */ + sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); + if (sysInfo->pllPlbDiv == 0) { + sysInfo->pllPlbDiv = 16; + } + + /* + * Determine EXTBUS_DIV. + */ + sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); + if (sysInfo->pllExtBusDiv == 0) { + sysInfo->pllExtBusDiv = 16; + } + + /* + * Determine OPB_DIV. + */ + sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); + if (sysInfo->pllOpbDiv == 0) { + sysInfo->pllOpbDiv = 16; + } + + /* + * Determine the M factor + */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + + /* + * Determine VCO clock frequency + */ + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + + /* + * Determine CPU clock frequency + */ + primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); + if (primad_cpudv == 0) { + primad_cpudv = 16; + } + + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv; + + /* + * Determine PLB clock frequency + */ + sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv; +} + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; + + return val; +} + #endif int get_clocks (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) || defined(CONFIG_405) sys_info_t sys_info; get_sys_info (&sys_info); @@ -796,7 +904,9 @@ ulong get_bus_freq (ulong dummy) { ulong val; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) || defined(CONFIG_405) sys_info_t sys_info; get_sys_info (&sys_info); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 24b30dfe716..a50d66e14b6 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -699,7 +699,9 @@ _start: #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405) /*----------------------------------------------------------------------- */ /* Clear and set up some registers. */ /*----------------------------------------------------------------------- */ @@ -727,13 +729,13 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - addis r4,r0,0x8000 - addi r4,r4,0x0001 + lis r4,0x8000 + ori r4,r4,0x0001 mticcr r4 /* instruction cache */ isync - addis r4,r0,0x0000 - addi r4,r4,0x0000 + lis r4,0x0000 + ori r4,r4,0x0000 mtdccr r4 /* data cache */ #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) @@ -755,6 +757,70 @@ _start: #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) +/* test-only... (clean up later when NAND booting is supported) */ +#if defined(CONFIG_405EZ) + /******************************************************************** + * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 + *******************************************************************/ + /* + * We can map the OCM on the PLB3, so map it at + * CFG_OCM_DATA_ADDR + 0x8000 + */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l + ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */ + mtdcr ocmplb3cr1,r3 /* Set PLB Access */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr ocmplb3cr2,r3 /* Set PLB Access */ + isync + + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ + mtdcr ocmdscr1, r3 /* Set Data Side */ + mtdcr ocmiscr1, r3 /* Set Instruction Side */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr ocmdscr2, r3 /* Set Data Side */ + mtdcr ocmiscr2, r3 /* Set Instruction Side */ + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ + mtdcr ocmdsisdpc,r4 + + isync + +#if defined(CONFIG_NAND_SPL) + /* + * 405EZ can boot from NAND Flash. + * If we are booting the SPL (Pre-loader), copy code from + * the mapped 4K NAND Flash to the OCM + */ + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 + mtctr r4 + lis r2,CFG_NAND_BOOT_SPL_SRC@h + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l +spl_loop: + lwzu r4,4(r2) + stwu r4,4(r3) + bdnz spl_loop + + /* + * Jump to code in OCM Ram + */ + bl 00f +00: mflr r10 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l + sub r10,r10,r3 + addi r10,r10,28 + mtlr r10 + blr +start_ram: + sync + isync +#endif +#else +/* ...test-only */ /******************************************************************** * Setup OCM - On Chip Memory *******************************************************************/ @@ -774,6 +840,7 @@ _start: addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 isync +#endif /* CONFIG_405EZ */ #endif /*----------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index ab852c525cf..c71a6a9d85a 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -76,7 +76,7 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) +#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX) #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) #else @@ -1601,7 +1601,7 @@ int usb_lowlevel_init(void) gohci.irq = -1; #if defined(CONFIG_440EP) gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); -#elif defined(CONFIG_440EPX) +#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); #endif @@ -1625,8 +1625,10 @@ int usb_lowlevel_init(void) ohci_inited = 1; urb_finished = 1; +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* init the device driver */ usb_dev_init(); +#endif return 0; } diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 685d48bcf64..bddf9e5daa9 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -231,6 +231,47 @@ #else /* !defined(CONFIG_440) */ +#if defined(CONFIG_405EZ) +#define VECNUM_D0 0 /* DMA channel 0 */ +#define VECNUM_D1 1 /* DMA channel 1 */ +#define VECNUM_D2 2 /* DMA channel 2 */ +#define VECNUM_D3 3 /* DMA channel 3 */ +#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ +#define VECNUM_U0 5 /* UART0 */ +#define VECNUM_U1 6 /* UART1 */ +#define VECNUM_CAN0 7 /* CAN 0 */ +#define VECNUM_CAN1 8 /* CAN 1 */ +#define VECNUM_SPI 9 /* SPI */ +#define VECNUM_IIC0 10 /* I2C */ +#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ +#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ +#define VECNUM_USBH1 13 /* USB Host 1 */ +#define VECNUM_USBH2 14 /* USB Host 2 */ +#define VECNUM_USBDEV 15 /* USB Device */ +#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ +#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ + +#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ +#define VECNUM_MS 18 /* MAL_SERR_INT */ +#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ +#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ + +#define VECNUM_MTE 19 /* MAL TXEOB */ +#define VECNUM_MTE1 20 /* MAL TXEOB1 */ +#define VECNUM_MRE 21 /* MAL RXEOB */ +#define VECNUM_NAND 22 /* NAND Flash controller */ +#define VECNUM_ADC 23 /* ADC */ +#define VECNUM_DAC 24 /* DAC */ +#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ +#define VECNUM_RESERVED0 26 /* Reserved */ +#define VECNUM_EIR0 27 /* External interrupt 0 */ +#define VECNUM_EIR1 28 /* External interrupt 1 */ +#define VECNUM_EIR2 29 /* External interrupt 2 */ +#define VECNUM_EIR3 30 /* External interrupt 3 */ +#define VECNUM_EIR4 31 /* External interrupt 4 */ + +#else /* !CONFIG_405EZ */ + #define VECNUM_U0 0 /* UART0 */ #define VECNUM_U1 1 /* UART1 */ #define VECNUM_D0 5 /* DMA channel 0 */ @@ -251,6 +292,7 @@ #define VECNUM_EIR4 29 /* External interrupt 4 */ #define VECNUM_EIR5 30 /* External interrupt 5 */ #define VECNUM_EIR6 31 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ #endif /* defined(CONFIG_440) */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index ad9fd49ad43..058596275f4 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -298,6 +298,10 @@ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ @@ -529,6 +533,10 @@ #define SPRG1 SPRN_SPRG1 #define SPRG2 SPRN_SPRG2 #define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ #define SVR SPRN_SVR /* System Version Register */ @@ -731,6 +739,7 @@ #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 30b44e3d228..464f6b5756e 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -83,6 +83,7 @@ typedef struct bd_info { defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ @@ -107,7 +108,8 @@ typedef struct bd_info { unsigned char bi_enet3addr[6]; #endif -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned int bi_opbfreq; /* OPB clock in Hz */ diff --git a/include/ppc405.h b/include/ppc405.h index a49912cabb9..08f10d27b2a 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -117,6 +117,48 @@ /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ +#if defined(CONFIG_405EZ) +#define UIC_DMA0 0x80000000 /* DMA chan. 0 */ +#define UIC_DMA1 0x40000000 /* DMA chan. 1 */ +#define UIC_DMA2 0x20000000 /* DMA chan. 2 */ +#define UIC_DMA3 0x10000000 /* DMA chan. 3 */ +#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ +#define UIC_UART0 0x04000000 /* UART 0 */ +#define UIC_UART1 0x02000000 /* UART 1 */ +#define UIC_CAN0 0x01000000 /* CAN 0 */ +#define UIC_CAN1 0x00800000 /* CAN 1 */ +#define UIC_SPI 0x00400000 /* SPI */ +#define UIC_IIC 0x00200000 /* IIC */ +#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ +#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ +#define UIC_USBH1 0x00040000 /* USB Host 1 */ +#define UIC_USBH2 0x00020000 /* USB Host 2 */ +#define UIC_USBDEV 0x00010000 /* USB Device */ +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ +#define UIC_ENET1 0x00008000 /* dummy define */ +#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ + +#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ +#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ +#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ + +#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ +#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ +#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ +#define UIC_NAND 0x00000200 /* NAND Flash controller */ +#define UIC_ADC 0x00000100 /* ADC */ +#define UIC_DAC 0x00000080 /* DAC */ +#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ +#define UIC_RESERVED0 0x00000020 /* Reserved */ +#define UIC_EXT0 0x00000010 /* External interrupt 0 */ +#define UIC_EXT1 0x00000008 /* External interrupt 1 */ +#define UIC_EXT2 0x00000004 /* External interrupt 2 */ +#define UIC_EXT3 0x00000002 /* External interrupt 3 */ +#define UIC_EXT4 0x00000001 /* External interrupt 4 */ + +#else /* !defined(CONFIG_405EZ) */ + #define UIC_UART0 0x80000000 /* UART 0 */ #define UIC_UART1 0x40000000 /* UART 1 */ #define UIC_IIC 0x20000000 /* IIC */ @@ -144,6 +186,7 @@ #define UIC_EXT4 0x00000004 /* External interrupt 4 */ #define UIC_EXT5 0x00000002 /* External interrupt 5 */ #define UIC_EXT6 0x00000001 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ /****************************************************************************** * SDRAM Controller @@ -496,6 +539,325 @@ */ #define VCO_MIN 500 #define VCO_MAX 1000 +#elif defined(CONFIG_405EZ) +/****************************************************************************** + * SDR Registers + ******************************************************************************/ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ +#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ + +#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) +#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) + +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 + +#define SDR_NAND0_NDEN 0x80000000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0C +#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */ +#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */ + +/* CPR Registers */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ + +/* + * Macro for accessing the indirect CPR register + */ +#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data) +#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd) + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#if 0 /* Deprecated */ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#endif /* #if 0 */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** * Control @@ -578,6 +940,121 @@ /****************************************************************************** * Memory Access Layer ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ + +#else /* !defined(CONFIG_405EZ) */ + #define MAL_DCR_BASE 0x180 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ @@ -598,6 +1075,7 @@ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#endif /* defined(CONFIG_405EZ) */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -635,15 +1113,76 @@ /****************************************************************************** * On Chip Memory ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define OCM_DCR_BASE 0x020 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#else #define OCM_DCR_BASE 0x018 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#endif /* CONFIG_405EZ */ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ +#if defined(CONFIG_405EZ) +/* Only the 405EZ has 2 GPIOs */ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#define GPIO1_BASE 0xEF600800 +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#else /* !405EZ */ + #define GPIO_BASE 0xEF600700 #define GPIO0_OR (GPIO_BASE+0x0) #define GPIO0_TCR (GPIO_BASE+0x4) @@ -660,6 +1199,7 @@ #define GPIO0_ISR2H (GPIO_BASE+0x38) #define GPIO0_ISR2L (GPIO_BASE+0x3C) +#endif /* CONFIG_405EZ */ /* * Macro for accessing the indirect EBC register diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 43c5ca451e0..3d8ca090600 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -130,13 +130,13 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440GX) -#define EMAC_NUM_DEV 4 +#define EMAC_NUM_DEV 4 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ defined(CONFIG_NET_MULTI) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) -#define EMAC_NUM_DEV 2 +#define EMAC_NUM_DEV 2 #else -#define EMAC_NUM_DEV 1 +#define EMAC_NUM_DEV 1 #endif #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ @@ -153,16 +153,16 @@ typedef struct emac_4xx_hw_st { /*ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) #else -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) #endif -#define ZMII_FER (ZMII_BASE) -#define ZMII_SSR (ZMII_BASE + 4) -#define ZMII_SMIISR (ZMII_BASE + 8) +#define ZMII_FER (ZMII_BASE) +#define ZMII_SSR (ZMII_BASE + 4) +#define ZMII_SMIISR (ZMII_BASE + 8) -#define ZMII_RMII 0x22000000 -#define ZMII_MDI0 0x80000000 +#define ZMII_RMII 0x22000000 +#define ZMII_MDI0 0x80000000 /* ZMII FER Register Bit Definitions */ #define ZMII_FER_DIS (0x0) @@ -299,49 +299,41 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) #else -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) #endif #else -#define EMAC_BASE 0xEF600800 +#if defined(CONFIG_405EZ) +#define EMAC_BASE 0xEF600900 +#else +#define EMAC_BASE 0xEF600800 +#endif #endif -#define EMAC_M0 (EMAC_BASE) -#define EMAC_M1 (EMAC_BASE + 4) -#define EMAC_TXM0 (EMAC_BASE + 8) -#define EMAC_TXM1 (EMAC_BASE + 12) -#define EMAC_RXM (EMAC_BASE + 16) -#define EMAC_ISR (EMAC_BASE + 20) -#define EMAC_IER (EMAC_BASE + 24) -#define EMAC_IAH (EMAC_BASE + 28) -#define EMAC_IAL (EMAC_BASE + 32) -#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36) -#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40) +#define EMAC_M0 (EMAC_BASE) +#define EMAC_M1 (EMAC_BASE + 4) +#define EMAC_TXM0 (EMAC_BASE + 8) +#define EMAC_TXM1 (EMAC_BASE + 12) +#define EMAC_RXM (EMAC_BASE + 16) +#define EMAC_ISR (EMAC_BASE + 20) +#define EMAC_IER (EMAC_BASE + 24) +#define EMAC_IAH (EMAC_BASE + 28) +#define EMAC_IAL (EMAC_BASE + 32) #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) -#define EMAC_IND_HASH_1 (EMAC_BASE + 48) -#define EMAC_IND_HASH_2 (EMAC_BASE + 52) -#define EMAC_IND_HASH_3 (EMAC_BASE + 56) -#define EMAC_IND_HASH_4 (EMAC_BASE + 60) -#define EMAC_GRP_HASH_1 (EMAC_BASE + 64) -#define EMAC_GRP_HASH_2 (EMAC_BASE + 68) -#define EMAC_GRP_HASH_3 (EMAC_BASE + 72) -#define EMAC_GRP_HASH_4 (EMAC_BASE + 76) -#define EMAC_LST_SRC_LOW (EMAC_BASE + 80) -#define EMAC_LST_SRC_HI (EMAC_BASE + 84) #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) -#define EMAC_STACR (EMAC_BASE + 92) -#define EMAC_TRTR (EMAC_BASE + 96) -#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) +#define EMAC_STACR (EMAC_BASE + 92) +#define EMAC_TRTR (EMAC_BASE + 96) +#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) /* bit definitions */ /* MODE REG 0 */ -#define EMAC_M0_RXI (0x80000000) -#define EMAC_M0_TXI (0x40000000) -#define EMAC_M0_SRST (0x20000000) -#define EMAC_M0_TXE (0x10000000) -#define EMAC_M0_RXE (0x08000000) -#define EMAC_M0_WKE (0x04000000) +#define EMAC_M0_RXI (0x80000000) +#define EMAC_M0_TXI (0x40000000) +#define EMAC_M0_SRST (0x20000000) +#define EMAC_M0_TXE (0x10000000) +#define EMAC_M0_RXE (0x08000000) +#define EMAC_M0_WKE (0x04000000) /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ @@ -351,23 +343,23 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) #define EMAC_M1_VLE (0x20000000) -#define EMAC_M1_EIFC (0x10000000) -#define EMAC_M1_APP (0x08000000) -#define EMAC_M1_RSVD (0x06000000) -#define EMAC_M1_IST (0x01000000) -#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS (0x00400000) -#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_2K (0x00100000) -#define EMAC_M1_RFS_1K (0x00080000) -#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ -#define EMAC_M1_TX_FIFO_8K (0x00040000) -#define EMAC_M1_TX_FIFO_4K (0x00030000) +#define EMAC_M1_EIFC (0x10000000) +#define EMAC_M1_APP (0x08000000) +#define EMAC_M1_RSVD (0x06000000) +#define EMAC_M1_IST (0x01000000) +#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS (0x00400000) +#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K (0x00100000) +#define EMAC_M1_RFS_1K (0x00080000) +#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_8K (0x00040000) +#define EMAC_M1_TX_FIFO_4K (0x00030000) #define EMAC_M1_TX_FIFO_2K (0x00020000) -#define EMAC_M1_TX_FIFO_1K (0x00010000) -#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ +#define EMAC_M1_TX_FIFO_1K (0x00010000) +#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ #define EMAC_M1_MWSW (0x00007000) #define EMAC_M1_JUMBO_ENABLE (0x00000800) #define EMAC_M1_IPPA (0x000007c0) @@ -378,34 +370,34 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_RSVD1 (0x00000007) #else /* defined(CONFIG_440GX) */ /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ -#define EMAC_M1_FDE 0x80000000 -#define EMAC_M1_ILE 0x40000000 -#define EMAC_M1_VLE 0x20000000 -#define EMAC_M1_EIFC 0x10000000 -#define EMAC_M1_APP 0x08000000 -#define EMAC_M1_AEMI 0x02000000 -#define EMAC_M1_IST 0x01000000 -#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS 0x00400000 -#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ -#define EMAC_M1_RFS_2K 0x00200000 -#define EMAC_M1_RFS_1K 0x00100000 -#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ -#define EMAC_M1_TX_FIFO_1K 0x00040000 -#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ -#define EMAC_M1_TR0_MULTI 0x00008000 -#define EMAC_M1_TR1_DEPEND 0x00004000 -#define EMAC_M1_TR1_MULTI 0x00002000 +#define EMAC_M1_FDE 0x80000000 +#define EMAC_M1_ILE 0x40000000 +#define EMAC_M1_VLE 0x20000000 +#define EMAC_M1_EIFC 0x10000000 +#define EMAC_M1_APP 0x08000000 +#define EMAC_M1_AEMI 0x02000000 +#define EMAC_M1_IST 0x01000000 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS 0x00400000 +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K 0x00200000 +#define EMAC_M1_RFS_1K 0x00100000 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_1K 0x00040000 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ +#define EMAC_M1_TR0_MULTI 0x00008000 +#define EMAC_M1_TR1_DEPEND 0x00004000 +#define EMAC_M1_TR1_MULTI 0x00002000 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define EMAC_M1_JUMBO_ENABLE 0x00001000 +#define EMAC_M1_JUMBO_ENABLE 0x00001000 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #endif /* defined(CONFIG_440GX) */ /* Transmit Mode Register 0 */ -#define EMAC_TXM0_GNP0 (0x80000000) -#define EMAC_TXM0_GNP1 (0x40000000) -#define EMAC_TXM0_GNPD (0x20000000) -#define EMAC_TXM0_FC (0x10000000) +#define EMAC_TXM0_GNP0 (0x80000000) +#define EMAC_TXM0_GNP1 (0x40000000) +#define EMAC_TXM0_GNPD (0x20000000) +#define EMAC_TXM0_FC (0x10000000) /* Receive Mode Register */ #define EMAC_RMR_SP (0x80000000) @@ -427,39 +419,38 @@ typedef struct emac_4xx_hw_st { #define EMAC_ISR_PP (0x01000000) #define EMAC_ISR_BP (0x00800000) #define EMAC_ISR_RP (0x00400000) -#define EMAC_ISR_SE (0x00200000) -#define EMAC_ISR_SYE (0x00100000) -#define EMAC_ISR_BFCS (0x00080000) -#define EMAC_ISR_PTLE (0x00040000) -#define EMAC_ISR_ORE (0x00020000) -#define EMAC_ISR_IRE (0x00010000) -#define EMAC_ISR_DBDM (0x00000200) -#define EMAC_ISR_DB0 (0x00000100) -#define EMAC_ISR_SE0 (0x00000080) -#define EMAC_ISR_TE0 (0x00000040) -#define EMAC_ISR_DB1 (0x00000020) -#define EMAC_ISR_SE1 (0x00000010) -#define EMAC_ISR_TE1 (0x00000008) -#define EMAC_ISR_MOS (0x00000002) -#define EMAC_ISR_MOF (0x00000001) - +#define EMAC_ISR_SE (0x00200000) +#define EMAC_ISR_SYE (0x00100000) +#define EMAC_ISR_BFCS (0x00080000) +#define EMAC_ISR_PTLE (0x00040000) +#define EMAC_ISR_ORE (0x00020000) +#define EMAC_ISR_IRE (0x00010000) +#define EMAC_ISR_DBDM (0x00000200) +#define EMAC_ISR_DB0 (0x00000100) +#define EMAC_ISR_SE0 (0x00000080) +#define EMAC_ISR_TE0 (0x00000040) +#define EMAC_ISR_DB1 (0x00000020) +#define EMAC_ISR_SE1 (0x00000010) +#define EMAC_ISR_TE1 (0x00000008) +#define EMAC_ISR_MOS (0x00000002) +#define EMAC_ISR_MOF (0x00000001) /* STA CONTROL REG */ -#define EMAC_STACR_OC (0x00008000) -#define EMAC_STACR_PHYE (0x00004000) +#define EMAC_STACR_OC (0x00008000) +#define EMAC_STACR_PHYE (0x00004000) #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ -#define EMAC_STACR_INDIRECT_MODE (0x00002000) -#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ -#define EMAC_STACR_READ (0x00001000) /* $BUC */ -#define EMAC_STACR_OP_MASK (0x00001800) -#define EMAC_STACR_MDIO_ADDR (0x00000000) -#define EMAC_STACR_MDIO_WRITE (0x00000800) -#define EMAC_STACR_MDIO_READ (0x00001800) -#define EMAC_STACR_MDIO_READ_INC (0x00001000) +#define EMAC_STACR_INDIRECT_MODE (0x00002000) +#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ +#define EMAC_STACR_READ (0x00001000) /* $BUC */ +#define EMAC_STACR_OP_MASK (0x00001800) +#define EMAC_STACR_MDIO_ADDR (0x00000000) +#define EMAC_STACR_MDIO_WRITE (0x00000800) +#define EMAC_STACR_MDIO_READ (0x00001800) +#define EMAC_STACR_MDIO_READ_INC (0x00001000) #else -#define EMAC_STACR_WRITE (0x00002000) -#define EMAC_STACR_READ (0x00001000) +#define EMAC_STACR_WRITE (0x00002000) +#define EMAC_STACR_READ (0x00001000) #endif #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ @@ -467,9 +458,9 @@ typedef struct emac_4xx_hw_st { #define EMAC_STACR_CLK_100MHZ (0x00000C00) /* Transmit Request Threshold Register */ -#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ -#define EMAC_TRTR_192 (0x10000000) -#define EMAC_TRTR_128 (0x01000000) +#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ +#define EMAC_TRTR_192 (0x10000000) +#define EMAC_TRTR_128 (0x01000000) /* the follwing defines are for the MadMAL status and control registers. */ /* For bits 0..5 look at the mal.h file */ -- cgit v1.3.1 From 9964a4dd0d4ef5a037febaebf1aa494b1a72991c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 7 Dec 2006 10:35:55 -0600 Subject: Set Rev 2.x 86xx PIC in mixed mode. Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- cpu/mpc86xx/interrupts.c | 20 ++++++++++++++++++++ include/asm-ppc/immap_86xx.h | 2 ++ 2 files changed, 22 insertions(+) (limited to 'include/asm-ppc') diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 1df6cdc5b93..49820bbd811 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -80,6 +80,26 @@ int interrupt_init(void) { int ret; + /* + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to + * implement PEX10 errata. As INT is active high, it + * will cause core to take 0x500 interrupt. + * + * Due to the PIC's default pass through mode, as soon + * as interrupts are enabled (MSR[EE] = 1), an interrupt + * will be taken and u-boot will hang. This is due to a + * hardware change (per an errata fix) on new revisions + * of the board with Rev 2.x parts. + * + * Setting the PIC to mixed mode prevents the hang. + */ + if ((get_svr() & 0xf0) == 0x20) { + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; + } + /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index a5552c48ee9..0e3fc3403d5 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -721,6 +721,8 @@ typedef struct ccsr_pic { uint frr; /* 0x41000 - Feature Reporting Register */ char res10[28]; uint gcr; /* 0x41020 - Global Configuration Register */ +#define MPC86xx_PICGCR_RST 0x80000000 +#define MPC86xx_PICGCR_MODE 0x20000000 char res11[92]; uint vir; /* 0x41080 - Vendor Identification Register */ char res12[12]; -- cgit v1.3.1 From 0d974d5297349504a2ddfa09314be573b5df320a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 24 Mar 2007 15:57:09 +0100 Subject: [PATCH] Add 4xx GPIO functions This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese --- board/amcc/bamboo/bamboo.c | 1 + board/amcc/bamboo/bamboo.h | 10 ---- board/amcc/katmai/katmai.c | 1 + cpu/ppc4xx/Makefile | 2 +- cpu/ppc4xx/cpu_init.c | 115 +-------------------------------------------- include/asm-ppc/gpio.h | 56 ++++++++++++++++++++++ include/ppc440.h | 23 --------- 7 files changed, 61 insertions(+), 147 deletions(-) create mode 100644 include/asm-ppc/gpio.h (limited to 'include/asm-ppc') diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index c93ba6e3ca1..b5bb1458080 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include "bamboo.h" diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 1ce6366da4a..447486297a8 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -264,19 +264,9 @@ #define TRUE 1 #define FALSE 0 -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - #define GPIO0 0 #define GPIO1 1 - /*#define MAX_SELECTION_NB CORE_NB */ #define MAX_CORE_SELECT_NB 22 diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index fbf1a98ab3d..286bdc1f21d 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "../cpu/ppc4xx/440spe_pcie.h" diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 96f0f62eb60..4068b53208f 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -29,7 +29,7 @@ START = start.o resetvec.o kgdb.o SOBJS = dcr.o COBJS = 405gp_pci.o 4xx_enet.o \ bedbug_405.o commproc.o \ - cpu.o cpu_init.o i2c.o interrupts.o \ + cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ miiphy.o ndfc.o sdram.o serial.o \ 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \ tlb.o traps.o usb_ohci.o usbdev.o \ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 9d1cd1343d2..66e86372603 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #if defined(CONFIG_405GP) || defined(CONFIG_405EP) @@ -98,118 +99,6 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif /* CFG_INIT_DCACHE_CS */ -#if defined(CFG_440_GPIO_TABLE) -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; - -void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX]) -{ - unsigned char i=0, j=0, reg_offset = 0, gpio_core; - unsigned long gpio_reg, gpio_core_add; - - for (gpio_core=0; gpio_core> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - - if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) || - ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { - - switch ((*gpio_tab)[gpio_core][i].alt_nb) { - case GPIO_SEL: - if (gpio_core == GPIO0) { - gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j)); - out32(GPIO0_TCR, gpio_reg); - } - - if (gpio_core == GPIO1) { - gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j)); - out32(GPIO1_TCR, gpio_reg); - } - - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT1: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - } - } -} -#endif /* CFG_440_GPIO_TABLE */ - /* * Breath some life into the CPU... * @@ -248,7 +137,7 @@ cpu_init_f (void) #endif /* CONFIG_405EP */ #if defined(CFG_440_GPIO_TABLE) - set_chip_gpio_configuration(&gpio_tab); + gpio_set_chip_configuration(); #endif /* CFG_440_GPIO_TABLE */ /* diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h new file mode 100644 index 00000000000..114dc92db9e --- /dev/null +++ b/include/asm-ppc/gpio.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* 4xx PPC's have 2 GPIO controllers */ +#if defined(CONFIG_405EZ) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define GPIO_GROUP_MAX 2 +#else +#define GPIO_GROUP_MAX 1 +#endif + +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 +#define GPIO_ALT2_SEL 0x80000000 +#define GPIO_ALT3_SEL 0xc0000000 +#define GPIO_IN_SEL 0x40000000 +#define GPIO_MASK 0xc0000000 + +#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) + +#ifndef __ASSEMBLY__ +typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; +typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; +typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t; + +typedef struct { + unsigned long add; /* gpio core base address */ + gpio_driver_t in_out; /* Driver Setting */ + gpio_select_t alt_nb; /* Selected Alternate */ +} gpio_param_s; +#endif + +void gpio_config(int pin, int in_out, int gpio_alt, int out_val); +void gpio_write_bit(int pin, int val); +void gpio_set_chip_configuration(void); diff --git a/include/ppc440.h b/include/ppc440.h index 1c7f11c4885..d8272287c34 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3267,29 +3267,6 @@ #define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - -#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) - -#ifndef __ASSEMBLY__ - -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; - -typedef struct { unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ -} gpio_param_s; - -#endif /* __ASSEMBLY__ */ - /* * Macros for accessing the indirect EBC registers */ -- cgit v1.3.1 From 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Thu, 14 Dec 2006 14:14:55 +0800 Subject: u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang --- board/cds/mpc8548cds/init.S | 77 ++++++++++++++++++++++++----------------- board/cds/mpc8548cds/u-boot.lds | 1 + include/asm-ppc/mmu.h | 1 + include/configs/MPC8548CDS.h | 28 ++++++++++----- 4 files changed, 67 insertions(+), 40 deletions(-) (limited to 'include/asm-ppc') diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 978bda5e4dc..2c15debd488 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -64,8 +64,9 @@ tlb1_entry: /* * Number of TLB0 and TLB1 entries in the following table */ - .long 13 + .long (2f-1f)/16 +1: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* * TLB0 4K Non-cacheable, guarded @@ -134,7 +135,7 @@ tlb1_entry: /* * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * 0x80000000 256M PCI1 MEM */ .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) @@ -143,40 +144,37 @@ tlb1_entry: /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half + * 0x90000000 256M PCI2 MEM */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half + * TLB 3: 1GB Non-cacheable, guarded + * 0xa0000000 256M PEX MEM First half + * 0xb0000000 256M PEX MEM Second half + * 0xc0000000 256M Rapid IO MEM First half + * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half + * TLB 4: Reserved for future usage */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO + * 0xe200_0000 8M PCI1 IO + * 0xe280_0000 8M PCI2 IO + * 0xe300_0000 16M PEX IO */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) @@ -200,19 +198,22 @@ tlb1_entry: .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) - +2: entry_end /* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M + * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M + * 0xa000_0000 0xbfff_ffff PEX MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M + * 0xe300_0000 0xe3ff_ffff PEX IO 16M + * 0xf000_0000 0xf3ff_ffff SDRAM 64M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M @@ -229,27 +230,39 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) +#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR7 ((CFG_PEX_IO_BASE>>12) & 0xfffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .section .bootpg, "ax" .globl law_entry law_entry: entry_start - .long 6 + .long (4f-3f)/8 +3: .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7 + .long LAWBAR8,LAWAR8 +4: entry_end diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds index 2c8fe9603d9..c1f3495d759 100644 --- a/board/cds/mpc8548cds/u-boot.lds +++ b/board/cds/mpc8548cds/u-boot.lds @@ -69,6 +69,7 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) + drivers/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b226825ee20..67c2c571ed8 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_PEX 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7c4849fadfb..bfd316cb945 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -36,7 +36,7 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ -#undef CONFIG_PCI +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -344,18 +344,30 @@ extern unsigned long get_clock_freq(void); */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_BASE 0x90000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe2800000 +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_PEX_MEM_BASE 0xa0000000 +#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE +#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PEX_IO_BASE 0xe3000000 +#define CFG_PEX_IO_PHYS CFG_PEX_IO_BASE +#define CFG_PEX_IO_SIZE 0x1000000 /* 16M */ +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xC0000000 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #if defined(CONFIG_PCI) -- cgit v1.3.1 From 45cef612cc601d2d1c890fbbd7cdc9609a189a46 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 17:11:16 -0600 Subject: Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming --- board/cds/mpc8548cds/init.S | 2 +- include/asm-ppc/mmu.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include/asm-ppc') diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 2c15debd488..34ca711bde4 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -161,7 +161,7 @@ tlb1_entry: * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 67c2c571ed8..48fd9829506 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_16M 7 #define BOOKE_PAGESZ_64M 8 #define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 +#define BOOKE_PAGESZ_1G 10 +#define BOOKE_PAGESZ_4G 11 #if defined(CONFIG_MPC86xx) #define LAWBAR_BASE_ADDR 0x00FFFFFF -- cgit v1.3.1 From 81f481ca708ed6a56bf9c410e3191dbad581c565 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:24:28 -0500 Subject: Enable 8544 support * Add support to the Makefile * Add 8544 configuration support to the tsec driver * Add 8544 SVR numbers to processor.h Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- MAKEALL | 8 ++++---- Makefile | 3 +++ drivers/tsec.c | 6 +++++- drivers/tsec.h | 3 ++- include/asm-ppc/processor.h | 11 +++++++++-- 5 files changed, 23 insertions(+), 8 deletions(-) (limited to 'include/asm-ppc') diff --git a/MAKEALL b/MAKEALL index 0f0ec296f26..59aec2867f0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -142,10 +142,10 @@ LIST_83xx=" \ ######################################################################### LIST_85xx=" \ - MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \ - MPC8555CDS MPC8560ADS PM854 PM856 \ - sbc8540 sbc8560 stxgp3 TQM8540 \ - TQM8541 TQM8555 TQM8560 \ + MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \ + MPC8548CDS MPC8555CDS MPC8560ADS PM854 \ + PM856 sbc8540 sbc8560 stxgp3 \ + TQM8540 TQM8541 TQM8555 TQM8560 \ " ######################################################################### diff --git a/Makefile b/Makefile index 94cda54c731..d447a9610d4 100644 --- a/Makefile +++ b/Makefile @@ -1730,6 +1730,9 @@ MPC8560ADS_config: unconfig MPC8541CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds +MPC8544DS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale + MPC8548CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds diff --git a/drivers/tsec.c b/drivers/tsec.c index 3f11eb03b41..ed35f227c1b 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -66,7 +66,11 @@ struct tsec_info_struct { */ static struct tsec_info_struct tsec_info[] = { #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) +#if defined(CONFIG_MPC8544DS) + {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, +#else {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, +#endif #elif defined(CONFIG_MPC86XX_TSEC1) {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else diff --git a/drivers/tsec.h b/drivers/tsec.h index 422bc669229..7bf3dee2b68 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming @@ -65,6 +65,7 @@ #define ECNTRL_INIT_SETTINGS 0x00001000 #define ECNTRL_TBI_MODE 0x00000020 #define ECNTRL_R100 0x00000008 +#define ECNTRL_SGMII_MODE 0x00000002 #define miim_end -2 #define miim_read -1 diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 058596275f4..944cbe90c38 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -232,6 +232,9 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -415,10 +418,12 @@ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ @@ -840,6 +845,8 @@ #define SVR_8560 0x8070 #define SVR_8555 0x8079 #define SVR_8541 0x807A +#define SVR_8544 0x8034 +#define SVR_8544_E 0x803C #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 -- cgit v1.3.1 From 6743105988fc44d5b0d30388c790607835aae7a6 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:54:25 -0500 Subject: Add support for the 8568 MDS board This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming --- Makefile | 3 + board/mpc8568mds/Makefile | 58 +++++ board/mpc8568mds/bcsr.c | 49 ++++ board/mpc8568mds/bcsr.h | 99 +++++++++ board/mpc8568mds/config.mk | 30 +++ board/mpc8568mds/ft_board.c | 45 ++++ board/mpc8568mds/init.S | 258 +++++++++++++++++++++ board/mpc8568mds/mpc8568mds.c | 288 ++++++++++++++++++++++++ board/mpc8568mds/u-boot.lds | 152 +++++++++++++ cpu/mpc85xx/cpu.c | 7 + cpu/mpc85xx/cpu_init.c | 2 - include/asm-ppc/processor.h | 1 + include/configs/MPC8568MDS.h | 505 ++++++++++++++++++++++++++++++++++++++++++ 13 files changed, 1495 insertions(+), 2 deletions(-) create mode 100644 board/mpc8568mds/Makefile create mode 100644 board/mpc8568mds/bcsr.c create mode 100644 board/mpc8568mds/bcsr.h create mode 100644 board/mpc8568mds/config.mk create mode 100644 board/mpc8568mds/ft_board.c create mode 100644 board/mpc8568mds/init.S create mode 100644 board/mpc8568mds/mpc8568mds.c create mode 100644 board/mpc8568mds/u-boot.lds create mode 100644 include/configs/MPC8568MDS.h (limited to 'include/asm-ppc') diff --git a/Makefile b/Makefile index d447a9610d4..a9d56ecb20e 100644 --- a/Makefile +++ b/Makefile @@ -1739,6 +1739,9 @@ MPC8548CDS_config: unconfig MPC8555CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds +MPC8568MDS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds + PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/board/mpc8568mds/Makefile b/board/mpc8568mds/Makefile new file mode 100644 index 00000000000..a799aa4cc58 --- /dev/null +++ b/board/mpc8568mds/Makefile @@ -0,0 +1,58 @@ +# +# Copyright 2004-2007 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o \ + bcsr.o \ + ft_board.o + +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c new file mode 100644 index 00000000000..2e2e8cd18fa --- /dev/null +++ b/board/mpc8568mds/bcsr.c @@ -0,0 +1,49 @@ +/* + * Copyright 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "bcsr.h" + +void enable_8568mds_duart() +{ + volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060); + volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070); + volatile u8 *bcsr = (u8 *)(CFG_BCSR); + + *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ + *devices = 0; /* Enable all peripheral devices */ + bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ +} + +void enable_8568mds_flash_write() +{ + volatile u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[9] |= 0x01; +} + +void disable_8568mds_flash_write() +{ + volatile u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[9] &= ~(0x01); +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h new file mode 100644 index 00000000000..8d4cb2f1412 --- /dev/null +++ b/board/mpc8568mds/bcsr.h @@ -0,0 +1,99 @@ +/* + * Copyright 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include + +/* BCSR Bit definitions + * BCSR 0 * + 0:3 ccb sys pll + 4:6 cfg core pll + 7 cfg boot seq + + * BCSR 1 * + 0:2 cfg rom lock + 3:5 cfg host agent + 6 PCI IO + 7 cfg RIO size + + * BCSR 2 * + 0:4 QE PLL + 5 QE clock + 6 cfg PCI arbiter + + * BCSR 3 * + 0 TSEC1 reduce + 1 TSEC2 reduce + 2:3 TSEC1 protocol + 4:5 TSEC2 protocol + 6 PHY1 slave + 7 PHY2 slave + + * BCSR 4 * + 4 clock enable + 5 boot EPROM + 6 GETH transactive reset + 7 BRD write potect + + * BCSR 5 * + 1:3 Leds 1-3 + 4 UPC1 enable + 5 UPC2 enable + 6 UPC2 pos + 7 RS232 enable + + * BCSR 6 * + 0 CFG ver 0 + 1 CFG ver 1 + 6 Register config led + 7 Power on reset + + * BCSR 7 * + 2 board host mode indication + 5 enable TSEC1 PHY + 6 enable TSEC2 PHY + + * BCSR 8 * + 0 UCC GETH1 enable + 1 UCC GMII enable + 3 UCC TBI enable + 5 UCC MII enable + 7 Real time clock reset + + * BCSR 9 * + 0 UCC2 GETH enable + 1 UCC2 GMII enable + 3 UCC2 TBI enable + 5 UCC2 MII enable + 6 Ready only - indicate flash ready after burning + 7 Flash write protect +*/ + +/*BCSR Utils functions*/ + +void enable_8568mds_duart(void); +void enable_8568mds_flash_write(void); +void disable_8568mds_flash_write(void); + +#endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/config.mk b/board/mpc8568mds/config.mk new file mode 100644 index 00000000000..021522cafc4 --- /dev/null +++ b/board/mpc8568mds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8568mds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8568=1 diff --git a/board/mpc8568mds/ft_board.c b/board/mpc8568mds/ft_board.c new file mode 100644 index 00000000000..36815ccfbb5 --- /dev/null +++ b/board/mpc8568mds/ft_board.c @@ -0,0 +1,45 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +extern void ft_cpu_setup(void *blob, bd_t *bd); + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */ diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S new file mode 100644 index 00000000000..0d879821e33 --- /dev/null +++ b/board/mpc8568mds/init.S @@ -0,0 +1,258 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long (2f-1f)/16 + +1: +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + /* TLB 1 Initializations */ + /* + * TLBe 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH (upper half) + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLBe 1: 16M Non-cacheable, guarded + * 0xfe000000 16M FLASH (lower half) + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLBe 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLBe 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCIe Mem + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLBe 4: Reserved for future usage + */ + + /* + * TLBe 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 8M PCI1 IO + * 0xe280_0000 8M PCIe IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLBe 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLBe 7: 256K Non-cacheable, guarded + * 0xf8000000 32K BCSR + * 0xf8008000 32K PIB (CS4) + * 0xf8010000 32K PIB (CS5) + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1) + +2: + entry_end + +/* + * LAW(Local Access Window) configuration: + * + *0) 0x0000_0000 0x7fff_ffff DDR 2G + *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB + *2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB + *5) 0xc000_0000 0xdfff_ffff SRIO 256MB + *-) 0xe000_0000 0xe00f_ffff CCSR 1M + *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M + *4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M + *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB + *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB + *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB + *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB + *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB + * + *Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) + +#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + + +#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ +#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long (4f-3f)/8 +3: + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6 +4: + entry_end diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c new file mode 100644 index 00000000000..9c7960d47e7 --- /dev/null +++ b/board/mpc8568mds/mpc8568mds.c @@ -0,0 +1,288 @@ +/* + * Copyright 2007 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "bcsr.h" + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + /* + * Initialize local bus. + */ + local_bus_init (); + + enable_8568mds_duart(); + enable_8568mds_flash_write(); + + return 0; +} + +int checkboard (void) +{ + printf ("Board: 8568 MDS\n"); + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * MPC8568 uses "new" 15-16 style addressing. + */ + lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8568mds_config_table[] = { + { + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, + {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + }, + {} +}; +#endif + +static struct pci_controller hose[] = { +#ifndef CONFIG_PCI_PNP + { config_table: pci_mpc8568mds_config_table,}, +#endif +#ifdef CONFIG_MPC85XX_PCI2 + {}, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/mpc8568mds/u-boot.lds b/board/mpc8568mds/u-boot.lds new file mode 100644 index 00000000000..71099f6f134 --- /dev/null +++ b/board/mpc8568mds/u-boot.lds @@ -0,0 +1,152 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ + +SECTIONS +{ + /* ELIOR - From RAM: From FLASH: 0xFFFFFFFC*/ + .resetvec 0xFFFFFFFC: + { + *(.resetvec) + } = 0xffff + + /*(ELIOR - From RAM: From FLASH: 0xFFFFF000*/ + .bootpg 0xFFFFF000: + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8568mds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8568mds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index d5102dfddfd..63176d2841d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -76,6 +76,9 @@ int checkcpu (void) case SVR_8544_E: puts("8544_E"); break; + case SVR_8568_E: + puts("8568_E"); + break; default: puts("Unknown"); break; @@ -265,6 +268,10 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); + p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); if (p != NULL) *p = cpu_to_be32(clock); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9f4d36c1ab4..9517146ed23 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -143,12 +143,10 @@ void cpu_init_f (void) memctl->br1 = CFG_BR1_PRELIM; #endif -#if !defined(CONFIG_MPC85xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif -#endif #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 944cbe90c38..e9361c5174b 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -850,6 +850,7 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 +#define SVR_8568_E 0x807D /* I am just adding a single entry for 8260 boards. I think we may be diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h new file mode 100644 index 00000000000..66293c5221e --- /dev/null +++ b/include/configs/MPC8568MDS.h @@ -0,0 +1,505 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8568mds board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ +#define CONFIG_MPC8568 1 /* MPC8568 specific */ +#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ + +#undef CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ + +/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the MDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif /*Replace a call to get_clock_freq (after it is implemented)*/ +#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ +#define CFG_BCSR_BASE 0xf8000000 + +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ + +/*Chip select 0 - Flash*/ +#define CFG_BR0_PRELIM 0xfe001001 +#define CFG_OR0_PRELIM 0xfe006ff7 + +/*Chip slelect 1 - BCSR*/ +#define CFG_BR1_PRELIM 0xf8000801 +#define CFG_OR1_PRELIM 0xffffe9f7 + +//#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +/* + * SDRAM on the LocalBus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + + +/*Chip select 2 - SDRAM*/ +#define CFG_BR2_PRELIM 0xf0001861 +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * The bcsr registers are connected to CS3 on MDS. + * The new memory map places bcsr at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ +#define CFG_BCSR (0xf8000000) + +/*Chip slelect 4 - PIB*/ +#define CFG_BR4_PRELIM 0xf8008801 +#define CFG_OR4_PRELIM 0xffffe9f7 + +/*Chip select 5 - PIB*/ +#define CFG_BR5_PRELIM 0xf8010801 +#define CFG_OR5_PRELIM 0xffff69f7 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser*/ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8568@0" +#define OF_SOC "soc8568@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory Addresses are mapped 1-1. I/O is mapped from 0 + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_PEX_MEM_BASE 0xa0000000 +#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE +#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PEX_IO_BASE 0x00000000 +#define CFG_PEX_IO_PHYS 0xe2800000 +#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_SRIO_MEM_BASE 0xc0000000 + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" +#undef CONFIG_MPC85XX_TSEC3 +#undef CONFIG_MPC85XX_TSEC4 +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + + +#define CONFIG_NFSBOOTCOMMAND \ + "run nfsargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "run ramargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2 Mon Sep 17 00:00:00 2001 From: Grzegorz Wianecki Date: Sun, 29 Apr 2007 14:01:54 +0200 Subject: [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki Signed-off-by: Bartlomiej Sieka Signed-off-by: Grant Likely --- cpu/mpc5xxx/cpu.c | 12 ++++++++---- include/asm-ppc/processor.h | 8 ++++++-- 2 files changed, 14 insertions(+), 6 deletions(-) (limited to 'include/asm-ppc') diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 813aa7935d1..73b166d999e 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -53,12 +53,16 @@ int checkcpu (void) #else svr = get_svr(); pvr = get_pvr(); - switch (SVR_VER (svr)) { - case SVR_MPC5200: - printf ("MPC5200"); + + switch (pvr) { + case PVR_5200: + printf("MPC5200"); + break; + case PVR_5200B: + printf("MPC5200B"); break; default: - printf ("MPC52?? (SVR %08x)", svr); + printf("Unknown MPC5xxx"); break; } diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e9361c5174b..5efc3ee2ca7 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -706,8 +706,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -818,6 +816,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register -- cgit v1.3.1