From 96e5fc0e6a1861d0fea4efa3cd376df95a5b1b89 Mon Sep 17 00:00:00 2001 From: Feng Kan Date: Tue, 8 Jul 2008 22:48:07 -0700 Subject: ppc4xx: Add initial 460SX reference board (redwood) config file and defines. Signed-off-by: Feng Kan Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 3 ++- include/asm-ppc/processor.h | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index e151f0c1139..cdccd8fe6f8 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -282,7 +282,8 @@ * Memory Bank 0-7 configuration */ #if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 10fd478baba..6e134c3d1e0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -810,6 +810,10 @@ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 -- cgit v1.3.1 From 5b457d00730d4aa0c6450d21a9104723e606fb98 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Wed, 9 Jul 2008 11:55:46 -0700 Subject: PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r) While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in the 405EX(r), SDRAM_MCSTAT has a different DCR value. Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF which causes SDRAM initialization to periodically fail since it can prematurely indicate SDRAM ready status. Signed-off-by: Grant Erickson Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index cdccd8fe6f8..59f1c30839c 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -354,7 +354,11 @@ /* * Memory controller registers */ +#ifndef CONFIG_405EX #define SDRAM_MCSTAT 0x14 /* memory controller status */ +#else +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#endif #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -- cgit v1.3.1 From ad7382d828982e9c1bafc4313ef1b666f6145f58 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Wed, 9 Jul 2008 16:31:59 -0700 Subject: ppc4xx: Add AMCC/IBM DDR2 SDRAM ECC Field Mnemonics Add additional DDR2 SDRAM memory controller DCR mneomnics, condition revision ID DCR based on 405EX, and add field mnemonics for bus error status and ECC error status registers. Signed-off-by: Grant Erickson Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 52 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 59f1c30839c..d01e07e8baa 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -354,6 +354,14 @@ /* * Memory controller registers */ +#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ +#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ +#define SDRAM_BEARL 0x02 /* PLB bus error address low */ +#define SDRAM_BEARH 0x03 /* PLB bus error address high */ +#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */ +#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ +#define SDRAM_PLBOPT 0x08 /* PLB slave options */ +#define SDRAM_PUABA 0x09 /* PLB upper address base */ #ifndef CONFIG_405EX #define SDRAM_MCSTAT 0x14 /* memory controller status */ #else @@ -403,9 +411,35 @@ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_ECCES SDRAM_ECCCR #define SDRAM_CID 0xA4 /* core ID */ +#ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ +#endif +#define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ +#ifdef CONFIG_405EX +#define SDRAM_RID 0xF8 /* revision ID */ +#endif + +/* + * Memory Controller Bus Error Status + */ +#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF) +#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF) +#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0) +#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1) +#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2) +#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3) +#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4) +#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5) +#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6) +#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7) +#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7) +#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0) +#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1) +#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0) +#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1) /* * Memory Controller Status @@ -688,6 +722,24 @@ #define SDRAM_SDTR3_RFC_MASK 0x0000003F #define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0) +/* + * ECC Error Status + */ +#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF) +#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF) +#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) +#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3) +#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0) +#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2) +#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1) +#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2) +#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3) +#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1) +#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1) +#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3) +#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1) +#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1) + /* * Memory Bank 0-1 configuration */ -- cgit v1.3.1 From 2e2050842e731c823ce8d41fb0c15579eb70ced9 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Wed, 9 Jul 2008 16:46:35 -0700 Subject: ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM controller registers (MODT and INITPLR) used by the PowerPC405EX(r). The MMODE and MEMODE registers are unified with their peer values used for the INITPLR MR and EMR registers, respectively. Finally, a spelling typo is correct (MANUEL to MANUAL). With these mnemonics in place, the CFG_SDRAM0_* magic numbers for Kilauea are replaced by equivalent mnemonics to make it easier to compare and contrast other 405EX(r)-based boards (e.g. during board bring-up). Finally, unified the SDRAM controller register dump routine such that it can be used across all processor variants that utilize the IBM DDR2 SDRAM controller core. It produces output of the form: PPC4xx IBM DDR2 Register Dump: ... SDRAM_MB0CF[40] = 0x00006701 ... which is '[] = '. The DCR number is included since it is not uncommon that the DCR values in header files get mixed up and it helps to validate, at a glance, they match what is printed in the user manual. Tested on: AMCC Kilauea/Haleakala: - NFS Linux Boot: PASSED - NAND Linux Boot: PASSED Signed-off-by: Grant Erickson Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 262 +++++++++++++++------------------------- include/asm-ppc/ppc4xx-sdram.h | 267 ++++++++++++++++++++++++++++++++++------- include/configs/kilauea.h | 145 +++++++++++++++++----- 3 files changed, 433 insertions(+), 241 deletions(-) (limited to 'include/asm-ppc') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f813ba604dd..d7f20a17817 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -50,6 +50,8 @@ #include "ecc.h" +static void ppc4xx_ibm_ddr2_register_dump(void); + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ @@ -258,7 +260,6 @@ static void test(void); #else static void DQS_calibration_process(void); #endif -static void ppc440sp_sdram_register_dump(void); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); @@ -608,7 +609,7 @@ phys_size_t initdram(int board_type) remove_tlb(0, dram_size); program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); - ppc440sp_sdram_register_dump(); + ppc4xx_ibm_ddr2_register_dump(); /* * Clear potential errors resulting from auto-calibration. @@ -2761,7 +2762,7 @@ calibration_loop: printf("\nERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); - ppc440sp_sdram_register_dump(); + ppc4xx_ibm_ddr2_register_dump(); spd_ddr_init_hang (); } @@ -2947,168 +2948,6 @@ static void test(void) } #endif -#if defined(DEBUG) -static void ppc440sp_sdram_register_dump(void) -{ - unsigned int sdram_reg; - unsigned int sdram_data; - unsigned int dcr_data; - - printf("\n Register Dump:\n"); - sdram_reg = SDRAM_MCSTAT; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MCSTAT = 0x%08X", sdram_data); - sdram_reg = SDRAM_MCOPT1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MCOPT2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data); - sdram_reg = SDRAM_MODT0; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MODT1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT1 = 0x%08X", sdram_data); - sdram_reg = SDRAM_MODT2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MODT3; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT3 = 0x%08X", sdram_data); - sdram_reg = SDRAM_CODT; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_CODT = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_VVPR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_VVPR = 0x%08X", sdram_data); - sdram_reg = SDRAM_OPARS; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_OPARS = 0x%08X\n", sdram_data); - /* - * OPAR2 is only used as a trigger register. - * No data is contained in this register, and reading or writing - * to is can cause bad things to happen (hangs). Just skip it - * and report NA - * sdram_reg = SDRAM_OPAR2; - * mfsdram(sdram_reg, sdram_data); - * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data); - */ - printf(" SDRAM_OPART = N/A "); - sdram_reg = SDRAM_RTR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RTR = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MB0CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB0CF = 0x%08X", sdram_data); - sdram_reg = SDRAM_MB1CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MB2CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB2CF = 0x%08X", sdram_data); - sdram_reg = SDRAM_MB3CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR0; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR3; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR4; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR5; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR6; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR7; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR8; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR9; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR10; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR11; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR12; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR13; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR14; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR15; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_RQDC; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RQDC = 0x%08X", sdram_data); - sdram_reg = SDRAM_RFDC; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RFDC = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_RDCC; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RDCC = 0x%08X", sdram_data); - sdram_reg = SDRAM_DLCR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_DLCR = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_CLKTR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_CLKTR = 0x%08X", sdram_data); - sdram_reg = SDRAM_WRDTR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_SDTR1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_SDTR1 = 0x%08X", sdram_data); - sdram_reg = SDRAM_SDTR2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_SDTR3; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_SDTR3 = 0x%08X", sdram_data); - sdram_reg = SDRAM_MMODE; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MMODE = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MEMODE; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MEMODE = 0x%08X", sdram_data); - sdram_reg = SDRAM_ECCCR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data); - - dcr_data = mfdcr(SDRAM_R0BAS); - printf(" MQ0_B0BAS = 0x%08X", dcr_data); - dcr_data = mfdcr(SDRAM_R1BAS); - printf(" MQ1_B0BAS = 0x%08X\n", dcr_data); - dcr_data = mfdcr(SDRAM_R2BAS); - printf(" MQ2_B0BAS = 0x%08X", dcr_data); - dcr_data = mfdcr(SDRAM_R3BAS); - printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); -} -#else /* !defined(DEBUG) */ -static void ppc440sp_sdram_register_dump(void) -{ -} -#endif /* defined(DEBUG) */ #elif defined(CONFIG_405EX) /*----------------------------------------------------------------------------- * Function: initdram @@ -3223,8 +3062,101 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_DDR_ECC) ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ + + ppc4xx_ibm_ddr2_register_dump(); #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ return (CFG_MBYTES_SDRAM << 20); } #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */ + +static void ppc4xx_ibm_ddr2_register_dump(void) +{ +#if defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \ + do { \ + u32 data; \ + mfsdram(SDRAM_##mnemonic, data); \ + printf("%20s[%02x] = 0x%08X\n", \ + "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ + } while (0) + + printf("\nPPC4xx IBM DDR2 Register Dump:\n"); + +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS); + PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS); + PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS); + PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS); +#endif /* (defined(CONFIG_440SP) || ... */ +#if defined(CONFIG_405EX) + PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL); + PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH); + PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ); + PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT); + PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA); +#endif /* defined(CONFIG_405EX) */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT); +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS); + /* + * OPART is only used as a trigger register. + * + * No data is contained in this register, and reading or writing + * to is can cause bad things to happen (hangs). Just skip it and + * report "N/A". + */ + printf("%20s = N/A\n", "SDRAM_OPART"); +#endif /* defined(CONFIG_440SP) || ... */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE); + PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR); +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(CID); +#endif /* defined(CONFIG_440SP) || ... */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(RID); + PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR); +#endif /* defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index d01e07e8baa..df787b3d4c7 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -562,7 +562,7 @@ * SDRAM Delay Line Calibration Register */ #define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_MANUAL 0x80000000 #define SDRAM_DLCR_DCLM_AUTO 0x00000000 #define SDRAM_DLCR_DLCR_MASK 0x08000000 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 @@ -577,60 +577,235 @@ #define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0) #define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF) +/* + * SDRAM Memory On Die Terimination Control Register + */ +#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0) +#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1) +#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0) +#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1) +#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0) +#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1) +#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0) +#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1) + /* * SDRAM Controller On Die Termination Register */ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1) +#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0) +#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1) +#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0) +#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1) +#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0) +#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1) +#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0) +#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1) +#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0) +#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0) +#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1) +#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2) +#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3) +#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0) +#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1) +#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0) +#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1) +#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0) +#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1) +#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0) +#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1) +#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0) +#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1) +#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0) +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0) +#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1) +#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0) +#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1) +#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0) +#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1) +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1) +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1) +#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0) +#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1) + +/* + * SDRAM Initialization Preload Register + */ +#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF) +#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(u32, \ + n)) \ + & 0xFF) +#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7) +#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7) +#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF) +#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \ + (static_cast(u32, \ + n)) \ + & 0x7FFF) + +/* + * JEDEC DDR Initialization Commands + */ +#define JEDEC_CMD_NOP 7 +#define JEDEC_CMD_PRECHARGE 2 +#define JEDEC_CMD_REFRESH 1 +#define JEDEC_CMD_EMR 0 +#define JEDEC_CMD_READ 5 +#define JEDEC_CMD_WRITE 4 + +/* + * JEDEC Precharge Command Memory Address Arguments + */ +#define JEDEC_MA_PRECHARGE_ONE (0 << 10) +#define JEDEC_MA_PRECHARGE_ALL (1 << 10) + +/* + * JEDEC DDR EMR Command Bank Address Arguments + */ +#define JEDEC_BA_MR 0 +#define JEDEC_BA_EMR 1 +#define JEDEC_BA_EMR2 2 +#define JEDEC_BA_EMR3 3 + +/* + * JEDEC DDR Mode Register + */ +#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12) +#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12) +#define JEDEC_MA_MR_WR_MASK (0x7 << 9) +#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9) +#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9) +#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9) +#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9) +#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9) +#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9) +#define JEDEC_MA_MR_DLL_RESET (1 << 8) +#define JEDEC_MA_MR_MODE_NORMAL (0 << 8) +#define JEDEC_MA_MR_MODE_TEST (1 << 8) +#define JEDEC_MA_MR_CL_MASK (0x7 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4) +#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4) +#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4) +#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3) +#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3) +#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0) +#define JEDEC_MA_MR_BLEN_4 (2 << 0) +#define JEDEC_MA_MR_BLEN_8 (3 << 0) + +/* + * JEDEC DDR Extended Mode Register + */ +#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12) +#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12) +#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12) +#define JEDEC_MA_EMR_RQDS_MASK (1 << 11) +#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11) +#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11) +#define JEDEC_MA_EMR_DQS_MASK (1 << 10) +#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10) +#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10) +#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7) +#define JEDEC_MA_EMR_OCD_EXIT (0 << 7) +#define JEDEC_MA_EMR_OCD_ENTER (7 << 7) +#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3) +#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3) +#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3) +#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3) +#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3) +#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2) +#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2) +#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2) +#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2) +#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2) +#define JEDEC_MA_EMR_ODS_MASK (1 << 1) +#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1) +#define JEDEC_MA_EMR_ODS_WEAK (1 << 1) +#define JEDEC_MA_EMR_DLL_MASK (1 << 0) +#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0) +#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0) + +/* + * JEDEC DDR Extended Mode Register 2 + */ +#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7) +#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7) /* - * SDRAM Mode Register + * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register) */ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 +#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK +#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1 +#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC +#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC +#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC +#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC +#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC +#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK +#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL +#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED +#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK +#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4 +#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8 /* - * SDRAM Extended Mode Register + * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended + * Mode Register) */ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 +#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK +#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE +#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE +#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK +#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE +#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE +#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK +#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE +#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE +#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC +#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC +#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC +#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC +#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC +#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK +#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED +#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM +#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM +#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM +#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK +#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL +#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK +#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK +#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE +#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE /* * SDRAM Clock Timing Register diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 9c1a3a4c1e5..f3d048cb7ed 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -233,39 +233,124 @@ #define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE -#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_8_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_DCOO_DISABLED) #define CFG_SDRAM0_MCOPT2 0x00000000 -#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ + SDRAM_MODT_EB0R_ENABLE) #define CFG_SDRAM0_MODT1 0x00000000 -#define CFG_SDRAM0_CODT 0x0080f837 -#define CFG_SDRAM0_RTR 0x06180000 -#define CFG_SDRAM0_INITPLR0 0xa8380000 -#define CFG_SDRAM0_INITPLR1 0x81900400 -#define CFG_SDRAM0_INITPLR2 0x81020000 -#define CFG_SDRAM0_INITPLR3 0x81030000 -#define CFG_SDRAM0_INITPLR4 0x81010404 -#define CFG_SDRAM0_INITPLR5 0x81000542 -#define CFG_SDRAM0_INITPLR6 0x81900400 -#define CFG_SDRAM0_INITPLR7 0x8D080000 -#define CFG_SDRAM0_INITPLR8 0x8D080000 -#define CFG_SDRAM0_INITPLR9 0x8D080000 -#define CFG_SDRAM0_INITPLR10 0x8D080000 -#define CFG_SDRAM0_INITPLR11 0x81000442 -#define CFG_SDRAM0_INITPLR12 0x81010780 -#define CFG_SDRAM0_INITPLR13 0x81010400 -#define CFG_SDRAM0_INITPLR14 0x00000000 -#define CFG_SDRAM0_INITPLR15 0x00000000 -#define CFG_SDRAM0_RQDC 0x80000038 -#define CFG_SDRAM0_RFDC 0x00000209 -#define CFG_SDRAM0_RDCC 0x40000000 -#define CFG_SDRAM0_DLCR 0x030000a5 -#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_CKLZ_36OHM | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CFG_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CFG_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CFG_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CFG_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CFG_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_75OHM)) +#define CFG_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CFG_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4)) +#define CFG_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CFG_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) +#define CFG_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CFG_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(165)) +#define CFG_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) #define CFG_SDRAM0_WRDTR 0x00000000 -#define CFG_SDRAM0_SDTR1 0x80201000 -#define CFG_SDRAM0_SDTR2 0x32204232 -#define CFG_SDRAM0_SDTR3 0x080b0d1a -#define CFG_SDRAM0_MMODE 0x00000442 -#define CFG_SDRAM0_MEMODE 0x00000404 +#define CFG_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CFG_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CFG_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ + SDRAM_SDTR3_RC_ENCODE(11) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(26)) +#define CFG_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + SDRAM_MMODE_DCL_DDR2_4_0_CLK | \ + SDRAM_MMODE_BLEN_4) +#define CFG_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ + SDRAM_MEMODE_RTT_75OHM) /*----------------------------------------------------------------------- * I2C -- cgit v1.3.1 From 7ee2619c20ccecd57966d74d844e6329e141261c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 24 Jun 2008 17:18:50 +0200 Subject: ppc4xx: Consolidate PPC4xx EBC defines This patch removes all EBC related defines from the PPC4xx headers ppc405.h and ppc440.h and introduces a new header include/asm-ppc/ppc4xx-ebc.h with all those defines. Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-ebc.h | 156 +++++++++++++++++++++++++++++++++++++++++++ include/ppc405.h | 114 ------------------------------- include/ppc440.h | 87 ------------------------ include/ppc4xx.h | 1 + 4 files changed, 157 insertions(+), 201 deletions(-) create mode 100644 include/asm-ppc/ppc4xx-ebc.h (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h new file mode 100644 index 00000000000..d180e045fc5 --- /dev/null +++ b/include/asm-ppc/ppc4xx-ebc.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_EBC_H_ +#define _PPC4xx_EBC_H_ + +/* + * Currently there are two register layout versions for the + * IBM EBC core used on 4xx PPC's: + */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define CONFIG_EBC_PPC4xx_IBM_VER1 +#endif + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2) +#else +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) +#endif + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Common fields in EBC0_CFG register */ +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F) + +/* Now the two versions of the other bits */ +#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) +#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) +#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) +#define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3) +#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3) +#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) +#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) +#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3) +#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0) +#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1) +#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2) +#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3) +#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0) +#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1) +#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2) +#else +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) +#endif + +#endif /* _PPC4xx_EBC_H_ */ diff --git a/include/ppc405.h b/include/ppc405.h index 061ac708ce7..fee4ee5b53f 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -366,120 +366,6 @@ #define UIC_EXT6 0x00000001 /* External interrupt 6 */ #endif /* defined(CONFIG_405EZ) */ -/****************************************************************************** - * External Bus Controller (EBC) - *****************************************************************************/ - -/* Bank Configuration Register */ -#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) -#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ - EBC_BXCR_BAS_MASK) << 0) -#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) -#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) -#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) -#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) -#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) -#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) -#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) -#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) -#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) -#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) -#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) -#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) -#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) -#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) - -/* Bank Access Parameter Register */ -#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) -#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) -#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(unsigned long, n)) \ - & 0xFF) -#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ - (static_cast(unsigned long, n)) \ - & 0x1F) -#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(unsigned long, n)) \ - & 0x7) -#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) -#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) -#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) -#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) -#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) -#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ - (static_cast(unsigned long, n)) \ - & 0x7) -#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) -#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) -#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) -#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) -#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) -#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) -#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) -#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) - -/* Configuration Register */ -#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) -#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) -#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) -#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) -#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) -#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) -#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) -#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) -#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) -#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) -#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) -#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) -#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) -#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) -#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) -#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) -#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) -#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) -#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) -#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) -#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) -#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) -#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) -#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) -#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) -#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) -#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) -#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) -#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ - (static_cast(unsigned long, n)) \ - & 0x1F) -#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) -#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) -#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) -#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) -#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) - #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller diff --git a/include/ppc440.h b/include/ppc440.h index fe988fbc27e..f843792443a 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1755,93 +1755,6 @@ #define UIC_EIR0 0x00000004 /* External interrupt 0 */ #endif /* CONFIG_440SPE */ -/*-----------------------------------------------------------------------------+ -| External Bus Controller Bit Settings -+-----------------------------------------------------------------------------*/ -#define EBC_CFGADDR_MASK 0x0000003F - -#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) -#define EBC_BXCR_BS_MASK 0x000E0000 -#define EBC_BXCR_BS_1MB 0x00000000 -#define EBC_BXCR_BS_2MB 0x00020000 -#define EBC_BXCR_BS_4MB 0x00040000 -#define EBC_BXCR_BS_8MB 0x00060000 -#define EBC_BXCR_BS_16MB 0x00080000 -#define EBC_BXCR_BS_32MB 0x000A0000 -#define EBC_BXCR_BS_64MB 0x000C0000 -#define EBC_BXCR_BS_128MB 0x000E0000 -#define EBC_BXCR_BU_MASK 0x00018000 -#define EBC_BXCR_BU_R 0x00008000 -#define EBC_BXCR_BU_W 0x00010000 -#define EBC_BXCR_BU_RW 0x00018000 -#define EBC_BXCR_BW_MASK 0x00006000 -#define EBC_BXCR_BW_8BIT 0x00000000 -#define EBC_BXCR_BW_16BIT 0x00002000 -#define EBC_BXCR_BW_32BIT 0x00006000 -#define EBC_BXAP_BME_ENABLED 0x80000000 -#define EBC_BXAP_BME_DISABLED 0x00000000 -#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) -#define EBC_BXAP_BCE_DISABLE 0x00000000 -#define EBC_BXAP_BCE_ENABLE 0x00400000 -#define EBC_BXAP_BCT_MASK 0x00300000 -#define EBC_BXAP_BCT_2TRANS 0x00000000 -#define EBC_BXAP_BCT_4TRANS 0x00100000 -#define EBC_BXAP_BCT_8TRANS 0x00200000 -#define EBC_BXAP_BCT_16TRANS 0x00300000 -#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) -#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) -#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) -#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) -#define EBC_BXAP_RE_ENABLED 0x00000100 -#define EBC_BXAP_RE_DISABLED 0x00000000 -#define EBC_BXAP_SOR_DELAYED 0x00000000 -#define EBC_BXAP_SOR_NONDELAYED 0x00000080 -#define EBC_BXAP_BEM_WRITEONLY 0x00000000 -#define EBC_BXAP_BEM_RW 0x00000040 -#define EBC_BXAP_PEN_DISABLED 0x00000000 - -#define EBC_CFG_LE_MASK 0x80000000 -#define EBC_CFG_LE_UNLOCK 0x00000000 -#define EBC_CFG_LE_LOCK 0x80000000 -#define EBC_CFG_PTD_MASK 0x40000000 -#define EBC_CFG_PTD_ENABLE 0x00000000 -#define EBC_CFG_PTD_DISABLE 0x40000000 -#define EBC_CFG_RTC_MASK 0x38000000 -#define EBC_CFG_RTC_16PERCLK 0x00000000 -#define EBC_CFG_RTC_32PERCLK 0x08000000 -#define EBC_CFG_RTC_64PERCLK 0x10000000 -#define EBC_CFG_RTC_128PERCLK 0x18000000 -#define EBC_CFG_RTC_256PERCLK 0x20000000 -#define EBC_CFG_RTC_512PERCLK 0x28000000 -#define EBC_CFG_RTC_1024PERCLK 0x30000000 -#define EBC_CFG_RTC_2048PERCLK 0x38000000 -#define EBC_CFG_ATC_MASK 0x04000000 -#define EBC_CFG_ATC_HI 0x00000000 -#define EBC_CFG_ATC_PREVIOUS 0x04000000 -#define EBC_CFG_DTC_MASK 0x02000000 -#define EBC_CFG_DTC_HI 0x00000000 -#define EBC_CFG_DTC_PREVIOUS 0x02000000 -#define EBC_CFG_CTC_MASK 0x01000000 -#define EBC_CFG_CTC_HI 0x00000000 -#define EBC_CFG_CTC_PREVIOUS 0x01000000 -#define EBC_CFG_OEO_MASK 0x00800000 -#define EBC_CFG_OEO_HI 0x00000000 -#define EBC_CFG_OEO_PREVIOUS 0x00800000 -#define EBC_CFG_EMC_MASK 0x00400000 -#define EBC_CFG_EMC_NONDEFAULT 0x00000000 -#define EBC_CFG_EMC_DEFAULT 0x00400000 -#define EBC_CFG_PME_MASK 0x00200000 -#define EBC_CFG_PME_DISABLE 0x00000000 -#define EBC_CFG_PME_ENABLE 0x00200000 -#define EBC_CFG_PMT_MASK 0x001F0000 -#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) -#define EBC_CFG_PR_MASK 0x0000C000 -#define EBC_CFG_PR_16 0x00000000 -#define EBC_CFG_PR_32 0x00004000 -#define EBC_CFG_PR_64 0x00008000 -#define EBC_CFG_PR_128 0x0000C000 - /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 54897f759d7..ca0636ca853 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -53,6 +53,7 @@ #endif #include +#include /* * Macro for generating register field mnemonics -- cgit v1.3.1 From 4fb25a3db3b3839094aa9ab748efd7a95924690b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 25 Jun 2008 10:59:22 +0200 Subject: ppc4xx: Consolidate PPC4xx UIC defines This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese --- board/amcc/sequoia/sequoia.c | 3 +- cpu/ppc4xx/4xx_enet.c | 1 - cpu/ppc4xx/4xx_uart.c | 2 +- cpu/ppc4xx/interrupts.c | 1 - cpu/ppc4xx/iop480_uart.c | 1 - cpu/ppc4xx/usbdev.c | 2 +- include/asm-ppc/ppc4xx-intvec.h | 474 ---------------------------------------- include/asm-ppc/ppc4xx-uic.h | 469 +++++++++++++++++++++++++++++++++++++++ include/ppc4xx.h | 1 + 9 files changed, 473 insertions(+), 481 deletions(-) delete mode 100644 include/asm-ppc/ppc4xx-intvec.h create mode 100644 include/asm-ppc/ppc4xx-uic.h (limited to 'include/asm-ppc') diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index b833092f191..87f5d5d6c1d 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -25,12 +25,11 @@ #include #include #include -#include +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 26d74d258d0..47d8abc1775 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -90,7 +90,6 @@ #include <405_mal.h> #include #include -#include /* * Only compile for platform with AMCC EMAC ethernet controller and diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index a7587d4351f..766e586808b 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -46,7 +46,7 @@ #include #include #include -#include +#include #ifdef CONFIG_SERIAL_MULTI #include diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 8620e2b4847..eb9cb1d397b 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -34,7 +34,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/ppc4xx/iop480_uart.c b/cpu/ppc4xx/iop480_uart.c index 3af0767c552..0e3423f7abb 100644 --- a/cpu/ppc4xx/iop480_uart.c +++ b/cpu/ppc4xx/iop480_uart.c @@ -26,7 +26,6 @@ #include #include #include -#include #ifdef CONFIG_SERIAL_MULTI #include diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index d71ba7710a0..27e6a4056c9 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -6,8 +6,8 @@ #if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && defined(CONFIG_CMD_USB) #include +#include #include "usbdev.h" -#include #define USB_DT_DEVICE 0x01 #define USB_DT_CONFIG 0x02 diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h deleted file mode 100644 index 5b45de4335d..00000000000 --- a/include/asm-ppc/ppc4xx-intvec.h +++ /dev/null @@ -1,474 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -/* - * Interrupt vector number definitions to ease the - * 405 -- 440 porting pain ;-) - * - * NOTE: They're not all here yet ... update as needed. - * - */ - -#ifndef _VECNUMS_H_ -#define _VECNUMS_H_ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART 0 */ -#define VECNUM_U1 1 /* UART 1 */ -#define VECNUM_IIC0 2 /* IIC */ -#define VECNUM_KRD 3 /* Kasumi Ready for data */ -#define VECNUM_KDA 4 /* Kasumi Data Available */ -#define VECNUM_PCRW 5 /* PCI command register write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_IIC1 7 /* IIC */ -#define VECNUM_SPI 8 /* SPI */ -#define VECNUM_EPCISER 9 /* External PCI SERR */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UD0 16 /* UDMA irq 0 */ -#define VECNUM_UD1 17 /* UDMA irq 1 */ -#define VECNUM_UD2 18 /* UDMA irq 2 */ -#define VECNUM_UD3 19 /* UDMA irq 3 */ -#define VECNUM_HSB2D 20 /* USB2.0 Device */ -#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ -#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ -#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ -#define VECNUM_EIP94 23 /* Security EIP94 */ -#define VECNUM_ETH0 24 /* Emac 0 */ -#define VECNUM_ETH1 25 /* Emac 1 */ -#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0) /* MAL SERR */ -#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ -#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ -#define VECNUM_U2 (32 + 3) /* UART 2 */ -#define VECNUM_U3 (32 + 4) /* UART 3 */ -#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ -#define VECNUM_NDFC (32 + 6) /* NDFC */ -#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ -#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ -#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ -#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ -#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ -#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ -#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ -#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ -#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ -#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ -#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ -#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ -#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ -#define VECNUM_SRE (32 + 24) /* Serial ROM error */ -#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ -#define VECNUM_RSVD0 (32 + 26) /* Reserved */ -#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ -#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ -#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ -#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ - -#define VECNUM_TXDE VECNUM_MTDE -#define VECNUM_RXDE VECNUM_MRDE - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ -#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ -#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ -#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ -#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ -#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ -#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ -#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ -#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ -#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -/* UIC 0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 8 /* PCI MSI level 0 */ -#define VECNUM_EIR0 9 /* External interrupt 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_EIR1 9 /* External interrupt 1 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ -#define VECNUM_U0 (32 + 1) /* UART0 */ -#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ -#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ -#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ -#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ -#define VECNUM_U2 (32 + 28) /* UART2 */ -#define VECNUM_U3 (32 + 29) /* UART3 */ -#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */ - -/* UIC 2 */ -#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ -#define VECNUM_MS (64 + 3) /* MAL SERR */ -#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ -#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ -#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ -#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ -#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ -#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */ -#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */ -#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */ -#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */ -#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */ -#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */ -#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */ -#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */ -#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */ - -/* UIC 3 */ -#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ -#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ -#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ -#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ -#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ -#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ -#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ -#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ -#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ -#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */ -#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */ -#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */ - -#elif defined(CONFIG_440SPE) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 1 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */ -#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */ -#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */ -#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */ -#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */ -#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */ - -#elif defined(CONFIG_440SP) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ -#define VECNUM_MS (32 + 1) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -#elif defined(CONFIG_440) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_CT0 18 /* GPT compare timer 0 */ -#define VECNUM_CT1 19 /* GPT compare timer 1 */ -#define VECNUM_CT2 20 /* GPT compare timer 2 */ -#define VECNUM_CT3 21 /* GPT compare timer 3 */ -#define VECNUM_CT4 22 /* GPT compare timer 4 */ -#define VECNUM_EIR0 23 /* External interrupt 0 */ -#define VECNUM_EIR1 24 /* External interrupt 1 */ -#define VECNUM_EIR2 25 /* External interrupt 2 */ -#define VECNUM_EIR3 26 /* External interrupt 3 */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_EIR5 28 /* External interrupt 5 */ -#define VECNUM_EIR6 29 /* External interrupt 6 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ -#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ - -#else /* !defined(CONFIG_440) */ - -#if defined(CONFIG_405EZ) -#define VECNUM_D0 0 /* DMA channel 0 */ -#define VECNUM_D1 1 /* DMA channel 1 */ -#define VECNUM_D2 2 /* DMA channel 2 */ -#define VECNUM_D3 3 /* DMA channel 3 */ -#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ -#define VECNUM_U0 5 /* UART0 */ -#define VECNUM_U1 6 /* UART1 */ -#define VECNUM_CAN0 7 /* CAN 0 */ -#define VECNUM_CAN1 8 /* CAN 1 */ -#define VECNUM_SPI 9 /* SPI */ -#define VECNUM_IIC0 10 /* I2C */ -#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ -#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ -#define VECNUM_USBH1 13 /* USB Host 1 */ -#define VECNUM_USBH2 14 /* USB Host 2 */ -#define VECNUM_USBDEV 15 /* USB Device */ -#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ -#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ - -#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ -#define VECNUM_MS 18 /* MAL_SERR_INT */ -#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ -#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ - -#define VECNUM_MTE 19 /* MAL TXEOB */ -#define VECNUM_MTE1 20 /* MAL TXEOB1 */ -#define VECNUM_MRE 21 /* MAL RXEOB */ -#define VECNUM_NAND 22 /* NAND Flash controller */ -#define VECNUM_ADC 23 /* ADC */ -#define VECNUM_DAC 24 /* DAC */ -#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ -#define VECNUM_RESERVED0 26 /* Reserved */ -#define VECNUM_EIR0 27 /* External interrupt 0 */ -#define VECNUM_EIR1 28 /* External interrupt 1 */ -#define VECNUM_EIR2 29 /* External interrupt 2 */ -#define VECNUM_EIR3 30 /* External interrupt 3 */ -#define VECNUM_EIR4 31 /* External interrupt 4 */ - -#elif defined(CONFIG_405EX) - -/* UIC 0 */ -#define VECNUM_U0 00 -#define VECNUM_U1 01 -#define VECNUM_IIC0 02 -#define VECNUM_PKA 03 -#define VECNUM_TRNG 04 -#define VECNUM_EBM 05 -#define VECNUM_BGI 06 -#define VECNUM_IIC1 07 -#define VECNUM_SPI 08 -#define VECNUM_EIR0 09 -#define VECNUM_MTE 10 /* MAL Tx EOB */ -#define VECNUM_MRE 11 /* MAL Rx EOB */ -#define VECNUM_DMA0 12 -#define VECNUM_DMA1 13 -#define VECNUM_DMA2 14 -#define VECNUM_DMA3 15 -#define VECNUM_PCIE0AL 16 -#define VECNUM_PCIE0VPD 17 -#define VECNUM_RPCIE0HRST 18 -#define VECNUM_FPCIE0HRST 19 -#define VECNUM_PCIE0TCR 20 -#define VECNUM_PCIEMSI0 21 -#define VECNUM_PCIEMSI1 22 -#define VECNUM_SECURITY 23 -#define VECNUM_ETH0 24 -#define VECNUM_ETH1 25 -#define VECNUM_PCIEMSI2 26 -#define VECNUM_EIR4 27 -#define VECNUM_UIC2NC 28 -#define VECNUM_UIC2C 29 -#define VECNUM_UIC1NC 30 -#define VECNUM_UIC1C 31 - -/* UIC 1 */ -#define VECNUM_MS (32 + 00) /* MAL SERR */ -#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ -#define VECNUM_PCIE0BMVC0 (32 + 03) -#define VECNUM_PCIE0DCRERR (32 + 04) -#define VECNUM_EBC (32 + 05) -#define VECNUM_NDFC (32 + 06) -#define VECNUM_PCEI1DCRERR (32 + 07) -#define VECNUM_CT8 (32 + 08) -#define VECNUM_CT9 (32 + 09) -#define VECNUM_PCIE1AL (32 + 10) -#define VECNUM_PCIE1VPD (32 + 11) -#define VECNUM_RPCE1HRST (32 + 12) -#define VECNUM_FPCE1HRST (32 + 13) -#define VECNUM_PCIE1TCR (32 + 14) -#define VECNUM_PCIE1VC0 (32 + 15) -#define VECNUM_CT3 (32 + 16) -#define VECNUM_CT4 (32 + 17) -#define VECNUM_EIR7 (32 + 18) -#define VECNUM_EIR8 (32 + 19) -#define VECNUM_EIR9 (32 + 20) -#define VECNUM_CT5 (32 + 21) -#define VECNUM_CT6 (32 + 22) -#define VECNUM_CT7 (32 + 23) -#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ -#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ -#define VECNUM_EIR2 (32 + 26) -#define VECNUM_EIR5 (32 + 27) -#define VECNUM_EIR6 (32 + 28) -#define VECNUM_EMAC0WAKE (32 + 29) -#define VECNUM_EIR1 (32 + 30) -#define VECNUM_EMAC1WAKE (32 + 31) - -/* UIC 2 */ -#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ -#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ -#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ -#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ -#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ -#define VECNUM_DDRMCUE (64 + 05) -#define VECNUM_DDRMCCE (64 + 06) -#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ -#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ -#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ -#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ -#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ -#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ -#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ -#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ -#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ -#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ -#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ -#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ -#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ -#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ -#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ -#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ -#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ -#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ -#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ -#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ -#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ -#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ -#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ -#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ -#define VECNUM_USBOTG (64 + 31) /* USB OTG */ - -#else /* !CONFIG_405EZ */ - -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_D0 5 /* DMA channel 0 */ -#define VECNUM_D1 6 /* DMA channel 1 */ -#define VECNUM_D2 7 /* DMA channel 2 */ -#define VECNUM_D3 8 /* DMA channel 3 */ -#define VECNUM_EWU0 9 /* Ethernet wakeup */ -#define VECNUM_MS 10 /* MAL SERR */ -#define VECNUM_MTE 11 /* MAL TXEOB */ -#define VECNUM_MRE 12 /* MAL RXEOB */ -#define VECNUM_TXDE 13 /* MAL TXDE */ -#define VECNUM_RXDE 14 /* MAL RXDE */ -#define VECNUM_ETH0 15 /* Ethernet interrupt status */ -#define VECNUM_EIR0 25 /* External interrupt 0 */ -#define VECNUM_EIR1 26 /* External interrupt 1 */ -#define VECNUM_EIR2 27 /* External interrupt 2 */ -#define VECNUM_EIR3 28 /* External interrupt 3 */ -#define VECNUM_EIR4 29 /* External interrupt 4 */ -#define VECNUM_EIR5 30 /* External interrupt 5 */ -#define VECNUM_EIR6 31 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - -#endif /* defined(CONFIG_440) */ - -#endif /* _VECNUMS_H_ */ diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h new file mode 100644 index 00000000000..1573b1eab18 --- /dev/null +++ b/include/asm-ppc/ppc4xx-uic.h @@ -0,0 +1,469 @@ +/* + * Copyright (C) 2002 Scott McNutt + * + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_UIC_H_ +#define _PPC4xx_UIC_H_ + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART 0 */ +#define VECNUM_U1 1 /* UART 1 */ +#define VECNUM_IIC0 2 /* IIC */ +#define VECNUM_KRD 3 /* Kasumi Ready for data */ +#define VECNUM_KDA 4 /* Kasumi Data Available */ +#define VECNUM_PCRW 5 /* PCI command register write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_IIC1 7 /* IIC */ +#define VECNUM_SPI 8 /* SPI */ +#define VECNUM_EPCISER 9 /* External PCI SERR */ +#define VECNUM_MTE 10 /* MAL TXEOB */ +#define VECNUM_MRE 11 /* MAL RXEOB */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UD0 16 /* UDMA irq 0 */ +#define VECNUM_UD1 17 /* UDMA irq 1 */ +#define VECNUM_UD2 18 /* UDMA irq 2 */ +#define VECNUM_UD3 19 /* UDMA irq 3 */ +#define VECNUM_HSB2D 20 /* USB2.0 Device */ +#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ +#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ +#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ +#define VECNUM_EIP94 23 /* Security EIP94 */ +#define VECNUM_ETH0 24 /* Emac 0 */ +#define VECNUM_ETH1 25 /* Emac 1 */ +#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ +#define VECNUM_EIR4 27 /* External interrupt 4 */ +#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ +#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 0) /* MAL SERR */ +#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ +#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ +#define VECNUM_U2 (32 + 3) /* UART 2 */ +#define VECNUM_U3 (32 + 4) /* UART 3 */ +#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ +#define VECNUM_NDFC (32 + 6) /* NDFC */ +#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ +#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ +#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ +#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ +#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ +#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ +#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ +#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ +#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ +#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ +#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ +#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ +#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ +#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ +#define VECNUM_SRE (32 + 24) /* Serial ROM error */ +#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ +#define VECNUM_RSVD0 (32 + 26) /* Reserved */ +#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ +#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ +#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ +#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ +#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ + +#define VECNUM_TXDE VECNUM_MTDE +#define VECNUM_RXDE VECNUM_MRDE + +/* UIC 2 */ +#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ +#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ +#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ +#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ +#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ +#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ +#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ +#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ +#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ +#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ + +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +/* UIC 0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 8 /* PCI MSI level 0 */ +#define VECNUM_EIR0 9 /* External interrupt 0 */ +#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ +#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ +#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ +#define VECNUM_EIR1 9 /* External interrupt 1 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ +#define VECNUM_U0 (32 + 1) /* UART0 */ +#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ +#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ +#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ +#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ +#define VECNUM_U2 (32 + 28) /* UART2 */ +#define VECNUM_U3 (32 + 29) /* UART3 */ +#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */ +#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */ + +/* UIC 2 */ +#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ +#define VECNUM_MS (64 + 3) /* MAL SERR */ +#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ +#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ +#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ +#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ +#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ +#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */ +#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */ +#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */ +#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */ +#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */ +#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */ +#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */ +#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */ +#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */ + +/* UIC 3 */ +#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ +#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ +#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ +#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ +#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ +#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ +#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ +#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ +#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ +#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */ +#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */ +#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */ + +#elif defined(CONFIG_440SPE) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ +#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ +#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 1 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +/* UIC 2 */ +#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */ +#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */ +#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */ +#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */ +#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */ +#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */ + +#elif defined(CONFIG_440SP) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ +#define VECNUM_MS (32 + 1) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +#elif defined(CONFIG_440) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_MTE 10 /* MAL TXEOB */ +#define VECNUM_MRE 11 /* MAL RXEOB */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_CT0 18 /* GPT compare timer 0 */ +#define VECNUM_CT1 19 /* GPT compare timer 1 */ +#define VECNUM_CT2 20 /* GPT compare timer 2 */ +#define VECNUM_CT3 21 /* GPT compare timer 3 */ +#define VECNUM_CT4 22 /* GPT compare timer 4 */ +#define VECNUM_EIR0 23 /* External interrupt 0 */ +#define VECNUM_EIR1 24 /* External interrupt 1 */ +#define VECNUM_EIR2 25 /* External interrupt 2 */ +#define VECNUM_EIR3 26 /* External interrupt 3 */ +#define VECNUM_EIR4 27 /* External interrupt 4 */ +#define VECNUM_EIR5 28 /* External interrupt 5 */ +#define VECNUM_EIR6 29 /* External interrupt 6 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 0 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ +#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ + +#else /* !defined(CONFIG_440) */ + +#if defined(CONFIG_405EZ) +#define VECNUM_D0 0 /* DMA channel 0 */ +#define VECNUM_D1 1 /* DMA channel 1 */ +#define VECNUM_D2 2 /* DMA channel 2 */ +#define VECNUM_D3 3 /* DMA channel 3 */ +#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ +#define VECNUM_U0 5 /* UART0 */ +#define VECNUM_U1 6 /* UART1 */ +#define VECNUM_CAN0 7 /* CAN 0 */ +#define VECNUM_CAN1 8 /* CAN 1 */ +#define VECNUM_SPI 9 /* SPI */ +#define VECNUM_IIC0 10 /* I2C */ +#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ +#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ +#define VECNUM_USBH1 13 /* USB Host 1 */ +#define VECNUM_USBH2 14 /* USB Host 2 */ +#define VECNUM_USBDEV 15 /* USB Device */ +#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ +#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ + +#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ +#define VECNUM_MS 18 /* MAL_SERR_INT */ +#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ +#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ + +#define VECNUM_MTE 19 /* MAL TXEOB */ +#define VECNUM_MTE1 20 /* MAL TXEOB1 */ +#define VECNUM_MRE 21 /* MAL RXEOB */ +#define VECNUM_NAND 22 /* NAND Flash controller */ +#define VECNUM_ADC 23 /* ADC */ +#define VECNUM_DAC 24 /* DAC */ +#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ +#define VECNUM_RESERVED0 26 /* Reserved */ +#define VECNUM_EIR0 27 /* External interrupt 0 */ +#define VECNUM_EIR1 28 /* External interrupt 1 */ +#define VECNUM_EIR2 29 /* External interrupt 2 */ +#define VECNUM_EIR3 30 /* External interrupt 3 */ +#define VECNUM_EIR4 31 /* External interrupt 4 */ + +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define VECNUM_U0 00 +#define VECNUM_U1 01 +#define VECNUM_IIC0 02 +#define VECNUM_PKA 03 +#define VECNUM_TRNG 04 +#define VECNUM_EBM 05 +#define VECNUM_BGI 06 +#define VECNUM_IIC1 07 +#define VECNUM_SPI 08 +#define VECNUM_EIR0 09 +#define VECNUM_MTE 10 /* MAL Tx EOB */ +#define VECNUM_MRE 11 /* MAL Rx EOB */ +#define VECNUM_DMA0 12 +#define VECNUM_DMA1 13 +#define VECNUM_DMA2 14 +#define VECNUM_DMA3 15 +#define VECNUM_PCIE0AL 16 +#define VECNUM_PCIE0VPD 17 +#define VECNUM_RPCIE0HRST 18 +#define VECNUM_FPCIE0HRST 19 +#define VECNUM_PCIE0TCR 20 +#define VECNUM_PCIEMSI0 21 +#define VECNUM_PCIEMSI1 22 +#define VECNUM_SECURITY 23 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1 25 +#define VECNUM_PCIEMSI2 26 +#define VECNUM_EIR4 27 +#define VECNUM_UIC2NC 28 +#define VECNUM_UIC2C 29 +#define VECNUM_UIC1NC 30 +#define VECNUM_UIC1C 31 + +/* UIC 1 */ +#define VECNUM_MS (32 + 00) /* MAL SERR */ +#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ +#define VECNUM_PCIE0BMVC0 (32 + 03) +#define VECNUM_PCIE0DCRERR (32 + 04) +#define VECNUM_EBC (32 + 05) +#define VECNUM_NDFC (32 + 06) +#define VECNUM_PCEI1DCRERR (32 + 07) +#define VECNUM_CT8 (32 + 08) +#define VECNUM_CT9 (32 + 09) +#define VECNUM_PCIE1AL (32 + 10) +#define VECNUM_PCIE1VPD (32 + 11) +#define VECNUM_RPCE1HRST (32 + 12) +#define VECNUM_FPCE1HRST (32 + 13) +#define VECNUM_PCIE1TCR (32 + 14) +#define VECNUM_PCIE1VC0 (32 + 15) +#define VECNUM_CT3 (32 + 16) +#define VECNUM_CT4 (32 + 17) +#define VECNUM_EIR7 (32 + 18) +#define VECNUM_EIR8 (32 + 19) +#define VECNUM_EIR9 (32 + 20) +#define VECNUM_CT5 (32 + 21) +#define VECNUM_CT6 (32 + 22) +#define VECNUM_CT7 (32 + 23) +#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ +#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ +#define VECNUM_EIR2 (32 + 26) +#define VECNUM_EIR5 (32 + 27) +#define VECNUM_EIR6 (32 + 28) +#define VECNUM_EMAC0WAKE (32 + 29) +#define VECNUM_EIR1 (32 + 30) +#define VECNUM_EMAC1WAKE (32 + 31) + +/* UIC 2 */ +#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ +#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ +#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ +#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ +#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ +#define VECNUM_DDRMCUE (64 + 05) +#define VECNUM_DDRMCCE (64 + 06) +#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ +#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ +#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ +#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ +#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ +#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ +#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ +#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ +#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ +#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ +#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ +#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ +#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ +#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ +#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ +#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ +#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ +#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ +#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ +#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ +#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ +#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ +#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ +#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ +#define VECNUM_USBOTG (64 + 31) /* USB OTG */ + +#else /* !CONFIG_405EZ */ + +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_D0 5 /* DMA channel 0 */ +#define VECNUM_D1 6 /* DMA channel 1 */ +#define VECNUM_D2 7 /* DMA channel 2 */ +#define VECNUM_D3 8 /* DMA channel 3 */ +#define VECNUM_EWU0 9 /* Ethernet wakeup */ +#define VECNUM_MS 10 /* MAL SERR */ +#define VECNUM_MTE 11 /* MAL TXEOB */ +#define VECNUM_MRE 12 /* MAL RXEOB */ +#define VECNUM_TXDE 13 /* MAL TXDE */ +#define VECNUM_RXDE 14 /* MAL RXDE */ +#define VECNUM_ETH0 15 /* Ethernet interrupt status */ +#define VECNUM_EIR0 25 /* External interrupt 0 */ +#define VECNUM_EIR1 26 /* External interrupt 1 */ +#define VECNUM_EIR2 27 /* External interrupt 2 */ +#define VECNUM_EIR3 28 /* External interrupt 3 */ +#define VECNUM_EIR4 29 /* External interrupt 4 */ +#define VECNUM_EIR5 30 /* External interrupt 5 */ +#define VECNUM_EIR6 31 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ + +#endif /* defined(CONFIG_440) */ + +#endif /* _PPC4xx_UIC_H_ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ca0636ca853..d593b072fcd 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -54,6 +54,7 @@ #include #include +#include /* * Macro for generating register field mnemonics -- cgit v1.3.1 From d1631fe1a05b063ccaf62ea892a8887b829847d1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Jun 2008 13:40:57 +0200 Subject: ppc4xx: Consolidate PPC4xx UIC defines This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese --- board/amcc/sequoia/sequoia.c | 2 +- common/cmd_reginfo.c | 5 +- cpu/ppc4xx/4xx_enet.c | 408 +++++++------------------ cpu/ppc4xx/interrupts.c | 75 ++--- cpu/ppc4xx/usbdev.c | 2 +- include/asm-ppc/ppc4xx-uic.h | 648 +++++++++++++++------------------------ include/configs/HH405.h | 2 +- include/ppc405.h | 247 --------------- include/ppc440.h | 708 ------------------------------------------- 9 files changed, 397 insertions(+), 1700 deletions(-) (limited to 'include/asm-ppc') diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 87f5d5d6c1d..d7d2aa2fcfa 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -334,7 +334,7 @@ int checkboard(void) */ void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); } #endif diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 0657e4b1f10..c0a145991d1 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -93,11 +93,10 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #elif defined (CONFIG_405GP) printf ("\n405GP registers; MSR=%08x\n",mfmsr()); printf ("\nUniversal Interrupt Controller Regs\n" - "uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr" + "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr" "\n" - "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n", + "%08x %08x %08x %08x %08x %08x %08x %08x\n", mfdcr(uicsr), - mfdcr(uicsrs), mfdcr(uicer), mfdcr(uiccr), mfdcr(uicpr), diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 47d8abc1775..01712b056e0 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -121,11 +121,62 @@ * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal * Interrupt Controller). *-----------------------------------------------------------------------------*/ -#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) -#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) -#define EMAC_UIC_DEF UIC_ENET -#define EMAC_UIC_DEF1 UIC_ENET1 -#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) +#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS)) + +#if defined(CONFIG_HAS_ETH3) +#if !defined(CONFIG_440GX) +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ + UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) +#else +/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */ +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) +#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) +#endif /* !defined(CONFIG_440GX) */ +#elif defined(CONFIG_HAS_ETH2) +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ + UIC_MASK(ETH_IRQ_NUM(2))) +#elif defined(CONFIG_HAS_ETH1) +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) +#else +#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0)) +#endif + +/* + * Define a default version for UIC_ETHxB for non 440GX so that we can + * use common code for all 4xx variants + */ +#if !defined(UIC_ETHxB) +#define UIC_ETHxB 0 +#endif + +#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR) +#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE) +#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE) +#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB) +#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB) + +#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) +#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) + +/* + * We have 3 different interrupt types: + * - MAL interrupts indicating successful transfer + * - MAL error interrupts indicating MAL related errors + * - EMAC interrupts indicating EMAC related errors + * + * All those interrupts can be on different UIC's, but since + * now at least all interrupts from one type are on the same + * UIC. Only exception is 440GX where the EMAC interrupts are + * spread over two UIC's! + */ +#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) +#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) +#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) +#if defined(CONFIG_440GX) +#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(2)) * 0x10)) +#else +#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) +#endif #undef INFO_4XX_ENET @@ -165,9 +216,6 @@ /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ -/* IER globals */ -static uint32_t mal_ier; - #if !defined(CONFIG_NET_MULTI) struct eth_device *emac0_dev = NULL; #endif @@ -199,12 +247,6 @@ struct eth_device *emac0_dev = NULL; #define CONFIG_EMAC_NR_START 0 #endif -#if defined(CONFIG_405EX) || defined(CONFIG_440EPX) -#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev))) -#else -#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2)) -#endif - #define MAL_RX_DESC_SIZE 2048 #define MAL_TX_DESC_SIZE 2048 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) @@ -1434,59 +1476,17 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, } } - -#if defined (CONFIG_440) || defined(CONFIG_405EX) - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -/* - * Hack: On 440SP all enet irq sources are located on UIC1 - * Needs some cleanup. --sr - */ -#define UIC0MSR uic1msr -#define UIC0SR uic1sr -#define UIC1MSR uic1msr -#define UIC1SR uic1sr -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -/* - * Hack: On 460EX/GT all enet irq sources are located on UIC2 - * Needs some cleanup. --ag - */ -#define UIC0MSR uic2msr -#define UIC0SR uic2sr -#define UIC1MSR uic2msr -#define UIC1SR uic2sr -#else -#define UIC0MSR uic0msr -#define UIC0SR uic0sr -#define UIC1MSR uic1msr -#define UIC1SR uic1sr -#endif - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#define UICMSR_ETHX uic0msr -#define UICSR_ETHX uic0sr -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UICMSR_ETHX uic2msr -#define UICSR_ETHX uic2sr -#else -#define UICMSR_ETHX uic1msr -#define UICSR_ETHX uic1sr -#endif - int enetInt (struct eth_device *dev) { int serviced; int rc = -1; /* default to not us */ - unsigned long mal_isr; - unsigned long emac_isr = 0; - unsigned long mal_rx_eob; - unsigned long my_uic0msr, my_uic1msr; - unsigned long my_uicmsr_ethx; - -#if defined(CONFIG_440GX) - unsigned long my_uic2msr; -#endif + u32 mal_isr; + u32 emac_isr = 0; + u32 mal_eob; + u32 uic_mal; + u32 uic_mal_err; + u32 uic_emac; + u32 uic_emac_b; EMAC_4XX_HW_PST hw_p; /* @@ -1505,256 +1505,79 @@ int enetInt (struct eth_device *dev) do { serviced = 0; - my_uic0msr = mfdcr (UIC0MSR); - my_uic1msr = mfdcr (UIC1MSR); -#if defined(CONFIG_440GX) - my_uic2msr = mfdcr (uic2msr); -#endif - my_uicmsr_ethx = mfdcr (UICMSR_ETHX); + uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR); + uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR); + uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR); + uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR); - if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) - && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) - && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { - /* not for us */ - return (rc); - } -#if defined (CONFIG_440GX) - if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) - && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { + if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB)) + && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) + && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) { /* not for us */ return (rc); } -#endif + /* get and clear controller status interrupts */ - /* look at Mal and EMAC interrupts */ - if ((my_uic0msr & (UIC_MRE | UIC_MTE)) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - /* we have a MAL interrupt */ - mal_isr = mfdcr (malesr); - /* look for mal error */ - if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { - mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); - serviced = 1; - rc = 0; - } - } + /* look at MAL and EMAC error interrupts */ + if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { + /* we have a MAL error interrupt */ + mal_isr = mfdcr(malesr); + mal_err(dev, mal_isr, uic_mal_err, + MAL_UIC_DEF, MAL_UIC_ERR); - /* port by port dispatch of emac interrupts */ - if (hw_p->devnum == 0) { - if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ - return (rc); /* we had errors so get out */ - } - } + /* clear MAL error interrupt status bits */ + mtdcr(UIC_BASE_MAL_ERR + UIC_SR, + UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE); -#if !defined(CONFIG_440SP) - if (hw_p->devnum == 1) { - if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ - return (rc); /* we had errors so get out */ - } - } -#if defined (CONFIG_440GX) - if (hw_p->devnum == 2) { - if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (uic2sr, UIC_ETH2); - return (rc); /* we had errors so get out */ - } + return -1; } - if (hw_p->devnum == 3) { - if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (uic2sr, UIC_ETH3); - return (rc); /* we had errors so get out */ - } - } -#endif /* CONFIG_440GX */ -#endif /* !CONFIG_440SP */ + /* look for EMAC errors */ + if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_err(dev, emac_isr); - /* handle MAX TX EOB interrupt from a tx */ - if (my_uic0msr & UIC_MTE) { - mal_rx_eob = mfdcr (maltxeobisr); - mtdcr (maltxeobisr, mal_rx_eob); - mtdcr (UIC0SR, UIC_MTE); - } - /* handle MAL RX EOB interupt from a receive */ - /* check for EOB on valid channels */ - if (my_uic0msr & UIC_MRE) { - mal_rx_eob = mfdcr (malrxeobisr); - if ((mal_rx_eob & - (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) - != 0) { /* call emac routine for channel x */ - /* clear EOB - mtdcr(malrxeobisr, mal_rx_eob); */ - enet_rcv (dev, emac_isr); - /* indicate that we serviced an interrupt */ - serviced = 1; - rc = 0; - } - } + /* clear EMAC error interrupt status bits */ + mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx); + mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB); - mtdcr (UIC0SR, UIC_MRE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - switch (hw_p->devnum) { - case 0: - mtdcr (UICSR_ETHX, UIC_ETH0); - break; - case 1: - mtdcr (UICSR_ETHX, UIC_ETH1); - break; -#if defined (CONFIG_440GX) - case 2: - mtdcr (uic2sr, UIC_ETH2); - break; - case 3: - mtdcr (uic2sr, UIC_ETH3); - break; -#endif /* CONFIG_440GX */ - default: - break; + return -1; } - } while (serviced); - - return (rc); -} - -#else /* CONFIG_440 */ - -int enetInt (struct eth_device *dev) -{ - int serviced; - int rc = -1; /* default to not us */ - unsigned long mal_isr; - unsigned long emac_isr = 0; - unsigned long mal_rx_eob; - unsigned long my_uicmsr; - - EMAC_4XX_HW_PST hw_p; - - /* - * Because the mal is generic, we need to get the current - * eth device - */ -#if defined(CONFIG_NET_MULTI) - dev = eth_get_dev(); -#else - dev = emac0_dev; -#endif - hw_p = dev->priv; - - /* enter loop that stays in interrupt code until nothing to service */ - do { - serviced = 0; - - my_uicmsr = mfdcr (uicmsr); - - if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ - return (rc); - } - /* get and clear controller status interrupts */ - /* look at Mal and EMAC interrupts */ - if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ - mal_isr = mfdcr (malesr); - /* look for mal error */ - if ((my_uicmsr & MAL_UIC_ERR) != 0) { - mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); - serviced = 1; - rc = 0; - } + /* handle MAX TX EOB interrupt from a tx */ + if (uic_mal & UIC_MAL_TXEOB) { + /* clear MAL interrupt status bits */ + mal_eob = mfdcr(maltxeobisr); + mtdcr(maltxeobisr, mal_eob); + mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); + + /* indicate that we serviced an interrupt */ + serviced = 1; + rc = 0; } - /* port by port dispatch of emac interrupts */ + /* handle MAL RX EOB interupt from a receive */ + /* check for EOB on valid channels */ + if (uic_mal & UIC_MAL_RXEOB) { + mal_eob = mfdcr(malrxeobisr); + if (mal_eob & + (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { + /* push packet to upper layer */ + enet_rcv(dev, emac_isr); - if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { - mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ - return (rc); /* we had errors so get out */ - } + /* clear MAL interrupt status bits */ + mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB); - /* handle MAX TX EOB interrupt from a tx */ - if (my_uicmsr & UIC_MAL_TXEOB) { - mal_rx_eob = mfdcr (maltxeobisr); - mtdcr (maltxeobisr, mal_rx_eob); - mtdcr (uicsr, UIC_MAL_TXEOB); - } - /* handle MAL RX EOB interupt from a receive */ - /* check for EOB on valid channels */ - if (my_uicmsr & UIC_MAL_RXEOB) - { - mal_rx_eob = mfdcr (malrxeobisr); - if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ - /* clear EOB - mtdcr(malrxeobisr, mal_rx_eob); */ - enet_rcv (dev, emac_isr); /* indicate that we serviced an interrupt */ serviced = 1; rc = 0; } } - mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ -#if defined(CONFIG_405EZ) - mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); -#endif /* defined(CONFIG_405EZ) */ - } - while (serviced); + } while (serviced); return (rc); } -#endif /* CONFIG_440 */ - /*-----------------------------------------------------------------------------+ * MAL Error Routine *-----------------------------------------------------------------------------*/ @@ -1940,6 +1763,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) EMAC_4XX_HW_PST hw = NULL; u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; u32 hw_addr[4]; + u32 mal_ier; #if defined(CONFIG_440GX) unsigned long pfc1; @@ -2077,19 +1901,19 @@ int ppc_4xx_eth_initialize (bd_t * bis) mtdcr (malier, mal_ier); /* install MAL interrupt handler */ - irq_install_handler (VECNUM_MS, + irq_install_handler (VECNUM_MAL_SERR, (interrupt_handler_t *) enetInt, dev); - irq_install_handler (VECNUM_MTE, + irq_install_handler (VECNUM_MAL_TXEOB, (interrupt_handler_t *) enetInt, dev); - irq_install_handler (VECNUM_MRE, + irq_install_handler (VECNUM_MAL_RXEOB, (interrupt_handler_t *) enetInt, dev); - irq_install_handler (VECNUM_TXDE, + irq_install_handler (VECNUM_MAL_TXDE, (interrupt_handler_t *) enetInt, dev); - irq_install_handler (VECNUM_RXDE, + irq_install_handler (VECNUM_MAL_RXDE, (interrupt_handler_t *) enetInt, dev); virgin = 1; diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index eb9cb1d397b..6dbd6d28190 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -35,25 +35,27 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - -/* - * Define the number of UIC's - */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UIC_MAX 4 -#elif defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#define UIC_MAX 3 -#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define UIC_MAX 2 +#if (UIC_MAX > 3) +#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ + UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \ + UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI)) +#elif (UIC_MAX > 2) +#if defined(CONFIG_440GX) +#define UICB0_ALL (UIC_MASK(VECNUM_UIC0CI) | UIC_MASK(VECNUM_UIC0NCI) | \ + UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ + UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) +#else +#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ + UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) +#endif +#elif (UIC_MAX > 1) +#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI)) #else -#define UIC_MAX 1 +#define UICB0_ALL 0 #endif +DECLARE_GLOBAL_DATA_PTR; + /* * CPM interrupt vector functions. */ @@ -158,18 +160,23 @@ int interrupt_init_cpu (unsigned *decrementer_count) #if !defined(CONFIG_440GX) #if (UIC_MAX > 1) /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC1NCI, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC1CI, uic_cascade_interrupt, 0); #endif #if (UIC_MAX > 2) - irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC2NCI, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC2CI, uic_cascade_interrupt, 0); #endif #if (UIC_MAX > 3) - irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC3NCI, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC3CI, uic_cascade_interrupt, 0); #endif #else /* !defined(CONFIG_440GX) */ + /* + * ToDo: Remove this 440GX special handling: + * Move SDR0_MFR setup to cpu.c and use common code with UICB0 + * on 440GX. 2008-06-26, sr + */ /* Take the GX out of compatibility mode * Travis Sawyer, 9 Mar 2004 * NOTE: 440gx user manual inconsistency here @@ -182,7 +189,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* Enable UIC interrupts via UIC Base Enable Register */ mtdcr(uicb0sr, UICB0_ALL); - mtdcr(uicb0er, 0x54000000); + mtdcr(uicb0er, UICB0_ALL); /* None are critical */ mtdcr(uicb0cr, 0); #endif /* !defined(CONFIG_440GX) */ @@ -216,8 +223,7 @@ static void uic_interrupt(u32 uic_base, int vec_base) (*irq_vecs[vec].handler)(irq_vecs[vec].arg); } else { set_dcr(uic_base + UIC_ER, - get_dcr(uic_base + UIC_ER) & - ~(0x80000000 >> (vec & 0x1f))); + get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec)); printf("Masking bogus interrupt vector %d" " (UIC_BASE=0x%x)\n", vec, uic_base); } @@ -226,7 +232,7 @@ static void uic_interrupt(u32 uic_base, int vec_base) * After servicing the interrupt, we have to remove the * status indicator */ - set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f))); + set_dcr(uic_base + UIC_SR, UIC_MASK(vec)); } /* @@ -244,7 +250,6 @@ static void uic_cascade_interrupt(void *para) } #endif -#if defined(CONFIG_440) #if defined(CONFIG_440GX) /* 440GX uses base uic register */ #define UIC_BMSR uicb0msr @@ -253,10 +258,6 @@ static void uic_cascade_interrupt(void *para) #define UIC_BMSR uic0msr #define UIC_BSR uic0sr #endif -#else /* CONFIG_440 */ -#define UIC_BMSR uicmsr -#define UIC_BSR uicsr -#endif /* CONFIG_440 */ /* * Handle external interrupts @@ -271,17 +272,20 @@ void external_interrupt(struct pt_regs *regs) uic_msr = mfdcr(UIC_BMSR); #if (UIC_MAX > 1) - if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr)) + if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC1NCI) & uic_msr)) uic_interrupt(UIC1_DCR_BASE, 32); #endif #if (UIC_MAX > 2) - if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr)) + if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC2NCI) & uic_msr)) uic_interrupt(UIC2_DCR_BASE, 64); #endif #if (UIC_MAX > 3) - if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr)) + if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC3NCI) & uic_msr)) uic_interrupt(UIC3_DCR_BASE, 96); #endif @@ -290,7 +294,8 @@ void external_interrupt(struct pt_regs *regs) if (uic_msr & ~(UICB0_ALL)) uic_interrupt(UIC0_DCR_BASE, 0); #else - if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr)) + if ((UIC_MASK(VECNUM_UIC0CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC0NCI) & uic_msr)) uic_interrupt(UIC0_DCR_BASE, 0); #endif #else /* CONFIG_440 */ diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index 27e6a4056c9..faf7f0878ff 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -197,7 +197,7 @@ void usb_dev_init() /*enable interrupts */ *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; - irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt, + irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, NULL); } #else diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h index 1573b1eab18..b596f0edfb8 100644 --- a/include/asm-ppc/ppc4xx-uic.h +++ b/include/asm-ppc/ppc4xx-uic.h @@ -26,444 +26,268 @@ #ifndef _PPC4xx_UIC_H_ #define _PPC4xx_UIC_H_ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART 0 */ -#define VECNUM_U1 1 /* UART 1 */ -#define VECNUM_IIC0 2 /* IIC */ -#define VECNUM_KRD 3 /* Kasumi Ready for data */ -#define VECNUM_KDA 4 /* Kasumi Data Available */ -#define VECNUM_PCRW 5 /* PCI command register write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_IIC1 7 /* IIC */ -#define VECNUM_SPI 8 /* SPI */ -#define VECNUM_EPCISER 9 /* External PCI SERR */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UD0 16 /* UDMA irq 0 */ -#define VECNUM_UD1 17 /* UDMA irq 1 */ -#define VECNUM_UD2 18 /* UDMA irq 2 */ -#define VECNUM_UD3 19 /* UDMA irq 3 */ -#define VECNUM_HSB2D 20 /* USB2.0 Device */ -#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ -#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ -#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ -#define VECNUM_EIP94 23 /* Security EIP94 */ -#define VECNUM_ETH0 24 /* Emac 0 */ -#define VECNUM_ETH1 25 /* Emac 1 */ -#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0) /* MAL SERR */ -#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ -#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ -#define VECNUM_U2 (32 + 3) /* UART 2 */ -#define VECNUM_U3 (32 + 4) /* UART 3 */ -#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ -#define VECNUM_NDFC (32 + 6) /* NDFC */ -#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ -#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ -#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ -#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ -#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ -#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ -#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ -#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ -#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ -#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ -#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ -#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ -#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ -#define VECNUM_SRE (32 + 24) /* Serial ROM error */ -#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ -#define VECNUM_RSVD0 (32 + 26) /* Reserved */ -#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ -#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ -#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ -#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ +/* + * Define the number of UIC's + */ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define UIC_MAX 4 +#elif defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) +#define UIC_MAX 3 +#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UIC_MAX 2 +#else +#define UIC_MAX 1 +#endif -#define VECNUM_TXDE VECNUM_MTDE -#define VECNUM_RXDE VECNUM_MRDE +/* + * UIC register + */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + +#define UIC0_DCR_BASE 0xc0 +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +#define UIC1_DCR_BASE 0xd0 +#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ +#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ +#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ +#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ +#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ +#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ +#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ +#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ + +#if defined(CONFIG_440GX) +#define UIC2_DCR_BASE 0x210 +#else +#define UIC2_DCR_BASE 0xe0 +#endif +#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ +#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ + +#define UIC3_DCR_BASE 0xf0 +#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ +#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ +#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ +#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ +#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ +#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ +#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ +#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ + +#if defined(CONFIG_440GX) +#define UIC_DCR_BASE 0x200 +#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ +#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ +#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ +#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ +#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ +#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ +#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ +#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration*/ +#endif /* CONFIG_440GX */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ -#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ -#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ -#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ -#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ -#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ -#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ -#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ -#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ -#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ +/* + * Now the interrupt vector definitions. They are different for most of + * the 4xx variants, so we need some more #ifdef's here. No mask + * definitions anymore here. For this please use the UIC_MASK macro below. + * + * Note: Please only define the interrupts really used in U-Boot here. + * Those are the cascading and EMAC/MAL related interrupt. + */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_405EP) || defined(CONFIG_405GP) +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 +#endif /* defined(CONFIG_405EP) */ +#if defined(CONFIG_405EZ) +#define VECNUM_USBDEV 15 +#define VECNUM_ETH0 16 +#define VECNUM_MAL_SERR 18 +#define VECNUM_MAL_TXDE 18 +#define VECNUM_MAL_RXDE 18 +#define VECNUM_MAL_TXEOB 19 +#define VECNUM_MAL_RXEOB 21 +#endif /* CONFIG_405EX */ + +#if defined(CONFIG_405EX) /* UIC 0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 8 /* PCI MSI level 0 */ -#define VECNUM_EIR0 9 /* External interrupt 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_EIR1 9 /* External interrupt 1 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC2NCI 28 +#define VECNUM_UIC2CI 29 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 /* UIC 1 */ -#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ -#define VECNUM_U0 (32 + 1) /* UART0 */ -#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ -#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ -#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ -#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ -#define VECNUM_U2 (32 + 28) /* UART2 */ -#define VECNUM_U3 (32 + 29) /* UART3 */ -#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */ - -/* UIC 2 */ -#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ -#define VECNUM_MS (64 + 3) /* MAL SERR */ -#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ -#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ -#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ -#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ -#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ -#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */ -#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */ -#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */ -#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */ -#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */ -#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */ -#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */ -#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */ -#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */ - -/* UIC 3 */ -#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ -#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ -#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ -#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ -#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ -#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ -#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ -#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ -#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ -#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */ -#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */ -#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */ - -#elif defined(CONFIG_440SPE) +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#endif /* CONFIG_405EX */ +#if defined(CONFIG_440GP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) /* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 /* UIC 1 */ -#define VECNUM_MS (32 + 1 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */ -#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */ -#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */ -#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */ -#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */ -#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */ - -#elif defined(CONFIG_440SP) - +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#define VECNUM_USBDEV (32 + 23) +#define VECNUM_ETH0 (32 + 28) +#define VECNUM_ETH1_OFFS 2 +#endif /* CONFIG_440GP */ + +#if defined(CONFIG_440GX) /* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 /* UIC 1 */ -#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ -#define VECNUM_MS (32 + 1) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -#elif defined(CONFIG_440) +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#define VECNUM_ETH0 (32 + 28) +#define VECNUM_ETH1_OFFS 2 + +/* UICB 0 (440GX only) */ +#define VECNUM_UIC0CI 0 +#define VECNUM_UIC0NCI 1 +#define VECNUM_UIC1CI 2 +#define VECNUM_UIC1NCI 3 +#define VECNUM_UIC2CI 4 +#define VECNUM_UIC2NCI 5 +#endif /* CONFIG_440GX */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_CT0 18 /* GPT compare timer 0 */ -#define VECNUM_CT1 19 /* GPT compare timer 1 */ -#define VECNUM_CT2 20 /* GPT compare timer 2 */ -#define VECNUM_CT3 21 /* GPT compare timer 3 */ -#define VECNUM_CT4 22 /* GPT compare timer 4 */ -#define VECNUM_EIR0 23 /* External interrupt 0 */ -#define VECNUM_EIR1 24 /* External interrupt 1 */ -#define VECNUM_EIR2 25 /* External interrupt 2 */ -#define VECNUM_EIR3 26 /* External interrupt 3 */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_EIR5 28 /* External interrupt 5 */ -#define VECNUM_EIR6 29 /* External interrupt 6 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_USBDEV 20 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC2NCI 28 +#define VECNUM_UIC2CI 29 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 /* UIC 1 */ -#define VECNUM_MS (32 + 0 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ -#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ - -#else /* !defined(CONFIG_440) */ - -#if defined(CONFIG_405EZ) -#define VECNUM_D0 0 /* DMA channel 0 */ -#define VECNUM_D1 1 /* DMA channel 1 */ -#define VECNUM_D2 2 /* DMA channel 2 */ -#define VECNUM_D3 3 /* DMA channel 3 */ -#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ -#define VECNUM_U0 5 /* UART0 */ -#define VECNUM_U1 6 /* UART1 */ -#define VECNUM_CAN0 7 /* CAN 0 */ -#define VECNUM_CAN1 8 /* CAN 1 */ -#define VECNUM_SPI 9 /* SPI */ -#define VECNUM_IIC0 10 /* I2C */ -#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ -#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ -#define VECNUM_USBH1 13 /* USB Host 1 */ -#define VECNUM_USBH2 14 /* USB Host 2 */ -#define VECNUM_USBDEV 15 /* USB Device */ -#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ -#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ - -#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ -#define VECNUM_MS 18 /* MAL_SERR_INT */ -#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ -#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) -#define VECNUM_MTE 19 /* MAL TXEOB */ -#define VECNUM_MTE1 20 /* MAL TXEOB1 */ -#define VECNUM_MRE 21 /* MAL RXEOB */ -#define VECNUM_NAND 22 /* NAND Flash controller */ -#define VECNUM_ADC 23 /* ADC */ -#define VECNUM_DAC 24 /* DAC */ -#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ -#define VECNUM_RESERVED0 26 /* Reserved */ -#define VECNUM_EIR0 27 /* External interrupt 0 */ -#define VECNUM_EIR1 28 /* External interrupt 1 */ -#define VECNUM_EIR2 29 /* External interrupt 2 */ -#define VECNUM_EIR3 30 /* External interrupt 3 */ -#define VECNUM_EIR4 31 /* External interrupt 4 */ +/* UIC 2 */ +#define VECNUM_EIRQ2 (64 + 3) +#endif /* CONFIG_440EPX */ -#elif defined(CONFIG_405EX) +#if defined(CONFIG_440SP) +/* UIC 0 */ +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#define VECNUM_ETH0 (32 + 28) +#endif /* CONFIG_440SP */ + +#if defined(CONFIG_440SPE) /* UIC 0 */ -#define VECNUM_U0 00 -#define VECNUM_U1 01 -#define VECNUM_IIC0 02 -#define VECNUM_PKA 03 -#define VECNUM_TRNG 04 -#define VECNUM_EBM 05 -#define VECNUM_BGI 06 -#define VECNUM_IIC1 07 -#define VECNUM_SPI 08 -#define VECNUM_EIR0 09 -#define VECNUM_MTE 10 /* MAL Tx EOB */ -#define VECNUM_MRE 11 /* MAL Rx EOB */ -#define VECNUM_DMA0 12 -#define VECNUM_DMA1 13 -#define VECNUM_DMA2 14 -#define VECNUM_DMA3 15 -#define VECNUM_PCIE0AL 16 -#define VECNUM_PCIE0VPD 17 -#define VECNUM_RPCIE0HRST 18 -#define VECNUM_FPCIE0HRST 19 -#define VECNUM_PCIE0TCR 20 -#define VECNUM_PCIEMSI0 21 -#define VECNUM_PCIEMSI1 22 -#define VECNUM_SECURITY 23 -#define VECNUM_ETH0 24 -#define VECNUM_ETH1 25 -#define VECNUM_PCIEMSI2 26 -#define VECNUM_EIR4 27 -#define VECNUM_UIC2NC 28 -#define VECNUM_UIC2C 29 -#define VECNUM_UIC1NC 30 -#define VECNUM_UIC1C 31 +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 /* UIC 1 */ -#define VECNUM_MS (32 + 00) /* MAL SERR */ -#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ -#define VECNUM_PCIE0BMVC0 (32 + 03) -#define VECNUM_PCIE0DCRERR (32 + 04) -#define VECNUM_EBC (32 + 05) -#define VECNUM_NDFC (32 + 06) -#define VECNUM_PCEI1DCRERR (32 + 07) -#define VECNUM_CT8 (32 + 08) -#define VECNUM_CT9 (32 + 09) -#define VECNUM_PCIE1AL (32 + 10) -#define VECNUM_PCIE1VPD (32 + 11) -#define VECNUM_RPCE1HRST (32 + 12) -#define VECNUM_FPCE1HRST (32 + 13) -#define VECNUM_PCIE1TCR (32 + 14) -#define VECNUM_PCIE1VC0 (32 + 15) -#define VECNUM_CT3 (32 + 16) -#define VECNUM_CT4 (32 + 17) -#define VECNUM_EIR7 (32 + 18) -#define VECNUM_EIR8 (32 + 19) -#define VECNUM_EIR9 (32 + 20) -#define VECNUM_CT5 (32 + 21) -#define VECNUM_CT6 (32 + 22) -#define VECNUM_CT7 (32 + 23) -#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ -#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ -#define VECNUM_EIR2 (32 + 26) -#define VECNUM_EIR5 (32 + 27) -#define VECNUM_EIR6 (32 + 28) -#define VECNUM_EMAC0WAKE (32 + 29) -#define VECNUM_EIR1 (32 + 30) -#define VECNUM_EMAC1WAKE (32 + 31) +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#define VECNUM_ETH0 (32 + 28) +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 /* UIC 2 */ -#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ -#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ -#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ -#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ -#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ -#define VECNUM_DDRMCUE (64 + 05) -#define VECNUM_DDRMCCE (64 + 06) -#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ -#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ -#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ -#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ -#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ -#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ -#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ -#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ -#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ -#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ -#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ -#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ -#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ -#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ -#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ -#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ -#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ -#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ -#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ -#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ -#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ -#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ -#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ -#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ -#define VECNUM_USBOTG (64 + 31) /* USB OTG */ +#define VECNUM_MAL_SERR (64 + 3) +#define VECNUM_MAL_TXDE (64 + 4) +#define VECNUM_MAL_RXDE (64 + 5) +#define VECNUM_MAL_TXEOB (64 + 6) +#define VECNUM_MAL_RXEOB (64 + 7) +#define VECNUM_ETH0 (64 + 16) +#define VECNUM_ETH1_OFFS 1 +#endif /* CONFIG_460EX */ + +#if !defined(VECNUM_ETH1_OFFS) +#define VECNUM_ETH1_OFFS 1 +#endif -#else /* !CONFIG_405EZ */ - -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_D0 5 /* DMA channel 0 */ -#define VECNUM_D1 6 /* DMA channel 1 */ -#define VECNUM_D2 7 /* DMA channel 2 */ -#define VECNUM_D3 8 /* DMA channel 3 */ -#define VECNUM_EWU0 9 /* Ethernet wakeup */ -#define VECNUM_MS 10 /* MAL SERR */ -#define VECNUM_MTE 11 /* MAL TXEOB */ -#define VECNUM_MRE 12 /* MAL RXEOB */ -#define VECNUM_TXDE 13 /* MAL TXDE */ -#define VECNUM_RXDE 14 /* MAL RXDE */ -#define VECNUM_ETH0 15 /* Ethernet interrupt status */ -#define VECNUM_EIR0 25 /* External interrupt 0 */ -#define VECNUM_EIR1 26 /* External interrupt 1 */ -#define VECNUM_EIR2 27 /* External interrupt 2 */ -#define VECNUM_EIR3 28 /* External interrupt 3 */ -#define VECNUM_EIR4 29 /* External interrupt 4 */ -#define VECNUM_EIR5 30 /* External interrupt 5 */ -#define VECNUM_EIR6 31 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - -#endif /* defined(CONFIG_440) */ +/* + * Mask definitions (used for example in 4xx_enet.c) + */ +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +#define UIC_NR(vec) ((vec) >> 5) #endif /* _PPC4xx_UIC_H_ */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 8ea1ac37d15..9bcbfe3b7d9 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -407,7 +407,7 @@ /* * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high */ -#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) +#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) /*----------------------------------------------------------------------- * FPGA stuff diff --git a/include/ppc405.h b/include/ppc405.h index fee4ee5b53f..f19b67f1bb7 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -119,253 +119,6 @@ #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ -/****************************************************************************** - * Universal interrupt controller - ******************************************************************************/ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define UIC_DCR_BASE 0xc0 -#define UIC0_DCR_BASE UIC_DCR_BASE -#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ -#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ -#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ -#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ -#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ -#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ -#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ -#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ -#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ - -#if defined(CONFIG_405EX) -#define uic0sr uicsr /* UIC status */ -#define uic0srs uicsrs /* UIC status set */ -#define uic0er uicer /* UIC enable */ -#define uic0cr uiccr /* UIC critical */ -#define uic0pr uicpr /* UIC polarity */ -#define uic0tr uictr /* UIC triggering */ -#define uic0msr uicmsr /* UIC masked status */ -#define uic0vr uicvr /* UIC vector */ -#define uic0vcr uicvcr /* UIC vector configuration*/ - -#define UIC_DCR_BASE1 0xd0 -#define UIC1_DCR_BASE 0xd0 -#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ -#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ -#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ -#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ -#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ -#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ -#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ -#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ -#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ - -#define UIC_DCR_BASE2 0xe0 -#define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ -#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ -#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ -#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ -#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ -#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ -#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ -#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ -#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ -#endif - -/*-----------------------------------------------------------------------------+ -| Universal interrupt controller interrupts -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_405EZ) -#define UIC_DMA0 0x80000000 /* DMA chan. 0 */ -#define UIC_DMA1 0x40000000 /* DMA chan. 1 */ -#define UIC_DMA2 0x20000000 /* DMA chan. 2 */ -#define UIC_DMA3 0x10000000 /* DMA chan. 3 */ -#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ -#define UIC_UART0 0x04000000 /* UART 0 */ -#define UIC_UART1 0x02000000 /* UART 1 */ -#define UIC_CAN0 0x01000000 /* CAN 0 */ -#define UIC_CAN1 0x00800000 /* CAN 1 */ -#define UIC_SPI 0x00400000 /* SPI */ -#define UIC_IIC 0x00200000 /* IIC */ -#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ -#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ -#define UIC_USBH1 0x00040000 /* USB Host 1 */ -#define UIC_USBH2 0x00020000 /* USB Host 2 */ -#define UIC_USBDEV 0x00010000 /* USB Device */ -#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ -#define UIC_ENET1 0x00008000 /* dummy define */ -#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ - -#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ -#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ -#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ -#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ - -#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ -#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ -#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ -#define UIC_NAND 0x00000200 /* NAND Flash controller */ -#define UIC_ADC 0x00000100 /* ADC */ -#define UIC_DAC 0x00000080 /* DAC */ -#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ -#define UIC_RESERVED0 0x00000020 /* Reserved */ -#define UIC_EXT0 0x00000010 /* External interrupt 0 */ -#define UIC_EXT1 0x00000008 /* External interrupt 1 */ -#define UIC_EXT2 0x00000004 /* External interrupt 2 */ -#define UIC_EXT3 0x00000002 /* External interrupt 3 */ -#define UIC_EXT4 0x00000001 /* External interrupt 4 */ - -#elif defined(CONFIG_405EX) - -/* UIC 0 */ -#define UIC_U0 0x80000000 /* */ -#define UIC_U1 0x40000000 /* */ -#define UIC_IIC0 0x20000000 /* */ -#define UIC_PKA 0x10000000 /* */ -#define UIC_TRNG 0x08000000 /* */ -#define UIC_EBM 0x04000000 /* */ -#define UIC_BGI 0x02000000 /* */ -#define UIC_IIC1 0x01000000 /* */ -#define UIC_SPI 0x00800000 /* */ -#define UIC_EIRQ0 0x00400000 /**/ -#define UIC_MTE 0x00200000 /*MAL Tx EOB */ -#define UIC_MRE 0x00100000 /*MAL Rx EOB */ -#define UIC_DMA0 0x00080000 /* */ -#define UIC_DMA1 0x00040000 /* */ -#define UIC_DMA2 0x00020000 /* */ -#define UIC_DMA3 0x00010000 /* */ -#define UIC_PCIE0AL 0x00008000 /* */ -#define UIC_PCIE0VPD 0x00004000 /* */ -#define UIC_RPCIE0HRST 0x00002000 /* */ -#define UIC_FPCIE0HRST 0x00001000 /* */ -#define UIC_PCIE0TCR 0x00000800 /* */ -#define UIC_PCIEMSI0 0x00000400 /* */ -#define UIC_PCIEMSI1 0x00000200 /* */ -#define UIC_SECURITY 0x00000100 /* */ -#define UIC_ENET 0x00000080 /* */ -#define UIC_ENET1 0x00000040 /* */ -#define UIC_PCIEMSI2 0x00000020 /* */ -#define UIC_EIRQ4 0x00000010 /**/ -#define UICB0_UIC2NCI 0x00000008 /* */ -#define UICB0_UIC2CI 0x00000004 /* */ -#define UICB0_UIC1NCI 0x00000002 /* */ -#define UICB0_UIC1CI 0x00000001 /* */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) - -#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ -#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ -/* UIC 1 */ -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_PCIE0BMVC0 0x10000000 /* */ -#define UIC_PCIE0DCRERR 0x08000000 /* */ -#define UIC_EBC 0x04000000 /* */ -#define UIC_NDFC 0x02000000 /* */ -#define UIC_PCEI1DCRERR 0x01000000 /* */ -#define UIC_GPTCMPT8 0x00800000 /* */ -#define UIC_GPTCMPT9 0x00400000 /* */ -#define UIC_PCIE1AL 0x00200000 /* */ -#define UIC_PCIE1VPD 0x00100000 /* */ -#define UIC_RPCE1HRST 0x00080000 /* */ -#define UIC_FPCE1HRST 0x00040000 /* */ -#define UIC_PCIE1TCR 0x00020000 /* */ -#define UIC_PCIE1VC0 0x00010000 /* */ -#define UIC_GPTCMPT3 0x00008000 /* */ -#define UIC_GPTCMPT4 0x00004000 /* */ -#define UIC_EIRQ7 0x00002000 /* */ -#define UIC_EIRQ8 0x00001000 /* */ -#define UIC_EIRQ9 0x00000800 /* */ -#define UIC_GPTCMP5 0x00000400 /* */ -#define UIC_GPTCMP6 0x00000200 /* */ -#define UIC_GPTCMP7 0x00000100 /* */ -#define UIC_SROM 0x00000080 /* SERIAL ROM*/ -#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ -#define UIC_EIRQ2 0x00000020 /* */ -#define UIC_EIRQ5 0x00000010 /* */ -#define UIC_EIRQ6 0x00000008 /* */ -#define UIC_EMAC0WAKE 0x00000004 /* */ -#define UIC_EIRQ1 0x00000002 /* */ -#define UIC_EMAC1WAKE 0x00000001 /* */ -#define UIC_MAL_SERR UIC_MS /* MAL SERR */ -#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ -#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ -/* UIC 2 */ -#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ -#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ -#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ -#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ -#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ -#define UIC_DDRMCUE 0x04000000 /* */ -#define UIC_DDRMCCE 0x02000000 /* */ -#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ -#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ -#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ -#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ -#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ -#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ -#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ -#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ -#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ -#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ -#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ -#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ -#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ -#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ -#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ -#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ -#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ -#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ -#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ -#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ -#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ -#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ -#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ -#define UIC_USBWAKE 0x00000002 /* USB wakup*/ -#define UIC_USBOTG 0x00000001 /* USB OTG*/ -#define UIC_ETH0 UIC_ENET -#define UIC_ETH1 UIC_ENET1 - -#else /* !defined(CONFIG_405EZ) */ - -#define UIC_UART0 0x80000000 /* UART 0 */ -#define UIC_UART1 0x40000000 /* UART 1 */ -#define UIC_IIC 0x20000000 /* IIC */ -#define UIC_EXT_MAST 0x10000000 /* External Master */ -#define UIC_PCI 0x08000000 /* PCI write to command reg */ -#define UIC_DMA0 0x04000000 /* DMA chan. 0 */ -#define UIC_DMA1 0x02000000 /* DMA chan. 1 */ -#define UIC_DMA2 0x01000000 /* DMA chan. 2 */ -#define UIC_DMA3 0x00800000 /* DMA chan. 3 */ -#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ -#define UIC_MAL_SERR 0x00200000 /* MAL SERR */ -#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ -#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ -#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ -#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ -#define UIC_ENET 0x00010000 /* Ethernet0 */ -#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ -#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ -#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ -#define UIC_PCI_PM 0x00002000 /* PCI Power Management */ -#define UIC_EXT0 0x00000040 /* External interrupt 0 */ -#define UIC_EXT1 0x00000020 /* External interrupt 1 */ -#define UIC_EXT2 0x00000010 /* External interrupt 2 */ -#define UIC_EXT3 0x00000008 /* External interrupt 3 */ -#define UIC_EXT4 0x00000004 /* External interrupt 4 */ -#define UIC_EXT5 0x00000002 /* External interrupt 5 */ -#define UIC_EXT6 0x00000001 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller diff --git a/include/ppc440.h b/include/ppc440.h index f843792443a..5df8eb0d13f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -864,98 +864,6 @@ #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ -/*----------------------------------------------------------------------------- - | Universal interrupt controller - +----------------------------------------------------------------------------*/ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define UIC0_DCR_BASE 0xc0 -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ - -#define UIC1_DCR_BASE 0xd0 -#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ -#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ -#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ -#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ -#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ -#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ -#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ -#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ - -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - -#define UIC3_DCR_BASE 0xf0 -#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ -#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ -#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ -#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ -#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ -#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ -#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ -#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_440GX) -#define UIC2_DCR_BASE 0x210 -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - - -#define UIC_DCR_BASE 0x200 -#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ -#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ -#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ -#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ -#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ -#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ -#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ -#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ -#endif /* CONFIG_440GX */ - -/* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr - #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. @@ -1139,622 +1047,6 @@ #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ #endif /* CONFIG_440GX */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 0 interrupts (UIC0) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI0 inbound message */ -#define UIC_PCRW 0x04000000 /* PCI0 command write register */ -#define UIC_PPM 0x02000000 /* PCI0 power management */ -#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */ -#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */ -#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */ -#define UIC_P1CRW 0x00200000 /* PCI1 command write register */ -#define UIC_P1PM 0x00100000 /* PCI1 power management */ -#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */ -#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */ -#define UIC_P2IM 0x00020000 /* PCI2 inbound message */ -#define UIC_P2CRW 0x00010000 /* PCI2 command register write */ -#define UIC_P2PM 0x00008000 /* PCI2 power management */ -#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */ -#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */ -#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */ -#define UIC_D0CSF 0x00000800 /* DMA0 command status */ -#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */ -#define UIC_D1CSF 0x00000200 /* DMA1 command status */ -#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */ -#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */ -#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */ -#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */ -#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */ -#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */ -#define UIC_GPTCT 0x00000004 /* GPT count timer */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_RSVD0 0x00008000 /* Reserved */ -#define UIC_RSVD1 0x00004000 /* Reserved */ -#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ -#define UIC_EIR0 0x00000100 /* External interrupt 0 */ -#define UIC_EIR1 0x00000080 /* External interrupt 1 */ -#define UIC_EIR2 0x00000040 /* External interrupt 2 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_EIR5 0x00000008 /* External interrupt 5 */ -#define UIC_EIR6 0x00000004 /* External interrupt 6 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_KRD 0x10000000 /* Kasumi Ready for data */ -#define UIC_KDA 0x08000000 /* Kasumi Data Available */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_IIC1 0x01000000 /* IIC */ -#define UIC_SPI 0x00800000 /* SPI */ -#define UIC_EPCISER 0x00400000 /* External PCI SERR */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_UD0 0x00008000 /* UDMA irq 0 */ -#define UIC_UD1 0x00004000 /* UDMA irq 1 */ -#define UIC_UD2 0x00002000 /* UDMA irq 2 */ -#define UIC_UD3 0x00001000 /* UDMA irq 3 */ -#define UIC_HSB2D 0x00000800 /* USB2.0 Device */ -#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */ -#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */ -#define UIC_EIP94 0x00000100 /* Security EIP94 */ -#define UIC_ETH0 0x00000080 /* Emac 0 */ -#define UIC_ETH1 0x00000040 /* Emac 1 */ -#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */ -#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -/* For compatibility with 405 code */ -#define UIC_MAL_TXEOB UIC_MTE -#define UIC_MAL_RXEOB UIC_MRE - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_RSVD0 0x80000000 /* N/A - unused */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_PCIVPD 0x01000000 /* PCI VPD */ -#define UIC_MSI0 0x00800000 /* PCI MSI level 0 */ -#define UIC_EIR0 0x00400000 /* External interrupt 0 */ -#define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */ -#define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */ -#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */ -#define UIC_EIR1 0x00002000 /* External interrupt 1 */ -#define UIC_TRNGDA 0x00001000 /* TRNG data available */ -#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */ -#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ -#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ -#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ -#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ -#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ -#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ -#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ -#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ -#define UIC_EIP94 0x00000004 /* Security EIP94 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -#elif !defined(CONFIG_440SPE) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_RSVD0 0x00008000 /* Reserved */ -#define UIC_RSVD1 0x00004000 /* Reserved */ -#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ -#define UIC_EIR0 0x00000100 /* External interrupt 0 */ -#define UIC_EIR1 0x00000080 /* External interrupt 1 */ -#define UIC_EIR2 0x00000040 /* External interrupt 2 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_EIR5 0x00000008 /* External interrupt 5 */ -#define UIC_EIR6 0x00000004 /* External interrupt 6 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#endif /* CONFIG_440GX */ - -/* For compatibility with 405 code */ -#define UIC_MAL_TXEOB UIC_MTE -#define UIC_MAL_RXEOB UIC_MRE - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 1 interrupts (UIC1) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define UIC_EIR0 0x80000000 /* External interrupt 0 */ -#define UIC_MS 0x40000000 /* MAL SERR */ -#define UIC_MTDE 0x20000000 /* MAL TXDE */ -#define UIC_MRDE 0x10000000 /* MAL RXDE */ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ -#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */ -#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_EIR1 0x00004000 /* External interrupt 1 */ -#define UIC_EIR2 0x00002000 /* External interrupt 2 */ -#define UIC_EIR3 0x00001000 /* External interrupt 3 */ -#define UIC_EIR4 0x00000800 /* External interrupt 4 */ -#define UIC_EIR5 0x00000400 /* External interrupt 5 */ -#define UIC_DMAE 0x00000200 /* DMA error */ -#define UIC_I2OE 0x00000100 /* I2O error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ -#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */ -#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Reserved */ -#define UIC_XOR 0x00000001 /* XOR */ -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ -#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ -#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ -#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ -#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ -#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ -#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ -#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ -#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ -#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ -#define UIC_PPMI 0x00004000 /* PPM interrupt status */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR10 0x00000400 /* External interrupt 10 */ -#define UIC_EIR11 0x00000200 /* External interrupt 11 */ -#define UIC_EIR12 0x00000100 /* External interrupt 12 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_RSVD2 0x00000040 /* Reserved */ -#define UIC_RSVD3 0x00000020 /* Reserved */ -#define UIC_PAE 0x00000010 /* PCI asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Ethernet 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_EIR2 0x80000000 /* External interrupt 2 */ -#define UIC_U0 0x40000000 /* UART 0 */ -#define UIC_SPI 0x20000000 /* SPI */ -#define UIC_TRNGAL 0x10000000 /* TRNG alarm */ -#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_NDFC 0x02000000 /* NDFC */ -#define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */ -#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ -#define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */ -#define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_CT5 0x00004000 /* GPT compare timer 5 */ -#define UIC_CT6 0x00002000 /* GPT compare timer 6 */ -#define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */ -#define UIC_EIR3 0x00000800 /* External interrupt 3 */ -#define UIC_EIR4 0x00000400 /* External interrupt 4 */ -#define UIC_DMAE 0x00000200 /* DMA error */ -#define UIC_I2OE 0x00000100 /* I2O error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ -#define UIC_EIR5 0x00000020 /* External interrupt 5 */ -#define UIC_EIR6 0x00000010 /* External interrupt 6 */ -#define UIC_U2 0x00000008 /* UART 2 */ -#define UIC_U3 0x00000004 /* UART 3 */ -#define UIC_EIR7 0x00000002 /* External interrupt 7 */ -#define UIC_EIR8 0x00000001 /* External interrupt 8 */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_U2 0x10000000 /* UART 2 */ -#define UIC_U3 0x08000000 /* UART 3 */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_NDFC 0x02000000 /* NDFC */ -#define UIC_KSLE 0x01000000 /* KASUMI slave error */ -#define UIC_CT5 0x00800000 /* GPT compare timer 5 */ -#define UIC_CT6 0x00400000 /* GPT compare timer 6 */ -#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */ -#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */ -#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */ -#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */ -#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */ -#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */ -#define UIC_CT0 0x00008000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00004000 /* GPT compare timer 1 */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_CT2 0x00000400 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000200 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000100 /* GPT compare timer 4 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */ -#define UIC_RSVD0 0x00000020 /* Reserved */ -#define UIC_EPCIPER 0x00000010 /* External PCI PERR */ -#define UIC_EIR0 0x00000008 /* External interrupt 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_EIR1 0x00000002 /* External interrupt 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ - -/* For compatibility with 405 code */ -#define UIC_MAL_SERR UIC_MS -#define UIC_MAL_TXDE UIC_MTDE -#define UIC_MAL_RXDE UIC_MRDE -#define UIC_ENET UIC_ETH0 - -#elif !defined(CONFIG_440SPE) -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ -#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ -#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ -#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ -#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ -#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ -#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ -#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ -#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ -#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ -#define UIC_PPMI 0x00004000 /* PPM interrupt status */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR10 0x00000400 /* External interrupt 10 */ -#define UIC_EIR11 0x00000200 /* External interrupt 11 */ -#define UIC_EIR12 0x00000100 /* External interrupt 12 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_RSVD2 0x00000040 /* Reserved */ -#define UIC_RSVD3 0x00000020 /* Reserved */ -#define UIC_PAE 0x00000010 /* PCI asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Ethernet 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ -#endif /* CONFIG_440SP */ - -/* For compatibility with 405 code */ -#define UIC_MAL_SERR UIC_MS -#define UIC_MAL_TXDE UIC_MTDE -#define UIC_MAL_RXDE UIC_MRDE -#define UIC_ENET UIC_ETH0 - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 2 interrupts (UIC2) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) -#define UIC_ETH2 0x80000000 /* Ethernet 2 */ -#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ -#define UIC_ETH3 0x20000000 /* Ethernet 3 */ -#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ -#define UIC_TAH0 0x08000000 /* TAH 0 */ -#define UIC_TAH1 0x04000000 /* TAH 1 */ -#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ -#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ -#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ -#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ -#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ -#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ -#define UIC_IMUTO 0x00080000 /* IMU timeout */ -#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ -#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ -#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ -#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ -#define UIC_EIR13 0x00004000 /* External interrupt 13 */ -#define UIC_EIR14 0x00002000 /* External interrupt 14 */ -#define UIC_EIR15 0x00001000 /* External interrupt 15 */ -#define UIC_EIR16 0x00000800 /* External interrupt 16 */ -#define UIC_EIR17 0x00000400 /* External interrupt 17 */ -#define UIC_PCIVPD 0x00000200 /* PCI VPD */ -#define UIC_L2C 0x00000100 /* L2 Cache */ -#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ -#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ -#define UIC_RSVD26 0x00000020 /* Reserved */ -#define UIC_RSVD27 0x00000010 /* Reserved */ -#define UIC_RSVD28 0x00000008 /* Reserved */ -#define UIC_RSVD29 0x00000004 /* Reserved */ -#define UIC_RSVD30 0x00000002 /* Reserved */ -#define UIC_RSVD31 0x00000001 /* Reserved */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_TAH0 0x80000000 /* TAHOE 0 */ -#define UIC_TAH1 0x40000000 /* TAHOE 1 */ -#define UIC_EIR9 0x20000000 /* External interrupt 9 */ -#define UIC_MS 0x10000000 /* MAL SERR */ -#define UIC_MTDE 0x08000000 /* MAL TXDE */ -#define UIC_MRDE 0x04000000 /* MAL RXDE */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */ -#define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */ -#define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */ -#define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */ -#define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */ -#define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */ -#define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */ -#define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */ -#define UIC_ETH0 0x00008000 /* Ethernet 0 */ -#define UIC_ETH1 0x00004000 /* Ethernet 1 */ -#define UIC_ETH2 0x00002000 /* Ethernet 2 */ -#define UIC_ETH3 0x00001000 /* Ethernet 3 */ -#define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */ -#define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */ -#define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */ -#define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */ -#define UIC_EIR10 0x00000080 /* External interrupt 10 */ -#define UIC_EIR11 0x00000040 /* External interrupt 11 */ -#define UIC_RSVD2 0x00000020 /* Reserved */ -#define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */ -#define UIC_OTG 0x00000008 /* USB2.0 OTG */ -#define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */ -#define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */ -#define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ - -#define UIC_EIR5 0x80000000 /* External interrupt 5 */ -#define UIC_EIR6 0x40000000 /* External interrupt 6 */ -#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_EIR2 0x10000000 /* External interrupt 2 */ -#define UIC_EIR3 0x08000000 /* External interrupt 3 */ -#define UIC_DDR2 0x04000000 /* DDR2 sdram */ -#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */ -#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */ -#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */ -#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */ - -#endif /* CONFIG_440GX */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller Base 0 interrupts (UICB0) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) -#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ -#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ - UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) - -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */ -#define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ - UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) - -#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) - -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI) - -#endif /* CONFIG_440GX */ -/*---------------------------------------------------------------------------+ -| Universal interrupt controller interrupts -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) -/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */ -/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */ -#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */ -#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ - UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 0 interrupts (UIC0) -+---------------------------------------------------------------------------*/ -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */ -#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */ -#define UIC_EIR15 0x00400000 /* External intp 15 */ -#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */ -#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */ -#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */ -#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */ -#define UIC_EIR14 0x00002000 /* External interrupt 14 */ -#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */ -#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */ -#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ -#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ -#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ -#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ -#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ -#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ -#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ -#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ -#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */ -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 1 interrupts (UIC1) -+---------------------------------------------------------------------------*/ -#define UIC_EIR13 0x80000000 /* externei intp 13 */ -#define UIC_MS 0x40000000 /* MAL SERR */ -#define UIC_MTDE 0x20000000 /* MAL TXDE */ -#define UIC_MRDE 0x10000000 /* MAL RXDE */ -#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_EIR12 0x00004000 /* External interrupt 12 */ -#define UIC_EIR11 0x00002000 /* External interrupt 11 */ -#define UIC_EIR10 0x00001000 /* External interrupt 10 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR8 0x00000400 /* External interrupt 8 */ -#define UIC_DMAE 0x00000200 /* dma error */ -#define UIC_I2OE 0x00000100 /* i2o error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */ -#define UIC_EIR7 0x00000020 /* External interrupt 7 */ -#define UIC_EIR6 0x00000010 /* External interrupt 6 */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* reserved */ -#define UIC_XOR 0x00000001 /* xor */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 2 interrupts (UIC2) -+---------------------------------------------------------------------------*/ -#define UIC_PEOAL 0x80000000 /* PE0 AL */ -#define UIC_PEOVA 0x40000000 /* PE0 VPD access */ -#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */ -#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */ -#define UIC_PE0TCR 0x08000000 /* PE0 TCR */ -#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */ -#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */ -#define UIC_PE1AL 0x00800000 /* PE1 AL */ -#define UIC_PE1VA 0x00400000 /* PE1 VPD access */ -#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */ -#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */ -#define UIC_PE1TCR 0x00080000 /* PE1 TCR */ -#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */ -#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */ -#define UIC_PE2AL 0x00008000 /* PE2 AL */ -#define UIC_PE2VA 0x00004000 /* PE2 VPD access */ -#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */ -#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */ -#define UIC_PE2TCR 0x00000800 /* PE2 TCR */ -#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */ -#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */ -#define UIC_EIR5 0x00000080 /* External interrupt 5 */ -#define UIC_EIR4 0x00000040 /* External interrupt 4 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR2 0x00000010 /* External interrupt 2 */ -#define UIC_EIR1 0x00000008 /* External interrupt 1 */ -#define UIC_EIR0 0x00000004 /* External interrupt 0 */ -#endif /* CONFIG_440SPE */ - /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ -- cgit v1.3.1 From 5de851403b01489b493fa83137ad990b8ce60d1c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Jun 2008 17:36:39 +0200 Subject: ppc4xx: Rework 440GX UIC handling This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese --- board/amcc/ocotea/ocotea.c | 50 +++++++++++-------- board/amcc/taishan/taishan.c | 50 +++++++++++-------- board/prodrive/alpr/alpr.c | 50 +++++++++++-------- board/sandburst/karef/karef.c | 50 +++++++++++-------- board/sandburst/metrobox/metrobox.c | 50 +++++++++++-------- board/xpedite1k/xpedite1k.c | 50 +++++++++++-------- cpu/ppc4xx/4xx_enet.c | 9 ++-- cpu/ppc4xx/cpu_init.c | 15 +++++- cpu/ppc4xx/interrupts.c | 97 ++++++------------------------------- include/asm-ppc/ppc4xx-uic.h | 93 +++++++++++++++++------------------ 10 files changed, 269 insertions(+), 245 deletions(-) (limited to 'include/asm-ppc') diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index eea1e1e177c..4d1d093219e 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -147,36 +147,48 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(sdr_mfr, mfr); */ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index b6c306539e4..fdd82e7ccad 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -119,36 +119,48 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ mfsdr(sdr_pfc0,reg); diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 131a62dd649..cc491d05b14 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -48,36 +48,48 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe03); /* per manual */ - mtdcr (uic0tr, 0x01c00000); /* per manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe03); /* per manual */ + mtdcr (uic1tr, 0x01c00000); /* per manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 2d71d3b2cc7..72ce976350e 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -195,36 +195,48 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ * Setup the interrupt controller polarities, triggers, etc. +-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non- critical */ - mtdcr (uic0pr, 0xfffffe03); /* polarity */ - mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc8ff); /* polarity */ - mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1cr, 0x00000000); /* all non- critical */ + mtdcr (uic1pr, 0xfffffe03); /* polarity */ + mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffff83ff); /* polarity */ - mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2pr, 0xffffc8ff); /* polarity */ + mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); - mtdcr (uicb0tr, 0x00000000); - mtdcr (uicb0vr, 0x00000001); + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffff83ff); /* polarity */ + mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); + mtdcr (uic0tr, 0x00000000); + mtdcr (uic0vr, 0x00000001); fpga_init(); diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index 97049013e1c..63c91dc59c6 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -185,36 +185,48 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ * Setup the interrupt controller polarities, triggers, etc. +-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non- critical */ - mtdcr (uic0pr, 0xfffffe03); /* polarity */ - mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc8ff); /* polarity */ - mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1cr, 0x00000000); /* all non- critical */ + mtdcr (uic1pr, 0xfffffe03); /* polarity */ + mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffff83ff); /* polarity */ - mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2pr, 0xffffc8ff); /* polarity */ + mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); - mtdcr (uicb0tr, 0x00000000); - mtdcr (uicb0vr, 0x00000001); + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffff83ff); /* polarity */ + mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); + mtdcr (uic0tr, 0x00000000); + mtdcr (uic0vr, 0x00000001); fpga_init(); diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index bc7e3bd17cb..c94a345d90d 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -59,36 +59,48 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */ + mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ LED0_ON(); diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 01712b056e0..8a3833513e2 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -169,12 +169,15 @@ * UIC. Only exception is 440GX where the EMAC interrupts are * spread over two UIC's! */ +#if defined(CONFIG_440GX) +#define UIC_BASE_MAL UIC1_DCR_BASE +#define UIC_BASE_MAL_ERR UIC2_DCR_BASE +#define UIC_BASE_EMAC UIC2_DCR_BASE +#define UIC_BASE_EMAC_B UIC3_DCR_BASE +#else #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) -#if defined(CONFIG_440GX) -#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(2)) * 0x10)) -#else #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) #endif diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index ac642790516..e2d04027815 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -138,9 +138,10 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) u32 val; #endif + reconfigure_pll(CFG_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) @@ -273,6 +274,18 @@ cpu_init_f (void) reset_4xx_watchdog(); #endif /* CONFIG_WATCHDOG */ +#if defined(CONFIG_440GX) + /* Take the GX out of compatibility mode + * Travis Sawyer, 9 Mar 2004 + * NOTE: 440gx user manual inconsistency here + * Compatibility mode and Ethernet Clock select are not + * correct in the manual + */ + mfsdr(sdr_mfr, val); + val &= ~0x10000000; + mtsdr(sdr_mfr,val); +#endif /* CONFIG_440GX */ + #if defined(CONFIG_460EX) /* * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 6dbd6d28190..8215dc652ed 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -40,14 +40,8 @@ UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \ UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI)) #elif (UIC_MAX > 2) -#if defined(CONFIG_440GX) -#define UICB0_ALL (UIC_MASK(VECNUM_UIC0CI) | UIC_MASK(VECNUM_UIC0NCI) | \ - UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ - UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) -#else #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) -#endif #elif (UIC_MAX > 1) #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI)) #else @@ -70,10 +64,6 @@ static struct irq_action irq_vecs[UIC_MAX * 32]; u32 get_dcr(u16); void set_dcr(u16, u32); -#if (UIC_MAX > 1) && !defined(CONFIG_440GX) -static void uic_cascade_interrupt(void *para); -#endif - #if defined(CONFIG_440) /* SPRN changed in 440 */ @@ -157,42 +147,19 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ set_evpr(0x00000000); -#if !defined(CONFIG_440GX) #if (UIC_MAX > 1) /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NCI, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC1CI, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0); + irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0); #endif #if (UIC_MAX > 2) - irq_install_handler(VECNUM_UIC2NCI, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC2CI, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0); + irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0); #endif #if (UIC_MAX > 3) - irq_install_handler(VECNUM_UIC3NCI, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC3CI, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0); + irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0); #endif -#else /* !defined(CONFIG_440GX) */ - /* - * ToDo: Remove this 440GX special handling: - * Move SDR0_MFR setup to cpu.c and use common code with UICB0 - * on 440GX. 2008-06-26, sr - */ - /* Take the GX out of compatibility mode - * Travis Sawyer, 9 Mar 2004 - * NOTE: 440gx user manual inconsistency here - * Compatibility mode and Ethernet Clock select are not - * correct in the manual - */ - mfsdr(sdr_mfr, val); - val &= ~0x10000000; - mtsdr(sdr_mfr,val); - - /* Enable UIC interrupts via UIC Base Enable Register */ - mtdcr(uicb0sr, UICB0_ALL); - mtdcr(uicb0er, UICB0_ALL); - /* None are critical */ - mtdcr(uicb0cr, 0); -#endif /* !defined(CONFIG_440GX) */ return (0); } @@ -243,22 +210,6 @@ static void uic_interrupt(u32 uic_base, int vec_base) } } -#if (UIC_MAX > 1) && !defined(CONFIG_440GX) -static void uic_cascade_interrupt(void *para) -{ - external_interrupt(para); -} -#endif - -#if defined(CONFIG_440GX) -/* 440GX uses base uic register */ -#define UIC_BMSR uicb0msr -#define UIC_BSR uicb0sr -#else -#define UIC_BMSR uic0msr -#define UIC_BSR uic0sr -#endif - /* * Handle external interrupts */ @@ -269,7 +220,7 @@ void external_interrupt(struct pt_regs *regs) /* * Read masked interrupt status register to determine interrupt source */ - uic_msr = mfdcr(UIC_BMSR); + uic_msr = mfdcr(uic0msr); #if (UIC_MAX > 1) if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || @@ -289,20 +240,10 @@ void external_interrupt(struct pt_regs *regs) uic_interrupt(UIC3_DCR_BASE, 96); #endif -#if defined(CONFIG_440) -#if !defined(CONFIG_440GX) if (uic_msr & ~(UICB0_ALL)) uic_interrupt(UIC0_DCR_BASE, 0); -#else - if ((UIC_MASK(VECNUM_UIC0CI) & uic_msr) || - (UIC_MASK(VECNUM_UIC0NCI) & uic_msr)) - uic_interrupt(UIC0_DCR_BASE, 0); -#endif -#else /* CONFIG_440 */ - uic_interrupt(UIC0_DCR_BASE, 0); -#endif /* CONFIG_440 */ - mtdcr(UIC_BSR, uic_msr); + mtdcr(uic0sr, uic_msr); return; } @@ -312,8 +253,6 @@ void external_interrupt(struct pt_regs *regs) */ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) { - int i; - /* * Print warning when replacing with a different irq vector */ @@ -324,20 +263,19 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) irq_vecs[vec].handler = handler; irq_vecs[vec].arg = arg; - i = vec & 0x1f; if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i)); + mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec)); #if (UIC_MAX > 1) else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i)); + mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec)); #endif #if (UIC_MAX > 2) else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i)); + mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec)); #endif #if (UIC_MAX > 3) else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i)); + mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); #endif debug("Install interrupt for vector %d ==> %p\n", vec, handler); @@ -345,25 +283,22 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) void irq_free_handler (int vec) { - int i; - debug("Free interrupt for vector %d ==> %p\n", vec, irq_vecs[vec].handler); - i = vec & 0x1f; if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i)); + mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec)); #if (UIC_MAX > 1) else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i)); + mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec)); #endif #if (UIC_MAX > 2) else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i)); + mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec)); #endif #if (UIC_MAX > 3) else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i)); + mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec)); #endif irq_vecs[vec].handler = NULL; diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h index b596f0edfb8..eeaaa493efe 100644 --- a/include/asm-ppc/ppc4xx-uic.h +++ b/include/asm-ppc/ppc4xx-uic.h @@ -29,11 +29,10 @@ /* * Define the number of UIC's */ -#if defined(CONFIG_440SPE) || \ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UIC_MAX 4 -#elif defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) #define UIC_MAX 3 #elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ @@ -55,7 +54,23 @@ #define UIC_VR 0x7 /* UIC vector */ #define UIC_VCR 0x8 /* UIC vector configuration */ +/* + * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's + * are cascaded on. With this trick we can use the common UIC code for 440GX + * too. + */ +#if defined(CONFIG_440GX) +#define UIC0_DCR_BASE 0x200 +#define UIC1_DCR_BASE 0xc0 +#define UIC2_DCR_BASE 0xd0 +#define UIC3_DCR_BASE 0x210 +#else #define UIC0_DCR_BASE 0xc0 +#define UIC1_DCR_BASE 0xd0 +#define UIC2_DCR_BASE 0xe0 +#define UIC3_DCR_BASE 0xf0 +#endif + #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ @@ -65,7 +80,6 @@ #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ -#define UIC1_DCR_BASE 0xd0 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ @@ -75,11 +89,6 @@ #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ -#if defined(CONFIG_440GX) -#define UIC2_DCR_BASE 0x210 -#else -#define UIC2_DCR_BASE 0xe0 -#endif #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ @@ -90,7 +99,6 @@ #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ -#define UIC3_DCR_BASE 0xf0 #define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ #define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ #define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ @@ -101,27 +109,15 @@ #define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ #define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ -#if defined(CONFIG_440GX) -#define UIC_DCR_BASE 0x200 -#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ -#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ -#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ -#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ -#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ -#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ -#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ -#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration*/ -#endif /* CONFIG_440GX */ - /* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr /* * Now the interrupt vector definitions. They are different for most of @@ -188,24 +184,28 @@ #endif /* CONFIG_440GP */ #if defined(CONFIG_440GX) -/* UIC 0 */ -#define VECNUM_MAL_TXEOB 10 -#define VECNUM_MAL_RXEOB 11 +/* UICB 0 (440GX only) */ +/* + * All those defines below are off-by-one, so that the common UIC code + * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc. + */ +#define VECNUM_UIC1CI 0 +#define VECNUM_UIC1NCI 1 +#define VECNUM_UIC2CI 2 +#define VECNUM_UIC2NCI 3 +#define VECNUM_UIC3CI 4 +#define VECNUM_UIC3NCI 5 -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 0) -#define VECNUM_MAL_TXDE (32 + 1) -#define VECNUM_MAL_RXDE (32 + 2) -#define VECNUM_ETH0 (32 + 28) -#define VECNUM_ETH1_OFFS 2 +/* UIC 0, used as UIC1 on 440GX because of UICB0 */ +#define VECNUM_MAL_TXEOB (32 + 10) +#define VECNUM_MAL_RXEOB (32 + 11) -/* UICB 0 (440GX only) */ -#define VECNUM_UIC0CI 0 -#define VECNUM_UIC0NCI 1 -#define VECNUM_UIC1CI 2 -#define VECNUM_UIC1NCI 3 -#define VECNUM_UIC2CI 4 -#define VECNUM_UIC2NCI 5 +/* UIC 1, used as UIC2 on 440GX because of UICB0 */ +#define VECNUM_MAL_SERR (64 + 0) +#define VECNUM_MAL_TXDE (64 + 1) +#define VECNUM_MAL_RXDE (64 + 2) +#define VECNUM_ETH0 (64 + 28) +#define VECNUM_ETH1_OFFS 2 #endif /* CONFIG_440GX */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -288,6 +288,7 @@ * Mask definitions (used for example in 4xx_enet.c) */ #define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ #define UIC_NR(vec) ((vec) >> 5) #endif /* _PPC4xx_UIC_H_ */ -- cgit v1.3.1 From 3a82113ed5934d498f25080441a8261fc9454b15 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 10 Jul 2008 16:37:09 +0200 Subject: ppc4xx: Add 460SX UIC defines Only the really needed ones are added (cascading and EMAC/MAL). Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-uic.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h index eeaaa493efe..d50c3635637 100644 --- a/include/asm-ppc/ppc4xx-uic.h +++ b/include/asm-ppc/ppc4xx-uic.h @@ -30,7 +30,8 @@ * Define the number of UIC's */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -280,6 +281,25 @@ #define VECNUM_ETH1_OFFS 1 #endif /* CONFIG_460EX */ +#if defined(CONFIG_460SX) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_ETH0 19 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#endif /* CONFIG_460EX */ + #if !defined(VECNUM_ETH1_OFFS) #define VECNUM_ETH1_OFFS 1 #endif -- cgit v1.3.1 From d865fd09809a3a18669f35f970781820af40e4de Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Thu, 17 Jul 2008 11:44:12 +0200 Subject: ppc4xx: CPU PPC440x5 on Virtex5 FX -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese --- cpu/ppc4xx/Makefile | 13 ++- cpu/ppc4xx/cpu.c | 8 ++ cpu/ppc4xx/interrupts.c | 178 +++++++----------------------------- cpu/ppc4xx/speed.c | 6 +- cpu/ppc4xx/uic.c | 209 +++++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/xilinx_irq.c | 100 +++++++++++++++++++++ include/asm-ppc/interrupt.h | 36 ++++++++ include/asm-ppc/ppc4xx-uic.h | 2 + include/asm-ppc/processor.h | 2 + include/asm-ppc/xilinx_irq.h | 36 ++++++++ include/ppc4xx.h | 2 + 11 files changed, 439 insertions(+), 153 deletions(-) create mode 100644 cpu/ppc4xx/uic.c create mode 100644 cpu/ppc4xx/xilinx_irq.c create mode 100644 include/asm-ppc/interrupt.h create mode 100644 include/asm-ppc/xilinx_irq.h (limited to 'include/asm-ppc') diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 800bb41d014..c773400a5de 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -35,10 +35,8 @@ SOBJS += kgdb.o COBJS := 40x_spd_sdram.o COBJS += 44x_spd_ddr.o COBJS += 44x_spd_ddr2.o -COBJS += 4xx_enet.o COBJS += 4xx_pci.o COBJS += 4xx_pcie.o -COBJS += 4xx_uart.o COBJS += bedbug_405.o COBJS += commproc.o COBJS += cpu.o @@ -47,11 +45,9 @@ COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o COBJS += ecc.o COBJS += fdt.o -COBJS += gpio.o COBJS += i2c.o COBJS += interrupts.o COBJS += iop480_uart.o -COBJS += miiphy.o COBJS += ndfc.o COBJS += sdram.o COBJS += speed.o @@ -60,6 +56,15 @@ COBJS += traps.o COBJS += usb.o COBJS += usb_ohci.o COBJS += usbdev.o +ifndef CONFIG_XILINX_440 +COBJS += 4xx_enet.o +COBJS += 4xx_uart.o +COBJS += gpio.o +COBJS += miiphy.o +COBJS += uic.o +else +COBJS += xilinx_irq.o +endif SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index ef32bc64d29..bc9335a05ea 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -279,7 +279,11 @@ int checkcpu (void) get_sys_info(&sys_info); +#if defined(CONFIG_XILINX_440) + puts("IBM PowerPC 4"); +#else puts("AMCC PowerPC 4"); +#endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ @@ -542,6 +546,10 @@ int checkcpu (void) strcpy(addstr, "No Security support"); break; + case PVR_VIRTEX5: + puts("x5 VIRTEX5"); + break; + default: printf (" UNKNOWN (PVR=%08x)", pvr); break; diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 8215dc652ed..58d1d81c7db 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -8,6 +8,10 @@ * (C) Copyright 2003 (440GX port) * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com * + * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) + * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Work supported by Qtechnology (htpp://qtec.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,23 +35,11 @@ #include #include #include +#include #include #include #include -#if (UIC_MAX > 3) -#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ - UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \ - UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI)) -#elif (UIC_MAX > 2) -#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ - UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) -#elif (UIC_MAX > 1) -#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI)) -#else -#define UICB0_ALL 0 -#endif - DECLARE_GLOBAL_DATA_PTR; /* @@ -58,11 +50,7 @@ struct irq_action { void *arg; int count; }; - -static struct irq_action irq_vecs[UIC_MAX * 32]; - -u32 get_dcr(u16); -void set_dcr(u16, u32); +static struct irq_action irq_vecs[IRQ_MAX]; #if defined(CONFIG_440) @@ -103,7 +91,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* * Mark all irqs as free */ - for (vec = 0; vec < (UIC_MAX * 32); vec++) { + for (vec = 0; vec < IRQ_MAX; vec++) { irq_vecs[vec].handler = NULL; irq_vecs[vec].arg = NULL; irq_vecs[vec].count = 0; @@ -147,110 +135,36 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ set_evpr(0x00000000); -#if (UIC_MAX > 1) - /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0); - irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0); -#endif -#if (UIC_MAX > 2) - irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0); - irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0); -#endif -#if (UIC_MAX > 3) - irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0); - irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0); -#endif + /* + *Call uic or xilinx_irq pic_enable + */ + pic_enable(); return (0); } -/* Handler for UIC interrupt */ -static void uic_interrupt(u32 uic_base, int vec_base) +void timer_interrupt_cpu(struct pt_regs *regs) { - u32 uic_msr; - u32 msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = get_dcr(uic_base + UIC_MSR); - msr_shift = uic_msr; - vec = vec_base; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs[vec].count++; - - if (irq_vecs[vec].handler != NULL) { - /* call isr */ - (*irq_vecs[vec].handler)(irq_vecs[vec].arg); - } else { - set_dcr(uic_base + UIC_ER, - get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec)); - printf("Masking bogus interrupt vector %d" - " (UIC_BASE=0x%x)\n", vec, uic_base); - } - - /* - * After servicing the interrupt, we have to remove the - * status indicator - */ - set_dcr(uic_base + UIC_SR, UIC_MASK(vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } + /* nothing to do here */ + return; } -/* - * Handle external interrupts - */ -void external_interrupt(struct pt_regs *regs) +void interrupt_run_handler(int vec) { - u32 uic_msr; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = mfdcr(uic0msr); - -#if (UIC_MAX > 1) - if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || - (UIC_MASK(VECNUM_UIC1NCI) & uic_msr)) - uic_interrupt(UIC1_DCR_BASE, 32); -#endif - -#if (UIC_MAX > 2) - if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) || - (UIC_MASK(VECNUM_UIC2NCI) & uic_msr)) - uic_interrupt(UIC2_DCR_BASE, 64); -#endif - -#if (UIC_MAX > 3) - if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) || - (UIC_MASK(VECNUM_UIC3NCI) & uic_msr)) - uic_interrupt(UIC3_DCR_BASE, 96); -#endif - - if (uic_msr & ~(UICB0_ALL)) - uic_interrupt(UIC0_DCR_BASE, 0); - - mtdcr(uic0sr, uic_msr); + irq_vecs[vec].count++; + + if (irq_vecs[vec].handler != NULL) { + /* call isr */ + (*irq_vecs[vec].handler) (irq_vecs[vec].arg); + } else { + pic_irq_disable(vec); + printf("Masking bogus interrupt vector %d\n", vec); + } + pic_irq_ack(vec); return; } -/* - * Install and free a interrupt handler. - */ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) { /* @@ -263,51 +177,19 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) irq_vecs[vec].handler = handler; irq_vecs[vec].arg = arg; - if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec)); -#if (UIC_MAX > 1) - else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec)); -#endif -#if (UIC_MAX > 2) - else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec)); -#endif -#if (UIC_MAX > 3) - else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); -#endif - - debug("Install interrupt for vector %d ==> %p\n", vec, handler); + pic_irq_enable(vec); + return; } -void irq_free_handler (int vec) +void irq_free_handler(int vec) { debug("Free interrupt for vector %d ==> %p\n", vec, irq_vecs[vec].handler); - if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec)); -#if (UIC_MAX > 1) - else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec)); -#endif -#if (UIC_MAX > 2) - else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec)); -#endif -#if (UIC_MAX > 3) - else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec)); -#endif + pic_irq_disable(vec); irq_vecs[vec].handler = NULL; irq_vecs[vec].arg = NULL; -} - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ return; } @@ -319,7 +201,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("Interrupt-Information:\n"); printf ("Nr Routine Arg Count\n"); - for (vec = 0; vec < (UIC_MAX * 32); vec++) { + for (vec = 0; vec < IRQ_MAX; vec++) { if (irq_vecs[vec].handler != NULL) { printf ("%02d %08lx %08lx %d\n", vec, diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index b86b6dece66..d21bd82dc6f 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -416,7 +416,8 @@ ulong get_PCI_freq (void) return sys_info.freqPCI; } -#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) +#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \ + && !defined(CONFIG_XILINX_440) void get_sys_info (sys_info_t * sysInfo) { unsigned long strp0; @@ -449,6 +450,8 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqUART = sysInfo->freqPLB; } #else + +#if !defined(CONFIG_XILINX_440) void get_sys_info (sys_info_t * sysInfo) { unsigned long strp0; @@ -535,6 +538,7 @@ void get_sys_info (sys_info_t * sysInfo) } #endif +#endif /* CONFIG_XILINX_440 */ #if defined(CONFIG_YUCCA) unsigned long determine_sysper(void) diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c new file mode 100644 index 00000000000..fbf0c2b6ba9 --- /dev/null +++ b/cpu/ppc4xx/uic.c @@ -0,0 +1,209 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 (440 port) + * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com + * + * (C) Copyright 2003 (440GX port) + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) + * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Work supported by Qtechnology (htpp://qtec.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#if (UIC_MAX > 3) +#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ + UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \ + UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI)) +#elif (UIC_MAX > 2) +#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ + UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) +#elif (UIC_MAX > 1) +#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI)) +#else +#define UICB0_ALL 0 +#endif + +u32 get_dcr(u16); + +DECLARE_GLOBAL_DATA_PTR; + +void pic_enable(void) +{ + +#if (UIC_MAX > 1) + /* Install the UIC1 handlers */ + irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, + 0); + irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, + 0); +#endif +#if (UIC_MAX > 2) + irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, + 0); + irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, + 0); +#endif +#if (UIC_MAX > 3) + irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, + 0); + irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, + 0); +#endif + +} + +/* Handler for UIC interrupt */ +static void uic_interrupt(u32 uic_base, int vec_base) +{ + u32 uic_msr; + u32 msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) + interrupt_run_handler(vec); + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} + +/* + * Handle external interrupts + */ +void external_interrupt(struct pt_regs *regs) +{ + u32 uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uic0msr); + +#if (UIC_MAX > 1) + if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC1NCI) & uic_msr)) + uic_interrupt(UIC1_DCR_BASE, 32); +#endif + +#if (UIC_MAX > 2) + if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC2NCI) & uic_msr)) + uic_interrupt(UIC2_DCR_BASE, 64); +#endif + +#if (UIC_MAX > 3) + if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) || + (UIC_MASK(VECNUM_UIC3NCI) & uic_msr)) + uic_interrupt(UIC3_DCR_BASE, 96); +#endif + + if (uic_msr & ~(UICB0_ALL)) + uic_interrupt(UIC0_DCR_BASE, 0); + + mtdcr(uic0sr, uic_msr); + + return; +} + +void pic_irq_ack(unsigned int vec) +{ + + if ((vec >= 0) && (vec < 32)) + mtdcr(uicsr, UIC_MASK(vec)); +#if (UIC_MAX > 1) + else if ((vec >= 32) && (vec < 64)) + mtdcr(uic1sr, UIC_MASK(vec)); +#endif +#if (UIC_MAX > 2) + else if ((vec >= 64) && (vec < 96)) + mtdcr(uic2sr, UIC_MASK(vec)); +#endif +#if (UIC_MAX > 3) + else if (vec >= 96) + mtdcr(uic3sr, UIC_MASK(vec)); +#endif +} + +/* + * Install and free a interrupt handler. + */ +void pic_irq_enable(unsigned int vec) +{ + + if ((vec >= 0) && (vec < 32)) + mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec)); +#if (UIC_MAX > 1) + else if ((vec >= 32) && (vec < 64)) + mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec)); +#endif +#if (UIC_MAX > 2) + else if ((vec >= 64) && (vec < 96)) + mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec)); +#endif +#if (UIC_MAX > 3) + else if (vec >= 96) + mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); +#endif + + debug("Install interrupt for vector %d ==> %p\n", vec, handler); +} + +void pic_irq_disable(unsigned int vec) +{ + + if ((vec >= 0) && (vec < 32)) + mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec)); +#if (UIC_MAX > 1) + else if ((vec >= 32) && (vec < 64)) + mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec)); +#endif +#if (UIC_MAX > 2) + else if ((vec >= 64) && (vec < 96)) + mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec)); +#endif +#if (UIC_MAX > 3) + else if (vec >= 96) + mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec)); +#endif + +} diff --git a/cpu/ppc4xx/xilinx_irq.c b/cpu/ppc4xx/xilinx_irq.c new file mode 100644 index 00000000000..71087771cb6 --- /dev/null +++ b/cpu/ppc4xx/xilinx_irq.c @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void pic_enable(void) +{ + debug("Xilinx PIC at 0x%8x\n", intc); + + /* + * Disable all external interrupts until they are + * explicitly requested. + */ + out_be32((u32 *) IER, 0); + + /* Acknowledge any pending interrupts just in case. */ + out_be32((u32 *) IAR, 0xffffffff); + + /* Turn on the Master Enable. */ + out_be32((u32 *) MER, 0x3UL); + + return; +} + +int xilinx_pic_irq_get(void) +{ + u32 irq; + irq = in_be32((u32 *) IVR); + + /* If no interrupt is pending then all bits of the IVR are set to 1. As + * the IVR is as many bits wide as numbers of inputs are available. + * Therefore, if all bits of the IVR are set to one, its content will + * be bigger than XPAR_INTC_MAX_NUM_INTR_INPUTS. + */ + if (irq >= XPAR_INTC_MAX_NUM_INTR_INPUTS) + irq = -1; /* report no pending interrupt. */ + + debug("get_irq: %d\n", irq); + return (irq); +} + +void pic_irq_enable(unsigned int irq) +{ + u32 mask = IRQ_MASK(irq); + debug("enable: %d\n", irq); + out_be32((u32 *) SIE, mask); +} + +void pic_irq_disable(unsigned int irq) +{ + u32 mask = IRQ_MASK(irq); + debug("disable: %d\n", irq); + out_be32((u32 *) CIE, mask); +} + +void pic_irq_ack(unsigned int irq) +{ + u32 mask = IRQ_MASK(irq); + debug("ack: %d\n", irq); + out_be32((u32 *) IAR, mask); +} + +void external_interrupt(struct pt_regs *regs) +{ + int irq; + + irq = xilinx_pic_irq_get(); + if (irq < 0) + return; + + interrupt_run_handler(irq); + + return; +} diff --git a/include/asm-ppc/interrupt.h b/include/asm-ppc/interrupt.h new file mode 100644 index 00000000000..792836b2294 --- /dev/null +++ b/include/asm-ppc/interrupt.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ +#ifndef INTERRUPT_H +#define INTERRUPT_H + +#if defined(CONFIG_XILINX_440) +#include +#else +#include +#endif + +void pic_enable(void); +void pic_irq_enable(unsigned int irq); +void pic_irq_disable(unsigned int irq); +void pic_irq_ack(unsigned int irq); +void external_interrupt(struct pt_regs *regs); +void interrupt_run_handler(int vec); + +#endif diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h index d50c3635637..c908d424525 100644 --- a/include/asm-ppc/ppc4xx-uic.h +++ b/include/asm-ppc/ppc4xx-uic.h @@ -43,6 +43,8 @@ #define UIC_MAX 1 #endif +#define IRQ_MAX UIC_MAX * 32 + /* * UIC register */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index b2148444a1f..dce4717f427 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -859,6 +859,8 @@ #define PVR_86xx 0x80040000 #define PVR_86xx_REV1 (PVR_86xx | 0x0010) +#define PVR_VIRTEX5 0x7ff21912 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h new file mode 100644 index 00000000000..ddccc750169 --- /dev/null +++ b/include/asm-ppc/xilinx_irq.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ +#ifndef XILINX_IRQ_H +#define XILINX_IRQ_H + +#define intc XPAR_INTC_0_BASEADDR +#define ISR (intc+(0*4)) /* Interrupt Status Register */ +#define IPR (intc+(1*4)) /* Interrupt Pending Register */ +#define IER (intc+(2*4)) /* Interrupt Enable Register */ +#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */ +#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */ +#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */ +#define IVR (intc+(6*4)) /* Interrupt Vector Register */ +#define MER (intc+(7*4)) /* Master Enable Register */ + +#define IRQ_MASK(irq) (1<<(irq&0x1f)) + +#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +#endif diff --git a/include/ppc4xx.h b/include/ppc4xx.h index d593b072fcd..5a6b8559168 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -54,7 +54,9 @@ #include #include +#if !defined(CONFIG_XILINX_440) #include +#endif /* * Macro for generating register field mnemonics -- cgit v1.3.1 From 60204d06ed9f8c2a67cc79eb67fd2b1d22bcbc8c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 18 Jul 2008 12:24:41 +0200 Subject: ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support Signed-off-by: Stefan Roese --- cpu/ppc4xx/interrupts.c | 2 +- cpu/ppc4xx/uic.c | 41 ++++++--------------------------------- drivers/serial/serial_xuartlite.c | 10 +++++----- include/asm-ppc/xilinx_irq.h | 22 ++++++++++----------- 4 files changed, 23 insertions(+), 52 deletions(-) (limited to 'include/asm-ppc') diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 58d1d81c7db..494bd8c9ef9 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -136,7 +136,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) set_evpr(0x00000000); /* - *Call uic or xilinx_irq pic_enable + * Call uic or xilinx_irq pic_enable */ pic_enable(); diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c index fbf0c2b6ba9..7944c6c3c2e 100644 --- a/cpu/ppc4xx/uic.c +++ b/cpu/ppc4xx/uic.c @@ -59,27 +59,19 @@ DECLARE_GLOBAL_DATA_PTR; void pic_enable(void) { - #if (UIC_MAX > 1) /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, - 0); - irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, - 0); + irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0); + irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0); #endif #if (UIC_MAX > 2) - irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, - 0); - irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, - 0); + irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0); + irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0); #endif #if (UIC_MAX > 3) - irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, - 0); - irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, - 0); + irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0); + irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0); #endif - } /* Handler for UIC interrupt */ @@ -147,21 +139,14 @@ void external_interrupt(struct pt_regs *regs) void pic_irq_ack(unsigned int vec) { - if ((vec >= 0) && (vec < 32)) mtdcr(uicsr, UIC_MASK(vec)); -#if (UIC_MAX > 1) else if ((vec >= 32) && (vec < 64)) mtdcr(uic1sr, UIC_MASK(vec)); -#endif -#if (UIC_MAX > 2) else if ((vec >= 64) && (vec < 96)) mtdcr(uic2sr, UIC_MASK(vec)); -#endif -#if (UIC_MAX > 3) else if (vec >= 96) mtdcr(uic3sr, UIC_MASK(vec)); -#endif } /* @@ -172,38 +157,24 @@ void pic_irq_enable(unsigned int vec) if ((vec >= 0) && (vec < 32)) mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec)); -#if (UIC_MAX > 1) else if ((vec >= 32) && (vec < 64)) mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec)); -#endif -#if (UIC_MAX > 2) else if ((vec >= 64) && (vec < 96)) mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec)); -#endif -#if (UIC_MAX > 3) else if (vec >= 96) mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); -#endif debug("Install interrupt for vector %d ==> %p\n", vec, handler); } void pic_irq_disable(unsigned int vec) { - if ((vec >= 0) && (vec < 32)) mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec)); -#if (UIC_MAX > 1) else if ((vec >= 32) && (vec < 64)) mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec)); -#endif -#if (UIC_MAX > 2) else if ((vec >= 64) && (vec < 96)) mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec)); -#endif -#if (UIC_MAX > 3) else if (vec >= 96) mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec)); -#endif - } diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 5c41a1c40a6..61e68873eb5 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -56,8 +56,8 @@ void serial_putc(const char c) { if (c == '\n') serial_putc('\r'); - while (in_be32(UARTLITE_STATUS) & SR_TX_FIFO_FULL); - out_be32(UARTLITE_TX_FIFO, (unsigned char) (c & 0xff)); + while (in_be32((void *)UARTLITE_STATUS) & SR_TX_FIFO_FULL); + out_be32((void *)UARTLITE_TX_FIFO, (unsigned char) (c & 0xff)); } void serial_puts(const char * s) @@ -69,13 +69,13 @@ void serial_puts(const char * s) int serial_getc(void) { - while (!(in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA)); - return in_be32(UARTLITE_RX_FIFO) & 0xff; + while (!(in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA)); + return in_be32((void *)UARTLITE_RX_FIFO) & 0xff; } int serial_tstc(void) { - return (in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA); + return (in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA); } #endif /* CONFIG_MICROBLZE */ diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h index ddccc750169..61171c21ffa 100644 --- a/include/asm-ppc/xilinx_irq.h +++ b/include/asm-ppc/xilinx_irq.h @@ -19,18 +19,18 @@ #ifndef XILINX_IRQ_H #define XILINX_IRQ_H -#define intc XPAR_INTC_0_BASEADDR -#define ISR (intc+(0*4)) /* Interrupt Status Register */ -#define IPR (intc+(1*4)) /* Interrupt Pending Register */ -#define IER (intc+(2*4)) /* Interrupt Enable Register */ -#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */ -#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */ -#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */ -#define IVR (intc+(6*4)) /* Interrupt Vector Register */ -#define MER (intc+(7*4)) /* Master Enable Register */ +#define intc XPAR_INTC_0_BASEADDR +#define ISR (intc + (0 * 4)) /* Interrupt Status Register */ +#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ +#define IER (intc + (2 * 4)) /* Interrupt Enable Register */ +#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ +#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ +#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ +#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ +#define MER (intc + (7 * 4)) /* Master Enable Register */ -#define IRQ_MASK(irq) (1<<(irq&0x1f)) +#define IRQ_MASK(irq) (1 << (irq & 0x1f)) -#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS +#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS #endif -- cgit v1.3.1 From f2302d4430e7f3f48308d6a585320fe96af8afbd Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 6 Aug 2008 14:05:38 +0200 Subject: Fix merge problems Signed-off-by: Stefan Roese --- .gitignore | 7 + CHANGELOG | 550 +++++++++++++++++++++++++++ MAKEALL | 1 - Makefile | 9 +- api/api_storage.c | 45 ++- api_examples/demo.c | 78 +++- board/adsvix/Makefile | 51 --- board/adsvix/adsvix.c | 75 ---- board/adsvix/config.mk | 1 - board/adsvix/lowlevel_init.S | 466 ----------------------- board/adsvix/pcmcia.c | 67 ---- board/adsvix/pxavoltage.S | 230 ----------- board/adsvix/u-boot.lds | 56 --- board/atmel/atngw100/atngw100.c | 2 +- board/atmel/atstk1000/atstk1000.c | 2 +- board/atmel/atstk1000/flash.c | 2 +- board/esd/common/flash.c | 2 + board/freescale/m5275evb/Makefile | 2 +- board/freescale/mpc8540ads/u-boot.lds | 37 +- board/freescale/mpc8541cds/u-boot.lds | 38 +- board/freescale/mpc8544ds/u-boot.lds | 37 +- board/freescale/mpc8548cds/u-boot.lds | 37 +- board/freescale/mpc8555cds/u-boot.lds | 38 +- board/freescale/mpc8560ads/u-boot.lds | 42 +- board/freescale/mpc8568mds/u-boot.lds | 40 +- board/idmr/mii.c | 2 +- board/ids8247/ids8247.c | 2 +- board/matrix_vision/mvbc_p/mvbc_p.c | 3 +- board/tqc/tqm85xx/tqm85xx.c | 3 +- board/w7o/post2.c | 6 + common/cmd_bdinfo.c | 2 +- common/cmd_bootm.c | 9 +- common/cmd_flash.c | 4 +- common/cmd_ide.c | 50 ++- common/cmd_mfsl.c | 6 +- common/dlmalloc.c | 21 +- common/lcd.c | 19 +- common/main.c | 4 +- cpu/microblaze/interrupts.c | 2 +- cpu/mips/au1x00_serial.c | 2 +- cpu/mpc8260/speed.c | 47 ++- cpu/nios2/interrupts.c | 1 + cpu/nios2/sysid.c | 2 +- cpu/ppc4xx/44x_spd_ddr2.c | 24 +- cpu/pxa/mmc.c | 5 - doc/README.autoboot | 15 +- doc/README.qemu_mips | 2 +- drivers/i2c/fsl_i2c.c | 18 +- drivers/mmc/atmel_mci.c | 16 +- drivers/mtd/cfi_flash.c | 5 +- drivers/mtd/spi/atmel.c | 6 +- drivers/net/e1000.c | 13 +- drivers/serial/Makefile | 12 +- drivers/serial/atmel_usart.c | 3 - drivers/serial/mcfuart.c | 3 - drivers/serial/s3c4510b_uart.c | 4 - drivers/serial/serial_max3100.c | 4 - drivers/serial/serial_xuartlite.c | 18 +- drivers/serial/usbtty.c | 5 - drivers/usb/usbdcore.c | 2 +- drivers/video/atmel_lcdfb.c | 4 + include/api_public.h | 1 + include/asm-arm/arch-at91rm9200/AT91RM9200.h | 4 +- include/asm-avr32/io.h | 2 + include/asm-avr32/sysreg.h | 6 +- include/asm-nios2/types.h | 3 + include/asm-ppc/fsl_lbc.h | 9 + include/asm-ppc/global_data.h | 3 + include/command.h | 2 + include/configs/ADS860.h | 2 +- include/configs/APC405.h | 3 +- include/configs/Adder.h | 2 +- include/configs/AmigaOneG3SE.h | 3 +- include/configs/CPCI405DT.h | 5 +- include/configs/DU440.h | 5 +- include/configs/FADS860T.h | 2 +- include/configs/GTH.h | 5 +- include/configs/KUP4K.h | 3 +- include/configs/KUP4X.h | 3 +- include/configs/MPC86xADS.h | 2 +- include/configs/MPC885ADS.h | 2 +- include/configs/MVBC_P.h | 6 +- include/configs/MVBLUE.h | 7 +- include/configs/NC650.h | 5 +- include/configs/PLU405.h | 5 +- include/configs/PMC440.h | 3 +- include/configs/RPXlite_DW.h | 3 +- include/configs/SXNI855T.h | 2 +- include/configs/adsvix.h | 365 ------------------ include/configs/apollon.h | 8 - include/configs/at91rm9200dk.h | 12 +- include/configs/atngw100.h | 4 +- include/configs/atstk1002.h | 4 +- include/configs/atstk1003.h | 4 +- include/configs/atstk1004.h | 4 +- include/configs/atstk1006.h | 4 +- include/configs/csb637.h | 13 +- include/configs/gth2.h | 5 +- include/configs/gw8260.h | 3 +- include/configs/hymod.h | 2 +- include/configs/linkstation.h | 3 +- include/configs/lwmon.h | 3 +- include/configs/lwmon5.h | 3 +- include/configs/m501sk.h | 3 +- include/configs/motionpro.h | 2 +- include/configs/mp2usb.h | 3 +- include/configs/netstar.h | 3 +- include/configs/ppmc8260.h | 3 +- include/configs/quantum.h | 3 +- include/configs/rmu.h | 3 +- include/configs/sacsng.h | 2 +- include/configs/sbc8260.h | 3 +- include/configs/sc3.h | 3 +- include/configs/trab.h | 3 +- include/configs/utx8245.h | 2 +- include/ppc4xx.h | 6 + lib_arm/board.c | 17 + lib_arm/bootm.c | 3 - lib_m68k/time.c | 5 + lib_sparc/board.c | 4 +- nand_spl/board/amcc/kilauea/Makefile | 2 +- onenand_ipl/board/apollon/Makefile | 42 +- post/cpu/ppc4xx/spr.c | 2 + post/lib_ppc/b.c | 4 + post/lib_ppc/cmp.c | 4 + post/lib_ppc/cmpi.c | 4 + post/lib_ppc/complex.c | 4 + post/lib_ppc/cr.c | 4 + post/lib_ppc/load.c | 4 + post/lib_ppc/multi.c | 4 + post/lib_ppc/store.c | 4 + post/lib_ppc/string.c | 4 + 132 files changed, 1173 insertions(+), 1771 deletions(-) delete mode 100644 board/adsvix/Makefile delete mode 100644 board/adsvix/adsvix.c delete mode 100644 board/adsvix/config.mk delete mode 100644 board/adsvix/lowlevel_init.S delete mode 100644 board/adsvix/pcmcia.c delete mode 100644 board/adsvix/pxavoltage.S delete mode 100644 board/adsvix/u-boot.lds delete mode 100644 include/configs/adsvix.h (limited to 'include/asm-ppc') diff --git a/.gitignore b/.gitignore index 89e96f566d9..96c1b4a7ae6 100644 --- a/.gitignore +++ b/.gitignore @@ -26,6 +26,8 @@ /u-boot.ldr /u-boot.ldr.hex /u-boot.ldr.srec +/u-boot-onenand.bin +/u-boot-flexonenand.bin # # Generated files @@ -46,3 +48,8 @@ series # cscope files cscope.* + +# OneNAND IPL files +/onenand_ipl/onenand-ipl* +/onenand_ipl/board/*/onenand* +/onenand_ipl/board/*/*.S diff --git a/CHANGELOG b/CHANGELOG index 0e317cb1df5..7ff1a8af936 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,553 @@ +commit a48311557db6e7e9473a6163b44bb1e6c6ed64c4 +Author: Mark Jackson +Date: Thu Jul 31 16:09:00 2008 +0100 + + Add gzipped logo support + + The README file states that CONFIG_VIDEO_BMP_GZIP behaves as follows: + + If this option is set, additionally to standard BMP + images, gzipped BMP images can be displayed via the + splashscreen support or the bmp command. + + However, the splashscreen function *only* supports standard BMP images. + + This patch adds the documented gzip support. + + Signed-off-by: Mark Jackson + +commit a5bcb01fbde6b1f1c9863cd86e5c4c369f0121ac +Author: Mark Jackson +Date: Thu Jul 31 15:56:48 2008 +0100 + + Fix Atmel LCD controller endianess for AVR32 processors + + The Atmel lcd controller is used on Atmel's AT91 (little endian) and + AVR32 (big endian) platforms. + + As such, the controller can handle both big and little endian memory. + + This patch fixes the driver for the AVR32 platform. + + Signed-off-by: Mark Jackson + +commit cdb8bd2fd3bcbe65d8e4334a55f5a667845426a1 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu Jul 31 15:56:01 2008 +0200 + + apollon: fix build out of tree + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 2e752be39d3e398d4ab89ffa6634c397df298297 +Author: Guennadi Liakhovetski +Date: Thu Jul 31 12:35:04 2008 +0200 + + Uncompressed images loaded to their start address shall set load_end too + + Signed-off-by: Guennadi Liakhovetski + Acked-by: Bartlomiej Sieka + +commit c37207d7f51e19c17f859966f314e27cc1231801 +Author: Wolfgang Denk +Date: Wed Jul 16 16:38:59 2008 +0200 + + Fix printf() format problems with configurable prompts + + U-Boot allows for configurable prompt strings using the + CONFIG_AUTOBOOT_PROMPT resp. CONFIG_MENUPROMPT definitions. So far, + the assumption was that any such user defined problts would contain + exactly one "%d" format specifier. But some boards did not. + + To allow for flexible boot prompts without adding too complex code we + now allow to specify the whole list of printf() arguments in the user + definition. This is powerful, but requires a responsible user who + really understands what he is doing, as he needs to know for exanple + which variables are available in the respective context. + + Signed-off-by: Wolfgang Denk + +commit 54754120637b6a7f4ff774fb199fc550bcfea1da +Author: Wolfgang Denk +Date: Thu Jul 31 17:02:14 2008 +0200 + + TQM85xx: fix typo introduce by commit ffbb5cb9 + + Signed-off-by: Wolfgang Denk + +commit 0b4951d4cddca9cc800745891c95b291e47cbbd7 +Author: Wolfgang Denk +Date: Thu Jul 31 15:27:01 2008 +0200 + + mvbc_p board: fix most build warnings. + + Signed-off-by: Wolfgang Denk + +commit c4ec6db074051d2f6fc76a66411c60621b22bc02 +Author: Wolfgang Denk +Date: Thu Jul 31 13:57:20 2008 +0200 + + E1000: clean up CONFIG_E1000_FALLBACK_MAC handling + + Avoid "integer constant is too large for 'long' type" warnings. + And simplify the code. + + Signed-off-by: Wolfgang Denk + +commit 9196b44334c330cc13de2464c59181e4db71f549 +Author: Matvejchikov Ilya +Date: Wed Jul 30 23:21:19 2008 +0400 + + 8260: Making the use of gd->pci_clk dependant on the CONFIG_PCI + + Signed-off-by: Matvejchikov Ilya + +commit 6361ad4b596f5a940a01c91ae0297d98f790cbe0 +Author: Matvejchikov Ilya +Date: Wed Jul 30 23:20:32 2008 +0400 + + PPC: Add pci_clk in the global_data for CPM2 processors + + This patch adds pci_clk field to the global_data structure for the + processors which have CPM2 module in case the CONFIG_PCI is defined. + + Signed-off-by: Matvejchikov Ilya + +commit f0ff885ca64655bee6540eb8a25eed90b1152686 +Author: Kumar Gala +Date: Wed Jul 30 14:13:30 2008 -0500 + + mpc85xx: Update linker scripts for Freescale boards + + * Move to using absolute addressing always. Makes the scripts a bit more + portable and common + * Moved .bss after the end of the image. These allows us to have more + room in the resulting binary image for code and data. + * Removed .text object files that aren't really needed + * Make sure _end is 4-byte aligned as the .bss init code expects this. + (Its possible that the end of .bss isn't 4-byte aligned) + + Signed-off-by: Kumar Gala + +commit 57c219ad5d34dd9d49991777a62e3899595f2ec7 +Author: Kumar Gala +Date: Wed Jul 30 08:01:15 2008 -0500 + + Fix compile warnings in dlmalloc + + The origional code was using on odd reference to get to the first + real element in av_[]. The first two elements of the array are + not used for actual bins, but for house keeping. If we are more + explicit about how use the first few elements we can get rid of the + warnings: + + dlmalloc.c: In function 'malloc_extend_top': + dlmalloc.c:1971: warning: dereferencing type-punned pointer will break strict-aliasing rules + dlmalloc.c:1999: warning: dereferencing type-punned pointer will break strict-aliasing rules + dlmalloc.c:2029: warning: dereferencing type-punned pointer will break strict-aliasing rules + ... + + The logic of how this code came to be is: + bin_at(0) = (char*)&(av_[2]) - 2*SIZE_SZ + + SIZE_SZ is the size of pointer, and av_ is arry of pointers so: + bin_at(0) = &(av_[0]) + + Going from there to bin_at(0)->fd or bin_at(0)->size should be straight forward. + + Signed-off-by: Kumar Gala + +commit 3f9ae1a5d43c49a8ecf497470c3d1d80255e44b9 +Author: Stefan Roese +Date: Wed Jul 30 10:21:01 2008 +0200 + + ppc4xx: Fix W7OLMG compile problems by adding missing LM75 defines + + Signed-off-by: Stefan Roese + +commit ebb86c4ecd37a7701358284e497ca4c6483c7cc5 +Author: Stefan Roese +Date: Wed Jul 30 09:59:51 2008 +0200 + + cmd_bootm.c: Fix problem with '#if (CONFIG_CMD_USB)' + + A recent patch used '#if (CONFIG_CMD_USB)' instead of + '#if defined(CONFIG_CMD_USB)'. This patch fixes this problem and makes + common/bootm.c compile again. + + Signed-off-by: Stefan Roese + Acked-by: Markus Klotzbuecher + +commit 2cb9080427fe641dcb71da46cd0634dd406f37ed +Author: Kyungmin Park +Date: Tue Jul 22 08:01:43 2008 +0900 + + Remove unused I2C at apollon board + + There are no I2C devices on this board. + + Signed-off-by: Kyungmin Park + +commit 3c95960e526b3b026da20201db64526f46faf14b +Author: Wolfgang Denk +Date: Thu Jul 31 10:12:09 2008 +0200 + + at91rm9200dk, csb637: fix NAND related build problems + + Tried fixing NAND support for the at91rm9200dk board; untested. + Disabled NAND support in the csb637 board config file. + + Signed-off-by: Wolfgang Denk + +commit 09d318a8bb1444ec92e31cafcdba877eb9409e58 +Author: Kumar Gala +Date: Tue Jul 29 12:23:49 2008 -0500 + + fsl_i2c: Use timebase timer functions instead of get_timer() + + The current implementation of get_timer() is only really useful after we + have relocated u-boot to memory. The i2c code is used before that as part + of the SPD DDR setup. + + We actually have a bug when using the get_timer() code before relocation + because the .bss hasn't been setup and thus we could be reading/writing + a random location (probably in flash). + + Signed-off-by: Kumar Gala + +commit 4fc72a0d6ca85070a5e90d76cc5a853526ac09c4 +Author: Frank Svendsbøe +Date: Tue Jul 29 14:49:31 2008 +0200 + + Adder8xx: Fix CFG_MONITOR_LEN + + Due to increased space usage, U-Boot can no longer be stored in three sectors. + The current U-Boot use just over three flash sectors (197k), and U-Boot will + become corrupt after saving environment variables. This patch adds another 64k + to CFG_MONITOR_LEN. + + Signed-off-by: Frank E. Svendsbøe + +commit a4c59ad4a21140550ada6f97690d2527c4146ce5 +Author: Kyungmin Park +Date: Tue Jul 29 08:47:57 2008 +0900 + + Add OneNAND IPL related files to gitignore + + Signed-off-by: Kyungmin Park + +commit 8d87589e8e874df7120a3d9667f051bc33bac250 +Author: Rafal Jaworowski +Date: Mon Jul 28 20:38:25 2008 +0200 + + API: Teach the storage layer about SATA and MMC options. + + Signed-off-by: Rafal Czubak + Acked-by: Rafal Jaworowski + +commit 6b73b754f782e1ecce5048bf20b22ce56a07a5b8 +Author: Rafal Jaworowski +Date: Mon Jul 28 20:37:48 2008 +0200 + + API: Dump contents of sector 0 in the demo application. + + Signed-off-by: Rafal Czubak + Acked-by: Rafal Jaworowski + +commit 13ca6305f2eba49c175f6370c35286141059c789 +Author: Rafal Jaworowski +Date: Mon Jul 28 20:37:10 2008 +0200 + + API: Correct storage enumeration routine, other minor fixes in API storage area. + + Signed-off-by: Rafal Czubak + Acked-by: Rafal Jaworowski + +commit 05c7fe0f049b1c9eb9a1992f27e5e350d865f4a8 +Author: Rafal Jaworowski +Date: Mon Jul 28 20:36:19 2008 +0200 + + API: Fix compilation warnings in api_examples/demo.c. + + Signed-off-by: Rafal Czubak + +commit c14eefcc48212af2f3314809605698dd8393a90a +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Jul 27 17:09:43 2008 +0200 + + Fix more printf() format warnings + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 936897d4d1365452bbbdf8430db5e7769ef08d38 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Jul 25 15:18:16 2008 +0200 + + Fix remaining CFG_CMD_ define, ifdef and comments + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 5d1d00fb36005482e1803a00ddc46efa11d719af +Author: Stefano Babic +Date: Fri Jul 25 08:57:40 2008 +0200 + + Add include for config.h in command.h. + + Because the cmd_tbl_s structure depends on the configuration file, it + must be assured that config.h is included before the structure is + evaluated by the compiler. If this is not certain, it could happen + that the compiler generates structures of different size, depending + on the fact if the source file includes before or after + . + + The effect is that u-boot crashes when tries to relocate the command + table (for ppc) or try to access to the command table for other + architectures. + + The problem can happen on board-depending commands. All general + commands under /common are unaffected, because they include already + config.h before command.h. + + Signed-off-by: Stefano Babic + +commit 2dacb734bac9dba1db9e704d3e0b200ef521c79a +Author: Scott Wood +Date: Wed Jul 23 13:16:06 2008 -0500 + + NAND: $(obj)-qualify ecc.h in kilauea NAND boot Makefile. + + This fixes building out-of-tree. + + Signed-off-by: Scott Wood + +commit 36d59bd9da9e15d19b867b48449408830f4e2ad5 +Author: Heiko Schocher +Date: Wed Jul 23 07:30:46 2008 +0200 + + Fix warnings if compiling with IDE support. + + cmd_ide.c:827: Warnung: weak declaration of `ide_outb' after first use results in unspecified behavior + cmd_ide.c:839: Warnung: weak declaration of `ide_inb' after first use results in unspecified behavior + + Signed-off-by: Heiko Schocher + +commit 7610db17fd4d59c51d825488526d85ede2f06767 +Author: Adrian Filipi +Date: Tue Jul 22 14:28:11 2008 -0400 + + Removed support for the adsvix board. + + Support for the adsvix was originally provided by Applied Data + Systems (ADS), inc., now EuroTech, Inc. + The board never shipped aside from some sample boards. + + Signed-off-by: Adrian Filipi + +commit f96b44cef897bd372beb86dde1b33637c119d84d +Author: Remy Bohmer +Date: Tue Jul 22 16:22:11 2008 +0200 + + ARM: set GD_FLG_RELOC for boards skipping relocation to RAM + + If CONFIG_SKIP_RELOCATE_UBOOT is set the flag GD_FLG_RELOC is usually + never set, because relocation to RAM is actually never done by U-boot + itself. However, several pieces of code check if this flag is set at + some time. + + So, to make sure this flag is set on boards skipping relocation, this + is added to the initialisation of U-boot at a moment where it is safe + to do so. + + Signed-off-by: Remy Bohmer + +commit e4dafff86f289b5677143a3e41da7b45c6d27fc7 +Author: Timur Tabi +Date: Mon Jul 21 14:26:23 2008 -0500 + + fsl-i2c: fix writes to data segment before relocation + + Prevent i2c_init() in fsl_i2c.c from writing to the data segment before + relocation. Commit d8c82db4 added the ability for i2c_init() to program the + I2C bus speed and save the value in i2c_bus_speed[], which is a global + variable. It is an error to write to the data segment before relocation, + which is what i2c_init() does when it stores the bus speed in i2c_bus_speed[]. + + Signed-off-by: Timur Tabi + +commit dbd32387920e5ad6f9dd58a7b5012bbabe2a6a21 +Author: Wolfgang Ocker +Date: Mon Jul 28 16:56:51 2008 +0200 + + mips: Fix baudrate divisor computation on alchemy cpus + + Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor + on alchemy cpus. + + Signed-off-by: Wolfgang Ocker + Signed-off-by: Shinya Kuribayashi + +commit a229d291f33308ab7761d39f25fa1a53c0fc00a2 +Author: Haavard Skinnemoen +Date: Wed Jul 23 10:55:46 2008 +0200 + + spi flash: Fix printf() format warnings + + Signed-off-by: Haavard Skinnemoen + +commit 252a5e0738bcafaf25f7fbb40f19a59abc2cb13e +Author: Haavard Skinnemoen +Date: Wed Jul 23 10:55:31 2008 +0200 + + atmel_mci: Fix printf() format warnings + + Signed-off-by: Haavard Skinnemoen + +commit 7f4b009f4232d57084ce0ec5aeb3b57bccb08e4c +Author: Haavard Skinnemoen +Date: Wed Jul 23 10:55:15 2008 +0200 + + avr32: Fix printf() format warnings + + Signed-off-by: Haavard Skinnemoen + +commit a79c3e8d9c31db25d5ca3ec8e08a97f323410dd4 +Author: Haavard Skinnemoen +Date: Wed Jul 23 10:52:19 2008 +0200 + + avr32: asm/io.h needs asm/types.h + + map_physmem() takes a phys_addr_t as parameter. This type is defined in + asm/types.h, so we need to include that file. + + Signed-off-by: Haavard Skinnemoen + +commit 1953d128fd07f07d1c3810a28c0863ea64dae1b6 +Author: Michal Simek +Date: Thu Jul 17 12:25:46 2008 +0200 + + microblaze: Fix printf() format issues + + Signed-off-by: Michal Simek + +commit de2a07e534f18b1ca5f9869a4ef0604ca829cff0 +Author: Gururaja Hebbar K R +Date: Thu Jul 17 07:27:51 2008 +0530 + + Remove unused code from lib_arm/bootm.c + + Signed-off-by: Gururaja Hebbar + +commit ffbb5cb942e9856fa24e946977e0a60c64df04ab +Author: Detlev Zundel +Date: Wed Jul 16 18:56:45 2008 +0200 + + tqm85xx: Demystify 'DK: !!!' comment + + Signed-off-by: Detlev Zundel + +commit b2f44ba570f3a01113bbb745daf46f3858d22f53 +Author: Detlev Zundel +Date: Wed Jul 16 18:56:44 2008 +0200 + + 83xx/85xx/86xx: Add LTEDR local bus definitions + + Signed-off-by: Detlev Zundel + +commit f13f64cf42d5abec3e0f920233f6a7a61e7ae494 +Author: Ricardo Ribalda Delgado +Date: Wed Jul 16 16:22:32 2008 +0200 + + serial_xuartlite.c: fix compiler warnings + + Signed-off-by: Ricardo Ribalda Delgado + Acked-by: Grant Likely + +commit 86446d3a5d9d3ca81e85d1ccd3accaaae6f8e3c9 +Author: Stefan Roese +Date: Fri Jul 18 11:03:35 2008 +0200 + + POST: Add disable interrupts in some of the missing CPU POST tests + + Some CPU POST tests did not disable the interrupts while running. This + seems to be necessary to protect this self modifying code. + + Signed-off-by: Stefan Roese + +commit 97a3bf268d096e0e97e54048448c35114edcf557 +Author: Stefan Roese +Date: Fri Jul 18 10:43:24 2008 +0200 + + ide: Use CFG_64BIT_LBA instead of CFG_64BIT_STRTOUL + + This is needed for boards that define CFG_64BIT_STRTOUL but don't define + CFG_64BIT_LBA. + + Signed-off-by: Stefan Roese + +commit 0043ac55024963295fc79b39af85b6dc3b261e17 +Author: Niklaus Giger +Date: Fri Jul 18 11:22:23 2008 +0200 + + POST PPC4xx/spr IVPR only if PPC440 + + The SPR IVPR register is only present (as far as I know) for + processors with a PPC440 core. + + Signed-off-by: Niklaus Giger + Acked-by: Stefan Roese + +commit 1092fbd64748dfa2e979b102611ece9bc5ec1855 +Author: Stefan Roese +Date: Fri Jul 18 10:42:29 2008 +0200 + + ppc4xx: Enable 64bit printf format on 440/460 platforms + + This patch defines CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL for all + 440/460 platforms. This may be needed since those platforms support + 36bit physical address space. + + Signed-off-by: Stefan Roese + +commit 66fe183b1dd9c7534605147a8ecfed1c02345ee5 +Author: Stefan Roese +Date: Fri Jul 18 15:57:23 2008 +0200 + + ppc4xx: Fix incorrect MODTx setup for some DIMM configurations + + This patch fixes a problem with incorrect MODTx (On Die Termination) + setup for a configuration with multiple DIMM's and multiple ranks. + Without this change Katmai was unable to boot Linux with DDR2 frequency + >= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux + with DDR2 frequency = 640MHz and mem=4GB. + + Signed-off-by: Stefan Roese + +commit 340ccb260f21516be360745d5c5e3bd0657698df +Author: Sebastian Siewior +Date: Wed Jul 16 20:04:49 2008 +0200 + + cfi_flash: fix flash on BE machines with CFG_WRITE_SWAPPED_DATA + + This got broken by commits 93c56f212c + [cfi_flash: support of long cmd in U-boot.] + + That command needs to be in little endian format on BE machines + with CFG_WRITE_SWAPPED_DATA. Without this patch, the command 0xf0 + gets saved on stack as 0x00 00 00 f0 and 0x00 gets written into + the cmdbuf in case portwidth = chipwidth = 8bit. + + Cc: Alexey Korolev + Cc: Vasiliy Leonenko + Signed-off-by: Sebastian Siewior + +commit 699f05125509249072a0b865c8d35520d97cd501 +Author: Wolfgang Denk +Date: Tue Jul 15 22:22:44 2008 +0200 + + Prepare v1.3.4-rc1: Code cleanup, update CHANGELOG, sort Makefile + + Signed-off-by: Wolfgang Denk + commit bcab74baa6b1b1c969038ab6f64a186239180405 Author: Hugo Villeneuve Date: Tue Jul 15 11:23:02 2008 -0400 diff --git a/MAKEALL b/MAKEALL index 2948387723a..ac4195f7d8f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -543,7 +543,6 @@ LIST_at91=" \ ######################################################################### LIST_pxa=" \ - adsvix \ cerf250 \ cradle \ csb226 \ diff --git a/Makefile b/Makefile index ea572cf36d3..92410bad835 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 1 PATCHLEVEL = 3 SUBLEVEL = 4 -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h @@ -346,10 +346,9 @@ $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin $(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all + $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all $(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk - $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin @@ -2609,9 +2608,6 @@ actux3_config : unconfig actux4_config : unconfig @$(MKCONFIG) $(@:_config=) arm ixp actux4 -adsvix_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa adsvix - cerf250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa cerf250 @@ -2678,6 +2674,7 @@ zylonite_config : apollon_config : unconfig @mkdir -p $(obj)include + @mkdir -p $(obj)onenand_ipl/board/apollon @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk diff --git a/api/api_storage.c b/api/api_storage.c index 7e6324044d6..74391a59d08 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Semihalf + * (C) Copyright 2007-2008 Semihalf * * Written by: Rafal Jaworowski * @@ -46,14 +46,15 @@ #define ENUM_USB 1 #define ENUM_SCSI 2 #define ENUM_MMC 3 -#define ENUM_MAX 4 +#define ENUM_SATA 4 +#define ENUM_MAX 5 struct stor_spec { int max_dev; int enum_started; int enum_ended; int type; /* "external" type: DT_STOR_{IDE,USB,etc} */ - char name[4]; + char *name; }; static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, }; @@ -68,12 +69,19 @@ void dev_stor_init(void) specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE; specs[ENUM_IDE].name = "ide"; #endif -#if defined(CONFIG_CMD_USB) - specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV; - specs[ENUM_USB].enum_started = 0; - specs[ENUM_USB].enum_ended = 0; - specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB; - specs[ENUM_USB].name = "usb"; +#if defined(CONFIG_CMD_MMC) + specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE; + specs[ENUM_MMC].enum_started = 0; + specs[ENUM_MMC].enum_ended = 0; + specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC; + specs[ENUM_MMC].name = "mmc"; +#endif +#if defined(CONFIG_CMD_SATA) + specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE; + specs[ENUM_SATA].enum_started = 0; + specs[ENUM_SATA].enum_ended = 0; + specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA; + specs[ENUM_SATA].name = "sata"; #endif #if defined(CONFIG_CMD_SCSI) specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE; @@ -82,6 +90,13 @@ void dev_stor_init(void) specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI; specs[ENUM_SCSI].name = "scsi"; #endif +#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) + specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV; + specs[ENUM_USB].enum_started = 0; + specs[ENUM_USB].enum_ended = 0; + specs[ENUM_USB].type = DEV_TYP_STOR | DT_STOR_USB; + specs[ENUM_USB].name = "usb"; +#endif } /* @@ -108,7 +123,10 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di) if (first) { di->cookie = (void *)get_dev(specs[type].name, 0); - found = 1; + if (di->cookie == NULL) + return 0; + else + found = 1; } else { for (i = 0; i < specs[type].max_dev; i++) @@ -123,7 +141,10 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di) } di->cookie = (void *)get_dev(specs[type].name, i); - found = 1; + if (di->cookie == NULL) + return 0; + else + found = 1; /* provide hint if there are more devices in * this group to enumerate */ @@ -360,7 +381,7 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start return 0; if ((dd->block_read) == NULL) { - debugf("no block_read() for device 0x%08x\n"); + debugf("no block_read() for device 0x%08x\n", cookie); return 0; } diff --git a/api_examples/demo.c b/api_examples/demo.c index eae9712b71f..69ac318375a 100644 --- a/api_examples/demo.c +++ b/api_examples/demo.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Semihalf + * (C) Copyright 2007-2008 Semihalf * * Written by: Rafal Jaworowski * @@ -31,13 +31,15 @@ #define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0) -void test_dump_si(struct sys_info *); +#define BUF_SZ 2048 +#define WAIT_SECS 5 + +void test_dump_buf(void *, int); void test_dump_di(int); +void test_dump_si(struct sys_info *); void test_dump_sig(struct api_signature *); -char buf[2048]; - -#define WAIT_SECS 5 +static char buf[BUF_SZ]; int main(int argc, char *argv[]) { @@ -58,11 +60,12 @@ int main(int argc, char *argv[]) if (sig->version > API_SIG_VERSION) return -3; - printf("API signature found @%x\n", sig); + printf("API signature found @%x\n", (unsigned int)sig); test_dump_sig(sig); printf("\n*** Consumer API test ***\n"); - printf("syscall ptr 0x%08x@%08x\n", syscall_ptr, &syscall_ptr); + printf("syscall ptr 0x%08x@%08x\n", (unsigned int)syscall_ptr, + (unsigned int)&syscall_ptr); /* console activities */ ub_putc('B'); @@ -125,11 +128,17 @@ int main(int argc, char *argv[]) if (i == devs_no) printf("No storage devices available\n"); else { + memset(buf, 0, BUF_SZ); + if ((rv = ub_dev_open(i)) != 0) errf("open device %d error %d\n", i, rv); - else if ((rv = ub_dev_read(i, &buf, 200, 20)) != 0) + + else if ((rv = ub_dev_read(i, buf, 1, 0)) != 0) errf("could not read from device %d, error %d\n", i, rv); + printf("Sector 0 dump (512B):\n"); + test_dump_buf(buf, 512); + ub_dev_close(i); } @@ -180,7 +189,7 @@ void test_dump_sig(struct api_signature *sig) printf("signature:\n"); printf(" version\t= %d\n", sig->version); printf(" checksum\t= 0x%08x\n", sig->checksum); - printf(" sc entry\t= 0x%08x\n", sig->syscall); + printf(" sc entry\t= 0x%08x\n", (unsigned int)sig->syscall); } void test_dump_si(struct sys_info *si) @@ -188,9 +197,9 @@ void test_dump_si(struct sys_info *si) int i; printf("sys info:\n"); - printf(" clkbus\t= 0x%08x\n", si->clk_bus); - printf(" clkcpu\t= 0x%08x\n", si->clk_cpu); - printf(" bar\t\t= 0x%08x\n", si->bar); + printf(" clkbus\t= 0x%08x\n", (unsigned int)si->clk_bus); + printf(" clkcpu\t= 0x%08x\n", (unsigned int)si->clk_cpu); + printf(" bar\t\t= 0x%08x\n", (unsigned int)si->bar); printf("---\n"); for (i = 0; i < si->mr_no; i++) { @@ -217,23 +226,56 @@ void test_dump_si(struct sys_info *si) } } -static char * test_stor_typ(int type) +static char *test_stor_typ(int type) { if (type & DT_STOR_IDE) return "IDE"; + if (type & DT_STOR_MMC) + return "MMC"; + + if (type & DT_STOR_SATA) + return "SATA"; + if (type & DT_STOR_SCSI) return "SCSI"; if (type & DT_STOR_USB) return "USB"; - if (type & DT_STOR_MMC); - return "MMC"; - return "Unknown"; } +void test_dump_buf(void *buf, int len) +{ + int i; + int line_counter = 0; + int sep_flag = 0; + int addr = 0; + + printf("%07x:\t", addr); + + for (i = 0; i < len; i++) { + if (line_counter++ > 15) { + line_counter = 0; + sep_flag = 0; + addr += 16; + i--; + printf("\n%07x:\t", addr); + continue; + } + + if (sep_flag++ > 1) { + sep_flag = 1; + printf(" "); + } + + printf("%02x", *((char *)buf++)); + } + + printf("\n"); +} + void test_dump_di(int handle) { int i; @@ -252,7 +294,7 @@ void test_dump_di(int handle) } else if (di->type & DEV_TYP_STOR) { printf(" type\t\t= %s\n", test_stor_typ(di->type)); - printf(" blk size\t\t= %d\n", di->di_stor.block_size); - printf(" blk count\t\t= %d\n", di->di_stor.block_count); + printf(" blk size\t\t= %d\n", (unsigned int)di->di_stor.block_size); + printf(" blk count\t\t= %d\n", (unsigned int)di->di_stor.block_count); } } diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile deleted file mode 100644 index 05601b48d1d..00000000000 --- a/board/adsvix/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := adsvix.o pcmcia.o -SOBJS := lowlevel_init.o pxavoltage.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c deleted file mode 100644 index c430d634e12..00000000000 --- a/board/adsvix/adsvix.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of ADSVIX-Board */ - gd->bd->bi_arch_number = 620; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa000003c; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return 0; -} diff --git a/board/adsvix/config.mk b/board/adsvix/config.mk deleted file mode 100644 index 98be4ebe008..00000000000 --- a/board/adsvix/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0xa1700000 diff --git a/board/adsvix/lowlevel_init.S b/board/adsvix/lowlevel_init.S deleted file mode 100644 index 8dea71c3562..00000000000 --- a/board/adsvix/lowlevel_init.S +++ /dev/null @@ -1,466 +0,0 @@ -/* - * This was originally from the Lubbock u-boot port. - * - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPSR3 - ldr r1, =CFG_GPSR3_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPCR3 - ldr r1, =CFG_GPCR3_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GPDR3 - ldr r1, =CFG_GPDR3_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =GAFR3_L - ldr r1, =CFG_GAFR3_L_VAL - str r1, [r0] - - ldr r0, =GAFR3_U - ldr r1, =CFG_GAFR3_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - ldr r2, =CFG_FLYCNFG_VAL - str r2, [r1, #FLYCNFG_OFFSET] - str r2, [r1, #FLYCNFG_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r4, [r1, #MDREFR_OFFSET] - ldr r2, =0xFFF - bic r4, r4, r2 - - ldr r3, =CFG_MDREFR_VAL - and r3, r3, r2 - - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - - orr r4, r4, #MDREFR_K0RUN - orr r4, r4, #MDREFR_K0DB4 - orr r4, r4, #MDREFR_K0FREE - orr r4, r4, #MDREFR_K0DB2 - orr r4, r4, #MDREFR_K1DB2 - bic r4, r4, #MDREFR_K1FREE - bic r4, r4, #MDREFR_K2FREE - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - ldr r2, =CFG_SXCNFG_VAL - str r2, [r1, #SXCNFG_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) - - orr r4, r4, #MDREFR_K1RUN - bic r4, r4, #MDREFR_K2DB2 - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - bic r4, r4, #MDREFR_SLFRSH - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - orr r4, r4, #MDREFR_E1PIN - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - nop - nop - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - mov r4, r3 - orr r3, r3, #MDCNFG_DE0 - str r3, [r1, #MDCNFG_OFFSET] - mov r0, r3 - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* enable APD */ - ldr r3, [r1, #MDREFR_OFFSET] - orr r3, r3, #MDREFR_APD - str r3, [r1, #MDREFR_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ - -setvoltage: - - mov r10, lr - bl initPXAvoltage /* In case the board is rebooting with a */ - mov lr, r10 /* low voltage raise it up to a good one. */ - -wakeup: - /* Are we waking from sleep? */ - ldr r0, =RCSR - ldr r1, [r0] - and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) - str r1, [r0] - teq r1, #RCSR_SMR - - bne initirqs - - ldr r0, =PSSR - mov r1, #PSSR_PH - str r1, [r0] - - /* if so, resume at PSPR */ - ldr r0, =PSPR - ldr r1, [r0] - mov pc, r1 - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - - /* Turn Off on-chip peripheral clocks (except for memory) */ - /* for re-configuration. */ - ldr r1, =CKEN - ldr r2, =CFG_CKEN - str r2, [r1] - - /* ... and write the core clock config register */ - ldr r2, =CFG_CCCR - ldr r1, =CCCR - str r2, [r1] - - /* Turn on turbo mode */ - mrc p14, 0, r2, c6, c0, 0 - orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ - mcr p14, 0, r2, c6, c0, 0 - - /* Re-write MDREFR */ - ldr r1, =MEMC_BASE - ldr r2, [r1, #MDREFR_OFFSET] - str r2, [r1, #MDREFR_OFFSET] -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#else -#error "RTC not defined" -#endif - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - /* FIXME */ - -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/adsvix/pcmcia.c b/board/adsvix/pcmcia.c deleted file mode 100644 index ba5be013975..00000000000 --- a/board/adsvix/pcmcia.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void pcmcia_power_on(void) -{ -#if 0 - if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */ - GPCR(81) = GPIO_bit(81); - GPSR(82) = GPIO_bit(82); - } - else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */ - GPCR(81) = GPIO_bit(81); - GPCR(82) = GPIO_bit(82); - } -#else -#warning "Board will only supply 5V, wait for next HW spin for selectable power" - /* 5.0V */ - GPCR(81) = GPIO_bit(81); - GPCR(82) = GPIO_bit(82); -#endif - - udelay(300000); - - /* reset the card */ - GPSR(52) = GPIO_bit(52); - - /* enable PCMCIA */ - GPCR(83) = GPIO_bit(83); - - /* clear reset */ - udelay(10); - GPCR(52) = GPIO_bit(52); - - udelay(20000); -} - -void pcmcia_power_off(void) -{ - /* 0V */ - GPSR(81) = GPIO_bit(81); - GPSR(82) = GPIO_bit(82); - /* disable PCMCIA */ - GPSR(83) = GPIO_bit(83); -} diff --git a/board/adsvix/pxavoltage.S b/board/adsvix/pxavoltage.S deleted file mode 100644 index 2fe1cabd7c7..00000000000 --- a/board/adsvix/pxavoltage.S +++ /dev/null @@ -1,230 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define LTC1663_ADDR 0x20 - -#define LTC1663_SY 0x01 /* Sync ACK */ -#define LTC1663_SD 0x04 /* shutdown */ -#define LTC1663_BG 0x04 /* Internal Voltage Ref */ - -#define VOLT_1_55 18 /* DAC value for 1.55V */ - - .global initPXAvoltage - -@ Set the voltage to 1.55V early in the boot process so we can run -@ at a high clock speed and boot quickly. Note that this is necessary -@ because the reset button does not reset the CPU voltage, so if the -@ voltage was low (say 0.85V) then the CPU would crash without this -@ routine - -@ This routine clobbers r0-r4 - -initializei2c: - - ldr r2, =CKEN - ldr r3, [r2] - orr r3, r3, #CKEN15_PWRI2C - str r3, [r2] - - ldr r2, =PCFR - ldr r3, [r2] - orr r3, r3, #PCFR_PI2C_EN - str r3, [r2] - - /* delay for about 250msec - */ - ldr r3, =OSCR - mov r2, #0 - str r2, [r3] - ldr r1, =0xC0000 - -1: - ldr r2, [r3] - cmp r1, r2 - bgt 1b - ldr r0, =PWRICR - ldr r1, [r0] - bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP) - str r1, [r0] - - orr r1, r1, #ICR_UR - str r1, [r0] - - ldr r2, =PWRISR - ldr r3, =0x7ff - str r3, [r2] - - bic r1, r1, #ICR_UR - str r1, [r0] - - mov r1, #(ICR_GCD | ICR_SCLE) - str r1, [r0] - - orr r1, r1, #ICR_IUE - str r1, [r0] - - orr r1, r1, #ICR_FM - str r1, [r0] - - /* delay for about 1msec - */ - ldr r3, =OSCR - mov r2, #0 - str r2, [r3] - ldr r1, =0xC00 - -1: - ldr r2, [r3] - cmp r1, r2 - bgt 1b - mov pc, lr - -sendbytei2c: - ldr r3, =PWRIDBR - str r0, [r3] - ldr r3, =PWRICR - ldr r0, [r3] - orr r0, r0, r1 - bic r0, r0, r2 - str r0, [r3] - orr r0, r0, #ICR_TB - str r0, [r3] - - mov r2, #0x100000 - -waitfortxemptyi2c: - - ldr r0, =PWRISR - ldr r1, [r0] - - /* take it from the top if we don't get empty after a while */ - subs r2, r2, #1 - moveq lr, r4 - beq initPXAvoltage - - tst r1, #ISR_ITE - - beq waitfortxemptyi2c - - orr r1, r1, #ISR_ITE - str r1, [r0] - - mov pc, lr - -initPXAvoltage: - - mov r4, lr - - bl setleds - - bl initializei2c - - bl setleds - - /* now send the real message to set the correct voltage */ - ldr r0, =LTC1663_ADDR - mov r0, r0, LSL #1 - mov r1, #ICR_START - ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK) - bl sendbytei2c - - bl setleds - - mov r0, #LTC1663_BG - mov r1, #0 - mov r2, #(ICR_STOP | ICR_START) - bl sendbytei2c - - bl setleds - - ldr r0, =VOLT_1_55 - and r0, r0, #0xff - mov r1, #0 - mov r2, #(ICR_STOP | ICR_START) - bl sendbytei2c - - bl setleds - - ldr r0, =VOLT_1_55 - mov r0, r0, ASR #8 - and r0, r0, #0xff - mov r1, #ICR_STOP - mov r2, #ICR_START - bl sendbytei2c - - bl setleds - - @ delay a little for the volatage to stablize - ldr r3, =OSCR - mov r2, #0 - str r2, [r3] - ldr r1, =0xC0 - -1: - ldr r2, [r3] - cmp r1, r2 - bgt 1b - mov pc, r4 - -setleds: - mov pc, lr - - ldr r5, =0x40e00058 - ldr r3, [r5] - bic r3, r3, #0x3 - str r3, [r5] - ldr r5, =0x40e0000c - ldr r3, [r5] - orr r3, r3, #0x00010000 - str r3, [r5] - - @ inner loop - mov r0, #0x2 -1: - - ldr r5, =0x40e00018 - mov r3, #0x00010000 - str r3, [r5] - - @ outer loop - mov r3, #0x00F00000 -2: - subs r3, r3, #1 - bne 2b - - ldr r5, =0x40e00024 - mov r3, #0x00010000 - str r3, [r5] - - @ outer loop - mov r3, #0x00F00000 -3: - subs r3, r3, #1 - bne 3b - - subs r0, r0, #1 - bne 1b - - mov pc, lr diff --git a/board/adsvix/u-boot.lds b/board/adsvix/u-boot.lds deleted file mode 100644 index 14d264a6861..00000000000 --- a/board/adsvix/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) } - _end = .; -} diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index f2c3e797996..4ead5336c65 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -81,7 +81,7 @@ phys_size_t initdram(int board_type) unmap_physmem(sdram_base, EBI_SDRAM_SIZE); if (expected_size != actual_size) - printf("Warning: Only %u of %u MiB SDRAM is working\n", + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); return actual_size; diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 6371e2d4e3a..d284fc1438a 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -104,7 +104,7 @@ phys_size_t initdram(int board_type) unmap_physmem(sdram_base, EBI_SDRAM_SIZE); if (expected_size != actual_size) - printf("Warning: Only %u of %u MiB SDRAM is working\n", + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); return actual_size; diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 12537f3142e..e2bfd4aff27 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -70,7 +70,7 @@ unsigned long flash_init(void) void flash_print_info(flash_info_t *info) { - printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", info->flash_id >> 16, info->flash_id & 0xffff); printf("Size: %ld MB in %d sectors\n", info->size >> 10, info->sector_count); diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c index dca10be1b5a..bda361ead94 100644 --- a/board/esd/common/flash.c +++ b/board/esd/common/flash.c @@ -22,7 +22,9 @@ */ #include +#ifdef __PPC__ #include +#endif #include flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile index f337a7563c5..74c25286982 100644 --- a/board/freescale/m5275evb/Makefile +++ b/board/freescale/m5275evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -OBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds index f200810f069..0e4f5a24587 100644 --- a/board/freescale/mpc8540ads/u-boot.lds +++ b/board/freescale/mpc8540ads/u-boot.lds @@ -2,6 +2,8 @@ * (C) Copyright 2002,2003, Motorola,Inc. * Xianghua Xiao, X.Xiao@motorola.com. * + * Copyright 2008 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -26,16 +28,6 @@ OUTPUT_ARCH(powerpc) __DYNAMIC = 0; */ SECTIONS { - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -62,17 +54,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) *(.text) *(.fixup) *(.got1) @@ -134,6 +115,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -142,6 +135,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds index 5f4dcf021dd..1c583de83f2 100644 --- a/board/freescale/mpc8541cds/u-boot.lds +++ b/board/freescale/mpc8541cds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2008 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -25,16 +25,6 @@ OUTPUT_ARCH(powerpc) __DYNAMIC = 0; */ SECTIONS { - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -61,18 +51,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - drivers/net/tsec.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) *(.text) *(.fixup) *(.got1) @@ -134,6 +112,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -142,6 +132,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index c66c69fcbe4..500e6475aaf 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,16 +25,6 @@ OUTPUT_ARCH(powerpc) __DYNAMIC = 0; */ SECTIONS { - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -61,17 +51,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - drivers/bios_emulator/atibios.o (.text) *(.text) *(.fixup) *(.got1) @@ -133,6 +112,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -141,6 +132,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds index eba7e8a9d31..6b9339511aa 100644 --- a/board/freescale/mpc8548cds/u-boot.lds +++ b/board/freescale/mpc8548cds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,16 +25,6 @@ OUTPUT_ARCH(powerpc) __DYNAMIC = 0; */ SECTIONS { - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -61,17 +51,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - drivers/net/tsec.o (.text) - cpu/mpc85xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) *(.text) *(.fixup) *(.got1) @@ -133,6 +112,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -141,6 +132,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds index 5f4dcf021dd..a18b3a7b500 100644 --- a/board/freescale/mpc8555cds/u-boot.lds +++ b/board/freescale/mpc8555cds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2008 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,16 +25,6 @@ OUTPUT_ARCH(powerpc) __DYNAMIC = 0; */ SECTIONS { - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -61,18 +51,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - drivers/net/tsec.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) *(.text) *(.fixup) *(.got1) @@ -134,6 +112,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -142,6 +132,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds index cb30ea9a291..0e4f5a24587 100644 --- a/board/freescale/mpc8560ads/u-boot.lds +++ b/board/freescale/mpc8560ads/u-boot.lds @@ -1,7 +1,9 @@ /* - * (C) Copyright 2002,2003,Motorola,Inc. + * (C) Copyright 2002,2003, Motorola,Inc. * Xianghua Xiao, X.Xiao@motorola.com. * + * Copyright 2008 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -26,16 +28,6 @@ OUTPUT_ARCH(powerpc) __DYNAMIC = 0; */ SECTIONS { - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -62,20 +54,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/commproc.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/serial_scc.o (.text) - cpu/mpc85xx/ether_fcc.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) *(.text) *(.fixup) *(.got1) @@ -137,6 +115,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -145,6 +135,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds index 1b83834c868..9d245e4ec60 100644 --- a/board/freescale/mpc8568mds/u-boot.lds +++ b/board/freescale/mpc8568mds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor. + * Copyright 2004-2008 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,21 +23,8 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ - SECTIONS { - /* ELIOR - From RAM: From FLASH: 0xFFFFFFFC*/ - .resetvec 0xFFFFFFFC: - { - *(.resetvec) - } = 0xffff - - /*(ELIOR - From RAM: From FLASH: 0xFFFFF000*/ - .bootpg 0xFFFFF000: - { - cpu/mpc85xx/start.o (.bootpg) - } = 0xffff - /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } @@ -64,17 +51,6 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc85xx/start.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) *(.text) *(.fixup) *(.got1) @@ -136,6 +112,18 @@ SECTIONS . = ALIGN(256); __init_end = .; + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000; + __bss_start = .; .bss (NOLOAD) : { @@ -144,6 +132,8 @@ SECTIONS *(.bss) *(COMMON) } + + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/idmr/mii.c b/board/idmr/mii.c index f130e6e5368..78a7028bcfa 100644 --- a/board/idmr/mii.c +++ b/board/idmr/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 44fc79cd58d..065014a11e4 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -321,7 +321,7 @@ nand_init (void) printf ("%4lu MB\n", totlen >>20); } -#endif /* CFG_CMD_NAND */ +#endif /* CONFIG_CMD_NAND */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) /* diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c index b61e84e3873..5c71dec8221 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ b/board/matrix_vision/mvbc_p/mvbc_p.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -109,7 +110,7 @@ void mvbc_init_gpio(void) struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08x\n", *(vu_long*)MPC5XXX_CDM_PORCFG); + printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG); out_be32(&gpio->simple_ddr, SIMPLE_DDR); out_be32(&gpio->simple_dvo, SIMPLE_DVO); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index f1c2e58edd0..ae3c2456fbc 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -464,7 +464,8 @@ void local_bus_init (void) if (lbc_mhz < 66) { lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - lbc->ltedr = 0xa4c80000; /* DK: !!! */ + lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | + LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ } else if (lbc_mhz >= 133) { lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ diff --git a/board/w7o/post2.c b/board/w7o/post2.c index e590128244e..6ee33eba36e 100644 --- a/board/w7o/post2.c +++ b/board/w7o/post2.c @@ -29,6 +29,12 @@ #include "errors.h" #include "dtt.h" +/* for LM75 DTT POST test */ +#define DTT_READ_TEMP 0x0 +#define DTT_CONFIG 0x1 +#define DTT_TEMP_HYST 0x2 +#define DTT_TEMP_SET 0x3 + #if defined(CONFIG_RTC_M48T35A) void rtctest(void) { diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index caa467d0268..24ff9b9956e 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -205,7 +205,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr); #endif - printf ("\nbaudrate = %d bps\n", (ulong)bd->bi_baudrate); + printf ("\nbaudrate = %ld bps\n", (ulong)bd->bi_baudrate); return 0; } diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 1c0a4161d0e..18d71008dad 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -36,7 +36,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_USB) +#if defined(CONFIG_CMD_USB) #include #endif @@ -217,7 +217,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ iflag = disable_interrupts(); -#if (CONFIG_COMMANDS & CFG_CMD_USB) +#if defined(CONFIG_CMD_USB) /* * turn off USB to prevent the host controller from writing to the * SDRAM while Linux is booting. This could happen (at least for OHCI @@ -251,10 +251,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) memmove_wd ((void *)load_start, (void *)os_data, os_len, CHUNKSZ); - - load_end = load_start + os_len; - puts("OK\n"); } + load_end = load_start + os_len; + puts("OK\n"); break; case IH_COMP_GZIP: printf (" Uncompressing %s ... ", type_name); diff --git a/common/cmd_flash.c b/common/cmd_flash.c index a7f66ddbfad..18d2250f30b 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -342,7 +342,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("Bad sector specification\n"); return 1; } - printf ("Erase Flash Sectors %d-%d in Bank # %d ", + printf ("Erase Flash Sectors %d-%d in Bank # %zu ", sect_first, sect_last, (info-flash_info)+1); rcode = flash_erase(info, sect_first, sect_last); return rcode; @@ -534,7 +534,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("Bad sector specification\n"); return 1; } - printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", + printf("%sProtect Flash Sectors %d-%d in Bank # %zu\n", p ? "" : "Un-", sect_first, sect_last, (info-flash_info)+1); for (i = sect_first; i <= sect_last; i++) { diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 97a873d1c96..d6ba79f7040 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -161,8 +161,6 @@ static uchar ide_wait (int dev, ulong t); #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ -void inline ide_outb(int dev, int port, unsigned char val); -unsigned char inline ide_inb(int dev, int port); static void input_data(int dev, ulong *sect_buf, int words); static void output_data(int dev, ulong *sect_buf, int words); static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); @@ -298,7 +296,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong addr = simple_strtoul(argv[2], NULL, 16); ulong cnt = simple_strtoul(argv[4], NULL, 16); ulong n; -#ifdef CFG_64BIT_STRTOUL +#ifdef CFG_64BIT_LBA lbaint_t blk = simple_strtoull(argv[3], NULL, 16); printf ("\nIDE read: device %d block # %qd, count %ld ... ", @@ -327,7 +325,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong addr = simple_strtoul(argv[2], NULL, 16); ulong cnt = simple_strtoul(argv[4], NULL, 16); ulong n; -#ifdef CFG_64BIT_STRTOUL +#ifdef CFG_64BIT_LBA lbaint_t blk = simple_strtoull(argv[3], NULL, 16); printf ("\nIDE write: device %d block # %qd, count %ld ... ", @@ -523,6 +521,28 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* ------------------------------------------------------------------------- */ +void inline +__ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); + outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); +} +void inline ide_outb (int dev, int port, unsigned char val) + __attribute__((weak, alias("__ide_outb"))); + +unsigned char inline +__ide_inb(int dev, int port) +{ + uchar val; + val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val); + return val; +} +unsigned char inline ide_inb(int dev, int port) + __attribute__((weak, alias("__ide_inb"))); + void ide_init (void) { @@ -817,28 +837,6 @@ set_pcmcia_timing (int pmode) /* ------------------------------------------------------------------------- */ -void inline -__ide_outb(int dev, int port, unsigned char val) -{ - debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", - dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); - outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); -} -void inline ide_outb (int dev, int port, unsigned char val) - __attribute__((weak, alias("__ide_outb"))); - -unsigned char inline -__ide_inb(int dev, int port) -{ - uchar val; - val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); - debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", - dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val); - return val; -} -unsigned char inline ide_inb(int dev, int port) - __attribute__((weak, alias("__ide_inb"))); - #ifdef __PPC__ # ifdef CONFIG_AMIGAONEG3SE static void diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c index 5982b76e6e9..c2442eed136 100644 --- a/common/cmd_mfsl.c +++ b/common/cmd_mfsl.c @@ -183,7 +183,7 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - printf ("%01x: 0x%08lx - %s %s read\n", fslnum, num, + printf ("%01x: 0x%08x - %s %s read\n", fslnum, num, blocking < 2 ? "non blocking" : "blocking", ((blocking == 1) || (blocking == 3)) ? "control" : "data" ); return 0; @@ -341,7 +341,7 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - printf ("%01x: 0x%08lx - %s %s write\n", fslnum, num, + printf ("%01x: 0x%08x - %s %s write\n", fslnum, num, blocking < 2 ? "non blocking" : "blocking", ((blocking == 1) || (blocking == 3)) ? "control" : "data" ); return 0; @@ -382,7 +382,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) puts ("Unsupported register\n"); return 1; } - printf (": 0x%08lx\n", val); + printf (": 0x%08x\n", val); return 0; } diff --git a/common/dlmalloc.c b/common/dlmalloc.c index c51351e9618..4a185620f98 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1457,7 +1457,7 @@ typedef struct malloc_chunk* mbinptr; indexing, maintain locality, and avoid some initialization tests. */ -#define top (bin_at(0)->fd) /* The topmost chunk */ +#define top (av_[2]) /* The topmost chunk */ #define last_remainder (bin_at(1)) /* remainder from last split */ @@ -1552,13 +1552,14 @@ void malloc_bin_reloc (void) #define BINBLOCKWIDTH 4 /* bins per block */ -#define binblocks (bin_at(0)->size) /* bitvector of nonempty blocks */ +#define binblocks_r ((INTERNAL_SIZE_T)av_[1]) /* bitvector of nonempty blocks */ +#define binblocks_w (av_[1]) /* bin<->block macros */ #define idx2binblock(ix) ((unsigned)1 << (ix / BINBLOCKWIDTH)) -#define mark_binblock(ii) (binblocks |= idx2binblock(ii)) -#define clear_binblock(ii) (binblocks &= ~(idx2binblock(ii))) +#define mark_binblock(ii) (binblocks_w = (mbinptr)(binblocks_r | idx2binblock(ii))) +#define clear_binblock(ii) (binblocks_w = (mbinptr)(binblocks_r & ~(idx2binblock(ii)))) @@ -2250,17 +2251,17 @@ Void_t* mALLOc(bytes) size_t bytes; search for best fitting chunk by scanning bins in blockwidth units. */ - if ( (block = idx2binblock(idx)) <= binblocks) + if ( (block = idx2binblock(idx)) <= binblocks_r) { /* Get to the first marked block */ - if ( (block & binblocks) == 0) + if ( (block & binblocks_r) == 0) { /* force to an even block boundary */ idx = (idx & ~(BINBLOCKWIDTH - 1)) + BINBLOCKWIDTH; block <<= 1; - while ((block & binblocks) == 0) + while ((block & binblocks_r) == 0) { idx += BINBLOCKWIDTH; block <<= 1; @@ -2315,7 +2316,7 @@ Void_t* mALLOc(bytes) size_t bytes; { if ((startidx & (BINBLOCKWIDTH - 1)) == 0) { - binblocks &= ~block; + av_[1] = (mbinptr)(binblocks_r & ~block); break; } --startidx; @@ -2324,9 +2325,9 @@ Void_t* mALLOc(bytes) size_t bytes; /* Get to the next possibly nonempty block */ - if ( (block <<= 1) <= binblocks && (block != 0) ) + if ( (block <<= 1) <= binblocks_r && (block != 0) ) { - while ((block & binblocks) == 0) + while ((block & binblocks_r) == 0) { idx += BINBLOCKWIDTH; block <<= 1; diff --git a/common/lcd.c b/common/lcd.c index eec1f53b0a7..e3347ec93c6 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -678,6 +678,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) /* Set color map */ for (i=0; icolor_table[i]; +#if !defined(CONFIG_ATMEL_LCD) ushort colreg = ( ((cte.red) << 8) & 0xf800) | ( ((cte.green) << 3) & 0x07e0) | @@ -691,6 +692,9 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap++; #elif defined(CONFIG_MPC823) cmap--; +#endif +#else /* CONFIG_ATMEL_LCD */ + lcd_setcolreg(i, cte.red, cte.green, cte.blue); #endif } } @@ -727,7 +731,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) for (i = 0; i < height; ++i) { WATCHDOG_RESET(); for (j = 0; j < width ; j++) -#if defined(CONFIG_PXA250) +#if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD) *(fb++) = *(bmap++); #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) *(fb++)=255-*(bmap++); @@ -740,6 +744,9 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } #endif +#ifdef CONFIG_VIDEO_BMP_GZIP +extern bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp); +#endif static void *lcd_logo (void) { @@ -761,6 +768,16 @@ static void *lcd_logo (void) addr = simple_strtoul(s, NULL, 16); do_splash = 0; +#ifdef CONFIG_VIDEO_BMP_GZIP + bmp_image_t *bmp = (bmp_image_t *)addr; + unsigned long len; + + if (!((bmp->header.signature[0]=='B') && + (bmp->header.signature[1]=='M'))) { + addr = (ulong)gunzip_bmp(addr, &len); + } +#endif + if (lcd_display_bitmap (addr, 0, 0) == 0) { return ((void *)lcd_base); } diff --git a/common/main.c b/common/main.c index 79ad2912a75..187ef8a3a5a 100644 --- a/common/main.c +++ b/common/main.c @@ -116,7 +116,7 @@ static __inline__ int abortboot(int bootdelay) u_int i; # ifdef CONFIG_AUTOBOOT_PROMPT - printf(CONFIG_AUTOBOOT_PROMPT, bootdelay); + printf(CONFIG_AUTOBOOT_PROMPT); # endif # ifdef CONFIG_AUTOBOOT_DELAY_STR @@ -212,7 +212,7 @@ static __inline__ int abortboot(int bootdelay) int abort = 0; #ifdef CONFIG_MENUPROMPT - printf(CONFIG_MENUPROMPT, bootdelay); + printf(CONFIG_MENUPROMPT); #else printf("Hit any key to stop autoboot: %2d ", bootdelay); #endif diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index 3f04b299838..26e88cb519b 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -203,7 +203,7 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) for (i = 0; i < CFG_INTC_0_NUM; i++) { if (act->handler != (interrupt_handler_t*) def_hdlr) { - printf ("%02d %08lx %08lx %d\n", i, + printf ("%02d %08x %08x %d\n", i, (int)act->handler, (int)act->arg, act->count); } act++; diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 63097940acc..e8baab5b1f5 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -76,7 +76,7 @@ void serial_setbrg (void) sd = (*sys_powerctrl & 0x03) + 2; /* calulate 2x baudrate and round */ - divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE))); + divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); if (divisorx2 & 0x01) divisorx2 = divisorx2 + 1; diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c index 38cd0d9a70f..8d280fbb7b0 100644 --- a/cpu/mpc8260/speed.c +++ b/cpu/mpc8260/speed.c @@ -162,6 +162,30 @@ int get_clocks (void) gd->cpu_clk = clkin; } +#ifdef CONFIG_PCI + gd->pci_clk = clkin; + + if (sccr & SCCR_PCI_MODE) { + uint pci_div; + uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; + + if (sccr & SCCR_PCI_MODCK) { + pci_div = 2; + if (pcidf == 9) { + pci_div *= 5; + } else if (pcidf == 0xB) { + pci_div *= 6; + } else { + pci_div *= (pcidf + 1); + } + } else { + pci_div = pcidf + 1; + } + + gd->pci_clk = (gd->cpm_clk * 2) / pci_div; + } +#endif + return (0); } @@ -220,26 +244,9 @@ int prt_8260_clks (void) printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", gd->cpu_clk, gd->cpm_clk, gd->bus_clk); - - if (sccr & SCCR_PCI_MODE) { - uint pci_div; - uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; - - if (sccr & SCCR_PCI_MODCK) { - pci_div = 2; - if (pcidf == 9) { - pci_div *= 5; - } else if (pcidf == 0xB) { - pci_div *= 6; - } else { - pci_div *= (pcidf + 1); - } - } else { - pci_div = pcidf + 1; - } - - printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div); - } +#ifdef CONFIG_PCI + printf (" - pci_clk %10ld\n", gd->pci_clk); +#endif putc ('\n'); return (0); diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index aeb5b65b330..ec5db31b0ff 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index b5a29593ea6..697ed03a2cb 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -40,7 +40,7 @@ void display_sysid (void) stamp = readl (&sysid->timestamp); localtime_r (&stamp, &t); asctime_r (&t, asc); - printf ("SYSID : %08x, %s", readl (&sysid->id), asc); + printf ("SYSID : %08lx, %s", readl (&sysid->id), asc); } diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index ec1765e171c..1c3632428ca 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1159,50 +1159,50 @@ static void program_codt(unsigned long *dimm_populated, if (dimm_type == SDRAM_DDR2) { codt |= SDRAM_CODT_DQS_1_8_V_DDR2; if ((total_dimm == 1) && (firstSlot == TRUE)) { - if (total_rank == 1) { + if (total_rank == 1) { /* PUUU */ codt |= CALC_ODT_R(0); modt0 = CALC_ODT_W(0); modt1 = 0x00000000; modt2 = 0x00000000; modt3 = 0x00000000; } - if (total_rank == 2) { + if (total_rank == 2) { /* PPUU */ codt |= CALC_ODT_R(0) | CALC_ODT_R(1); - modt0 = CALC_ODT_W(0); - modt1 = CALC_ODT_W(0); + modt0 = CALC_ODT_W(0) | CALC_ODT_W(1); + modt1 = 0x00000000; modt2 = 0x00000000; modt3 = 0x00000000; } } else if ((total_dimm == 1) && (firstSlot != TRUE)) { - if (total_rank == 1) { + if (total_rank == 1) { /* UUPU */ codt |= CALC_ODT_R(2); modt0 = 0x00000000; modt1 = 0x00000000; modt2 = CALC_ODT_W(2); modt3 = 0x00000000; } - if (total_rank == 2) { + if (total_rank == 2) { /* UUPP */ codt |= CALC_ODT_R(2) | CALC_ODT_R(3); modt0 = 0x00000000; modt1 = 0x00000000; - modt2 = CALC_ODT_W(2); - modt3 = CALC_ODT_W(2); + modt2 = CALC_ODT_W(2) | CALC_ODT_W(3); + modt3 = 0x00000000; } } if (total_dimm == 2) { - if (total_rank == 2) { + if (total_rank == 2) { /* PUPU */ codt |= CALC_ODT_R(0) | CALC_ODT_R(2); modt0 = CALC_ODT_RW(2); modt1 = 0x00000000; modt2 = CALC_ODT_RW(0); modt3 = 0x00000000; } - if (total_rank == 4) { + if (total_rank == 4) { /* PPPP */ codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3); - modt0 = CALC_ODT_RW(2); + modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3); modt1 = 0x00000000; - modt2 = CALC_ODT_RW(0); + modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1); modt3 = 0x00000000; } } diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 2c86a01a032..121dcbe1329 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -559,11 +559,6 @@ mmc_init(int verbose) set_GPIO_mode(GPIO8_MMCCS0_MD); #endif CKEN |= CKEN12_MMC; /* enable MMC unit clock */ -#if defined(CONFIG_ADSVIX) - /* turn on the power */ - GPCR(114) = GPIO_bit(114); - udelay(1000); -#endif MMC_CLKRT = MMC_CLKRT_0_3125MHZ; MMC_RESTO = MMC_RES_TO_MAX; diff --git a/doc/README.autoboot b/doc/README.autoboot index e4c41867351..2042fe5c406 100644 --- a/doc/README.autoboot +++ b/doc/README.autoboot @@ -114,10 +114,17 @@ What they do CONFIG_AUTOBOOT_PROMPT is displayed before the boot delay selected by CONFIG_BOOTDELAY starts. If it is not defined there is no output indicating that autoboot is in progress. - If "%d" is included, it is replaced by the number of seconds - remaining before autoboot will start, but it does not count - down the seconds. "autoboot in %d seconds\n" is a reasonable - prompt. + + Note that CONFIG_AUTOBOOT_PROMPT is used as the (only) + argument to a printf() call, so it may contain '%' format + specifications, provided that it also includes, sepearated by + commas exactly like in a printf statement, the required + arguments. It is the responsibility of the user to select only + such arguments that are valid in the given context. A + reasonable prompt could be defined as + + #define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds\n",bootdelay If CONFIG_AUTOBOOT_DELAY_STR or "bootdelaykey" is specified and this string is received from console input before diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 476c5e68992..c9ac3f307de 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -15,4 +15,4 @@ create image: # dd of=flash bs=1k count=4k if=/dev/zero # dd of=flash bs=1k conv=notrunc if=u-boot.bin start it: -# qemu-system-mips -pflash flash -monitor null -nographic +# qemu-system-mips -M mips -pflash flash -monitor null -nographic diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 9f2c1eced4d..3f78e2f5c84 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -143,12 +143,15 @@ void i2c_init(int speed, int slaveadd) { struct fsl_i2c *dev; + unsigned int temp; dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ - i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); + temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); + if (gd->flags & GD_FLG_RELOC) + i2c_bus_speed[0] = temp; writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ @@ -158,7 +161,9 @@ i2c_init(int speed, int slaveadd) writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ - i2c_bus_speed[1] = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); + temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); + if (gd->flags & GD_FLG_RELOC) + i2c_bus_speed[1] = temp; writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ @@ -168,12 +173,11 @@ i2c_init(int speed, int slaveadd) static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer(0); + unsigned long long timeval = get_ticks(); while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { - if (get_timer(timeval) > I2C_TIMEOUT) { + if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) return -1; - } } return 0; @@ -183,7 +187,7 @@ static __inline__ int i2c_wait(int write) { u32 csr; - ulong timeval = get_timer(0); + unsigned long long timeval = get_ticks(); do { csr = readb(&i2c_dev[i2c_bus_num]->sr); @@ -208,7 +212,7 @@ i2c_wait(int write) } return 0; - } while (get_timer (timeval) < I2C_TIMEOUT); + } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT)); debug("i2c_wait: timed out\n"); return -1; diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index 61aa1849c24..a151488d125 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -135,10 +135,10 @@ mmc_cmd(unsigned long cmd, unsigned long arg, status = mmci_readl(SR); } while (!(status & MMCI_BIT(CMDRDY))); - pr_debug("mmc: status 0x%08lx\n", status); + pr_debug("mmc: status 0x%08x\n", status); if (status & error_flags) { - printf("mmc: command %lu failed (status: 0x%08lx)\n", + printf("mmc: command %lu failed (status: 0x%08x)\n", cmd, status); return -EIO; } @@ -245,7 +245,7 @@ out: read_error: mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); - printf("mmc: bread failed, status = %08x, card status = %08x\n", + printf("mmc: bread failed, status = %08x, card status = %08lx\n", status, card_status); goto out; } @@ -284,13 +284,13 @@ static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) static void mmc_dump_cid(const struct mmc_cid *cid) { - printf("Manufacturer ID: %02lX\n", cid->mid); - printf("OEM/Application ID: %04lX\n", cid->oid); + printf("Manufacturer ID: %02X\n", cid->mid); + printf("OEM/Application ID: %04X\n", cid->oid); printf("Product name: %s\n", cid->pnm); - printf("Product Revision: %lu.%lu\n", + printf("Product Revision: %u.%u\n", cid->prv >> 4, cid->prv & 0x0f); printf("Product Serial Number: %lu\n", cid->psn); - printf("Manufacturing Date: %02lu/%02lu\n", + printf("Manufacturing Date: %02u/%02u\n", cid->mdt >> 4, cid->mdt & 0x0f); } @@ -501,7 +501,7 @@ int mmc_init(int verbose) mmc_blkdev.part_type = PART_TYPE_DOS; mmc_blkdev.block_read = mmc_bread; sprintf((char *)mmc_blkdev.vendor, - "Man %02x%04x Snr %08x", + "Man %02x%04x Snr %08lx", cid.mid, cid.oid, cid.psn); strncpy((char *)mmc_blkdev.product, cid.pnm, sizeof(mmc_blkdev.product)); diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 4340b1b5c7b..12647ef9861 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -306,6 +306,9 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) int i; int cword_offset; int cp_offset; +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) + u32 cmd_le = cpu_to_le32(cmd); +#endif uchar val; uchar *cp = (uchar *) cmdbuf; @@ -313,7 +316,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) cword_offset = (info->portwidth-i)%info->chipwidth; #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) cp_offset = info->portwidth - i; - val = *((uchar*)&cmd + cword_offset); + val = *((uchar*)&cmd_le + cword_offset); #else cp_offset = i - 1; val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c index fb7a4a939b0..10fcf0cdde8 100644 --- a/drivers/mtd/spi/atmel.c +++ b/drivers/mtd/spi/atmel.c @@ -205,7 +205,7 @@ static int dataflash_write_at45(struct spi_flash *flash, byte_addr = 0; } - debug("SF: AT45: Successfully programmed %u bytes @ 0x%x\n", + debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n", len, offset); ret = 0; @@ -268,7 +268,7 @@ int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len) page_addr++; } - debug("SF: AT45: Successfully erased %u bytes @ 0x%x\n", + debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n", len, offset); ret = 0; @@ -351,7 +351,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) * params->blocks_per_sector * params->nr_sectors; - debug("SF: Detected %s with page size %u, total %u bytes\n", + debug("SF: Detected %s with page size %lu, total %u bytes\n", params->name, page_size, asf->flash.size); return &asf->flash; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 060b5189968..c8b4e98c669 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -513,9 +513,11 @@ e1000_read_mac_addr(struct eth_device *nic) nic->enetaddr[5] += 1; } #ifdef CONFIG_E1000_FALLBACK_MAC - if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) - for ( i=0; i < NODE_ADDRESS_SIZE; i++ ) - nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff; + if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) { + unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; + + memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); + } #endif #else /* @@ -531,10 +533,9 @@ e1000_read_mac_addr(struct eth_device *nic) DEBUGFUNC(); s = getenv ("ethaddr"); - if (s == NULL){ + if (s == NULL) { return -E1000_ERR_EEPROM; - } - else{ + } else { for(ii = 0; ii < 6; ii++) { nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; if (s){ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c9e797e8c0c..de6fbab740c 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,18 +25,18 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a -COBJS-y += atmel_usart.o -COBJS-y += mcfuart.o +COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o +COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-y += ns9750_serial.o COBJS-y += ns16550.o -COBJS-y += s3c4510b_uart.o +COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-y += serial.o -COBJS-y += serial_max3100.o +COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-y += serial_pl010.o COBJS-y += serial_pl011.o -COBJS-y += serial_xuartlite.o +COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-y += serial_sh.o -COBJS-y += usbtty.o +COBJS-$(CONFIG_USB_TTY) += usbtty.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index f35b99730f7..f3b146c22d7 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -17,7 +17,6 @@ */ #include -#ifdef CONFIG_ATMEL_USART #include #include #include @@ -96,5 +95,3 @@ int serial_tstc(void) { return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0; } - -#endif /* CONFIG_ATMEL_USART */ diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 5eb4f458f81..a1fcd057a46 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -29,8 +29,6 @@ #include -#ifdef CONFIG_MCFUART - #include #include @@ -130,4 +128,3 @@ void serial_setbrg(void) uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; } -#endif /* CONFIG_MCFUART */ diff --git a/drivers/serial/s3c4510b_uart.c b/drivers/serial/s3c4510b_uart.c index ddcd591f84a..aa378e1ac1e 100644 --- a/drivers/serial/s3c4510b_uart.c +++ b/drivers/serial/s3c4510b_uart.c @@ -45,8 +45,6 @@ #include -#ifdef CONFIG_DRIVER_S3C4510_UART - #include #include "s3c4510b_uart.h" @@ -212,5 +210,3 @@ void serial_puts (const char *s) uart->m_ctrl.bf.sendBreak = 0; } - -#endif diff --git a/drivers/serial/serial_max3100.c b/drivers/serial/serial_max3100.c index 0611fc1dd41..4abc27109b4 100644 --- a/drivers/serial/serial_max3100.c +++ b/drivers/serial/serial_max3100.c @@ -26,8 +26,6 @@ #include #include -#ifdef CONFIG_MAX3100_SERIAL - DECLARE_GLOBAL_DATA_PTR; /**************************************************************/ @@ -298,5 +296,3 @@ int serial_tstc(void) void serial_setbrg(void) { } - -#endif diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 61e68873eb5..ef6371e66ec 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -27,8 +27,6 @@ #include #include -#ifdef CONFIG_XILINX_UARTLITE - #define RX_FIFO_OFFSET 0 /* receive FIFO, read only */ #define TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ #define STATUS_REG_OFFSET 8 /* status register, read only */ @@ -56,8 +54,13 @@ void serial_putc(const char c) { if (c == '\n') serial_putc('\r'); +<<<<<<< .merge_file_kaofiJ while (in_be32((void *)UARTLITE_STATUS) & SR_TX_FIFO_FULL); out_be32((void *)UARTLITE_TX_FIFO, (unsigned char) (c & 0xff)); +======= + while (in_be32((u32 *) UARTLITE_STATUS) & SR_TX_FIFO_FULL); + out_be32((u32 *) UARTLITE_TX_FIFO, (unsigned char) (c & 0xff)); +>>>>>>> .merge_file_zSz9BG } void serial_puts(const char * s) @@ -69,13 +72,20 @@ void serial_puts(const char * s) int serial_getc(void) { +<<<<<<< .merge_file_kaofiJ while (!(in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA)); return in_be32((void *)UARTLITE_RX_FIFO) & 0xff; +======= + while (!(in_be32((u32 *) UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA)); + return in_be32((u32 *) UARTLITE_RX_FIFO) & 0xff; +>>>>>>> .merge_file_zSz9BG } int serial_tstc(void) { +<<<<<<< .merge_file_kaofiJ return (in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA); +======= + return (in_be32((u32 *) UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA); +>>>>>>> .merge_file_zSz9BG } - -#endif /* CONFIG_MICROBLZE */ diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 2bc5c3c8387..e738c562714 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -23,8 +23,6 @@ #include -#ifdef CONFIG_USB_TTY - #include #include #include "usbtty.h" @@ -1007,6 +1005,3 @@ void usbtty_poll (void) udc_irq(); } - - -#endif diff --git a/drivers/usb/usbdcore.c b/drivers/usb/usbdcore.c index 808da9faa5c..53ed669e971 100644 --- a/drivers/usb/usbdcore.c +++ b/drivers/usb/usbdcore.c @@ -552,7 +552,7 @@ struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct urb *urb; if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) { - usberr (" F A T A L: malloc(%u) FAILED!!!!", + usberr (" F A T A L: malloc(%zu) FAILED!!!!", sizeof (struct urb)); return NULL; } diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 27df449660c..b332a825e30 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -100,7 +100,11 @@ void lcd_ctrl_init(void *lcdbase) value << ATMEL_LCDC_CLKVAL_OFFSET); /* Initialize control register 2 */ +#ifdef CONFIG_AVR32 + value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; +#else value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; +#endif if (panel_info.vl_tft) value |= ATMEL_LCDC_DISTYPE_TFT; diff --git a/include/api_public.h b/include/api_public.h index 9bc0501334a..5b0c09e3108 100644 --- a/include/api_public.h +++ b/include/api_public.h @@ -126,6 +126,7 @@ typedef unsigned long lbastart_t; #define DT_STOR_SCSI 0x0020 #define DT_STOR_USB 0x0040 #define DT_STOR_MMC 0x0080 +#define DT_STOR_SATA 0x0100 #define DEV_STA_CLOSED 0x0000 /* invalid, closed */ #define DEV_STA_OPEN 0x0001 /* open i.e. active */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 2f7f71036bf..95db0177cd4 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -25,6 +25,7 @@ #ifndef AT91RM9200_H #define AT91RM9200_H +#ifndef __ASSEMBLY__ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ /*****************************************************************************/ @@ -780,4 +781,5 @@ typedef struct _AT91S_PDC #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ -#endif +#endif /* __ASSEMBLY__ */ +#endif /* AT91RM9200_H */ diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index d030c262a58..06e52b137f5 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -22,6 +22,8 @@ #ifndef __ASM_AVR32_IO_H #define __ASM_AVR32_IO_H +#include + #ifdef __KERNEL__ /* diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h index 72ad49e5e2d..4f6970448b8 100644 --- a/include/asm-avr32/sysreg.h +++ b/include/asm-avr32/sysreg.h @@ -273,7 +273,9 @@ | SYSREG_BF(name,value)) /* Register access macros */ -#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) -#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value) +#define sysreg_read(reg) \ + ((unsigned long)__builtin_mfsr(SYSREG_##reg)) +#define sysreg_write(reg, value) \ + __builtin_mtsr(SYSREG_##reg, value) #endif /* __ASM_AVR32_SYSREG_H__ */ diff --git a/include/asm-nios2/types.h b/include/asm-nios2/types.h index f13d8bd4b47..ea859c07741 100644 --- a/include/asm-nios2/types.h +++ b/include/asm-nios2/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* __ASM_NIOS2_TYPES_H */ diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index c4af7971b16..ea49ddc515d 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -298,4 +298,13 @@ #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +/* LTEDR - Transfer Error Check Disable Register + */ +#define LTEDR_BMD 0x80000000 /* Bus monitor disable */ +#define LTEDR_PARD 0x20000000 /* Parity error checking disabled */ +#define LTEDR_WPD 0x04000000 /* Write protect error checking diable */ +#define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */ +#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */ +#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */ + #endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index c5ac6584acb..be2ce247782 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -51,6 +51,9 @@ typedef struct global_data { unsigned long cpm_clk; unsigned long scc_clk; unsigned long brg_clk; +#ifdef CONFIG_PCI + unsigned long pci_clk; +#endif #endif unsigned long mem_clk; #if defined(CONFIG_MPC83XX) diff --git a/include/command.h b/include/command.h index c3ef51d8c48..4a27e972476 100644 --- a/include/command.h +++ b/include/command.h @@ -27,6 +27,8 @@ #ifndef __COMMAND_H #define __COMMAND_H +#include + #ifndef NULL #define NULL 0 #endif diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h index 2ee8c61cea4..f677b9c80a1 100644 --- a/include/configs/ADS860.h +++ b/include/configs/ADS860.h @@ -51,7 +51,7 @@ /* This is picked up again in fads.h */ #define FADS_COMMANDS_ALREADY_DEFINED -#include "fads.h" +#include "../../board/fads/fads.h" #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 02f0c76e074..2f266a242ff 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -193,7 +193,8 @@ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 7389c38b9e1..cefdd29602d 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -131,7 +131,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ #ifdef CONFIG_BZIP2 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ #else diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index a992498dc08..84efd2fe086 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -371,7 +371,8 @@ #define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ #define CONFIG_PREBOOT "" #define CONFIG_BOOTCOMMAND "fdcboot; diskboot" -#define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d " +#define CONFIG_MENUPROMPT \ + "Press any key to interrupt autoboot: %2d ", bootdelay #define CONFIG_MENUKEY ' ' #define CONFIG_MENUCOMMAND "menu" /* #define CONFIG_AUTOBOOT_KEYED */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 6b585bed5f7..c1735392022 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -152,8 +152,9 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /* Only interrupt boot if special string is typed */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Autobooting in %d seconds\n", bootdelay #undef CONFIG_AUTOBOOT_DELAY_STR #undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ #define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 0f5f85c22a6..64c9ac076da 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -345,8 +345,9 @@ int du440_phy_addr(int devnum); #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h index 18de6b00e7a..38295c4550b 100644 --- a/include/configs/FADS860T.h +++ b/include/configs/FADS860T.h @@ -38,7 +38,7 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 -#include "fads.h" +#include "../../board/fads/fads.h" #ifdef USE_REAL_FLASH_VALUES /* diff --git a/include/configs/GTH.h b/include/configs/GTH.h index 00e09f703cd..461670a1042 100644 --- a/include/configs/GTH.h +++ b/include/configs/GTH.h @@ -62,8 +62,9 @@ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press space to abort autoboot in %d second\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index f6c31ea8497..e52fbfde0e7 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -488,7 +488,8 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ #if 0 -#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay #endif #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ #define CONFIG_SILENT_CONSOLE 1 diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index e558aa481b3..be0c7af8f3e 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -454,7 +454,8 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ #if 0 -#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay #endif #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ #define CONFIG_SILENT_CONSOLE 1 diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index e0e85548115..233a8d19fa9 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -41,7 +41,7 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 -#include "fads.h" +#include "../../board/fads/fads.h" #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index 1867c5bf0a2..f4d18427710 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -27,7 +27,7 @@ #define CONFIG_SDRAM_50MHZ 1 -#include "fads.h" +#include "../../board/fads/fads.h" #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 04580b7a264..8c8a445c8b3 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -40,7 +40,7 @@ #define CONFIG_MISC_INIT_R 1 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef (CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 #endif @@ -255,7 +255,7 @@ #define CONFIG_NET_RETRY_COUNT 5 #define CONFIG_E1000 -#define CONFIG_E1000_FALLBACK_MAC 0xb6b445ebfbc0 +#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 } #undef CONFIG_MPC5xxx_FEC #undef CONFIG_PHY_ADDR #define CONFIG_NETDEV eth0 @@ -268,7 +268,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #undef CFG_LONGHELP #define CFG_PROMPT "=> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef (CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index d08d79520c9..8e247af63cd 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -59,17 +59,18 @@ #define CONFIG_CLOCKS_IN_MHZ 1 -#define CONFIG_BOARD_TYPES 1 +#define CONFIG_BOARD_TYPES 1 #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds (stop with 's')...\n", bootdelay #define CONFIG_AUTOBOOT_STOP_STR "s" #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 60 diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 0b094827d76..84c6e9b6179 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -65,9 +65,10 @@ #define CFG_MEASURE_CPUCLK #define CFG_8XX_XIN CONFIG_8xx_OSCLK -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d seconds...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d seconds...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "ids" #define CONFIG_BOOT_RETRY_TIME 900 #define CONFIG_BOOT_RETRY_MIN 30 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 0bd77c07b65..a3d1c56dc25 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -154,8 +154,9 @@ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index e8b405a8849..42f1d8d0062 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -409,7 +409,8 @@ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 872765c92f4..faae407da5d 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -68,7 +68,8 @@ #ifdef DEPLOYMENT #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds (stop with 'st')...\n", bootdelay #define CONFIG_AUTOBOOT_STOP_STR "st" #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1 diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index 3aee45c3c7c..aefc7eecbd1 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -465,7 +465,7 @@ #if 1 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "delayabit" #define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ #endif diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h deleted file mode 100644 index 427b5482f5c..00000000000 --- a/include/configs/adsvix.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the LUBBOCK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ -#define CONFIG_ADSVIX 1 /* on a Adsvix Board */ -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define RTC - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_DOS_PARTITION 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_PCMCIA - -#undef CONFIG_CMD_NET - - -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_SERVERIP 192.168.1.99 -#define CONFIG_BOOTCOMMAND "run boot_flash" -#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ - " rw root=/dev/ram initrd=0xa0800000,5m" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "program_boot_cf=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_cf=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_cf=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_cf=" \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0030000 uzImage && " \ - "fatload ide 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "program_boot_mmc=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_mmc=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_mmc=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa0030000 uzImage && " \ - "fatload mmc 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "boot_flash=" \ - "cp.b 0x1c0000 0xa0800000 0x500000; " \ - "bootm 0x40000\0" \ - -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -/* #define CONFIG_INITRD_TAG 1 */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * GPIO settings - */ - -#define CFG_GPSR0_VAL 0x00018004 -#define CFG_GPSR1_VAL 0x004F0080 -#define CFG_GPSR2_VAL 0x13EFC000 -#define CFG_GPSR3_VAL 0x0006E032 -#define CFG_GPCR0_VAL 0x084AFE1A -#define CFG_GPCR1_VAL 0x003003F2 -#define CFG_GPCR2_VAL 0x0C014000 -#define CFG_GPCR3_VAL 0x00000C00 -#define CFG_GPDR0_VAL 0xCBC3BFFC -#define CFG_GPDR1_VAL 0x00FFABF3 -#define CFG_GPDR2_VAL 0x1EEFFC00 -#define CFG_GPDR3_VAL 0x0187EC32 -#define CFG_GAFR0_L_VAL 0x84400000 -#define CFG_GAFR0_U_VAL 0xA51A8010 -#define CFG_GAFR1_L_VAL 0x699A955A -#define CFG_GAFR1_U_VAL 0x0005A0AA -#define CFG_GAFR2_L_VAL 0x40000000 -#define CFG_GAFR2_U_VAL 0x0109A400 -#define CFG_GAFR3_L_VAL 0x54000000 -#define CFG_GAFR3_U_VAL 0x00001409 - -#define CFG_PSSR_VAL 0x20 - -/* - * Clock settings - */ -#define CFG_CKEN 0x00400200 -#define CFG_CCCR 0x02000290 /* 520Mhz */ -/* #define CFG_CCCR 0x02000210 416 Mhz */ - -/* - * Memory settings - */ - -#define CFG_MSC0_VAL 0x23F2B3DB -#define CFG_MSC1_VAL 0x0000CCD1 -#define CFG_MSC2_VAL 0x0000B884 -#define CFG_MDCNFG_VAL 0x08000AC8 -#define CFG_MDREFR_VAL 0x0000001E -#define CFG_MDMRS_VAL 0x00000000 - -#define CFG_FLYCNFG_VAL 0x00010001 -#define CFG_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000002 -#define CFG_MCMEM0_VAL 0x00004204 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00008407 -#define CFG_MCIO1_VAL 0x00000000 - -#define CONFIG_PXA_PCMCIA 1 -#define CONFIG_PXA_IDE 1 - -#define CONFIG_PCMCIA_SLOT_A 1 -/* just to keep build system happy */ - -#define CFG_PCMCIA_MEM_ADDR 0x28000000 -#define CFG_PCMCIA_MEM_SIZE 0x04000000 - - -#define CFG_IDE_MAXBUS 1 -/* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 -/* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR 0x20000000 - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0x1f0 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0x1f0 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x3f0 - -/* - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 - -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x20000 - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* write flash less slowly */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 - -/* Flash environment locations */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 89732968ade..5884611b9ad 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -103,14 +103,6 @@ */ #define CONFIG_SERIAL1 1 /* UART1 on H4 */ - /* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP24XX_I2C - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 951ce160a45..cd2eae20634 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -112,16 +112,11 @@ */ #include -#define CONFIG_CMD_MII #define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_LOADS - +#define CFG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -137,6 +132,7 @@ #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ +#include /* needed for port definitions */ #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 84d235ea9d5..f040b863c77 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -82,8 +82,8 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 90910bb98a5..68f0cecf39e 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -110,8 +110,8 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 03472a8869c..d3a2f69edea 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -110,8 +110,8 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 07add821a94..a37ba92416b 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -110,8 +110,8 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index f9af67540a0..a6c5b6e24ed 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -110,8 +110,8 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/csb637.h b/include/configs/csb637.h index e9c6d8e7aec..735a211e07e 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -114,17 +114,11 @@ */ #include -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_PING -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_LOADS - +#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -140,6 +134,7 @@ #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ +#include /* needed for port definitions */ #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) @@ -155,6 +150,8 @@ #define NAND_CTL_CLRCLE(nandptr) #define NAND_CTL_SETCLE(nandptr) +#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */ + #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 #define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2d6ca70a54..7f7190bcdb4 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -54,8 +54,9 @@ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press space to abort autoboot in %d second\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 7c2c224060d..d9187825e54 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -279,7 +279,8 @@ * To stop use: " " */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Autobooting in %d seconds, press \" \" to stop\n", bootdelay #define CONFIG_AUTOBOOT_STOP_STR " " #undef CONFIG_AUTOBOOT_DELAY_STR #define DEBUG_BOOTKEYS 0 diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 01e79701623..264192f2620 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -224,7 +224,7 @@ */ #define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press to stop\n" + "press to stop\n", bootdelay #define CONFIG_AUTOBOOT_STOP_STR " " #undef CONFIG_AUTOBOOT_DELAY_STR #define DEBUG_BOOTKEYS 0 diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index d3908b9eaf4..bc642941162 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -82,7 +82,8 @@ #undef CONFIG_BOOT_RETRY_TIME #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Boot in %02d seconds ('s' to stop)..." +#define CONFIG_AUTOBOOT_PROMPT \ + "Boot in %02d seconds ('s' to stop)...", bootdelay #define CONFIG_AUTOBOOT_STOP_STR "s" #define CONFIG_CMD_IDE diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 8a8270260a3..87abfba14c2 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -252,7 +252,8 @@ #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #if 0 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d sec...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ #endif /*----------------------------------------------------------------------*/ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index cf406c8c0da..2f3a0660628 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -277,7 +277,8 @@ #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #if 0 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d sec...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ #endif diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index 095fdaf5c8b..e4be1ed33fe 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -40,7 +40,6 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -#undef CONFIG_AUTOBOOT_PROMPT #define CONFIG_MENUPROMPT "." /* @@ -105,7 +104,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "unlock=yes\0" -#define CFG_CMD_JFFS2 +#define CONFIG_CMD_JFFS2 #undef CONFIG_CMD_EEPROM #define CONFIG_CMD_NET #define CONFIG_CMD_RUN diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index b6843af3dc6..3d1eafee696 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -96,7 +96,7 @@ #undef CONFIG_AUTOBOOT_DELAY_STR #undef CONFIG_BOOTARGS #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press \"\" to stop\n" + "press \"\" to stop\n", bootdelay #define CONFIG_ETHADDR 00:50:C2:40:10:00 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 2eb4af1554d..87264fbb4b5 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -230,7 +230,8 @@ #undef CONFIG_SILENT_CONSOLE /* enable silent startup */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_DELAY_STR "d" diff --git a/include/configs/netstar.h b/include/configs/netstar.h index d4deda407fb..756b7c26717 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -195,7 +195,8 @@ #if 0 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d secs...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nNetStar PBX - boot in %d secs...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ #endif diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 56b4d92f1a7..dee664361f9 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -228,7 +228,8 @@ * To stop use: " " */ # define CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" +# define CONFIG_AUTOBOOT_PROMPT \ + "Autobooting in %d seconds, press \" \" to stop\n", bootdelay # define CONFIG_AUTOBOOT_STOP_STR " " # undef CONFIG_AUTOBOOT_DELAY_STR # define DEBUG_BOOTKEYS 0 diff --git a/include/configs/quantum.h b/include/configs/quantum.h index f49e2b0716e..cc261c33e10 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -116,7 +116,8 @@ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d sec...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "system" /* * Miscellaneous configurable options diff --git a/include/configs/rmu.h b/include/configs/rmu.h index 28fb7c3318c..596bf155660 100644 --- a/include/configs/rmu.h +++ b/include/configs/rmu.h @@ -111,7 +111,8 @@ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d sec...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "system" /* diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 2a398e8c45c..8427752d78e 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -436,7 +436,7 @@ * To stop use: " " */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" +#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" #define CONFIG_AUTOBOOT_STOP_STR " " #undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 79931372113..b92344ccc18 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -306,7 +306,8 @@ */ #undef CONFIG_AUTOBOOT_KEYED #ifdef CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" +# define CONFIG_AUTOBOOT_PROMPT \ + "Autobooting in %d seconds, press \" \" to stop\n", bootdelay # define CONFIG_AUTOBOOT_STOP_STR " " # undef CONFIG_AUTOBOOT_DELAY_STR # define DEBUG_BOOTKEYS 0 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index f6e40def518..87311ea6c7a 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -132,7 +132,8 @@ #if 1 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nSC3 - booting... stop with ENTER\n" #define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */ #define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */ #endif diff --git a/include/configs/trab.h b/include/configs/trab.h index de36fca11e7..b0615a0e377 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -289,7 +289,8 @@ #if 1 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d sec...\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ #endif diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index 287a6187a2d..1675ab752cb 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -58,7 +58,7 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay #define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ #define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 5a6b8559168..c71da608440 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -47,6 +47,12 @@ #endif #if defined(CONFIG_440) +/* + * Enable long long (%ll ...) printf format on 440 PPC's since most of + * them support 36bit physical addressing + */ +#define CFG_64BIT_VSPRINTF +#define CFG_64BIT_STRTOUL #include #else #include diff --git a/lib_arm/board.c b/lib_arm/board.c index 80b149b534a..a09386046c3 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -233,6 +233,18 @@ static int init_func_i2c (void) } #endif +#ifdef CONFIG_SKIP_RELOCATE_UBOOT +/* + * This routine sets the relocation done flag, because even if + * relocation is skipped, the flag is used by other generic code. + */ +static int reloc_init(void) +{ + gd->flags |= GD_FLG_RELOC; + return 0; +} +#endif + /* * Breathe some life into the board... * @@ -262,6 +274,11 @@ int print_cpuinfo (void); /* test-only */ init_fnc_t *init_sequence[] = { cpu_init, /* basic cpu dependent setup */ +#if defined(CONFIG_SKIP_RELOCATE_UBOOT) + reloc_init, /* Set the relocation done flag, must + do this AFTER cpu_init(), but as soon + as possible */ +#endif board_init, /* basic board dependent setup */ interrupt_init, /* set up exceptions */ env_init, /* initialize environment */ diff --git a/lib_arm/bootm.c b/lib_arm/bootm.c index 6b4a80723ff..b838c374ac6 100644 --- a/lib_arm/bootm.c +++ b/lib_arm/bootm.c @@ -43,9 +43,6 @@ static void setup_memory_tags (bd_t *bd); # endif static void setup_commandline_tag (bd_t *bd, char *commandline); -#if 0 -static void setup_ramdisk_tag (bd_t *bd); -#endif # ifdef CONFIG_INITRD_TAG static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end); diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 28d371d5e68..6eba784b5c1 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -199,6 +199,11 @@ unsigned long long get_ticks(void) return get_timer(0); } +unsigned long usec2ticks(unsigned long usec) +{ + return get_timer(usec); +} + /* * This function is derived from PowerPC code (timebase clock frequency). * On M68K it returns the number of timer ticks per second. diff --git a/lib_sparc/board.c b/lib_sparc/board.c index af301c046e1..205a8ca5327 100644 --- a/lib_sparc/board.c +++ b/lib_sparc/board.c @@ -451,7 +451,7 @@ void board_init_f(ulong bootflag) if ((s = getenv("bootfile")) != NULL) { copy_filename(BootFile, s, sizeof(BootFile)); } -#endif /* CFG_CMD_NET */ +#endif /* CONFIG_CMD_NET */ WATCHDOG_RESET(); @@ -483,7 +483,7 @@ void board_init_f(ulong bootflag) WATCHDOG_RESET(); puts("IDE: "); ide_init(); -#endif /* CFG_CMD_IDE */ +#endif /* CONFIG_CMD_IDE */ #ifdef CONFIG_LAST_STAGE_INIT WATCHDOG_RESET(); diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 0667fc1a54c..cedc8e02e6e 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -57,7 +57,7 @@ $(nandobj)u-boot-spl: $(OBJS) # create symbolic links for common files # from cpu directory -$(obj)44x_spd_ddr2.c: ecc.h +$(obj)44x_spd_ddr2.c: $(obj)ecc.h @rm -f $(obj)44x_spd_ddr2.c ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile index f10ed02292a..1f996a40be6 100644 --- a/onenand_ipl/board/apollon/Makefile +++ b/onenand_ipl/board/apollon/Makefile @@ -1,6 +1,5 @@ include $(TOPDIR)/config.mk -include $(TOPDIR)/include/config.mk include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds @@ -9,8 +8,11 @@ AFLAGS += -DCONFIG_ONENAND_IPL CFLAGS += -DCONFIG_ONENAND_IPL OBJCLFAGS += --gap-fill=0x00 -SOBJS = start.o low_levelinit.o -COBJS = apollon.o onenand_read.o onenand_boot.o +SOBJS := low_levelinit.o +SOBJS += start.o +COBJS := apollon.o +COBJS += onenand_read.o +COBJS += onenand_boot.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -34,28 +36,39 @@ $(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl: $(OBJS) cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - -Map $(onenandobj)onenand-ipl.map \ - -o $(onenandobj)onenand-ipl + -Map $@.map -o $@ # create symbolic links from common files # from cpu directory $(obj)start.S: - rm -f $(obj)start.S - ln -s $(SRCTREE)/cpu/$(CPU)/start.S $(obj)start.S + @rm -f $@ + ln -s $(SRCTREE)/cpu/$(CPU)/start.S $@ # from onenand_ipl directory $(obj)onenand_ipl.h: - rm -f $(obj)onenand_ipl.h - ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $(obj)onenand_ipl.h + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@ $(obj)onenand_boot.c: $(obj)onenand_ipl.h - rm -f $(obj)onenand_boot.c - ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $(obj)onenand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@ $(obj)onenand_read.c: $(obj)onenand_ipl.h - rm -f $(obj)onenand_read.c - ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $(obj)onenand_read.c + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@ + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)apollon.c: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/apollon.c $@ + +$(obj)low_levelinit.S: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/low_levelinit.S $@ +endif + +######################################################################### $(obj)%.o: $(obj)%.S $(CC) $(AFLAGS) -c -o $@ $< @@ -63,6 +76,9 @@ $(obj)%.o: $(obj)%.S $(obj)%.o: $(obj)$.c $(CC) $(CFLAGS) -c -o $@ $< +# defines $(obj).depend target include $(SRCTREE)/rules.mk sinclude $(obj).depend + +######################################################################### diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index 6152eb21a90..110df6e9103 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -76,7 +76,9 @@ static struct { {0x3b, "CSRR1", 0x00000000, 0x00000000}, {0x3d, "DEAR", 0x00000000, 0x00000000}, {0x3e, "ESR", 0x00000000, 0x00000000}, +#ifdef CONFIG_440 {0x3f, "IVPR", 0xffff0000, 0x00000000}, +#endif {0x100, "USPRG0", 0x00000000, 0x00000000}, {0x104, "SPRG4", 0x00000000, 0x00000000}, {0x105, "SPRG5", 0x00000000, 0x00000000}, diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c index 45b9ff26e86..7a2583dc747 100644 --- a/post/lib_ppc/b.c +++ b/post/lib_ppc/b.c @@ -95,6 +95,7 @@ int cpu_post_test_b (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); if (ret == 0) { @@ -188,6 +189,9 @@ int cpu_post_test_b (void) } } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/cmp.c b/post/lib_ppc/cmp.c index 8d80f86aafd..13809d417bb 100644 --- a/post/lib_ppc/cmp.c +++ b/post/lib_ppc/cmp.c @@ -102,6 +102,7 @@ int cpu_post_test_cmp (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); for (i = 0; i < cpu_post_cmp_size && ret == 0; i++) { @@ -124,6 +125,9 @@ int cpu_post_test_cmp (void) } } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/cmpi.c b/post/lib_ppc/cmpi.c index 92b4d57b1fd..5ecfe872a4f 100644 --- a/post/lib_ppc/cmpi.c +++ b/post/lib_ppc/cmpi.c @@ -102,6 +102,7 @@ int cpu_post_test_cmpi (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++) { @@ -124,6 +125,9 @@ int cpu_post_test_cmpi (void) } } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/complex.c b/post/lib_ppc/complex.c index 271392a0e8c..4983c51919e 100644 --- a/post/lib_ppc/complex.c +++ b/post/lib_ppc/complex.c @@ -101,6 +101,7 @@ static int cpu_post_test_complex_2 (void) int cpu_post_test_complex (void) { int ret = 0; + int flag = disable_interrupts(); if (ret == 0) { @@ -117,6 +118,9 @@ int cpu_post_test_complex (void) post_log ("Error at complex test !\n"); } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/cr.c b/post/lib_ppc/cr.c index 0bd9e748f2a..2c7976ac311 100644 --- a/post/lib_ppc/cr.c +++ b/post/lib_ppc/cr.c @@ -248,6 +248,7 @@ int cpu_post_test_cr (void) int ret = 0; unsigned int i; unsigned long cr_sav; + int flag = disable_interrupts(); asm ( "mfcr %0" : "=r" (cr_sav) : ); @@ -347,6 +348,9 @@ int cpu_post_test_cr (void) asm ( "mtcr %0" : : "r" (cr_sav)); + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/load.c b/post/lib_ppc/load.c index 86bc2234cf5..eccebb7ca14 100644 --- a/post/lib_ppc/load.c +++ b/post/lib_ppc/load.c @@ -178,6 +178,7 @@ int cpu_post_test_load (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); for (i = 0; i < cpu_post_load_size && ret == 0; i++) { @@ -246,6 +247,9 @@ int cpu_post_test_load (void) } } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/multi.c b/post/lib_ppc/multi.c index 5d3f5842811..47135abd4ca 100644 --- a/post/lib_ppc/multi.c +++ b/post/lib_ppc/multi.c @@ -44,6 +44,7 @@ int cpu_post_test_multi (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); if (ret == 0) { @@ -72,6 +73,9 @@ int cpu_post_test_multi (void) post_log ("Error at multi test !\n"); } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/store.c b/post/lib_ppc/store.c index 09ec48554e2..c96f263e300 100644 --- a/post/lib_ppc/store.c +++ b/post/lib_ppc/store.c @@ -163,6 +163,7 @@ int cpu_post_test_store (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); for (i = 0; i < cpu_post_store_size && ret == 0; i++) { @@ -226,6 +227,9 @@ int cpu_post_test_store (void) } } + if (flag) + enable_interrupts(); + return ret; } diff --git a/post/lib_ppc/string.c b/post/lib_ppc/string.c index b2daa880496..3683ac9956a 100644 --- a/post/lib_ppc/string.c +++ b/post/lib_ppc/string.c @@ -47,6 +47,7 @@ int cpu_post_test_string (void) { int ret = 0; unsigned int i; + int flag = disable_interrupts(); if (ret == 0) { @@ -97,6 +98,9 @@ int cpu_post_test_string (void) post_log ("Error at string test !\n"); } + if (flag) + enable_interrupts(); + return ret; } -- cgit v1.3.1