From 7118d961cccdb3cf86f3e2eebf19c476bba5aca9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:26 +0200 Subject: imx: kontron-sl-mx6ul: Enable standard boot and disable legacy distro boot Disable the legacy distro boot and use bootstd instead. Signed-off-by: Frieder Schrempf --- include/configs/kontron-sl-mx6ul.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'include/configs') diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 015df01db4e..e2152eb05ed 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -24,22 +24,10 @@ /* Board and environment settings */ #define CFG_MXC_UART_BASE UART4_BASE -/* Boot order for distro boot */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0, UBI, boot) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#include - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS BOOTENV - #endif /* __KONTRON_MX6UL_CONFIG_H */ -- cgit v1.3.1 From 28d6f787b0deb3f66118857297a855233eba18d1 Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Tue, 2 Sep 2025 08:07:32 +0200 Subject: Add imx8mp-libra-fpsc board Add new imx8mp-libra-fpsc board. Bootph tags as well as USB device tree nodes are in u-boot.dtsi for now and will be removed when upstreamed. The Libra i.MX 8M Plus FPSC is a single board computer. It uses an i.MX 8M Plus FPSC [1] System on Module which utilizes the FPSC standard [2]. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc Signed-off-by: Benjamin Hahn Reviewed-by: Teresa Remmet Tested-by: Teresa Remmet Signed-off-by: Yannic Moog --- arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi | 131 ++ arch/arm/mach-imx/imx8m/Kconfig | 10 + board/phytec/imx8mp-libra-fpsc/Kconfig | 16 + board/phytec/imx8mp-libra-fpsc/MAINTAINERS | 9 + board/phytec/imx8mp-libra-fpsc/Makefile | 10 + board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c | 89 + .../phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env | 19 + board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg | 9 + board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c | 1813 ++++++++++++++++++++ board/phytec/imx8mp-libra-fpsc/spl.c | 132 ++ configs/imx8mp-libra-fpsc_defconfig | 175 ++ doc/board/phytec/imx8mp-libra-fpsc.rst | 83 + doc/board/phytec/index.rst | 1 + include/configs/imx8mp-libra-fpsc.h | 27 + 14 files changed, 2524 insertions(+) create mode 100644 arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi create mode 100644 board/phytec/imx8mp-libra-fpsc/Kconfig create mode 100644 board/phytec/imx8mp-libra-fpsc/MAINTAINERS create mode 100644 board/phytec/imx8mp-libra-fpsc/Makefile create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env create mode 100644 board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg create mode 100644 board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c create mode 100644 board/phytec/imx8mp-libra-fpsc/spl.c create mode 100644 configs/imx8mp-libra-fpsc_defconfig create mode 100644 doc/board/phytec/imx8mp-libra-fpsc.rst create mode 100644 include/configs/imx8mp-libra-fpsc.h (limited to 'include/configs') diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi new file mode 100644 index 00000000000..1320f1540ed --- /dev/null +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc2", "mmc1", "ethernet"; + + efi { + compatible = "u-boot,distro-efi"; + }; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart4 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart4 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; +}; + +/* USB1 Type-C */ +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + fsl,power-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + vbus-supply = <®_vdd_5v0>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 74416a78847..e7bc154b805 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP select IMX8M_LPDDR4 imply OF_UPSTREAM +config TARGET_IMX8MP_LIBRA_FPSC + bool "PHYTEC Libra i.MX 8M Plus FPSC" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + imply OF_UPSTREAM + help + Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC. + config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" select IMX8MM @@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" +source "board/phytec/imx8mp-libra-fpsc/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/polyhex/imx8mp_debix_model_a/Kconfig" diff --git a/board/phytec/imx8mp-libra-fpsc/Kconfig b/board/phytec/imx8mp-libra-fpsc/Kconfig new file mode 100644 index 00000000000..4961611f7b2 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Kconfig @@ -0,0 +1,16 @@ +if TARGET_IMX8MP_LIBRA_FPSC + +config SYS_BOARD + default "imx8mp-libra-fpsc" + +config SYS_VENDOR + default "phytec" + +config IMX_CONFIG + default "board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg" + +config SYS_CONFIG_NAME + default "imx8mp-libra-fpsc" + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/imx8mp-libra-fpsc/MAINTAINERS b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS new file mode 100644 index 00000000000..1fd99888a2e --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS @@ -0,0 +1,9 @@ +Libra-i.MX 8M Plus +M: Teresa Remmet +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ +S: Maintained +F: arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +F: board/phytec/imx8mp-libra-fpsc/ +F: configs/imx8mp-libra-fpsc_defconfig +F: include/configs/imx8mp-libra-fpsc.h +F: doc/board/phytec/imx8mp-libra-fpsc.rst diff --git a/board/phytec/imx8mp-libra-fpsc/Makefile b/board/phytec/imx8mp-libra-fpsc/Makefile new file mode 100644 index 00000000000..21b35d9142f --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2025 PHYTEC Messtechnik GmbH + +obj-y += imx8mp-libra-fpsc.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c new file mode 100644 index 00000000000..ffa21da1b34 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EEPROM_ADDR 0x51 + +#define TUSB_PORT_POL_CRTL_REG 0xB +#define TUSB_CUSTOM_POL BIT(7) +#define TUSB_P0_POL BIT(0) + +/* + * WORKAROUND for PCM-937-L 1618.0, 1618.1. + * USB HUB TUSB8042A has swapped upstream pin polarity. + * Set i2c registers to inform the hub that the lines + * are swapped. + */ +void tusb8042a_swap_lines(void) +{ + const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL); + const int addr = 0x44; + struct udevice *dev = 0; + int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev); + + if (!ret) + dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1); + else + printf("TUSB8042A: Failed to fixup USB HUB.\n"); +} + +int board_init(void) +{ + tusb8042a_swap_lines(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + if (!strcmp(env_get("boot_targets"), env_get_default("boot_targets"))) + env_set("boot_targets", "mmc1 mmc2 ethernet"); + break; + case MMC3_BOOT: + env_set_ulong("mmcdev", 2); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; + default: + break; + } + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env new file mode 100644 index 00000000000..c744248ab7a --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env @@ -0,0 +1,19 @@ +boot_script_dhcp=boot.scr.uimg +console=ttymxc3,CONFIG_BAUDRATE +emmc_dev=2 /* This is needed by built-in uuu flash scripts */ +fdtfile=CONFIG_DEFAULT_FDT_FILE +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +mmcroot=2 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 +sd_dev=1 /* This is needed by built-in uuu flash scripts */ +ip_dyn=yes +nfsroot=/srv/nfs diff --git a/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg new file mode 100644 index 00000000000..6dedf1724ab --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c new file mode 100644 index 00000000000..1b501828726 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c @@ -0,0 +1,1813 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.5.0_9-1ddf053d. + * DDR PHY FW2020.06 + */ + +#include +#include + +/* Initialize DDRC registers */ +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400020, 0x1323}, + {0x3d400024, 0x1e84800}, + {0x3d400064, 0x7a0118}, + {0x3d400070, 0x7027f90}, + {0x3d400074, 0x790}, + {0x3d4000d0, 0xc00307a3}, + {0x3d4000d4, 0xc50000}, + {0x3d4000dc, 0xf4003f}, + {0x3d4000e0, 0xe30000}, + {0x3d4000e8, 0x440048}, + {0x3d4000ec, 0x140048}, + {0x3d400100, 0x2028222a}, + {0x3d400104, 0x8083f}, + {0x3d40010c, 0xe0e000}, + {0x3d400110, 0x12040a12}, + {0x3d400114, 0x2050f0f}, + {0x3d400118, 0x1010009}, + {0x3d40011c, 0x502}, + {0x3d400130, 0x20800}, + {0x3d400134, 0xe100002}, + {0x3d400138, 0x120}, + {0x3d400144, 0xc80064}, + {0x3d400180, 0x3e8001e}, + {0x3d400184, 0x3207a12}, + {0x3d400188, 0x0}, + {0x3d400190, 0x4a3820e}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x230e}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x7}, + {0x3d4001c4, 0x1}, + {0x3d4000f4, 0x799}, + {0x3d400108, 0x9141d1c}, + {0x3d400200, 0x1f}, + {0x3d400208, 0x0}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, + {0x3d400250, 0x1705}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400404, 0x72ff}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x18}, + {0x2002e, 0x2}, + {0x90204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x20056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x1204d, 0x600}, + {0x1214d, 0x600}, + {0x1304d, 0x600}, + {0x1314d, 0x600}, + {0x10049, 0x618}, + {0x10149, 0x618}, + {0x11049, 0x618}, + {0x11149, 0x618}, + {0x12049, 0x618}, + {0x12149, 0x618}, + {0x13049, 0x618}, + {0x13149, 0x618}, + {0x43, 0x21}, + {0x1043, 0x21}, + {0x2043, 0x21}, + {0x3043, 0x21}, + {0x4043, 0x21}, + {0x5043, 0x21}, + {0x6043, 0x21}, + {0x7043, 0x21}, + {0x8043, 0x21}, + {0x9043, 0x21}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x3e8}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x200fa, 0x1}, + {0x20019, 0x1}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5555}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x1}, + {0x2002c, 0x0}, +}; + +/* PHY trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x1205f, 0x0}, + {0x1215f, 0x0}, + {0x1305f, 0x0}, + {0x1315f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x3055, 0x0}, + {0x4055, 0x0}, + {0x5055, 0x0}, + {0x6055, 0x0}, + {0x7055, 0x0}, + {0x8055, 0x0}, + {0x9055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x1204d, 0x0}, + {0x1214d, 0x0}, + {0x1304d, 0x0}, + {0x1314d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x12049, 0x0}, + {0x12149, 0x0}, + {0x13049, 0x0}, + {0x13149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x3043, 0x0}, + {0x4043, 0x0}, + {0x5043, 0x0}, + {0x6043, 0x0}, + {0x7043, 0x0}, + {0x8043, 0x0}, + {0x9043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x12043, 0x0}, + {0x12143, 0x0}, + {0x13043, 0x0}, + {0x13143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x400fd, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x12011, 0x0}, + {0x12012, 0x0}, + {0x12013, 0x0}, + {0x12018, 0x0}, + {0x12002, 0x0}, + {0x120b2, 0x0}, + {0x121b4, 0x0}, + {0x122b4, 0x0}, + {0x123b4, 0x0}, + {0x124b4, 0x0}, + {0x125b4, 0x0}, + {0x126b4, 0x0}, + {0x127b4, 0x0}, + {0x128b4, 0x0}, + {0x13011, 0x0}, + {0x13012, 0x0}, + {0x13013, 0x0}, + {0x13018, 0x0}, + {0x13002, 0x0}, + {0x130b2, 0x0}, + {0x131b4, 0x0}, + {0x132b4, 0x0}, + {0x133b4, 0x0}, + {0x134b4, 0x0}, + {0x135b4, 0x0}, + {0x136b4, 0x0}, + {0x137b4, 0x0}, + {0x138b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x12068, 0x0}, + {0x12069, 0x0}, + {0x12168, 0x0}, + {0x12169, 0x0}, + {0x12268, 0x0}, + {0x12269, 0x0}, + {0x12368, 0x0}, + {0x12369, 0x0}, + {0x12468, 0x0}, + {0x12469, 0x0}, + {0x12568, 0x0}, + {0x12569, 0x0}, + {0x12668, 0x0}, + {0x12669, 0x0}, + {0x12768, 0x0}, + {0x12769, 0x0}, + {0x12868, 0x0}, + {0x12869, 0x0}, + {0x120aa, 0x0}, + {0x12062, 0x0}, + {0x12001, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x13068, 0x0}, + {0x13069, 0x0}, + {0x13168, 0x0}, + {0x13169, 0x0}, + {0x13268, 0x0}, + {0x13269, 0x0}, + {0x13368, 0x0}, + {0x13369, 0x0}, + {0x13468, 0x0}, + {0x13469, 0x0}, + {0x13568, 0x0}, + {0x13569, 0x0}, + {0x13668, 0x0}, + {0x13669, 0x0}, + {0x13768, 0x0}, + {0x13769, 0x0}, + {0x13868, 0x0}, + {0x13869, 0x0}, + {0x130aa, 0x0}, + {0x13062, 0x0}, + {0x13001, 0x0}, + {0x130a0, 0x0}, + {0x130a1, 0x0}, + {0x130a2, 0x0}, + {0x130a3, 0x0}, + {0x130a4, 0x0}, + {0x130a5, 0x0}, + {0x130a6, 0x0}, + {0x130a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x3080, 0x0}, + {0x4080, 0x0}, + {0x5080, 0x0}, + {0x6080, 0x0}, + {0x7080, 0x0}, + {0x8080, 0x0}, + {0x9080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x12020, 0x0}, + {0x12080, 0x0}, + {0x12081, 0x0}, + {0x120d0, 0x0}, + {0x120d1, 0x0}, + {0x1208c, 0x0}, + {0x1208d, 0x0}, + {0x12180, 0x0}, + {0x12181, 0x0}, + {0x121d0, 0x0}, + {0x121d1, 0x0}, + {0x1218c, 0x0}, + {0x1218d, 0x0}, + {0x120c0, 0x0}, + {0x120c1, 0x0}, + {0x121c0, 0x0}, + {0x121c1, 0x0}, + {0x122c0, 0x0}, + {0x122c1, 0x0}, + {0x123c0, 0x0}, + {0x123c1, 0x0}, + {0x124c0, 0x0}, + {0x124c1, 0x0}, + {0x125c0, 0x0}, + {0x125c1, 0x0}, + {0x126c0, 0x0}, + {0x126c1, 0x0}, + {0x127c0, 0x0}, + {0x127c1, 0x0}, + {0x128c0, 0x0}, + {0x128c1, 0x0}, + {0x120ae, 0x0}, + {0x120af, 0x0}, + {0x13020, 0x0}, + {0x13080, 0x0}, + {0x13081, 0x0}, + {0x130d0, 0x0}, + {0x130d1, 0x0}, + {0x1308c, 0x0}, + {0x1308d, 0x0}, + {0x13180, 0x0}, + {0x13181, 0x0}, + {0x131d0, 0x0}, + {0x131d1, 0x0}, + {0x1318c, 0x0}, + {0x1318d, 0x0}, + {0x130c0, 0x0}, + {0x130c1, 0x0}, + {0x131c0, 0x0}, + {0x131c1, 0x0}, + {0x132c0, 0x0}, + {0x132c1, 0x0}, + {0x133c0, 0x0}, + {0x133c1, 0x0}, + {0x134c0, 0x0}, + {0x134c1, 0x0}, + {0x135c0, 0x0}, + {0x135c1, 0x0}, + {0x136c0, 0x0}, + {0x136c1, 0x0}, + {0x137c0, 0x0}, + {0x137c1, 0x0}, + {0x138c0, 0x0}, + {0x138c1, 0x0}, + {0x130ae, 0x0}, + {0x130af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + {0x12040, 0x0}, + {0x12140, 0x0}, + {0x12240, 0x0}, + {0x12340, 0x0}, + {0x12440, 0x0}, + {0x12540, 0x0}, + {0x12640, 0x0}, + {0x12740, 0x0}, + {0x12840, 0x0}, + {0x13040, 0x0}, + {0x13140, 0x0}, + {0x13240, 0x0}, + {0x13340, 0x0}, + {0x13440, 0x0}, + {0x13540, 0x0}, + {0x13640, 0x0}, + {0x13740, 0x0}, + {0x13840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x8}, + {0x90159, 0xe8}, + {0x9015a, 0x109}, + {0x9015b, 0x0}, + {0x9015c, 0x8140}, + {0x9015d, 0x10c}, + {0x9015e, 0x10}, + {0x9015f, 0x8138}, + {0x90160, 0x104}, + {0x90161, 0x8}, + {0x90162, 0x448}, + {0x90163, 0x109}, + {0x90164, 0xf}, + {0x90165, 0x7c0}, + {0x90166, 0x109}, + {0x90167, 0x0}, + {0x90168, 0xe8}, + {0x90169, 0x109}, + {0x9016a, 0x47}, + {0x9016b, 0x630}, + {0x9016c, 0x109}, + {0x9016d, 0x8}, + {0x9016e, 0x618}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0xe0}, + {0x90172, 0x109}, + {0x90173, 0x0}, + {0x90174, 0x7c8}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x8140}, + {0x90178, 0x10c}, + {0x90179, 0x0}, + {0x9017a, 0x478}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x1}, + {0x9017e, 0x8}, + {0x9017f, 0x8}, + {0x90180, 0x4}, + {0x90181, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x68}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x7d}, + {0x2000c, 0xfa}, + {0x2000d, 0x9c4}, + {0x2000e, 0x2c}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, }, +}; diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c new file mode 100644 index 00000000000..d704d588579 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) +#include "../common/imx8m_som_detection.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define EEPROM_ADDR 0x51 + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + int ret; + + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + if (!ret) { + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + } +#endif + + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_pca9450_init(0, 0x25); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +void spl_board_init(void) +{ + arch_misc_init(); + + /* Set GIC clock to 500Mhz for OD VDD_SOC. */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig new file mode 100644 index 00000000000..a23e604425d --- /dev/null +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3C0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc" +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 +CONFIG_TARGET_IMX8MP_LIBRA_FPSC=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SYS_LOAD_ADDR=0x47602000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3e0000 +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-libra-rdk-fpsc.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_REG=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x13000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_POWER_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_IMX_WATCHDOG=y diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst new file mode 100644 index 00000000000..26752ac1882 --- /dev/null +++ b/doc/board/phytec/imx8mp-libra-fpsc.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Libra i.MX 8M Plus FPSC +======================= + +The Libra i.MX 8M Plus FPSC is a SBC based with the phyCORE-i.MX 8M Plus FPSC +SoM. +The phyCORE-i.MX 8M Plus FPSC with 2GB of main memory is supported. + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Build the OP-TEE binary +- Get ddr firmware +- Build U-Boot +- Boot + +Build the ARM Trusted firmware binary +------------------------------------- + +.. code-block:: bash + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mp \ + IMX_BOOT_UART_BASE=0x30a60000 \ + BL32_BASE=0x7e000000 \ + SPD=opteed \ + bl31 + +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + CFG_TEE_BENCHMARK=n \ + O=out/arm \ + PLATFORM=imx-mx8mp_libra_fpsc + +Get the ddr firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin + +Build U-Boot for SD card +------------------------ + +Copy binaries +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ cp /build/imx8mp/release/bl31.bin . + $ cp /out/arm/core/tee-raw.bin tee.bin + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + imx8mp-libra-fpsc_defconfig \ + flash.bin + +Flash SD card +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=fsync diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 1ae30c2dcd5..e24040a496e 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -6,6 +6,7 @@ PHYTEC .. toctree:: :maxdepth: 2 + imx8mp-libra-fpsc imx8mm-phygate-tauri-l imx93-phycore phycore-am62x diff --git a/include/configs/imx8mp-libra-fpsc.h b/include/configs/imx8mp-libra-fpsc.h new file mode 100644 index 00000000000..cde91dc3642 --- /dev/null +++ b/include/configs/imx8mp-libra-fpsc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#ifndef __IMX8MP_LIBRA_FPSC_H +#define __IMX8MP_LIBRA_FPSC_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K + +#define CFG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ + +#endif /* __IMX8MP_LIBRA_FPSC_H */ -- cgit v1.3.1 From 30fbbde2cdfaebb1db47d7c0d457a32e3c6552c3 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Wed, 10 Sep 2025 10:16:17 +0800 Subject: arm: nuvoton: remove unused parameter remove CFG_SYS_BOOTM_LEN parameter Signed-off-by: Jim Liu --- include/configs/arbel.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/arbel.h b/include/configs/arbel.h index b5f684e88fe..63112baf9b2 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -8,7 +8,6 @@ #define CFG_SYS_SDRAM_BASE 0x0 #define CFG_SYS_BOOTMAPSZ (192 << 20) -#define CFG_SYS_BOOTM_LEN (20 << 20) #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CFG_SYS_INIT_RAM_SIZE 0x8000 -- cgit v1.3.1 From 409c73ef6368b07d4dbdf8391a0b9c7682dcf4b4 Mon Sep 17 00:00:00 2001 From: Randolph Lin Date: Thu, 21 Aug 2025 19:31:22 +0800 Subject: include: configs: andes: Remove fdt_high env variable Remove the fdt_high environment variable, as a value of all ones indicates using the FDT in place. This setting is incorrect for the current board. Signed-off-by: Randolph Lin Reviewed-by: Leo Yu-Chi Liang --- include/configs/voyager.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/voyager.h b/include/configs/voyager.h index f6630b07ec9..0e5fed99dd0 100644 --- a/include/configs/voyager.h +++ b/include/configs/voyager.h @@ -26,7 +26,6 @@ #include #define CFG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x400600000\0" \ "kernel_comp_addr_r=0x404600000\0" \ -- cgit v1.3.1 From d141a41feb005a9f6a830006f1a4b66d1a3a3cd2 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:10:58 +0100 Subject: board: microchip: icicle: rename all icicle files to generic Make all Icicle Kit files generic. This supports the addition of upcoming support for other MPFS boards. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 6 +- board/microchip/mpfs_generic/Kconfig | 67 +++++++++ board/microchip/mpfs_generic/MAINTAINERS | 7 + board/microchip/mpfs_generic/Makefile | 7 + board/microchip/mpfs_generic/mpfs_generic.c | 204 ++++++++++++++++++++++++++++ board/microchip/mpfs_icicle/Kconfig | 67 --------- board/microchip/mpfs_icicle/MAINTAINERS | 7 - board/microchip/mpfs_icicle/Makefile | 7 - board/microchip/mpfs_icicle/mpfs_icicle.c | 204 ---------------------------- configs/microchip_mpfs_generic_defconfig | 29 ++++ configs/microchip_mpfs_icicle_defconfig | 29 ---- include/configs/microchip_mpfs_generic.h | 32 +++++ include/configs/microchip_mpfs_icicle.h | 32 ----- 13 files changed, 349 insertions(+), 349 deletions(-) create mode 100644 board/microchip/mpfs_generic/Kconfig create mode 100644 board/microchip/mpfs_generic/MAINTAINERS create mode 100644 board/microchip/mpfs_generic/Makefile create mode 100644 board/microchip/mpfs_generic/mpfs_generic.c delete mode 100644 board/microchip/mpfs_icicle/Kconfig delete mode 100644 board/microchip/mpfs_icicle/MAINTAINERS delete mode 100644 board/microchip/mpfs_icicle/Makefile delete mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c create mode 100644 configs/microchip_mpfs_generic_defconfig delete mode 100644 configs/microchip_mpfs_icicle_defconfig create mode 100644 include/configs/microchip_mpfs_generic.h delete mode 100644 include/configs/microchip_mpfs_icicle.h (limited to 'include/configs') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f0d2c904349..265b5320777 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,8 +23,8 @@ config TARGET_K230_CANMV config TARGET_LICHEERV_NANO bool "Support LicheeRV Nano Board" -config TARGET_MICROCHIP_ICICLE - bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_MICROCHIP_GENERIC + bool "Support Microchip PolarFire-SoC Boards" config TARGET_MILKV_DUO bool "Support Milk-v Duo Board" @@ -108,7 +108,7 @@ source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -source "board/microchip/mpfs_icicle/Kconfig" +source "board/microchip/mpfs_generic/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig new file mode 100644 index 00000000000..8dcf55a0311 --- /dev/null +++ b/board/microchip/mpfs_generic/Kconfig @@ -0,0 +1,67 @@ +if TARGET_MICROCHIP_GENERIC + +config SYS_BOARD + default "mpfs_generic" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_generic" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CLK_CCF + imply CLK_MPFS + imply REGMAP + imply SYSCON + imply SYS_NS16550 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply PHY_LIB + imply PHY_VITESSE + imply MMC + imply MMC_WRITE + imply MMC_SDHCI + imply MMC_SDHCI_CADENCE + imply MMC_SDHCI_ADMA + imply MMC_HS200_SUPPORT + imply CMD_I2C + imply DM_I2C + imply SYS_I2C_MICROCHIP + imply MTD + imply SPI + imply DM_SPI + imply MICROCHIP_COREQSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER + +endif diff --git a/board/microchip/mpfs_generic/MAINTAINERS b/board/microchip/mpfs_generic/MAINTAINERS new file mode 100644 index 00000000000..3de99144c41 --- /dev/null +++ b/board/microchip/mpfs_generic/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS Generic +M: Conor Dooley +M: Jamie Gibbons +S: Maintained +F: board/microchip/mpfs_generic/ +F: include/configs/microchip_mpfs_generic.h +F: configs/microchip_mpfs_generic_defconfig diff --git a/board/microchip/mpfs_generic/Makefile b/board/microchip/mpfs_generic/Makefile new file mode 100644 index 00000000000..dfe4b2634e6 --- /dev/null +++ b/board/microchip/mpfs_generic/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari +# + +obj-y += mpfs_generic.o diff --git a/board/microchip/mpfs_generic/mpfs_generic.c b/board/microchip/mpfs_generic/mpfs_generic.c new file mode 100644 index 00000000000..739a9b6cd76 --- /dev/null +++ b/board/microchip/mpfs_generic/mpfs_generic.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x1e8u + +static unsigned char mac_addr[6]; + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char copy[64]; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + /* + * The naming scheme for compatibles doesn't produce anything + * close to this long. + */ + if (len >= 64) + return -EINVAL; + + strncpy(copy, compat, 64); + strtok(copy, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + mac_addr[5] = device_serial_number[0] + 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + return 0; +} diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig deleted file mode 100644 index 760dffc488b..00000000000 --- a/board/microchip/mpfs_icicle/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -if TARGET_MICROCHIP_ICICLE - -config SYS_BOARD - default "mpfs_icicle" - -config SYS_VENDOR - default "microchip" - -config SYS_CPU - default "generic" - -config SYS_CONFIG_NAME - default "microchip_mpfs_icicle" - -config TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select GENERIC_RISCV - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - imply SMP - imply CLK_CCF - imply CLK_MPFS - imply REGMAP - imply SYSCON - imply SYS_NS16550 - imply CMD_DHCP - imply CMD_EXT2 - imply CMD_EXT4 - imply CMD_FAT - imply CMD_FS_GENERIC - imply CMD_NET - imply CMD_PING - imply CMD_MMC - imply DOS_PARTITION - imply EFI_PARTITION - imply IP_DYN - imply ISO_PARTITION - imply MACB - imply MII - imply PHY_LIB - imply PHY_VITESSE - imply MMC - imply MMC_WRITE - imply MMC_SDHCI - imply MMC_SDHCI_CADENCE - imply MMC_SDHCI_ADMA - imply MMC_HS200_SUPPORT - imply CMD_I2C - imply DM_I2C - imply SYS_I2C_MICROCHIP - imply MTD - imply SPI - imply DM_SPI - imply MICROCHIP_COREQSPI - imply MTD_SPI_NAND - imply CMD_MTD - imply CMD_MTDPARTS - imply DM_MAILBOX - imply MPFS_MBOX - imply MISC - imply MPFS_SYSCONTROLLER - -endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS deleted file mode 100644 index d092b5a8111..00000000000 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -Microchip MPFS icicle -M: Conor Dooley -M: Cyril Jean -S: Maintained -F: board/microchip/mpfs_icicle/ -F: include/configs/microchip_mpfs_icicle.h -F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile deleted file mode 100644 index 72b0410dda8..00000000000 --- a/board/microchip/mpfs_icicle/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 Microchip Technology Inc. -# Padmarao Begari -# - -obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c deleted file mode 100644 index 739a9b6cd76..00000000000 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define PERIPH_RESET_VALUE 0x1e8u - -static unsigned char mac_addr[6]; - -#if defined(CONFIG_MULTI_DTB_FIT) -int board_fit_config_name_match(const char *name) -{ - const void *fdt; - int list_len; - - /* - * If there's not a HSS provided dtb, there's no point re-selecting - * since we'd just end up re-selecting the same dtb again. - */ - if (!gd->arch.firmware_fdt_addr) - return -EINVAL; - - fdt = (void *)gd->arch.firmware_fdt_addr; - - list_len = fdt_stringlist_count(fdt, 0, "compatible"); - if (list_len < 1) - return -EINVAL; - - for (int i = 0; i < list_len; i++) { - int len, match; - const char *compat; - char copy[64]; - char *devendored; - - compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); - if (!compat) - return -EINVAL; - - /* - * The naming scheme for compatibles doesn't produce anything - * close to this long. - */ - if (len >= 64) - return -EINVAL; - - strncpy(copy, compat, 64); - strtok(copy, ","); - - devendored = strtok(NULL, ","); - if (!devendored) - return -EINVAL; - - match = strcmp(devendored, name); - if (!match) - return 0; - } - - return -EINVAL; -} -#endif - -int board_fdt_blob_setup(void **fdtp) -{ - fdtp = (void *)_end; - - /* - * The devicetree provided by the previous stage is very minimal due to - * severe space constraints. The firmware performs no fixups etc. - * U-Boot, if providing a devicetree, almost certainly has a better - * more complete one than the firmware so that provided by the firmware - * is ignored for OF_SEPARATE. - */ - if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { - if (gd->arch.firmware_fdt_addr) - fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; - } - - return 0; -} - -int board_init(void) -{ - /* For now nothing to do here. */ - - return 0; -} - -int board_early_init_f(void) -{ - unsigned int val; - - /* Reset uart, mmc peripheral */ - val = readl(MPFS_SYSREG_SOFT_RESET); - val = (val & ~(PERIPH_RESET_VALUE)); - writel(val, MPFS_SYSREG_SOFT_RESET); - - return 0; -} - -int board_late_init(void) -{ - u32 ret; - int node; - u8 device_serial_number[16] = {0}; - void *blob = (void *)gd->fdt_blob; - struct udevice *dev; - struct mpfs_sys_serv *sys_serv_priv; - - ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); - if (ret) { - debug("%s: system controller setup failed\n", __func__); - return ret; - } - - sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); - if (!sys_serv_priv) - return -ENOMEM; - - sys_serv_priv->dev = dev; - - sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); - ret = IS_ERR(sys_serv_priv->sys_controller); - if (ret) { - debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); - return -ENODEV; - } - - ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); - if (ret) { - printf("Cannot read device serial number\n"); - return -EINVAL; - } - - /* Update MAC address with device serial number */ - mac_addr[0] = 0x00; - mac_addr[1] = 0x04; - mac_addr[2] = 0xA3; - mac_addr[3] = device_serial_number[2]; - mac_addr[4] = device_serial_number[1]; - mac_addr[5] = device_serial_number[0]; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - mac_addr[5] = device_serial_number[0] + 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u32 ret; - int node; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - mac_addr[5] -= 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - return 0; -} diff --git a/configs/microchip_mpfs_generic_defconfig b/configs/microchip_mpfs_generic_defconfig new file mode 100644 index 00000000000..0ed0cae93eb --- /dev/null +++ b/configs/microchip_mpfs_generic_defconfig @@ -0,0 +1,29 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_MEM_TOP_HIDE=0x400000 +# CONFIG_DEBUG_UART is not set +CONFIG_TARGET_MICROCHIP_GENERIC=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_OF_UPSTREAM=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_DM_MTD=y +CONFIG_SYSRESET=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig deleted file mode 100644 index 9f933592c9d..00000000000 --- a/configs/microchip_mpfs_icicle_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_LOAD_ADDR=0x80200000 -CONFIG_SYS_MEM_TOP_HIDE=0x400000 -# CONFIG_DEBUG_UART is not set -CONFIG_TARGET_MICROCHIP_ICICLE=y -CONFIG_ARCH_RV64I=y -CONFIG_RISCV_SMODE=y -CONFIG_FIT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=282 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y -CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_DM_MTD=y -CONFIG_SYSRESET=y diff --git a/include/configs/microchip_mpfs_generic.h b/include/configs/microchip_mpfs_generic.h new file mode 100644 index 00000000000..0077f6a5f95 --- /dev/null +++ b/include/configs/microchip_mpfs_generic.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h deleted file mode 100644 index 0077f6a5f95..00000000000 --- a/include/configs/microchip_mpfs_icicle.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 62f1afbe7a8ae8f8b9e85c5ea4eb446b97892a7c Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 15 Sep 2025 07:45:49 +0800 Subject: riscv: qemu: Remove fdt_high default Setting fdt_high to all ones is discouraged and does not appear to be useful for RISC-V QEMU. Moreover, it causes a boot failure when the FDT generated internally by QEMU is used while booting. Remove it to allow U-Boot to pick a suitable address and relocate the FDT. Closes: https://lore.kernel.org/u-boot/8397369a-9b0b-4798-9c30-3a81165657d6@iscas.ac.cn Signed-off-by: Vivian Wang Reviewed-by: Tom Rini Reviewed-by: Lukas Auer Reviewed-by: Leo Yu-Chi Liang --- include/configs/qemu-riscv.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index cf4fcb90b04..dad59cc0d58 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -32,7 +32,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ CFG_STD_DEVICES_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ "kernel_comp_addr_r=0x88000000\0" \ -- cgit v1.3.1 From e246e2b65885e6d5fd052ec2acdf2b07a53171f0 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 10 Sep 2025 18:23:26 +0900 Subject: configs: qemu-sbsa: Define GIC register base address If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at arch/arm/cpu/armv8/start.S. Signed-off-by: Kunihiko Hayashi --- include/configs/qemu-sbsa.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/configs') diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h index aff78160e12..669d0fe7c58 100644 --- a/include/configs/qemu-sbsa.h +++ b/include/configs/qemu-sbsa.h @@ -86,4 +86,8 @@ #define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE 0x1000000 +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR +#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 3d4e14f4c903819b15ec7e83a29d175692557b3f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:04 +0800 Subject: imx94_evk: Add i.MX943 EVK board support Add board-level code and defconfig for the i.MX943 EVK board, supporting multiple SOM variants: 19x19 LPDDR5, 19x19 LPDDR4 and 15x15 LPDDR4. Signed-off-by: Ye Li Signed-off-by: Alice Guo Acked-by: Peng Fan Reviewed-by: Jacky Bai --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/imx9/Kconfig | 8 +++ board/freescale/imx94_evk/Kconfig | 12 ++++ board/freescale/imx94_evk/MAINTAINERS | 6 ++ board/freescale/imx94_evk/Makefile | 11 +++ board/freescale/imx94_evk/imx94_evk.c | 41 ++++++++++++ board/freescale/imx94_evk/imx94_evk.env | 100 +++++++++++++++++++++++++++ board/freescale/imx94_evk/spl.c | 81 ++++++++++++++++++++++ configs/imx943_evk_defconfig | 115 ++++++++++++++++++++++++++++++++ doc/board/nxp/imx943_evk.rst | 112 +++++++++++++++++++++++++++++++ doc/board/nxp/index.rst | 1 + include/configs/imx94_evk.h | 24 +++++++ 12 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 board/freescale/imx94_evk/Kconfig create mode 100644 board/freescale/imx94_evk/MAINTAINERS create mode 100644 board/freescale/imx94_evk/Makefile create mode 100644 board/freescale/imx94_evk/imx94_evk.c create mode 100644 board/freescale/imx94_evk/imx94_evk.env create mode 100644 board/freescale/imx94_evk/spl.c create mode 100644 configs/imx943_evk_defconfig create mode 100644 doc/board/nxp/imx943_evk.rst create mode 100644 include/configs/imx94_evk.h (limited to 'include/configs') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index fa2cdaba144..1efe690e876 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,7 +223,7 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -ifneq ($(and $(CONFIG_IMX95),$(CONFIG_BINMAN)),) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) SPL: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) else diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index f2011448c23..48f458fa55c 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -106,6 +106,13 @@ config TARGET_IMX95_19X19_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_IMX943_EVK + bool "imx943_evk" + select IMX94 + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + endchoice source "board/freescale/imx91_evk/Kconfig" @@ -114,6 +121,7 @@ source "board/freescale/imx93_frdm/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" +source "board/freescale/imx94_evk/Kconfig" source "board/freescale/imx95_evk/Kconfig" endif diff --git a/board/freescale/imx94_evk/Kconfig b/board/freescale/imx94_evk/Kconfig new file mode 100644 index 00000000000..a4237244ace --- /dev/null +++ b/board/freescale/imx94_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX943_EVK + +config SYS_BOARD + default "imx94_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx94_evk" + +endif diff --git a/board/freescale/imx94_evk/MAINTAINERS b/board/freescale/imx94_evk/MAINTAINERS new file mode 100644 index 00000000000..95309430734 --- /dev/null +++ b/board/freescale/imx94_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX94 EVK BOARD +M: Alice Guo +S: Maintained +F: board/freescale/imx94_evk/ +F: include/configs/imx94_evk.h +F: configs/imx943_evk_defconfig diff --git a/board/freescale/imx94_evk/Makefile b/board/freescale/imx94_evk/Makefile new file mode 100644 index 00000000000..ca31602f6ba --- /dev/null +++ b/board/freescale/imx94_evk/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx94_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/freescale/imx94_evk/imx94_evk.c b/board/freescale/imx94_evk/imx94_evk.c new file mode 100644 index 00000000000..28d512ac5f3 --- /dev/null +++ b/board/freescale/imx94_evk/imx94_evk.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include + +int board_early_init_f(void) +{ + init_uart_clk(0); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); + + if (IS_ENABLED(CONFIG_AHAB_BOOT)) + env_set("sec_boot", "yes"); + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} diff --git a/board/freescale/imx94_evk/imx94_evk.env b/board/freescale/imx94_evk/imx94_evk.env new file mode 100644 index 00000000000..2baf1bbadcb --- /dev/null +++ b/board/freescale/imx94_evk/imx94_evk.env @@ -0,0 +1,100 @@ +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx943-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/freescale/imx94_evk/spl.c b/board/freescale/imx94_evk/spl.c new file mode 100644 index 00000000000..341b165b3c8 --- /dev/null +++ b/board/freescale/imx94_evk/spl.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +/* SCMI support by default */ +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION) && + IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); + + timer_init(); + + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + board_early_init_f(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig new file mode 100644 index 00000000000..27230ed3207 --- /dev/null +++ b/configs/imx943_evk_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="imx94_evk" +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx943-evk" +CONFIG_TARGET_IMX943_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx943-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_RGPIO2P=y +CONFIG_IMX_MU_MBOX=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y diff --git a/doc/board/nxp/imx943_evk.rst b/doc/board/nxp/imx943_evk.rst new file mode 100644 index 00000000000..651db08a0f7 --- /dev/null +++ b/doc/board/nxp/imx943_evk.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx943_evk +======================= + +U-Boot for the NXP i.MX943 19x19 EVK board + +Quick Start +----------- + +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Get ahab-container.img +-------------------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx943a0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +-------------------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +-------------------------------------- + +Note: srctree is U-Boot source directory +Get OEI from: https://github.com/nxp-imx/imx-oei +branch: master + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone -b master https://github.com/nxp-imx/imx-oei.git + $ cd imx-oei + $ make board=mx943lp5-19 oei=ddr DEBUG=1 all + $ cp build/mx943lp5-19/ddr/oei-m33-ddr.bin $(srctree) + +Get and Build System Manager Image +-------------------------------------- + +Note: srctree is U-Boot source directory +Get System Manager from: https://github.com/nxp-imx/imx-sm +branch: master + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone -b master https://github.com/nxp-imx/imx-sm.git + $ cd imx-sm + $ make config=mx94evk all + $ cp build/mx94evk/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx94 bl31 + $ cp build/imx94/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx943_evk_defconfig + $ make + +Copy flash.bin to the MicroSD card: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set i.MX943 boot device to MicroSD card diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index aa7d857346d..670501164b5 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -16,6 +16,7 @@ NXP Semiconductors imx93_9x9_qsb imx93_11x11_evk imx93_frdm + imx943_evk imx95_evk imxrt1020-evk imxrt1050-evk diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h new file mode 100644 index 00000000000..f93c3c4e4a8 --- /dev/null +++ b/include/configs/imx94_evk.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX94_EVK_H +#define __IMX94_EVK_H + +#include +#include +#include + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */ + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif -- cgit v1.3.1