From 37a0c6008553f3bbd0db6bb8a88e3f5b0c7606eb Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 15 May 2017 17:51:18 +0800 Subject: rockchip: rk3368: Add core start-up code for RK3368 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber Signed-off-by: Andy Yan Reviewed-by: Simon Glass --- include/configs/rk3368_common.h | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/configs/rk3368_common.h (limited to 'include/configs') diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h new file mode 100644 index 00000000000..8ebf2324c56 --- /dev/null +++ b/include/configs/rk3368_common.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3368_COMMON_H +#define __CONFIG_RK3368_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include +#include + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00280000 + +#define CONFIG_BOUNCE_BUFFER + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x5600000\0" \ + "kernel_addr_r=0x280000\0" \ + "ramdisk_addr_r=0x5bf0000\0" + +#include + +#define BOOT_TARGET_DEVICES(func) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV + +#endif + +#endif -- cgit v1.3.1