From 046c76a6c0af77952a1ec5ab576d12f93ed52641 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren@nvidia.com>
Date: Tue, 15 May 2012 14:38:03 -0700
Subject: spi: Tegra2: Seaboard: enable SPI/UART corruption fix

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/seaboard.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 46d42281b78..889bdfff383 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -52,6 +52,15 @@
 
 /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
 #define CONFIG_UART_DISABLE_GPIO	GPIO_PI3
+/*
+ * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are
+ * needed to work around that design error.
+ */
+#define CONFIG_SPI_UART_SWITCH
+#define CONFIG_SPI_CORRUPTS_UART	NV_PA_APB_UARTD_BASE
+#define CONFIG_SPI_CORRUPTS_UART_NR	3
+#define CONFIG_SPI_CORRUPTS_UART_DLY	2500
+#undef CONFIG_CMDLINE_EDITING		/* avoid NUL in input buffer */
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
 #define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
-- 
cgit v1.3.1


From d5ebc937c90b95f52bd85c15ce74edff4df2e0be Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 15 May 2012 06:45:28 +0000
Subject: tegra: Whistler board support

Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:

E1120 motherboard
E1108 CPU board
E1116 PMU board

The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.

Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 MAINTAINERS                          |   1 +
 board/nvidia/dts/tegra2-whistler.dts |  67 ++++++++++++++++++++
 board/nvidia/whistler/Makefile       |  48 +++++++++++++++
 board/nvidia/whistler/whistler.c     | 116 +++++++++++++++++++++++++++++++++++
 boards.cfg                           |   1 +
 include/configs/whistler.h           |  90 +++++++++++++++++++++++++++
 6 files changed, 323 insertions(+)
 create mode 100644 board/nvidia/dts/tegra2-whistler.dts
 create mode 100644 board/nvidia/whistler/Makefile
 create mode 100644 board/nvidia/whistler/whistler.c
 create mode 100644 include/configs/whistler.h

(limited to 'include/configs')

diff --git a/MAINTAINERS b/MAINTAINERS
index e55893b52ce..0db7e84d9a0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -914,6 +914,7 @@ Stephen Warren <swarren@nvidia.com>
 
 	ventana		Tegra2 (ARM7 & A9 Dual Core)
 	paz00		Tegra2 (ARM7 & A9 Dual Core)
+	whistler	Tegra2 (ARM7 & A9 Dual Core)
 
 Thomas Weber <weber@corscience.de>
 
diff --git a/board/nvidia/dts/tegra2-whistler.dts b/board/nvidia/dts/tegra2-whistler.dts
new file mode 100644
index 00000000000..b22d4073f6f
--- /dev/null
+++ b/board/nvidia/dts/tegra2-whistler.dts
@@ -0,0 +1,67 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Tegra2 Whistler evaluation board";
+	compatible = "nvidia,whistler", "nvidia,tegra20";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = < 0x00000000 0x20000000 >;
+	};
+
+	clocks {
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&clk_32k &osc>;
+	};
+
+	serial@70006000 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		clock-frequency = <100000>;
+
+		pmic@3c {
+			compatible = "maxim,max8907b";
+			reg = <0x3c>;
+
+			clk_32k: clock {
+				compatible = "fixed-clock";
+				/*
+				 * leave out for now due to CPP:
+				 * #clock-cells = <0>;
+				 */
+				clock-frequency = <32768>;
+			};
+		};
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+};
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile
new file mode 100644
index 00000000000..a910577f21a
--- /dev/null
+++ b/board/nvidia/whistler/Makefile
@@ -0,0 +1,48 @@
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
new file mode 100644
index 00000000000..1c2f33face5
--- /dev/null
+++ b/board/nvidia/whistler/whistler.c
@@ -0,0 +1,116 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Whistler - no UART-related GPIOs.
+ */
+void gpio_config_uart(void)
+{
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	uchar val;
+	int ret;
+
+	debug("board_mmc_init called\n");
+
+	/* Turn on MAX8907B LDO12 to 2.8V for J40 power */
+	ret = i2c_set_bus_num(0);
+	if (ret)
+		printf("i2c_set_bus_num failed: %d\n", ret);
+	val = 0x29;
+	ret = i2c_write(0x3c, 0x46, 1, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
+	val = 0x00;
+	ret = i2c_write(0x3c, 0x45, 1, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
+	val = 0x1f;
+	ret = i2c_write(0x3c, 0x44, 1, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
+
+	/* Enable muxes, etc. for SDMMC controllers */
+	pin_mux_mmc();
+
+	/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
+	tegra2_mmc_init(0, 8, -1, -1);
+
+	/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
+	tegra2_mmc_init(1, 8, -1, -1);
+
+	return 0;
+}
+
+/* this is a weak define that we are overriding */
+void pin_mux_usb(void)
+{
+	uchar val;
+	int ret;
+
+	/*
+	 * This is a hack. This should be represented in DT using the
+	 * vbus-gpio property. However, U-Boot's DT support doesn't
+	 * support any GPIO controller other than the Tegra's yet.
+	 */
+
+	/* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
+	ret = i2c_set_bus_num(0);
+	if (ret)
+		printf("i2c_set_bus_num failed: %d\n", ret);
+	val = 0x03;
+	ret = i2c_write(0x20, 2, 1, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x20 2 failed: %d\n", ret);
+	val = 0xfc;
+	ret = i2c_write(0x20, 6, 1, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x20 6 failed: %d\n", ret);
+}
diff --git a/boards.cfg b/boards.cfg
index a723f67eb14..055dbbc7b19 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -231,6 +231,7 @@ trats                        arm         armv7       trats               samsung
 harmony                      arm         armv7       harmony             nvidia         tegra2
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
 ventana                      arm         armv7       ventana             nvidia         tegra2
+whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
new file mode 100644
index 00000000000..6b9ef988379
--- /dev/null
+++ b/include/configs/whistler.h
@@ -0,0 +1,90 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-whistler
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM		"mem=512M@0M"
+#define V_PROMPT		"Tegra2 (Whistler) # "
+#define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Whistler"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTA
+#define CONFIG_TEGRA2_UARTA_UAA_UAB
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_WHISTLER
+#define CONFIG_SYS_BOARD_ODMDATA	0x2B080105 /* lp?, 512MB, UARTA */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		4
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA2_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/* Environment not stored */
+#define CONFIG_ENV_IS_NOWHERE
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+
+#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
+#define CONFIG_CMD_NFS      /* NFS support          */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 07a84b7b1905f5b7464ad5746507306733eae964 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 16 May 2012 06:20:59 +0000
Subject: tegra: remove some cruft from CONFIG_EXTRA_ENV_SETTINGS

console isn't used by anything, and the kernel should be set appropriately
by whatever script is booting the kernel, not imposed by the bootloader.

mem might be useful, but the current value is pretty bogus, since it
includes nvmem options that make no sense for an upstream kernel, and
equally should not be required for any downstream kernel. Either way, this
is also best left to the kernel boot script.

smpflag isn't used by anything, and again was probably intended to be a
kernel command-line option better set by the kernel boot script.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/harmony.h       | 1 -
 include/configs/medcom.h        | 1 -
 include/configs/paz00.h         | 1 -
 include/configs/plutux.h        | 1 -
 include/configs/seaboard.h      | 1 -
 include/configs/tegra2-common.h | 3 ---
 include/configs/ventana.h       | 1 -
 include/configs/whistler.h      | 1 -
 8 files changed, 10 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index ce0ae9fe1f8..3706a4089ac 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -28,7 +28,6 @@
 #include "tegra2-common.h"
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM		"mem=384M@0M nvmem=128M@384M mem=512M@512M"
 #define V_PROMPT		"Tegra2 (Harmony) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Harmony"
 
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index 2dc350762d5..725abc3ddc4 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -29,7 +29,6 @@
 #include "tegra2-common.h"
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM			"mem=384M@0M nvmem=128M@384M"
 #define V_PROMPT			"Tegra2 (Medcom) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"Avionic Design Medcom"
 #define CONFIG_SYS_BOARD_ODMDATA	0x2b0d8011
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index f53f20eb977..ae3a2de02f7 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -21,7 +21,6 @@
 #include "tegra2-common.h"
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM		"mem=512M@0M"
 #define V_PROMPT		"Tegra2 (Paz00) MOD # "
 #define CONFIG_TEGRA2_BOARD_STRING	"Compal Paz00"
 
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index f869191f34a..475be6c4bab 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -29,7 +29,6 @@
 #include "tegra2-common.h"
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM			"mem=384M@0M nvmem=128M@384M"
 #define V_PROMPT			"Tegra2 (Plutux) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"Avionic Design Plutux"
 #define CONFIG_SYS_BOARD_ODMDATA	0x2b2d8011
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 889bdfff383..c346366ae06 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -41,7 +41,6 @@
 #define CONFIG_OF_SEPARATE
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM		"mem=384M@0M nvmem=128M@384M mem=512M@512M"
 #define V_PROMPT		"Tegra2 (SeaBoard) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Seaboard"
 
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 52dc38e60e2..d60b5a1978a 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -140,9 +140,6 @@
 					"stderr=serial\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"console=ttyS0,115200n8\0" \
-	"mem=" TEGRA2_SYSMEM "\0" \
-	"smpflag=smp\0" \
 	TEGRA2_DEVICE_SETTINGS
 
 #define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 3e55fe5d1ad..a7338f10768 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -33,7 +33,6 @@
 #define CONFIG_OF_SEPARATE
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM		"mem=384M@0M nvmem=128M@384M mem=512M@512M"
 #define V_PROMPT		"Tegra2 (Ventana) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Ventana"
 
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 6b9ef988379..5efa60cdf6a 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -33,7 +33,6 @@
 #define CONFIG_OF_SEPARATE
 
 /* High-level configuration options */
-#define TEGRA2_SYSMEM		"mem=512M@0M"
 #define V_PROMPT		"Tegra2 (Whistler) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Whistler"
 
-- 
cgit v1.3.1


From bea2674ccde5a495710adef62ebd5a294752f59d Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 16 May 2012 06:21:00 +0000
Subject: tegra: flesh out bootcmd

This implements a useful bootcmd for Tegra. The boot order is:

* If USB enabled, USB storage
* Internal MMC (SD card or eMMC)
* If networking is enabled, BOOTP/TFTP

When booting from USB or MMC, the boot script is assumed to be in
partition 1 (although this may be overridden via the rootpart variable),
both ext2 and FAT filesystems are supported, the boot script may exist
in either / or /boot, and the boot script may be named boot.scr.uimg or
boot.scr.

When booting over the network, it is assumed that boot.scr.uimg exists
on the TFTP server. There is less flexibility here since those setting
up network booting are expected to need less hand-holding.

In all cases, it is expected that the initial file loaded is a U-Boot
image containing a script that will load the kernel, load any required
initrd, load any required DTB, and finally bootm the kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/harmony.h            |   3 +
 include/configs/medcom.h             |   2 +
 include/configs/paz00.h              |   3 +
 include/configs/plutux.h             |   2 +
 include/configs/seaboard.h           |   3 +
 include/configs/tegra2-common-post.h | 117 +++++++++++++++++++++++++++++++++++
 include/configs/tegra2-common.h      |   3 -
 include/configs/ventana.h            |   3 +
 include/configs/whistler.h           |   2 +
 9 files changed, 135 insertions(+), 3 deletions(-)
 create mode 100644 include/configs/tegra2-common-post.h

(limited to 'include/configs')

diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 3706a4089ac..25d6ec7f909 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -60,4 +60,7 @@
 
 /* Environment not stored */
 #define CONFIG_ENV_IS_NOWHERE
+
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index 725abc3ddc4..eecfa50e3eb 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -60,4 +60,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index ae3a2de02f7..ced185e106f 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -47,4 +47,7 @@
 
 /* Environment not stored */
 #define CONFIG_ENV_IS_NOWHERE
+
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 475be6c4bab..18882762368 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -60,4 +60,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index c346366ae06..d02a11e03cb 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -116,4 +116,7 @@
 #define TEGRA2_DEVICE_SETTINGS	"stdin=serial,tegra-kbc\0" \
 					"stdout=serial\0" \
 					"stderr=serial\0"
+
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra2-common-post.h b/include/configs/tegra2-common-post.h
new file mode 100644
index 00000000000..0484a522d5c
--- /dev/null
+++ b/include/configs/tegra2-common-post.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA2_COMMON_POST_H
+#define __TEGRA2_COMMON_POST_H
+
+#ifdef CONFIG_BOOTCOMMAND
+
+#define BOOTCMDS_COMMON ""
+
+#else
+
+#ifdef CONFIG_CMD_EXT2
+#define BOOTCMD_FS_EXT2 "ext2 "
+#else
+#define BOOTCMD_FS_EXT2 ""
+#endif
+
+#ifdef CONFIG_CMD_FAT
+#define BOOTCMD_FS_FAT "fat"
+#else
+#define BOOTCMD_FS_FAT ""
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTCMDS_MMC \
+	"mmc_boot=" \
+		"setenv devtype mmc; " \
+		"if mmc dev ${devnum}; then " \
+			"run script_boot; " \
+		"fi\0" \
+	"mmc0_boot=setenv devnum 0; run mmc_boot;\0" \
+	"mmc1_boot=setenv devnum 1; run mmc_boot;\0" \
+	"bootcmd_mmc=run mmc1_boot; run mmc0_boot\0"
+#define BOOTCMD_MMC "run bootcmd_mmc; "
+#else
+#define BOOTCMDS_MMC ""
+#define BOOTCMD_MMC ""
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOTCMDS_USB \
+	"usb_boot=" \
+		"setenv devtype usb; " \
+		"if usb dev ${devnum}; then " \
+			"run script_boot; " \
+		"fi\0" \
+	"usb0_boot=setenv devnum 0; run usb_boot;\0" \
+	"bootcmd_usb=run usb0_boot\0"
+#define BOOTCMD_USB "run bootcmd_usb; "
+#define BOOTCMD_INIT_USB "usb start 0; "
+#else
+#define BOOTCMDS_USB ""
+#define BOOTCMD_USB ""
+#define BOOTCMD_INIT_USB ""
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOTCMDS_DHCP \
+	"bootcmd_dhcp=" \
+		"if dhcp ${scriptaddr} boot.scr.uimg; then "\
+			"source ${scriptaddr}; " \
+		"fi\0"
+#define BOOTCMD_DHCP "run bootcmd_dhcp; "
+#else
+#define BOOTCMDS_DHCP ""
+#define BOOTCMD_DHCP ""
+#endif
+
+#define BOOTCMDS_COMMON \
+	"scriptaddr=0x400000\0" \
+	"rootpart=1\0" \
+	"script_boot="													\
+		"for fs in " BOOTCMD_FS_EXT2 BOOTCMD_FS_FAT "; do "							\
+		    "for prefix in / /boot/; do "									\
+			"for script in boot.scr.uimg boot.scr; do "							\
+			    "echo Scanning ${devtype} ${devnum}:${rootpart} ${fs} ${prefix}${script} ...; "		\
+			    "if ${fs}load ${devtype} ${devnum}:${rootpart} ${scriptaddr} ${prefix}${script}; then "	\
+				"echo ${script} found! Executing ...;"							\
+				"source ${scriptaddr};"									\
+			    "fi; "											\
+			"done; "											\
+		    "done; "												\
+		"done;\0"												\
+	BOOTCMDS_MMC \
+	BOOTCMDS_USB \
+	BOOTCMDS_DHCP
+
+#define CONFIG_BOOTCOMMAND BOOTCMD_INIT_USB BOOTCMD_USB BOOTCMD_MMC BOOTCMD_DHCP
+
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	TEGRA2_DEVICE_SETTINGS \
+	BOOTCMDS_COMMON
+
+#endif /* __TEGRA2_COMMON_POST_H */
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index d60b5a1978a..a4146a50c6c 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -139,9 +139,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	TEGRA2_DEVICE_SETTINGS
-
 #define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
 #define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
 
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index a7338f10768..8e95db13a66 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -59,4 +59,7 @@
 
 /* Environment not stored */
 #define CONFIG_ENV_IS_NOWHERE
+
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 5efa60cdf6a..2f2a512e159 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -86,4 +86,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 
+#include "tegra2-common-post.h"
+
 #endif /* __CONFIG_H */
-- 
cgit v1.3.1


From dae2aeab7161aad105cfdb61b722c9b22c6ac6fb Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 16 May 2012 06:36:11 +0000
Subject: tegra: whistler: reduce and comment network cfg options

CONFIG_CMD_PING/NFS aren't required for Whistler to boot.

Add some comments.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/whistler.h | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 2f2a512e159..6c0c77e3ca0 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -74,16 +74,14 @@
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_USB_ETHER_ASIX
+
+/* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
 
-#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
-#define CONFIG_CMD_NFS      /* NFS support          */
-#define CONFIG_CMD_PING
+/* General networking support */
+#define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
 #include "tegra2-common-post.h"
-- 
cgit v1.3.1


From defd5e497960b870d11bffbfd952ec3eaf2dd20e Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 16 May 2012 06:36:12 +0000
Subject: tegra: seaboard: add support for USB networking

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/seaboard.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index d02a11e03cb..643af81a1b8 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -108,6 +108,15 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 /* Enable keyboard */
 #define CONFIG_TEGRA2_KEYBOARD
 #define CONFIG_KEYBOARD
-- 
cgit v1.3.1


From 39e37118398158d98f0e9b926d69af289ae7e7b8 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 16 May 2012 13:54:07 +0000
Subject: tegra: Compulab TrimSlice board support

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 MAINTAINERS                             |  1 +
 board/compulab/dts/tegra2-trimslice.dts | 57 +++++++++++++++++++++
 board/compulab/trimslice/Makefile       | 49 ++++++++++++++++++
 board/compulab/trimslice/trimslice.c    | 73 +++++++++++++++++++++++++++
 boards.cfg                              |  1 +
 include/configs/trimslice.h             | 89 +++++++++++++++++++++++++++++++++
 6 files changed, 270 insertions(+)
 create mode 100644 board/compulab/dts/tegra2-trimslice.dts
 create mode 100644 board/compulab/trimslice/Makefile
 create mode 100644 board/compulab/trimslice/trimslice.c
 create mode 100644 include/configs/trimslice.h

(limited to 'include/configs')

diff --git a/MAINTAINERS b/MAINTAINERS
index 0db7e84d9a0..6438e1cbe95 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -914,6 +914,7 @@ Stephen Warren <swarren@nvidia.com>
 
 	ventana		Tegra2 (ARM7 & A9 Dual Core)
 	paz00		Tegra2 (ARM7 & A9 Dual Core)
+	trimslice	Tegra2 (ARM7 & A9 Dual Core)
 	whistler	Tegra2 (ARM7 & A9 Dual Core)
 
 Thomas Weber <weber@corscience.de>
diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra2-trimslice.dts
new file mode 100644
index 00000000000..c707eb84ec2
--- /dev/null
+++ b/board/compulab/dts/tegra2-trimslice.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "Compulab TrimSlice board";
+	compatible = "compulab,trimslice", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+	};
+
+	memory {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	clocks {
+		clk_32k: clk_32k {
+			clock-frequency = <32000>;
+		};
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&clk_32k &osc>;
+	};
+
+	serial@70006000 {
+		clock-frequency = <216000000>;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+};
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
new file mode 100644
index 00000000000..bf624f41a25
--- /dev/null
+++ b/board/compulab/trimslice/Makefile
@@ -0,0 +1,49 @@
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../nvidia/common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+COBJS	+= ../../nvidia/common/board.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
new file mode 100644
index 00000000000..7167c914e05
--- /dev/null
+++ b/board/compulab/trimslice/trimslice.c
@@ -0,0 +1,73 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on TrimSlice - no UART-related GPIOs.
+ */
+void gpio_config_uart(void)
+{
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+
+	/* For CD GPIO PP1 */
+	pinmux_tristate_disable(PINGRP_DAP3);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	debug("board_mmc_init called\n");
+
+	/* Enable muxes, etc. for SDMMC controllers */
+	pin_mux_mmc();
+
+	/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
+	tegra2_mmc_init(0, 4, -1, GPIO_PP1);
+
+	/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
+	tegra2_mmc_init(3, 4, -1, -1);
+
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 055dbbc7b19..92050708b23 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -260,6 +260,7 @@ jornada                      arm         sa1100
 plutux                       arm         armv7       plutux              avionic-design tegra2
 medcom                       arm         armv7       medcom              avionic-design tegra2
 paz00                        arm         armv7       paz00               compal         tegra2
+trimslice                    arm         armv7       trimslice           compulab       tegra2
 atngw100                     avr32       at32ap      -                   atmel          at32ap700x
 atstk1002                    avr32       at32ap      atstk1000           atmel          at32ap700x
 atstk1003                    avr32       at32ap      atstk1000           atmel          at32ap700x
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
new file mode 100644
index 00000000000..dafca5eef60
--- /dev/null
+++ b/include/configs/trimslice.h
@@ -0,0 +1,89 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-trimslice
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra2 (TrimSlice) # "
+#define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Trimslice"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTA
+#define CONFIG_TEGRA2_UARTA_GPU
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRIMSLICE
+#define CONFIG_SYS_BOARD_ODMDATA	0x300c0011 /* lp?, 1GB, UARTA */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		4
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA2_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/* Environment not stored */
+#define CONFIG_ENV_IS_NOWHERE
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra2-common-post.h"
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From f3d93309c1ab0fe22e3229f99dbcfa7c857eb067 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 21 May 2012 10:04:27 +0000
Subject: tegra: harmony: add device tree support

... to enable USB host support, which enables Ethernet support.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/dts/tegra2-harmony.dts | 57 +++++++++++++++++++++++++++++++++++++
 include/configs/harmony.h           | 22 +++++++++++++-
 2 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 board/nvidia/dts/tegra2-harmony.dts

(limited to 'include/configs')

diff --git a/board/nvidia/dts/tegra2-harmony.dts b/board/nvidia/dts/tegra2-harmony.dts
new file mode 100644
index 00000000000..4f60a05f331
--- /dev/null
+++ b/board/nvidia/dts/tegra2-harmony.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Tegra2 Harmony evaluation board";
+	compatible = "nvidia,harmony", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+	};
+
+	memory {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	clocks {
+		clk_32k: clk_32k {
+			clock-frequency = <32000>;
+		};
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&clk_32k &osc>;
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+};
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 25d6ec7f909..88189bedb57 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,11 @@
 #include <asm/sizes.h>
 #include "tegra2-common.h"
 
+/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-harmony
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
 /* High-level configuration options */
 #define V_PROMPT		"Tegra2 (Harmony) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Harmony"
@@ -61,6 +66,21 @@
 /* Environment not stored */
 #define CONFIG_ENV_IS_NOWHERE
 
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 #include "tegra2-common-post.h"
 
 #endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 00a55add04222539846dd884217bcf40c504da92 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 21 May 2012 10:04:37 +0000
Subject: tegra: paz00: add device tree support

... to enable USB host support, which enables Ethernet support.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/compal/dts/tegra2-paz00.dts | 57 +++++++++++++++++++++++++++++++++++++++
 include/configs/paz00.h           | 22 ++++++++++++++-
 2 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 board/compal/dts/tegra2-paz00.dts

(limited to 'include/configs')

diff --git a/board/compal/dts/tegra2-paz00.dts b/board/compal/dts/tegra2-paz00.dts
new file mode 100644
index 00000000000..9e3e1690696
--- /dev/null
+++ b/board/compal/dts/tegra2-paz00.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+        model = "Toshiba AC100 / Dynabook AZ";
+        compatible = "compal,paz00", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	clocks {
+		clk_32k: clk_32k {
+			clock-frequency = <32000>;
+		};
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&clk_32k &osc>;
+	};
+
+	serial@70006000 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+};
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index ced185e106f..f8bd7dc749b 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010,2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,6 +20,11 @@
 #include <asm/sizes.h>
 #include "tegra2-common.h"
 
+/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-paz00
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
 /* High-level configuration options */
 #define V_PROMPT		"Tegra2 (Paz00) MOD # "
 #define CONFIG_TEGRA2_BOARD_STRING	"Compal Paz00"
@@ -48,6 +53,21 @@
 /* Environment not stored */
 #define CONFIG_ENV_IS_NOWHERE
 
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 #include "tegra2-common-post.h"
 
 #endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 59f8ac65f823fa02c73606860480b0e16febc68d Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 23 May 2012 07:29:29 +0000
Subject: tegra: remove CONFIG_USB_ETHER_SMSC95XX from boards without it

The SMSC95xx series may exist either directly on a main board, or as a USB
to Ethernet dongle. However, dongles containing these chips are very rare.
Hence, remove this config option, except on Harmony where such a chip is
actually present on the board.

The asix option remains, since it's a popular chip, and I actively use a
dongle containing this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
---
 include/configs/paz00.h     | 1 -
 include/configs/seaboard.h  | 1 -
 include/configs/trimslice.h | 1 -
 include/configs/whistler.h  | 1 -
 4 files changed, 4 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index f8bd7dc749b..3edd102d15d 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -61,7 +61,6 @@
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 643af81a1b8..f46740e53a1 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -110,7 +110,6 @@
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index dafca5eef60..21b9ef234b0 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -77,7 +77,6 @@
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 6c0c77e3ca0..51f806a108d 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -77,7 +77,6 @@
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-- 
cgit v1.3.1


From b1b9e4ce3af6d10c8442bff48b69cad151ddff82 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 23 May 2012 07:46:15 +0000
Subject: tegra: ventana: add own device tree, enable USB

Add a device tree for Ventana; the Seaboard file no longer represents
the HW present on Ventana.

Enable USB on Ventana.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/dts/tegra2-ventana.dts | 57 +++++++++++++++++++++++++++++++++++++
 include/configs/ventana.h           | 16 ++++++++++-
 2 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 board/nvidia/dts/tegra2-ventana.dts

(limited to 'include/configs')

diff --git a/board/nvidia/dts/tegra2-ventana.dts b/board/nvidia/dts/tegra2-ventana.dts
new file mode 100644
index 00000000000..900e871d741
--- /dev/null
+++ b/board/nvidia/dts/tegra2-ventana.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Tegra2 Ventana evaluation board";
+	compatible = "nvidia,ventana", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+	};
+
+	memory {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	clocks {
+		clk_32k: clk_32k {
+			clock-frequency = <32000>;
+		};
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&clk_32k &osc>;
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+};
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 8e95db13a66..2c7355b1971 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -28,7 +28,7 @@
 #include "tegra2-common.h"
 
 /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-seaboard
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-ventana
 #define CONFIG_OF_CONTROL
 #define CONFIG_OF_SEPARATE
 
@@ -60,6 +60,20 @@
 /* Environment not stored */
 #define CONFIG_ENV_IS_NOWHERE
 
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
 #include "tegra2-common-post.h"
 
 #endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 294cd67c8d4a7049dc8d972a52527f605dbdaff7 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 24 May 2012 11:38:35 +0000
Subject: tegra: ventana: store environment in eMMC

Store the environment in eMMC, at the end of the second boot sector.
This should not conflict with any other eMMC usage: U-Boot is stored
well below this location, and the kernel only uses the general area
of the eMMC once booted, not the boot sectors.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/ventana.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 2c7355b1971..665076d08ec 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -57,8 +57,10 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
-- 
cgit v1.3.1


From 616887016d4e82f15fa5acc5d111c16bf2d29843 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 24 May 2012 11:38:36 +0000
Subject: tegra: whistler: store environment in eMMC

Store the environment in eMMC, at the end of the second boot sector.
This should not conflict with any other eMMC usage: U-Boot is stored
well below this location, and the kernel only uses the general area
of the eMMC once booted, not the boot sectors.

Note: This assumes the user plugged the standard 8MB MoviNAND card into
J29/HSMMC/POP. If they didn't, the boot sector layout may be different.
However, use of that particular card is standard practice as far as I
know.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/whistler.h | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 51f806a108d..ec96cff49b2 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -66,8 +66,15 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/*
+ * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
+ * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If
+ * they didn't, the boot sector layout may be different. However, use of that
+ * particular card is standard practice as far as I know.
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
-- 
cgit v1.3.1


From edffa63d3d6e76991998789f9fcbaa483731ca65 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren.nvidia@gmail.com>
Date: Tue, 22 May 2012 07:33:47 +0000
Subject: spi: tegra2: rename tegra2_spi.* to tegra_spi.*

In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra2/tegra2_spi.h |  76 -------
 arch/arm/include/asm/arch-tegra2/tegra_spi.h  |  75 +++++++
 board/nvidia/common/uart-spi-switch.c         |   2 +-
 drivers/spi/Makefile                          |   2 +-
 drivers/spi/tegra2_spi.c                      | 290 --------------------------
 drivers/spi/tegra_spi.c                       | 290 ++++++++++++++++++++++++++
 include/configs/seaboard.h                    |   2 +-
 7 files changed, 368 insertions(+), 369 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_spi.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/tegra_spi.h
 delete mode 100644 drivers/spi/tegra2_spi.c
 create mode 100644 drivers/spi/tegra_spi.c

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
deleted file mode 100644
index ceec4287a3b..00000000000
--- a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * NVIDIA Tegra2 SPI-FLASH controller
- *
- * Copyright 2010-2011 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA2_SPI_H_
-#define _TEGRA2_SPI_H_
-
-#include <asm/types.h>
-
-struct spi_tegra {
-	u32 command;	/* SPI_COMMAND_0 register  */
-	u32 status;	/* SPI_STATUS_0 register */
-	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
-	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
-	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
-	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
-	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
-};
-
-#define SPI_CMD_GO			(1 << 30)
-#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
-#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA			(1 << 21)
-#define SPI_CMD_ACTIVE_SDA_SHIFT	18
-#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL			(1 << 16)
-#define SPI_CMD_TXEN			(1 << 15)
-#define SPI_CMD_RXEN			(1 << 14)
-#define SPI_CMD_CS_VAL			(1 << 13)
-#define SPI_CMD_CS_SOFT			(1 << 12)
-#define SPI_CMD_CS_DELAY		(1 << 9)
-#define SPI_CMD_CS3_EN			(1 << 8)
-#define SPI_CMD_CS2_EN			(1 << 7)
-#define SPI_CMD_CS1_EN			(1 << 6)
-#define SPI_CMD_CS0_EN			(1 << 5)
-#define SPI_CMD_BIT_LENGTH		(1 << 4)
-#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
-
-#define SPI_STAT_BSY			(1 << 31)
-#define SPI_STAT_RDY			(1 << 30)
-#define SPI_STAT_RXF_FLUSH		(1 << 29)
-#define SPI_STAT_TXF_FLUSH		(1 << 28)
-#define SPI_STAT_RXF_UNR		(1 << 27)
-#define SPI_STAT_TXF_OVF		(1 << 26)
-#define SPI_STAT_RXF_EMPTY		(1 << 25)
-#define SPI_STAT_RXF_FULL		(1 << 24)
-#define SPI_STAT_TXF_EMPTY		(1 << 23)
-#define SPI_STAT_TXF_FULL		(1 << 22)
-#define SPI_STAT_SEL_TXRX_N		(1 << 16)
-#define SPI_STAT_CUR_BLKCNT		(1 << 15)
-
-#define SPI_TIMEOUT		1000
-#define TEGRA2_SPI_MAX_FREQ	52000000
-
-
-#endif	/* _TEGRA2_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra_spi.h b/arch/arm/include/asm/arch-tegra2/tegra_spi.h
new file mode 100644
index 00000000000..892d90c00ba
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra_spi.h
@@ -0,0 +1,75 @@
+/*
+ * NVIDIA Tegra2 SPI-FLASH controller
+ *
+ * Copyright 2010-2012 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_SPI_H_
+#define _TEGRA_SPI_H_
+
+#include <asm/types.h>
+
+struct spi_tegra {
+	u32 command;	/* SPI_COMMAND_0 register  */
+	u32 status;	/* SPI_STATUS_0 register */
+	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
+	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
+	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
+	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
+	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
+};
+
+#define SPI_CMD_GO			(1 << 30)
+#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
+#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
+#define SPI_CMD_CK_SDA			(1 << 21)
+#define SPI_CMD_ACTIVE_SDA_SHIFT	18
+#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
+#define SPI_CMD_CS_POL			(1 << 16)
+#define SPI_CMD_TXEN			(1 << 15)
+#define SPI_CMD_RXEN			(1 << 14)
+#define SPI_CMD_CS_VAL			(1 << 13)
+#define SPI_CMD_CS_SOFT			(1 << 12)
+#define SPI_CMD_CS_DELAY		(1 << 9)
+#define SPI_CMD_CS3_EN			(1 << 8)
+#define SPI_CMD_CS2_EN			(1 << 7)
+#define SPI_CMD_CS1_EN			(1 << 6)
+#define SPI_CMD_CS0_EN			(1 << 5)
+#define SPI_CMD_BIT_LENGTH		(1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+
+#define SPI_STAT_BSY			(1 << 31)
+#define SPI_STAT_RDY			(1 << 30)
+#define SPI_STAT_RXF_FLUSH		(1 << 29)
+#define SPI_STAT_TXF_FLUSH		(1 << 28)
+#define SPI_STAT_RXF_UNR		(1 << 27)
+#define SPI_STAT_TXF_OVF		(1 << 26)
+#define SPI_STAT_RXF_EMPTY		(1 << 25)
+#define SPI_STAT_RXF_FULL		(1 << 24)
+#define SPI_STAT_TXF_EMPTY		(1 << 23)
+#define SPI_STAT_TXF_FULL		(1 << 22)
+#define SPI_STAT_SEL_TXRX_N		(1 << 16)
+#define SPI_STAT_CUR_BLKCNT		(1 << 15)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA2_SPI_MAX_FREQ	52000000
+
+#endif	/* _TEGRA_SPI_H_ */
diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c
index 1ba1afd1c91..307937a8364 100644
--- a/board/nvidia/common/uart-spi-switch.c
+++ b/board/nvidia/common/uart-spi-switch.c
@@ -25,7 +25,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart-spi-switch.h>
 #include <asm/arch/tegra2.h>
-#include <asm/arch/tegra2_spi.h>
+#include <asm/arch/tegra_spi.h>
 
 
 /* position of the UART/SPI select switch */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c967d87834a..c20f1f2daac 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,7 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
-COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
+COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
deleted file mode 100644
index fe7b405b132..00000000000
--- a/drivers/spi/tegra2_spi.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright (c) 2010-2011 NVIDIA Corporation
- * With help from the mpc8xxx SPI driver
- * With more help from omap3_spi SPI driver
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <malloc.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clk_rst.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra2_spi.h>
-
-#if defined(CONFIG_SPI_CORRUPTS_UART)
- #define corrupt_delay()	udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
-#else
- #define corrupt_delay()
-#endif
-
-struct tegra_spi_slave {
-	struct spi_slave slave;
-	struct spi_tegra *regs;
-	unsigned int freq;
-	unsigned int mode;
-};
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	/* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
-	if (bus != 0 || cs != 0)
-		return 0;
-	else
-		return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct tegra_spi_slave *spi;
-
-	if (!spi_cs_is_valid(bus, cs)) {
-		printf("SPI error: unsupported bus %d / chip select %d\n",
-		       bus, cs);
-		return NULL;
-	}
-
-	if (max_hz > TEGRA2_SPI_MAX_FREQ) {
-		printf("SPI error: unsupported frequency %d Hz. Max frequency"
-			" is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ);
-		return NULL;
-	}
-
-	spi = malloc(sizeof(struct tegra_spi_slave));
-	if (!spi) {
-		printf("SPI error: malloc of SPI structure failed\n");
-		return NULL;
-	}
-	spi->slave.bus = bus;
-	spi->slave.cs = cs;
-	spi->freq = max_hz;
-	spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE;
-	spi->mode = mode;
-
-	return &spi->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-	free(spi);
-}
-
-void spi_init(void)
-{
-	/* do nothing */
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_tegra *regs = spi->regs;
-	u32 reg;
-
-	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
-
-	/* Clear stale status here */
-	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
-		SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
-	writel(reg, &regs->status);
-	debug("spi_init: STATUS = %08x\n", readl(&regs->status));
-
-	/*
-	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
-	 */
-	reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
-	if (spi->mode & 2)
-		reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
-	clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
-		SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
-	debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
-
-	/*
-	 * SPI pins on Tegra2 are muxed - change pinmux later due to UART
-	 * issue.
-	 */
-	pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
-	pinmux_tristate_disable(PINGRP_LSPI);
-
-#ifndef CONFIG_SPI_UART_SWITCH
-	/*
-	 * NOTE:
-	 * Only set PinMux bits 3:2 to SPI here on boards that don't have the
-	 * SPI UART switch or subsequent UART data won't go out!  See
-	 * spi_uart_switch().
-	 */
-	/* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
-#endif
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	/*
-	 * We can't release UART_DISABLE and set pinmux to UART4 here since
-	 * some code (e,g, spi_flash_probe) uses printf() while the SPI
-	 * bus is held. That is arguably bad, but it has the advantage of
-	 * already being in the source tree.
-	 */
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-	pinmux_select_spi();
-
-	/* CS is negated on Tegra, so drive a 1 to get a 0 */
-	setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
-
-	corrupt_delay();		/* Let UART settle */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-	pinmux_select_uart();
-
-	/* CS is negated on Tegra, so drive a 0 to get a 1 */
-	clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
-
-	corrupt_delay();		/* Let SPI settle */
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		const void *data_out, void *data_in, unsigned long flags)
-{
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_tegra *regs = spi->regs;
-	u32 reg, tmpdout, tmpdin = 0;
-	const u8 *dout = data_out;
-	u8 *din = data_in;
-	int num_bytes;
-	int ret;
-
-	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
-	      slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
-	if (bitlen % 8)
-		return -1;
-	num_bytes = bitlen / 8;
-
-	ret = 0;
-
-	reg = readl(&regs->status);
-	writel(reg, &regs->status);	/* Clear all SPI events via R/W */
-	debug("spi_xfer entry: STATUS = %08x\n", reg);
-
-	reg = readl(&regs->command);
-	reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
-	writel(reg, &regs->command);
-	debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
-
-	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
-
-	/* handle data in 32-bit chunks */
-	while (num_bytes > 0) {
-		int bytes;
-		int is_read = 0;
-		int tm, i;
-
-		tmpdout = 0;
-		bytes = (num_bytes > 4) ?  4 : num_bytes;
-
-		if (dout != NULL) {
-			for (i = 0; i < bytes; ++i)
-				tmpdout = (tmpdout << 8) | dout[i];
-		}
-
-		num_bytes -= bytes;
-		if (dout)
-			dout += bytes;
-
-		clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
-				bytes * 8 - 1);
-		writel(tmpdout, &regs->tx_fifo);
-		setbits_le32(&regs->command, SPI_CMD_GO);
-
-		/*
-		 * Wait for SPI transmit FIFO to empty, or to time out.
-		 * The RX FIFO status will be read and cleared last
-		 */
-		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
-			u32 status;
-
-			status = readl(&regs->status);
-
-			/* We can exit when we've had both RX and TX activity */
-			if (is_read && (status & SPI_STAT_TXF_EMPTY))
-				break;
-
-			if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
-					SPI_STAT_RDY)
-				tm++;
-
-			else if (!(status & SPI_STAT_RXF_EMPTY)) {
-				tmpdin = readl(&regs->rx_fifo);
-				is_read = 1;
-
-				/* swap bytes read in */
-				if (din != NULL) {
-					for (i = bytes - 1; i >= 0; --i) {
-						din[i] = tmpdin & 0xff;
-						tmpdin >>= 8;
-					}
-					din += bytes;
-				}
-			}
-		}
-
-		if (tm >= SPI_TIMEOUT)
-			ret = tm;
-
-		/* clear ACK RDY, etc. bits */
-		writel(readl(&regs->status), &regs->status);
-	}
-
-	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
-
-	debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
-		tmpdin, readl(&regs->status));
-
-	if (ret) {
-		printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
-		return -1;
-	}
-
-	return 0;
-}
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
new file mode 100644
index 00000000000..4a3e7996f96
--- /dev/null
+++ b/drivers/spi/tegra_spi.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2010-2012 NVIDIA Corporation
+ * With help from the mpc8xxx SPI driver
+ * With more help from omap3_spi SPI driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart-spi-switch.h>
+#include <asm/arch/tegra_spi.h>
+
+#if defined(CONFIG_SPI_CORRUPTS_UART)
+ #define corrupt_delay()	udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
+#else
+ #define corrupt_delay()
+#endif
+
+struct tegra_spi_slave {
+	struct spi_slave slave;
+	struct spi_tegra *regs;
+	unsigned int freq;
+	unsigned int mode;
+};
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
+	if (bus != 0 || cs != 0)
+		return 0;
+	else
+		return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct tegra_spi_slave *spi;
+
+	if (!spi_cs_is_valid(bus, cs)) {
+		printf("SPI error: unsupported bus %d / chip select %d\n",
+		       bus, cs);
+		return NULL;
+	}
+
+	if (max_hz > TEGRA2_SPI_MAX_FREQ) {
+		printf("SPI error: unsupported frequency %d Hz. Max frequency"
+			" is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ);
+		return NULL;
+	}
+
+	spi = malloc(sizeof(struct tegra_spi_slave));
+	if (!spi) {
+		printf("SPI error: malloc of SPI structure failed\n");
+		return NULL;
+	}
+	spi->slave.bus = bus;
+	spi->slave.cs = cs;
+	spi->freq = max_hz;
+	spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE;
+	spi->mode = mode;
+
+	return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	free(spi);
+}
+
+void spi_init(void)
+{
+	/* do nothing */
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_tegra *regs = spi->regs;
+	u32 reg;
+
+	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
+	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
+
+	/* Clear stale status here */
+	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
+		SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
+	writel(reg, &regs->status);
+	debug("spi_init: STATUS = %08x\n", readl(&regs->status));
+
+	/*
+	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
+	 */
+	reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+	if (spi->mode & 2)
+		reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
+	clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
+		SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
+	debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
+
+	/*
+	 * SPI pins on Tegra2 are muxed - change pinmux later due to UART
+	 * issue.
+	 */
+	pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+	pinmux_tristate_disable(PINGRP_LSPI);
+
+#ifndef CONFIG_SPI_UART_SWITCH
+	/*
+	 * NOTE:
+	 * Only set PinMux bits 3:2 to SPI here on boards that don't have the
+	 * SPI UART switch or subsequent UART data won't go out!  See
+	 * spi_uart_switch().
+	 */
+	/* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
+#endif
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	/*
+	 * We can't release UART_DISABLE and set pinmux to UART4 here since
+	 * some code (e,g, spi_flash_probe) uses printf() while the SPI
+	 * bus is held. That is arguably bad, but it has the advantage of
+	 * already being in the source tree.
+	 */
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	pinmux_select_spi();
+
+	/* CS is negated on Tegra, so drive a 1 to get a 0 */
+	setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+
+	corrupt_delay();		/* Let UART settle */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	pinmux_select_uart();
+
+	/* CS is negated on Tegra, so drive a 0 to get a 1 */
+	clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+
+	corrupt_delay();		/* Let SPI settle */
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		const void *data_out, void *data_in, unsigned long flags)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_tegra *regs = spi->regs;
+	u32 reg, tmpdout, tmpdin = 0;
+	const u8 *dout = data_out;
+	u8 *din = data_in;
+	int num_bytes;
+	int ret;
+
+	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+	      slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+	if (bitlen % 8)
+		return -1;
+	num_bytes = bitlen / 8;
+
+	ret = 0;
+
+	reg = readl(&regs->status);
+	writel(reg, &regs->status);	/* Clear all SPI events via R/W */
+	debug("spi_xfer entry: STATUS = %08x\n", reg);
+
+	reg = readl(&regs->command);
+	reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
+	writel(reg, &regs->command);
+	debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/* handle data in 32-bit chunks */
+	while (num_bytes > 0) {
+		int bytes;
+		int is_read = 0;
+		int tm, i;
+
+		tmpdout = 0;
+		bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+		if (dout != NULL) {
+			for (i = 0; i < bytes; ++i)
+				tmpdout = (tmpdout << 8) | dout[i];
+		}
+
+		num_bytes -= bytes;
+		if (dout)
+			dout += bytes;
+
+		clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
+				bytes * 8 - 1);
+		writel(tmpdout, &regs->tx_fifo);
+		setbits_le32(&regs->command, SPI_CMD_GO);
+
+		/*
+		 * Wait for SPI transmit FIFO to empty, or to time out.
+		 * The RX FIFO status will be read and cleared last
+		 */
+		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+			u32 status;
+
+			status = readl(&regs->status);
+
+			/* We can exit when we've had both RX and TX activity */
+			if (is_read && (status & SPI_STAT_TXF_EMPTY))
+				break;
+
+			if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
+					SPI_STAT_RDY)
+				tm++;
+
+			else if (!(status & SPI_STAT_RXF_EMPTY)) {
+				tmpdin = readl(&regs->rx_fifo);
+				is_read = 1;
+
+				/* swap bytes read in */
+				if (din != NULL) {
+					for (i = bytes - 1; i >= 0; --i) {
+						din[i] = tmpdin & 0xff;
+						tmpdin >>= 8;
+					}
+					din += bytes;
+				}
+			}
+		}
+
+		if (tm >= SPI_TIMEOUT)
+			ret = tm;
+
+		/* clear ACK RDY, etc. bits */
+		writel(readl(&regs->status), &regs->status);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
+		tmpdin, readl(&regs->status));
+
+	if (ret) {
+		printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index f46740e53a1..db11d8a308c 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -67,7 +67,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* SPI */
-#define CONFIG_TEGRA2_SPI
+#define CONFIG_TEGRA_SPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_WINBOND
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-- 
cgit v1.3.1


From 3f82d89d3de76acf86279815a7752f7c04d043a2 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren.nvidia@gmail.com>
Date: Tue, 22 May 2012 11:44:48 +0000
Subject: mmc: tegra2: rename tegra2_mmc.* to tegra_mmc.*

In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/harmony/harmony.c   |   4 +-
 board/nvidia/seaboard/seaboard.c |   4 +-
 board/nvidia/whistler/whistler.c |   2 +-
 drivers/mmc/Makefile             |   2 +-
 drivers/mmc/tegra2_mmc.c         | 570 ---------------------------------------
 drivers/mmc/tegra2_mmc.h         | 131 ---------
 drivers/mmc/tegra_mmc.c          | 570 +++++++++++++++++++++++++++++++++++++++
 drivers/mmc/tegra_mmc.h          | 131 +++++++++
 include/configs/harmony.h        |   2 +-
 include/configs/medcom.h         |   2 +-
 include/configs/paz00.h          |   2 +-
 include/configs/plutux.h         |   2 +-
 include/configs/seaboard.h       |   2 +-
 include/configs/trimslice.h      |   2 +-
 include/configs/ventana.h        |   2 +-
 include/configs/whistler.h       |   2 +-
 16 files changed, 715 insertions(+), 715 deletions(-)
 delete mode 100644 drivers/mmc/tegra2_mmc.c
 delete mode 100644 drivers/mmc/tegra2_mmc.h
 create mode 100644 drivers/mmc/tegra_mmc.c
 create mode 100644 drivers/mmc/tegra_mmc.h

(limited to 'include/configs')

diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 8f8e7bf3fe5..f27ad37b701 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -29,7 +29,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
 #include <mmc.h>
 #endif
 
@@ -41,7 +41,7 @@ void gpio_config_uart(void)
 {
 }
 
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 94efb1e83d5..36039c4ed86 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -29,7 +29,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
 #include <mmc.h>
 #endif
 
@@ -54,7 +54,7 @@ void gpio_config_uart(void)
 }
 #endif
 
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
index 1c2f33face5..3ec24df2e74 100644
--- a/board/nvidia/whistler/whistler.c
+++ b/board/nvidia/whistler/whistler.c
@@ -30,7 +30,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
 #include <mmc.h>
 #endif
 
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index a8e681c2fed..c5677370157 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -42,7 +42,7 @@ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
 COBJS-$(CONFIG_SDHCI) += sdhci.o
 COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
 COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
-COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
+COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c
deleted file mode 100644
index fb8a57d162f..00000000000
--- a/drivers/mmc/tegra2_mmc.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
-#include <asm/arch/clock.h>
-#include "tegra2_mmc.h"
-
-/* support 4 mmc hosts */
-struct mmc mmc_dev[4];
-struct mmc_host mmc_host[4];
-
-
-/**
- * Get the host address and peripheral ID for a device. Devices are numbered
- * from 0 to 3.
- *
- * @param host		Structure to fill in (base, reg, mmc_id)
- * @param dev_index	Device index (0-3)
- */
-static void tegra2_get_setup(struct mmc_host *host, int dev_index)
-{
-	debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
-
-	switch (dev_index) {
-	case 1:
-		host->base = TEGRA2_SDMMC3_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC3;
-		break;
-	case 2:
-		host->base = TEGRA2_SDMMC2_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC2;
-		break;
-	case 3:
-		host->base = TEGRA2_SDMMC1_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC1;
-		break;
-	case 0:
-	default:
-		host->base = TEGRA2_SDMMC4_BASE;
-		host->mmc_id = PERIPH_ID_SDMMC4;
-		break;
-	}
-
-	host->reg = (struct tegra2_mmc *)host->base;
-}
-
-static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
-{
-	unsigned char ctrl;
-
-	debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
-	(u32)data->dest, data->blocks, data->blocksize);
-
-	writel((u32)data->dest, &host->reg->sysad);
-	/*
-	 * DMASEL[4:3]
-	 * 00 = Selects SDMA
-	 * 01 = Reserved
-	 * 10 = Selects 32-bit Address ADMA2
-	 * 11 = Selects 64-bit Address ADMA2
-	 */
-	ctrl = readb(&host->reg->hostctl);
-	ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
-	ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
-	writeb(ctrl, &host->reg->hostctl);
-
-	/* We do not handle DMA boundaries, so set it to max (512 KiB) */
-	writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
-	writew(data->blocks, &host->reg->blkcnt);
-}
-
-static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
-{
-	unsigned short mode;
-	debug(" mmc_set_transfer_mode called\n");
-	/*
-	 * TRNMOD
-	 * MUL1SIN0[5]	: Multi/Single Block Select
-	 * RD1WT0[4]	: Data Transfer Direction Select
-	 *	1 = read
-	 *	0 = write
-	 * ENACMD12[2]	: Auto CMD12 Enable
-	 * ENBLKCNT[1]	: Block Count Enable
-	 * ENDMA[0]	: DMA Enable
-	 */
-	mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
-		TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
-
-	if (data->blocks > 1)
-		mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
-
-	if (data->flags & MMC_DATA_READ)
-		mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
-
-	if (data->flags & MMC_DATA_WRITE) {
-		if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1))
-			printf("Warning: unaligned write to %p may fail\n",
-			       data->src);
-		flush_dcache_range((ulong)data->src, (ulong)data->src +
-			data->blocks * data->blocksize);
-	}
-
-	writew(mode, &host->reg->trnmod);
-}
-
-static int mmc_wait_inhibit(struct mmc_host *host,
-			    struct mmc_cmd *cmd,
-			    struct mmc_data *data,
-			    unsigned int timeout)
-{
-	/*
-	 * PRNSTS
-	 * CMDINHDAT[1] : Command Inhibit (DAT)
-	 * CMDINHCMD[0] : Command Inhibit (CMD)
-	 */
-	unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
-
-	/*
-	 * We shouldn't wait for data inhibit for stop commands, even
-	 * though they might use busy signaling
-	 */
-	if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
-		mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
-
-	while (readl(&host->reg->prnsts) & mask) {
-		if (timeout == 0) {
-			printf("%s: timeout error\n", __func__);
-			return -1;
-		}
-		timeout--;
-		udelay(1000);
-	}
-
-	return 0;
-}
-
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
-	int flags, i;
-	int result;
-	unsigned int mask = 0;
-	unsigned int retry = 0x100000;
-	debug(" mmc_send_cmd called\n");
-
-	result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
-
-	if (result < 0)
-		return result;
-
-	if (data)
-		mmc_prepare_data(host, data);
-
-	debug("cmd->arg: %08x\n", cmd->cmdarg);
-	writel(cmd->cmdarg, &host->reg->argument);
-
-	if (data)
-		mmc_set_transfer_mode(host, data);
-
-	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
-		return -1;
-
-	/*
-	 * CMDREG
-	 * CMDIDX[13:8]	: Command index
-	 * DATAPRNT[5]	: Data Present Select
-	 * ENCMDIDX[4]	: Command Index Check Enable
-	 * ENCMDCRC[3]	: Command CRC Check Enable
-	 * RSPTYP[1:0]
-	 *	00 = No Response
-	 *	01 = Length 136
-	 *	10 = Length 48
-	 *	11 = Length 48 Check busy after response
-	 */
-	if (!(cmd->resp_type & MMC_RSP_PRESENT))
-		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
-	else if (cmd->resp_type & MMC_RSP_136)
-		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
-	else if (cmd->resp_type & MMC_RSP_BUSY)
-		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
-	else
-		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
-
-	if (cmd->resp_type & MMC_RSP_CRC)
-		flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
-	if (cmd->resp_type & MMC_RSP_OPCODE)
-		flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
-	if (data)
-		flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
-
-	debug("cmd: %d\n", cmd->cmdidx);
-
-	writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
-
-	for (i = 0; i < retry; i++) {
-		mask = readl(&host->reg->norintsts);
-		/* Command Complete */
-		if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
-			if (!data)
-				writel(mask, &host->reg->norintsts);
-			break;
-		}
-	}
-
-	if (i == retry) {
-		printf("%s: waiting for status update\n", __func__);
-		writel(mask, &host->reg->norintsts);
-		return TIMEOUT;
-	}
-
-	if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
-		/* Timeout Error */
-		debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
-		writel(mask, &host->reg->norintsts);
-		return TIMEOUT;
-	} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
-		/* Error Interrupt */
-		debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
-		writel(mask, &host->reg->norintsts);
-		return -1;
-	}
-
-	if (cmd->resp_type & MMC_RSP_PRESENT) {
-		if (cmd->resp_type & MMC_RSP_136) {
-			/* CRC is stripped so we need to do some shifting. */
-			for (i = 0; i < 4; i++) {
-				unsigned int offset =
-					(unsigned int)(&host->reg->rspreg3 - i);
-				cmd->response[i] = readl(offset) << 8;
-
-				if (i != 3) {
-					cmd->response[i] |=
-						readb(offset - 1);
-				}
-				debug("cmd->resp[%d]: %08x\n",
-						i, cmd->response[i]);
-			}
-		} else if (cmd->resp_type & MMC_RSP_BUSY) {
-			for (i = 0; i < retry; i++) {
-				/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
-				if (readl(&host->reg->prnsts)
-					& (1 << 20))	/* DAT[0] */
-					break;
-			}
-
-			if (i == retry) {
-				printf("%s: card is still busy\n", __func__);
-				writel(mask, &host->reg->norintsts);
-				return TIMEOUT;
-			}
-
-			cmd->response[0] = readl(&host->reg->rspreg0);
-			debug("cmd->resp[0]: %08x\n", cmd->response[0]);
-		} else {
-			cmd->response[0] = readl(&host->reg->rspreg0);
-			debug("cmd->resp[0]: %08x\n", cmd->response[0]);
-		}
-	}
-
-	if (data) {
-		unsigned long	start = get_timer(0);
-
-		while (1) {
-			mask = readl(&host->reg->norintsts);
-
-			if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
-				/* Error Interrupt */
-				writel(mask, &host->reg->norintsts);
-				printf("%s: error during transfer: 0x%08x\n",
-						__func__, mask);
-				return -1;
-			} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
-				/*
-				 * DMA Interrupt, restart the transfer where
-				 * it was interrupted.
-				 */
-				unsigned int address = readl(&host->reg->sysad);
-
-				debug("DMA end\n");
-				writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
-				       &host->reg->norintsts);
-				writel(address, &host->reg->sysad);
-			} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
-				/* Transfer Complete */
-				debug("r/w is done\n");
-				break;
-			} else if (get_timer(start) > 2000UL) {
-				writel(mask, &host->reg->norintsts);
-				printf("%s: MMC Timeout\n"
-				       "    Interrupt status        0x%08x\n"
-				       "    Interrupt status enable 0x%08x\n"
-				       "    Interrupt signal enable 0x%08x\n"
-				       "    Present status          0x%08x\n",
-				       __func__, mask,
-				       readl(&host->reg->norintstsen),
-				       readl(&host->reg->norintsigen),
-				       readl(&host->reg->prnsts));
-				return -1;
-			}
-		}
-		writel(mask, &host->reg->norintsts);
-		if (data->flags & MMC_DATA_READ) {
-			if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1))
-				printf("Warning: unaligned read from %p "
-					"may fail\n", data->dest);
-			invalidate_dcache_range((ulong)data->dest,
-				(ulong)data->dest +
-					data->blocks * data->blocksize);
-		}
-	}
-
-	udelay(1000);
-	return 0;
-}
-
-static void mmc_change_clock(struct mmc_host *host, uint clock)
-{
-	int div;
-	unsigned short clk;
-	unsigned long timeout;
-
-	debug(" mmc_change_clock called\n");
-
-	/*
-	 * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
-	 * PLLP_OUT0
-	 */
-	if (clock == 0)
-		goto out;
-	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
-				    &div);
-	debug("div = %d\n", div);
-
-	writew(0, &host->reg->clkcon);
-
-	/*
-	 * CLKCON
-	 * SELFREQ[15:8]	: base clock divided by value
-	 * ENSDCLK[2]		: SD Clock Enable
-	 * STBLINTCLK[1]	: Internal Clock Stable
-	 * ENINTCLK[0]		: Internal Clock Enable
-	 */
-	div >>= 1;
-	clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
-	       TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
-	writew(clk, &host->reg->clkcon);
-
-	/* Wait max 10 ms */
-	timeout = 10;
-	while (!(readw(&host->reg->clkcon) &
-		 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
-		if (timeout == 0) {
-			printf("%s: timeout error\n", __func__);
-			return;
-		}
-		timeout--;
-		udelay(1000);
-	}
-
-	clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
-	writew(clk, &host->reg->clkcon);
-
-	debug("mmc_change_clock: clkcon = %08X\n", clk);
-
-out:
-	host->clock = clock;
-}
-
-static void mmc_set_ios(struct mmc *mmc)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned char ctrl;
-	debug(" mmc_set_ios called\n");
-
-	debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
-
-	/* Change clock first */
-	mmc_change_clock(host, mmc->clock);
-
-	ctrl = readb(&host->reg->hostctl);
-
-	/*
-	 * WIDE8[5]
-	 * 0 = Depend on WIDE4
-	 * 1 = 8-bit mode
-	 * WIDE4[1]
-	 * 1 = 4-bit mode
-	 * 0 = 1-bit mode
-	 */
-	if (mmc->bus_width == 8)
-		ctrl |= (1 << 5);
-	else if (mmc->bus_width == 4)
-		ctrl |= (1 << 1);
-	else
-		ctrl &= ~(1 << 1);
-
-	writeb(ctrl, &host->reg->hostctl);
-	debug("mmc_set_ios: hostctl = %08X\n", ctrl);
-}
-
-static void mmc_reset(struct mmc_host *host)
-{
-	unsigned int timeout;
-	debug(" mmc_reset called\n");
-
-	/*
-	 * RSTALL[0] : Software reset for all
-	 * 1 = reset
-	 * 0 = work
-	 */
-	writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
-
-	host->clock = 0;
-
-	/* Wait max 100 ms */
-	timeout = 100;
-
-	/* hw clears the bit when it's done */
-	while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
-		if (timeout == 0) {
-			printf("%s: timeout error\n", __func__);
-			return;
-		}
-		timeout--;
-		udelay(1000);
-	}
-}
-
-static int mmc_core_init(struct mmc *mmc)
-{
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
-	unsigned int mask;
-	debug(" mmc_core_init called\n");
-
-	mmc_reset(host);
-
-	host->version = readw(&host->reg->hcver);
-	debug("host version = %x\n", host->version);
-
-	/* mask all */
-	writel(0xffffffff, &host->reg->norintstsen);
-	writel(0xffffffff, &host->reg->norintsigen);
-
-	writeb(0xe, &host->reg->timeoutcon);	/* TMCLK * 2^27 */
-	/*
-	 * NORMAL Interrupt Status Enable Register init
-	 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
-	 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
-	 * [3] ENSTADMAINT   : DMA boundary interrupt
-	 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
-	 * [0] ENSTACMDCMPLT : Command Complete Status Enable
-	*/
-	mask = readl(&host->reg->norintstsen);
-	mask &= ~(0xffff);
-	mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
-		 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
-		 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
-		 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
-		 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
-	writel(mask, &host->reg->norintstsen);
-
-	/*
-	 * NORMAL Interrupt Signal Enable Register init
-	 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
-	 */
-	mask = readl(&host->reg->norintsigen);
-	mask &= ~(0xffff);
-	mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
-	writel(mask, &host->reg->norintsigen);
-
-	return 0;
-}
-
-int tegra2_mmc_getcd(struct mmc *mmc)
-{
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
-
-	debug("tegra2_mmc_getcd called\n");
-
-	if (host->cd_gpio >= 0)
-		return !gpio_get_value(host->cd_gpio);
-
-	return 1;
-}
-
-int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
-{
-	struct mmc_host *host;
-	char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
-	struct mmc *mmc;
-
-	debug(" tegra2_mmc_init: index %d, bus width %d "
-		"pwr_gpio %d cd_gpio %d\n",
-		dev_index, bus_width, pwr_gpio, cd_gpio);
-
-	host = &mmc_host[dev_index];
-
-	host->clock = 0;
-	host->pwr_gpio = pwr_gpio;
-	host->cd_gpio = cd_gpio;
-	tegra2_get_setup(host, dev_index);
-
-	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
-
-	if (host->pwr_gpio >= 0) {
-		sprintf(gpusage, "SD/MMC%d PWR", dev_index);
-		gpio_request(host->pwr_gpio, gpusage);
-		gpio_direction_output(host->pwr_gpio, 1);
-	}
-
-	if (host->cd_gpio >= 0) {
-		sprintf(gpusage, "SD/MMC%d CD", dev_index);
-		gpio_request(host->cd_gpio, gpusage);
-		gpio_direction_input(host->cd_gpio);
-	}
-
-	mmc = &mmc_dev[dev_index];
-
-	sprintf(mmc->name, "Tegra2 SD/MMC");
-	mmc->priv = host;
-	mmc->send_cmd = mmc_send_cmd;
-	mmc->set_ios = mmc_set_ios;
-	mmc->init = mmc_core_init;
-	mmc->getcd = tegra2_mmc_getcd;
-
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	if (bus_width == 8)
-		mmc->host_caps = MMC_MODE_8BIT;
-	else
-		mmc->host_caps = MMC_MODE_4BIT;
-	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
-
-	/*
-	 * min freq is for card identification, and is the highest
-	 *  low-speed SDIO card frequency (actually 400KHz)
-	 * max freq is highest HS eMMC clock as per the SD/MMC spec
-	 *  (actually 52MHz)
-	 * Both of these are the closest equivalents w/216MHz source
-	 *  clock and Tegra2 SDMMC divisors.
-	 */
-	mmc->f_min = 375000;
-	mmc->f_max = 48000000;
-
-	mmc_register(mmc);
-
-	return 0;
-}
diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h
deleted file mode 100644
index 67c00db9de8..00000000000
--- a/drivers/mmc/tegra2_mmc.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __TEGRA2_MMC_H_
-#define __TEGRA2_MMC_H_
-
-#define TEGRA2_SDMMC1_BASE	0xC8000000
-#define TEGRA2_SDMMC2_BASE	0xC8000200
-#define TEGRA2_SDMMC3_BASE	0xC8000400
-#define TEGRA2_SDMMC4_BASE	0xC8000600
-
-#ifndef __ASSEMBLY__
-struct tegra2_mmc {
-	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
-	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
-	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
-	unsigned int	argument;	/* _ARGUMENT_0 */
-	unsigned short	trnmod;		/* _CMD_XFER_MODE_0 15:00 xfer mode */
-	unsigned short	cmdreg;		/* _CMD_XFER_MODE_0 31:16 cmd reg */
-	unsigned int	rspreg0;	/* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
-	unsigned int	rspreg1;	/* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
-	unsigned int	rspreg2;	/* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
-	unsigned int	rspreg3;	/* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
-	unsigned int	bdata;		/* _BUFFER_DATA_PORT_0 */
-	unsigned int	prnsts;		/* _PRESENT_STATE_0 */
-	unsigned char	hostctl;	/* _POWER_CONTROL_HOST_0 7:00 */
-	unsigned char	pwrcon;		/* _POWER_CONTROL_HOST_0 15:8 */
-	unsigned char	blkgap;		/* _POWER_CONTROL_HOST_9 23:16 */
-	unsigned char	wakcon;		/* _POWER_CONTROL_HOST_0 31:24 */
-	unsigned short	clkcon;		/* _CLOCK_CONTROL_0 15:00 */
-	unsigned char	timeoutcon;	/* _TIMEOUT_CTRL 23:16 */
-	unsigned char	swrst;		/* _SW_RESET_ 31:24 */
-	unsigned int	norintsts;	/* _INTERRUPT_STATUS_0 */
-	unsigned int	norintstsen;	/* _INTERRUPT_STATUS_ENABLE_0 */
-	unsigned int	norintsigen;	/* _INTERRUPT_SIGNAL_ENABLE_0 */
-	unsigned short	acmd12errsts;	/* _AUTO_CMD12_ERR_STATUS_0 15:00 */
-	unsigned char	res1[2];	/* _RESERVED 31:16 */
-	unsigned int	capareg;	/* _CAPABILITIES_0 */
-	unsigned char	res2[4];	/* RESERVED, offset 44h-47h */
-	unsigned int	maxcurr;	/* _MAXIMUM_CURRENT_0 */
-	unsigned char	res3[4];	/* RESERVED, offset 4Ch-4Fh */
-	unsigned short	setacmd12err;	/* offset 50h */
-	unsigned short	setinterr;	/* offset 52h */
-	unsigned char	admaerr;	/* offset 54h */
-	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
-	unsigned long	admaaddr;	/* offset 58h-5Fh */
-	unsigned char	res5[0x9c];	/* RESERVED, offset 60h-FBh */
-	unsigned short	slotintstatus;	/* offset FCh */
-	unsigned short	hcver;		/* HOST Version */
-	unsigned char	res6[0x100];	/* RESERVED, offset 100h-1FFh */
-};
-
-#define TEGRA_MMC_HOSTCTL_DMASEL_MASK				(3 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA				(0 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT			(2 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT			(3 << 3)
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE				(1 << 0)
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE			(1 << 1)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE		(0 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ			(1 << 4)
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT			(1 << 5)
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK			(3 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE		(0 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136		(1 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48		(2 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY	(3 << 0)
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK				(1 << 3)
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK			(1 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER	(1 << 5)
-
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD			(1 << 0)
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT			(1 << 1)
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE			(1 << 0)
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE			(1 << 1)
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE			(1 << 2)
-
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE			(1 << 0)
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE			(1 << 1)
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT			(1 << 3)
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT			(1 << 15)
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT				(1 << 16)
-
-#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE			(1 << 0)
-#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE			(1 << 1)
-#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT			(1 << 3)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY		(1 << 4)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY			(1 << 5)
-
-#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
-
-struct mmc_host {
-	struct tegra2_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-	unsigned int base;	/* Base address, SDMMC1/2/3/4 */
-	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
-	int pwr_gpio;		/* Power GPIO */
-	int cd_gpio;		/* Change Detect GPIO */
-};
-
-#endif	/* __ASSEMBLY__ */
-#endif	/* __TEGRA2_MMC_H_ */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
new file mode 100644
index 00000000000..29bf58359db
--- /dev/null
+++ b/drivers/mmc/tegra_mmc.c
@@ -0,0 +1,570 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ * Portions Copyright 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include "tegra_mmc.h"
+
+/* support 4 mmc hosts */
+struct mmc mmc_dev[4];
+struct mmc_host mmc_host[4];
+
+
+/**
+ * Get the host address and peripheral ID for a device. Devices are numbered
+ * from 0 to 3.
+ *
+ * @param host		Structure to fill in (base, reg, mmc_id)
+ * @param dev_index	Device index (0-3)
+ */
+static void tegra2_get_setup(struct mmc_host *host, int dev_index)
+{
+	debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
+
+	switch (dev_index) {
+	case 1:
+		host->base = TEGRA2_SDMMC3_BASE;
+		host->mmc_id = PERIPH_ID_SDMMC3;
+		break;
+	case 2:
+		host->base = TEGRA2_SDMMC2_BASE;
+		host->mmc_id = PERIPH_ID_SDMMC2;
+		break;
+	case 3:
+		host->base = TEGRA2_SDMMC1_BASE;
+		host->mmc_id = PERIPH_ID_SDMMC1;
+		break;
+	case 0:
+	default:
+		host->base = TEGRA2_SDMMC4_BASE;
+		host->mmc_id = PERIPH_ID_SDMMC4;
+		break;
+	}
+
+	host->reg = (struct tegra2_mmc *)host->base;
+}
+
+static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
+{
+	unsigned char ctrl;
+
+	debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
+	(u32)data->dest, data->blocks, data->blocksize);
+
+	writel((u32)data->dest, &host->reg->sysad);
+	/*
+	 * DMASEL[4:3]
+	 * 00 = Selects SDMA
+	 * 01 = Reserved
+	 * 10 = Selects 32-bit Address ADMA2
+	 * 11 = Selects 64-bit Address ADMA2
+	 */
+	ctrl = readb(&host->reg->hostctl);
+	ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
+	ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
+	writeb(ctrl, &host->reg->hostctl);
+
+	/* We do not handle DMA boundaries, so set it to max (512 KiB) */
+	writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
+	writew(data->blocks, &host->reg->blkcnt);
+}
+
+static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
+{
+	unsigned short mode;
+	debug(" mmc_set_transfer_mode called\n");
+	/*
+	 * TRNMOD
+	 * MUL1SIN0[5]	: Multi/Single Block Select
+	 * RD1WT0[4]	: Data Transfer Direction Select
+	 *	1 = read
+	 *	0 = write
+	 * ENACMD12[2]	: Auto CMD12 Enable
+	 * ENBLKCNT[1]	: Block Count Enable
+	 * ENDMA[0]	: DMA Enable
+	 */
+	mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
+		TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
+
+	if (data->blocks > 1)
+		mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
+
+	if (data->flags & MMC_DATA_READ)
+		mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
+
+	if (data->flags & MMC_DATA_WRITE) {
+		if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1))
+			printf("Warning: unaligned write to %p may fail\n",
+			       data->src);
+		flush_dcache_range((ulong)data->src, (ulong)data->src +
+			data->blocks * data->blocksize);
+	}
+
+	writew(mode, &host->reg->trnmod);
+}
+
+static int mmc_wait_inhibit(struct mmc_host *host,
+			    struct mmc_cmd *cmd,
+			    struct mmc_data *data,
+			    unsigned int timeout)
+{
+	/*
+	 * PRNSTS
+	 * CMDINHDAT[1] : Command Inhibit (DAT)
+	 * CMDINHCMD[0] : Command Inhibit (CMD)
+	 */
+	unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
+
+	/*
+	 * We shouldn't wait for data inhibit for stop commands, even
+	 * though they might use busy signaling
+	 */
+	if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
+		mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
+
+	while (readl(&host->reg->prnsts) & mask) {
+		if (timeout == 0) {
+			printf("%s: timeout error\n", __func__);
+			return -1;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	return 0;
+}
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	int flags, i;
+	int result;
+	unsigned int mask = 0;
+	unsigned int retry = 0x100000;
+	debug(" mmc_send_cmd called\n");
+
+	result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
+
+	if (result < 0)
+		return result;
+
+	if (data)
+		mmc_prepare_data(host, data);
+
+	debug("cmd->arg: %08x\n", cmd->cmdarg);
+	writel(cmd->cmdarg, &host->reg->argument);
+
+	if (data)
+		mmc_set_transfer_mode(host, data);
+
+	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
+		return -1;
+
+	/*
+	 * CMDREG
+	 * CMDIDX[13:8]	: Command index
+	 * DATAPRNT[5]	: Data Present Select
+	 * ENCMDIDX[4]	: Command Index Check Enable
+	 * ENCMDCRC[3]	: Command CRC Check Enable
+	 * RSPTYP[1:0]
+	 *	00 = No Response
+	 *	01 = Length 136
+	 *	10 = Length 48
+	 *	11 = Length 48 Check busy after response
+	 */
+	if (!(cmd->resp_type & MMC_RSP_PRESENT))
+		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
+	else if (cmd->resp_type & MMC_RSP_136)
+		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
+	else if (cmd->resp_type & MMC_RSP_BUSY)
+		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
+	else
+		flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
+	if (data)
+		flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
+
+	debug("cmd: %d\n", cmd->cmdidx);
+
+	writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
+
+	for (i = 0; i < retry; i++) {
+		mask = readl(&host->reg->norintsts);
+		/* Command Complete */
+		if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
+			if (!data)
+				writel(mask, &host->reg->norintsts);
+			break;
+		}
+	}
+
+	if (i == retry) {
+		printf("%s: waiting for status update\n", __func__);
+		writel(mask, &host->reg->norintsts);
+		return TIMEOUT;
+	}
+
+	if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
+		/* Timeout Error */
+		debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
+		writel(mask, &host->reg->norintsts);
+		return TIMEOUT;
+	} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
+		/* Error Interrupt */
+		debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
+		writel(mask, &host->reg->norintsts);
+		return -1;
+	}
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		if (cmd->resp_type & MMC_RSP_136) {
+			/* CRC is stripped so we need to do some shifting. */
+			for (i = 0; i < 4; i++) {
+				unsigned int offset =
+					(unsigned int)(&host->reg->rspreg3 - i);
+				cmd->response[i] = readl(offset) << 8;
+
+				if (i != 3) {
+					cmd->response[i] |=
+						readb(offset - 1);
+				}
+				debug("cmd->resp[%d]: %08x\n",
+						i, cmd->response[i]);
+			}
+		} else if (cmd->resp_type & MMC_RSP_BUSY) {
+			for (i = 0; i < retry; i++) {
+				/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
+				if (readl(&host->reg->prnsts)
+					& (1 << 20))	/* DAT[0] */
+					break;
+			}
+
+			if (i == retry) {
+				printf("%s: card is still busy\n", __func__);
+				writel(mask, &host->reg->norintsts);
+				return TIMEOUT;
+			}
+
+			cmd->response[0] = readl(&host->reg->rspreg0);
+			debug("cmd->resp[0]: %08x\n", cmd->response[0]);
+		} else {
+			cmd->response[0] = readl(&host->reg->rspreg0);
+			debug("cmd->resp[0]: %08x\n", cmd->response[0]);
+		}
+	}
+
+	if (data) {
+		unsigned long	start = get_timer(0);
+
+		while (1) {
+			mask = readl(&host->reg->norintsts);
+
+			if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
+				/* Error Interrupt */
+				writel(mask, &host->reg->norintsts);
+				printf("%s: error during transfer: 0x%08x\n",
+						__func__, mask);
+				return -1;
+			} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
+				/*
+				 * DMA Interrupt, restart the transfer where
+				 * it was interrupted.
+				 */
+				unsigned int address = readl(&host->reg->sysad);
+
+				debug("DMA end\n");
+				writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
+				       &host->reg->norintsts);
+				writel(address, &host->reg->sysad);
+			} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
+				/* Transfer Complete */
+				debug("r/w is done\n");
+				break;
+			} else if (get_timer(start) > 2000UL) {
+				writel(mask, &host->reg->norintsts);
+				printf("%s: MMC Timeout\n"
+				       "    Interrupt status        0x%08x\n"
+				       "    Interrupt status enable 0x%08x\n"
+				       "    Interrupt signal enable 0x%08x\n"
+				       "    Present status          0x%08x\n",
+				       __func__, mask,
+				       readl(&host->reg->norintstsen),
+				       readl(&host->reg->norintsigen),
+				       readl(&host->reg->prnsts));
+				return -1;
+			}
+		}
+		writel(mask, &host->reg->norintsts);
+		if (data->flags & MMC_DATA_READ) {
+			if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1))
+				printf("Warning: unaligned read from %p "
+					"may fail\n", data->dest);
+			invalidate_dcache_range((ulong)data->dest,
+				(ulong)data->dest +
+					data->blocks * data->blocksize);
+		}
+	}
+
+	udelay(1000);
+	return 0;
+}
+
+static void mmc_change_clock(struct mmc_host *host, uint clock)
+{
+	int div;
+	unsigned short clk;
+	unsigned long timeout;
+
+	debug(" mmc_change_clock called\n");
+
+	/*
+	 * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
+	 * PLLP_OUT0
+	 */
+	if (clock == 0)
+		goto out;
+	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
+				    &div);
+	debug("div = %d\n", div);
+
+	writew(0, &host->reg->clkcon);
+
+	/*
+	 * CLKCON
+	 * SELFREQ[15:8]	: base clock divided by value
+	 * ENSDCLK[2]		: SD Clock Enable
+	 * STBLINTCLK[1]	: Internal Clock Stable
+	 * ENINTCLK[0]		: Internal Clock Enable
+	 */
+	div >>= 1;
+	clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
+	       TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
+	writew(clk, &host->reg->clkcon);
+
+	/* Wait max 10 ms */
+	timeout = 10;
+	while (!(readw(&host->reg->clkcon) &
+		 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
+		if (timeout == 0) {
+			printf("%s: timeout error\n", __func__);
+			return;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+	writew(clk, &host->reg->clkcon);
+
+	debug("mmc_change_clock: clkcon = %08X\n", clk);
+
+out:
+	host->clock = clock;
+}
+
+static void mmc_set_ios(struct mmc *mmc)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned char ctrl;
+	debug(" mmc_set_ios called\n");
+
+	debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
+
+	/* Change clock first */
+	mmc_change_clock(host, mmc->clock);
+
+	ctrl = readb(&host->reg->hostctl);
+
+	/*
+	 * WIDE8[5]
+	 * 0 = Depend on WIDE4
+	 * 1 = 8-bit mode
+	 * WIDE4[1]
+	 * 1 = 4-bit mode
+	 * 0 = 1-bit mode
+	 */
+	if (mmc->bus_width == 8)
+		ctrl |= (1 << 5);
+	else if (mmc->bus_width == 4)
+		ctrl |= (1 << 1);
+	else
+		ctrl &= ~(1 << 1);
+
+	writeb(ctrl, &host->reg->hostctl);
+	debug("mmc_set_ios: hostctl = %08X\n", ctrl);
+}
+
+static void mmc_reset(struct mmc_host *host)
+{
+	unsigned int timeout;
+	debug(" mmc_reset called\n");
+
+	/*
+	 * RSTALL[0] : Software reset for all
+	 * 1 = reset
+	 * 0 = work
+	 */
+	writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
+
+	host->clock = 0;
+
+	/* Wait max 100 ms */
+	timeout = 100;
+
+	/* hw clears the bit when it's done */
+	while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
+		if (timeout == 0) {
+			printf("%s: timeout error\n", __func__);
+			return;
+		}
+		timeout--;
+		udelay(1000);
+	}
+}
+
+static int mmc_core_init(struct mmc *mmc)
+{
+	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	unsigned int mask;
+	debug(" mmc_core_init called\n");
+
+	mmc_reset(host);
+
+	host->version = readw(&host->reg->hcver);
+	debug("host version = %x\n", host->version);
+
+	/* mask all */
+	writel(0xffffffff, &host->reg->norintstsen);
+	writel(0xffffffff, &host->reg->norintsigen);
+
+	writeb(0xe, &host->reg->timeoutcon);	/* TMCLK * 2^27 */
+	/*
+	 * NORMAL Interrupt Status Enable Register init
+	 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
+	 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
+	 * [3] ENSTADMAINT   : DMA boundary interrupt
+	 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
+	 * [0] ENSTACMDCMPLT : Command Complete Status Enable
+	*/
+	mask = readl(&host->reg->norintstsen);
+	mask &= ~(0xffff);
+	mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
+		 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
+		 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
+		 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
+		 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
+	writel(mask, &host->reg->norintstsen);
+
+	/*
+	 * NORMAL Interrupt Signal Enable Register init
+	 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
+	 */
+	mask = readl(&host->reg->norintsigen);
+	mask &= ~(0xffff);
+	mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
+	writel(mask, &host->reg->norintsigen);
+
+	return 0;
+}
+
+int tegra2_mmc_getcd(struct mmc *mmc)
+{
+	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+
+	debug("tegra2_mmc_getcd called\n");
+
+	if (host->cd_gpio >= 0)
+		return !gpio_get_value(host->cd_gpio);
+
+	return 1;
+}
+
+int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+{
+	struct mmc_host *host;
+	char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
+	struct mmc *mmc;
+
+	debug(" tegra2_mmc_init: index %d, bus width %d "
+		"pwr_gpio %d cd_gpio %d\n",
+		dev_index, bus_width, pwr_gpio, cd_gpio);
+
+	host = &mmc_host[dev_index];
+
+	host->clock = 0;
+	host->pwr_gpio = pwr_gpio;
+	host->cd_gpio = cd_gpio;
+	tegra2_get_setup(host, dev_index);
+
+	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
+
+	if (host->pwr_gpio >= 0) {
+		sprintf(gpusage, "SD/MMC%d PWR", dev_index);
+		gpio_request(host->pwr_gpio, gpusage);
+		gpio_direction_output(host->pwr_gpio, 1);
+	}
+
+	if (host->cd_gpio >= 0) {
+		sprintf(gpusage, "SD/MMC%d CD", dev_index);
+		gpio_request(host->cd_gpio, gpusage);
+		gpio_direction_input(host->cd_gpio);
+	}
+
+	mmc = &mmc_dev[dev_index];
+
+	sprintf(mmc->name, "Tegra2 SD/MMC");
+	mmc->priv = host;
+	mmc->send_cmd = mmc_send_cmd;
+	mmc->set_ios = mmc_set_ios;
+	mmc->init = mmc_core_init;
+	mmc->getcd = tegra2_mmc_getcd;
+
+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	if (bus_width == 8)
+		mmc->host_caps = MMC_MODE_8BIT;
+	else
+		mmc->host_caps = MMC_MODE_4BIT;
+	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+
+	/*
+	 * min freq is for card identification, and is the highest
+	 *  low-speed SDIO card frequency (actually 400KHz)
+	 * max freq is highest HS eMMC clock as per the SD/MMC spec
+	 *  (actually 52MHz)
+	 * Both of these are the closest equivalents w/216MHz source
+	 *  clock and Tegra2 SDMMC divisors.
+	 */
+	mmc->f_min = 375000;
+	mmc->f_max = 48000000;
+
+	mmc_register(mmc);
+
+	return 0;
+}
diff --git a/drivers/mmc/tegra_mmc.h b/drivers/mmc/tegra_mmc.h
new file mode 100644
index 00000000000..f9cdcaaaa6d
--- /dev/null
+++ b/drivers/mmc/tegra_mmc.h
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __TEGRA_MMC_H_
+#define __TEGRA_MMC_H_
+
+#define TEGRA2_SDMMC1_BASE	0xC8000000
+#define TEGRA2_SDMMC2_BASE	0xC8000200
+#define TEGRA2_SDMMC3_BASE	0xC8000400
+#define TEGRA2_SDMMC4_BASE	0xC8000600
+
+#ifndef __ASSEMBLY__
+struct tegra2_mmc {
+	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
+	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
+	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
+	unsigned int	argument;	/* _ARGUMENT_0 */
+	unsigned short	trnmod;		/* _CMD_XFER_MODE_0 15:00 xfer mode */
+	unsigned short	cmdreg;		/* _CMD_XFER_MODE_0 31:16 cmd reg */
+	unsigned int	rspreg0;	/* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
+	unsigned int	rspreg1;	/* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
+	unsigned int	rspreg2;	/* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
+	unsigned int	rspreg3;	/* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
+	unsigned int	bdata;		/* _BUFFER_DATA_PORT_0 */
+	unsigned int	prnsts;		/* _PRESENT_STATE_0 */
+	unsigned char	hostctl;	/* _POWER_CONTROL_HOST_0 7:00 */
+	unsigned char	pwrcon;		/* _POWER_CONTROL_HOST_0 15:8 */
+	unsigned char	blkgap;		/* _POWER_CONTROL_HOST_9 23:16 */
+	unsigned char	wakcon;		/* _POWER_CONTROL_HOST_0 31:24 */
+	unsigned short	clkcon;		/* _CLOCK_CONTROL_0 15:00 */
+	unsigned char	timeoutcon;	/* _TIMEOUT_CTRL 23:16 */
+	unsigned char	swrst;		/* _SW_RESET_ 31:24 */
+	unsigned int	norintsts;	/* _INTERRUPT_STATUS_0 */
+	unsigned int	norintstsen;	/* _INTERRUPT_STATUS_ENABLE_0 */
+	unsigned int	norintsigen;	/* _INTERRUPT_SIGNAL_ENABLE_0 */
+	unsigned short	acmd12errsts;	/* _AUTO_CMD12_ERR_STATUS_0 15:00 */
+	unsigned char	res1[2];	/* _RESERVED 31:16 */
+	unsigned int	capareg;	/* _CAPABILITIES_0 */
+	unsigned char	res2[4];	/* RESERVED, offset 44h-47h */
+	unsigned int	maxcurr;	/* _MAXIMUM_CURRENT_0 */
+	unsigned char	res3[4];	/* RESERVED, offset 4Ch-4Fh */
+	unsigned short	setacmd12err;	/* offset 50h */
+	unsigned short	setinterr;	/* offset 52h */
+	unsigned char	admaerr;	/* offset 54h */
+	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
+	unsigned long	admaaddr;	/* offset 58h-5Fh */
+	unsigned char	res5[0x9c];	/* RESERVED, offset 60h-FBh */
+	unsigned short	slotintstatus;	/* offset FCh */
+	unsigned short	hcver;		/* HOST Version */
+	unsigned char	res6[0x100];	/* RESERVED, offset 100h-1FFh */
+};
+
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK				(3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA				(0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT			(2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT			(3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE				(1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE			(1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE		(0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ			(1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT			(1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK			(3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE		(0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136		(1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48		(2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY	(3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK				(1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK			(1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER	(1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD			(1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT			(1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE			(1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE			(1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE			(1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE			(1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE			(1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT			(1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT			(1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT				(1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE			(1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE			(1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT			(1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY		(1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY			(1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
+
+struct mmc_host {
+	struct tegra2_mmc *reg;
+	unsigned int version;	/* SDHCI spec. version */
+	unsigned int clock;	/* Current clock (MHz) */
+	unsigned int base;	/* Base address, SDMMC1/2/3/4 */
+	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
+	int pwr_gpio;		/* Power GPIO */
+	int cd_gpio;		/* Change Detect GPIO */
+};
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __TEGRA_MMC_H_ */
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 88189bedb57..d13ead99098 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -55,7 +55,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index eecfa50e3eb..d3d10550af3 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -45,7 +45,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 3edd102d15d..d6f7fe38a0d 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -42,7 +42,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 18882762368..e73be0bf929 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -45,7 +45,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index db11d8a308c..cae6e2347ec 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -86,7 +86,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 21b9ef234b0..7e6adc74a3f 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -58,7 +58,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 665076d08ec..77a0a141520 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -49,7 +49,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index ec96cff49b2..9dafe5cadca 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -58,7 +58,7 @@
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
 #define CONFIG_DOS_PARTITION
-- 
cgit v1.3.1


From 52a8b82074d1c3a3dcde8e3d90e6a04f7eb3a1f8 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren.nvidia@gmail.com>
Date: Tue, 22 May 2012 12:19:25 +0000
Subject: gpio: tegra2: rename tegra2_gpio.* to tegra_gpio.*

In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra2/gpio.h |   7 +-
 drivers/gpio/Makefile                   |   2 +-
 drivers/gpio/tegra2_gpio.c              | 262 --------------------------------
 drivers/gpio/tegra_gpio.c               | 262 ++++++++++++++++++++++++++++++++
 include/configs/tegra2-common.h         |   4 +-
 5 files changed, 269 insertions(+), 268 deletions(-)
 delete mode 100644 drivers/gpio/tegra2_gpio.c
 create mode 100644 drivers/gpio/tegra_gpio.c

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h
index 41e66fe1b15..40ddb02565a 100644
--- a/arch/arm/include/asm/arch-tegra2/gpio.h
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -2,6 +2,7 @@
  * Copyright (c) 2011, Google Inc. All rights reserved.
  * See file CREDITS for list of people who contributed to this
  * project.
+ * Portions Copyright 2011-2012 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,8 +20,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA2_GPIO_H_
-#define _TEGRA2_GPIO_H_
+#ifndef _TEGRA_GPIO_H_
+#define _TEGRA_GPIO_H_
 
 /*
  * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
@@ -286,4 +287,4 @@ enum gpio_pin {
 void gpio_info(void);
 
 #define gpio_status()	gpio_info()
-#endif	/* TEGRA2_GPIO_H_ */
+#endif	/* TEGRA_GPIO_H_ */
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09ae74c..5ae68d5ba82 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_PCA953X)		+= pca953x.o
 COBJS-$(CONFIG_PCA9698)		+= pca9698.o
 COBJS-$(CONFIG_S5P)		+= s5p_gpio.o
 COBJS-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
-COBJS-$(CONFIG_TEGRA2_GPIO)	+= tegra2_gpio.o
+COBJS-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
 COBJS-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 COBJS-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 COBJS-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
diff --git a/drivers/gpio/tegra2_gpio.c b/drivers/gpio/tegra2_gpio.c
deleted file mode 100644
index 70ca46fae5c..00000000000
--- a/drivers/gpio/tegra2_gpio.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * NVIDIA Tegra2 GPIO handling.
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
- * Tom Warren (twarren@nvidia.com)
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <asm/arch/tegra2.h>
-#include <asm/gpio.h>
-
-enum {
-	TEGRA2_CMD_INFO,
-	TEGRA2_CMD_PORT,
-	TEGRA2_CMD_OUTPUT,
-	TEGRA2_CMD_INPUT,
-};
-
-static struct gpio_names {
-	char name[GPIO_NAME_SIZE];
-} gpio_names[MAX_NUM_GPIOS];
-
-static char *get_name(int i)
-{
-	return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN";
-}
-
-/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
-static int get_config(unsigned gpio)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	u32 u;
-	int type;
-
-	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
-	type =  (u >> GPIO_BIT(gpio)) & 1;
-
-	debug("get_config: port = %d, bit = %d is %s\n",
-		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
-
-	return type;
-}
-
-/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
-static void set_config(unsigned gpio, int type)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	u32 u;
-
-	debug("set_config: port = %d, bit = %d, %s\n",
-		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
-
-	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
-	if (type)				/* GPIO */
-		u |= 1 << GPIO_BIT(gpio);
-	else
-		u &= ~(1 << GPIO_BIT(gpio));
-	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
-}
-
-/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
-static int get_direction(unsigned gpio)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	u32 u;
-	int dir;
-
-	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
-	dir =  (u >> GPIO_BIT(gpio)) & 1;
-
-	debug("get_direction: port = %d, bit = %d, %s\n",
-		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
-
-	return dir;
-}
-
-/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
-static void set_direction(unsigned gpio, int output)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	u32 u;
-
-	debug("set_direction: port = %d, bit = %d, %s\n",
-		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
-
-	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
-	if (output)
-		u |= 1 << GPIO_BIT(gpio);
-	else
-		u &= ~(1 << GPIO_BIT(gpio));
-	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
-}
-
-/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
-static void set_level(unsigned gpio, int high)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	u32 u;
-
-	debug("set_level: port = %d, bit %d == %d\n",
-		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
-
-	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
-	if (high)
-		u |= 1 << GPIO_BIT(gpio);
-	else
-		u &= ~(1 << GPIO_BIT(gpio));
-	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
-}
-
-/*
- * Generic_GPIO primitives.
- */
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	if (gpio >= MAX_NUM_GPIOS)
-		return -1;
-
-	if (label != NULL) {
-		strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE);
-		gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0';
-	}
-
-	/* Configure as a GPIO */
-	set_config(gpio, 1);
-
-	return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
-	if (gpio >= MAX_NUM_GPIOS)
-		return -1;
-
-	gpio_names[gpio].name[0] = '\0';
-	/* Do not configure as input or change pin mux here */
-	return 0;
-}
-
-/* read GPIO OUT value of pin 'gpio' */
-static int gpio_get_output_value(unsigned gpio)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	int val;
-
-	debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n",
-		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
-
-	val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
-
-	return (val >> GPIO_BIT(gpio)) & 1;
-}
-
-/* set GPIO pin 'gpio' as an input */
-int gpio_direction_input(unsigned gpio)
-{
-	debug("gpio_direction_input: pin = %d (port %d:bit %d)\n",
-		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
-
-	/* Configure GPIO direction as input. */
-	set_direction(gpio, 0);
-
-	return 0;
-}
-
-/* set GPIO pin 'gpio' as an output, with polarity 'value' */
-int gpio_direction_output(unsigned gpio, int value)
-{
-	debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n",
-		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio),
-		value ? "HIGH" : "LOW");
-
-	/* Configure GPIO output value. */
-	set_level(gpio, value);
-
-	/* Configure GPIO direction as output. */
-	set_direction(gpio, 1);
-
-	return 0;
-}
-
-/* read GPIO IN value of pin 'gpio' */
-int gpio_get_value(unsigned gpio)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	int val;
-
-	debug("gpio_get_value: pin = %d (port %d:bit %d)\n",
-		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
-
-	val = readl(&bank->gpio_in[GPIO_PORT(gpio)]);
-
-	return (val >> GPIO_BIT(gpio)) & 1;
-}
-
-/* write GPIO OUT value to pin 'gpio' */
-int gpio_set_value(unsigned gpio, int value)
-{
-	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
-		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
-
-	/* Configure GPIO output value. */
-	set_level(gpio, value);
-
-	return 0;
-}
-
-/*
- * Display Tegra GPIO information
- */
-void gpio_info(void)
-{
-	unsigned c;
-	int type;
-
-	for (c = 0; c < MAX_NUM_GPIOS; c++) {
-		type = get_config(c);		/* GPIO, not SFPIO */
-		if (type) {
-			printf("GPIO_%d:\t%s is an %s, ", c,
-				get_name(c),
-				get_direction(c) ? "OUTPUT" : "INPUT");
-			if (get_direction(c))
-				printf("value = %d", gpio_get_output_value(c));
-			else
-				printf("value = %d", gpio_get_value(c));
-			printf("\n");
-		} else
-			continue;
-	}
-}
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
new file mode 100644
index 00000000000..60ec6e3d789
--- /dev/null
+++ b/drivers/gpio/tegra_gpio.c
@@ -0,0 +1,262 @@
+/*
+ * NVIDIA Tegra2 GPIO handling.
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
+ * Tom Warren (twarren@nvidia.com)
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/arch/tegra2.h>
+#include <asm/gpio.h>
+
+enum {
+	TEGRA2_CMD_INFO,
+	TEGRA2_CMD_PORT,
+	TEGRA2_CMD_OUTPUT,
+	TEGRA2_CMD_INPUT,
+};
+
+static struct gpio_names {
+	char name[GPIO_NAME_SIZE];
+} gpio_names[MAX_NUM_GPIOS];
+
+static char *get_name(int i)
+{
+	return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN";
+}
+
+/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
+static int get_config(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+	int type;
+
+	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
+	type =  (u >> GPIO_BIT(gpio)) & 1;
+
+	debug("get_config: port = %d, bit = %d is %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
+
+	return type;
+}
+
+/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
+static void set_config(unsigned gpio, int type)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+
+	debug("set_config: port = %d, bit = %d, %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
+
+	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
+	if (type)				/* GPIO */
+		u |= 1 << GPIO_BIT(gpio);
+	else
+		u &= ~(1 << GPIO_BIT(gpio));
+	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
+}
+
+/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
+static int get_direction(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+	int dir;
+
+	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
+	dir =  (u >> GPIO_BIT(gpio)) & 1;
+
+	debug("get_direction: port = %d, bit = %d, %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
+
+	return dir;
+}
+
+/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
+static void set_direction(unsigned gpio, int output)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+
+	debug("set_direction: port = %d, bit = %d, %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
+
+	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
+	if (output)
+		u |= 1 << GPIO_BIT(gpio);
+	else
+		u &= ~(1 << GPIO_BIT(gpio));
+	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
+}
+
+/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
+static void set_level(unsigned gpio, int high)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+
+	debug("set_level: port = %d, bit %d == %d\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
+
+	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
+	if (high)
+		u |= 1 << GPIO_BIT(gpio);
+	else
+		u &= ~(1 << GPIO_BIT(gpio));
+	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
+}
+
+/*
+ * Generic_GPIO primitives.
+ */
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	if (gpio >= MAX_NUM_GPIOS)
+		return -1;
+
+	if (label != NULL) {
+		strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE);
+		gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0';
+	}
+
+	/* Configure as a GPIO */
+	set_config(gpio, 1);
+
+	return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+	if (gpio >= MAX_NUM_GPIOS)
+		return -1;
+
+	gpio_names[gpio].name[0] = '\0';
+	/* Do not configure as input or change pin mux here */
+	return 0;
+}
+
+/* read GPIO OUT value of pin 'gpio' */
+static int gpio_get_output_value(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	int val;
+
+	debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
+
+	val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
+
+	return (val >> GPIO_BIT(gpio)) & 1;
+}
+
+/* set GPIO pin 'gpio' as an input */
+int gpio_direction_input(unsigned gpio)
+{
+	debug("gpio_direction_input: pin = %d (port %d:bit %d)\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
+
+	/* Configure GPIO direction as input. */
+	set_direction(gpio, 0);
+
+	return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+int gpio_direction_output(unsigned gpio, int value)
+{
+	debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio),
+		value ? "HIGH" : "LOW");
+
+	/* Configure GPIO output value. */
+	set_level(gpio, value);
+
+	/* Configure GPIO direction as output. */
+	set_direction(gpio, 1);
+
+	return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+int gpio_get_value(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	int val;
+
+	debug("gpio_get_value: pin = %d (port %d:bit %d)\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
+
+	val = readl(&bank->gpio_in[GPIO_PORT(gpio)]);
+
+	return (val >> GPIO_BIT(gpio)) & 1;
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+int gpio_set_value(unsigned gpio, int value)
+{
+	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
+
+	/* Configure GPIO output value. */
+	set_level(gpio, value);
+
+	return 0;
+}
+
+/*
+ * Display Tegra GPIO information
+ */
+void gpio_info(void)
+{
+	unsigned c;
+	int type;
+
+	for (c = 0; c < MAX_NUM_GPIOS; c++) {
+		type = get_config(c);		/* GPIO, not SFPIO */
+		if (type) {
+			printf("GPIO_%d:\t%s is an %s, ", c,
+				get_name(c),
+				get_direction(c) ? "OUTPUT" : "INPUT");
+			if (get_direction(c))
+				printf("value = %d", gpio_get_output_value(c));
+			else
+				printf("value = %d", gpio_get_value(c));
+			printf("\n");
+		} else
+			continue;
+	}
+}
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index a4146a50c6c..94e1aa628d4 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -190,6 +190,6 @@
 						CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_TEGRA2_GPIO
+#define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_GPIO
 #endif /* __TEGRA2_COMMON_H */
-- 
cgit v1.3.1


From a5c168c6d6699e050c9333c03a4d53d62eb7949b Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 24 May 2012 11:38:37 +0000
Subject: tegra: trimslice: store environment in SPI flash

The chosen flash offset matches Compulab's downstream U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/trimslice.h | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 7e6adc74a3f..915b07ae23b 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -47,6 +47,14 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
+/* SPI */
+#define CONFIG_TEGRA_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
 /* I2C */
 #define CONFIG_TEGRA_I2C
 #define CONFIG_SYS_I2C_INIT_BOARD
@@ -66,8 +74,12 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* Environment in SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		48000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		(512 * 1024)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
-- 
cgit v1.3.1


From e87c2bda9c45bcfcc8239f6052d6fa9aec7351d6 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 24 May 2012 11:38:38 +0000
Subject: tegra: paz00: store environment in eMMC

Store the environment in eMMC, at the end of the second boot sector.
This should not conflict with any other eMMC usage: U-Boot is stored
well below this location, and the kernel only uses the general area
of the eMMC once booted, not the boot sectors.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/paz00.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index d6f7fe38a0d..29c368a99e0 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -50,8 +50,10 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
-- 
cgit v1.3.1


From f9f2f12e2cace3685ea0dbb6b6d78789fb75f043 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 24 May 2012 11:38:39 +0000
Subject: tegra: seaboard: disable SPI, move environment to eMMC

The SPI hardware on Seaboard is too broken to use; it is muxed with the
console UART and requires evil interactions between the SPI and UART
drivers to work even partially. The current code in U-Boot is not
sufficient to make this work correctly; auto boot is aborted due to
corruption in the UART RX channel interrupting it.

Instead, move the environment to eMMC, at the end of the second boot
sector. This should not conflict with any other eMMC usage, irrespective
of whether the board boots from SPI, NAND, or eMMC: if U-Boot is stored
in eMMC, it will be stored well below this location. The kernel only
uses the general area of the eMMC once booted, not the boot sectors.

Boards that are derivatives of Seaboard don't have the muxing issue,
and should/could have a separate U-Boot configuration file that does
enable SPI if desired.

Alternatively, the environment could be stored in NAND flash, but we
currently have no driver for that controller.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/seaboard.h | 29 ++++-------------------------
 1 file changed, 4 insertions(+), 25 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index cae6e2347ec..537ab0e71cd 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -51,30 +51,12 @@
 
 /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
 #define CONFIG_UART_DISABLE_GPIO	GPIO_PI3
-/*
- * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are
- * needed to work around that design error.
- */
-#define CONFIG_SPI_UART_SWITCH
-#define CONFIG_SPI_CORRUPTS_UART	NV_PA_APB_UARTD_BASE
-#define CONFIG_SPI_CORRUPTS_UART_NR	3
-#define CONFIG_SPI_CORRUPTS_UART_DLY	2500
-#undef CONFIG_CMDLINE_EDITING		/* avoid NUL in input buffer */
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
 #define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
-/* SPI */
-#define CONFIG_TEGRA_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
-
 /* I2C */
 #define CONFIG_TEGRA_I2C
 #define CONFIG_SYS_I2C_INIT_BOARD
@@ -94,13 +76,10 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment in SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MAX_HZ		48000000
-#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
-
-#define CONFIG_ENV_SECT_SIZE    CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET       (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
-- 
cgit v1.3.1


From 76e350b7a3c568c8d27cf72f98036ec3ddb64f31 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren@nvidia.com>
Date: Wed, 30 May 2012 14:06:09 -0700
Subject: arm: Tegra: Use ODMDATA from BCT in IRAM

Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.

Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
---
 arch/arm/cpu/armv7/tegra2/ap20.c          | 22 +++++++++++++++++++++-
 arch/arm/include/asm/arch-tegra2/tegra2.h |  4 ++++
 include/configs/harmony.h                 |  1 -
 include/configs/medcom.h                  |  1 -
 include/configs/paz00.h                   |  1 -
 include/configs/plutux.h                  |  1 -
 include/configs/seaboard.h                |  1 -
 include/configs/trimslice.h               |  1 -
 include/configs/ventana.h                 |  1 -
 include/configs/whistler.h                |  1 -
 10 files changed, 25 insertions(+), 9 deletions(-)

(limited to 'include/configs')

diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 24e582d95cc..1aad3879ee1 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -314,9 +314,28 @@ void enable_scu(void)
 	writel(reg, &scu->scu_ctrl);
 }
 
+static u32 get_odmdata(void)
+{
+	/*
+	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
+	 * The BCT start and size are stored in the BIT in IRAM.
+	 * Read the data @ bct_start + (bct_size - 12). This works
+	 * on T20 and T30 BCTs, which are locked down. If this changes
+	 * in new chips (T114, etc.), we can revisit this algorithm.
+	 */
+
+	u32 bct_start, odmdata;
+
+	bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+	odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+	return odmdata;
+}
+
 void init_pmc_scratch(void)
 {
 	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+	u32 odmdata;
 	int i;
 
 	/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@@ -324,7 +343,8 @@ void init_pmc_scratch(void)
 		writel(0, &pmc->pmc_scratch1+i);
 
 	/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
-	writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+	odmdata = get_odmdata();
+	writel(odmdata, &pmc->pmc_scratch20);
 
 #ifdef CONFIG_TEGRA2_LP0
 	/* save Sdram params to PMC 2, 4, and 24 for WB0 */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index d4ada10ea8c..3c8d8a84b55 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -60,6 +60,10 @@ struct timerus {
 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
 #define AP20_WB_RUN_ADDRESS	0x40020000
 
+#define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
+#define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
+
 /* These are the available SKUs (product types) for Tegra */
 enum {
 	SKU_ID_T20		= 0x8,
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d13ead99098..df5265a5a0d 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -48,7 +48,6 @@
 #endif
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_HARMONY
-#define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index d3d10550af3..bdea7c9c531 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -31,7 +31,6 @@
 /* High-level configuration options */
 #define V_PROMPT			"Tegra2 (Medcom) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"Avionic Design Medcom"
-#define CONFIG_SYS_BOARD_ODMDATA	0x2b0d8011
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 29c368a99e0..0dd1e83a504 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
-#define CONFIG_SYS_BOARD_ODMDATA	0x800c0085 /* lp1, 512MB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index e73be0bf929..6397eb104a6 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -31,7 +31,6 @@
 /* High-level configuration options */
 #define V_PROMPT			"Tegra2 (Plutux) # "
 #define CONFIG_TEGRA2_BOARD_STRING	"Avionic Design Plutux"
-#define CONFIG_SYS_BOARD_ODMDATA	0x2b2d8011
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 537ab0e71cd..f661583fed6 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -53,7 +53,6 @@
 #define CONFIG_UART_DISABLE_GPIO	GPIO_PI3
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
-#define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 915b07ae23b..91de348d59e 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -43,7 +43,6 @@
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_TRIMSLICE
-#define CONFIG_SYS_BOARD_ODMDATA	0x300c0011 /* lp?, 1GB, UARTA */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 77a0a141520..5e4d53861c6 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
-#define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 9dafe5cadca..f2952d5f45e 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -43,7 +43,6 @@
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_WHISTLER
-#define CONFIG_SYS_BOARD_ODMDATA	0x2B080105 /* lp?, 512MB, UARTA */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
-- 
cgit v1.3.1


From 1e7e716e80f7a8f599390dd5aa4ae7dce465a1da Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 30 May 2012 06:45:50 +0000
Subject: tegra: trimslice: fix a couple typos

Fix the .dts file USB unit addresses not to duplicate each-other.

Fix the board name string to indicate the vendor is Compulab not NVIDIA.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
---
 board/compulab/dts/tegra2-trimslice.dts | 2 +-
 include/configs/trimslice.h             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra2-trimslice.dts
index c707eb84ec2..db79e7796d0 100644
--- a/board/compulab/dts/tegra2-trimslice.dts
+++ b/board/compulab/dts/tegra2-trimslice.dts
@@ -47,7 +47,7 @@
 		status = "disabled";
 	};
 
-	usb@c5004000 {
+	usb@c5000000 {
 		status = "disabled";
 	};
 
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 91de348d59e..34be8a98a1c 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -34,7 +34,7 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra2 (TrimSlice) # "
-#define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Trimslice"
+#define CONFIG_TEGRA2_BOARD_STRING	"Compulab Trimslice"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-- 
cgit v1.3.1


From d1df0fd37388fe0dc77a75f5aece04f70cc3f7e6 Mon Sep 17 00:00:00 2001
From: Thomas Weber <thomas@tomweber.eu>
Date: Mon, 14 May 2012 10:28:54 +0000
Subject: omap4/5: Use CPUDIR for .lds script

Signed-off-by: Thomas Weber <thomas@tomweber.eu>
---
 include/configs/omap4_common.h | 2 +-
 include/configs/omap5_evm.h    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 84481420e48..e7a3de5a667 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -281,7 +281,7 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 #define CONFIG_SYS_ENABLE_PADS_ALL
 
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
index 60c7a291c02..837838700aa 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -261,7 +261,7 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 /*
  * 64 bytes before this address should be set aside for u-boot.img's
-- 
cgit v1.3.1


From 14b9f16c401206097c361ae4198c6b2ece805964 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 14 May 2012 20:24:14 +0000
Subject: arm,davinci: update for enbw_cmc board

- change gpio pin settings:

  - gpio pin 6[13] (PLC reset) default value low
  - gpio pin 6[0] (TPM reset) default value low
  - 4 new GPIO pins
      pin  i/o   name
    - 3[9] input Board Type
    - 2[7] input HW-ID0
    - 2[6] input HW-ID1
    - 2[3] input HW-ID2

- read board type and hw id from gpio pins on the enbw_cmc board,
  and use board type for setting up different gpio pin settings.

- do not pass "davinci_mmc.use_dma=0" to linux, as MMC now
  works with DMA.

- update logbuf support:
  store post word in RTC scratch register

- add support for configuring KSZ8864RMN switch through
  a config file on u-boot startup. For more infos see:
  doc/README.switch_config

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
 board/enbw/enbw_cmc/enbw_cmc.c | 347 ++++++++++++++++++++++++++++++++++++++---
 doc/README.switch_config       |  25 +++
 include/configs/enbw_cmc.h     |  20 ++-
 3 files changed, 364 insertions(+), 28 deletions(-)
 create mode 100644 doc/README.switch_config

(limited to 'include/configs')

diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
index 6c0d931eea0..0874e9c4e8c 100644
--- a/board/enbw/enbw_cmc/enbw_cmc.c
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -35,6 +35,8 @@
 #include <mmc.h>
 #include <net.h>
 #include <netdev.h>
+#include <spi.h>
+#include <linux/ctype.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/da850_lowlevel.h>
@@ -86,16 +88,22 @@ static const struct pinmux_config enbw_pins[] = {
 	{ pinmux(5), 1, 0 },
 	{ pinmux(5), 1, 3 },
 	{ pinmux(5), 1, 7 },
-	{ pinmux(6), 1, 0 },
-	{ pinmux(6), 1, 1 },
+	{ pinmux(5), 1, 5 },
+	{ pinmux(5), 1, 4 },
+	{ pinmux(5), 1, 3 },
+	{ pinmux(5), 1, 2 },
+	{ pinmux(5), 1, 1 },
+	{ pinmux(5), 1, 0 },
+	{ pinmux(6), 8, 0 },
+	{ pinmux(6), 8, 1 },
 	{ pinmux(6), 8, 2 },
 	{ pinmux(6), 8, 3 },
-	{ pinmux(6), 1, 4 },
+	{ pinmux(6), 8, 4 },
 	{ pinmux(6), 8, 5 },
 	{ pinmux(6), 1, 7 },
 	{ pinmux(7), 8, 2 },
 	{ pinmux(7), 1, 3 },
-	{ pinmux(7), 1, 6 },
+	{ pinmux(7), 8, 6 },
 	{ pinmux(7), 1, 7 },
 	{ pinmux(13), 8, 2 },
 	{ pinmux(13), 8, 3 },
@@ -163,24 +171,37 @@ struct gpio_config {
 	unsigned char value;
 };
 
-static const struct gpio_config enbw_gpio_config[] = {
+static const struct gpio_config enbw_gpio_config_hut[] = {
+	{ "RS485 enable",	8, 11, 1, 0 },
+	{ "RS485 iso",		8, 10, 1, 1 },
+	{ "W2HUT RS485 Rx ena",	8,  9, 1, 0 },
+	{ "W2HUT RS485 iso",	8,  8, 1, 1 },
+};
+
+static const struct gpio_config enbw_gpio_config_w[] = {
 	{ "RS485 enable",	8, 11, 1, 0 },
 	{ "RS485 iso",		8, 10, 1, 0 },
 	{ "W2HUT RS485 Rx ena",	8,  9, 1, 0 },
 	{ "W2HUT RS485 iso",	8,  8, 1, 0 },
+};
+
+static const struct gpio_config enbw_gpio_config[] = {
 	{ "LAN reset",		7, 15, 1, 1 },
 	{ "ena 11V PLC",	7, 14, 1, 0 },
 	{ "ena 1.5V PLC",	7, 13, 1, 0 },
 	{ "disable VBUS",	7, 12, 1, 1 },
-	{ "PLC reset",		6, 13, 1, 1 },
+	{ "PLC reset",		6, 13, 1, 0 },
 	{ "LCM RS",		6, 12, 1, 0 },
 	{ "LCM R/W",		6, 11, 1, 0 },
 	{ "PLC pairing",	6, 10, 1, 1 },
 	{ "PLC MDIO CLK",	6,  9, 1, 0 },
 	{ "HK218",		6,  8, 1, 0 },
 	{ "HK218 Rx",		6,  1, 1, 1 },
-	{ "TPM reset",		6,  0, 1, 1 },
-	{ "LCM E",		2,  2, 1, 1 },
+	{ "TPM reset",		6,  0, 1, 0 },
+	{ "Board-Type",		3,  9, 0, 0 },
+	{ "HW-ID0",		2,  7, 0, 0 },
+	{ "HW-ID1",		2,  6, 0, 0 },
+	{ "HW-ID2",		2,  3, 0, 0 },
 	{ "PV-IF RxD ena",	0, 15, 1, 1 },
 	{ "LED1",		1, 15, 1, 1 },
 	{ "LED2",		0,  1, 1, 1 },
@@ -229,34 +250,57 @@ static void enbw_cmc_switch(int port, int on)
 	}
 }
 
-int board_init(void)
+static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz)
 {
 	int i, ret;
 
-#ifndef CONFIG_USE_IRQ
-	irq_init();
-#endif
-	/* address of boot parameters, not used as booting with DTT */
-	gd->bd->bi_boot_params = 0;
+	for (i = 0; i < sz; i++) {
+		int gpio = conf[i].bank * 16 +
+			conf[i].gpio;
 
-	for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) {
-		int gpio = enbw_gpio_config[i].bank * 16 +
-			enbw_gpio_config[i].gpio;
-
-		ret = gpio_request(gpio, enbw_gpio_config[i].name);
+		ret = gpio_request(gpio, conf[i].name);
 		if (ret) {
 			printf("%s: Could not get %s gpio\n", __func__,
-				enbw_gpio_config[i].name);
-			return -1;
+				conf[i].name);
+			return ret;
 		}
 
-		if (enbw_gpio_config[i].out)
+		if (conf[i].out)
 			gpio_direction_output(gpio,
-				enbw_gpio_config[i].value);
+				conf[i].value);
 		else
 			gpio_direction_input(gpio);
 	}
 
+	return 0;
+}
+
+int board_init(void)
+{
+	int board_type, hw_id;
+
+#ifndef CONFIG_USE_IRQ
+	irq_init();
+#endif
+	/* address of boot parameters, not used as booting with DTT */
+	gd->bd->bi_boot_params = 0;
+
+	enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config));
+
+	/* detect HW version */
+	board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE);
+	hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) +
+		(gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) +
+		(gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2);
+	printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"),
+		hw_id);
+	if (board_type)
+		enbw_cmc_init_gpio(enbw_gpio_config_w,
+			ARRAY_SIZE(enbw_gpio_config_w));
+	else
+		enbw_cmc_init_gpio(enbw_gpio_config_hut,
+			ARRAY_SIZE(enbw_gpio_config_hut));
+
 	/* setup the SUSPSRC for ARM to control emulation suspend */
 	clrbits_le32(&davinci_syscfg_regs->suspsrc,
 		(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
@@ -267,14 +311,231 @@ int board_init(void)
 }
 
 #ifdef CONFIG_DRIVER_TI_EMAC
+
+#define KSZ_CMD_READ	0x03
+#define KSZ_CMD_WRITE	0x02
+#define KSZ_ID		0x95
+
+static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val)
+{
+	unsigned long flags = SPI_XFER_BEGIN;
+	int ret;
+	int cmd_len;
+	u8 cmd[2];
+
+	cmd[0] = KSZ_CMD_READ;
+	cmd[1] = reg;
+	cmd_len = 2;
+
+	ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+	if (ret) {
+		debug("Failed to send command (%zu bytes): %d\n",
+				cmd_len, ret);
+		return -EINVAL;
+	}
+	flags |= SPI_XFER_END;
+	*val = 0;
+	cmd_len = 1;
+	ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags);
+	if (ret) {
+		debug("Failed to read (%zu bytes): %d\n",
+				cmd_len, ret);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int enbw_cmc_switch_read_ident(struct spi_slave *spi)
+{
+	int ret;
+	u8 val;
+
+	ret = enbw_cmc_switch_read(spi, 0, &val);
+	if (ret) {
+		debug("Failed to read\n");
+		return -EINVAL;
+	}
+
+	if (val != KSZ_ID)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg,
+		unsigned long val)
+{
+	unsigned long flags = SPI_XFER_BEGIN;
+	int ret;
+	int cmd_len;
+	u8 cmd[3];
+
+	cmd[0] = KSZ_CMD_WRITE;
+	cmd[1] = reg;
+	cmd[2] = val;
+	cmd_len = 3;
+	flags |= SPI_XFER_END;
+
+	ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+	if (ret) {
+		debug("Failed to send command (%zu bytes): %d\n",
+				cmd_len, ret);
+		return -EINVAL;
+	}
+
+	udelay(1000);
+	ret = enbw_cmc_switch_read(spi, reg, &cmd[0]);
+	if (ret) {
+		debug("Failed to read\n");
+		return -EINVAL;
+	}
+	if (val != cmd[0])
+		debug("warning: reg: %lx va: %x soll: %lx\n",
+			reg, cmd[0], val);
+
+	return 0;
+}
+
+static int enbw_cmc_eof(unsigned char *ptr)
+{
+	if (*ptr == 0xff)
+		return 1;
+
+	return 0;
+}
+
+static char *enbw_cmc_getnewline(char *ptr)
+{
+	while (*ptr != 0x0a) {
+		ptr++;
+		if (enbw_cmc_eof((unsigned char *)ptr))
+			return NULL;
+	}
+
+	ptr++;
+	return ptr;
+}
+
+static char *enbw_cmc_getvalue(char *ptr, int *value)
+{
+	int	end = 0;
+
+	*value = -EINVAL;
+
+	if (!isxdigit(*ptr))
+		end = 1;
+
+	while (end) {
+		if ((*ptr == '#') || (*ptr == ';')) {
+			ptr = enbw_cmc_getnewline(ptr);
+			return ptr;
+		}
+		if (ptr != NULL) {
+			if (isxdigit(*ptr)) {
+				end = 0;
+			} else if (*ptr == 0x0a) {
+				ptr++;
+				return ptr;
+			} else {
+				ptr++;
+				if (enbw_cmc_eof((unsigned char *)ptr))
+					return NULL;
+			}
+		} else {
+			return NULL;
+		}
+	}
+	*value = (int)simple_strtoul((const char *)ptr, &ptr, 16);
+	ptr++;
+	return ptr;
+}
+
+static int enbw_cmc_config_switch(unsigned long addr)
+{
+	struct spi_slave *spi;
+	char *ptr = (char *)addr;
+	int value, reg;
+	int ret;
+	int bus, cs, max_hz, spi_mode;
+
+	debug("configure switch with file on addr: 0x%lx\n", addr);
+
+	bus = 0;
+	cs = 0;
+	max_hz = 1000000;
+	spi_mode = 0;
+
+	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+	if (!spi) {
+		printf("Failed to set up slave\n");
+		return -EINVAL;
+	}
+
+	ret = spi_claim_bus(spi);
+	if (ret) {
+		debug("Failed to claim SPI bus: %d\n", ret);
+		goto err_claim_bus;
+	}
+
+	ret = enbw_cmc_switch_read_ident(spi);
+	if (ret)
+		goto err_claim_bus;
+
+	ptr = (char *)addr;
+	while (ptr != NULL) {
+		ptr = enbw_cmc_getvalue(ptr, &reg);
+		if (ptr != NULL) {
+			ptr = enbw_cmc_getvalue(ptr, &value);
+			if ((ptr != NULL) && (value >= 0))
+				if (enbw_cmc_switch_write(spi, reg, value))
+					goto err_read;
+		}
+	}
+	return 0;
+
+err_read:
+	spi_release_bus(spi);
+err_claim_bus:
+	spi_free_slave(spi);
+	return -EINVAL;
+}
+
+static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	unsigned long addr;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+	enbw_cmc_config_switch(addr);
+
+	return 0;
+}
+
+U_BOOT_CMD(switch, 3, 1, do_switch,
+	"switch addr",
+	"[addr]"
+);
+
 /*
  * Initializes on-board ethernet controllers.
  */
 int board_eth_init(bd_t *bis)
 {
-#ifdef CONFIG_DRIVER_TI_EMAC
+	const char *s;
+	size_t len;
+
 	davinci_emac_mii_mode_sel(0);
-#endif /* CONFIG_DRIVER_TI_EMAC */
+
+	/* send a config file to the switch */
+	s = hwconfig_subarg("switch", "config", &len);
+	if (len) {
+		unsigned long addr = simple_strtoul(s, NULL, 16);
+
+		enbw_cmc_config_switch(addr);
+	}
 
 	if (!davinci_emac_initialize()) {
 		printf("Error: Ethernet init failed!\n");
@@ -546,6 +807,29 @@ ulong bootcount_load(void)
 }
 #endif
 
+ulong post_word_load(void)
+{
+	struct davinci_rtc *reg =
+		(struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
+
+	return in_be32(&reg->scratch2);
+}
+
+void post_word_store(ulong value)
+{
+	struct davinci_rtc *reg =
+		(struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
+
+	/*
+	 * write RTC kick register to enable write
+	 * for RTC Scratch registers. Cratch0 and 1 are
+	 * used for bootcount values.
+	 */
+	writel(RTC_KICK0R_WE, &reg->kick0r);
+	writel(RTC_KICK1R_WE, &reg->kick1r);
+	out_be32(&reg->scratch2, value);
+}
+
 void board_gpio_init(void)
 {
 	struct davinci_gpio *gpio = davinci_gpio_bank01;
@@ -558,6 +842,19 @@ void board_gpio_init(void)
 	clrbits_le32(&gpio->out_data, 0x8000407e);
 	/* set LED 1 - 5 to state on */
 	setbits_le32(&gpio->out_data, 0x8000001e);
+
+	/*
+	 * set some gpio pins to low, this is needed early,
+	 * so we have no gpio Interface here
+	 * gpios:
+	 * 8[8]  Mode PV select  low
+	 * 8[9]  Debug Rx Enable low
+	 * 8[10] Mode Select PV  low
+	 * 8[11] Counter Interface RS485 Rx-Enable low
+	 */
+	gpio = davinci_gpio_bank8;
+	clrbits_le32(&gpio->dir, 0x00000f00);
+	clrbits_le32(&gpio->out_data, 0x0f00);
 }
 
 int board_late_init(void)
diff --git a/doc/README.switch_config b/doc/README.switch_config
new file mode 100644
index 00000000000..f8903738e1f
--- /dev/null
+++ b/doc/README.switch_config
@@ -0,0 +1,25 @@
+On the enbw_cmc board is a KSZ8864RMN switch which needs
+configured through spi before working. This is done on
+startup from u-boot through a config file stored at an
+address specified in the "hwconfig" environment variable,
+subcommand "config".
+
+For example on the enbw_cmc board:
+
+hwconfig=switch:lan=on,pwl=off,config=0x60160000
+
+The file has the following structure:
+
+- a comment starts with a '#' or a ';' and ends with a newline
+- The switch needs for its config a reg/value pair, so we
+  have two columns in the file:
+    reg  : contains the register address
+    value: contains a 8 bit register value
+  This 2 columns are seperated through space or tab.
+
+example (minimal configuration on the enbw_cmc board):
+
+;reg    value   comment
+;-----------------------------------------
+0x01	0x00
+0x01	0x01    ; Start Switch with this configuration
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index c1a0f6a7701..3fc07e672aa 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -101,6 +101,14 @@
 #define CONFIG_SYS_DTT_LOW_TEMP	-30
 #define CONFIG_SYS_DTT_HYSTERESIS	3
 
+/*
+ * SPI Configuration
+ */
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_CMD_SPI
+
 /*
  * Flash & Environment
  */
@@ -225,9 +233,9 @@
 	"key_magic_2=2\0"						\
 	"key_magic_3=3\0"						\
 	"magic_keys=0123\0"						\
-	"hwconfig=switch:lan=on,pwl=off\0"				\
+	"hwconfig=switch:lan=on,pwl=off,config=0x60100000\0"		\
 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0"	\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
 	"mtdids=" MTDIDS_DEFAULT "\0"					\
 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
 	"logversion=2\0"						\
@@ -336,6 +344,11 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MMC
 
+/* GPIO */
+#define CONFIG_ENBW_CMC_BOARD_TYPE	57
+#define CONFIG_ENBW_CMC_HW_ID_BIT0	39
+#define CONFIG_ENBW_CMC_HW_ID_BIT1	38
+#define CONFIG_ENBW_CMC_HW_ID_BIT2	35
 
 /* FDT support */
 #define CONFIG_OF_LIBFDT
@@ -438,7 +451,8 @@
 #define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
 
 #define CONFIG_POST	(CONFIG_SYS_POST_MEMORY)
-#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
 #define CONFIG_LOGBUFFER
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-- 
cgit v1.3.1


From 1dd07fe8e9ba4e0ae449faf871bb81ebd36c62a9 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@ti.com>
Date: Mon, 21 May 2012 11:20:44 +0000
Subject: OMAP3 Beagle: Set BOOTDELAY to 3

We change the bootdelay to give users a little bit longer to break in if
needed.

Signed-off-by: Tom Rini <trini@ti.com>
---
 include/configs/omap3_beagle.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 268215cb867..c10ac82dcd9 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -213,7 +213,7 @@
 							/* partition */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY		2
+#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x80200000\0" \
-- 
cgit v1.3.1


From 2e4b8b5cd282515d496f5a5b30f5a9c037b70fce Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@ti.com>
Date: Mon, 21 May 2012 11:20:45 +0000
Subject: omap3evm: Set BOOTDELAY to 3

We reduce the bootdelay from 10s to 3s to give users a short but usable
window to interrupt the boot process if needed.

Signed-off-by: Tom Rini <trini@ti.com>
---
 include/configs/omap3_evm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 1fcb7af9fe2..fb3bf34b95b 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -134,7 +134,7 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	10
+#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
-- 
cgit v1.3.1


From 776bebb75875dee80401ce098d06d7728c1e4a89 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@ti.com>
Date: Mon, 21 May 2012 11:20:46 +0000
Subject: omap3_beagle: Add CONFIG_CMD_ASKENV

Signed-off-by: Tom Rini <trini@ti.com>
---
 include/configs/omap3_beagle.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index c10ac82dcd9..657780edcff 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -146,6 +146,8 @@
 /* commands to include */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_ASKENV
+
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
-- 
cgit v1.3.1


From 1ee6d31ff4a0cff3176f722ead734f31e58d0c26 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@ti.com>
Date: Mon, 21 May 2012 11:20:47 +0000
Subject: omap3evm: Add CONFIG_CMD_ASKENV

Signed-off-by: Tom Rini <trini@ti.com>
---
 include/configs/omap3_evm.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index fb3bf34b95b..632a13fa9f9 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -42,6 +42,8 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_ASKENV
+
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
-- 
cgit v1.3.1


From 390cdcda1b1d07eb054120e9bdfc4374b6ef8f6e Mon Sep 17 00:00:00 2001
From: Igor Grinberg <grinberg@compulab.co.il>
Date: Thu, 24 May 2012 04:01:21 +0000
Subject: cm-t35: reduce the environment size

Reduce the environment size (128KB => 16KB) to improve the environment
operations time (e.g. reading, ecc calculation).
Also, remove the unused CONFIG_SYS_ENV_SECT_SIZE.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
---
 include/configs/cm_t35.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 782d28c55d0..b97e8871502 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -77,7 +77,7 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
 					/* Sector */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
 
@@ -315,7 +315,6 @@
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
-- 
cgit v1.3.1


From eae08eb2b53ffb87f3342e45ab422d8625659fcd Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Tue, 29 May 2012 05:54:39 +0000
Subject: mx53loco: Fix revision of Dialog boards

Original code was assuming that the fuse revision version for all mx53loco boards
based on Dialog PMIC was the same, which is not the case.

Force the revision of all Dialog-based boards to 0.

This fixes a kernel crash when PMIC is accessed in the 2.6.35 kernel
for Dialog rev E boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 board/freescale/mx53loco/mx53loco.c | 12 +++++++-----
 include/configs/mx53loco.h          |  1 -
 2 files changed, 7 insertions(+), 6 deletions(-)

(limited to 'include/configs')

diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index d8e027ce663..cbdcfadf279 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -75,6 +75,9 @@ u32 get_board_rev(void)
 
 	int rev = readl(&fuse->gp[6]);
 
+	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+		rev = 0;
+
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
 
@@ -495,11 +498,6 @@ int print_cpuinfo(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-	setup_iomux_i2c();
-	if (!power_init())
-		clock_1GHz();
-	print_cpuinfo();
-
 	setenv("stdout", "serial");
 
 	return 0;
@@ -511,6 +509,10 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
 	mxc_set_sata_internal_clock();
+	setup_iomux_i2c();
+	if (!power_init())
+		clock_1GHz();
+	print_cpuinfo();
 
 	lcd_enable();
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 8b4e00855d2..b63d37d55f9 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 #define CONFIG_REVISION_TAG
 
-- 
cgit v1.3.1


From 212033fc9a6bb10e97712e309fc53c9316acdaa8 Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Sat, 12 May 2012 13:40:15 +0000
Subject: m28evk: fix board config include guardian macro name

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
---
 include/configs/m28evk.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 3abaadc877f..6cefaa43abc 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -17,8 +17,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-#ifndef __M28_H__
-#define __M28_H__
+#ifndef __M28EVK_CONFIG_H__
+#define __M28EVK_CONFIG_H__
 
 #include <asm/arch/regs-base.h>
 
@@ -325,4 +325,4 @@
 		"fi ; "							\
 		"fi\0"
 
-#endif /* __M28_H__ */
+#endif /* __M28EVK_CONFIG_H__ */
-- 
cgit v1.3.1


From 3b4efee97c50b5fb85890498034ced32668e0809 Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Sat, 12 May 2012 13:40:13 +0000
Subject: mx28evk: ensure command definition is in alphabetic order

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx28evk.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 51b172ddb4e..8d44380a1e9 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -54,11 +54,11 @@
 #include <config_cmd_default.h>
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-- 
cgit v1.3.1


From 606de8b6a606823366fb7b59555446cb18fd28ec Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Sat, 12 May 2012 13:40:16 +0000
Subject: mx28evk: fix board config include guardian macro name

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx28evk.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 8d44380a1e9..640dcb4be7c 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -16,8 +16,8 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  */
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __MX28EVK_CONFIG_H__
+#define __MX28EVK_CONFIG_H__
 
 #include <asm/arch/regs-base.h>
 
@@ -250,4 +250,4 @@
 		"run netargs; " \
 		"dhcp ${uimage}; bootm\0" \
 
-#endif /* __CONFIG_H */
+#endif /* __MX28EVK_CONFIG_H__ */
-- 
cgit v1.3.1


From a2277e84036fb22aac44e83a391431539086f110 Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Tue, 15 May 2012 10:59:30 +0000
Subject: m28evk: drop duplicated definition of CONFIG_OF_LIBFDT

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
---
 include/configs/m28evk.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 6cefaa43abc..156af27a863 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -43,8 +43,6 @@
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_ARCH_MISC_INIT
 
-#define CONFIG_OF_LIBFDT
-
 /*
  * SPL
  */
-- 
cgit v1.3.1


From be8d6b614f0868fe3b92dff4e00bd9f3458d9e8c Mon Sep 17 00:00:00 2001
From: Otavio Salvador <otavio@ossystems.com.br>
Date: Sat, 12 May 2012 13:40:11 +0000
Subject: m28evk: use same notation to alloc the 128kB stack

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Wolfgang Denk <wd@denx.de>
---
 include/configs/m28evk.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 156af27a863..a0e90ca694a 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -86,7 +86,7 @@
 #define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
 #define	PHYS_SDRAM_1			0x40000000	/* Base address */
 #define	PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
-#define	CONFIG_STACKSIZE		0x00010000	/* 128 KB stack */
+#define	CONFIG_STACKSIZE		(128 * 1024)	/* 128 KB stack */
 #define	CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
 #define	CONFIG_SYS_GBL_DATA_SIZE	128		/* Initial data */
 #define	CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
-- 
cgit v1.3.1


From 3e5a0f35f1785a65d2269f21a3aaec335140a08c Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Thu, 7 Jun 2012 08:05:41 +0000
Subject: mx53ard: Remove unused CONFIG_MII_GASKET

CONFIG_MII_GASKET is not defined anywhere, so remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx53ard.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index f4512ffff2c..8da381f01e2 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -68,7 +68,6 @@
 /* Eth Configs */
 #define CONFIG_HAS_ETH1
 #define CONFIG_MII
-#define CONFIG_MII_GASKET
 #define CONFIG_DISCOVER_PHY
 
 #define CONFIG_CMD_PING
-- 
cgit v1.3.1


From 29ee7f5487b8081d264e91daaa2ae98577cca7aa Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 2 Jun 2012 21:53:25 +0000
Subject: imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition

According to include/i2c.h:

"/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif
"

As the mxc_i2c driver does not support slave mode, there is no need
to define CONFIG_SYS_I2C_SLAVE in i.MX board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/imx31_phycore.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 17283582116..acbd6701c75 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -56,7 +56,6 @@
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_MX31_PORT2
 #define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		0xfe
 
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
-- 
cgit v1.3.1


From bd6f402b2af061bda27a68e7b7aa8cfc03a2f585 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 2 Jun 2012 21:53:26 +0000
Subject: mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition

According to include/i2c.h:

"/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif
"

As the mxc_i2c driver does not support slave mode, there is no need
to define CONFIG_SYS_I2C_SLAVE in i.MX board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx35pdk.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 016864a6584..ebbd371165c 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -59,7 +59,6 @@
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_MX35_PORT1
 #define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		0xfe
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
-- 
cgit v1.3.1


From b6a5fbf4bfc139d48b91e1e7b3ccbabb37727e80 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@gmail.com>
Date: Sat, 2 Jun 2012 21:53:27 +0000
Subject: mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition

According to include/i2c.h:

"/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif
"

As the mxc_i2c driver does not support slave mode, there is no need
to define CONFIG_SYS_I2C_SLAVE in i.MX board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx53ard.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 8da381f01e2..ffc799cd7fe 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -52,7 +52,6 @@
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_MX53_PORT2
 #define CONFIG_SYS_I2C_SPEED            100000
-#define CONFIG_SYS_I2C_SLAVE            0xfe
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
-- 
cgit v1.3.1


From 6ce85ad5c76a7d6a9c50c39842d9c5705f98e229 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 2 Jun 2012 21:53:28 +0000
Subject: mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition

According to include/i2c.h:

"/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif
"

As the mxc_i2c driver does not support slave mode, there is no need
to define CONFIG_SYS_I2C_SLAVE in i.MX board file.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx53evk.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index a5f32e317da..8f2c03f1a03 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -55,7 +55,6 @@
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_MX53_PORT2       1
 #define CONFIG_SYS_I2C_SPEED            100000
-#define CONFIG_SYS_I2C_SLAVE            0xfe
 
 /* PMIC Configs */
 #define CONFIG_PMIC
-- 
cgit v1.3.1


From fd8223eaa94539b60d6a26e6bdf8f60146431951 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 2 Jun 2012 21:53:29 +0000
Subject: mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition

According to include/i2c.h:

"/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif
"

As the mxc_i2c driver does not support slave mode, there is no need
to define CONFIG_SYS_I2C_SLAVE in i.MX board file.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx53loco.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index b63d37d55f9..e71148dee60 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -91,7 +91,6 @@
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_MX53_PORT1
 #define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		0xfe
 
 /* PMIC Controller */
 #define CONFIG_PMIC
-- 
cgit v1.3.1


From 7d778916053aa579155c71e68debb0bde612b139 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sat, 2 Jun 2012 21:53:30 +0000
Subject: mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition

According to include/i2c.h:

"/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif
"

As the mxc_i2c driver does not support slave mode, there is no need
to define CONFIG_SYS_I2C_SLAVE in i.MX board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 include/configs/mx53smd.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 0d7086dde82..1df20faf6b4 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -52,7 +52,6 @@
 #define CONFIG_I2C_MXC
 #define CONFIG_SYS_I2C_MX53_PORT2
 #define CONFIG_SYS_I2C_SPEED            100000
-#define CONFIG_SYS_I2C_SLAVE            0xfe
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
-- 
cgit v1.3.1


From 5e7d0917b644e1768ddfdeb1fa5822dc7c974fa4 Mon Sep 17 00:00:00 2001
From: "esw@bus-elektronik.de" <esw@bus-elektronik.de>
Date: Mon, 19 Mar 2012 05:18:17 +0000
Subject: Fix: AT91SAM9263 nor flash usage
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix: board doesn't boot from norflash
 Fix: environment can't write to flash (end address/start address not on sector boundary)

Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
---
 include/configs/at91sam9263ek.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 61a622a843b..f2163f1475c 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -33,7 +33,11 @@
  */
 #include <asm/hardware.h>
 
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
 #define CONFIG_SYS_TEXT_BASE		0x21F00000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x0000000
+#endif
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
@@ -147,11 +151,11 @@
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN	(256 << 10)
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007FE000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
 
 /* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SIZE		0x10000
 
 #define xstr(s)   str(s)
 #define str(s)	#s
-- 
cgit v1.3.1


From e1edd06594f41a53cbc3344db78b3093ccb84bf3 Mon Sep 17 00:00:00 2001
From: Bo Shen <voice.shen@atmel.com>
Date: Wed, 27 Jun 2012 21:24:10 +0000
Subject: AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enable EHCI support instead OHCI

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
---
 include/configs/at91sam9m10g45ek.h | 20 +++-----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index f8b3095b49e..1d5fc8f73ef 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -59,17 +59,6 @@
 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
 #define	CONFIG_USART_ID			ATMEL_ID_SYS
 
-/*
- * This needs to be defined for the OHCI code to work but it is defined as
- * ATMEL_ID_UHPHS in the CPU specific header files.
- */
-#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
-
-/*
- * Specify the clock enable bit in the PMC_SCER register.
- */
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
-
 /* LCD */
 #define CONFIG_LCD
 #define LCD_BPP				LCD_COLOR8
@@ -147,13 +136,10 @@
 #define CONFIG_RESET_PHY_R
 
 /* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
 #define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_BASE_HCI
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
 
 #define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
-- 
cgit v1.3.1


From e139cb31d32a4f39241bfd83bf622a97d08f6c9d Mon Sep 17 00:00:00 2001
From: Alexandre Belloni <alexandre.belloni@piout.net>
Date: Mon, 2 Jul 2012 04:26:58 +0000
Subject: AT91SAM9*: Change kernel address in dataflash to match u-boot's size
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On at91sam platforms, u-boot grew larger than the allocated size in
dataflash, the layout was:
bootstrap  0x00000000
ubootenv   0x00004200
uboot      0x00008400
kernel     0x00042000
fs         0x00252000

u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 =
0x39C00 bytes anymore.

Now, the layout is:
bootstrap  0x00000000
ubootenv   0x00004200
uboot      0x00008400
kernel     0x00084000
fs         0x00294000

Signed-off-by: Alexandre Belloni <alexandre.belloni@piout.net>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
---
 board/atmel/at91sam9260ek/partition.c | 6 +++---
 board/atmel/at91sam9261ek/partition.c | 6 +++---
 board/atmel/at91sam9263ek/partition.c | 6 +++---
 board/atmel/at91sam9rlek/partition.c  | 6 +++---
 include/configs/at91sam9260ek.h       | 5 +++--
 include/configs/at91sam9261ek.h       | 5 +++--
 include/configs/at91sam9263ek.h       | 2 +-
 include/configs/at91sam9rlek.h        | 3 ++-
 8 files changed, 21 insertions(+), 18 deletions(-)

(limited to 'include/configs')

diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c
index 2629c671868..9ec054f22b7 100644
--- a/board/atmel/at91sam9260ek/partition.c
+++ b/board/atmel/at91sam9260ek/partition.c
@@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
 	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
 	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
-	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
-	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
-	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
 };
diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c
index c739b116bf1..51cac77d4f5 100644
--- a/board/atmel/at91sam9261ek/partition.c
+++ b/board/atmel/at91sam9261ek/partition.c
@@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
 	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
 	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
-	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
-	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
-	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
 };
diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c
index 7e1d46f5309..d48fab791c1 100644
--- a/board/atmel/at91sam9263ek/partition.c
+++ b/board/atmel/at91sam9263ek/partition.c
@@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
 	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
 	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
-	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
-	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
-	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
 };
diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c
index 7e1d46f5309..d48fab791c1 100644
--- a/board/atmel/at91sam9rlek/partition.c
+++ b/board/atmel/at91sam9rlek/partition.c
@@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
 	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
 	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
-	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
-	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
-	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+	{0x00008400, 0x00083FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
 };
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 07b19680703..ef25fa5e0c8 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -187,7 +187,7 @@
 #define CONFIG_ENV_OFFSET		0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
 				"mtdparts=atmel_nand:-(root) "		\
@@ -201,7 +201,7 @@
 #define CONFIG_ENV_OFFSET		0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0084000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
 				"mtdparts=atmel_nand:-(root) "		\
@@ -230,6 +230,7 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 6fd0b832fe1..014437b5e08 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -189,7 +189,7 @@
 #define CONFIG_ENV_OFFSET	0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
 				"mtdparts=atmel_nand:-(root) "		\
@@ -203,7 +203,7 @@
 #define CONFIG_ENV_OFFSET	0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0084000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
 				"mtdparts=atmel_nand:-(root) "		\
@@ -232,6 +232,7 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index f2163f1475c..4309f71f16b 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -318,7 +318,7 @@
 #define CONFIG_ENV_OFFSET		0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock0 " \
 				"mtdparts=atmel_nand:-(root) "\
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 45f8baff053..c5952e93192 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -155,7 +155,7 @@
 #define CONFIG_ENV_OFFSET		0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock0 " \
 				"mtdparts=atmel_nand:-(root) "\
@@ -182,6 +182,7 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
 
 /*
  * Size of malloc() pool
-- 
cgit v1.3.1


From e29c6d040183cad9aab413f2c22599a09b717197 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Fri, 25 May 2012 01:57:13 +0000
Subject: arm/km: add board type to boards.cfg

Some other kirkwood boards from keymile will follow. They will have some
small differences, but we want to use the km_kirkwood.h for all to
distinguish them. This patch a preparation for this.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 boards.cfg                    | 4 ++--
 include/configs/km_kirkwood.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'include/configs')

diff --git a/boards.cfg b/boards.cfg
index 92050708b23..7e1241d6958 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -138,8 +138,8 @@ enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw
 calimain                     arm         arm926ejs   calimain            omicron        davinci
 pogo_e02                     arm         arm926ejs   -                   cloudengines   kirkwood
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
-km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_RECONFIG_XLX
+km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index ed361241567..f639edc7a68 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -42,10 +42,10 @@
 /*
  * Version number information
  */
-#ifdef CONFIG_KM_DISABLE_PCI
+#if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING	"\nKeymile Kirkwood"
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
-#else
+#elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING	"\nKeymile Kirkwood PCI"
 #endif
 
-- 
cgit v1.3.1


From f5b5a1c80ede478c44de605e41c41daae5bfcda3 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Fri, 25 May 2012 01:57:14 +0000
Subject: arm/km: add piggy mac adress offset for mgcoge3un

On mgcoge3un the piggy mac adress is at offset 3.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/mgcoge3un.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
index 797b0dfcd31..156821c611d 100644
--- a/include/configs/mgcoge3un.h
+++ b/include/configs/mgcoge3un.h
@@ -77,6 +77,7 @@
 	MVGBE_SET_MII_SPEED_TO_100)
 
 #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
 
 /*
  * PCIe port not used on mgcoge3un
-- 
cgit v1.3.1


From af85f0858808cb1598dd4353def58cf8eec3a83e Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Fri, 25 May 2012 01:57:16 +0000
Subject: arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE

This config option sounds like the it is responsible for the
update of  the environment, but it is the u-boot update handling.
Therefore we adapt it to a more apropriate naming.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 011f838106e..20b0c36679d 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -81,7 +81,7 @@
 	"boot=bootm ${load_addr_r} - -\0"				\
 	"cramfsloadfdt=true\0"						\
 	"u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0"			\
-	CONFIG_KM_DEF_ENV_UPDATE					\
+	CONFIG_KM_UPDATE_UBOOT						\
 	""
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
@@ -239,7 +239,7 @@ int get_scl(void);
 		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
 #endif /* MTDPARTS_DEFAULT */
 
-#define	CONFIG_KM_DEF_ENV_UPDATE					\
+#define	CONFIG_KM_UPDATE_UBOOT						\
 	"update="							\
 		"spi on;sf probe 0;sf erase 0 50000;"			\
 		"sf write ${load_addr_r} 0 ${filesize};"		\
-- 
cgit v1.3.1


From be67190e48b0f5f57f05104ee1e01d285cc96844 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Fri, 25 May 2012 01:57:19 +0000
Subject: arm/km: remove CONFIG_RESET_PHY_R

This is already defined in the generic kirkwood header.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 20b0c36679d..6423a07b044 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -164,7 +164,6 @@
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
 
 /*
  * UBI related stuff
-- 
cgit v1.3.1


From 002ec08d6d4e6bc32ac8f5d35ea4fbbc1f9138ab Mon Sep 17 00:00:00 2001
From: Valentin Longchamp <valentin.longchamp@keymile.com>
Date: Fri, 25 May 2012 01:57:20 +0000
Subject: arm/km: enable mii cmd

This is useful to debug the switch initialization

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 6423a07b044..43a0efb4261 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -159,6 +159,7 @@
  */
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_CMD_MII		/* to debug mdio phy config */
 #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
-- 
cgit v1.3.1


From a0fb94f9ed865ff8073b4d493918cb78411de2b1 Mon Sep 17 00:00:00 2001
From: Valentin Longchamp <valentin.longchamp@keymile.com>
Date: Fri, 25 May 2012 01:57:21 +0000
Subject: km_arm: use filesize for erase in update command

We used to have an arbitrary value, which can be a problem if we have a
u-boot image that is bigger than this value.

This patch is dependant on the whole km/arm series and will be included
in the v3 of the series if there is one.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/configs/km/km_arm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 43a0efb4261..4a0b80e292d 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -241,7 +241,7 @@ int get_scl(void);
 
 #define	CONFIG_KM_UPDATE_UBOOT						\
 	"update="							\
-		"spi on;sf probe 0;sf erase 0 50000;"			\
+		"spi on;sf probe 0;sf erase 0 +${filesize};"		\
 		"sf write ${load_addr_r} 0 ${filesize};"		\
 		"spi off\0"
 
-- 
cgit v1.3.1


From f214a20e7e4c072da3d5d857e8fa79a41a6446ab Mon Sep 17 00:00:00 2001
From: Michael Walle <michael@walle.cc>
Date: Tue, 5 Jun 2012 11:33:17 +0000
Subject: Kirkwood: add lschlv2 and lsxhl board support

This patch adds support for both the Linkstation Live (LS-CHLv2) and
Linkstation Pro (LS-XHL) by Buffalo.

Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 MAINTAINERS                           |   5 +
 board/buffalo/lsxl/Makefile           |  44 ++++++
 board/buffalo/lsxl/kwbimage-lschl.cfg | 229 +++++++++++++++++++++++++++
 board/buffalo/lsxl/kwbimage-lsxhl.cfg | 229 +++++++++++++++++++++++++++
 board/buffalo/lsxl/lsxl.c             | 283 ++++++++++++++++++++++++++++++++++
 board/buffalo/lsxl/lsxl.h             |  75 +++++++++
 boards.cfg                            |   2 +
 include/configs/lsxl.h                | 182 ++++++++++++++++++++++
 8 files changed, 1049 insertions(+)
 create mode 100644 board/buffalo/lsxl/Makefile
 create mode 100644 board/buffalo/lsxl/kwbimage-lschl.cfg
 create mode 100644 board/buffalo/lsxl/kwbimage-lsxhl.cfg
 create mode 100644 board/buffalo/lsxl/lsxl.c
 create mode 100644 board/buffalo/lsxl/lsxl.h
 create mode 100644 include/configs/lsxl.h

(limited to 'include/configs')

diff --git a/MAINTAINERS b/MAINTAINERS
index 8a524bac3a9..ce9fc9d80d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -904,6 +904,11 @@ Prafulla Wadaskar <prafulla@marvell.com>
 	rd6281a		ARM926EJS (Kirkwood SoC)
 	sheevaplug	ARM926EJS (Kirkwood SoC)
 
+Michael Walle <michael@walle.cc>
+
+	lschlv2		ARM926EJS (Kirkwood SoC)
+	lsxhl		ARM926EJS (Kirkwood SoC)
+
 Tom Warren <twarren@nvidia.com>
 
 	harmony		Tegra2 (ARM7 & A9 Dual Core)
diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile
new file mode 100644
index 00000000000..36f2560ba9d
--- /dev/null
+++ b/board/buffalo/lsxl/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= lsxl.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg
new file mode 100644
index 00000000000..2b9b3cd1b78
--- /dev/null
+++ b/board/buffalo/lsxl/kwbimage-lschl.cfg
@@ -0,0 +1,229 @@
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B1B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0:  0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24:    1, enable exit self refresh mode on DDR access
+# bit25:    1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543000
+# bit3-0:   0 required
+# bit4:     0, addr/cmd in same cycle
+# bit5:     0, clk is driven during self refresh, we don't care for APX
+# bit6:     0, use recommended falling edge of clk for addr/cmd
+# bit11-7:  0 required
+# bit12:    1 required
+# bit13:    1 required
+# bit14:    0, input buffer always powered up
+# bit17-15: 0 required
+# bit18:    1, cpu lock transaction enabled
+# bit19:    0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x3302444F
+# bit3-0:   0xf, 16 cycle tRAS (tRAS[3-0])
+# bit7-4:   4, 5 cycle tRCD
+# bit11-8:  4, 5 cyle tRP
+# bit15-12: 4, 5 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20:    0, 16 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 3, 4 cycle tRRD
+# bit31-28: 3, 4 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000823
+# bit6-0:   0x23, 35 cycle tRFC
+# bit8-7:   0, 1 cycle tR2R
+# bit10-9:  0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x00000009
+# bit1-0:   1, Cs0width=x16
+# bit3-2:   2, Cs0size=512Mbit
+# bit5-4:   0, Cs1width=nonexistent
+# bit7-6:   0, Cs1size=nonexistent
+# bit9-8:   0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16:    0, Cs0AddrSel
+# bit17:    0, Cs1AddrSel
+# bit18:    0, Cs2AddrSel
+# bit19:    0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0:    0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0:   0, Cmd=Normal SDRAM Mode
+# bit31-4:  0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0:   2, Burst Length (2 required)
+# bit3:     0, Burst Type (0 required)
+# bit6-4:   5, CAS Latency (CL) 5
+# bit7:     0, (Test Mode) Normal operation
+# bit8:     0, (Reset DLL) Normal operation
+# bit11-9:  3, Write recovery for auto-precharge (3 required)
+# bit12:    0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000042
+# bit0:     0, DRAM DLL enabled
+# bit1:     1, DRAM drive strength reduced
+# bit2:     0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3:   0 required
+# bit6:     1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7:   0 required
+# bit10:    0, differential DQS enabled
+# bit11:    0 required
+# bit12:    0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0:   0x7 required
+# bit3:     1, MBUS Burst Chop disabled
+# bit6-4:   0x7 required
+# bit7:     0 required (???)
+# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0, no half clock cycle addition to dataout
+# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0:   0 required
+# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x03FFFFF1
+# bit0:     1, Window enabled
+# bit1:     0, Write Protect disabled
+# bit3-2:   0x0, CS0 hit selected
+# bit23-4:  0xfffff required
+# bit31-24: 0x03, Size (i.e. 64MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x003C0000
+# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8:  0 required
+# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
+# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4   0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8:   0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14:    1, M_STARTBURST_IN ODT enabled
+# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0:     1, enable DDR init upon this register write
+# bit31-1:  0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
new file mode 100644
index 00000000000..8a94b6c718d
--- /dev/null
+++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
@@ -0,0 +1,229 @@
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B9B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0:  0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24:    1, enable exit self refresh mode on DDR access
+# bit25:    1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543010
+# bit3-0:   0 required
+# bit4:     1, T2 mode, addr/cmd are driven for two cycles
+# bit5:     0, clk is driven during self refresh, we don't care for APX
+# bit6:     0, use recommended falling edge of clk for addr/cmd
+# bit11-7:  0 required
+# bit12:    1 required
+# bit13:    1 required
+# bit14:    0, input buffer always powered up
+# bit17-15: 0 required
+# bit18:    1, cpu lock transaction enabled
+# bit19:    0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x22125441
+# bit3-0:   0x1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4:   4, 5 cycle tRCD
+# bit11-8:  4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20:    1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000832
+# bit6-0:   0x32, 50 cycle tRFC
+# bit8-7:   0, 1 cycle tR2R
+# bit10-9:  0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x0000000C
+# bit1-0:   0, Cs0width=x8
+# bit3-2:   3, Cs0size=1Gbit
+# bit5-4:   0, Cs1width=nonexistent
+# bit7-6:   0, Cs1size=nonexistent
+# bit9-8:   0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16:    0, Cs0AddrSel
+# bit17:    0, Cs1AddrSel
+# bit18:    0, Cs2AddrSel
+# bit19:    0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0:    0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0:   0, Cmd=Normal SDRAM Mode
+# bit31-4:  0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0:   2, Burst Length (2 required)
+# bit3:     0, Burst Type (0 required)
+# bit6-4:   5, CAS Latency (CL) 5
+# bit7:     0, (Test Mode) Normal operation
+# bit8:     0, (Reset DLL) Normal operation
+# bit11-9:  3, Write recovery for auto-precharge (3 required)
+# bit12:    0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000006
+# bit0:     0, DRAM DLL enabled
+# bit1:     1, DRAM drive strength reduced
+# bit2:     1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
+# bit5-3:   0 required
+# bit6:     0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
+# bit9-7:   0 required
+# bit10:    0, differential DQS enabled
+# bit11:    0 required
+# bit12:    0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0:   0x7 required
+# bit3:     1, MBUS Burst Chop disabled
+# bit6-4:   0x7 required
+# bit7:     0 required (???)
+# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0, no half clock cycle addition to dataout
+# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0:   0 required
+# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x0FFFFFF1
+# bit0:     1, Window enabled
+# bit1:     0, Write Protect disabled
+# bit3-2:   0x0, CS0 hit selected
+# bit23-4:  0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x00010000
+# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8:  0 required
+# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4   0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8:   0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14:    1, M_STARTBURST_IN ODT enabled
+# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0:     1, enable DDR init upon this register write
+# bit31-1:  0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
new file mode 100644
index 00000000000..fe155112c9e
--- /dev/null
+++ b/board/buffalo/lsxl/lsxl.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * Based on sheevaplug/sheevaplug.c by
+ *   Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include <spi_flash.h>
+
+#include "lsxl.h"
+
+/*
+ * Rescue mode
+ *
+ * Selected by holding the push button for 3 seconds, while powering on
+ * the device.
+ *
+ * These linkstations don't have a (populated) serial port. There is no
+ * way to access an (unmodified) board other than using the netconsole. If
+ * you want to recover from a bad environment setting or an empty environment,
+ * you can do this only with a working network connection. Therefore, a random
+ * ethernet address is generated if none is set and a DHCP request is sent.
+ * After a successful DHCP response is received, the network settings are
+ * configured and the ncip parameter is set to the serverip. Eg. for a working
+ * resuce mode, you should set 'next-server' to the host where the netconsole
+ * client is started.
+ * Additionally, the bootsource is set to 'rescue'.
+ */
+
+#ifndef CONFIG_ENV_OVERWRITE
+# error "You need to set CONFIG_ENV_OVERWRITE"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(LSXL_OE_VAL_LOW,
+			LSXL_OE_VAL_HIGH,
+			LSXL_OE_LOW, LSXL_OE_HIGH);
+
+	/*
+	 * Multi-Purpose Pins Functionality configuration
+	 * These strappings are taken from the original vendor uboot port.
+	 */
+	u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_UART0_RXD,
+		MPP5_UART0_TXD,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_GPIO,
+		MPP9_GPIO,
+		MPP10_GPO,		/* HDD power */
+		MPP11_GPIO,		/* USB Vbus enable */
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_GPO,		/* fan speed high */
+		MPP19_GPO,		/* fan speed low */
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,		/* function LED */
+		MPP37_GPIO,		/* alarm LED */
+		MPP38_GPIO,		/* info LED */
+		MPP39_GPIO,		/* power LED */
+		MPP40_GPIO,		/* fan alarm */
+		MPP41_GPIO,		/* funtion button */
+		MPP42_GPIO,		/* power switch */
+		MPP43_GPIO,		/* power auto switch */
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,		/* function red LED */
+		MPP49_GPIO,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+#define LED_OFF             0
+#define LED_ALARM_ON        1
+#define LED_ALARM_BLINKING  2
+#define LED_POWER_ON        3
+#define LED_POWER_BLINKING  4
+#define LED_INFO_ON         5
+#define LED_INFO_BLINKING   6
+
+static void __set_led(int blink_alarm, int blink_info, int blink_power,
+		int value_alarm, int value_info, int value_power)
+{
+	kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm);
+	kw_gpio_set_blink(GPIO_INFO_LED, blink_info);
+	kw_gpio_set_blink(GPIO_POWER_LED, blink_power);
+	kw_gpio_set_value(GPIO_ALARM_LED, value_alarm);
+	kw_gpio_set_value(GPIO_INFO_LED, value_info);
+	kw_gpio_set_value(GPIO_POWER_LED, value_power);
+}
+
+static void set_led(int state)
+{
+	switch (state) {
+	case LED_OFF:
+		__set_led(0, 0, 0, 0, 0, 0);
+		break;
+	case LED_ALARM_ON:
+		__set_led(0, 0, 0, 0, 1, 1);
+		break;
+	case LED_ALARM_BLINKING:
+		__set_led(1, 0, 0, 1, 1, 1);
+		break;
+	case LED_INFO_ON:
+		__set_led(0, 0, 0, 1, 0, 1);
+		break;
+	case LED_INFO_BLINKING:
+		__set_led(0, 1, 0, 1, 1, 1);
+		break;
+	case LED_POWER_ON:
+		__set_led(0, 0, 0, 1, 1, 0);
+		break;
+	case LED_POWER_BLINKING:
+		__set_led(0, 0, 1, 1, 1, 1);
+		break;
+	}
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	set_led(LED_POWER_BLINKING);
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+void check_enetaddr(void)
+{
+	uchar enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		/* signal unset/invalid ethaddr to user */
+		set_led(LED_INFO_BLINKING);
+	}
+}
+
+static void erase_environment(void)
+{
+	struct spi_flash *flash;
+
+	printf("Erasing environment..\n");
+	flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (!flash) {
+		printf("Erasing flash failed\n");
+		return;
+	}
+
+	spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
+	spi_flash_free(flash);
+	do_reset(NULL, 0, 0, NULL);
+}
+
+static void rescue_mode(void)
+{
+	uchar enetaddr[6];
+
+	printf("Entering rescue mode..\n");
+#ifdef CONFIG_RANDOM_MACADDR
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		eth_random_enetaddr(enetaddr);
+		if (eth_setenv_enetaddr("ethaddr", enetaddr)) {
+			printf("Failed to set ethernet address\n");
+				set_led(LED_ALARM_BLINKING);
+			return;
+		}
+	}
+#endif
+	setenv("bootsource", "rescue");
+}
+
+static void check_push_button(void)
+{
+	int i = 0;
+
+	while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) {
+		udelay(100000);
+		i++;
+
+		if (i == 10)
+			set_led(LED_INFO_ON);
+
+		if (i >= 100) {
+			set_led(LED_INFO_BLINKING);
+			break;
+		}
+	}
+
+	if (i >= 100)
+		erase_environment();
+	else if (i >= 10)
+		rescue_mode();
+}
+
+int misc_init_r(void)
+{
+	check_enetaddr();
+	check_push_button();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+	if (progress > 0)
+		return;
+
+	/* this is not an error, eg. bootp with autoload=no will trigger this */
+	if (progress == -BOOTSTAGE_ID_NET_LOADED)
+		return;
+
+	set_led(LED_ALARM_BLINKING);
+}
+#endif
diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h
new file mode 100644
index 00000000000..2a2642e4877
--- /dev/null
+++ b/board/buffalo/lsxl/lsxl.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __LSXL_H
+#define __LSXL_H
+
+#define GPIO_HDD_POWER		10
+#define GPIO_USB_VBUS		11
+#define GPIO_FAN_HIGH		18
+#define GPIO_FAN_LOW		19
+#define GPIO_FUNC_LED		36
+#define GPIO_ALARM_LED		37
+#define GPIO_INFO_LED		38
+#define GPIO_POWER_LED		39
+#define GPIO_FAN_LOCK		40
+#define GPIO_FUNC_BUTTON	41
+#define GPIO_POWER_SWITCH	42
+#define GPIO_POWER_AUTO_SWITCH	43
+#define GPIO_FUNC_RED_LED	48
+
+#define _BIT(x) (1<<(x))
+
+#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER)		    \
+			| _BIT(GPIO_USB_VBUS)		    \
+			| _BIT(GPIO_FAN_HIGH)		    \
+			| _BIT(GPIO_FAN_LOW)))
+
+#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32)	    \
+			| _BIT(GPIO_ALARM_LED - 32)	    \
+			| _BIT(GPIO_INFO_LED - 32)	    \
+			| _BIT(GPIO_POWER_LED - 32)	    \
+			| _BIT(GPIO_FUNC_RED_LED - 32)))
+
+#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER)		    \
+			| _BIT(GPIO_USB_VBUS))
+
+#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32)	    \
+			| _BIT(GPIO_ALARM_LED - 32)	    \
+			| _BIT(GPIO_INFO_LED - 32)	    \
+			| _BIT(GPIO_POWER_LED - 32)	    \
+			| _BIT(GPIO_FUNC_RED_LED - 32))
+
+#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH)		    \
+			| _BIT(GPIO_FAN_LOW))
+
+#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32)	    \
+			| _BIT(GPIO_ALARM_LED - 32)	    \
+			| _BIT(GPIO_INFO_LED - 32)	    \
+			| _BIT(GPIO_POWER_LED - 32)	    \
+			| _BIT(GPIO_FUNC_BUTTON - 32)	    \
+			| _BIT(GPIO_POWER_SWITCH - 32)	    \
+			| _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
+			| _BIT(GPIO_FUNC_RED_LED - 32))
+
+#endif /* __LSXL_H */
diff --git a/boards.cfg b/boards.cfg
index 7e1241d6958..d33ff273713 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -138,6 +138,8 @@ enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw
 calimain                     arm         arm926ejs   calimain            omicron        davinci
 pogo_e02                     arm         arm926ejs   -                   cloudengines   kirkwood
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
+lschlv2                      arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSCHLV2
+lsxhl                        arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSXHL
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
new file mode 100644
index 00000000000..0db559cf6cc
--- /dev/null
+++ b/include/configs/lsxl.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_LSXL_H
+#define _CONFIG_LSXL_H
+
+/*
+ * Version number information
+ */
+#if defined(CONFIG_LSCHLV2)
+#define CONFIG_IDENT_STRING " LS-CHLv2"
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_MACH_TYPE 3006
+#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
+#elif defined(CONFIG_LSXHL)
+#define CONFIG_IDENT_STRING " LS-XHL"
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_MACH_TYPE 2663
+/* CONFIG_SYS_TCLK is 200000000 by default */
+#else
+#error "unknown board"
+#endif
+
+/*
+ * General configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_RANDOM_MACADDR
+#define CONFIG_KIRKWOOD_GPIO
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* ST M25P40 */
+#undef CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_STMICRO
+#undef CONFIG_ENV_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MAX_HZ		25000000
+#undef CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	8
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x10000 /* 64K */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x10000 /* 64k */
+#define CONFIG_ENV_OFFSET		0x70000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_LOADADDR		0x00800000
+#define CONFIG_BOOTCOMMAND	"run bootcmd_${bootsource}"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/sda2"
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootsource=hdd\0"						\
+	"hdpart=0:1\0"							\
+	"bootcmd_net=bootp 0x00100000 uImage "				\
+		"&& tftpboot 0x00800000 uInitrd "			\
+		"&& bootm 0x00100000 0x00800000\0"			\
+	"bootcmd_hdd=ide reset "					\
+		"&& ext2load ide ${hdpart} 0x00100000 /uImage "		\
+		"&& ext2load ide ${hdpart} 0x00800000 /uInitrd "	\
+		"&& bootm 0x00100000 0x00800000\0"			\
+	"bootcmd_usb=usb start "					\
+		"&& fatload usb 0:1 0x00100000 /uImage "		\
+		"&& fatload usb 0:1 0x00800000 /uInitrd "		\
+		"&& bootm 0x00100000 0x00800000\0"			\
+	"bootcmd_rescue=run config_nc_dhcp; run nc\0"			\
+	"eraseenv=sf probe 0 "						\
+		"&& sf erase " MK_STR(CONFIG_ENV_OFFSET)		\
+			" +" MK_STR(CONFIG_ENV_SIZE) "\0"		\
+	"config_nc_dhcp=setenv autoload_old ${autoload}; "		\
+		"setenv autoload no "					\
+		"&& bootp "						\
+		"&& setenv ncip ${serverip} "				\
+		"&& setenv autoload ${autoload_old}; "			\
+		"setenv autoload_old\0"					\
+	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; "	\
+		"setenv ncip; setenv gatewayip; setenv ethact; "	\
+		"setenv bootfile; setenv dnsip; "			\
+		"setenv bootsource hdd; run ser\0"			\
+	"restore_env=run standard_env; saveenv; reset\0"		\
+	"ser=setenv stdin serial; setenv stdout serial; "		\
+		"setenv stderr serial\0"				\
+	"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0"	\
+	"stdin=serial\0"						\
+	"stdout=serial\0"						\
+	"stderr=serial\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{0, 1} /* enable port 1 only */
+#define CONFIG_PHY_BASE_ADR		7
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+#endif /* _CONFIG_LSXL_H */
-- 
cgit v1.3.1


From c4c4b0e66188e7a21256ba67255f8bc874994039 Mon Sep 17 00:00:00 2001
From: Simon Guinot <simon.guinot@sequanux.org>
Date: Tue, 5 Jun 2012 13:15:58 +0000
Subject: lacie_kw: fix SDRAM banks number for net2big_v2

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
---
 include/configs/lacie_kw.h | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index cd8d59f9af6..0796ccf8f3d 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -66,11 +66,7 @@
 /*
  * SDRAM configuration
  */
-#if defined(CONFIG_NET2BIG_V2)
-#define CONFIG_NR_DRAM_BANKS		2
-#else
 #define CONFIG_NR_DRAM_BANKS		1
-#endif
 
 #ifdef CONFIG_INETSPACE_V2
 /* Different SDRAM configuration and size for Internet Space v2 */
-- 
cgit v1.3.1


From d92151b9259bc009a4dd8ed1683770520f3b10ac Mon Sep 17 00:00:00 2001
From: Simon Guinot <simon.guinot@sequanux.org>
Date: Tue, 5 Jun 2012 13:15:59 +0000
Subject: lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
---
 include/configs/lacie_kw.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 0796ccf8f3d..c35c2db30c9 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -70,7 +70,7 @@
 
 #ifdef CONFIG_INETSPACE_V2
 /* Different SDRAM configuration and size for Internet Space v2 */
-#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
 #endif
 
 /*
-- 
cgit v1.3.1


From 0c25defccdc0461bf6695d7e0fe3091c9da8778e Mon Sep 17 00:00:00 2001
From: Valentin Longchamp <valentin.longchamp@keymile.com>
Date: Wed, 13 Jun 2012 03:01:03 +0000
Subject: arm/km: use spi claim bus to switch between SPI and NAND

We overwrite these weak functions from the kirkwood spi code to
use our own method to be able to switch between the SPI NOR and
the NAND flash. This is needed e.g. to update the u-boot. The former
command do_spi_toggle can therefore be removed. And the usage of
this command is removed from the u-boot update command in the
u-boot environment.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c | 44 +++++++------------------------------------
 include/configs/km/km_arm.h   |  9 ++++++---
 2 files changed, 13 insertions(+), 40 deletions(-)

(limited to 'include/configs')

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ed12b5c5d8c..cb3402b8f96 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -33,6 +33,7 @@
 #include <nand.h>
 #include <netdev.h>
 #include <miiphy.h>
+#include <spi.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
@@ -284,48 +285,17 @@ int board_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_CMD_SF)
-int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int board_spi_claim_bus(struct spi_slave *slave)
 {
-	u32 tmp;
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if ((strcmp(argv[1], "off") == 0)) {
-		printf("SPI FLASH disabled, NAND enabled\n");
-		/* Multi-Purpose Pins Functionality configuration */
-		kwmpp_config[0] = MPP0_NF_IO2;
-		kwmpp_config[1] = MPP1_NF_IO3;
-		kwmpp_config[2] = MPP2_NF_IO4;
-		kwmpp_config[3] = MPP3_NF_IO5;
-
-		kirkwood_mpp_conf(kwmpp_config, NULL);
-		tmp = readl(KW_GPIO0_BASE);
-		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	} else if ((strcmp(argv[1], "on") == 0)) {
-		printf("SPI FLASH enabled, NAND disabled\n");
-		/* Multi-Purpose Pins Functionality configuration */
-		kwmpp_config[0] = MPP0_SPI_SCn;
-		kwmpp_config[1] = MPP1_SPI_MOSI;
-		kwmpp_config[2] = MPP2_SPI_SCK;
-		kwmpp_config[3] = MPP3_SPI_MISO;
-
-		kirkwood_mpp_conf(kwmpp_config, NULL);
-		tmp = readl(KW_GPIO0_BASE);
-		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
-	} else {
-		return cmd_usage(cmdtp);
-	}
+	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
 
 	return 0;
 }
 
-U_BOOT_CMD(
-	spitoggle,	2,	0,	do_spi_toggle,
-	"En-/disable SPI FLASH access",
-	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
-	);
-#endif
+void board_spi_release_bus(struct spi_slave *slave)
+{
+	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+}
 
 int dram_init(void)
 {
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 4a0b80e292d..b14093f4f3d 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -227,7 +227,11 @@ int get_scl(void);
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 
+/* SPI bus claim MPP configuration */
+#define CONFIG_SYS_KW_SPI_MPP	0x0
+
 #define FLASH_GPIO_PIN			0x00010000
+#define KM_FLASH_GPIO_PIN	16
 
 #ifndef MTDIDS_DEFAULT
 # define MTDIDS_DEFAULT		"nand0=orion_nand"
@@ -241,9 +245,8 @@ int get_scl(void);
 
 #define	CONFIG_KM_UPDATE_UBOOT						\
 	"update="							\
-		"spi on;sf probe 0;sf erase 0 +${filesize};"		\
-		"sf write ${load_addr_r} 0 ${filesize};"		\
-		"spi off\0"
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"
 
 /*
  * Default environment variables
-- 
cgit v1.3.1


From 0ec005fe00b9057fd16531f44146c9e363bb7861 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 3 Jul 2012 03:02:20 +0000
Subject: Kirkwood: Add support for Ka-Ro TK71

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Wolfgang Denk <wd@denx.de>
---
 board/karo/tk71/Makefile     |  45 +++++++++++
 board/karo/tk71/kwbimage.cfg | 174 +++++++++++++++++++++++++++++++++++++++++++
 board/karo/tk71/tk71.c       | 166 +++++++++++++++++++++++++++++++++++++++++
 boards.cfg                   |   1 +
 include/configs/tk71.h       | 130 ++++++++++++++++++++++++++++++++
 5 files changed, 516 insertions(+)
 create mode 100644 board/karo/tk71/Makefile
 create mode 100644 board/karo/tk71/kwbimage.cfg
 create mode 100644 board/karo/tk71/tk71.c
 create mode 100644 include/configs/tk71.h

(limited to 'include/configs')

diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile
new file mode 100644
index 00000000000..934e3911d14
--- /dev/null
+++ b/board/karo/tk71/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+# on behalf of DENX Software Engineering GmbH
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= tk71.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg
new file mode 100644
index 00000000000..0166826e728
--- /dev/null
+++ b/board/karo/tk71/kwbimage.cfg
@@ -0,0 +1,174 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# adopted to TK71 by
+# Nils Faerber <nils.faerber@kernelconcepts.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x1101355b	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000034	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000000	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   01, Cs1width=x16
+# bit7-6:   10, Cs1size=512Mb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x1FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x00000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00110000	#  DDR ODT Control (Low)
+# bit3-0:   0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4:   0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F	# CPU ODT Control
+# bit3-0:    1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10:    01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12:    10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14:        1, M_STARTBURST_IN ODT: Enabled
+# bit15:        1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c
new file mode 100644
index 00000000000..96410d77d60
--- /dev/null
+++ b/board/karo/tk71/tk71.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TK71_OE_LOW			(~0)
+#define TK71_OE_HIGH			(~0)
+#define TK71_OE_VAL_LOW			(0)
+#define TK71_OE_VAL_HIGH		(0)
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(TK71_OE_VAL_LOW,
+			TK71_OE_VAL_HIGH,
+			TK71_OE_LOW, TK71_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+
+#define MV88E1116_MAC_CTRL2_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+static void mv_phy_88e1118_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1118 Initialized on %s\n", name);
+}
+
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+	/* configure and initialize PHY */
+	mv_phy_88e1118_init("egiga0");
+
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index d33ff273713..a423555fb7a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -158,6 +158,7 @@ rd6281a                      arm         arm926ejs   -                   Marvell
 sheevaplug                   arm         arm926ejs   -                   Marvell        kirkwood
 ib62x0                       arm         arm926ejs   ib62x0              raidsonic      kirkwood
 dockstar                     arm         arm926ejs   -                   Seagate        kirkwood
+tk71                         arm         arm926ejs   tk71                karo           kirkwood
 devkit3250                   arm         arm926ejs   devkit3250          timll          lpc32xx
 jadecpu                      arm         arm926ejs   jadecpu             syteco         mb86r0x
 mx25pdk                      arm         arm926ejs   mx25pdk             freescale      mx25		mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
diff --git a/include/configs/tk71.h b/include/configs/tk71.h
new file mode 100644
index 00000000000..f929f203ab8
--- /dev/null
+++ b/include/configs/tk71.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_TK71_H__
+#define __CONFIG_TK71_H__
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nKa-Ro TK71"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define MACH_TYPE_TK71		2399
+#define CONFIG_MACH_TYPE	MACH_TYPE_TK71
+
+/*
+ * Commands configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * NAND flash
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV		"nand0,3"
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}
+#define CONFIG_PHY_BASE_ADR	0x08
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_KIRKWOOD
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_ADDR			0x80000
+#define CONFIG_ENV_OFFSET		0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
+#define CONFIG_MTDPARTS 	"512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
+	"update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
+	"update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
+	"update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
+	"bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
+#define MTDIDS_DEFAULT			"nand0=orion_nand"
+#define MTDPARTS_DEFAULT		"mtdparts=orion_nand:"CONFIG_MTDPARTS
+
+#define PHYS_SDRAM_1		0x00000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* Max 512 MB RAM */
+
+#endif	/* __CONFIG_TK71_H__ */
-- 
cgit v1.3.1


From f3f98bb0b8cc520e08ea2bdfc3f9cbe4e4ac29f5 Mon Sep 17 00:00:00 2001
From: SRICHARAN R <r.sricharan@ti.com>
Date: Tue, 12 Jun 2012 19:53:33 +0000
Subject: ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.

Currently on OMAP4/5 platforms, many kernel drivers are dependent
upon the bootloaders for mux, dpll and clock configurations.
This should not be the case and bootloaders should set only the
minimum required for the uboot functionality and kernel boot.

Note that this is going to break the kernel drivers. But this
is the only way to get things fixed in the kernel.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
 include/configs/omap4_common.h | 5 -----
 include/configs/omap5_evm.h    | 2 --
 2 files changed, 7 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index e7a3de5a667..2192c2b8993 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -120,9 +120,6 @@
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 
-/* clocks */
-#define CONFIG_SYS_CLOCKS_ENABLE_ALL
-
 /* commands to include */
 #include <config_cmd_default.h>
 
@@ -283,8 +280,6 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 
-#define CONFIG_SYS_ENABLE_PADS_ALL
-
 #define CONFIG_SYS_THUMB_BUILD
 
 #endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
index 837838700aa..c5874bbf67b 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -50,8 +50,6 @@
 /* Clock Defines */
 #define V_OSCK			19200000	/* Clock output from T2 */
 #define V_SCLK	V_OSCK
-#define CONFIG_SYS_CLOCKS_ENABLE_ALL	1	/* Enable all clocks */
-#define CONFIG_SYS_ENABLE_PADS_ALL	1	/* Enable all PADS for now */
 
 #undef CONFIG_USE_IRQ	/* no support for IRQs */
 #define CONFIG_MISC_INIT_R
-- 
cgit v1.3.1


From 816e3921480d216c415a7c27ac4e0bf62004db1d Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Mon, 2 Jul 2012 02:27:59 +0000
Subject: cm-t35: fix incorrect NAND_ECC layout selection

The current configuration selects an incorrect NAND ECC layout,
which causes u-boot to write HW ECC data incorrectly.
This patch selects the right layout.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
---
 include/configs/cm_t35.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index b97e8871502..ee4bce5d341 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -174,7 +174,7 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-- 
cgit v1.3.1


From 8170aefc84b04af1e5bd217b04aef81a047f8d28 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Thu, 5 Jul 2012 05:37:46 +0000
Subject: arm/km: add kmnusa board support

This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
 - IVM EEPROM is at adress: pca9547:70:9
 - PCI is enabled
 - PIGGY4 is connected via MV88E6352 simple switch. There is no phy
   between the simple switch and the kirkwood.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 MAINTAINERS                                |   1 +
 board/keymile/km_arm/km_arm.c              |   7 +-
 board/keymile/km_arm/kwbimage_128M16_1.cfg | 294 +++++++++++++++++++++++++++++
 boards.cfg                                 |   1 +
 include/configs/km/km_arm.h                |  44 ++++-
 include/configs/km_kirkwood.h              |  67 +++++--
 6 files changed, 391 insertions(+), 23 deletions(-)
 create mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg

(limited to 'include/configs')

diff --git a/MAINTAINERS b/MAINTAINERS
index ce9fc9d80d5..864a827c46c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -740,6 +740,7 @@ Sergey Lapin <slapin@ossfans.org>
 Valentin Longchamp <valentin.longchamp@keymile.com>
 
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
+	kmnusa		ARM926EJS (Kirkwood SoC)
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index cb3402b8f96..e77c5ad96dd 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -134,10 +134,11 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+	defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
  */
 int ethernet_present(void)
 {
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg
new file mode 100644
index 00000000000..bcce9073f6f
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -0,0 +1,294 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001	#  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start command
+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start command
+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index a423555fb7a..64b5dbc3d48 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -142,6 +142,7 @@ lschlv2                      arm         arm926ejs   lsxl                buffalo
 lsxhl                        arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSXHL
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index b14093f4f3d..60e2450d285 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -57,6 +57,13 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C		/* I2C bit-banged	*/
 
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		5000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#endif
+
 #include "asm/arch/config.h"
 
 #define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
@@ -211,6 +218,15 @@ int get_scl(void);
 /*
  *  Environment variables configurations
  */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment vars */
+#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
+#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
+#else
 #define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
 #define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
@@ -218,11 +234,11 @@ int get_scl(void);
 #define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
 #define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
 #define CONFIG_I2C_ENV_EEPROM_BUS	KM_ENV_BUS "\0"
-
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
 #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
@@ -248,17 +264,27 @@ int get_scl(void);
 		"sf probe 0;sf erase 0 +${filesize};"			\
 		"sf write ${load_addr_r} 0 ${filesize};\0"
 
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_KM_DEF_ENV						\
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " xstr(CONFIG_ENV_OFFSET) " "			\
+		xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV						\
 	"newenv=setenv addr 0x100000 && "				\
 		"i2c dev 1; mw.b ${addr} 0 4 && "			\
 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
 		" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "		\
 		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
-		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_NEW_ENV						\
 	"arch=arm\0"							\
 	"EEprom_ivm=" KM_IVM_BUS "\0"					\
 	""
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index f639edc7a68..34dd0a6b1ac 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -6,8 +6,9 @@
  * (C) Copyright 2009
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * (C) Copyright 2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -36,23 +37,67 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
 #if defined(CONFIG_KM_KIRKWOOD)
-#define CONFIG_IDENT_STRING	"\nKeymile Kirkwood"
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
-#define CONFIG_IDENT_STRING	"\nKeymile Kirkwood PCI"
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+/* KM_NUSA */
+#elif defined(CONFIG_KM_NUSA)
+#define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_PIGGY4_88E6352
+
+#else
+#error ("Board unsupported")
 #endif
 
+/* include common defines/options for all arm based Keymile boards */
+#include "km/km_arm.h"
+
 #define CONFIG_HOSTNAME			km_kirkwood
 
-#define KM_IVM_BUS	"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
+#endif
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
+/*
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			    | \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			    | \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				        | \
+	MVGBE_MIIPHY_MAC_MODE			    | \
+	MVGBE_AUTO_NEG_NO_CHANGE		    | \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			    | \
+	MVGBE_SET_FULL_DUPLEX_MODE		    | \
+	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_1000	    |\
+	MVGBE_SET_MII_SPEED_TO_100)
+
+#endif
 
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
-- 
cgit v1.3.1


From d9354530fe3a891718e3a9b88a756545c3891475 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Thu, 5 Jul 2012 05:05:02 +0000
Subject: arm/km: add kmcoge5un board support

For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 MAINTAINERS                               |   1 +
 board/keymile/km_arm/km_arm.c             |   4 +
 board/keymile/km_arm/kwbimage_256M8_1.cfg | 296 ++++++++++++++++++++++++++++++
 boards.cfg                                |   1 +
 include/configs/km_kirkwood.h             |  16 +-
 5 files changed, 316 insertions(+), 2 deletions(-)
 create mode 100644 board/keymile/km_arm/kwbimage_256M8_1.cfg

(limited to 'include/configs')

diff --git a/MAINTAINERS b/MAINTAINERS
index 864a827c46c..e42a32708ad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -742,6 +742,7 @@ Valentin Longchamp <valentin.longchamp@keymile.com>
 	km_kirkwood	ARM926EJS (Kirkwood SoC)
 	kmnusa		ARM926EJS (Kirkwood SoC)
 	mgcoge3un	ARM926EJS (Kirkwood SoC)
+	kmcoge5un	ARM926EJS (Kirkwood SoC)
 	portl2		ARM926EJS (Kirkwood SoC)
 
 Nishanth Menon <nm@ti.com>
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index e77c5ad96dd..73ddb610ec5 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -457,7 +457,11 @@ int get_scl(void)
 
 int post_hotkeys_pressed(void)
 {
+#if defined(CONFIG_KM_COGE5UN)
+	return kw_gpio_get_value(KM_POST_EN_L);
+#else
 	return !kw_gpio_get_value(KM_POST_EN_L);
+#endif
 }
 
 ulong post_word_load(void)
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg
new file mode 100644
index 00000000000..3e1237bbe31
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -0,0 +1,296 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300	# MPP Control 1 Register
+# bit 3-0:   0, MPPSel8	 GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserved
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+# bit 15-0:  ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000	# DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for APX
+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31:    0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E	# DDR Timing (Low) (active cycles value +1)
+# bit 3-0:   0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4:   0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8:  0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E	#  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000000	#  DDR Address Control
+# bit 1-0:    0, Cs0width=x8 (2 devices)
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1, DDR drive strenght reduced
+# bit 2:      1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for > 266Mhz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452	# DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start command
+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start command
+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1	# CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000004	#  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     1, ODT1 never active
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801	# CPU ODT Control
+# bit 3-0:     1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4:     0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8:     0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index 64b5dbc3d48..808f85b583f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -144,6 +144,7 @@ km_kirkwood                  arm         arm926ejs   km_arm              keymile
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
+kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_COGE5UN
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
 net2big_v2                   arm         arm926ejs   net2big_v2          LaCie          kirkwood	lacie_kw:NET2BIG_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 34dd0a6b1ac..d839a021423 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -39,15 +39,18 @@
 
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
+#define CONFIG_HOSTNAME			km_kirkwood
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define CONFIG_HOSTNAME			km_kirkwood_pci
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#define CONFIG_HOSTNAME			kmnusa
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG \
 		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
@@ -55,6 +58,17 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+#elif defined(CONFIG_KM_COGE5UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
+#define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
+#undef	CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
+#define CONFIG_HOSTNAME			kmcoge5un
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6352
 #else
 #error ("Board unsupported")
 #endif
@@ -62,8 +76,6 @@
 /* include common defines/options for all arm based Keymile boards */
 #include "km/km_arm.h"
 
-#define CONFIG_HOSTNAME			km_kirkwood
-
 #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
 #endif
-- 
cgit v1.3.1


From f945439af9198be07a32f8799e96df60ae1b0adb Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Thu, 5 Jul 2012 05:05:03 +0000
Subject: arm/km: convert mgcoge3un target to km_kirkwood

Use the generic header km_kirkwood.h and get rid of the
board specific header.

changes for v2: rebased because of changes in other patches

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |  9 ++---
 boards.cfg                    |  2 +-
 include/configs/km_kirkwood.h | 46 +++++++++++++++++++++++
 include/configs/mgcoge3un.h   | 87 -------------------------------------------
 4 files changed, 51 insertions(+), 93 deletions(-)
 delete mode 100644 include/configs/mgcoge3un.h

(limited to 'include/configs')

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 73ddb610ec5..831cbd98dc0 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -114,7 +114,7 @@ u32 kwmpp_config[] = {
 	0
 };
 
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
 /*
  * Wait for startup OK from mgcoge3ne
  */
@@ -134,8 +134,7 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
-	defined(CONFIG_KM_PIGGY4_88E6352))
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
 /*
  * All boards with PIGGY4 connected via a simple switch have ethernet always
  * present.
@@ -203,7 +202,7 @@ int misc_init_r(void)
 		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
 		gd->bd->bi_arch_number = mach_type;
 	}
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
 	char *wait_for_ne;
 	wait_for_ne = getenv("waitforne");
 	if (wait_for_ne != NULL) {
@@ -318,7 +317,7 @@ void dram_init_banksize(void)
 	}
 }
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
 
 #define	PHY_LED_SEL	0x18
 #define PHY_LED0_LINK	(0x5)
diff --git a/boards.cfg b/boards.cfg
index 808f85b583f..003c2af1238 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -143,7 +143,7 @@ lsxhl                        arm         arm926ejs   lsxl                buffalo
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
-mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
+mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_COGE5UN
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index d839a021423..f5b9d2746b7 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -58,6 +58,20 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE3UN"
+#define CONFIG_HOSTNAME			mgcoge3un
+#define KM_IVM_BUS			"pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KMCOGE5UN */
 #elif defined(CONFIG_KM_COGE5UN)
 #define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
@@ -111,7 +125,39 @@
 
 #endif
 
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			| \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			| \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		| \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				| \
+	MVGBE_MIIPHY_MAC_MODE			| \
+	MVGBE_AUTO_NEG_NO_CHANGE		| \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			| \
+	MVGBE_SET_FULL_DUPLEX_MODE		| \
+	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_10_100	|\
+	MVGBE_SET_MII_SPEED_TO_100)
+#endif
+
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
 
+#ifdef CONFIG_KM_DISABLE_PCI
+#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#endif
 #endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
deleted file mode 100644
index 156821c611d..00000000000
--- a/include/configs/mgcoge3un.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_MGCOGE3UN_H
-#define _CONFIG_MGCOGE3UN_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING	"\nKeymile MGCOGE3UN"
-#define CONFIG_HOSTNAME		mgcoge3un
-#define CONFIG_MGCOGE3UN
-
-#define KM_IVM_BUS	"pca9547:70:9" /* I2C2 (Mux-Port 1)*/
-#define KM_ENV_BUS	"pca9547:70:d" /* I2C2 (Mux-Port 5)*/
-
-/* we use a new RAM type on mgcoge3un board */
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
-
-/*
- * mgcoge3un has a fixed link to the marvell switch
- * with 100MB full duplex and autoneg off, for this
- * reason we have to change the default settings
- */
-#define PORT_SERIAL_CONTROL_VALUE		( \
-	MVGBE_FORCE_LINK_PASS			| \
-	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
-	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
-	MVGBE_ADV_NO_FLOW_CTRL			| \
-	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
-	MVGBE_FORCE_BP_MODE_NO_JAM		| \
-	(1 << 9) /* Reserved bit has to be 1 */	| \
-	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
-	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
-	MVGBE_DTE_ADV_0				| \
-	MVGBE_MIIPHY_MAC_MODE			| \
-	MVGBE_AUTO_NEG_NO_CHANGE		| \
-	MVGBE_MAX_RX_PACKET_1552BYTE		| \
-	MVGBE_CLR_EXT_LOOPBACK			| \
-	MVGBE_SET_FULL_DUPLEX_MODE		| \
-	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
-	MVGBE_SET_GMII_SPEED_TO_10_100	|\
-	MVGBE_SET_MII_SPEED_TO_100)
-
-#define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
-
-/*
- * PCIe port not used on mgcoge3un
- */
-#undef  CONFIG_KIRKWOOD_PCIE_INIT
-
-#endif /* _CONFIG_MGCOGE3UN_H */
-- 
cgit v1.3.1


From 6ef6486180678ab86d511676ec68cf78bf267582 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Thu, 5 Jul 2012 05:05:04 +0000
Subject: arm/km: remove portl2.h and use km_kirkwood instead

The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c |  2 +-
 boards.cfg                    |  2 +-
 include/configs/km_kirkwood.h |  8 ++++
 include/configs/portl2.h      | 85 -------------------------------------------
 4 files changed, 10 insertions(+), 87 deletions(-)
 delete mode 100644 include/configs/portl2.h

(limited to 'include/configs')

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 831cbd98dc0..daab27bbb71 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -317,7 +317,7 @@ void dram_init_banksize(void)
 	}
 }
 
-#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
 
 #define	PHY_LED_SEL	0x18
 #define PHY_LED0_LINK	(0x5)
diff --git a/boards.cfg b/boards.cfg
index 003c2af1238..db7902fa162 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -145,7 +145,7 @@ km_kirkwood_pci              arm         arm926ejs   km_arm              keymile
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_COGE5UN
-portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
+portl2                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_PORTL2
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:INETSPACE_V2
 net2big_v2                   arm         arm926ejs   net2big_v2          LaCie          kirkwood	lacie_kw:NET2BIG_V2
 netspace_max_v2              arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_MAX_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index f5b9d2746b7..44a3e7a6e89 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -83,6 +83,14 @@
 #define CONFIG_HOSTNAME			kmcoge5un
 #define CONFIG_KM_DISABLE_PCIE
 #define CONFIG_KM_PIGGY4_88E6352
+
+/* KM_PORTL2 */
+#elif defined(CONFIG_KM_PORTL2)
+#define CONFIG_IDENT_STRING		"\nKeymile Port-L2"
+#define CONFIG_HOSTNAME			portl2
+#define KM_IVM_BUS			"pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_PIGGY4_88E6061
+
 #else
 #error ("Board unsupported")
 #endif
diff --git a/include/configs/portl2.h b/include/configs/portl2.h
deleted file mode 100644
index e436cfea418..00000000000
--- a/include/configs/portl2.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com.
- * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_PORTL2_H
-#define _CONFIG_PORTL2_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING	"\nKeymile Port-L2"
-#define CONFIG_HOSTNAME			portl2
-#define CONFIG_PORTL2
-
-#define KM_IVM_BUS	"pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-/*
- * Note: This is only valid for HW > P1A if you got an outdated P1A
- *       use KM_ENV_BUS  "pca9544a:70:a"
- */
-#define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
-
-/*
- * portl2 has a fixed link to the XMPP backplane
- * with 100MB full duplex and autoneg off, for this
- * reason we have to change the default settings
- */
-#define PORT_SERIAL_CONTROL_VALUE		( \
-	MVGBE_FORCE_LINK_PASS			| \
-	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
-	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
-	MVGBE_ADV_NO_FLOW_CTRL			| \
-	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
-	MVGBE_FORCE_BP_MODE_NO_JAM		| \
-	(1 << 9) /* Reserved bit has to be 1 */	| \
-	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
-	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
-	MVGBE_DTE_ADV_0				| \
-	MVGBE_MIIPHY_MAC_MODE			| \
-	MVGBE_AUTO_NEG_NO_CHANGE		| \
-	MVGBE_MAX_RX_PACKET_1552BYTE		| \
-	MVGBE_CLR_EXT_LOOPBACK			| \
-	MVGBE_SET_FULL_DUPLEX_MODE		| \
-	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
-	MVGBE_SET_GMII_SPEED_TO_10_100	|\
-	MVGBE_SET_MII_SPEED_TO_100)
-
-/*
- * portl2 does use the PCIe Port0
- */
-#define  CONFIG_KIRKWOOD_PCIE_INIT
-
-#endif /* _CONFIG_PORTL2_H */
-- 
cgit v1.3.1


From b37f772433ab44d1730423eccf11f287ce61ec5f Mon Sep 17 00:00:00 2001
From: Valentin Longchamp <valentin.longchamp@keymile.com>
Date: Thu, 5 Jul 2012 05:05:05 +0000
Subject: arm/km: enable BOCO2 FPGA download support

This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.

This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
   for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
   the CPU can update the FPGA configuration when the kernel is running

The boards with a PCIe FPGA but without BOCO2 still are supported.

The config option name is CONFIG_KM_FPGA_CONFIG

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/common/common.h      |   5 +
 board/keymile/km_arm/Makefile      |   4 +
 board/keymile/km_arm/fpga_config.c | 212 +++++++++++++++++++++++++++++++++++++
 board/keymile/km_arm/km_arm.c      |  21 ++--
 boards.cfg                         |   2 +-
 include/configs/km/km_arm.h        |   3 +
 include/configs/km_kirkwood.h      |   8 +-
 7 files changed, 245 insertions(+), 10 deletions(-)
 create mode 100644 board/keymile/km_arm/fpga_config.c

(limited to 'include/configs')

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index f457aa30c6a..aab706e6c9c 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -131,6 +131,11 @@ struct bfticu_iomap {
 int ethernet_present(void);
 int ivm_read_eeprom(void);
 
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
 int set_km_env(void);
 int fdt_set_node_and_value(void *blob,
 			char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index aa512552658..13d485aedb4 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o ../common/common.o ../common/ivm.o
 
+ifdef CONFIG_KM_FPGA_CONFIG
+COBJS	+= fpga_config.o
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 00000000000..4356b9a64ef
--- /dev/null
+++ b/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN    39
+
+#define BOCO_ADDR	0x10
+
+#define ID_REG		0x00
+#define BOCO2_ID	0x5b
+
+static int check_boco2(void)
+{
+	int ret;
+	u8 id;
+
+	ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO id !!\n", __func__);
+		return ret;
+	}
+
+	return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+	int ret;
+	u8 regval;
+
+	/* give access to the EEPROM from FPGA */
+	ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+	regval &= ~flags;
+	ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error writing the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+	int ret;
+	u8 regval;
+
+	/* give access to the EEPROM from FPGA */
+	ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error reading the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+	regval |= flags;
+	ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
+	if (ret) {
+		printf("%s: error writing the BOCO @%#x !!\n",
+			__func__, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+#define SPI_REG		0x06
+#define CFG_EEPROM	0x02
+#define FPGA_PROG	0x04
+#define FPGA_DONE	0x20
+
+int trigger_fpga_config(void)
+{
+	int ret = 0;
+
+	if (check_boco2()) {
+		/* we have a BOCO2, this has to be triggered here */
+
+		/* make sure the FPGA_can access the EEPROM */
+		ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
+		if (ret)
+			return ret;
+
+		/* trigger the config start */
+		ret = boco_clear_bits(SPI_REG, FPGA_PROG);
+		if (ret)
+			return ret;
+
+		/* small delay for the pulse */
+		udelay(10);
+
+		/* up signal for pulse end */
+		ret = boco_set_bits(SPI_REG, FPGA_PROG);
+		if (ret)
+			return ret;
+
+	} else {
+		/* we do it the old way, with the gpio pin */
+		kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+		kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+		/* small delay for the pulse */
+		udelay(10);
+		kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+	}
+
+	return 0;
+}
+
+int wait_for_fpga_config(void)
+{
+	int ret = 0;
+	u8 spictrl;
+	u32 timeout = 20000;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	printf("PCIe FPGA config:");
+	do {
+		ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
+		if (ret) {
+			printf("%s: error reading the BOCO spictrl !!\n",
+				__func__);
+			return ret;
+		}
+		if (timeout-- == 0) {
+			printf(" FPGA_DONE timeout\n");
+			return -EFAULT;
+		}
+		udelay(10);
+	} while (!(spictrl & FPGA_DONE));
+
+	printf(" done\n");
+
+	return 0;
+}
+
+#define PRST1		0x4
+#define BRIDGE_RST	0x4
+
+int fpga_reset(void)
+{
+	int ret = 0;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	ret = boco_clear_bits(PRST1, BRIDGE_RST);
+	if (ret)
+		return ret;
+
+	/* small delay for the pulse */
+	udelay(10);
+
+	ret = boco_set_bits(PRST1, BRIDGE_RST);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
+ * is available from the Bobcat SPI bus */
+int toggle_eeprom_spi_bus(void)
+{
+	int ret = 0;
+
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	ret = boco_set_bits(SPI_REG, CFG_EEPROM);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index daab27bbb71..c8da823cb28 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -267,12 +267,6 @@ int board_early_init_f(void)
 #if defined(CONFIG_SYS_EEPROM_WREN)
 	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
-#endif
-#if defined(CONFIG_KM_RECONFIG_XLX)
-	/* trigger the reconfiguration of the xilinx fpga */
-	kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
-	kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
-	kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
 #endif
 	return 0;
 }
@@ -282,6 +276,21 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
+#if defined(CONFIG_KM_FPGA_CONFIG)
+	trigger_fpga_config();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_KM_FPGA_CONFIG)
+	wait_for_fpga_config();
+	fpga_reset();
+	toggle_eeprom_spi_bus();
+#endif
+
 	return 0;
 }
 
diff --git a/boards.cfg b/boards.cfg
index db7902fa162..26c0a9904e6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -141,7 +141,7 @@ dns325                       arm         arm926ejs   -                   d-link
 lschlv2                      arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSCHLV2
 lsxhl                        arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSXHL
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_COGE5UN
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 60e2450d285..1a5f04bc74f 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -313,4 +313,7 @@ int get_scl(void);
 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
 #define CONFIG_CMD_DIAG
 
+/* we do the whole PCIe FPGA config stuff here */
+#define	BOARD_LATE_INIT
+
 #endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 44a3e7a6e89..0a61b7d9eb1 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -162,10 +162,12 @@
 	MVGBE_SET_MII_SPEED_TO_100)
 #endif
 
-/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
-#define KM_XLX_PROGRAM_B_PIN    39
-
 #ifdef CONFIG_KM_DISABLE_PCI
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #endif
+
+#ifndef CONFIG_KM_FPGA_CONFIG
+#undef  BOARD_LATE_INIT
+#endif
+
 #endif /* _CONFIG_KM_KIRKWOOD */
-- 
cgit v1.3.1


From 48ced62cfb1722c97b6e598036b4e204980c4c47 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Thu, 5 Jul 2012 05:05:06 +0000
Subject: arm/km: cleanup km_kirkwood boards

Remove config options from boards.cfg and simply add one switch
per board and differ afterwards in km_kirkwood.h between the features.
More boards are upcoming and therefore it's easier to have this
at one place.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 boards.cfg                    | 4 ++--
 include/configs/km_kirkwood.h | 7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

(limited to 'include/configs')

diff --git a/boards.cfg b/boards.cfg
index 26c0a9904e6..a864ac555c4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -140,8 +140,8 @@ pogo_e02                     arm         arm926ejs   -                   clouden
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
 lschlv2                      arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSCHLV2
 lsxhl                        arm         arm926ejs   lsxl                buffalo        kirkwood    lsxl:LSXHL
-km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
+km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_KIRKWOOD_PCI
 kmnusa                       arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_NUSA
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_MGCOGE3UN
 kmcoge5un                    arm         arm926ejs   km_arm              keymile        kirkwood    km_kirkwood:KM_COGE5UN
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 0a61b7d9eb1..a95c6657ba1 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -37,15 +37,20 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
+/* KM_KIRKWOOD */
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
 #define CONFIG_HOSTNAME			km_kirkwood
-#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define CONFIG_KM_DISABLE_PCIE
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+
+/* KM_KIRKWOOD_PCI */
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
 #define CONFIG_HOSTNAME			km_kirkwood_pci
 #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_FPGA_CONFIG
+
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
-- 
cgit v1.3.1


From b8cf7cc8860d30b85b08377183688bf9564896bf Mon Sep 17 00:00:00 2001
From: Thomas Herzmann <thomas.herzmann@keymile.com>
Date: Thu, 5 Jul 2012 05:05:10 +0000
Subject: arm/km: add implementation for read_dip_switch

Add a function to read the dip_switch on kmcoge5un. If the
switch is set the actual_bank is set to 0 and this SW is
booted.

Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
---
 board/keymile/km_arm/km_arm.c | 14 +++++++++++++-
 include/configs/km_kirkwood.h |  3 ---
 2 files changed, 13 insertions(+), 4 deletions(-)

(limited to 'include/configs')

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ed2454ff0c0..ea5d0db1ca0 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -285,12 +285,24 @@ int board_init(void)
 
 int board_late_init(void)
 {
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE	43
+	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+	/* if pin 1 do full erase */
+	if (dip_switch != 0) {
+		/* start bootloader */
+		puts("DIP:   Enabled\n");
+		setenv("actual_bank", "0");
+	}
+#endif
+
 #if defined(CONFIG_KM_FPGA_CONFIG)
 	wait_for_fpga_config();
 	fpga_reset();
 	toggle_eeprom_spi_bus();
 #endif
-
 	return 0;
 }
 
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index a95c6657ba1..fba181fffa1 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -171,8 +171,5 @@
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #endif
 
-#ifndef CONFIG_KM_FPGA_CONFIG
-#undef  BOARD_LATE_INIT
-#endif
 
 #endif /* _CONFIG_KM_KIRKWOOD */
-- 
cgit v1.3.1


From c471d84808843dce6174eaab624779aa15ff71bf Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Thu, 5 Jul 2012 05:05:11 +0000
Subject: arm/km: remove calls to kw_gpio_* in board_early_init_f

These functions tried to access two static tables before relocation
(board_early_init_f is executed before relocation). But these static
tables lie in the bss section which is not valid before relocation.
These accesses then overwrote some parts of u-boot binary before it was
relocated. For the kmnusa build, this results in a corrupted important
env variable (bootcmd) but it may be that some other parts of the u-boot
binary are corrupted.

This patch solves this problem by moving all the kw_gpio_* calls to
board_init, which should be early enough in the boot sequence. The only
calls that could not be moved is the one for the SOFT (bitbang) I2C, and
they have been replaced by a direct access to the GPIO dataout Control
register to set the two GPIOs as output.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
 board/keymile/km_arm/km_arm.c | 43 ++++++++++++++++++++++++++++---------------
 include/configs/km/km_arm.h   |  1 +
 2 files changed, 29 insertions(+), 15 deletions(-)

(limited to 'include/configs')

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ea5d0db1ca0..2b2ca393765 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -243,38 +243,51 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
+#if defined(CONFIG_SOFT_I2C)
 	u32 tmp;
 
+	/* set the 2 bitbang i2c pins as output gpios */
+	tmp = readl(KW_GPIO0_BASE + 4);
+	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
+
 	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
 
+int board_init(void)
+{
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	/*
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 
 #if defined(CONFIG_SOFT_I2C)
-	/* init the GPIO for I2C Bitbang driver */
+	/*
+	 * Reinit the GPIO for I2C Bitbang driver so that the now
+	 * available gpio framework is consistent. The calls to
+	 * direction output in are not necessary, they are already done in
+	 * board_early_init_f
+	 */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
 	kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
-	kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
-	kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
 #endif
+
 #if defined(CONFIG_SYS_EEPROM_WREN)
 	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 #endif
-	return 0;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
 #if defined(CONFIG_KM_FPGA_CONFIG)
 	trigger_fpga_config();
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 1a5f04bc74f..3aa5ca152c8 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -192,6 +192,7 @@ int get_sda(void);
 int get_scl(void);
 #define KM_KIRKWOOD_SDA_PIN	8
 #define KM_KIRKWOOD_SCL_PIN	9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
 #define KM_KIRKWOOD_ENV_WP	38
 
 #define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
-- 
cgit v1.3.1


From 1fa943b99d06fee8b6552f4215923e4681d4a5a4 Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Tue, 22 May 2012 00:15:55 +0000
Subject: SPEAr: Configure FSMC driver for NAND interface

Since FSMC is a standard IP and it supports different memory interfaces, it
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
---
 arch/arm/include/asm/arch-spear/hardware.h |  8 ++++----
 board/spear/spear300/spear300.c            | 14 +++++++++-----
 board/spear/spear310/spear310.c            | 14 +++++++++-----
 board/spear/spear320/spear320.c            | 13 +++++++++----
 board/spear/spear600/spear600.c            | 14 +++++++++-----
 include/configs/spear-common.h             |  3 ++-
 include/configs/spear3xx.h                 |  4 ++++
 include/configs/spear6xx.h                 |  3 +++
 8 files changed, 49 insertions(+), 24 deletions(-)

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
index 818f36cc667..a6517b2187f 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -37,15 +37,15 @@
 
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			(0xD0200000)
-#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
+#define CONFIG_SYS_FSMC_BASE			(0xD1800000)
 
 #elif defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
+#define CONFIG_SYS_FSMC_BASE			(0x94000000)
 
 #elif defined(CONFIG_SPEAR310)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
+#define CONFIG_SYS_FSMC_BASE			(0x44000000)
 
 #undef CONFIG_SYS_NAND_CLE
 #undef CONFIG_SYS_NAND_ALE
@@ -57,7 +57,7 @@
 
 #elif defined(CONFIG_SPEAR320)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
+#define CONFIG_SYS_FSMC_BASE			(0x4C000000)
 
 #define CONFIG_SPEAR_EMIBASE			(0x40000000)
 #define CONFIG_SPEAR_RASBASE			(0xB3000000)
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index 60ee54470e4..72a36314089 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -24,10 +24,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {
@@ -41,18 +43,20 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
-
-	return -1;
+#endif
+	return;
 }
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 03dfe16175e..14e666d6417 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -25,10 +25,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {
@@ -42,18 +44,20 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
-
-	return -1;
+#endif
+	return;
 }
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 2ba2dbb5666..994eb2b64d2 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -25,10 +25,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {
@@ -42,18 +44,21 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
+#endif
 
-	return -1;
+	return;
 }
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index eef9a3771cf..ab0f760678b 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -24,10 +24,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {
@@ -41,13 +43,15 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		return spear_nand_init(nand);
-
-	return -1;
+		fsmc_nand_init(nand);
+#endif
+	return;
 }
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index ab1b33209e3..8d0f0369ca9 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -88,9 +88,10 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
 /* NAND FLASH Configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_NAND_SPEAR			1
+#define CONFIG_NAND_FSMC
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE		1
 
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
index 37bdebb392c..2a86c212531 100644
--- a/include/configs/spear3xx.h
+++ b/include/configs/spear3xx.h
@@ -117,6 +117,10 @@
 
 #endif
 
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
 #if defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_NAND_BASE			(0x80000000)
 
diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h
index 2ad5beb82c6..c5bcc30cb75 100644
--- a/include/configs/spear6xx.h
+++ b/include/configs/spear6xx.h
@@ -38,6 +38,9 @@
 #define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
 						(void *)CONFIG_SYS_SERIAL1 }
 
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
 #define CONFIG_SYS_NAND_BASE			(0xD2000000)
 
 #endif  /* __CONFIG_H */
-- 
cgit v1.3.1


From f3fcf92d595b297b47a1b58b8ec39f93f40ef912 Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:00:19 +0530
Subject: st_smi: Add support for SPEAr SMI driver

SMI is the serial memory interface controller provided by ST.

Earlier, a driver exists in the u-boot source code for the SMI IP. However, it
was specific to spear platforms. This commit converts the same driver to a more
generic driver. As a result, the driver files are renamed to st_smi.c and
st_smi.h and moved into drivers/mtd folder for reusability by other platforms
using smi controller peripheral.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/arm/include/asm/arch-spear/spr_smi.h | 115 -------
 drivers/mtd/Makefile                      |   2 +-
 drivers/mtd/spr_smi.c                     | 518 -----------------------------
 drivers/mtd/st_smi.c                      | 519 ++++++++++++++++++++++++++++++
 include/configs/spear-common.h            |   6 +-
 include/linux/mtd/st_smi.h                | 117 +++++++
 6 files changed, 640 insertions(+), 637 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-spear/spr_smi.h
 delete mode 100644 drivers/mtd/spr_smi.c
 create mode 100644 drivers/mtd/st_smi.c
 create mode 100644 include/linux/mtd/st_smi.h

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h
deleted file mode 100644
index 06df74557fd..00000000000
--- a/arch/arm/include/asm/arch-spear/spr_smi.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef SPR_SMI_H
-#define SPR_SMI_H
-
-/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
-/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
-
-#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
-
-#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
-#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
-#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
-#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
-
-#define BANK0			0
-#define BANK1			1
-#define BANK2			2
-#define BANK3			3
-
-struct smi_regs {
-	u32 smi_cr1;
-	u32 smi_cr2;
-	u32 smi_sr;
-	u32 smi_tr;
-	u32 smi_rr;
-};
-
-/* CONTROL REG 1 */
-#define BANK_EN			0x0000000F	/* enables all banks */
-#define DSEL_TIME		0x00000060	/* Deselect time */
-#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
-#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
-#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
-#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
-#define SW_MODE			0x10000000	/* enables SW Mode */
-#define WB_MODE			0x20000000	/* Write Burst Mode */
-#define FAST_MODE		0x00008000	/* Fast Mode */
-#define HOLD1			0x00010000
-
-/* CONTROL REG 2 */
-#define RD_STATUS_REG		0x00000400	/* reads status reg */
-#define WE			0x00000800	/* Write Enable */
-#define BANK0_SEL		0x00000000	/* Select Banck0 */
-#define BANK1_SEL		0x00001000	/* Select Banck1 */
-#define BANK2_SEL		0x00002000	/* Select Banck2 */
-#define BANK3_SEL		0x00003000	/* Select Banck3 */
-#define BANKSEL_SHIFT		12
-#define SEND			0x00000080	/* Send data */
-#define TX_LEN_1		0x00000001	/* data length = 1 byte */
-#define TX_LEN_2		0x00000002	/* data length = 2 byte */
-#define TX_LEN_3		0x00000003	/* data length = 3 byte */
-#define TX_LEN_4		0x00000004	/* data length = 4 byte */
-#define RX_LEN_1		0x00000010	/* data length = 1 byte */
-#define RX_LEN_2		0x00000020	/* data length = 2 byte */
-#define RX_LEN_3		0x00000030	/* data length = 3 byte */
-#define RX_LEN_4		0x00000040	/* data length = 4 byte */
-#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
-#define WCIE			0x00000200	/* WCF Interrupt Enable */
-
-/* STATUS_REG */
-#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
-#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
-#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
-#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
-#define RSR			0x00000005	/* Read Status regiser */
-#define TFF			0x00000100	/* Transfer Finished FLag */
-#define WCF			0x00000200	/* Transfer Finished FLag */
-#define ERF1			0x00000400	/* Error Flag 1 */
-#define ERF2			0x00000800	/* Error Flag 2 */
-#define WM0			0x00001000	/* WM Bank 0 */
-#define WM1			0x00002000	/* WM Bank 1 */
-#define WM2			0x00004000	/* WM Bank 2 */
-#define WM3			0x00008000	/* WM Bank 3 */
-#define WM_SHIFT		12
-
-/* TR REG */
-#define READ_ID			0x0000009F	/* Read Identification */
-#define BULK_ERASE		0x000000C7	/* BULK erase */
-#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
-#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
-
-struct flash_dev {
-	u32 density;
-	ulong size;
-	ushort sector_count;
-};
-
-#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
-#define XFER_FINISH_TOUT	2	/* xfer finish timeout */
-#define WMODE_TOUT		2	/* write enable timeout */
-
-#endif
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 5a5ecdfe3c6..543c845ff01 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
 COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
-COBJS-$(CONFIG_SPEARSMI) += spr_smi.o
+COBJS-$(CONFIG_ST_SMI) += st_smi.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c
deleted file mode 100644
index 6d4257a3f50..00000000000
--- a/drivers/mtd/spr_smi.c
+++ /dev/null
@@ -1,518 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <flash.h>
-#include <linux/err.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_smi.h>
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-static struct smi_regs *const smicntl =
-    (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
-static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
-    CONFIG_SYS_FLASH_ADDR_BASE;
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define ST_M25Pxx_ID		0x00002020
-
-static struct flash_dev flash_ids[] = {
-	{0x10, 0x10000, 2},	/* 64K Byte */
-	{0x11, 0x20000, 4},	/* 128K Byte */
-	{0x12, 0x40000, 4},	/* 256K Byte */
-	{0x13, 0x80000, 8},	/* 512K Byte */
-	{0x14, 0x100000, 16},	/* 1M Byte */
-	{0x15, 0x200000, 32},	/* 2M Byte */
-	{0x16, 0x400000, 64},	/* 4M Byte */
-	{0x17, 0x800000, 128},	/* 8M Byte */
-	{0x18, 0x1000000, 64},	/* 16M Byte */
-	{0x00,}
-};
-
-/*
- * smi_wait_xfer_finish - Wait until TFF is set in status register
- * @timeout:	 timeout in milliseconds
- *
- * Wait until TFF is set in status register
- */
-static void smi_wait_xfer_finish(int timeout)
-{
-	while (timeout--) {
-		if (readl(&smicntl->smi_sr) & TFF)
-			break;
-		udelay(1000);
-	}
-}
-
-/*
- * smi_read_id - Read flash id
- * @info:	 flash_info structure pointer
- * @banknum:	 bank number
- *
- * Read the flash id present at bank #banknum
- */
-static unsigned int smi_read_id(flash_info_t *info, int banknum)
-{
-	unsigned int value;
-
-	writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
-	writel(READ_ID, &smicntl->smi_tr);
-	writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
-	       &smicntl->smi_cr2);
-	smi_wait_xfer_finish(XFER_FINISH_TOUT);
-
-	value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
-
-	writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);
-	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
-
-	return value;
-}
-
-/*
- * flash_get_size - Detect the SMI flash by reading the ID.
- * @base:	 Base address of the flash area bank #banknum
- * @banknum:	 Bank number
- *
- * Detect the SMI flash by reading the ID. Initializes the flash_info structure
- * with size, sector count etc.
- */
-static ulong flash_get_size(ulong base, int banknum)
-{
-	flash_info_t *info = &flash_info[banknum];
-	struct flash_dev *dev;
-	unsigned int value;
-	unsigned int density;
-	int i;
-
-	value = smi_read_id(info, banknum);
-	density = (value >> 16) & 0xff;
-
-	for (i = 0, dev = &flash_ids[0]; dev->density != 0x0;
-	     i++, dev = &flash_ids[i]) {
-		if (dev->density == density) {
-			info->size = dev->size;
-			info->sector_count = dev->sector_count;
-			break;
-		}
-	}
-
-	if (dev->density == 0x0)
-		return 0;
-
-	info->flash_id = value & 0xffff;
-	info->start[0] = base;
-
-	return info->size;
-}
-
-/*
- * smi_read_sr - Read status register of SMI
- * @bank:	 bank number
- *
- * This routine will get the status register of the flash chip present at the
- * given bank
- */
-static unsigned int smi_read_sr(int bank)
-{
-	u32 ctrlreg1;
-
-	/* store the CTRL REG1 state */
-	ctrlreg1 = readl(&smicntl->smi_cr1);
-
-	/* Program SMI in HW Mode */
-	writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
-	       &smicntl->smi_cr1);
-
-	/* Performing a RSR instruction in HW mode */
-	writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
-
-	smi_wait_xfer_finish(XFER_FINISH_TOUT);
-
-	/* Restore the CTRL REG1 state */
-	writel(ctrlreg1, &smicntl->smi_cr1);
-
-	return readl(&smicntl->smi_sr);
-}
-
-/*
- * smi_wait_till_ready - Wait till last operation is over.
- * @bank:	 bank number shifted.
- * @timeout:	 timeout in milliseconds.
- *
- * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
- * The routine checks for #timeout loops, each at interval of 1 milli-second.
- * If successful the routine returns 0.
- */
-static int smi_wait_till_ready(int bank, int timeout)
-{
-	int count;
-	unsigned int sr;
-
-	/* One chip guarantees max 5 msec wait here after page writes,
-	   but potentially three seconds (!) after page erase. */
-	for (count = 0; count < timeout; count++) {
-
-		sr = smi_read_sr(bank);
-		if (sr < 0)
-			break;
-		else if (!(sr & WIP_BIT))
-			return 0;
-
-		/* Try again after 1m-sec */
-		udelay(1000);
-	}
-	printf("SMI controller is still in wait, timeout=%d\n", timeout);
-	return -EIO;
-}
-
-/*
- * smi_write_enable - Enable the flash to do write operation
- * @bank:	 bank number
- *
- * Set write enable latch with Write Enable command.
- * Returns negative if error occurred.
- */
-static int smi_write_enable(int bank)
-{
-	u32 ctrlreg1;
-	int timeout = WMODE_TOUT;
-
-	/* Store the CTRL REG1 state */
-	ctrlreg1 = readl(&smicntl->smi_cr1);
-
-	/* Program SMI in H/W Mode */
-	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
-
-	/* Give the Flash, Write Enable command */
-	writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
-
-	smi_wait_xfer_finish(XFER_FINISH_TOUT);
-
-	/* Restore the CTRL REG1 state */
-	writel(ctrlreg1, &smicntl->smi_cr1);
-
-	while (timeout--) {
-		if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT)))
-			break;
-		udelay(1000);
-	}
-
-	if (timeout)
-		return 0;
-
-	return -1;
-}
-
-/*
- * smi_init - SMI initialization routine
- *
- * SMI initialization routine. Sets SMI control register1.
- */
-static void smi_init(void)
-{
-	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
-	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
-	       &smicntl->smi_cr1);
-}
-
-/*
- * smi_sector_erase - Erase flash sector
- * @info:	 flash_info structure pointer
- * @sector:	 sector number
- *
- * Set write enable latch with Write Enable command.
- * Returns negative if error occurred.
- */
-static int smi_sector_erase(flash_info_t *info, unsigned int sector)
-{
-	int bank;
-	unsigned int sect_add;
-	unsigned int instruction;
-
-	switch (info->start[0]) {
-	case SMIBANK0_BASE:
-		bank = BANK0;
-		break;
-	case SMIBANK1_BASE:
-		bank = BANK1;
-		break;
-	case SMIBANK2_BASE:
-		bank = BANK2;
-		break;
-	case SMIBANK3_BASE:
-		bank = BANK3;
-		break;
-	default:
-		return -1;
-	}
-
-	sect_add = sector * (info->size / info->sector_count);
-	instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
-
-	writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
-
-	if (info->flash_id == ST_M25Pxx_ID) {
-		/* Wait until finished previous write command. */
-		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
-			return -EBUSY;
-
-		/* Send write enable, before erase commands. */
-		if (smi_write_enable(bank))
-			return -EIO;
-
-		/* Put SMI in SW mode */
-		writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
-
-		/* Send Sector Erase command in SW Mode */
-		writel(instruction, &smicntl->smi_tr);
-		writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
-		       &smicntl->smi_cr2);
-		smi_wait_xfer_finish(XFER_FINISH_TOUT);
-
-		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
-			return -EBUSY;
-
-		/* Put SMI in HW mode */
-		writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
-		       &smicntl->smi_cr1);
-
-		return 0;
-	} else {
-		/* Put SMI in HW mode */
-		writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
-		       &smicntl->smi_cr1);
-		return -EINVAL;
-	}
-}
-
-/*
- * smi_write - Write to SMI flash
- * @src_addr:	 source buffer
- * @dst_addr:	 destination buffer
- * @length:	 length to write in words
- * @bank:	 bank base address
- *
- * Write to SMI flash
- */
-static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
-		     unsigned int length, ulong bank_addr)
-{
-	int banknum;
-
-	switch (bank_addr) {
-	case SMIBANK0_BASE:
-		banknum = BANK0;
-		break;
-	case SMIBANK1_BASE:
-		banknum = BANK1;
-		break;
-	case SMIBANK2_BASE:
-		banknum = BANK2;
-		break;
-	case SMIBANK3_BASE:
-		banknum = BANK3;
-		break;
-	default:
-		return -1;
-	}
-
-	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
-		return -EBUSY;
-
-	/* Set SMI in Hardware Mode */
-	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
-
-	if (smi_write_enable(banknum))
-		return -EIO;
-
-	/* Perform the write command */
-	while (length--) {
-		if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
-			if (smi_wait_till_ready(banknum,
-						CONFIG_SYS_FLASH_WRITE_TOUT))
-				return -EBUSY;
-
-			if (smi_write_enable(banknum))
-				return -EIO;
-		}
-
-		*dst_addr++ = *src_addr++;
-
-		if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
-			return -EIO;
-	}
-
-	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
-		return -EBUSY;
-
-	writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
-
-	return 0;
-}
-
-/*
- * write_buff - Write to SMI flash
- * @info:	 flash info structure
- * @src:	 source buffer
- * @dest_addr:	 destination buffer
- * @length:	 length to write in words
- *
- * Write to SMI flash
- */
-int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
-{
-	return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
-		  (length + 3) / 4, info->start[0]);
-}
-
-/*
- * flash_init - SMI flash initialization
- *
- * SMI flash initialization
- */
-unsigned long flash_init(void)
-{
-	unsigned long size = 0;
-	int i, j;
-
-	smi_init();
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		size += flash_info[i].size = flash_get_size(bank_base[i], i);
-	}
-
-	for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
-		for (i = 1; i < flash_info[j].sector_count; i++)
-			flash_info[j].start[i] =
-			    flash_info[j].start[i - 1] +
-			    flash_info->size / flash_info->sector_count;
-
-	}
-
-	return size;
-}
-
-/*
- * flash_print_info - Print SMI flash information
- *
- * Print SMI flash information
- */
-void flash_print_info(flash_info_t *info)
-{
-	int i;
-	if (info->flash_id == FLASH_UNKNOWN) {
-		puts("missing or unknown FLASH type\n");
-		return;
-	}
-	printf("  Size: %ld MB in %d Sectors\n",
-	       info->size >> 20, info->sector_count);
-
-	puts("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
-		int size;
-		int erased;
-		u32 *flash;
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		size = (info->size) / (info->sector_count);
-		flash = (u32 *) info->start[i];
-		size = size / sizeof(int);
-
-		while ((size--) && (*flash++ == ~0))
-			;
-
-		size++;
-		if (size)
-			erased = 0;
-		else
-			erased = 1;
-
-		if ((i % 5) == 0)
-			printf("\n");
-
-		printf(" %08lX%s%s",
-		       info->start[i],
-		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
-#else
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-		       info->start[i], info->protect[i] ? " (RO)  " : "     ");
-#endif
-	}
-	putc('\n');
-	return;
-}
-
-/*
- * flash_erase - Erase SMI flash
- *
- * Erase SMI flash
- */
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	int rcode = 0;
-	int prot = 0;
-	flash_sect_t sect;
-
-	if (info->flash_id != ST_M25Pxx_ID) {
-		puts("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		puts("- no sectors to erase\n");
-		return 1;
-	}
-
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	} else {
-		putc('\n');
-	}
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {
-			if (smi_sector_erase(info, sect))
-				rcode = 1;
-			else
-				putc('.');
-		}
-	}
-	puts(" done\n");
-	return rcode;
-}
-#endif
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
new file mode 100644
index 00000000000..db08ab97e43
--- /dev/null
+++ b/drivers/mtd/st_smi.c
@@ -0,0 +1,519 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <linux/err.h>
+#include <linux/mtd/st_smi.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+static struct smi_regs *const smicntl =
+    (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
+    CONFIG_SYS_FLASH_ADDR_BASE;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define ST_M25Pxx_ID		0x00002020
+
+static struct flash_dev flash_ids[] = {
+	{0x10, 0x10000, 2},	/* 64K Byte */
+	{0x11, 0x20000, 4},	/* 128K Byte */
+	{0x12, 0x40000, 4},	/* 256K Byte */
+	{0x13, 0x80000, 8},	/* 512K Byte */
+	{0x14, 0x100000, 16},	/* 1M Byte */
+	{0x15, 0x200000, 32},	/* 2M Byte */
+	{0x16, 0x400000, 64},	/* 4M Byte */
+	{0x17, 0x800000, 128},	/* 8M Byte */
+	{0x18, 0x1000000, 64},	/* 16M Byte */
+	{0x00,}
+};
+
+/*
+ * smi_wait_xfer_finish - Wait until TFF is set in status register
+ * @timeout:	 timeout in milliseconds
+ *
+ * Wait until TFF is set in status register
+ */
+static void smi_wait_xfer_finish(int timeout)
+{
+	while (timeout--) {
+		if (readl(&smicntl->smi_sr) & TFF)
+			break;
+		udelay(1000);
+	}
+}
+
+/*
+ * smi_read_id - Read flash id
+ * @info:	 flash_info structure pointer
+ * @banknum:	 bank number
+ *
+ * Read the flash id present at bank #banknum
+ */
+static unsigned int smi_read_id(flash_info_t *info, int banknum)
+{
+	unsigned int value;
+
+	writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
+	writel(READ_ID, &smicntl->smi_tr);
+	writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
+	       &smicntl->smi_cr2);
+
+	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+	value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
+
+	writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);
+	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
+
+	return value;
+}
+
+/*
+ * flash_get_size - Detect the SMI flash by reading the ID.
+ * @base:	 Base address of the flash area bank #banknum
+ * @banknum:	 Bank number
+ *
+ * Detect the SMI flash by reading the ID. Initializes the flash_info structure
+ * with size, sector count etc.
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	struct flash_dev *dev;
+	unsigned int value;
+	unsigned int density;
+	int i;
+
+	value = smi_read_id(info, banknum);
+	density = (value >> 16) & 0xff;
+
+	for (i = 0, dev = &flash_ids[0]; dev->density != 0x0;
+	     i++, dev = &flash_ids[i]) {
+		if (dev->density == density) {
+			info->size = dev->size;
+			info->sector_count = dev->sector_count;
+			break;
+		}
+	}
+
+	if (dev->density == 0x0)
+		return 0;
+
+	info->flash_id = value & 0xffff;
+	info->start[0] = base;
+
+	return info->size;
+}
+
+/*
+ * smi_read_sr - Read status register of SMI
+ * @bank:	 bank number
+ *
+ * This routine will get the status register of the flash chip present at the
+ * given bank
+ */
+static unsigned int smi_read_sr(int bank)
+{
+	u32 ctrlreg1;
+
+	/* store the CTRL REG1 state */
+	ctrlreg1 = readl(&smicntl->smi_cr1);
+
+	/* Program SMI in HW Mode */
+	writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
+	       &smicntl->smi_cr1);
+
+	/* Performing a RSR instruction in HW mode */
+	writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
+
+	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+	/* Restore the CTRL REG1 state */
+	writel(ctrlreg1, &smicntl->smi_cr1);
+
+	return readl(&smicntl->smi_sr);
+}
+
+/*
+ * smi_wait_till_ready - Wait till last operation is over.
+ * @bank:	 bank number shifted.
+ * @timeout:	 timeout in milliseconds.
+ *
+ * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
+ * The routine checks for #timeout loops, each at interval of 1 milli-second.
+ * If successful the routine returns 0.
+ */
+static int smi_wait_till_ready(int bank, int timeout)
+{
+	int count;
+	unsigned int sr;
+
+	/* One chip guarantees max 5 msec wait here after page writes,
+	   but potentially three seconds (!) after page erase. */
+	for (count = 0; count < timeout; count++) {
+
+		sr = smi_read_sr(bank);
+		if (sr < 0)
+			break;
+		else if (!(sr & WIP_BIT))
+			return 0;
+
+		/* Try again after 1m-sec */
+		udelay(1000);
+	}
+	printf("SMI controller is still in wait, timeout=%d\n", timeout);
+	return -EIO;
+}
+
+/*
+ * smi_write_enable - Enable the flash to do write operation
+ * @bank:	 bank number
+ *
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+ */
+static int smi_write_enable(int bank)
+{
+	u32 ctrlreg1;
+	int timeout = WMODE_TOUT;
+
+	/* Store the CTRL REG1 state */
+	ctrlreg1 = readl(&smicntl->smi_cr1);
+
+	/* Program SMI in H/W Mode */
+	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
+
+	/* Give the Flash, Write Enable command */
+	writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
+
+	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+	/* Restore the CTRL REG1 state */
+	writel(ctrlreg1, &smicntl->smi_cr1);
+
+	while (timeout--) {
+		if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT)))
+			break;
+		udelay(1000);
+	}
+
+	if (timeout)
+		return 0;
+
+	return -1;
+}
+
+/*
+ * smi_init - SMI initialization routine
+ *
+ * SMI initialization routine. Sets SMI control register1.
+ */
+void smi_init(void)
+{
+	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+	       &smicntl->smi_cr1);
+}
+
+/*
+ * smi_sector_erase - Erase flash sector
+ * @info:	 flash_info structure pointer
+ * @sector:	 sector number
+ *
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+ */
+static int smi_sector_erase(flash_info_t *info, unsigned int sector)
+{
+	int bank;
+	unsigned int sect_add;
+	unsigned int instruction;
+
+	switch (info->start[0]) {
+	case SMIBANK0_BASE:
+		bank = BANK0;
+		break;
+	case SMIBANK1_BASE:
+		bank = BANK1;
+		break;
+	case SMIBANK2_BASE:
+		bank = BANK2;
+		break;
+	case SMIBANK3_BASE:
+		bank = BANK3;
+		break;
+	default:
+		return -1;
+	}
+
+	sect_add = sector * (info->size / info->sector_count);
+	instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
+
+	writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
+
+	if (info->flash_id == ST_M25Pxx_ID) {
+		/* Wait until finished previous write command. */
+		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
+			return -EBUSY;
+
+		/* Send write enable, before erase commands. */
+		if (smi_write_enable(bank))
+			return -EIO;
+
+		/* Put SMI in SW mode */
+		writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
+
+		/* Send Sector Erase command in SW Mode */
+		writel(instruction, &smicntl->smi_tr);
+		writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
+		       &smicntl->smi_cr2);
+		smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
+			return -EBUSY;
+
+		/* Put SMI in HW mode */
+		writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
+		       &smicntl->smi_cr1);
+
+		return 0;
+	} else {
+		/* Put SMI in HW mode */
+		writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
+		       &smicntl->smi_cr1);
+		return -EINVAL;
+	}
+}
+
+/*
+ * smi_write - Write to SMI flash
+ * @src_addr:	 source buffer
+ * @dst_addr:	 destination buffer
+ * @length:	 length to write in words
+ * @bank:	 bank base address
+ *
+ * Write to SMI flash
+ */
+static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
+		     unsigned int length, ulong bank_addr)
+{
+	int banknum;
+
+	switch (bank_addr) {
+	case SMIBANK0_BASE:
+		banknum = BANK0;
+		break;
+	case SMIBANK1_BASE:
+		banknum = BANK1;
+		break;
+	case SMIBANK2_BASE:
+		banknum = BANK2;
+		break;
+	case SMIBANK3_BASE:
+		banknum = BANK3;
+		break;
+	default:
+		return -1;
+	}
+
+	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
+		return -EBUSY;
+
+	/* Set SMI in Hardware Mode */
+	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
+
+	if (smi_write_enable(banknum))
+		return -EIO;
+
+	/* Perform the write command */
+	while (length--) {
+		if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
+			if (smi_wait_till_ready(banknum,
+						CONFIG_SYS_FLASH_WRITE_TOUT))
+				return -EBUSY;
+
+			if (smi_write_enable(banknum))
+				return -EIO;
+		}
+
+		*dst_addr++ = *src_addr++;
+
+		if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
+			return -EIO;
+	}
+
+	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
+		return -EBUSY;
+
+	writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
+
+	return 0;
+}
+
+/*
+ * write_buff - Write to SMI flash
+ * @info:	 flash info structure
+ * @src:	 source buffer
+ * @dest_addr:	 destination buffer
+ * @length:	 length to write in words
+ *
+ * Write to SMI flash
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
+{
+	return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
+		  (length + 3) / 4, info->start[0]);
+}
+
+/*
+ * flash_init - SMI flash initialization
+ *
+ * SMI flash initialization
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i, j;
+
+	smi_init();
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(bank_base[i], i);
+	}
+
+	for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
+		for (i = 1; i < flash_info[j].sector_count; i++)
+			flash_info[j].start[i] =
+			    flash_info[j].start[i - 1] +
+			    flash_info->size / flash_info->sector_count;
+
+	}
+
+	return size;
+}
+
+/*
+ * flash_print_info - Print SMI flash information
+ *
+ * Print SMI flash information
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts("missing or unknown FLASH type\n");
+		return;
+	}
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	puts("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		int size;
+		int erased;
+		u32 *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (info->size) / (info->sector_count);
+		flash = (u32 *) info->start[i];
+		size = size / sizeof(int);
+
+		while ((size--) && (*flash++ == ~0))
+			;
+
+		size++;
+		if (size)
+			erased = 0;
+		else
+			erased = 1;
+
+		if ((i % 5) == 0)
+			printf("\n");
+
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)  " : "     ");
+#endif
+	}
+	putc('\n');
+	return;
+}
+
+/*
+ * flash_erase - Erase SMI flash
+ *
+ * Erase SMI flash
+ */
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot = 0;
+	flash_sect_t sect;
+
+	if (info->flash_id != ST_M25Pxx_ID) {
+		puts("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		puts("- no sectors to erase\n");
+		return 1;
+	}
+
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		putc('\n');
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {
+			if (smi_sector_erase(info, sect))
+				rcode = 1;
+			else
+				putc('.');
+		}
+	}
+	puts(" done\n");
+	return rcode;
+}
+#endif
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 8d0f0369ca9..75cc5fff64c 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -55,10 +55,10 @@
 #if defined(CONFIG_FLASH_PNOR)
 #define CONFIG_SPEAR_EMI			1
 #else
-#define CONFIG_SPEARSMI				1
+#define CONFIG_ST_SMI
 #endif
 
-#if defined(CONFIG_SPEARSMI)
+#if defined(CONFIG_ST_SMI)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS		2
 #define CONFIG_SYS_FLASH_BASE			(0xF8000000)
@@ -125,7 +125,7 @@
  * U-Boot Environment placing definitions.
  */
 #if defined(CONFIG_ENV_IS_IN_FLASH)
-#ifdef CONFIG_SPEARSMI
+#ifdef CONFIG_ST_SMI
 /*
  * Environment is in serial NOR flash
  */
diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h
new file mode 100644
index 00000000000..b7a78acd7c2
--- /dev/null
+++ b/include/linux/mtd/st_smi.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ST_SMI_H
+#define ST_SMI_H
+
+/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
+/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
+
+#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
+
+#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
+#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
+#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
+#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
+
+#define BANK0			0
+#define BANK1			1
+#define BANK2			2
+#define BANK3			3
+
+struct smi_regs {
+	u32 smi_cr1;
+	u32 smi_cr2;
+	u32 smi_sr;
+	u32 smi_tr;
+	u32 smi_rr;
+};
+
+/* CONTROL REG 1 */
+#define BANK_EN			0x0000000F	/* enables all banks */
+#define DSEL_TIME		0x00000060	/* Deselect time */
+#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
+#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
+#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
+#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
+#define SW_MODE			0x10000000	/* enables SW Mode */
+#define WB_MODE			0x20000000	/* Write Burst Mode */
+#define FAST_MODE		0x00008000	/* Fast Mode */
+#define HOLD1			0x00010000
+
+/* CONTROL REG 2 */
+#define RD_STATUS_REG		0x00000400	/* reads status reg */
+#define WE			0x00000800	/* Write Enable */
+#define BANK0_SEL		0x00000000	/* Select Banck0 */
+#define BANK1_SEL		0x00001000	/* Select Banck1 */
+#define BANK2_SEL		0x00002000	/* Select Banck2 */
+#define BANK3_SEL		0x00003000	/* Select Banck3 */
+#define BANKSEL_SHIFT		12
+#define SEND			0x00000080	/* Send data */
+#define TX_LEN_1		0x00000001	/* data length = 1 byte */
+#define TX_LEN_2		0x00000002	/* data length = 2 byte */
+#define TX_LEN_3		0x00000003	/* data length = 3 byte */
+#define TX_LEN_4		0x00000004	/* data length = 4 byte */
+#define RX_LEN_1		0x00000010	/* data length = 1 byte */
+#define RX_LEN_2		0x00000020	/* data length = 2 byte */
+#define RX_LEN_3		0x00000030	/* data length = 3 byte */
+#define RX_LEN_4		0x00000040	/* data length = 4 byte */
+#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
+#define WCIE			0x00000200	/* WCF Interrupt Enable */
+
+/* STATUS_REG */
+#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
+#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
+#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
+#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
+#define RSR			0x00000005	/* Read Status regiser */
+#define TFF			0x00000100	/* Transfer Finished FLag */
+#define WCF			0x00000200	/* Transfer Finished FLag */
+#define ERF1			0x00000400	/* Error Flag 1 */
+#define ERF2			0x00000800	/* Error Flag 2 */
+#define WM0			0x00001000	/* WM Bank 0 */
+#define WM1			0x00002000	/* WM Bank 1 */
+#define WM2			0x00004000	/* WM Bank 2 */
+#define WM3			0x00008000	/* WM Bank 3 */
+#define WM_SHIFT		12
+
+/* TR REG */
+#define READ_ID			0x0000009F	/* Read Identification */
+#define BULK_ERASE		0x000000C7	/* BULK erase */
+#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
+#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
+
+struct flash_dev {
+	u32 density;
+	ulong size;
+	ushort sector_count;
+};
+
+#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
+#define XFER_FINISH_TOUT	2	/* xfer finish timeout */
+#define WMODE_TOUT		2	/* write enable timeout */
+
+extern void smi_init(void);
+
+#endif
-- 
cgit v1.3.1


From deb005622782bf568a4daa8daeb8adf95b606492 Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:42 +0530
Subject: SPEAr: Configure network support for spear SoCs

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/arm/include/asm/arch-spear/hardware.h |  1 +
 board/spear/spear300/spear300.c            | 10 ++++++++++
 board/spear/spear310/spear310.c            | 10 ++++++++++
 board/spear/spear320/spear320.c            | 10 ++++++++++
 board/spear/spear600/spear600.c            | 10 ++++++++++
 include/configs/spear-common.h             | 14 ++++++++++++--
 include/configs/spear3xx.h                 |  3 +++
 7 files changed, 56 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
index a6517b2187f..70fc0303553 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -31,6 +31,7 @@
 #define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
 #define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
 #define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
+#define CONFIG_SPEAR_ETHBASE			0xE0800000
 
 #define CONFIG_SYS_NAND_CLE			(1 << 16)
 #define CONFIG_SYS_NAND_ALE			(1 << 17)
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index 72a36314089..2283ad5ddbc 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
@@ -60,3 +61,12 @@ void board_nand_init()
 #endif
 	return;
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_DESIGNWARE_ETH)
+	return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY);
+#else
+	return -1;
+#endif
+}
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 14e666d6417..043a9f3aee9 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
@@ -61,3 +62,12 @@ void board_nand_init()
 #endif
 	return;
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_DESIGNWARE_ETH)
+	return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY);
+#else
+	return -1;
+#endif
+}
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 994eb2b64d2..1b6f362b5d8 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
@@ -62,3 +63,12 @@ void board_nand_init()
 
 	return;
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_DESIGNWARE_ETH)
+	return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY);
+#else
+	return -1;
+#endif
+}
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index ab0f760678b..d18d313b298 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
@@ -55,3 +56,12 @@ void board_nand_init()
 #endif
 	return;
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_DESIGNWARE_ETH)
+	return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY);
+#else
+	return -1;
+#endif
+}
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 75cc5fff64c..669d83eb7eb 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -27,6 +27,14 @@
  * Common configurations used for both spear3xx as well as spear6xx
  */
 
+/* Ethernet driver configuration */
+#define CONFIG_MII
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_DW0_PHY				1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+
 /* USBD driver configuration */
 #define CONFIG_DW_UDC
 #define CONFIG_USB_DEVICE
@@ -104,11 +112,13 @@
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
 
 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <config_cmd_default.h>
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
 
 /*
  * Default Environment Varible definitions
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
index 2a86c212531..035b32129dc 100644
--- a/include/configs/spear3xx.h
+++ b/include/configs/spear3xx.h
@@ -41,6 +41,9 @@
 
 #include <configs/spear-common.h>
 
+/* Ethernet driver configuration */
+#define CONFIG_DW_ALTDESCRIPTOR			1
+
 /* Serial Configuration (PL011) */
 #define CONFIG_SYS_SERIAL0			0xD0000000
 
-- 
cgit v1.3.1


From 8eb0ee6a649d09a41155bf6c9dbd4d531ed41f9e Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:43 +0530
Subject: SPEAr: Add macb driver support for spear310 and spear320

SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The
driver for this device is already supported by u-boot, so configuring
board configuration file and defining base addresses etc to make use
of the common driver

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/arm/include/asm/arch-spear/clk.h      | 27 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-spear/hardware.h |  7 +++++++
 board/spear/spear310/spear310.c            | 25 ++++++++++++++++++++++---
 board/spear/spear320/spear320.c            | 12 +++++++++---
 include/configs/spear3xx.h                 | 13 +++++++++++++
 5 files changed, 78 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-spear/clk.h

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h
new file mode 100644
index 00000000000..a45ec1861cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/clk.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+	return 83000000;
+}
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
index 70fc0303553..0012dd7e631 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -56,6 +56,11 @@
 #define CONFIG_SPEAR_EMIBASE			(0x4F000000)
 #define CONFIG_SPEAR_RASBASE			(0xB4000000)
 
+#define CONFIG_SYS_MACB0_BASE			0xB0000000
+#define CONFIG_SYS_MACB1_BASE			0xB0800000
+#define CONFIG_SYS_MACB2_BASE			0xB1000000
+#define CONFIG_SYS_MACB3_BASE			0xB1800000
+
 #elif defined(CONFIG_SPEAR320)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
 #define CONFIG_SYS_FSMC_BASE			(0x4C000000)
@@ -63,5 +68,7 @@
 #define CONFIG_SPEAR_EMIBASE			(0x40000000)
 #define CONFIG_SPEAR_RASBASE			(0xB3000000)
 
+#define CONFIG_SYS_MACB0_BASE			0xAA000000
+
 #endif
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 043a9f3aee9..c0e68299944 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -65,9 +65,28 @@ void board_nand_init()
 
 int board_eth_init(bd_t *bis)
 {
+	int ret = 0;
+
 #if defined(CONFIG_DESIGNWARE_ETH)
-	return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY);
-#else
-	return -1;
+	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0)
+		ret += -1;
+#endif
+#if defined(CONFIG_MACB)
+	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+				CONFIG_MACB0_PHY) < 0)
+		ret += -1;
+
+	if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
+				CONFIG_MACB1_PHY) < 0)
+		ret += -1;
+
+	if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
+				CONFIG_MACB2_PHY) < 0)
+		ret += -1;
+
+	if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
+				CONFIG_MACB3_PHY) < 0)
+		ret += -1;
 #endif
+	return ret;
 }
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 1b6f362b5d8..e101888e044 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -66,9 +66,15 @@ void board_nand_init()
 
 int board_eth_init(bd_t *bis)
 {
+	int ret = 0;
 #if defined(CONFIG_DESIGNWARE_ETH)
-	return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY);
-#else
-	return -1;
+	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0)
+		ret += -1;
 #endif
+#if defined(CONFIG_MACB)
+	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+				CONFIG_MACB0_PHY) < 0)
+		ret += -1;
+#endif
+	return ret;
 }
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
index 035b32129dc..f3e335465df 100644
--- a/include/configs/spear3xx.h
+++ b/include/configs/spear3xx.h
@@ -44,6 +44,19 @@
 /* Ethernet driver configuration */
 #define CONFIG_DW_ALTDESCRIPTOR			1
 
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_MACB				1
+#define CONFIG_MACB0_PHY			0x01
+#define CONFIG_MACB1_PHY			0x03
+#define CONFIG_MACB2_PHY			0x05
+#define CONFIG_MACB3_PHY			0x07
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_MACB				1
+#define CONFIG_MACB0_PHY			0x01
+
+#endif
+
 /* Serial Configuration (PL011) */
 #define CONFIG_SYS_SERIAL0			0xD0000000
 
-- 
cgit v1.3.1


From 962d026b6aaf7d801d182f3188e4bbc106e057e3 Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:45 +0530
Subject: SPEAr: Add basic arch related support for SPEAr SoCs

Earlier, architecture specific init code was mixed with board initialization
code in board/spear/... This patch updates architecture support for SPEAr in
latest u-boot and prints the SoC information.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/arm/cpu/arm926ejs/spear/Makefile      |  3 +-
 arch/arm/cpu/arm926ejs/spear/cpu.c         | 82 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-spear/spr_misc.h |  7 +++
 include/configs/spear-common.h             |  2 +
 4 files changed, 93 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/arm926ejs/spear/cpu.c

(limited to 'include/configs')

diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index f32ec4ccf38..46923a42fb1 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	:= reset.o \
+COBJS	:= cpu.o \
+	   reset.o \
 	   timer.o
 SOBJS	:=
 
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
new file mode 100644
index 00000000000..9e074bc9eb5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+
+int arch_cpu_init(void)
+{
+	struct misc_regs *const misc_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 periph1_clken;
+
+	periph1_clken = readl(&misc_p->periph1_clken);
+
+#if defined(CONFIG_SPEAR3XX)
+	periph1_clken |= MISC_GPT2ENB;
+#elif defined(CONFIG_SPEAR600)
+	periph1_clken |= MISC_GPT3ENB;
+#endif
+
+#if defined(CONFIG_PL011_SERIAL)
+	periph1_clken |= MISC_UART0ENB;
+#endif
+#if defined(CONFIG_DESIGNWARE_ETH)
+	periph1_clken |= MISC_ETHENB;
+#endif
+#if defined(CONFIG_DW_UDC)
+	periph1_clken |= MISC_USBDENB;
+#endif
+#if defined(CONFIG_DW_I2C)
+	periph1_clken |= MISC_I2CENB;
+#endif
+#if defined(CONFIG_ST_SMI)
+	periph1_clken |= MISC_SMIENB;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+	periph1_clken |= MISC_FSMCENB;
+#endif
+
+	writel(periph1_clken, &misc_p->periph1_clken);
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_SPEAR300
+	printf("CPU:   SPEAr300\n");
+#elif defined(CONFIG_SPEAR310)
+	printf("CPU:   SPEAr310\n");
+#elif defined(CONFIG_SPEAR320)
+	printf("CPU:   SPEAr320\n");
+#elif defined(CONFIG_SPEAR600)
+	printf("CPU:   SPEAr600\n");
+#else
+#error CPU not supported in spear platform
+#endif
+	return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index 8b96d9b52ae..b10c72607a5 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -126,5 +126,12 @@ struct misc_regs {
 
 /* PERIPH1_CLKEN, PERIPH1_RST value */
 #define MISC_USBDENB			0x01000000
+#define MISC_ETHENB			0x00800000
+#define MISC_SMIENB			0x00200000
+#define MISC_GPT3ENB			0x00010000
+#define MISC_GPT2ENB			0x00000800
+#define MISC_FSMCENB			0x00000200
+#define MISC_I2CENB			0x00000080
+#define MISC_UART0ENB			0x00000008
 
 #endif
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 669d83eb7eb..3a238945dcf 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -183,6 +183,8 @@
 #define CONFIG_ENV_SIZE				0x02000
 
 /* Miscellaneous configurable options */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
 #define CONFIG_CMDLINE_TAG			1
 #define CONFIG_SETUP_MEMORY_TAGS		1
-- 
cgit v1.3.1


From f273e5b2a6234f7fb486b8606258364a1cc655eb Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:46 +0530
Subject: SPEAr: Add configuration options for spear3xx and spear6xx boards

This patch adds options for all the below mentioned configurations and
subsequently renames the include/configs/spearxxx.h files to spear3xx_evb.h,
spear6xx_evb.h etc to depict evaluation board configuration.

SPEAr3xx and SPEAr6xx boards can be compiled in following configurations
1. Environment placed in NAND
2. Console on usb device
3. Console on usb device with environment placed in NAND
4. SPEAr310 and SPEAr320 support environment variables in parallel
NOR flash.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/spear/spear300/config.mk |  39 ----------
 board/spear/spear310/config.mk |  44 -----------
 board/spear/spear320/config.mk |  44 -----------
 board/spear/spear600/config.mk |  39 ----------
 boards.cfg                     |  24 +++++-
 doc/README.spear               |  50 +++++++++----
 include/configs/spear-common.h |   3 +
 include/configs/spear3xx.h     | 151 --------------------------------------
 include/configs/spear3xx_evb.h | 161 +++++++++++++++++++++++++++++++++++++++++
 include/configs/spear6xx.h     |  46 ------------
 include/configs/spear6xx_evb.h |  56 ++++++++++++++
 11 files changed, 274 insertions(+), 383 deletions(-)
 delete mode 100644 board/spear/spear300/config.mk
 delete mode 100644 board/spear/spear310/config.mk
 delete mode 100644 board/spear/spear320/config.mk
 delete mode 100644 board/spear/spear600/config.mk
 delete mode 100644 include/configs/spear3xx.h
 create mode 100644 include/configs/spear3xx_evb.h
 delete mode 100644 include/configs/spear6xx.h
 create mode 100644 include/configs/spear6xx_evb.h

(limited to 'include/configs')

diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk
deleted file mode 100644
index 5848ef89f89..00000000000
--- a/board/spear/spear300/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#########################################################################
-
-CONFIG_SYS_TEXT_BASE = 0x00700000
-
-ALL-y += $(obj)u-boot.img
-
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
-
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk
deleted file mode 100644
index f8a6bdb976c..00000000000
--- a/board/spear/spear310/config.mk
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#########################################################################
-
-CONFIG_SYS_TEXT_BASE = 0x00700000
-
-ALL-y += $(obj)u-boot.img
-
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
-
-# Support parallel flash
-ifeq ($(FLASH),PNOR)
-PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
-endif
-
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk
deleted file mode 100644
index f8a6bdb976c..00000000000
--- a/board/spear/spear320/config.mk
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#########################################################################
-
-CONFIG_SYS_TEXT_BASE = 0x00700000
-
-ALL-y += $(obj)u-boot.img
-
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
-
-# Support parallel flash
-ifeq ($(FLASH),PNOR)
-PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
-endif
-
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk
deleted file mode 100644
index 5848ef89f89..00000000000
--- a/board/spear/spear600/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#########################################################################
-
-CONFIG_SYS_TEXT_BASE = 0x00700000
-
-ALL-y += $(obj)u-boot.img
-
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
-
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
diff --git a/boards.cfg b/boards.cfg
index a864ac555c4..f28cb3142b1 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -178,10 +178,26 @@ omap730p2_cs0boot	     arm         arm926ejs   omap730p2		 ti             omap
 omap730p2_cs3boot	     arm         arm926ejs   omap730p2		 ti             omap        omap730p2:CS3_BOOT
 edminiv2                     arm         arm926ejs   -                   LaCie          orion5x
 dkb			     arm         arm926ejs   -                   Marvell        pantheon
-spear300                     arm         arm926ejs   spear300            spear          spear       spear3xx:spear300
-spear310                     arm         arm926ejs   spear310            spear          spear       spear3xx:spear310
-spear320                     arm         arm926ejs   spear320            spear          spear       spear3xx:spear320
-spear600                     arm         arm926ejs   spear600            spear          spear       spear6xx:spear600
+spear300                     arm         arm926ejs   spear300            spear          spear       spear3xx_evb:spear300
+spear300_nand                arm         arm926ejs   spear300            spear          spear       spear3xx_evb:spear300,nand
+spear300_usbtty              arm         arm926ejs   spear300            spear          spear       spear3xx_evb:spear300,usbtty
+spear300_usbtty_nand         arm         arm926ejs   spear300            spear          spear       spear3xx_evb:spear300,usbtty,nand
+spear310                     arm         arm926ejs   spear310            spear          spear       spear3xx_evb:spear310
+spear310_pnor                arm         arm926ejs   spear310            spear          spear       spear3xx_evb:spear310,FLASH_PNOR
+spear310_nand                arm         arm926ejs   spear310            spear          spear       spear3xx_evb:spear310,nand
+spear310_usbtty              arm         arm926ejs   spear310            spear          spear       spear3xx_evb:spear310,usbtty
+spear310_usbtty_pnor         arm         arm926ejs   spear310            spear          spear       spear3xx_evb:spear310,usbtty,FLASH_PNOR
+spear310_usbtty_nand         arm         arm926ejs   spear310            spear          spear       spear3xx_evb:spear310,usbtty,nand
+spear320                     arm         arm926ejs   spear320            spear          spear       spear3xx_evb:spear320
+spear320_pnor                arm         arm926ejs   spear320            spear          spear       spear3xx_evb:spear320,FLASH_PNOR
+spear320_nand                arm         arm926ejs   spear320            spear          spear       spear3xx_evb:spear320,nand
+spear320_usbtty              arm         arm926ejs   spear320            spear          spear       spear3xx_evb:spear320,usbtty
+spear320_usbtty_pnor         arm         arm926ejs   spear320            spear          spear       spear3xx_evb:spear320,usbtty,FLASH_PNOR
+spear320_usbtty_nand         arm         arm926ejs   spear320            spear          spear       spear3xx_evb:spear320,usbtty,nand
+spear600                     arm         arm926ejs   spear600            spear          spear       spear6xx_evb:spear600
+spear600_nand                arm         arm926ejs   spear600            spear          spear       spear6xx_evb:spear600,nand
+spear600_usbtty              arm         arm926ejs   spear600            spear          spear       spear6xx_evb:spear600,usbtty
+spear600_usbtty_nand         arm         arm926ejs   spear600            spear          spear       spear6xx_evb:spear600,usbtty,nand
 versatileab                  arm         arm926ejs   versatile           armltd         versatile   versatile:ARCH_VERSATILE_AB
 versatilepb                  arm         arm926ejs   versatile           armltd         versatile   versatile:ARCH_VERSATILE_PB
 versatileqemu                arm         arm926ejs   versatile           armltd         versatile   versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
diff --git a/doc/README.spear b/doc/README.spear
index a6ff7fdaefd..0789b3fd270 100644
--- a/doc/README.spear
+++ b/doc/README.spear
@@ -6,9 +6,10 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic
 The SPEAr SoC family embeds a customizable logic that can be programmed
 one-time by a customer at silicon mask level (i.e. not at runtime!).
 
-We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx.
+U-Boot supports four SoCs: SPEAr600, SPEAr3xx
 
-All 4 SoCs share common peripherals.
+All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr300 and
+SPEAr600 do not have EMI.
 
 1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux)
 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC)
@@ -22,7 +23,7 @@ All 4 SoCs share common peripherals.
 10. others ..
 
 Everything is supported in Linux.
-u-boot is not currently supporting all peripeharls (just a few as listed below).
+u-boot is currently not supporting all peripeharls (just a few as listed below).
 1. USB Device
 2. NAND controller (FSMC)
 3. Serial Memory Interface
@@ -31,21 +32,38 @@ u-boot is not currently supporting all peripeharls (just a few as listed below).
 5. UART
 
 Build options
-	make spear600_config
+	make spear320_config
+		spear320 build with environment variables placed at default
+		location i.e. Serial NOR device
+	make spear320_pnor_config
+		This option generates a uboot image that supports emi controller
+		for CFI compliant parallel NOR flash. Environment variables are
+		placed in Parallel NOR device
+	make spear320_nand_config
+		spear320 build with environment variables placed in NAND device
+	make spear320_usbtty_config
+		spear320 build with usbtty terminal as default and environment
+		placed at default location
+	make spear320_usbtty_pnor_config
+		spear320 build with usbtty terminal as default and environment
+		placed in pnor device
+	make spear320_usbtty_nand_config
+		Build with usbtty terminal as default and environment placed in
+		NAND device
 	make spear300_config
+	make spear300_nand_config
+	make spear300_usbtty_config
+	make spear300_usbtty_nand_config
 	make spear310_config
-	make spear320_config
-
-Further options
-	make ENV=NAND (supported by all 4 SoCs)
-	- This option generates a uboot image that saves environment inn NAND
-
-	make CONSOLE=USB (supported by all 4 SoCs)
-	- This option generates a uboot image for using usbdevice as a tty i/f
-
-	make FLASH=PNOR (supported by SPEAr310 and SPEAr320)
-	- This option generates a uboot image that supports emi controller for
-	CFI compliant parallel NOR flash
+	make spear310_pnor_config
+	make spear310_nand_config
+	make spear310_usbtty_config
+	make spear310_usbtty_pnor_config
+	make spear310_usbtty_nand_config
+	make spear600_config
+	make spear600_nand_config
+	make spear600_usbtty_config
+	make spear600_usbtty_nand_config
 
 Mac id storage and retrieval in spear platforms
 
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 3a238945dcf..2ba1090c95a 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -27,6 +27,9 @@
  * Common configurations used for both spear3xx as well as spear6xx
  */
 
+/* U-boot Load Address */
+#define CONFIG_SYS_TEXT_BASE			0x00700000
+
 /* Ethernet driver configuration */
 #define CONFIG_MII
 #define CONFIG_DESIGNWARE_ETH
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
deleted file mode 100644
index f3e335465df..00000000000
--- a/include/configs/spear3xx.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#if defined(CONFIG_spear300)
-#define CONFIG_SPEAR3XX				1
-#define CONFIG_SPEAR300				1
-#elif defined(CONFIG_spear310)
-#define CONFIG_SPEAR3XX				1
-#define CONFIG_SPEAR310				1
-#elif defined(CONFIG_spear320)
-#define CONFIG_SPEAR3XX				1
-#define CONFIG_SPEAR320				1
-#endif
-
-#include <configs/spear-common.h>
-
-/* Ethernet driver configuration */
-#define CONFIG_DW_ALTDESCRIPTOR			1
-
-#if defined(CONFIG_SPEAR310)
-#define CONFIG_MACB				1
-#define CONFIG_MACB0_PHY			0x01
-#define CONFIG_MACB1_PHY			0x03
-#define CONFIG_MACB2_PHY			0x05
-#define CONFIG_MACB3_PHY			0x07
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_MACB				1
-#define CONFIG_MACB0_PHY			0x01
-
-#endif
-
-/* Serial Configuration (PL011) */
-#define CONFIG_SYS_SERIAL0			0xD0000000
-
-#if defined(CONFIG_SPEAR300)
-#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
-
-#elif defined(CONFIG_SPEAR310)
-
-#if (CONFIG_CONS_INDEX)
-#undef  CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
-#endif
-
-#define CONFIG_SYS_SERIAL1			0xB2000000
-#define CONFIG_SYS_SERIAL2			0xB2080000
-#define CONFIG_SYS_SERIAL3			0xB2100000
-#define CONFIG_SYS_SERIAL4			0xB2180000
-#define CONFIG_SYS_SERIAL5			0xB2200000
-#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
-						(void *)CONFIG_SYS_SERIAL1, \
-						(void *)CONFIG_SYS_SERIAL2, \
-						(void *)CONFIG_SYS_SERIAL3, \
-						(void *)CONFIG_SYS_SERIAL4, \
-						(void *)CONFIG_SYS_SERIAL5 }
-#elif defined(CONFIG_SPEAR320)
-
-#if (CONFIG_CONS_INDEX)
-#undef  CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
-#endif
-
-#define CONFIG_SYS_SERIAL1			0xA3000000
-#define CONFIG_SYS_SERIAL2			0xA4000000
-#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
-						(void *)CONFIG_SYS_SERIAL1, \
-						(void *)CONFIG_SYS_SERIAL2 }
-#endif
-
-#if defined(CONFIG_SPEAR_EMI)
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#if defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_FLASH_BASE			0x50000000
-#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
-#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
-#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
-#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
-#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
-						CONFIG_SYS_CS1_FLASH_BASE, \
-						CONFIG_SYS_CS2_FLASH_BASE, \
-						CONFIG_SYS_CS3_FLASH_BASE, \
-						CONFIG_SYS_CS4_FLASH_BASE, \
-						CONFIG_SYS_CS5_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS		6
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_FLASH_BASE			0x44000000
-#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
-#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
-#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
-						CONFIG_SYS_CS1_FLASH_BASE, \
-						CONFIG_SYS_CS2_FLASH_BASE, \
-						CONFIG_SYS_CS3_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS		4
-
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
-#define CONFIG_SYS_FLASH_QUIET_TEST		1
-
-#endif
-
-/* NAND flash configuration */
-#define CONFIG_SYS_FSMC_NAND_SP
-#define CONFIG_SYS_FSMC_NAND_8BIT
-
-#if defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_NAND_BASE			(0x80000000)
-
-#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_NAND_BASE			(0x40000000)
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_NAND_BASE			(0x50000000)
-
-#endif
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
new file mode 100644
index 00000000000..d6fdc0932e0
--- /dev/null
+++ b/include/configs/spear3xx_evb.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#if defined(CONFIG_spear300)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR300				1
+#elif defined(CONFIG_spear310)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR310				1
+#elif defined(CONFIG_spear320)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR320				1
+#endif
+
+#if defined(CONFIG_usbtty)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#include <configs/spear-common.h>
+
+/* Ethernet driver configuration */
+#define CONFIG_DW_ALTDESCRIPTOR			1
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_MACB				1
+#define CONFIG_MACB0_PHY			0x01
+#define CONFIG_MACB1_PHY			0x03
+#define CONFIG_MACB2_PHY			0x05
+#define CONFIG_MACB3_PHY			0x07
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_MACB				1
+#define CONFIG_MACB0_PHY			0x01
+
+#endif
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
+
+#elif defined(CONFIG_SPEAR310)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xB2000000
+#define CONFIG_SYS_SERIAL2			0xB2080000
+#define CONFIG_SYS_SERIAL3			0xB2100000
+#define CONFIG_SYS_SERIAL4			0xB2180000
+#define CONFIG_SYS_SERIAL5			0xB2200000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2, \
+						(void *)CONFIG_SYS_SERIAL3, \
+						(void *)CONFIG_SYS_SERIAL4, \
+						(void *)CONFIG_SYS_SERIAL5 }
+#elif defined(CONFIG_SPEAR320)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xA3000000
+#define CONFIG_SYS_SERIAL2			0xA4000000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2 }
+#endif
+
+#if defined(CONFIG_SPEAR_EMI)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_BASE			0x50000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
+#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
+#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE, \
+						CONFIG_SYS_CS4_FLASH_BASE, \
+						CONFIG_SYS_CS5_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		6
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_BASE			0x44000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		4
+
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
+#define CONFIG_SYS_FLASH_QUIET_TEST		1
+
+#endif
+
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_NAND_BASE			(0x80000000)
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_NAND_BASE			(0x40000000)
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_NAND_BASE			(0x50000000)
+
+#endif
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h
deleted file mode 100644
index c5bcc30cb75..00000000000
--- a/include/configs/spear6xx.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SPEAR600				1
-
-#include <configs/spear-common.h>
-
-/* Serial Configuration (PL011) */
-#define CONFIG_SYS_SERIAL0			0xD0000000
-#define CONFIG_SYS_SERIAL1			0xD0080000
-#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
-						(void *)CONFIG_SYS_SERIAL1 }
-
-/* NAND flash configuration */
-#define CONFIG_SYS_FSMC_NAND_SP
-#define CONFIG_SYS_FSMC_NAND_8BIT
-#define CONFIG_SYS_NAND_BASE			(0xD2000000)
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
new file mode 100644
index 00000000000..18bd140fcc2
--- /dev/null
+++ b/include/configs/spear6xx_evb.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600				1
+
+#if defined(CONFIG_usbtty)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#include <configs/spear-common.h>
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_BASE			(0xD2000000)
+
+#endif  /* __CONFIG_H */
-- 
cgit v1.3.1


From 08166e19217cdcfd268760ecb7e94a3b1bdc4783 Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:47 +0530
Subject: SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)

SPEAr doesn't need CONFIG_SYS_HZ_CLOCK. This commit removes it.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 2ba1090c95a..dabd059d001 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -60,7 +60,6 @@
 
 /* Timer, HZ specific defines */
 #define CONFIG_SYS_HZ				(1000)
-#define CONFIG_SYS_HZ_CLOCK			(8300000)
 
 /* Flash configuration */
 #if defined(CONFIG_FLASH_PNOR)
-- 
cgit v1.3.1


From 1b7935cd96f2295d5cdf144fa46696fb60a820ef Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:48 +0530
Subject: SPEAr: Change the default environment variables

This patch modifies the default environment variables as:
1. Default bootargs:
 - console=ttyAMA0,115200
 - For environment present in NOR flash
     root=/dev/mtdblock3
 - For environment present in NAND flash
     root=/dev/mtdblock7
 - Removes "mem=" option
2. Introduces CONFIG_EXTRA_ENV_USBTTY as default usbtty env var even when usbtty
is not selected
3. Add default definitions for nfsboot and ramboot
4. Add a new default environment variable(CONFIG_EXTRA_ENV_UNLOCK) for SPEAr310
and SPEAr320

Signifacance of CONFIG_EXTRA_ENV_USBTTY:
This environment variable is important for flashing utility to work. So if
somebody accidently erases the env sector then also this variable must be
preserved so that flashing utility functions properly.

Signifacance of CONFIG_EXTRA_ENV_UNLOCK:
This env variable is read by the cfi driver to unlock all flash sectors.  This
is necessary because the Parallel NOR flash connected on the spear310 and
spear320 boards, M28W64, has all its sectors in locked state at reset and these
have to be unlocked explicitly before being erased or written.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 28 +++++++++++++++++++---------
 include/configs/spear3xx_evb.h | 10 ++++++++++
 include/configs/spear6xx_evb.h |  3 +++
 3 files changed, 32 insertions(+), 9 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index dabd059d001..cf09090ab17 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -46,9 +46,7 @@
 #define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
 #define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
 
-#if defined(CONFIG_USB_TTY)
 #define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
-#endif
 
 /* I2C driver configuration */
 #define CONFIG_HARD_I2C
@@ -143,7 +141,7 @@
  */
 #define CONFIG_SYS_MONITOR_LEN			0x00040000
 #define CONFIG_ENV_SECT_SIZE			0x00010000
-#define CONFIG_FSMTDBLK				"/dev/mtdblock8 "
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
 
 #define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
 
@@ -169,19 +167,33 @@
 
 #define CONFIG_ENV_OFFSET			0x60000
 #define CONFIG_ENV_RANGE			0x10000
-#define CONFIG_FSMTDBLK				"/dev/mtdblock12 "
+#define CONFIG_FSMTDBLK				"/dev/mtdblock7 "
 
 #define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
 						"0x80000 0x4C0000; " \
 						"bootm 0x1600000"
 #endif
 
-#define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
-						"console=ttyS0 init=/bin/sh"
-#define CONFIG_BOOTARGS				"console=ttyS0 mem=128M "  \
+#define CONFIG_BOOTARGS				"console=ttyAMA0,115200 " \
+						"mem=128M " \
 						"root="CONFIG_FSMTDBLK \
 						"rootfstype=jffs2"
 
+#define CONFIG_NFSBOOTCOMMAND						\
+	"bootp; "							\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$(serverip):$(rootpath) "				\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
+			"$(netmask):$(hostname):$(netdev):off "		\
+			"console=ttyAMA0,115200 $(othbootargs);"	\
+	"bootm; "
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=ttyAMA0,115200 $(othbootargs);"		\
+	CONFIG_BOOTCOMMAND
+
+
 #define CONFIG_ENV_SIZE				0x02000
 
 /* Miscellaneous configurable options */
@@ -212,8 +224,6 @@
 #define CONFIG_SYS_LOAD_ADDR			0x00800000
 #define CONFIG_SYS_CONSOLE_INFO_QUIET		1
 
-#define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_EXTRA_ENV_USBTTY
-
 /* Stack sizes */
 #define CONFIG_STACKSIZE			(128*1024)
 
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
index d6fdc0932e0..d6037851169 100644
--- a/include/configs/spear3xx_evb.h
+++ b/include/configs/spear3xx_evb.h
@@ -158,4 +158,14 @@
 
 #endif
 
+/* Environment Settings */
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
+
+#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320)
+#define CONFIG_EXTRA_ENV_UNLOCK                        "unlock=yes\0"
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY \
+						CONFIG_EXTRA_ENV_UNLOCK
+#endif
+
 #endif  /* __CONFIG_H */
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
index 18bd140fcc2..3e0f50bda8c 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear6xx_evb.h
@@ -53,4 +53,7 @@
 #define CONFIG_SYS_FSMC_NAND_8BIT
 #define CONFIG_SYS_NAND_BASE			(0xD2000000)
 
+/* Environment Settings */
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
+
 #endif  /* __CONFIG_H */
-- 
cgit v1.3.1


From 0b7ff3f4595f751ca796456f536c50cae498351d Mon Sep 17 00:00:00 2001
From: Amit Virdi <amit.virdi@st.com>
Date: Mon, 7 May 2012 13:06:49 +0530
Subject: SPEAr: Initialize SNOR in early_board_init_f

flash reading is required earlier than flash_init is called since the env_init
is called before flash_init. This makes the smi_init necessary before env_init
being called.

Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/spear/common/spr_misc.c  | 8 ++++++++
 include/configs/spear-common.h | 1 +
 2 files changed, 9 insertions(+)

(limited to 'include/configs')

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index e2918ff4056..043c72a05d3 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -25,6 +25,7 @@
 #include <command.h>
 #include <i2c.h>
 #include <net.h>
+#include <linux/mtd/st_smi.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_emi.h>
@@ -54,6 +55,13 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].size = gd->ram_size;
 }
 
+int board_early_init_f()
+{
+#if defined(CONFIG_ST_SMI)
+	smi_init();
+#endif
+	return 0;
+}
 int misc_init_r(void)
 {
 #if defined(CONFIG_CMD_NET)
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index cf09090ab17..c2dff8b45dd 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -198,6 +198,7 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
 #define CONFIG_CMDLINE_TAG			1
-- 
cgit v1.3.1


From 507266845025e0ff44892130292d51345596b0ba Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:50 +0530
Subject: SPEAr: Enable usb device high speed support

This patch enables the support for usb high speed device for spear platform SOCs

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index c2dff8b45dd..ec978962531 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -41,6 +41,7 @@
 /* USBD driver configuration */
 #define CONFIG_DW_UDC
 #define CONFIG_USB_DEVICE
+#define CONFIG_USBD_HS
 #define CONFIG_USB_TTY
 
 #define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
-- 
cgit v1.3.1


From b884236ec343ca1c24d4bf740fbf883ae16c1cd2 Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:51 +0530
Subject: SPEAr: Enable udc and usb-console support only for usbtty
 configuration

This patch enables the UDC and usb-console support only for usbtty
configurations

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index ec978962531..bd54a18465d 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -39,6 +39,7 @@
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 
 /* USBD driver configuration */
+#if defined(CONFIG_SPEAR_USBTTY)
 #define CONFIG_DW_UDC
 #define CONFIG_USB_DEVICE
 #define CONFIG_USBD_HS
@@ -47,6 +48,8 @@
 #define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
 #define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
 
+#endif
+
 #define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
 
 /* I2C driver configuration */
-- 
cgit v1.3.1


From 25b741a4efc280ab58e8a2d7b669de6d4ea4a7fb Mon Sep 17 00:00:00 2001
From: Shiraz Hashim <shiraz.hashim@st.com>
Date: Mon, 7 May 2012 13:06:52 +0530
Subject: SPEAr: Enable autoneg for ethernet

Enabling autoneg avoids situation on few phys with fixed configuration. For
example, in one situation, nfs boot timed out when phy configuration is 100Mbps.
In another situtation, when traffic is directed to SPEAr, either thru
cross-cable or thru switch, the TFTP or DHCP command in u-boot starts to timeout
very often.

When Autoneg is ON, same phys started working perfectly.

Reported-by: Deepak Sikri <deepak.sikri@st.com>
Reported-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index bd54a18465d..09604c5f101 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -37,6 +37,7 @@
 #define CONFIG_DW0_PHY				1
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+#define CONFIG_DW_AUTONEG
 
 /* USBD driver configuration */
 #if defined(CONFIG_SPEAR_USBTTY)
-- 
cgit v1.3.1


From 484e0b05f2dca43a827c950c91b31e151b48a8ef Mon Sep 17 00:00:00 2001
From: Vipin Kumar <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:54 +0530
Subject: SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION

This patch enables flash protection(lock/unlock) for CFI devices.
This is necessary because the Parallel NOR flash connected on the spear
boards, M28W64, can be locked/unlocked on a sector basis. Moreover, all its
sectors are in locked state at reset and these have to be unlocked explicitly
before being erased or written.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear3xx_evb.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
index d6037851169..242e648fc1d 100644
--- a/include/configs/spear3xx_evb.h
+++ b/include/configs/spear3xx_evb.h
@@ -111,6 +111,7 @@
 #define CONFIG_FLASH_CFI_DRIVER
 
 #if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_FLASH_BASE			0x50000000
 #define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
 #define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
@@ -126,6 +127,7 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS		6
 
 #elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_FLASH_BASE			0x44000000
 #define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
 #define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
-- 
cgit v1.3.1


From 0296f1599227280c24f53175ff04cce1faa10373 Mon Sep 17 00:00:00 2001
From: Vipin Kumar <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:55 +0530
Subject: SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE

The below text is copy pasted from README
- CONFIG_SYS_MONITOR_BASE:
	Physical start address of boot monitor code (set by
	make config files to be same as the text base address
	(TEXT_BASE) used when linking) - same as
	CONFIG_SYS_FLASH_BASE when booting from flash.

This patch corrects the definition of CONFIG_SYS_MONITOR_BASE and sets it to
TEXT_BASE

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 09604c5f101..0443bc6ebd2 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -162,8 +162,7 @@
 						"0x4C0000; bootm 0x1600000"
 #endif
 
-#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_FLASH_BASE + \
 						CONFIG_SYS_MONITOR_LEN)
 #elif defined(CONFIG_ENV_IS_IN_NAND)
 /*
@@ -200,6 +199,7 @@
 
 
 #define CONFIG_ENV_SIZE				0x02000
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
 
 /* Miscellaneous configurable options */
 #define CONFIG_ARCH_CPU_INIT
-- 
cgit v1.3.1


From cc4b5a34d294ba9fd8dad5a51bf84621310e685d Mon Sep 17 00:00:00 2001
From: Vipin Kumar <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:56 +0530
Subject: SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro

Enable CONFIG_SYS_FLASH_EMPTY_INFO macro to enable reporting of empty sector
information through flinfo command.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 0443bc6ebd2..4f067ebf4d2 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -81,7 +81,6 @@
 						CONFIG_SYS_CS1_FLASH_BASE}
 #define CONFIG_SYS_MAX_FLASH_SECT		128
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO		1
 #define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
 
@@ -230,6 +229,8 @@
 #define CONFIG_SYS_LOAD_ADDR			0x00800000
 #define CONFIG_SYS_CONSOLE_INFO_QUIET		1
 
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
 /* Stack sizes */
 #define CONFIG_STACKSIZE			(128*1024)
 
-- 
cgit v1.3.1


From bc912e78f4bad932096633815139cd003ad5c485 Mon Sep 17 00:00:00 2001
From: Vipin Kumar <vipin.kumar@st.com>
Date: Mon, 7 May 2012 13:06:57 +0530
Subject: SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 4f067ebf4d2..aa9ec5d9513 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -106,6 +106,8 @@
 #define CONFIG_NAND_FSMC
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE		1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_QUIET_TEST
 
 /*
  * Command support defines
-- 
cgit v1.3.1


From 8337aa5c0b22bc9e1d8ae9d7b2270735670233bd Mon Sep 17 00:00:00 2001
From: Amit Virdi <amit.virdi@st.com>
Date: Mon, 7 May 2012 13:06:58 +0530
Subject: SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access

When CONFIG_MTD_NAND_VERIFY_WRITE is defined, nand driver read back the data
everytime it writes. This process unnecessarily slows down the nand access.

Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index aa9ec5d9513..32e1fcc98d5 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -105,7 +105,6 @@
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_NAND_FSMC
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define CONFIG_MTD_NAND_VERIFY_WRITE		1
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_NAND_QUIET_TEST
 
-- 
cgit v1.3.1


From bc0bdf4c2296d02802ddfa76f349cbba3a869138 Mon Sep 17 00:00:00 2001
From: Amit Virdi <amit.virdi@st.com>
Date: Mon, 7 May 2012 13:07:01 +0530
Subject: cleanup/SPEAr: Remove unnecessary parenthesis

In SPEAr configuration files, unnecessary paranthesis are used in some
\#defines. Remove them as they serve no purpose

Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/arm/include/asm/arch-spear/spr_gpt.h | 4 ++--
 include/configs/spear-common.h            | 8 ++++----
 include/configs/spear3xx_evb.h            | 6 +++---
 include/configs/spear6xx_evb.h            | 2 +-
 4 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'include/configs')

diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h
index 965b5abb9ab..d95ba525973 100644
--- a/arch/arm/include/asm/arch-spear/spr_gpt.h
+++ b/arch/arm/include/asm/arch-spear/spr_gpt.h
@@ -79,7 +79,7 @@ struct gpt_regs {
 #define GPT_FREE_RUNNING		0xFFFF
 
 /* Timer, HZ specific defines */
-#define CONFIG_SPEAR_HZ			(1000)
-#define CONFIG_SPEAR_HZ_CLOCK		(8300000)
+#define CONFIG_SPEAR_HZ			1000
+#define CONFIG_SPEAR_HZ_CLOCK		8300000
 
 #endif
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 32e1fcc98d5..0aa9551bfe3 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -62,7 +62,7 @@
 #define CONFIG_I2C_CHIPADDRESS			0x50
 
 /* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ				(1000)
+#define CONFIG_SYS_HZ				1000
 
 /* Flash configuration */
 #if defined(CONFIG_FLASH_PNOR)
@@ -74,9 +74,9 @@
 #if defined(CONFIG_ST_SMI)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS		2
-#define CONFIG_SYS_FLASH_BASE			(0xF8000000)
-#define CONFIG_SYS_CS1_FLASH_BASE		(0xF9000000)
-#define CONFIG_SYS_FLASH_BANK_SIZE		(0x01000000)
+#define CONFIG_SYS_FLASH_BASE			0xF8000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
+#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
 #define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
 						CONFIG_SYS_CS1_FLASH_BASE}
 #define CONFIG_SYS_MAX_FLASH_SECT		128
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
index 242e648fc1d..d63c9dff399 100644
--- a/include/configs/spear3xx_evb.h
+++ b/include/configs/spear3xx_evb.h
@@ -150,13 +150,13 @@
 #define CONFIG_SYS_FSMC_NAND_8BIT
 
 #if defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_NAND_BASE			(0x80000000)
+#define CONFIG_SYS_NAND_BASE			0x80000000
 
 #elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_NAND_BASE			(0x40000000)
+#define CONFIG_SYS_NAND_BASE			0x40000000
 
 #elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_NAND_BASE			(0x50000000)
+#define CONFIG_SYS_NAND_BASE			0x50000000
 
 #endif
 
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
index 3e0f50bda8c..4a761341a81 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear6xx_evb.h
@@ -51,7 +51,7 @@
 /* NAND flash configuration */
 #define CONFIG_SYS_FSMC_NAND_SP
 #define CONFIG_SYS_FSMC_NAND_8BIT
-#define CONFIG_SYS_NAND_BASE			(0xD2000000)
+#define CONFIG_SYS_NAND_BASE			0xD2000000
 
 /* Environment Settings */
 #define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
-- 
cgit v1.3.1


From 9b382b43a1db000a78822ad9e1814577dd2e1a19 Mon Sep 17 00:00:00 2001
From: Amit Virdi <amit.virdi@st.com>
Date: Mon, 7 May 2012 13:07:02 +0530
Subject: cleanup/SPEAr: Define configuration flags more elegantly

In SPEAr, some of the configuration flags eg. CONFIG_SPEAR_EMI, were given value
"1", which isn't required. Define the flags without assigning any value

Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/spear-common.h | 14 +++++++-------
 include/configs/spear3xx_evb.h | 20 ++++++++++----------
 include/configs/spear6xx_evb.h |  2 +-
 3 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 0aa9551bfe3..36c2a8b1654 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -66,7 +66,7 @@
 
 /* Flash configuration */
 #if defined(CONFIG_FLASH_PNOR)
-#define CONFIG_SPEAR_EMI			1
+#define CONFIG_SPEAR_EMI
 #else
 #define CONFIG_ST_SMI
 #endif
@@ -206,11 +206,11 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
-#define CONFIG_CMDLINE_TAG			1
-#define CONFIG_SETUP_MEMORY_TAGS		1
-#define CONFIG_MISC_INIT_R			1
-#define CONFIG_ZERO_BOOTDELAY_CHECK		1
-#define CONFIG_AUTOBOOT_KEYED			1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
 #define CONFIG_AUTOBOOT_STOP_STR		" "
 #define CONFIG_AUTOBOOT_PROMPT			\
 		"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
@@ -228,7 +228,7 @@
 #define CONFIG_SYS_MAXARGS			16
 #define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LOAD_ADDR			0x00800000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET		1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
index d63c9dff399..3cd56dc4873 100644
--- a/include/configs/spear3xx_evb.h
+++ b/include/configs/spear3xx_evb.h
@@ -29,14 +29,14 @@
  * (easy to change)
  */
 #if defined(CONFIG_spear300)
-#define CONFIG_SPEAR3XX				1
-#define CONFIG_SPEAR300				1
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR300
 #elif defined(CONFIG_spear310)
-#define CONFIG_SPEAR3XX				1
-#define CONFIG_SPEAR310				1
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR310
 #elif defined(CONFIG_spear320)
-#define CONFIG_SPEAR3XX				1
-#define CONFIG_SPEAR320				1
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR320
 #endif
 
 #if defined(CONFIG_usbtty)
@@ -52,17 +52,17 @@
 #include <configs/spear-common.h>
 
 /* Ethernet driver configuration */
-#define CONFIG_DW_ALTDESCRIPTOR			1
+#define CONFIG_DW_ALTDESCRIPTOR
 
 #if defined(CONFIG_SPEAR310)
-#define CONFIG_MACB				1
+#define CONFIG_MACB
 #define CONFIG_MACB0_PHY			0x01
 #define CONFIG_MACB1_PHY			0x03
 #define CONFIG_MACB2_PHY			0x05
 #define CONFIG_MACB3_PHY			0x07
 
 #elif defined(CONFIG_SPEAR320)
-#define CONFIG_MACB				1
+#define CONFIG_MACB
 #define CONFIG_MACB0_PHY			0x01
 
 #endif
@@ -141,7 +141,7 @@
 #endif
 
 #define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
-#define CONFIG_SYS_FLASH_QUIET_TEST		1
+#define CONFIG_SYS_FLASH_QUIET_TEST
 
 #endif
 
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
index 4a761341a81..31b872552cd 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear6xx_evb.h
@@ -28,7 +28,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_SPEAR600				1
+#define CONFIG_SPEAR600
 
 #if defined(CONFIG_usbtty)
 #define CONFIG_SPEAR_USBTTY
-- 
cgit v1.3.1


From ef76025a99247cdb8f927a2c9f15400678dfb599 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 7 May 2012 12:04:25 +0200
Subject: net: Multiple updates/enhancements to designware.c

This patch adds the following changes to designware ethernet driver
found on the ST SPEAr SoC:

- Don't init MAC & PHY upon startup. This causes a delay, waiting for
  the auto negotiation to complete. And we don't want this delay to
  always happen. Especially not on platforms where ethernet is not
  used at all (e.g. booting via flash).
  Instead postpone the MAC / PHY configuration to the stage, where
  ethernet is first used.
- Add possibility for board specific PHY init code. This is needed
  for example on the X600 board, where the Vitesse PHY needs to be
  configured for GMII mode.
  This board specific PHY init is done via the function
  designware_board_phy_init(). And this driver now adds a weak default
  which can be overridden by board code.
- Use common functions miiphy_speed() & miiphy_duplex() to read
  link status from PHY.
- Print status and progress of auto negotiation.
- Print link status (speed, dupex) upon first usage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
---
 drivers/net/designware.c       | 118 +++++++++++++++++------------------------
 drivers/net/designware.h       |   1 +
 include/configs/spear-common.h |   1 +
 3 files changed, 51 insertions(+), 69 deletions(-)

(limited to 'include/configs')

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8f22e00ddd8..326d550c1f2 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <malloc.h>
+#include <linux/compiler.h>
 #include <linux/err.h>
 #include <asm/io.h>
 #include "designware.h"
@@ -153,6 +154,13 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 	if (priv->phy_configured != 1)
 		configure_phy(dev);
 
+	/* Print link status only once */
+	if (!priv->link_printed) {
+		printf("ENET Speed is %d Mbps - %s duplex connection\n",
+		       priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
+		priv->link_printed = 1;
+	}
+
 	/* Reset ethernet hardware */
 	if (mac_reset(dev) < 0)
 		return -1;
@@ -168,17 +176,17 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 
 	conf = FRAMEBURSTENABLE | DISABLERXOWN;
 
-	if (priv->speed != SPEED_1000M)
+	if (priv->speed != 1000)
 		conf |= MII_PORTSELECT;
 
 	if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
 		(priv->interface != PHY_INTERFACE_MODE_GMII)) {
 
-		if (priv->speed == SPEED_100M)
+		if (priv->speed == 100)
 			conf |= FES_100;
 	}
 
-	if (priv->duplex == FULL_DUPLEX)
+	if (priv->duplex == FULL)
 		conf |= FULLDPLXMODE;
 
 	writel(conf, &mac_p->conf);
@@ -396,6 +404,16 @@ static int dw_reset_phy(struct eth_device *dev)
 	return 0;
 }
 
+/*
+ * Add weak default function for board specific PHY configuration
+ */
+int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
+		int (*mii_write)(struct eth_device *, u8, u8, u16),
+		int dw_reset_phy(struct eth_device *))
+{
+	return 0;
+}
+
 static int configure_phy(struct eth_device *dev)
 {
 	struct dw_eth_dev *priv = dev->priv;
@@ -405,9 +423,6 @@ static int configure_phy(struct eth_device *dev)
 	u16 bmsr;
 	u32 timeout;
 	ulong start;
-	u16 anlpar, btsr;
-#else
-	u16 ctrl;
 #endif
 
 #if defined(CONFIG_DW_SEARCH_PHY)
@@ -419,6 +434,16 @@ static int configure_phy(struct eth_device *dev)
 #else
 	phy_addr = priv->address;
 #endif
+
+	/*
+	 * Some boards need board specific PHY initialization. This is
+	 * after the main driver init code but before the auto negotiation
+	 * is run.
+	 */
+	if (designware_board_phy_init(dev, phy_addr,
+				      eth_mdio_write, dw_reset_phy) < 0)
+		return -1;
+
 	if (dw_reset_phy(dev) < 0)
 		return -1;
 
@@ -444,72 +469,32 @@ static int configure_phy(struct eth_device *dev)
 #if defined(CONFIG_DW_AUTONEG)
 	timeout = CONFIG_AUTONEG_TIMEOUT;
 	start = get_timer(0);
-
+	puts("Waiting for PHY auto negotiation to complete");
 	while (get_timer(start) < timeout) {
 		eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
-		if (bmsr & BMSR_ANEGCOMPLETE)
+		if (bmsr & BMSR_ANEGCOMPLETE) {
+			priv->phy_configured = 1;
 			break;
-
-		/* Try again after 10usec */
-		udelay(10);
-	};
-
-	eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
-	eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
-
-	if (bmsr & BMSR_ANEGCOMPLETE) {
-		if (btsr & PHY_1000BTSR_1000FD) {
-			priv->speed = SPEED_1000M;
-			bmcr |= BMCR_SPEED1000;
-			priv->duplex = FULL_DUPLEX;
-			bmcr |= BMCR_FULLDPLX;
-		} else if (btsr & PHY_1000BTSR_1000HD) {
-			priv->speed = SPEED_1000M;
-			bmcr |= BMCR_SPEED1000;
-			priv->duplex = HALF_DUPLEX;
-			bmcr &= ~BMCR_FULLDPLX;
-		} else if (anlpar & LPA_100FULL) {
-			priv->speed = SPEED_100M;
-			bmcr |= BMCR_SPEED100;
-			priv->duplex = FULL_DUPLEX;
-			bmcr |= BMCR_FULLDPLX;
-		} else if (anlpar & LPA_100HALF) {
-			priv->speed = SPEED_100M;
-			bmcr |= BMCR_SPEED100;
-			priv->duplex = HALF_DUPLEX;
-			bmcr &= ~BMCR_FULLDPLX;
-		} else if (anlpar & LPA_10FULL) {
-			priv->speed = SPEED_10M;
-			bmcr &= ~BMCR_SPEED100;
-			priv->duplex = FULL_DUPLEX;
-			bmcr |= BMCR_FULLDPLX;
-		} else {
-				priv->speed = SPEED_10M;
-				bmcr &= ~BMCR_SPEED100;
-				priv->duplex = HALF_DUPLEX;
-				bmcr &= ~BMCR_FULLDPLX;
 		}
-		if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
-			return -1;
-	} else
-		return -1;
-#else
-	if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
-		return -1;
 
-	if (ctrl & BMCR_FULLDPLX)
-		priv->duplex = FULL_DUPLEX;
-	else
-		priv->duplex = HALF_DUPLEX;
+		/* Print dot all 1s to show progress */
+		if ((get_timer(start) % 1000) == 0)
+			putc('.');
+
+		/* Try again after 1msec */
+		udelay(1000);
+	};
 
-	if (ctrl & BMCR_SPEED1000)
-		priv->speed = SPEED_1000M;
-	else if (ctrl & BMCR_SPEED100)
-		priv->speed = SPEED_100M;
+	if (!(bmsr & BMSR_ANEGCOMPLETE))
+		puts(" TIMEOUT!\n");
 	else
-		priv->speed = SPEED_10M;
-#endif
+		puts(" done\n");
+#else
 	priv->phy_configured = 1;
+#endif
+
+	priv->speed = miiphy_speed(dev->name, phy_addr);
+	priv->duplex = miiphy_duplex(dev->name, phy_addr);
 
 	return 0;
 }
@@ -574,11 +559,6 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
 	priv->phy_configured = 0;
 	priv->interface = interface;
 
-	if (mac_reset(dev) < 0)
-		return -1;
-
-	configure_phy(dev);
-
 	dev->init = dw_eth_init;
 	dev->send = dw_eth_send;
 	dev->recv = dw_eth_recv;
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 40020bf26b8..d668f8fbf0e 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -240,6 +240,7 @@ struct dw_eth_dev {
 	u32 tx_currdescnum;
 	u32 rx_currdescnum;
 	u32 phy_configured;
+	int link_printed;
 	u32 padding;
 
 	struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 36c2a8b1654..a6d1cfbcb0e 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -38,6 +38,7 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 #define CONFIG_DW_AUTONEG
+#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
 
 /* USBD driver configuration */
 #if defined(CONFIG_SPEAR_USBTTY)
-- 
cgit v1.3.1


From 4324c75fccf1e87a58b216300e396dc1eb55a5f6 Mon Sep 17 00:00:00 2001
From: "esw@bus-elektronik.de" <esw@bus-elektronik.de>
Date: Mon, 16 Jan 2012 00:22:02 +0000
Subject: add new board vl_ma2sc

* add support for board VL+MA2SC
* adds vl_ma2sc_config for standard NOR boot configuration
* adds vl_ma2sc_ram_config for RAM load configuration

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
---
 MAINTAINERS                   |   1 +
 board/BuS/vl_ma2sc/Makefile   |  48 ++++
 board/BuS/vl_ma2sc/vl_ma2sc.c | 551 ++++++++++++++++++++++++++++++++++++++++++
 boards.cfg                    |   2 +
 include/configs/vl_ma2sc.h    | 463 +++++++++++++++++++++++++++++++++++
 5 files changed, 1065 insertions(+)
 create mode 100644 board/BuS/vl_ma2sc/Makefile
 create mode 100644 board/BuS/vl_ma2sc/vl_ma2sc.c
 create mode 100644 include/configs/vl_ma2sc.h

(limited to 'include/configs')

diff --git a/MAINTAINERS b/MAINTAINERS
index e42a32708ad..6893a0a3d4c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -848,6 +848,7 @@ Steve Sakoman <sakoman@gmail.com>
 Jens Scharsig <esw@bus-elektronik.de>
 
 	eb_cpux9k2	ARM920T (AT91RM9200 SoC)
+	vl_ma2sc	ARM926EJS (AT91SAM9263 SoC)
 
 Heiko Schocher <hs@denx.de>
 
diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile
new file mode 100644
index 00000000000..1cadfb30e09
--- /dev/null
+++ b/board/BuS/vl_ma2sc/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009-2012
+# Jens Scharsig  <esw@bus-elekronik.de>
+# BuS Elektronik GmbH & Co. KG
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS += vl_ma2sc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
new file mode 100644
index 00000000000..62ed6fb432b
--- /dev/null
+++ b/board/BuS/vl_ma2sc/vl_ma2sc.c
@@ -0,0 +1,551 @@
+/*
+ * (C) Copyright 2009-2012
+ * Jens Scharsig  <esw@bus-elekronik.de>
+ * BuS Elektronik GmbH & Co. KG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_common.h>
+#include <lcd.h>
+#include <i2c.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void vl_ma2sc_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t	*smc	= (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t	*matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_pio_output(AT91_PIO_PORTA, 13, 1);	/* CAN_TX -> H */
+	at91_set_pio_output(AT91_PIO_PORTA, 12, 1);	/* CAN_STB -> H */
+	at91_set_pio_output(AT91_PIO_PORTA, 11, 1);	/* CAN_EN -> H */
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+	writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
+		&pmc->pcer);
+
+	/* Configure RDY/BSY */
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void vl_ma2sc_macb_hw_init(void)
+{
+	unsigned long	erstl;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_rstc_t	*rstc	= (at91_rstc_t *) ATMEL_BASE_RSTC;
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+	/* Need to reset PHY -> 500ms reset */
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+	/* Wait for end hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col =		320,
+	.vl_row =		240,
+	.vl_clk =		6500000,
+	.vl_sync =		ATMEL_LCDC_INVDVAL_INVERTED |
+				ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVVD_INVERTED   |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		(ATMEL_LCDC_PIXELSIZE_8 >> 5),
+	.vl_tft =		1,
+	.vl_hsync_len =		5,	/* Horiz Sync Pulse Width */
+	.vl_left_margin =	68,	/* horiz back porch */
+	.vl_right_margin =	20,	/* horiz front porch */
+	.vl_vsync_len =		2,	/* vert Sync Pulse Width */
+	.vl_upper_margin =	18,	/* vert back porch */
+	.vl_lower_margin =	4,	/* vert front porch */
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+static void vl_ma2sc_lcd_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+
+	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+
+	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+
+	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD26 */
+	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD17 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	at91_set_pio_output(AT91_PIO_PORTE, 0, 0);	/* LCD QXH */
+
+	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* LCD SHUT */
+	at91_set_pio_output(AT91_PIO_PORTE, 3, 1);	/* LCD TopBottom */
+	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);	/* LCD REV */
+	at91_set_pio_output(AT91_PIO_PORTE, 5, 1);	/* LCD RightLeft */
+	at91_set_pio_output(AT91_PIO_PORTE, 6, 0);	/* LCD Color Mode CM */
+	at91_set_pio_output(AT91_PIO_PORTE, 7, 0);	/* LCD BGR */
+
+	at91_set_pio_output(AT91_PIO_PORTB, 9, 0);	/* LCD CC */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	gd->fb_base = ATMEL_BASE_SRAM0;
+}
+#endif /* Config LCD */
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOCDE),
+		&pmc->pcer);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	at91_smc_t	*smc	= (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	u32		pin;
+
+	pin = 0x1F000001;
+	writel(pin, &pio->pioa.idr);
+	writel(pin, &pio->pioa.pudr);
+	writel(pin, &pio->pioa.per);
+	writel(pin, &pio->pioa.oer);
+	writel(pin, &pio->pioa.sodr);
+	writel((1 << 25), &pio->pioa.codr);
+
+	pin = 0x1F000100;
+	writel(pin, &pio->piob.idr);
+	writel(pin, &pio->piob.pudr);
+	writel(pin, &pio->piob.per);
+	writel(pin, &pio->piob.oer);
+	writel(pin, &pio->piob.codr);
+	writel((1 << 24), &pio->piob.sodr);
+
+	pin = 0x40000000;			/* Pullup DRxD enbable */
+	writel(pin, &pio->pioc.puer);
+
+	pin = 0x0000000F;			/* HWversion als Input */
+	writel(pin, &pio->piod.idr);
+	writel(pin, &pio->piod.puer);
+	writel(pin, &pio->piod.per);
+	writel(pin, &pio->piod.odr);
+	writel(pin, &pio->piod.owdr);
+
+	/* Enable Ctrlc */
+	console_init_f();
+
+	gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
+	writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
+	writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
+	writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
+
+#ifdef CONFIG_CMD_NAND
+	vl_ma2sc_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	vl_ma2sc_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	vl_ma2sc_lcd_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	uchar	buffer[8];
+	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	u32		pin;
+
+	buffer[0] = 0x04;
+	buffer[1] = 0x00;
+	if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
+		puts("error reseting rtc clock\n\0");
+
+	/* read hardware version */
+
+	pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
+	printf("Board: revision %c\n", pin);
+	buffer[0] = pin;
+	buffer[1] = 0;
+	setenv("revision", (char *) buffer);
+
+	pin = 0x40000000;			/* Pullup DRxD enbable */
+	writel(pin, &pio->pioc.puer);
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_SOFT_I2C
+void i2c_init_board(void)
+{
+	u32 pin;
+
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	u8 sda = (1<<4);
+	u8 scl = (1<<5);
+
+	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
+	pin = sda | scl;
+	writel(pin, &pio->piob.idr);	/* Disable Interupt */
+	writel(pin, &pio->piob.pudr);
+	writel(pin, &pio->piob.per);
+	writel(pin, &pio->piob.oer);
+	writel(pin, &pio->piob.sodr);
+}
+#endif
+
+void watchdog_reset(void)
+{
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	u32	pin = 0x1;	/* PA0 */
+
+	if ((readl(&pio->pioa.odsr) & pin) > 0)
+		writel(pin, &pio->pioa.codr);
+	else
+		writel(pin, &pio->pioa.sodr);
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+/*---------------------------------------------------------------------------*/
+
+int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = 1;
+	int row;
+	int col;
+	u32 pinz;
+	u32 pins;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+	at91_set_pio_output(AT91_PIO_PORTB, 8, 0);	/* LCD DIM */
+
+	pins = 0x1F000000;
+	writel(pins, &pio->pioa.idr);
+	writel(pins, &pio->pioa.pudr);
+	writel(pins, &pio->pioa.per);
+	writel(pins, &pio->pioa.oer);
+	writel(pins, &pio->pioa.sodr);
+
+	pinz = 0x1F000000;
+	writel(pinz, &pio->piob.idr);
+	writel(pinz, &pio->piob.pudr);
+	writel(pinz, &pio->piob.per);
+	writel(pinz, &pio->piob.oer);
+	writel(pinz, &pio->piob.sodr);
+
+	for (row = 0; row < 5; row++) {
+		for (col = 0; col < 5; col++) {
+			writel((0x01000000 << col), &pio->piob.sodr);
+			writel((0x01000000 << row), &pio->pioa.codr);
+			printf("LED Test %d x %d\n", row, col);
+			udelay(1000000);
+			writel(pinz, &pio->piob.codr);
+			writel(pins, &pio->pioa.sodr);
+		}
+	}
+	return rcode;
+}
+
+void poweroff(void)
+{
+	watchdog_reset();
+	at91_set_pio_output(AT91_PIO_PORTA, 13, 1);	/* CAN_TX -> H */
+	udelay(100);
+	at91_set_pio_output(AT91_PIO_PORTA, 12, 0);	/* CAN_STB -> L */
+	udelay(100);
+	at91_set_pio_output(AT91_PIO_PORTA, 11, 0);	/* CAN_EN -> L */
+	udelay(100);
+	while (1)
+		watchdog_reset();
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc,  char * const argv[])
+{
+	int rcode = 1;
+	poweroff();
+	return rcode;
+}
+
+int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	u32 freq;
+	u32 durate;
+	int rcode = 1;
+
+	freq = 1000;
+	durate = 2;
+	switch (argc) {
+	case 3:
+		durate = simple_strtoul(argv[2], NULL, 10);
+	case 2:
+		freq = simple_strtoul(argv[1], NULL, 10);
+	case 1:
+		break;
+	default:
+		cmd_usage(cmdtp);
+		rcode = 1;
+		break;
+	}
+	durate = durate * freq;
+	freq = 500000 / freq;
+	for (i = 0; i < durate; i++) {
+		at91_set_pio_output(AT91_PIO_PORTB, 29, 1);	/* Sound On*/
+		udelay(freq);
+		at91_set_pio_output(AT91_PIO_PORTB, 29, 0);	/* Sound Off*/
+		udelay(freq);
+	}
+	at91_set_pio_output(AT91_PIO_PORTB, 29, 0);	/* Sound Off*/
+	return rcode;
+}
+
+int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = 1;
+	int row;
+	u32 col;
+	u32 pinz;
+	u32 pins;
+	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
+
+	pins = 0x001F0000;
+	writel(pins, &pio->pioa.idr);
+	writel(pins, &pio->pioa.pudr);
+	writel(pins, &pio->pioa.per);
+	writel(pins, &pio->pioa.odr);
+
+	pinz = 0x000F0000;
+	writel(pinz, &pio->piob.idr);
+	writel(pinz, &pio->piob.pudr);
+	writel(pinz, &pio->piob.per);
+	writel(pinz, &pio->piob.oer);
+	writel(pinz, &pio->piob.codr);
+
+	while (1) {
+		col = 0;
+		for (row = 0; row < 4; row++) {
+			writel((0x00010000 << row), &pio->piob.sodr);
+			udelay(10000);
+			col <<= 4;
+			col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
+			writel(pinz, &pio->piob.codr);
+		}
+		printf("Matix: ");
+		for (row = 0; row < 16; row++) {
+			printf("%1.1d", col & 1);
+			col >>= 1;
+		}
+		printf(" SP %d\r ",
+			1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
+		if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
+			/* SHUTDOWN */
+			row = 0;
+			while (row < 1000) {
+				if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
+					row++;
+				udelay(100);
+			}
+			udelay(100000);
+			row = 0;
+			while (row < 1000) {
+				if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
+					row++;
+					udelay(1000);
+				}
+			}
+			poweroff();
+			while (1)
+				;
+		}
+	}
+	return rcode;
+}
+
+/*****************************************************************************/
+
+U_BOOT_CMD(
+	ledtest,	1,	0,	do_ledtest,
+	"test ledmatrix",
+	"\n"
+	);
+
+U_BOOT_CMD(
+	keytest,	1,	0,	do_keytest,
+	"test keymatix and special keys, poweroff on pressing ON key",
+	"\n"
+	);
+
+U_BOOT_CMD(
+	poweroff,	1,	0,	do_poweroff,
+	"power off",
+	"\n"
+	);
+
+U_BOOT_CMD(
+	beep,	3,	0,	do_beep,
+	"[freq [duration]]",
+	"freq frequence of beep\nduration duration of beep\n"
+	);
+
+/*****************************************************************************/
diff --git a/boards.cfg b/boards.cfg
index f28cb3142b1..52375d500d6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -94,6 +94,8 @@ at91sam9xeek_dataflash_cs1   arm         arm926ejs   at91sam9260ek       atmel
 at91sam9xeek_nandflash       arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
 snapper9260                  arm         arm926ejs   -                   bluewater      at91        snapper9260:AT91SAM9260
 snapper9g20                  arm         arm926ejs   snapper9260         bluewater      at91        snapper9260:AT91SAM9G20
+vl_ma2sc                     arm         arm926ejs   vl_ma2sc            BuS            at91
+vl_ma2sc_ram                 arm         arm926ejs   vl_ma2sc            BuS            at91        vl_ma2sc:RAMLOAD
 sbc35_a9g20_eeprom           arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
 sbc35_a9g20_nandflash        arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
 tny_a9260_eeprom             arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9260,SYS_USE_EEPROM
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
new file mode 100644
index 00000000000..24f89c98e40
--- /dev/null
+++ b/include/configs/vl_ma2sc.h
@@ -0,0 +1,463 @@
+/*
+ * (C) Copyright 2009-2012
+ * Jens Scharsig  <esw@bus-elekronik.de>
+ * BuS Elektronik GmbH & Co. KG
+ *
+ * Configuation settings for the VL_MA2SC board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*--------------------------------------------------------------------------*/
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define CONFIG_ARM926EJS		/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91FAMILY
+#define CONFIG_AT91SAM9263		/* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_VL_MA2SC			/* on an VL_MA2SC Board	*/
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_MISC_INIT_R
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_VL_MA2SC		2412
+#define CONFIG_MACH_TYPE		MACH_TYPE_VL_MA2SC
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_RAMLOAD
+#define CONFIG_SYS_TEXT_BASE		0x21000000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#endif
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CONFIG_IDENT_STRING		" on MiS Activ 2"
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AT91_GPIO
+
+#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
+#define CONFIG_SYS_USE_NORFLASH
+#define CONFIG_SYS_USE_BOOT_NORFLASH
+#endif
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_WATCHDOG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_ATMEL_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_BLACK_ON_WHITE
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_ATMEL_LCD_BGR555
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_CMD_SHA1SUM
+/*
+#define CONFIG_CMD_SPI
+*/
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define	CONFIG_SYS_LONGHELP
+#define CONFIG_MD5
+#define	CONFIG_SHA1
+
+/*----------------------------------------------------------------------------
+ * Hardware confuguration
+ *---------------------------------------------------------------------------*/
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_AT91C_PQFP_UHPBUG
+
+/* I2C-Bus */
+
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0		/* not used */
+
+#ifndef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C
+
+/* Software  I2C driver configuration */
+
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#define AT91_PIN_SDA	(1<<4)		/* AT91C_PIO_PB4 */
+#define AT91_PIN_SCL	(1<<5)		/* AT91C_PIO_PB5 */
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(AT91_PIN_SDA, &pio->piob.mddr);
+#define I2C_TRISTATE	writel(AT91_PIN_SDA, &pio->piob.mder);
+#define I2C_READ	((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
+#define I2C_SDA(bit)						\
+	do {							\
+		if (bit)					\
+			writel(AT91_PIN_SDA, &pio->piob.sodr);	\
+		else						\
+			writel(AT91_PIN_SDA, &pio->piob.codr);	\
+	} while (0);
+#define I2C_SCL(bit)						\
+	do {							\
+		if (bit)					\
+			writel(AT91_PIN_SCL, &pio->piob.sodr);	\
+		else						\
+			writel(AT91_PIN_SCL, &pio->piob.codr);	\
+	} while (0);
+#endif
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_MR_URSTEN |		\
+		AT91_RSTC_MR_ERSTL(15))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xFFF) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xFFF))
+
+/* clocks */
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */
+
+#define MHZ180
+#if defined(MHZ199)
+/* 199,8994 MHZ */
+#define MASTER_PLL_MUL		911
+#define MASTER_PLL_DIV		56
+#define MASTER_PLL_OUT		2
+#elif defined(MHZ180)
+/* 180 MHZ */
+#define MASTER_PLL_MUL		1875
+#define MASTER_PLL_DIV		128
+#define MASTER_PLL_OUT		2
+#elif defined(MHZTEST)
+/* Test MHZ */
+#define CONFIG_DISPLAY_CPUINFO
+#define MASTER_PLL_MUL		8
+#define MASTER_PLL_DIV		1
+#define MASTER_PLL_OUT		2
+#else
+/* 176.9472 MHZ */
+#define MASTER_PLL_MUL		72
+#define MASTER_PLL_DIV		5
+#define MASTER_PLL_OUT		2
+#endif
+
+#define CONFIG_SYS_MOR_VAL					\
+	(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+
+#define CONFIG_SYS_PLLAR_VAL					\
+	(AT91_PMC_PLLAR_29 |					\
+	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
+	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
+	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |		\
+	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
+	 AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |	\
+	AT91_PMC_MCKR_MDIV_2)
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000  /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR		0x00504000  /* use internal SRAM0 */
+
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+#define CONFIG_SYS_SDRC_TR_VAL1		700
+#define CONFIG_SYS_SDRC_CR_VAL						\
+		(AT91_SDRAMC_NC_9 |					\
+		 AT91_SDRAMC_NR_13 |					\
+		 AT91_SDRAMC_NB_4 |					\
+		 AT91_SDRAMC_CAS_3 |					\
+		 AT91_SDRAMC_DBW_32 |					\
+		 (2 <<  8) |		/* Write Recovery Delay */	\
+		 (7 << 12) |		/* Row Cycle Delay */		\
+		 (2 << 16) |		/* Row Precharge Delay */	\
+		 (2 << 20) |		/* Row to Column Delay */	\
+		 (5 << 24) |		/* Active to Precharge Delay */	\
+		 (8 << 28))		/* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* NOR flash */
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define PHYS_FLASH_1			0x10000000
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00060000)
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
+	 AT91_SMC_MODE_DBW_16 |					\
+	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 0
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		5
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x21e00000
+
+/* Address and size of Primary Environment Sector */
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			0x20000
+#else
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{312500, 230400, 115200, 19200, \
+						38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		\
+	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifndef CONFIG_RAMLOAD
+#define CONFIG_BOOTCOMMAND		"run nfsboot"
+#endif
+#define CONFIG_BOOT_RETRY_TIME		-1
+#define CONFIG_BOOT_RETRY_MIN		15
+
+#define CONFIG_NFSBOOTCOMMAND						\
+		"dhcp $(copy_addr) $(kernelname);"			\
+		"run bootargsdefaults;"					\
+		"set bootargs $(bootargs) boot=nfs "			\
+		";echo $(bootargs)"					\
+	";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ubootaddr=10000000\0"						\
+	"splashimage=10080000\0"					\
+	"kerneladdr=100A0000\0"						\
+	"kernelsize=00800000\0"						\
+	"minifsaddr=108A0000\0"						\
+	"minifssize=00060000\0"						\
+	"rootfsaddr=10900000\0"						\
+	"copy_addr=20200000\0"						\
+	"rootfssize=01700000\0"						\
+	"kernelname=uImage_vl_ma2sc\0"					\
+	"bootargsdefaults=set bootargs "				\
+		"console=ttyS0,115200 "					\
+		"video=atmel_lcdfb "					\
+		"mem=62M "						\
+		"panic=10 "						\
+		"boardrevison=\\\"${revision}\\\" "			\
+		"uboot=\\\"${ver}\\\" "					\
+		"\0"							\
+	"update_all=run update_kernel;run update_root;"			\
+		"run update_splash; run update_uboot\0"			\
+	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
+		"dhcp $(copy_addr) $(kernelname);"			\
+		"erase $(kerneladdr) +$(kernelsize);"			\
+		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
+		"protect on $(kerneladdr) +$(kernelsize)"		\
+		"\0"							\
+	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
+		"dhcp $(copy_addr) vl_ma2sc.root;"			\
+		"erase $(rootfsaddr) +$(rootfssize);"			\
+		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
+		"\0"							\
+	"update_splash=protect off $(splashimage) +20000;"		\
+		"dhcp $(copy_addr) splash_vl_ma2sc.bmp;"		\
+		"erase $(splashimage) +20000;"				\
+		"cp.b $(fileaddr) 10080000 $(filesize);"		\
+		"protect on $(splashimage) +20000\0"			\
+	"update_uboot=protect off 10000000 1005FFFF;"			\
+		"dhcp $(copy_addr) u-boot_vl_ma2sc;"			\
+		"erase 10000000 1005FFFF;"				\
+		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
+		"protect on 10000000 1005FFFF;reset\0"			\
+	"emergency=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(kerneladdr)\0"				\
+	"netemergency=run bootargsdefaults;"				\
+		"dhcp $(copy_addr) $(kernelname);"			\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(copy_addr)\0"					\
+	"norboot=run bootargsdefaults;"					\
+		"set bootargs $(bootargs) root=initramfs boot=local quiet " \
+		";bootm $(kerneladdr)\0"				\
+	"nandboot=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=nand "	\
+		";bootm $(kerneladdr)\0"				\
+	"setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0"	\
+	"clearenv=protect off 10060000 1007FFFF;"			\
+		"erase 10060000 1007FFFF;reset\0"			\
+	" "
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
-- 
cgit v1.3.1


From 5427d29c26bd980c37e449687fa8456598a57c91 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Thu, 1 Mar 2012 04:02:39 +0000
Subject: No need to define CONFIG_ARCH_CPU_INIT.

All mx6 based boards should use arch_cpu_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
---
 arch/arm/cpu/armv7/mx6/soc.c    | 2 --
 include/configs/mx6qarm2.h      | 1 -
 include/configs/mx6qsabrelite.h | 1 -
 3 files changed, 4 deletions(-)

(limited to 'include/configs')

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 90f208809ba..84b458c7eb0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -43,7 +43,6 @@ u32 get_cpu_rev(void)
 	return system_rev;
 }
 
-#ifdef CONFIG_ARCH_CPU_INIT
 void init_aips(void)
 {
 	struct aipstz_regs *aips1, *aips2;
@@ -113,7 +112,6 @@ int arch_cpu_init(void)
 
 	return 0;
 }
-#endif
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index a155c772341..a9c1b1545e0 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -37,7 +37,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
-#define CONFIG_ARCH_CPU_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MXC_GPIO
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 5b566a8f2b7..fd25fafeabd 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -40,7 +40,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN	       (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
-#define CONFIG_ARCH_CPU_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
-- 
cgit v1.3.1


From c27c07b86b0a9ff71e3c4788d74cee50c7ed2283 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Thu, 1 Mar 2012 04:02:40 +0000
Subject: ARM: mx28: Remove CONFIG_ARCH_CPU_INIT

No need to define CONFIG_ARCH_CPU_INIT.

All mx28 based boards should use arch_cpu_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
---
 arch/arm/cpu/arm926ejs/mx28/mx28.c | 2 --
 include/configs/m28evk.h           | 1 -
 include/configs/mx28evk.h          | 1 -
 3 files changed, 4 deletions(-)

(limited to 'include/configs')

diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index a82ff2564bd..ff25772099b 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -153,7 +153,6 @@ int arch_misc_init(void)
 }
 #endif
 
-#ifdef	CONFIG_ARCH_CPU_INIT
 int arch_cpu_init(void)
 {
 	struct mx28_clkctrl_regs *clkctrl_regs =
@@ -187,7 +186,6 @@ int arch_cpu_init(void)
 
 	return 0;
 }
-#endif
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index a0e90ca694a..f12d927e038 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -40,7 +40,6 @@
 #define	CONFIG_SYS_ICACHE_OFF
 #define	CONFIG_SYS_DCACHE_OFF
 #define	CONFIG_BOARD_EARLY_INIT_F
-#define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_ARCH_MISC_INIT
 
 /*
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 640dcb4be7c..8f60496d355 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -34,7 +34,6 @@
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ARCH_CPU_INIT
 #define CONFIG_ARCH_MISC_INIT
 
 /*
-- 
cgit v1.3.1


From aac316a8b025a93295b0a82822313503976e85be Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 8 Mar 2012 05:41:23 +0000
Subject: PXA: Enable CONFIG_PREBOOT on zipitz2

Signed-off-by: Marek Vasut <marex@denx.de>
---
 include/configs/zipitz2.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index a330bd01a4b..8e6377019bf 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -32,6 +32,7 @@
 #undef	CONFIG_BOARD_LATE_INIT
 #undef	CONFIG_USE_IRQ
 #undef	CONFIG_SKIP_LOWLEVEL_INIT
+#define	CONFIG_PREBOOT
 
 /*
  * Environment settings
-- 
cgit v1.3.1