From 7dd6af85bc1c798108561a162aa7aba21d054b6a Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 23 Aug 2022 16:29:14 +0200 Subject: imx: imx6ul: kontron-sl-mx6ul: Migrate to use CONFIG_EXTRA_ENV_TEXT Move the environment from the board header to a separate text file and also drop those variables that are already set in env_default.h from the Kconfig options or are not needed anymore. Signed-off-by: Frieder Schrempf --- include/configs/kontron-sl-mx6ul.h | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'include/configs') diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 7aac5d3f5a1..f0586f7f721 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -49,14 +49,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "scriptaddr=0x80100000\0" \ - "bootdelay=3\0" \ - "ethact=" CONFIG_ETHPRIME "\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - BOOTENV +#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV #endif /* __KONTRON_MX6UL_CONFIG_H */ -- cgit v1.3.1 From 27effdd16b94e32fb6f6288ed197e06e0600b044 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 24 Aug 2022 15:59:09 +0200 Subject: imx: kontron-sl-mx8mm: Migrate to use CONFIG_EXTRA_ENV_TEXT Move the environment from the board header to a separate text file and also drop those variables that are already set in env_default.h from the Kconfig options. Signed-off-by: Frieder Schrempf Reviewed-by: Fabio Estevam --- board/kontron/sl-mx8mm/sl-mx8mm.env | 7 +++++++ include/configs/kontron-sl-mx8mm.h | 16 +--------------- 2 files changed, 8 insertions(+), 15 deletions(-) create mode 100644 board/kontron/sl-mx8mm/sl-mx8mm.env (limited to 'include/configs') diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.env b/board/kontron/sl-mx8mm/sl-mx8mm.env new file mode 100644 index 00000000000..ef6fc1f3428 --- /dev/null +++ b/board/kontron/sl-mx8mm/sl-mx8mm.env @@ -0,0 +1,7 @@ +kernel_addr_r=0x42000000 +fdt_addr_r=0x48000000 +fdtoverlay_addr_r=0x49000000 +ramdisk_addr_r=0x48080000 +scriptaddr=0x40000000 +pxefile_addr_r=0x40100000 +dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000 diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 622ab597624..a2aedefcec2 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -50,20 +50,6 @@ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif -#define ENV_MEM_LAYOUT_SETTINGS \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "kernel_addr_r=0x42000000\0" \ - "fdt_addr_r=0x48000000\0" \ - "fdtoverlay_addr_r=0x49000000\0" \ - "ramdisk_addr_r=0x48080000\0" \ - "scriptaddr=0x40000000\0"\ - "pxefile_addr_r=0x40100000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \ - "bootdelay=3\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV +#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV #endif /* __KONTRON_MX8MM_CONFIG_H */ -- cgit v1.3.1 From 5302576e933ef8611d726c0f244be306ffc40c18 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Sep 2022 21:35:56 +0200 Subject: ARM: dts: imx8mm: Swap i.MX8M Mini Menlo board UARTs back The first production revision of the MX8M Mini Menlo board implements a hardware change which swaps console UART and another UART connector. Implement the swap, which maps the console UART back to the way Verdin console is mapped. Signed-off-by: Marek Vasut --- arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi | 18 +----------------- board/menlo/mx8menlo/mx8menlo.c | 2 +- include/configs/imx8mm-mx8menlo.h | 2 +- 3 files changed, 3 insertions(+), 19 deletions(-) (limited to 'include/configs') diff --git a/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi b/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi index 66cc97842c0..484d493e33c 100644 --- a/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi @@ -6,7 +6,7 @@ / { chosen { - stdout-path = &uart2; + stdout-path = &uart1; }; aliases { @@ -20,19 +20,3 @@ &i2c4 { /delete-node/ codec@1a; }; - -&pinctrl_uart1 { - /delete-property/ u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&uart1 { - /delete-property/ u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index 61fc4ec85f0..18f5fd5c5ee 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -14,5 +14,5 @@ void board_early_init(void) { - init_uart_clk(1); + init_uart_clk(0); } diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index 530ecd1d460..938c5406b82 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -25,7 +25,7 @@ "fi ; " \ "boot\0" \ "boot_file=fitImage\0" \ - "console=ttymxc1\0" \ + "console=ttymxc0\0" \ "fdt_addr=0x43000000\0" \ "initrd_addr=0x43800000\0" \ "kernel_image=fitImage\0" -- cgit v1.3.1 From 8d2cbb096ca980b4935f22abe92e20e29c089a00 Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Tue, 20 Sep 2022 18:05:41 +0200 Subject: board: tbs2910: Add serial rx buffer in defconfig ... to avoid loosing characters when pasting text into the serial console. This allows to remove the workaround to disable the vidconsole output when no HDMI device is detected. This workaround only was there to speed-up serial console processing. Signed-off-by: Soeren Moch Reviewed-by: Fabio Estevam --- configs/tbs2910_defconfig | 3 ++- include/configs/tbs2910.h | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'include/configs') diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 59444372e93..20de590e276 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -24,7 +24,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc rescan; if run bootcmd_up1; then run bootcmd_up2; else run bootcmd_mmc || run distro_bootcmd; fi" CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi" +CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start" CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_HUSH_PARSER=y @@ -89,6 +89,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y CONFIG_DM_SERIAL=y +CONFIG_SERIAL_RX_BUFFER=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index c93df00d58d..7f197851d0a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -61,10 +61,6 @@ "pxefile_addr_r=0x10100000\0" \ "ramdisk_addr_r=0x18080000\0" \ "scriptaddr=0x10000000\0" \ - "set_con_serial=setenv stdout serial; " \ - "setenv stderr serial\0" \ - "set_con_hdmi=setenv stdout serial,vidconsole; " \ - "setenv stderr serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" -- cgit v1.3.1 From 16d6457d844e48ef4c8231fae3f4535a61c05f24 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 21 Sep 2022 13:34:19 +0200 Subject: verdin-imx8mm: verdin-imx8mp: drop obsolete net/phy configs Drop obsolete networking/PHY related configuration defines. Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam Reviewed-by: Ramon Fried --- include/configs/verdin-imx8mm.h | 3 --- include/configs/verdin-imx8mp.h | 8 -------- 2 files changed, 11 deletions(-) (limited to 'include/configs') diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 4d20b86591f..1dae9919789 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -67,9 +67,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* ENET */ -#define CONFIG_FEC_MXC_PHYADDR 7 - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 9b8db223bb2..69235cb42cb 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -25,14 +25,6 @@ #define CONFIG_SYS_I2C #endif /* CONFIG_SPL_BUILD */ -/* ENET Config */ -/* ENET1 */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 7 - -#define PHY_ANEG_TIMEOUT 20000 -#endif /* CONFIG_CMD_NET */ - #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x50200000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ -- cgit v1.3.1 From 187da7226c2c01499a98fd6ac088b9a1c5f3b07b Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Tue, 27 Sep 2022 11:24:53 -0300 Subject: nitrogen6x: Remove extra quotes in fdtfile After commit 395110284b56 ("nitrogen6x: Populate FDTFILE at build-time for all platforms") iMX.6Q Sabrelite fails to boot due to a bad fdtfile string: Retrieving file: /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb ** File not found /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb ** CONFIG_DEFAULT_DEVICE_TREE option is string typed, so __stringify() is adding extra quotes. Remove this. Signed-off-by: Ariel D'Alessandro Reviewed-by: Fabio Estevam Acked-by: Troy Kisky --- include/configs/nitrogen6x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 2007b48868f..26e6de2d2c8 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -76,7 +76,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ - "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ -- cgit v1.3.1 From 7fe2408b829faeaf51101a8c9b1bc0c3957606c3 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 27 Sep 2022 17:50:52 +0200 Subject: apalis/colibri_imx6/-imx6ull/_imx7: update env memory layout Update the distro config env memory layout for the Apalis iMX6, Colibri iMX6, Colibri iMX6ULL and Colibri iMX7: - loadaddr=0x84200000 (resp. 0x14200000 on them i.MX 6) allows for 64MB area for uncompressing (ie FIT images) - fdt_addr_r = loadaddr + 64MB : allows for 64MB kernel - scriptaddr = fdt_addr_r + 512KB : allows for 512KB fdt - pxefile_addr_r = scriptaddr + 512KB : allows for 512KB script - ramdisk_addr_r = pxefile_addr_r + 512KB : allows for 1MB extlinux.conf Memory layout analogous to 64-bit one from commit fd5c7173ade4 ("imx8m{m,n}_venice: update env memory layout") but left pxefile_addr_r updated according to doc/develop/distro.rst. This fixes a potential issue caused by the compressed kernel being relocated on top of the ramdisk causing its corruption. Signed-off-by: Marcel Ziswiler --- configs/apalis_imx6_defconfig | 1 + configs/colibri-imx6ull-emmc_defconfig | 1 + configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx6_defconfig | 1 + configs/colibri_imx7_defconfig | 1 + configs/colibri_imx7_emmc_defconfig | 1 + include/configs/apalis_imx6.h | 10 +++++----- include/configs/colibri-imx6ull.h | 10 +++++----- include/configs/colibri_imx6.h | 10 +++++----- include/configs/colibri_imx7.h | 10 +++++----- 10 files changed, 26 insertions(+), 20 deletions(-) (limited to 'include/configs') diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 5960aef698f..2689e8d9846 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_CMD_HDMIDETECT=y +CONFIG_SYS_LOAD_ADDR=0x14200000 CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index e6ed9b5fd0f..02b6be0a2b4 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -10,6 +10,7 @@ CONFIG_DM_GPIO=y CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc-eval-v3" CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +CONFIG_SYS_LOAD_ADDR=0x84200000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index d65f2533ca2..cc0a3473941 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -11,6 +11,7 @@ CONFIG_DM_GPIO=y CONFIG_TARGET_COLIBRI_IMX6ULL_NAND=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-eval-v3" CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +CONFIG_SYS_LOAD_ADDR=0x84200000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 5cf398b09e2..135095b275d 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_CMD_HDMIDETECT=y +CONFIG_SYS_LOAD_ADDR=0x14200000 CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index dfdb74f69b0..28872639b61 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_PROMPT="Colibri iMX7 # " CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y +CONFIG_SYS_LOAD_ADDR=0x84200000 CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8c000000 diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 033ce1747bf..c12717b4f25 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -12,6 +12,7 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y +CONFIG_SYS_LOAD_ADDR=0x84200000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 4922b063309..8f338943475 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -70,11 +70,11 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ - "fdt_addr_r=0x12100000\0" \ - "kernel_addr_r=0x11000000\0" \ - "pxefile_addr_r=0x17100000\0" \ - "ramdisk_addr_r=0x12200000\0" \ - "scriptaddr=0x17000000\0" + "fdt_addr_r=0x18200000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=0x18300000\0" \ + "ramdisk_addr_r=0x18400000\0" \ + "scriptaddr=0x18280000\0" #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 04cde9530ad..79b1284cc7a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -43,11 +43,11 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x82100000\0" \ - "kernel_addr_r=0x81000000\0" \ - "pxefile_addr_r=0x87100000\0" \ - "ramdisk_addr_r=0x82200000\0" \ - "scriptaddr=0x87000000\0" + "fdt_addr_r=0x88200000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=0x88300000\0" \ + "ramdisk_addr_r=0x88400000\0" \ + "scriptaddr=0x88280000\0" #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 3c220e0d6e3..d8b87366238 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -66,11 +66,11 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x12100000\0" \ - "kernel_addr_r=0x11000000\0" \ - "pxefile_addr_r=0x17100000\0" \ - "ramdisk_addr_r=0x12200000\0" \ - "scriptaddr=0x17000000\0" + "fdt_addr_r=0x18200000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=0x18300000\0" \ + "ramdisk_addr_r=0x18400000\0" \ + "scriptaddr=0x18280000\0" #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 9543e0233ee..b8d0dc959a7 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -83,11 +83,11 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x82000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "pxefile_addr_r=0x87100000\0" \ - "ramdisk_addr_r=0x82100000\0" \ - "scriptaddr=0x87000000\0" + "fdt_addr_r=0x88200000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=0x88300000\0" \ + "ramdisk_addr_r=0x88400000\0" \ + "scriptaddr=0x88280000\0" #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ -- cgit v1.3.1 From 39236acb0d97074618f4110f01ab20cfc246cec0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 28 Sep 2022 18:45:18 +0200 Subject: ARM: imx6: dh-imx6: Use sf update instead of sf erase and write With sf update fixed to support unaligned start offset, use plain sf update to update the bootloader in SPI NOR. This also helps avoid the case where not enough SPI NOR has been erased and the bootloader has been written to unerased area, and thus corrupted. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- include/configs/dh_imx6.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 0f7e1c5c451..2040deb2b87 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -60,8 +60,7 @@ "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ "load mmc 0:1 ${loadaddr} /boot/u-boot-with-spl.imx && "\ - "sf probe && sf erase 0x0 0x100000 && " \ - "sf write ${loadaddr} 0x400 ${filesize}\0" \ + "sf probe && sf update ${loadaddr} 0x400 ${filesize}\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ -- cgit v1.3.1 From 864ac2cf383e4b8008f09db2e7e53318093c431e Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Fri, 26 Aug 2022 18:03:37 +0530 Subject: board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Manoj Sai --- .../dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 149 ++ arch/arm/mach-imx/imx8m/Kconfig | 15 + board/engicam/imx8mp/Kconfig | 15 + board/engicam/imx8mp/MAINTAINERS | 7 + board/engicam/imx8mp/Makefile | 12 + board/engicam/imx8mp/icore_mx8mp.c | 73 + board/engicam/imx8mp/imximage-lpddr4.cfg | 8 + board/engicam/imx8mp/lpddr4_timing.c | 1850 ++++++++++++++++++++ board/engicam/imx8mp/spl.c | 152 ++ configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 112 ++ include/configs/imx8mp_evk.h | 6 +- include/configs/imx8mp_icore_mx8mp.h | 64 + 12 files changed, 2459 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi create mode 100644 board/engicam/imx8mp/Kconfig create mode 100644 board/engicam/imx8mp/MAINTAINERS create mode 100644 board/engicam/imx8mp/Makefile create mode 100644 board/engicam/imx8mp/icore_mx8mp.c create mode 100644 board/engicam/imx8mp/imximage-lpddr4.cfg create mode 100644 board/engicam/imx8mp/lpddr4_timing.c create mode 100644 board/engicam/imx8mp/spl.c create mode 100644 configs/imx8mp-icore-mx8mp-edimm2.2_defconfig create mode 100644 include/configs/imx8mp_icore_mx8mp.h (limited to 'include/configs') diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi new file mode 100644 index 00000000000..342c523b0c5 --- /dev/null +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&i2c4 { + u-boot,dm-spl; +}; + +&i2c5 { + u-boot,dm-spl; +}; + +&i2c6 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + no-1-8-v; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +ðphy0 { + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <15000>; + reset-post-delay-us = <100000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3470160990b..8cd7c7a8dd8 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -160,6 +160,20 @@ config TARGET_IMX8MP_DH_DHCOM_PDK2 select IMX8M_LPDDR4 select SUPPORT_SPL +config TARGET_IMX8MP_ICORE_MX8MP + bool "Engicam i.Core MX8M Plus SOM" + select BINMAN + select IMX8MP + select IMX8M_LPDDR4 + select SUPPORT_SPL + help + i.Core MX8M Plus is an EDIMM SOM based on NXP i.MX8MP. + + i.Core MX8M Plus EDIMM2.2: + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. + * i.Core MX8M Plus needs to mount on top of EDIMM2.2 for + creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. + config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" select BINMAN @@ -287,6 +301,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/data_modul/imx8mm_edm_sbc/Kconfig" source "board/dhelectronics/dh_imx8mp/Kconfig" source "board/engicam/imx8mm/Kconfig" +source "board/engicam/imx8mp/Kconfig" source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" diff --git a/board/engicam/imx8mp/Kconfig b/board/engicam/imx8mp/Kconfig new file mode 100644 index 00000000000..ada500ec43b --- /dev/null +++ b/board/engicam/imx8mp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MP_ICORE_MX8MP + +config SYS_BOARD + default "imx8mp" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "imx8mp_icore_mx8mp" + +config IMX_CONFIG + default "board/engicam/imx8mp/imximage-lpddr4.cfg" + +endif diff --git a/board/engicam/imx8mp/MAINTAINERS b/board/engicam/imx8mp/MAINTAINERS new file mode 100644 index 00000000000..a25908a76c7 --- /dev/null +++ b/board/engicam/imx8mp/MAINTAINERS @@ -0,0 +1,7 @@ +i.Core-MX8M-Plus-EDIMM2.2 +M: Manoj Sai +M: Matteo Lisi +S: Maintained +F: board/engicam/imx8mp +F: include/configs/imx8mp_icore_mx8mp.h +F: configs/imx8mp-icore-mx8mp-edimm2.2_defconfig diff --git a/board/engicam/imx8mp/Makefile b/board/engicam/imx8mp/Makefile new file mode 100644 index 00000000000..c3ec09d6e38 --- /dev/null +++ b/board/engicam/imx8mp/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2020 Amarula Solutions(India) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += icore_mx8mp.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c new file mode 100644 index 00000000000..b309a12df08 --- /dev/null +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Engicam S.r.l. + * Copyright (C) 2022 Amarula Solutions(India) + * + * Authors: + * Manoj Sai + * Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (CONFIG_IS_ENABLED(FEC_MXC)) + setup_fec(); + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + setup_eqos(); + + return 0; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/engicam/imx8mp/imximage-lpddr4.cfg b/board/engicam/imx8mp/imximage-lpddr4.cfg new file mode 100644 index 00000000000..8aadedb1028 --- /dev/null +++ b/board/engicam/imx8mp/imximage-lpddr4.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/engicam/imx8mp/lpddr4_timing.c b/board/engicam/imx8mp/lpddr4_timing.c new file mode 100644 index 00000000000..4444180c5c2 --- /dev/null +++ b/board/engicam/imx8mp/lpddr4_timing.c @@ -0,0 +1,1850 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c new file mode 100644 index 00000000000..6a16d58ae5a --- /dev/null +++ b/board/engicam/imx8mp/spl.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Amarula Solutions(India) + * Copyright (C) 2016 Engicam S.r.l. + * + * Authors: + * Manoj Sai + * Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#if CONFIG_IS_ENABLED(POWER_LEGACY) +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_pca9450_init(I2C_PMIC, 0x25); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + +#ifdef CONFIG_IMX8M_LPDDR4 + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ +#ifdef CONFIG_IMX8M_VDD_SOC_850MV + /* set DVS0 to 0.85v for special case*/ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); +#else + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); +#elif defined(CONFIG_IMX8M_DDR4) + /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set NVCC_DRAM to 1.2v for DDR4 */ + pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18); +#endif + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} +#endif + +void spl_board_init(void) +{ + /* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it. + * Should set the clock after PMIC setting done. + * Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig new file mode 100644 index 00000000000..dc2a3c23d56 --- /dev/null +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -0,0 +1,112 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-icore-mx8mp-edimm2.2.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 388f3bc9ffe..140eba3d1cb 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -55,11 +55,9 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -/* Totally 6GB DDR */ +/* Totally 2GB DDR */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ -#define PHYS_SDRAM_2 0x100000000 -#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ +#define PHYS_SDRAM_SIZE 0x80000000 #endif diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h new file mode 100644 index 00000000000..28d44163e4f --- /dev/null +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2022 Amarula Solutions(India) + */ + +#ifndef __IMX8MP_ICORE_MX8MP_H +#define __IMX8MP_ICORE_MX8MP_H + +#include +#include +#include + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ + +#define CONFIG_POWER_PCA9450 + +#endif + +#if defined(CONFIG_CMD_NET) +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define DWC_NET_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 + +/* Totally 2GB DDR */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 + +#endif /* __IMX8MP_ICORE_MX8MP_H */ -- cgit v1.3.1 From 559c5389c2f0229eb35b03a9b9eb72040903e890 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Sep 2022 23:28:32 +0200 Subject: verdin-imx8mm: verdin-imx8mp: update env memory layout (again) Update the distro config env memory layout for the Verdin iMX8M Mini and Verdin iMX8M Plus again: - loadaddr=0x48200000 allows for 128MB area for uncompressing (ie FIT images, kernel_comp_addr_r, kernel_comp_size) - fdt_addr_r = loadaddr + 128MB - allows for 128MB kernel - scriptaddr = fdt_addr_r + 512KB - allows for 512KB fdt - ramdisk_addr_r = scriptaddr + 512KB - allows for 512KB script Memory layout taken from commit fd5c7173ade4 ("imx8m{m,n}_venice: update env memory layout"). Note that for our regular BSP Layers and Reference Images for Yocto Project an updated distro boot script is required (see meta-toradex-bsp-common/recipes-bsp/u-boot/u-boot-distro-boot). Note that this corrects a pre-maturely applied version 2 of the same patch set. Fixes: bbe0089d29e ("verdin-imx8mm: verdin-imx8mp: update env memory layout") Signed-off-by: Marcel Ziswiler --- configs/verdin-imx8mm_defconfig | 2 +- configs/verdin-imx8mp_defconfig | 2 +- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 230fe55d068..8ed4c872b66 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -19,7 +19,7 @@ CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_LOAD_ADDR=0x48280000 +CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 5d0c57c52e4..071a2223d41 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x48280000 +CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 1dae9919789..1de00234f0a 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -23,7 +23,7 @@ "fdt_addr_r=0x50200000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_comp_addr_r=0x40200000\0" \ - "kernel_comp_size=0x08080000\0" \ + "kernel_comp_size=0x08000000\0" \ "ramdisk_addr_r=0x50300000\0" \ "scriptaddr=0x50280000\0" diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 69235cb42cb..ce727985148 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -29,7 +29,7 @@ "fdt_addr_r=0x50200000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_comp_addr_r=0x40200000\0" \ - "kernel_comp_size=0x08080000\0" \ + "kernel_comp_size=0x08000000\0" \ "ramdisk_addr_r=0x50300000\0" \ "scriptaddr=0x50280000\0" -- cgit v1.3.1