From 32556443840f127170e4baa8bdd5b567039f6c36 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 21 Apr 2007 21:07:22 +0200 Subject: [PATCH] SystemACE support for Microblaze --- include/configs/ml401.h | 26 +++++++++++++++++--------- include/configs/xupv2p.h | 14 ++++++++------ 2 files changed, 25 insertions(+), 15 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ml401.h b/include/configs/ml401.h index f4a8a1f2285..15c2fe7ecd1 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -36,7 +36,7 @@ #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } /* setting reset address */ -#define CFG_RESET_ADDRESS TEXT_BASE +//#define CFG_RESET_ADDRESS TEXT_BASE /* ethernet */ #define CONFIG_EMACLITE 1 @@ -66,7 +66,7 @@ * * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 - * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 + * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 * * 0x1000_0000 CFG_SDRAM_BASE * FREE @@ -93,7 +93,8 @@ /* global pointer */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ -#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */ +/* start of global data */ +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 @@ -152,6 +153,8 @@ CFG_CMD_IMI |\ CFG_CMD_NET |\ CFG_CMD_CACHE |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ CFG_CMD_IMLS |\ CFG_CMD_FLASH |\ CFG_CMD_PING \ @@ -174,6 +177,8 @@ CFG_CMD_FLASH |\ CFG_CMD_PING |\ CFG_CMD_ENV |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ CFG_CMD_SAVES \ ) @@ -189,6 +194,8 @@ CFG_CMD_BDI |\ CFG_CMD_RUN |\ CFG_CMD_LOADS |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ CFG_CMD_LOADB |\ CFG_CMD_IMI |\ CFG_CMD_NET |\ @@ -221,10 +228,11 @@ #define CFG_HZ 1000 /* system ace */ -/*#define CONFIG_SYSTEMACE -#define DEBUG_SYSTEMACE -#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -#define CONFIG_DOS_PARTITION -*/ +#define CONFIG_SYSTEMACE +/* #define DEBUG_SYSTEMACE */ +#define SYSTEMACE_CONFIG_FPGA +#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +#define CONFIG_DOS_PARTITION + #endif /* __CONFIG_H */ diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 224db5c8be1..c89ef7ce5c1 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -132,6 +132,8 @@ CFG_CMD_LOADS |\ CFG_CMD_LOADB |\ CFG_CMD_MISC |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ CFG_CMD_PING \ ) @@ -163,12 +165,12 @@ "base 0;" \ "echo" - /* system ace */ -/*#define CONFIG_SYSTEMACE -#define DEBUG_SYSTEMACE -#define CFG_SYSTEMACE_BASE 0xCF000000 -#define CFG_SYSTEMACE_WIDTH 16 -#define CONFIG_DOS_PARTITION*/ +#define CONFIG_SYSTEMACE +/* #define DEBUG_SYSTEMACE */ +#define SYSTEMACE_CONFIG_FPGA +#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +#define CONFIG_DOS_PARTITION #endif /* __CONFIG_H */ -- cgit v1.3.1 From 96b8a05432f346f36493535c85320b70ec9c7c1b Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Apr 2007 14:54:15 -0500 Subject: mpc83xx: Add MPC8313ERDB support. Signed-off-by: Scott Wood --- Makefile | 13 + board/mpc8313erdb/Makefile | 50 ++++ board/mpc8313erdb/config.mk | 1 + board/mpc8313erdb/mpc8313erdb.c | 116 ++++++++ board/mpc8313erdb/sdram.c | 133 ++++++++++ board/mpc8313erdb/u-boot.lds | 123 +++++++++ doc/README.mpc8313erdb | 83 ++++++ include/configs/MPC8313ERDB.h | 569 ++++++++++++++++++++++++++++++++++++++++ 8 files changed, 1088 insertions(+) create mode 100644 board/mpc8313erdb/Makefile create mode 100644 board/mpc8313erdb/config.mk create mode 100644 board/mpc8313erdb/mpc8313erdb.c create mode 100644 board/mpc8313erdb/sdram.c create mode 100644 board/mpc8313erdb/u-boot.lds create mode 100644 doc/README.mpc8313erdb create mode 100644 include/configs/MPC8313ERDB.h (limited to 'include/configs') diff --git a/Makefile b/Makefile index 94cda54c731..0b0c0d00e09 100644 --- a/Makefile +++ b/Makefile @@ -1689,6 +1689,19 @@ MPC8360EMDS_SLAVE_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds +MPC8313ERDB_33_config \ +MPC8313ERDB_66_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "...33M ..." ; \ + echo "#define CFG_33MHZ" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _66_,$@)" ] ; then \ + echo -n "...66M..." ; \ + echo "#define CFG_66MHZ" >>include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb + sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/board/mpc8313erdb/Makefile b/board/mpc8313erdb/Makefile new file mode 100644 index 00000000000..a987e510dd2 --- /dev/null +++ b/board/mpc8313erdb/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc8313erdb/config.mk b/board/mpc8313erdb/config.mk new file mode 100644 index 00000000000..f76826495ef --- /dev/null +++ b/board/mpc8313erdb/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xFE000000 diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/mpc8313erdb/mpc8313erdb.c new file mode 100644 index 00000000000..999fe9e39bb --- /dev/null +++ b/board/mpc8313erdb/mpc8313erdb.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * + * Author: Scott Wood + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ +#ifndef CFG_8313ERDB_BROKEN_PMC + volatile immap_t *im = (immap_t *)CFG_IMMR; + + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + gd->flags |= GD_FLG_SILENT; +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: Freescale MPC8313ERDB\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; +#ifndef CFG_8313ERDB_BROKEN_PMC + warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; +#endif + + mpc83xx_pci_init(1, reg, warmboot); +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c new file mode 100644 index 00000000000..4b6778837f2 --- /dev/null +++ b/board/mpc8313erdb/sdram.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +#include + +#ifndef CFG_8313ERDB_BROKEN_PMC +static void resume_from_sleep(void) +{ + DECLARE_GLOBAL_DATA_PTR; + u32 magic = *(u32 *)0; + + typedef void (*func_t)(void); + func_t resume = *(func_t *)4; + + if (magic == 0xf5153ae5) + resume(); + + gd->flags &= ~GD_FLG_SILENT; + puts("\nResume from sleep failed: bad magic word\n"); +} +#endif + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + + /* Currently we use only one CS, so disable the other bank. */ + im->ddr.cs_config[1] = 0; + + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; + else +#endif + im->ddr.sdram_cfg = CFG_SDRAM_CFG; + + im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE_2; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + sync(); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +long int initdram(int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + puts("Initializing\n"); + + /* DDR SDRAM - Main SODIMM */ + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + sync(); + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + resume_from_sleep(); +#endif + + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/mpc8313erdb/u-boot.lds b/board/mpc8313erdb/u-boot.lds new file mode 100644 index 00000000000..937c87a27cd --- /dev/null +++ b/board/mpc8313erdb/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/doc/README.mpc8313erdb b/doc/README.mpc8313erdb new file mode 100644 index 00000000000..7ad4cc76c32 --- /dev/null +++ b/doc/README.mpc8313erdb @@ -0,0 +1,83 @@ +Freescale MPC8313ERDB Board +----------------------------------------- + +1. Board Switches and Jumpers + + SW3 is used to set CFG_RESET_SOURCE. + + To boot the image at 0xFE000000 in NOR flash, use these DIP + switche settings for SW3 SW4: + + +------+ +------+ + | | | **** | + | **** | | | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x07ff_ffff DDR 128M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K + 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K + 0xfa00_0000 0xfa00_7fff Board Status/ 32K + LED Control (CS3) + 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8313ERDB.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC831x MPC831x specific + CONFIG_MPC8313ERDB MPC8313ERDB board specific + +4. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make MPC8313ERDB_33_config + (or make MPC8313ERDB_66_config, depending on the speed of + the oscillator on your board) + make + +5. Downloading and Flashing Images + +5.1 Reflash U-boot Image using U-boot + + =>run tftpflash + + You may want to try + =>tftpboot $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + have an alternate means of programming the flash available + if the new u-boot doesn't boot. + +5.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, rootpath (if using NFS root), + fdtfile, and bootfile). + + Then, do one of the following, depending on whether you + want an NFS root or a ramdisk root: + + =>run nfsboot + or + =>run ramboot + +6 Notes + + Booting from NAND flash is not yet supported. + The console baudrate for MPC8313ERDB is 115200bps. diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h new file mode 100644 index 00000000000..2519c6b8b52 --- /dev/null +++ b/include/configs/MPC8313ERDB.h @@ -0,0 +1,569 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * History + * 20061201: Wilson Lo (Wilson.Lo@freescale.com) + * Initialized + * 20061210: Tanya Jiang (tanya.jiang@freescale.com) + * Code Cleanup + * 20070410: Scott Wood + * More cleanup + */ +/* + * mpc8313epb board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 +#define CONFIG_MPC8313ERDB 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#ifdef CFG_66MHZ +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#elif defined(CFG_33MHZ) +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#else +#error Unknown oscillator frequency. +#endif + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#define CFG_MEMTEST_START 0x00001000 +#define CFG_MEMTEST_END 0x07f00000 + +/* Early revs of this board will lock up hard when attempting + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +#define CFG_8313ERDB_BROKEN_PMC 1 + +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE + +/* + * Manually set up DDR parameters, as this board does not + * seem to have the SPD connected to I2C. + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ + | 0x00040000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80840102 */ + +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3935d322 */ +#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | (31 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x0f9048ca */ /* P9-45,may need tuning */ +#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03200064 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_2T_EN \ + | SDRAM_CFG_DBW_32 ) +#else +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ +#endif +#define CFG_SDRAM_CFG2 0x00401000; +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44400232 */ +#define CFG_DDR_MODE_2 0x8000C000; + +#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +#define CFG_FLASH_EMPTY_INFO /* display empty sectors */ +#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD ) + /* 0xFF006FF7 TODO SLOW 16 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ +#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ + +/* drivers/nand/nand.c */ +#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CFG_BR1_PRELIM ( CFG_NAND_BASE \ + | (2<bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CONFIG_NET_MULTI + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_MPC83XX_TSEC1 1 + +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0x1c +#define TSEC2_PHY_ADDR 4 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_DHCP \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI) + +#define CONFIG_CMDLINE_EDITING 1 + +#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) + +#if defined(CFG_RAMBOOT) +#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS +#else +#define CONFIG_COMMANDS CFG_BASE_COMMANDS +#endif + +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#ifdef CFG_66MHZ + +/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ +/* 0x62040000 */ +#define CFG_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#elif defined(CFG_33MHZ) + +/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ +/* 0x65040000 */ +#define CFG_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_5X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#endif + +/* 0xa0606c00 */ +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +/* System IO Config */ +#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ETHADDR 00:E0:0C:00:95:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 + +#define CONFIG_IPADDR 10.0.0.2 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME mpc8313erdb +#define CONFIG_ROOTPATH /nfs/root/path +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE mpc8313erdb.dtb + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=400000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 144876a380f5756f57412caf74c1d6dc201dd796 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Apr 2007 23:01:02 +0200 Subject: [PATCH] MTD partition support, JFFS2 support --- fs/jffs2/compr_zlib.c | 2 +- include/configs/ml401.h | 29 +++++++++++++++++++++++++++-- include/linux/stat.h | 3 ++- 3 files changed, 30 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c index 1b35585eee5..d88d0f8f36e 100644 --- a/fs/jffs2/compr_zlib.c +++ b/fs/jffs2/compr_zlib.c @@ -45,7 +45,7 @@ long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen) { - return (decompress_block(cpage_out, data_in + 2, ldr_memcpy)); + return (decompress_block(cpage_out, data_in + 2, (void *) ldr_memcpy)); } diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 15c2fe7ecd1..acaa1e4f2b9 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -40,7 +40,7 @@ /* ethernet */ #define CONFIG_EMACLITE 1 -#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES +#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID /* gpio */ #define CFG_GPIO_0 1 @@ -118,6 +118,7 @@ #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + #define CFG_FLASH_PROTECTION /* hardware flash protection */ #ifdef RAMENV #define CFG_ENV_IS_NOWHERE 1 @@ -136,6 +137,7 @@ #define CFG_ENV_IS_NOWHERE 1 #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) + #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ #ifdef FLASH @@ -155,6 +157,8 @@ CFG_CMD_CACHE |\ CFG_CMD_FAT |\ CFG_CMD_EXT2 |\ + CFG_CMD_JFFS2 |\ + CFG_CMD_ECHO |\ CFG_CMD_IMLS |\ CFG_CMD_FLASH |\ CFG_CMD_PING \ @@ -179,6 +183,8 @@ CFG_CMD_ENV |\ CFG_CMD_FAT |\ CFG_CMD_EXT2 |\ + CFG_CMD_JFFS2 |\ + CFG_CMD_ECHO |\ CFG_CMD_SAVES \ ) @@ -206,6 +212,17 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +/* JFFS2 partitions */ +#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ +#define MTDIDS_DEFAULT "nor0=ml401-0" + +/* default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ + "256k(env),3m(kernel),1m(romfs),"\ + "1m(cramfs),-(jffs2)" +#endif + /* Miscellaneous configurable options */ #define CFG_PROMPT "U-Boot-mONStR> " #define CFG_CBSIZE 512 /* size of console buffer */ @@ -214,7 +231,7 @@ #define CFG_LONGHELP #define CFG_LOAD_ADDR 0x12000000 /* default load address */ -#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME "ml401" #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" @@ -235,4 +252,12 @@ #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH #define CONFIG_DOS_PARTITION +#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" + +#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ + "nor0=ml401-0\0"\ + "mtdparts=mtdparts=ml401-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0" + #endif /* __CONFIG_H */ diff --git a/include/linux/stat.h b/include/linux/stat.h index f9422cb1faf..39386f1220a 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -67,7 +67,8 @@ struct stat { #endif /* __PPC__ */ -#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) ||\ + defined (__microblaze__) struct stat { unsigned short st_dev; -- cgit v1.3.1 From 5c5d3242935cf3543af01142627494434834cf98 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Apr 2007 12:34:38 -0500 Subject: mpc83xx: minor fixups for 8313rdb introduction --- MAKEALL | 4 ++-- Makefile | 26 +++++++++++++------------- cpu/mpc83xx/pci.c | 1 + include/configs/MPC8313ERDB.h | 4 ++-- 4 files changed, 18 insertions(+), 17 deletions(-) (limited to 'include/configs') diff --git a/MAKEALL b/MAKEALL index 0f0ec296f26..a6b93b3c55b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -132,8 +132,8 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - MPC832XEMDS MPC8349EMDS MPC8349ITX MPC8349ITXGP \ - MPC8360EMDS sbc8349 TQM834x \ + MPC8313ERDB MPC832XEMDS MPC8349EMDS MPC8349ITX + MPC8349ITXGP MPC8360EMDS sbc8349 TQM834x " diff --git a/Makefile b/Makefile index 0b0c0d00e09..f7fde1ebcfa 100644 --- a/Makefile +++ b/Makefile @@ -1624,6 +1624,19 @@ r5200_config : unconfig ## MPC83xx Systems ######################################################################### +MPC8313ERDB_33_config \ +MPC8313ERDB_66_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "...33M ..." ; \ + echo "#define CFG_33MHZ" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _66_,$@)" ] ; then \ + echo -n "...66M..." ; \ + echo "#define CFG_66MHZ" >>include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb + MPC832XEMDS_config \ MPC832XEMDS_HOST_33_config \ MPC832XEMDS_HOST_66_config \ @@ -1689,19 +1702,6 @@ MPC8360EMDS_SLAVE_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds -MPC8313ERDB_33_config \ -MPC8313ERDB_66_config: unconfig - @echo "" >include/config.h ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define CFG_33MHZ" >>include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define CFG_66MHZ" >>include/config.h ; \ - fi ; - @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb - sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 2a2b0bd9028..785d6129daf 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -25,6 +25,7 @@ #include #include +#include #include #ifdef CONFIG_83XX_GENERIC_PCI diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 2519c6b8b52..11858bfb8f6 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -47,9 +47,9 @@ #define CONFIG_83XX_GENERIC_PCI #ifdef CFG_66MHZ -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ #elif defined(CFG_33MHZ) -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ #else #error Unknown oscillator frequency. #endif -- cgit v1.3.1 From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 30 Apr 2007 13:59:50 -0500 Subject: Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi Acked-by: Michael Benedict Signed-off-by: Kim Phillips --- board/mpc8349itx/mpc8349itx.c | 3 +-- cpu/mpc83xx/spd_sdram.c | 5 ----- include/configs/MPC8349ITX.h | 3 +++ 3 files changed, 4 insertions(+), 7 deletions(-) (limited to 'include/configs') diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 2b3ded17629..178b1d36fbf 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -80,8 +80,7 @@ int fixed_sdram(void) im->ddr.sdram_interval = (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = - DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; udelay(200); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 41a1f1fc7b0..647813f68d9 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -693,11 +693,6 @@ long int spd_sdram() #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; -#else - /* SS_EN = 0, source synchronous disable - * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd - */ - ddr->sdram_clk_cntl = 0x00000000; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 37bbfb336d2..906339e9d88 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -154,6 +154,9 @@ #define CFG_MEMTEST_START 0x1000 /* memtest region */ #define CFG_MEMTEST_END 0x2000 +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ #endif -- cgit v1.3.1 From ffc50f9bb194343c6303517a517708457a5eb6b8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 5 May 2007 18:54:42 +0200 Subject: new: FSL and MSR support #2 --- README | 1 + board/xilinx/ml401/xparameters.h | 3 +++ common/Makefile | 2 +- include/cmd_confdefs.h | 2 ++ include/configs/ml401.h | 3 +++ 5 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/README b/README index 15428643ede..33039f1d9ca 100644 --- a/README +++ b/README @@ -703,6 +703,7 @@ The following options need to be configured: CFG_CMD_VFD * VFD support (TRAB) CFG_CMD_BSP * Board SPecific functions CFG_CMD_CDP * Cisco Discover Protocol support + CFG_CMD_FSL * Microblaze FSL support ----------------------------------------------- CFG_CMD_ALL all diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h index 4fe36f8a9d2..f63ffed3dcc 100644 --- a/board/xilinx/ml401/xparameters.h +++ b/board/xilinx/ml401/xparameters.h @@ -29,6 +29,9 @@ /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 +/* Microblaze is microblaze_0 */ +#define XILINX_FSL_NUMBER 2 + /* Interrupt controller is intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 #define XILINX_INTC_NUM_INTR_INPUTS 4 diff --git a/common/Makefile b/common/Makefile index 6f81c4abcf3..c088821a57d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -50,7 +50,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o + virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index cf36583108c..b3ccdcea2b0 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -94,6 +94,7 @@ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ #define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ #define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ +#define CFG_CMD_MFSL 0x8000000000000000ULL /* FSL support for Microblaze */ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ @@ -125,6 +126,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ + CFG_CMD_MFSL | \ CFG_CMD_MII | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ diff --git a/include/configs/ml401.h b/include/configs/ml401.h index acaa1e4f2b9..f3ef962a785 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -161,6 +161,7 @@ CFG_CMD_ECHO |\ CFG_CMD_IMLS |\ CFG_CMD_FLASH |\ + CFG_CMD_MFSL |\ CFG_CMD_PING \ ) #else /* !RAMENV */ @@ -185,6 +186,7 @@ CFG_CMD_EXT2 |\ CFG_CMD_JFFS2 |\ CFG_CMD_ECHO |\ + CFG_CMD_MFSL |\ CFG_CMD_SAVES \ ) @@ -206,6 +208,7 @@ CFG_CMD_IMI |\ CFG_CMD_NET |\ CFG_CMD_CACHE |\ + CFG_CMD_MFSL |\ CFG_CMD_PING \ ) #endif /* !FLASH */ -- cgit v1.3.1 From 19bf1fbad7f19d5a120be9b1daf136e052fcab39 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 19:33:51 +0200 Subject: new: fsl interrupt support FSL_Has_data is connected to INTC. --- board/xilinx/ml401/ml401.c | 22 +++++++++++++++++++++- include/configs/ml401.h | 4 ++++ 2 files changed, 25 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c index b48103fdc02..955936d907e 100644 --- a/board/xilinx/ml401/ml401.c +++ b/board/xilinx/ml401/ml401.c @@ -27,6 +27,8 @@ #include #include +#include +#include void do_reset (void) { @@ -43,7 +45,25 @@ void do_reset (void) int gpio_init (void) { #ifdef CFG_GPIO_0 - *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0; + *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0xFFFFFFFF; #endif return 0; } + +#ifdef CFG_FSL_2 +void fsl_isr2 (void *arg) { + volatile int num; + *((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)) = + ++(*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4))); + GET (num, 2); + NGET (num, 2); + puts("*"); +} + +void fsl_init2 (void) { + puts("fsl_init2\n"); + install_interrupt_handler (FSL_INTR_2,\ + fsl_isr2,\ + NULL); +} +#endif diff --git a/include/configs/ml401.h b/include/configs/ml401.h index f3ef962a785..327d31c103a 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -58,6 +58,10 @@ #define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +/* FSL */ +#define CFG_FSL_2 +#define FSL_INTR_2 1 + /* * memory layout - Example * TEXT_BASE = 0x1200_0000; -- cgit v1.3.1 From 1f1369c34b629be94702684d41d3fddf0f6193e7 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 8 May 2007 09:21:57 +0200 Subject: [Motion-PRO] Enable Flat Device Tree support and modify default environment to allow booting of FDT-expecting kernels. --- board/motionpro/motionpro.c | 11 ++++++++++ include/configs/motionpro.h | 49 +++++++++++++++++++++++++++------------------ 2 files changed, 41 insertions(+), 19 deletions(-) (limited to 'include/configs') diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 95576ed56b8..887aadeeed2 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -29,6 +29,9 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif /* Kollmorgen DPR initialization data */ struct init_elem { @@ -169,3 +172,11 @@ int checkboard (void) puts("Board: Promess Motion-PRO board\n"); return 0; } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 5328e8d6b1c..b1edde8b46e 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -26,7 +26,6 @@ #ifndef __CONFIG_H #define __CONFIG_H - /* * High Level Configuration Options */ @@ -94,42 +93,44 @@ * Default environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "sdram_test=0\0" \ "netdev=eth0\0" \ "hostname=motionpro\0" \ "netmask=255.255.0.0\0" \ "ipaddr=192.168.160.22\0" \ "serverip=192.168.1.1\0" \ "gatewayip=192.168.1.1\0" \ - "kernel_addr=200000\0" \ + "console=ttyPSC0,115200\0" \ "u-boot_addr=100000\0" \ - "kernel_sector=20\0" \ - "kernel_size=1000\0" \ - "console=ttyS0,115200\0" \ + "kernel_addr=200000\0" \ + "fdt_addr=400000\0" \ + "ramdisk_addr=500000\0" \ "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ - "bootfile=/tftpboot/motionpro/uImage\0" \ "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ + "bootfile=/tftpboot/motionpro/uImage\0" \ + "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ + "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ "load=tftp $(u-boot_addr) $(u-boot)\0" \ "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \ "cp.b $(u-boot_addr) fff00000 $(filesize);" \ "prot on fff00000 fff3ffff\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) console=$(console) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \ - "bootm $(kernel_addr)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath)\0" \ - "fstype=ext3\0" \ - "fatargs=setenv bootargs init=/linuxrc rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1 " \ + "console=$(console)\0" \ + "net_nfs=tftp $(kernel_addr) $(bootfile); " \ + "tftp $(fdt_addr) $(fdt_file); run nfsargs addip; " \ + "bootm $(kernel_addr) - $(fdt_addr)\0" \ + "net_self=tftp $(kernel_addr) $(bootfile); " \ + "tftp $(fdt_addr) $(fdt_file); " \ + "tftp $(ramdisk_addr) $(ramdisk_file); " \ + "run ramargs addip; " \ + "bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" - /* * do board-specific init */ @@ -146,7 +147,6 @@ */ #define CFG_MPC5XXX_CLKIN 25000000 - /* * Memory map */ @@ -302,4 +302,15 @@ /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ #define CFG_RESET_ADDRESS 0xfff00100 +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PAT "/soc5200@f0000000/serial@2000" + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 06241d50a3ab1b20a0b08baeeaffcaa23ae4b839 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 8 May 2007 09:39:12 +0200 Subject: [Motion-PRO] Change IPB clock frequency from 50MHz to 100MHz. This eliminates networking problems in Linux (timeouts). --- include/configs/motionpro.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/configs') diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index b1edde8b46e..74ba800cbf8 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -147,6 +147,13 @@ */ #define CFG_MPC5XXX_CLKIN 25000000 + +/* + * Set IPB speed to 100MHz (yes, the #define is misnamed) + */ +#define CFG_IPBSPEED_133 + + /* * Memory map */ -- cgit v1.3.1 From fa5c2ba123b1bf88455bfc21db5e786ca045029d Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 8 May 2007 10:23:56 +0200 Subject: [Motion-PRO] Add ATA support. Add CF-booting commands to the default environment. --- include/configs/motionpro.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 74ba800cbf8..989a534e68d 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -30,7 +30,6 @@ * High Level Configuration Options */ - /* CPU and board */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ @@ -49,7 +48,9 @@ CFG_CMD_MII | \ CFG_CMD_BEDBUG | \ CFG_CMD_NET | \ - CFG_CMD_PING) + CFG_CMD_PING | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -104,11 +105,13 @@ "kernel_addr=200000\0" \ "fdt_addr=400000\0" \ "ramdisk_addr=500000\0" \ + "multi_image_addr=800000\0" \ "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ "bootfile=/tftpboot/motionpro/uImage\0" \ "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ + "multi_image_file=kernel+initrd+dtb.img\0" \ "load=tftp $(u-boot_addr) $(u-boot)\0" \ "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \ "cp.b $(u-boot_addr) fff00000 $(filesize);" \ @@ -116,6 +119,7 @@ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath)\0" \ + "fat_args=setenv bootargs rw\0" \ "addip=setenv bootargs $(bootargs) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):" \ "$(netmask):$(hostname):$(netdev):off panic=1 " \ @@ -128,6 +132,9 @@ "tftp $(ramdisk_addr) $(ramdisk_file); " \ "run ramargs addip; " \ "bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0" \ + "fat_multi=run fat_args addip; fatload ide 0:1 " \ + "${multi_image_addr} ${multi_image_file}; " \ + "bootm ${multi_image_addr}\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -251,6 +258,20 @@ #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ +/* + * IDE/ATA configuration + */ +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 +#define CONFIG_IDE_PREINIT + +#define CFG_ATA_DATA_OFFSET 0x0060 +#define CFG_ATA_REG_OFFSET CFG_ATA_DATA_OFFSET +#define CFG_ATA_STRIDE 4 +#define CONFIG_DOS_PARTITION + + /* * Environment settings */ -- cgit v1.3.1 From de1de02a7cbf05e6b63e0d8ffc624f12493f6ba3 Mon Sep 17 00:00:00 2001 From: Piotr Kruszynski Date: Tue, 8 May 2007 13:05:44 +0200 Subject: [Motion-PRO] Add support for I2C, EEPROM and RTC. --- include/configs/motionpro.h | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 989a534e68d..f1f7e2ba03a 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -50,7 +50,10 @@ CFG_CMD_NET | \ CFG_CMD_PING | \ CFG_CMD_IDE | \ - CFG_CMD_FAT) + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -272,6 +275,31 @@ #define CONFIG_DOS_PARTITION +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* select I2C module #2 */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 +#define CFG_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */ + + +/* + * RTC configuration + */ +#define CONFIG_RTC_DS1337 1 +#define CFG_I2C_RTC_ADDR 0x68 + + /* * Environment settings */ -- cgit v1.3.1 From 1a50f164beb065f360fbddb76029607d6b099698 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 May 2007 14:52:52 +0200 Subject: add: Microblaze V5 exception handling --- cpu/microblaze/exception.c | 10 ++++++++-- include/asm-microblaze/asm.h | 8 ++++++++ include/configs/ml401.h | 1 + 3 files changed, 17 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c index b135acbad9d..87ecbeaa49a 100644 --- a/cpu/microblaze/exception.c +++ b/cpu/microblaze/exception.c @@ -23,15 +23,16 @@ */ #include +#include void _hw_exception_handler (void) { int address = 0; int state = 0; /* loading address of exception EAR */ - __asm__ __volatile ("mfs %0,rear"::"r" (address):"memory"); + MFSEAR(address); /* loading excetpion state register ESR */ - __asm__ __volatile ("mfs %0,resr"::"r" (state):"memory"); + MFSESR(state); printf ("Hardware exception at 0x%x address\n", address); switch (state & 0x1f) { /* mask on exception cause */ case 0x1: @@ -49,6 +50,11 @@ void _hw_exception_handler (void) case 0x5: puts ("Divide by zero exception\n"); break; +#ifdef MICROBLAZE_V5 + case 0x1000: + puts ("Exception in delay slot\n"); + break; +#endif default: puts ("Undefined cause\n"); break; diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h index 26e369119e1..8302ed88507 100755 --- a/include/asm-microblaze/asm.h +++ b/include/asm-microblaze/asm.h @@ -48,12 +48,20 @@ __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); /* CPU dependent */ +/* machine status register */ #define MFS(val) \ __asm__ __volatile__ ("mfs %0, rmsr":"=r" (val)); #define MTS(val) \ __asm__ __volatile__ ("mts rmsr, %0"::"r" (val)); +/* exception status register */ +#define MFSEAR(val) \ + __asm__ __volatile ("mfs %0,rear":"=r" (val)); + +#define MFSESR(val) \ + __asm__ __volatile ("mfs %0,resr":"=r" (val)); + /* get return address from interrupt */ #define R14(val) \ __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 327d31c103a..4cfe802c36a 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -28,6 +28,7 @@ #include "../board/xilinx/ml401/xparameters.h" #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +#define MICROBLAZE_V5 1 #define CONFIG_ML401 1 /* ML401 Board */ /* uart */ -- cgit v1.3.1 From 7d98ba770a7eaefa29ce927f31a0956df85bf650 Mon Sep 17 00:00:00 2001 From: Piotr Kruszynski Date: Thu, 10 May 2007 16:55:52 +0200 Subject: [Motion-PRO] Add MTD and JFFS2 support, also add default partition definition. --- include/configs/motionpro.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/configs') diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index f1f7e2ba03a..e6e0eb1ff51 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -51,6 +51,7 @@ CFG_CMD_PING | \ CFG_CMD_IDE | \ CFG_CMD_FAT | \ + CFG_CMD_JFFS2 | \ CFG_CMD_I2C | \ CFG_CMD_DATE | \ CFG_CMD_EEPROM) @@ -260,6 +261,14 @@ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ +/* + * MTD configuration + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=motionpro-0" +#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ + "13m(fs),2m(kernel),256k(uboot)," \ + "64k(env),64k(dtb),-(user_data)" /* * IDE/ATA configuration -- cgit v1.3.1 From d62f64cc23a940eafe712c776b3249e4160753d1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 16 May 2007 00:13:33 +0200 Subject: Coding Style Cleanup, new CHANGELOG --- CHANGELOG | 252 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/systemace.c | 2 +- include/configs/ml401.h | 4 +- 3 files changed, 255 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/CHANGELOG b/CHANGELOG index 184e9418cba..cdcb9870e1e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,231 @@ +commit 7d98ba770a7eaefa29ce927f31a0956df85bf650 +Author: Piotr Kruszynski +Date: Thu May 10 16:55:52 2007 +0200 + + [Motion-PRO] Add MTD and JFFS2 support, also add default partition + definition. + +commit e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 +Author: Michal Simek +Date: Tue May 8 15:57:43 2007 +0200 + + add: reading special purpose registers + +commit 1a50f164beb065f360fbddb76029607d6b099698 +Author: Michal Simek +Date: Tue May 8 14:52:52 2007 +0200 + + add: Microblaze V5 exception handling + +commit ab874d5047e5d30dbc1e517ff26083efffa98ecb +Author: Michal Simek +Date: Tue May 8 14:39:11 2007 +0200 + + add: FSL control read and write + +commit de1de02a7cbf05e6b63e0d8ffc624f12493f6ba3 +Author: Piotr Kruszynski +Date: Tue May 8 13:05:44 2007 +0200 + + [Motion-PRO] Add support for I2C, EEPROM and RTC. + +commit fa5c2ba123b1bf88455bfc21db5e786ca045029d +Author: Bartlomiej Sieka +Date: Tue May 8 10:23:56 2007 +0200 + + [Motion-PRO] Add ATA support. Add CF-booting commands to the default + environment. + +commit 06241d50a3ab1b20a0b08baeeaffcaa23ae4b839 +Author: Bartlomiej Sieka +Date: Tue May 8 09:39:12 2007 +0200 + + [Motion-PRO] Change IPB clock frequency from 50MHz to 100MHz. This + eliminates networking problems in Linux (timeouts). + +commit 1f1369c34b629be94702684d41d3fddf0f6193e7 +Author: Bartlomiej Sieka +Date: Tue May 8 09:21:57 2007 +0200 + + [Motion-PRO] Enable Flat Device Tree support and modify default environment + to allow booting of FDT-expecting kernels. + +commit fb05f6da35ea1c15c553abe6f23f656bf18dc5db +Author: Michal Simek +Date: Mon May 7 23:58:31 2007 +0200 + + new: USE_MSR_INTR support + +commit 008861a2f3ef2c062744d733787c7e530a1b8761 +Author: Bartlomiej Sieka +Date: Mon May 7 22:36:15 2007 +0200 + + [MPC5xxx] There are networking problems on the Motion-PRO board with + current PHY initalization code (tftp timeouts all the time). This commit + temporarily disables PHY initalization sequence to make the networking + operational, until a fix is found. + +commit abca901869c3760b6c5fecb825db6c1d91a78a93 +Author: Wolfgang Denk +Date: Mon May 7 22:10:36 2007 +0200 + + Get rid of duplicated file (see include/configs/sbc8560.h instead) + + Signed-off-by: Wolfgang Denk + +commit 207b7b2c9d9752e0f6478c30c29b7087f6e6cbb6 +Author: Wolfgang Denk +Date: Mon May 7 22:07:08 2007 +0200 + + Get rid of duplicated file (see doc/README.SBC8560 instead) + + Signed-off-by: Wolfgang Denk + +commit a7bac7e9b57ba948051beb19ec5be3a75ce75383 +Author: Michal Simek +Date: Mon May 7 19:43:10 2007 +0200 + + fix: read and write MSR - repair number of parameters + +commit 19bf1fbad7f19d5a120be9b1daf136e052fcab39 +Author: Michal Simek +Date: Mon May 7 19:33:51 2007 +0200 + + new: fsl interrupt support + FSL_Has_data is connected to INTC. + +commit 792032baa7d625e34c981ab6df521911bd8dc861 +Author: Michal Simek +Date: Mon May 7 19:30:12 2007 +0200 + + fix: interrupt handler + remove asm code + +commit f3f001a341ef185d0f13841be5b5dc3395aacc31 +Author: Michal Simek +Date: Mon May 7 19:25:08 2007 +0200 + + fix: remove asm code + +commit fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01 +Author: Michal Simek +Date: Mon May 7 19:12:43 2007 +0200 + + fix: clean interrupt + +commit 42efed6130c8fcf7da881385b5427065d2801757 +Author: Michal Simek +Date: Mon May 7 17:22:25 2007 +0200 + + fix: interrupt handler for multiple sources + +commit 48fbd3a4cdabbebc1debd7eed73c00c2caf914f6 +Author: Michal Simek +Date: Mon May 7 17:11:09 2007 +0200 + + new: add writing to msr register + +commit ac4cd59d59c9bf3f89cb7a344abf8184d678f562 +Author: Timur Tabi +Date: Sat May 5 08:12:30 2007 +0200 + + 5xxx: write MAC address to mac-address and local-mac-address + + Some device trees have a mac-address property, some have local-mac-address, + and some have both. To support all of these device trees, ftp_cpu_setup() + should write the MAC address to mac-address and local-mac-address, if they + exist. + + Signed-off-by: Timur Tabi + Acked-by: Grant Likely + +commit a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2 +Author: Grzegorz Wianecki +Date: Sun Apr 29 14:01:54 2007 +0200 + + [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message + + MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up + message. Use PVR to distinguish between the two variants, and print proper CPU + information. + + Signed-off-by: Grzegorz Wianecki + Signed-off-by: Bartlomiej Sieka + Signed-off-by: Grant Likely + +commit 4ec5bd55ed1ffa91a774af298769621f4fbb18c1 +Author: Ladislav Michl +Date: Wed Apr 25 16:01:26 2007 +0200 + + [PATCH] simplify silent console + + Signed-off-by: Ladislav Michl + Acked-by: Stefan Roese + +commit b7598a43f2b421a713d8135e98a42c37d9eb9df0 +Author: Sergei Shtylyov +Date: Mon Apr 23 15:30:39 2007 +0200 + + [PATCH] Avoid assigning PCI resources from zero address + + If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE + core complains and IDE drivers fails to work. Also, assigning zero to a BAR + was illegal according to PCI 2.1 (the later revisions seem to have excluded the + sentence about "0" being considered an invalid address) -- so, use a reasonable + starting value of 0x1000 (that's what the most Linux archs are using). + + Alternatively, one might have fixed the calls to pci_set_region() individually + (some code even seems to have taken care of this issue) but that would have + been a lot more work. :-) + + Signed-off-by: Sergei Shtylyov + Acked-by: Stefan Roese + +commit 9ffd451afeb08e5be7ddae680487ec962b2bca25 +Author: Jeffrey Mann +Date: Mon Apr 23 14:00:11 2007 +0200 + + [patch] setenv(...) can delete environmentalvariables + + update setenv() function so that entering a NULL value for the + variable's value will delete the environmental variable + + Signed-off-by: Jeffrey Mann + Acked-by: Stefan Roese + +commit ebd0a0ae05a44769c4e27458ad4e9f3438250443 +Author: Mike Frysinger +Date: Mon Apr 23 13:54:24 2007 +0200 + + [patch] use unsigned char in smc91111 driver for mac + + the v_mac variable in the smc91111 driver is declared as a signed char ... + this causes problems when one of the bytes in the MAC is "signed" like 0xE0 + because when it gets printed out, you get a display like: + 0xFFFFFFE0 and that's no good + + Signed-off-by: Mike Frysinger + +commit ffc50f9bb194343c6303517a517708457a5eb6b8 +Author: Michal Simek +Date: Sat May 5 18:54:42 2007 +0200 + + new: FSL and MSR support #2 + +commit f7e2e0eb0668136305f78bb9c21be79b48a34247 +Author: Michal Simek +Date: Sat May 5 18:27:16 2007 +0200 + + new: FSL and MSR support + +commit 2f15278c2eb911c668b4fe562130b78cf554d139 +Author: Wolfgang Denk +Date: Sat May 5 18:23:11 2007 +0200 + + Coding stylke cleanup; update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 885ec89b648a899a2f32393fd3ffd9f7234c4402 Author: Wolfgang Denk Date: Sat May 5 18:05:02 2007 +0200 @@ -167,6 +395,12 @@ Date: Sun Apr 29 14:13:01 2007 +0200 Signed-off-by: Stefan Roese +commit 144876a380f5756f57412caf74c1d6dc201dd796 +Author: Michal Simek +Date: Tue Apr 24 23:01:02 2007 +0200 + + [PATCH] MTD partition support, JFFS2 support + commit 37ed6cdd4159195bfad68d8a237f6adda8f482cb Author: Matthias Fuchs Date: Tue Apr 24 14:03:45 2007 +0200 @@ -400,6 +634,24 @@ Date: Mon Apr 23 12:00:22 2007 +0200 Signed-off-by: Stefan Roese +commit 32556443840f127170e4baa8bdd5b567039f6c36 +Author: Michal Simek +Date: Sat Apr 21 21:07:22 2007 +0200 + + [PATCH] SystemACE support for Microblaze + +commit 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f +Author: Michal Simek +Date: Sat Apr 21 21:02:40 2007 +0200 + + 16bit read/write little endian + +commit 9d1d6a34d26c5933bc097ce73c9348f95573cdd4 +Author: Michal Simek +Date: Sat Apr 21 20:53:31 2007 +0200 + + Change ML401 parameters - Xilinx BSP + commit 2e343b9a57f32e1bd08c35c9976910333fb4e13d Author: Ed Swarthout Date: Wed Feb 28 05:37:29 2007 -0600 diff --git a/drivers/systemace.c b/drivers/systemace.c index c9fd5f16701..7d82c27c6ed 100644 --- a/drivers/systemace.c +++ b/drivers/systemace.c @@ -211,7 +211,7 @@ static unsigned long systemace_read(int dev, unsigned long start, /* Write sector count | ReadMemCardData. */ ace_writew((trans & 0xff) | 0x0300, 0x14); -/* +/* * For FPGA configuration via SystemACE is reset unacceptable * CFGDONE bit in STATUSREG is not set to 1. */ diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 4cfe802c36a..3db287784da 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -37,7 +37,7 @@ #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } /* setting reset address */ -//#define CFG_RESET_ADDRESS TEXT_BASE +/*#define CFG_RESET_ADDRESS TEXT_BASE*/ /* ethernet */ #define CONFIG_EMACLITE 1 @@ -99,7 +99,7 @@ /* global pointer */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ /* start of global data */ -#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 -- cgit v1.3.1 From a7676ea7732f3c596805079fed7e5c9fac652cfc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 16 May 2007 01:16:53 +0200 Subject: Minor Coding Style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 124 ++++++++++++++++++++++++++++++++++++++++++ include/configs/MPC8313ERDB.h | 40 ++++++-------- 2 files changed, 140 insertions(+), 24 deletions(-) (limited to 'include/configs') diff --git a/CHANGELOG b/CHANGELOG index cdcb9870e1e..24d805eb389 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,9 @@ +commit d62f64cc23a940eafe712c776b3249e4160753d1 +Author: Wolfgang Denk +Date: Wed May 16 00:13:33 2007 +0200 + + Coding Style Cleanup, new CHANGELOG + commit 7d98ba770a7eaefa29ce927f31a0956df85bf650 Author: Piotr Kruszynski Date: Thu May 10 16:55:52 2007 +0200 @@ -295,6 +301,14 @@ Date: Fri May 4 10:02:33 2007 +0200 Signed-off-by: Wolfgang Denk +commit 068aab660bc3912b930be5540e6b3f3fd6ad3c96 +Author: Kim Phillips +Date: Thu May 3 19:43:52 2007 -0500 + + mpc83xx: fix trivial error in MAKEALL + + Signed-off-by: Kim Phillips + commit c64a89d6ce8584b9fc64f4e85da9ecac3cfc2c2a Author: Wolfgang Denk Date: Thu May 3 16:34:41 2007 +0200 @@ -376,6 +390,33 @@ Date: Wed Feb 7 15:28:04 2007 -0600 Signed-off-by: James Yang Signed-off-by: Jon Loeliger +commit f64702b7fc8f8df39d31add770df6e372f9e9ce3 +Author: Timur Tabi +Date: Mon Apr 30 13:59:50 2007 -0500 + + Fix memory initialization on MPC8349E-mITX + + Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. + This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary + on some ITX boards, notably those with a revision 3.1 CPU. + + Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into + ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. + + Signed-off-by: Timur Tabi + Acked-by: Michael Benedict + Signed-off-by: Kim Phillips + +commit 54b2d434ae9d01787936f34fe1759cf3d7624ae3 +Author: Kim Phillips +Date: Mon Apr 30 15:26:21 2007 -0500 + + mpc83xx: replace elaborate boottime verbosity with 'clocks' command + + and fix CPU: to align with Board: display text. + + Signed-off-by: Kim Phillips + commit c1ab82669d9525998c34e802a12cad662723f22a Author: James Yang Date: Fri Mar 16 13:02:53 2007 -0500 @@ -395,6 +436,12 @@ Date: Sun Apr 29 14:13:01 2007 +0200 Signed-off-by: Stefan Roese +commit 5c5d3242935cf3543af01142627494434834cf98 +Author: Kim Phillips +Date: Wed Apr 25 12:34:38 2007 -0500 + + mpc83xx: minor fixups for 8313rdb introduction + commit 144876a380f5756f57412caf74c1d6dc201dd796 Author: Michal Simek Date: Tue Apr 24 23:01:02 2007 +0200 @@ -626,6 +673,71 @@ Date: Thu Dec 14 14:14:55 2006 +0800 board. Signed-off-by: Roy Zang +commit 96b8a05432f346f36493535c85320b70ec9c7c1b +Author: Scott Wood +Date: Mon Apr 16 14:54:15 2007 -0500 + + mpc83xx: Add MPC8313ERDB support. + + Signed-off-by: Scott Wood + +commit 49ea3b6eafe606285ae4d5c378026153dde53200 +Author: Scott Wood +Date: Mon Apr 16 14:34:21 2007 -0500 + + mpc83xx: Add generic PCI setup code. + + Board code can now request the generic setup code rather than having to + copy-and-paste it for themselves. Boards should be converted to use this + once they're tested with it. + + Signed-off-by: Scott Wood + +commit 7c98e5193e93df6b9b651851d54b638a61ebb0ea +Author: Scott Wood +Date: Mon Apr 16 14:34:19 2007 -0500 + + mpc83xx: Add 831x support to speed.c. + + Signed-off-by: Scott Wood + +commit 0f253283a32d91e06844d7f87f9b33f4f4fbce8f +Author: Scott Wood +Date: Mon Apr 16 14:34:18 2007 -0500 + + mpc83xx: Add 831x support to global_data.h + + Signed-off-by: Scott Wood + +commit 95e7ef897e54591e615fc1b458b74c286fe1fb06 +Author: Scott Wood +Date: Mon Apr 16 14:34:16 2007 -0500 + + mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu(). + + Rather than misleadingly define PVR_83xx as the specific type of 83xx + being built for, the PVR of each core revision is defined. checkcpu() now + prints the core that it detects, rather than aborting if it doesn't find + what it thinks it wants. + + Signed-off-by: Scott Wood + +commit a35b0c4950d84cf9e3a9e32b916135956d1ac636 +Author: Scott Wood +Date: Mon Apr 16 14:34:15 2007 -0500 + + mpc83xx: Recognize SPR values for MPC8311 and MPC8313. + + Signed-off-by: Scott Wood + +commit d87c57b201b4572d16f1b642998faa00c9912b16 +Author: Scott Wood +Date: Mon Apr 16 14:31:55 2007 -0500 + + mpc83xx: Add register definitions for MPC831x. + + Signed-off-by: Scott Wood + commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522 Author: Stefan Roese Date: Mon Apr 23 12:00:22 2007 +0200 @@ -1134,6 +1246,18 @@ Date: Fri Apr 13 08:02:24 2007 +0200 Signed-of-by: Greg Lopp Acked-by: Grant Likely +commit 6fbf261f8df294e589cfadebebe5468e3c0f29e9 +Author: Xie Xiaobo +Date: Fri Mar 9 19:08:25 2007 +0800 + + Fix two bugs for MPC83xx DDR2 controller SPD Init + + There are a few bugs in the cpu/mpc83xx/spd_sdram.c + the first bug is that the picos_to_clk routine introduces a huge + rounding error in 83xx. + the second bug is that the mode register write recovery field is + tWR-1, not tWR >> 1. + commit 2ad3aba01d37b72e7c957b07e102fccd64fe6d13 Author: Jeffrey Mann Date: Thu Apr 12 14:15:59 2007 +0200 diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 11858bfb8f6..697631345f6 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -18,14 +18,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * History - * 20061201: Wilson Lo (Wilson.Lo@freescale.com) - * Initialized - * 20061210: Tanya Jiang (tanya.jiang@freescale.com) - * Code Cleanup - * 20070410: Scott Wood - * More cleanup */ /* * mpc8313epb board configuration file @@ -154,10 +146,10 @@ #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR \ @@ -197,20 +189,20 @@ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ -#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ /* drivers/nand/nand.c */ -#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ +#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ - | (2< " /* Monitor Command Prompt */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ @@ -395,7 +387,7 @@ #define CFG_CACHELINE_SIZE 32 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ #ifdef CFG_66MHZ @@ -439,12 +431,12 @@ HRCWH_LALE_NORMAL) /* System IO Config */ -#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ -#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ +#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ #define CFG_HID0_INIT 0x000000000 #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CFG_HID2 HID2_HBE -- cgit v1.3.1