From d4061aa0e9bb48e55a958b59950e314c1c03f124 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:28 -0600 Subject: exynos: Enable new features for exynos5 boards Enable PMICs, regulators and the like so that new drivers will be made available. Signed-off-by: Simon Glass --- include/configs/arndale.h | 4 ++++ include/configs/exynos5-common.h | 10 ++-------- include/configs/exynos5-dt-common.h | 5 ----- include/configs/smdk5250.h | 3 --- include/configs/snow.h | 3 --- 5 files changed, 6 insertions(+), 19 deletions(-) (limited to 'include/configs') diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 3ad4a9ba91f..91e32dff52f 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -60,4 +60,8 @@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 +/* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C + #endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index e04dec74113..15363d00794 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -67,6 +67,8 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" @@ -126,10 +128,6 @@ #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ - -/* TODO(sjg@chromium.org): Move these two options to Kconfig */ -#define CONFIG_DM_I2C -#define CONFIG_DM_I2C_COMPAT #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ @@ -149,10 +147,6 @@ #define CONFIG_OF_SPI #endif -/* Power */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C - #ifdef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index b1b8e1ace70..098734b542b 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -18,11 +18,6 @@ #include "exynos5-common.h" -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - /* Enable keyboard */ #define CONFIG_KEYBOARD diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index e5655fce195..bbec6721931 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -17,9 +17,6 @@ #include -/* PMIC */ -#define CONFIG_POWER_MAX77686 - #define CONFIG_BOARD_COMMON #define CONFIG_USB_XHCI diff --git a/include/configs/snow.h b/include/configs/snow.h index 557f86c07cb..a467792cdd9 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -18,9 +18,6 @@ #include #include - -#define CONFIG_POWER_TPS65090_I2C - #define CONFIG_BOARD_COMMON #define CONFIG_USB_XHCI -- cgit v1.3.1 From bf637ea5e48b26e01c440ed7d108eada1345ffd2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:29 -0600 Subject: exynos: config: Move common options to the common headers and tidy up Many options are duplicated on the exynos5 boards. Move these to the common files. Also some options are not used so can be removed. Tidy this up to make the files easier to maintain. Signed-off-by: Simon Glass Acked-by: Przemyslaw Marczak --- include/configs/arndale.h | 14 ++------------ include/configs/exynos5-common.h | 3 --- include/configs/exynos5-dt-common.h | 16 +++++++++++++++- include/configs/exynos5250-common.h | 16 ++++++---------- include/configs/exynos5420-common.h | 9 +++------ include/configs/odroid_xu3.h | 2 ++ include/configs/peach-pi.h | 12 +----------- include/configs/peach-pit.h | 20 +------------------- include/configs/smdk5250.h | 15 ++++----------- include/configs/smdk5420.h | 10 ++++------ include/configs/snow.h | 12 +----------- 11 files changed, 39 insertions(+), 90 deletions(-) (limited to 'include/configs') diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 91e32dff52f..8784c4e38d9 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -13,6 +13,7 @@ "fdtfile=exynos5250-arndale.dtb\0" #include "exynos5250-common.h" +#include /* SD/MMC configuration */ #define CONFIG_SUPPORT_EMMC_BOOT @@ -20,15 +21,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* USB */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_EXYNOS - -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_ASIX88179 - /* MMC SPL */ #define CONFIG_EXYNOS_SPL @@ -36,9 +28,6 @@ #define CONFIG_SYS_PROMPT "ARNDALE # " #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ - #define CONFIG_IDENT_STRING " for ARNDALE" #define CONFIG_ENV_IS_IN_MMC @@ -49,6 +38,7 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK /* PMIC */ +#define CONFIG_POWER #define CONFIG_PMIC #define CONFIG_POWER_I2C diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 15363d00794..e710f41f79e 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -143,8 +143,6 @@ #define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#define CONFIG_OF_SPI #endif #ifdef CONFIG_ENV_IS_IN_SPI_FLASH @@ -194,7 +192,6 @@ #define CONFIG_FIT #define CONFIG_FIT_BEST_MATCH - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 098734b542b..29ef84b6a37 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -16,7 +16,21 @@ "stdout=serial,lcd\0" \ "stderr=serial,lcd\0" -#include "exynos5-common.h" +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_SPI_BOOTING + +#define CONFIG_BOARD_COMMON + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif /* Enable keyboard */ #define CONFIG_KEYBOARD diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 95e96ecde46..7d8921f24eb 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#include #define CONFIG_EXYNOS5250 #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -28,16 +27,13 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* I2C */ -#define CONFIG_MAX_I2C_NUM 8 +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS -/* Display */ -#define CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_ASIX88179 /* DRAM Memory Banks */ #define CONFIG_NR_DRAM_BANKS 8 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 3b1ac2cecd4..3cdec51fe78 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -13,8 +13,6 @@ /* A variant of Exynos5420 (Exynos5 Family) */ #define CONFIG_EXYNOS5800 -#include - #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 @@ -32,10 +30,6 @@ #define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \ "exynos5420-peach-pit exynos5420-smdk5420" -#define CONFIG_MAX_I2C_NUM 11 - -#define CONFIG_BOARD_REV_GPIO_COUNT 2 - #define CONFIG_PHY_IRAM_BASE 0x02020000 /* Address for relocating helper code (Last 4 KB of IRAM) */ @@ -52,4 +46,7 @@ */ #define CONFIG_CORE_COUNT 0x8 +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 8d5c736cc71..0deff460267 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -9,7 +9,9 @@ #define __CONFIG_ODROID_XU3_H #include "exynos5420-common.h" +#include +#undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SYS_PROMPT "ODROID-XU3 # " #define CONFIG_IDENT_STRING " for ODROID-XU3" diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 46699ff635c..b97faf2c3b0 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -9,12 +9,6 @@ #ifndef __CONFIG_PEACH_PI_H #define __CONFIG_PEACH_PI_H -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#define CONFIG_SPI_BOOTING - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "kernel_addr_r=0x22000000\0" \ @@ -25,8 +19,7 @@ #include #include - -#define CONFIG_BOARD_COMMON +#include #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_TEXT_BASE 0x23E00000 @@ -51,9 +44,6 @@ #define CONFIG_POWER_TPS65090_EC -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS - /* DRAM Memory Banks */ #define CONFIG_NR_DRAM_BANKS 7 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index c5c9e3aa38e..18be42c86eb 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,12 +9,6 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#define CONFIG_SPI_BOOTING - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "kernel_addr_r=0x22000000\0" \ @@ -25,8 +19,7 @@ #include #include - -#define CONFIG_BOARD_COMMON +#include #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_TEXT_BASE 0x23E00000 @@ -41,19 +34,8 @@ #define CONFIG_VIDEO_PARADE -/* Display */ -#define CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - #define CONFIG_POWER_TPS65090_EC -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS - /* DRAM Memory Banks */ #define CONFIG_NR_DRAM_BANKS 4 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index bbec6721931..82d41ccfbb8 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,23 +9,16 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#define CONFIG_SPI_BOOTING - #include +#include +#include -#define CONFIG_BOARD_COMMON +#undef CONFIG_KEYBOARD -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS +#define CONFIG_BOARD_COMMON #define CONFIG_SYS_PROMPT "SMDK5250 # " #define CONFIG_IDENT_STRING " for SMDK5250" - -/* Miscellaneous configurable options */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 607877c95d8..623efa8a622 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,13 +9,11 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#define CONFIG_SPI_BOOTING - #include +#include +#include + +#undef CONFIG_KEYBOARD #define CONFIG_BOARD_COMMON diff --git a/include/configs/snow.h b/include/configs/snow.h index a467792cdd9..bf3377cb10c 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,22 +9,12 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#define CONFIG_SPI_BOOTING - #include #include +#include #define CONFIG_BOARD_COMMON -#define CONFIG_USB_XHCI -#define CONFIG_USB_EHCI -#define CONFIG_USB_XHCI_EXYNOS -#define CONFIG_USB_EHCI_EXYNOS - #define CONFIG_SYS_PROMPT "snow # " #define CONFIG_IDENT_STRING " for snow" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -- cgit v1.3.1 From c51212332af188d8bdeb5488d57d6c19a4326d22 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:30 -0600 Subject: exynos: Drop old exynos5420-specific board code Now that exynos5420 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass Acked-by: Przemyslaw Marczak --- board/samsung/smdk5420/Makefile | 4 - board/samsung/smdk5420/smdk5420.c | 143 ------------------------------------ include/configs/exynos5420-common.h | 2 + 3 files changed, 2 insertions(+), 147 deletions(-) delete mode 100644 board/samsung/smdk5420/smdk5420.c (limited to 'include/configs') diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile index c2f8886c99c..96a400aacbd 100644 --- a/board/samsung/smdk5420/Makefile +++ b/board/samsung/smdk5420/Makefile @@ -5,7 +5,3 @@ # obj-y += smdk5420_spl.o - -ifndef CONFIG_SPL_BUILD -obj-y += smdk5420.o -endif diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c deleted file mode 100644 index 57cc92c50b9..00000000000 --- a/board/samsung/smdk5420/smdk5420.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int exynos_init(void) -{ - return 0; -} - -#ifdef CONFIG_LCD -static int has_edp_bridge(void) -{ - int node; - - node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625); - - /* No node for bridge in device tree. */ - if (node <= 0) - return 0; - - /* Default is with bridge ic */ - return 1; -} - -void exynos_lcd_power_on(void) -{ -#ifdef CONFIG_POWER_TPS65090 - int ret; - - ret = tps65090_init(); - if (ret < 0) { - printf("%s: tps65090_init() failed\n", __func__); - return; - } - - tps65090_fet_enable(6); -#endif - - mdelay(5); - - if (has_edp_bridge()) - if (parade_init(gd->fdt_blob)) - printf("%s: ps8625_init() failed\n", __func__); -} - -void exynos_backlight_on(unsigned int onoff) -{ -#ifdef CONFIG_POWER_TPS65090 - tps65090_fet_enable(1); -#endif -} -#endif - -int board_get_revision(void) -{ - return 0; -} - -#ifdef CONFIG_USB_DWC3 -static struct dwc3_device dwc3_device_data = { - .maximum_speed = USB_SPEED_SUPER, - .base = 0x12400000, - .dr_mode = USB_DR_MODE_PERIPHERAL, - .index = 0, -}; - -int usb_gadget_handle_interrupts(void) -{ - dwc3_uboot_handle_interrupt(0); - return 0; -} - -int board_usb_init(int index, enum usb_init_type init) -{ - struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *) - samsung_get_base_usb3_phy(); - - if (!phy) { - error("usb3 phy not supported"); - return -ENODEV; - } - - set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); - exynos5_usb3_phy_init(phy); - - return dwc3_uboot_init(&dwc3_device_data); -} -#endif -#ifdef CONFIG_SET_DFU_ALT_INFO -char *get_dfu_alt_system(char *interface, char *devstr) -{ - return getenv("dfu_alt_system"); -} - -char *get_dfu_alt_boot(char *interface, char *devstr) -{ - struct mmc *mmc; - char *alt_boot; - int dev_num; - - dev_num = simple_strtoul(devstr, NULL, 10); - - mmc = find_mmc_device(dev_num); - if (!mmc) - return NULL; - - if (mmc_init(mmc)) - return NULL; - - if (IS_SD(mmc)) - alt_boot = CONFIG_DFU_ALT_BOOT_SD; - else - alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; - - return alt_boot; -} -#endif diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 3cdec51fe78..cd86e066685 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -13,6 +13,8 @@ /* A variant of Exynos5420 (Exynos5 Family) */ #define CONFIG_EXYNOS5800 +#define CONFIG_EXYNOS5_DT + #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 -- cgit v1.3.1 From 54abb000e3d76ab7c2d0df11a2b4074aec7f3c1f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:31 -0600 Subject: exynos: Drop old exynos5250-specific board code Now that most exynos5250 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass --- board/samsung/smdk5250/Makefile | 4 - board/samsung/smdk5250/exynos5-dt.c | 306 ------------------------------------ include/configs/exynos5-dt-common.h | 2 + 3 files changed, 2 insertions(+), 310 deletions(-) delete mode 100644 board/samsung/smdk5250/exynos5-dt.c (limited to 'include/configs') diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 3d96b077b4c..501cab69e1c 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -5,7 +5,3 @@ # obj-y += smdk5250_spl.o - -ifndef CONFIG_SPL_BUILD -obj-y += exynos5-dt.o -endif diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c deleted file mode 100644 index 53ff7061d73..00000000000 --- a/board/samsung/smdk5250/exynos5-dt.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) -{ - /* Enable MAX98095 Codec */ - gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); - gpio_direction_output(EXYNOS5_GPIO_X17, 1); - gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); -} -#endif - -int exynos_init(void) -{ -#ifdef CONFIG_SOUND_MAX98095 - board_enable_audio_codec(); -#endif - return 0; -} - -#if defined(CONFIG_POWER) -#ifdef CONFIG_POWER_MAX77686 -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -static int max77686_init(void) -{ - struct pmic *p; - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif /* CONFIG_POWER_MAX77686 */ - -int exynos_power_init(void) -{ - int ret = 0; - -#ifdef CONFIG_POWER_MAX77686 - ret = max77686_init(); - if (ret) - return ret; -#endif -#ifdef CONFIG_POWER_TPS65090 - /* - * The TPS65090 may not be in the device tree. If so, it is not - * an error. - */ - ret = tps65090_init(); - if (ret == 0 || ret == -ENODEV) - return 0; -#endif - - return ret; -} -#endif /* CONFIG_POWER */ - -#ifdef CONFIG_LCD -static int board_dp_bridge_setup(void) -{ - const int max_tries = 10; - int num_tries, node; - - /* - * TODO(sjg): Use device tree for GPIOs when exynos GPIO - * numbering patch is in mainline. - */ - debug("%s\n", __func__); - node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460); - if (node < 0) { - debug("%s: No node for DP bridge in device tree\n", __func__); - return -ENODEV; - } - - /* Setup the GPIOs */ - - /* PD is ACTIVE_LOW, and initially de-asserted */ - gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd"); - gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE); - gpio_direction_output(EXYNOS5_GPIO_Y25, 1); - - /* Reset is ACTIVE_LOW */ - gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset"); - gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE); - gpio_direction_output(EXYNOS5_GPIO_X15, 0); - - udelay(10); - gpio_set_value(EXYNOS5_GPIO_X15, 1); - - gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd"); - gpio_direction_input(EXYNOS5_GPIO_X07); - - /* - * We need to wait for 90ms after bringing up the bridge since there - * is a phantom "high" on the HPD chip during its bootup. The phantom - * high comes within 7ms of de-asserting PD and persists for at least - * 15ms. The real high comes roughly 50ms after PD is de-asserted. The - * phantom high makes it hard for us to know when the NXP chip is up. - */ - mdelay(90); - - for (num_tries = 0; num_tries < max_tries; num_tries++) { - /* Check HPD. If it's high, we're all good. */ - if (gpio_get_value(EXYNOS5_GPIO_X07)) - return 0; - - debug("%s: eDP bridge failed to come up; try %d of %d\n", - __func__, num_tries, max_tries); - } - - /* Immediately go into bridge reset if the hp line is not high */ - return -ENODEV; -} - -void exynos_cfg_lcd_gpio(void) -{ - /* For Backlight */ - gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight"); - gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5_GPIO_B20, 1); - - /* LCD power on */ - gpio_request(EXYNOS5_GPIO_X15, "lcd_power"); - gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5_GPIO_X15, 1); - - /* Set Hotplug detect for DP */ - gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); -} - -void exynos_set_dp_phy(unsigned int onoff) -{ - set_dp_phy_ctrl(onoff); -} - -void exynos_backlight_on(unsigned int on) -{ - debug("%s(%u)\n", __func__, on); - - if (!on) - return; - -#ifdef CONFIG_POWER_TPS65090 - int ret; - - ret = tps65090_fet_enable(1); /* Enable FET1, backlight */ - if (ret) - return; - - /* T5 in the LCD timing spec (defined as > 10ms) */ - mdelay(10); - - /* board_dp_backlight_pwm */ - gpio_direction_output(EXYNOS5_GPIO_B20, 1); - - /* T6 in the LCD timing spec (defined as > 10ms) */ - mdelay(10); - - /* board_dp_backlight_en */ - gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en"); - gpio_direction_output(EXYNOS5_GPIO_X30, 1); -#endif -} - -void exynos_lcd_power_on(void) -{ - int ret; - - debug("%s\n", __func__); - -#ifdef CONFIG_POWER_TPS65090 - /* board_dp_lcd_vdd */ - tps65090_fet_enable(6); /* Enable FET6, lcd panel */ -#endif - - ret = board_dp_bridge_setup(); - if (ret && ret != -ENODEV) - printf("LCD bridge failed to enable: %d\n", ret); -} - -#endif diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 29ef84b6a37..8b61a52c5a2 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -16,6 +16,8 @@ "stdout=serial,lcd\0" \ "stderr=serial,lcd\0" +#define CONFIG_EXYNOS5_DT + #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) -- cgit v1.3.1 From 05bccbcd761e7170e236c982915781b143051abb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:32 -0600 Subject: power: Remove old TPS65090 drivers Remove the old drivers (both the normal one and the cros_ec one) now that we have new drivers that use driver model. Signed-off-by: Simon Glass --- drivers/power/pmic/Makefile | 2 - drivers/power/pmic/pmic_tps65090.c | 310 ---------------------------------- drivers/power/pmic/pmic_tps65090_ec.c | 218 ------------------------ include/configs/peach-pit.h | 2 - include/fdtdec.h | 1 - include/power/tps65090_pmic.h | 73 -------- lib/fdtdec.c | 1 - 7 files changed, 607 deletions(-) delete mode 100644 drivers/power/pmic/pmic_tps65090.c delete mode 100644 drivers/power/pmic/pmic_tps65090_ec.c delete mode 100644 include/power/tps65090_pmic.h (limited to 'include/configs') diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 322c2c6cac7..6ef149aee78 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -18,8 +18,6 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o -obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o -obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o diff --git a/drivers/power/pmic/pmic_tps65090.c b/drivers/power/pmic/pmic_tps65090.c deleted file mode 100644 index 337903acec8..00000000000 --- a/drivers/power/pmic/pmic_tps65090.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define TPS65090_NAME "TPS65090_PMIC" - -/* TPS65090 register addresses */ -enum { - REG_IRQ1 = 0, - REG_CG_CTRL0 = 4, - REG_CG_STATUS1 = 0xa, - REG_FET1_CTRL = 0x0f, - REG_FET2_CTRL, - REG_FET3_CTRL, - REG_FET4_CTRL, - REG_FET5_CTRL, - REG_FET6_CTRL, - REG_FET7_CTRL, - TPS65090_NUM_REGS, -}; - -enum { - IRQ1_VBATG = 1 << 3, - CG_CTRL0_ENC_MASK = 0x01, - - MAX_FET_NUM = 7, - MAX_CTRL_READ_TRIES = 5, - - /* TPS65090 FET_CTRL register values */ - FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ - FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ - FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ - FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ - FET_CTRL_ENFET = 1 << 0, /* Enable FET */ -}; - -/** - * Checks for a valid FET number - * - * @param fet_id FET number to check - * @return 0 if ok, -EINVAL if FET value is out of range - */ -static int tps65090_check_fet(unsigned int fet_id) -{ - if (fet_id == 0 || fet_id > MAX_FET_NUM) { - debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", - fet_id, MAX_FET_NUM); - return -EINVAL; - } - - return 0; -} - -/** - * Set the power state for a FET - * - * @param pmic pmic structure for the tps65090 - * @param fet_id Fet number to set (1..MAX_FET_NUM) - * @param set 1 to power on FET, 0 to power off - * @return -EIO if we got a comms error, -EAGAIN if the FET failed to - * change state. If all is ok, returns 0. - */ -static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set) -{ - int retry; - u32 reg, value; - - value = FET_CTRL_ADENFET | FET_CTRL_WAIT; - if (set) - value |= FET_CTRL_ENFET; - - if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value)) - return -EIO; - - /* Try reading until we get a result */ - for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { - if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®)) - return -EIO; - - /* Check that the fet went into the expected state */ - if (!!(reg & FET_CTRL_PGFET) == set) - return 0; - - /* If we got a timeout, there is no point in waiting longer */ - if (reg & FET_CTRL_TOFET) - break; - - mdelay(1); - } - - debug("FET %d: Power good should have set to %d but reg=%#02x\n", - fet_id, set, reg); - return -EAGAIN; -} - -int tps65090_fet_enable(unsigned int fet_id) -{ - struct pmic *pmic; - ulong start; - int loops; - int ret; - - ret = tps65090_check_fet(fet_id); - if (ret) - return ret; - - pmic = pmic_get(TPS65090_NAME); - if (!pmic) - return -EACCES; - - start = get_timer(0); - for (loops = 0;; loops++) { - ret = tps65090_fet_set(pmic, fet_id, true); - if (!ret) - break; - - if (get_timer(start) > 100) - break; - - /* Turn it off and try again until we time out */ - tps65090_fet_set(pmic, fet_id, false); - } - - if (ret) - debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", - __func__, fet_id, get_timer(start), loops); - else if (loops) - debug("%s: FET%d powered on after %lums, loops=%d\n", - __func__, fet_id, get_timer(start), loops); - - /* - * Unfortunately, there are some conditions where the power - * good bit will be 0, but the fet still comes up. One such - * case occurs with the lcd backlight. We'll just return 0 here - * and assume that the fet will eventually come up. - */ - if (ret == -EAGAIN) - ret = 0; - - return ret; -} - -int tps65090_fet_disable(unsigned int fet_id) -{ - struct pmic *pmic; - int ret; - - ret = tps65090_check_fet(fet_id); - if (ret) - return ret; - - pmic = pmic_get(TPS65090_NAME); - if (!pmic) - return -EACCES; - ret = tps65090_fet_set(pmic, fet_id, false); - - return ret; -} - -int tps65090_fet_is_enabled(unsigned int fet_id) -{ - struct pmic *pmic; - u32 reg; - int ret; - - ret = tps65090_check_fet(fet_id); - if (ret) - return ret; - - pmic = pmic_get(TPS65090_NAME); - if (!pmic) - return -ENODEV; - ret = pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®); - if (ret) { - debug("fail to read FET%u_CTRL register over I2C", fet_id); - return -EIO; - } - - return reg & FET_CTRL_ENFET; -} - -int tps65090_get_charging(void) -{ - struct pmic *pmic; - u32 val; - int ret; - - pmic = pmic_get(TPS65090_NAME); - if (!pmic) - return -EACCES; - - ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); - if (ret) - return ret; - - return !!(val & CG_CTRL0_ENC_MASK); -} - -static int tps65090_charger_state(struct pmic *pmic, int state, - int current) -{ - u32 val; - int ret; - - ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); - if (!ret) { - if (state == PMIC_CHARGER_ENABLE) - val |= CG_CTRL0_ENC_MASK; - else - val &= ~CG_CTRL0_ENC_MASK; - ret = pmic_reg_write(pmic, REG_CG_CTRL0, val); - } - if (ret) { - debug("%s: Failed to read/write register\n", __func__); - return ret; - } - - return 0; -} - -int tps65090_get_status(void) -{ - struct pmic *pmic; - u32 val; - int ret; - - pmic = pmic_get(TPS65090_NAME); - if (!pmic) - return -EACCES; - - ret = pmic_reg_read(pmic, REG_CG_STATUS1, &val); - if (ret) - return ret; - - return val; -} - -static int tps65090_charger_bat_present(struct pmic *pmic) -{ - u32 val; - int ret; - - ret = pmic_reg_read(pmic, REG_IRQ1, &val); - if (ret) - return ret; - - return !!(val & IRQ1_VBATG); -} - -static struct power_chrg power_chrg_pmic_ops = { - .chrg_bat_present = tps65090_charger_bat_present, - .chrg_state = tps65090_charger_state, -}; - -int tps65090_init(void) -{ - struct pmic *p; - int bus; - int addr; - const void *blob = gd->fdt_blob; - int node, parent; - - node = fdtdec_next_compatible(blob, 0, COMPAT_TI_TPS65090); - if (node < 0) { - debug("PMIC: No node for PMIC Chip in device tree\n"); - debug("node = %d\n", node); - return -ENODEV; - } - - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Cannot find node parent\n", __func__); - return -EINVAL; - } - - bus = i2c_get_bus_num_fdt(parent); - if (bus < 0) { - debug("%s: Cannot find I2C bus\n", __func__); - return -ENOENT; - } - addr = fdtdec_get_int(blob, node, "reg", TPS65090_I2C_ADDR); - p = pmic_alloc(); - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - p->name = TPS65090_NAME; - p->bus = bus; - p->interface = PMIC_I2C; - p->number_of_regs = TPS65090_NUM_REGS; - p->hw.i2c.addr = addr; - p->hw.i2c.tx_num = 1; - p->chrg = &power_chrg_pmic_ops; - - puts("TPS65090 PMIC init\n"); - - return 0; -} diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c deleted file mode 100644 index f79a8782c9c..00000000000 --- a/drivers/power/pmic/pmic_tps65090_ec.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2013 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define TPS65090_ADDR 0x48 - -static struct tps65090 { - struct cros_ec_dev *dev; /* The CROS_EC device */ -} config; - -/* TPS65090 register addresses */ -enum { - REG_IRQ1 = 0, - REG_CG_CTRL0 = 4, - REG_CG_STATUS1 = 0xa, - REG_FET1_CTRL = 0x0f, - REG_FET2_CTRL, - REG_FET3_CTRL, - REG_FET4_CTRL, - REG_FET5_CTRL, - REG_FET6_CTRL, - REG_FET7_CTRL, - TPS65090_NUM_REGS, -}; - -enum { - IRQ1_VBATG = 1 << 3, - CG_CTRL0_ENC_MASK = 0x01, - - MAX_FET_NUM = 7, - MAX_CTRL_READ_TRIES = 5, - - /* TPS65090 FET_CTRL register values */ - FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ - FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ - FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ - FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ - FET_CTRL_ENFET = 1 << 0, /* Enable FET */ -}; - -/** - * tps65090_read - read a byte from tps6090 - * - * @param reg The register address to read from. - * @param val We'll return value value read here. - * @return 0 if ok; error if EC returns failure. - */ -static int tps65090_read(u32 reg, u8 *val) -{ - return cros_ec_i2c_xfer_old(config.dev, TPS65090_ADDR, reg, 1, - val, 1, true); -} - -/** - * tps65090_write - write a byte to tps6090 - * - * @param reg The register address to write to. - * @param val The value to write. - * @return 0 if ok; error if EC returns failure. - */ -static int tps65090_write(u32 reg, u8 val) -{ - return cros_ec_i2c_xfer_old(config.dev, TPS65090_ADDR, reg, 1, - &val, 1, false); -} - -/** - * Checks for a valid FET number - * - * @param fet_id FET number to check - * @return 0 if ok, -EINVAL if FET value is out of range - */ -static int tps65090_check_fet(unsigned int fet_id) -{ - if (fet_id == 0 || fet_id > MAX_FET_NUM) { - debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", - fet_id, MAX_FET_NUM); - return -EINVAL; - } - - return 0; -} - -/** - * Set the power state for a FET - * - * @param fet_id Fet number to set (1..MAX_FET_NUM) - * @param set 1 to power on FET, 0 to power off - * @return -EIO if we got a comms error, -EAGAIN if the FET failed to - * change state. If all is ok, returns 0. - */ -static int tps65090_fet_set(int fet_id, bool set) -{ - int retry; - u8 reg, value; - - value = FET_CTRL_ADENFET | FET_CTRL_WAIT; - if (set) - value |= FET_CTRL_ENFET; - - if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) - return -EIO; - - /* Try reading until we get a result */ - for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { - if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) - return -EIO; - - /* Check that the fet went into the expected state */ - if (!!(reg & FET_CTRL_PGFET) == set) - return 0; - - /* If we got a timeout, there is no point in waiting longer */ - if (reg & FET_CTRL_TOFET) - break; - - mdelay(1); - } - - debug("FET %d: Power good should have set to %d but reg=%#02x\n", - fet_id, set, reg); - return -EAGAIN; -} - -int tps65090_fet_enable(unsigned int fet_id) -{ - ulong start; - int loops; - int ret; - - ret = tps65090_check_fet(fet_id); - if (ret) - return ret; - - start = get_timer(0); - for (loops = 0;; loops++) { - ret = tps65090_fet_set(fet_id, true); - if (!ret) - break; - - if (get_timer(start) > 100) - break; - - /* Turn it off and try again until we time out */ - tps65090_fet_set(fet_id, false); - } - - if (ret) { - debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", - __func__, fet_id, get_timer(start), loops); - } else if (loops) { - debug("%s: FET%d powered on after %lums, loops=%d\n", - __func__, fet_id, get_timer(start), loops); - } - /* - * Unfortunately, there are some conditions where the power - * good bit will be 0, but the fet still comes up. One such - * case occurs with the lcd backlight. We'll just return 0 here - * and assume that the fet will eventually come up. - */ - if (ret == -EAGAIN) - ret = 0; - - return ret; -} - -int tps65090_fet_disable(unsigned int fet_id) -{ - int ret; - - ret = tps65090_check_fet(fet_id); - if (ret) - return ret; - - ret = tps65090_fet_set(fet_id, false); - - return ret; -} - -int tps65090_fet_is_enabled(unsigned int fet_id) -{ - u8 reg = 0; - int ret; - - ret = tps65090_check_fet(fet_id); - if (ret) - return ret; - ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); - if (ret) { - debug("fail to read FET%u_CTRL register over I2C", fet_id); - return -EIO; - } - - return reg & FET_CTRL_ENFET; -} - -int tps65090_init(void) -{ - puts("TPS65090 PMIC EC init\n"); - - config.dev = board_get_cros_ec_dev(); - if (!config.dev) { - debug("%s: no cros_ec device: cannot init tps65090\n", - __func__); - return -ENODEV; - } - - return 0; -} diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 18be42c86eb..beb65b007d8 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -34,8 +34,6 @@ #define CONFIG_VIDEO_PARADE -#define CONFIG_POWER_TPS65090_EC - /* DRAM Memory Banks */ #define CONFIG_NR_DRAM_BANKS 4 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 4b3f8d13c35..12dc5fd2fad 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -170,7 +170,6 @@ enum fdt_compat_id { COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ - COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h deleted file mode 100644 index dcf99c956a5..00000000000 --- a/include/power/tps65090_pmic.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __TPS65090_PMIC_H_ -#define __TPS65090_PMIC_H_ - -/* I2C device address for TPS65090 PMU */ -#define TPS65090_I2C_ADDR 0x48 - -enum { - /* Status register fields */ - TPS65090_ST1_OTC = 1 << 0, - TPS65090_ST1_OCC = 1 << 1, - TPS65090_ST1_STATE_SHIFT = 4, - TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, -}; - -/** - * Enable FET - * - * @param fet_id FET ID, value between 1 and 7 - * @return 0 on success, non-0 on failure - */ -int tps65090_fet_enable(unsigned int fet_id); - -/** - * Disable FET - * - * @param fet_id FET ID, value between 1 and 7 - * @return 0 on success, non-0 on failure - */ -int tps65090_fet_disable(unsigned int fet_id); - -/** - * Is FET enabled? - * - * @param fet_id FET ID, value between 1 and 7 - * @return 1 enabled, 0 disabled, negative value on failure - */ -int tps65090_fet_is_enabled(unsigned int fet_id); - -/** - * Enable / disable the battery charger - * - * @param enable 0 to disable charging, non-zero to enable - */ -int tps65090_set_charge_enable(int enable); - -/** - * Check whether we have enabled battery charging - * - * @return 1 if enabled, 0 if disabled - */ -int tps65090_get_charging(void); - -/** - * Return the value of the status register - * - * @return status register value, or -1 on error - */ -int tps65090_get_status(void); - -/** - * Initialize the TPS65090 PMU. - * - * @return 0 on success, non-0 on failure - */ -int tps65090_init(void); - -#endif /* __TPS65090_PMIC_H_ */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 48667efcb58..3d20f388e06 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -62,7 +62,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645tt"), COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), - COMPAT(TI_TPS65090, "ti,tps65090"), COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), -- cgit v1.3.1 From 68964dbc838077c8ecd796fd43b0aa43bb309a50 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:34 -0600 Subject: video: Remove the old parade driver We have a new one which uses driver model and device tree configuration. Remove the old one. Signed-off-by: Simon Glass --- drivers/video/Makefile | 1 - drivers/video/parade.c | 231 -------------------------------------------- include/configs/peach-pi.h | 2 - include/configs/peach-pit.h | 2 - include/fdtdec.h | 1 - include/parade.h | 18 ---- lib/fdtdec.c | 1 - 7 files changed, 256 deletions(-) delete mode 100644 drivers/video/parade.c delete mode 100644 include/parade.h (limited to 'include/configs') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 599fe83b33a..c2c4dfc57ea 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -51,7 +51,6 @@ obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_AM335X_LCD) += am335x-fb.o -obj-$(CONFIG_VIDEO_PARADE) += parade.o obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ diff --git a/drivers/video/parade.c b/drivers/video/parade.c deleted file mode 100644 index ae5097160f7..00000000000 --- a/drivers/video/parade.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file is a driver for Parade dP<->LVDS bridges. The original submission - * is for the ps8625 chip. - */ -#include -#include -#include -#include -#include - -/* - * Initialization of the chip is a process of writing certaing values into - * certain registers over i2c bus. The chip in fact responds to a range of - * addresses on the i2c bus, so for each written value three parameters are - * required: i2c address, register address and the actual value. - * - * The base address is derived from the device tree, only address offset is - * stored in the table below. - */ -/** - * struct reg_data() - data for a parade register write - * - * @addr_off offset from the i2c base address for parade - * @reg_addr register address to write - * @value value to be written - */ -struct reg_data { - uint8_t addr_off; - uint8_t reg; - uint8_t value; -} _packed; - -#define END_OF_TABLE 0xff /* Ficticious offset */ - -static const struct reg_data parade_values[] = { - {0x02, 0xa1, 0x01}, /* HPD low */ - /* - * SW setting - * [1:0] SW output 1.2V voltage is lower to 96% - */ - {0x04, 0x14, 0x01}, - /* - * RCO SS setting - * [5:4] = b01 0.5%, b10 1%, b11 1.5% - */ - {0x04, 0xe3, 0x20}, - {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */ - /* - * RPHY Setting - * [3:2] CDR tune wait cycle before - * measure for fine tune b00: 1us, - * 01: 0.5us, 10:2us, 11:4us. - */ - {0x04, 0x8a, 0x0c}, - {0x04, 0x89, 0x08}, /* [3] RFD always on */ - /* - * CTN lock in/out: - * 20000ppm/80000ppm. Lock out 2 - * times. - */ - {0x04, 0x71, 0x2d}, - /* - * 2.7G CDR settings - * NOF=40LSB for HBR CDR setting - */ - {0x04, 0x7d, 0x07}, - {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */ - {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */ - /* - * 1.62G CDR settings - * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 - */ - {0x04, 0xc0, 0x12}, - {0x04, 0xc1, 0x92}, /* Gitune=-37% */ - {0x04, 0xc2, 0x1c}, /* Fbstep=100% */ - {0x04, 0x32, 0x80}, /* [7] LOS signal disable */ - /* - * RPIO Setting - * [7:4] LVDS driver bias current : - * 75% (250mV swing) - */ - {0x04, 0x00, 0xb0}, - /* - * [7:6] Right-bar GPIO output strength is 8mA - */ - {0x04, 0x15, 0x40}, - /* EQ Training State Machine Setting */ - {0x04, 0x54, 0x10}, /* RCO calibration start */ - /* [4:0] MAX_LANE_COUNT set to one lane */ - {0x01, 0x02, 0x81}, - /* [4:0] LANE_COUNT_SET set to one lane */ - {0x01, 0x21, 0x81}, - {0x00, 0x52, 0x20}, - {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */ - {0x00, 0x62, 0x41}, - /* Counter number, add 1ms counter delay */ - {0x00, 0xf6, 0x01}, - /* - * [6]PWM function control by - * DPCD0040f[7], default is PWM - * block always works. - */ - {0x00, 0x77, 0x06}, - /* - * 04h Adjust VTotal tolerance to - * fix the 30Hz no display issue - */ - {0x00, 0x4c, 0x04}, - /* DPCD00400='h00, Parade OUI = 'h001cf8 */ - {0x01, 0xc0, 0x00}, - {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */ - {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */ - /* - * DPCD403~408 = ASCII code - * D2SLV5='h4432534c5635 - */ - {0x01, 0xc3, 0x44}, - {0x01, 0xc4, 0x32}, /* DPCD404 */ - {0x01, 0xc5, 0x53}, /* DPCD405 */ - {0x01, 0xc6, 0x4c}, /* DPCD406 */ - {0x01, 0xc7, 0x56}, /* DPCD407 */ - {0x01, 0xc8, 0x35}, /* DPCD408 */ - /* - * DPCD40A, Initial Code major revision - * '01' - */ - {0x01, 0xca, 0x01}, - /* DPCD40B, Initial Code minor revision '05' */ - {0x01, 0xcb, 0x05}, - /* DPCD720, Select internal PWM */ - {0x01, 0xa5, 0xa0}, - /* - * FFh for 100% PWM of brightness, 0h for 0% - * brightness - */ - {0x01, 0xa7, 0xff}, - /* - * Set LVDS output as 6bit-VESA mapping, - * single LVDS channel - */ - {0x01, 0xcc, 0x13}, - /* Enable SSC set by register */ - {0x02, 0xb1, 0x20}, - /* - * Set SSC enabled and +/-1% central - * spreading - */ - {0x04, 0x10, 0x16}, - /* MPU Clock source: LC => RCO */ - {0x04, 0x59, 0x60}, - {0x04, 0x54, 0x14}, /* LC -> RCO */ - {0x02, 0xa1, 0x91}, /* HPD high */ - {END_OF_TABLE} -}; - -/** - * Write values table into the Parade eDP bridge - * - * @return 0 on success, non-0 on failure - */ - -static int parade_write_regs(int base_addr, const struct reg_data *table) -{ - int ret = 0; - - while (!ret && (table->addr_off != END_OF_TABLE)) { - ret = i2c_write(base_addr + table->addr_off, - table->reg, 1, - (uint8_t *)&table->value, - sizeof(table->value)); - table++; - } - return ret; -} - -int parade_init(const void *blob) -{ - struct gpio_desc rst_gpio; - struct gpio_desc slp_gpio; - int bus, old_bus; - int parent; - int node; - int addr; - int ret; - - node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625); - if (node < 0) - return 0; - - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Could not find parent i2c node\n", __func__); - return -1; - } - addr = fdtdec_get_int(blob, node, "reg", -1); - if (addr < 0) { - debug("%s: Could not find i2c address\n", __func__); - return -1; - } - - gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - mdelay(10); - - gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - bus = i2c_get_bus_num_fdt(parent); - old_bus = i2c_get_bus_num(); - - debug("%s: Using i2c bus %d\n", __func__, bus); - - /* - * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay - * here. - */ - mdelay(40); - i2c_set_bus_num(bus); - ret = parade_write_regs(addr, parade_values); - - i2c_set_bus_num(old_bus); - - return ret; -} diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index b97faf2c3b0..0f5e9feeac3 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -32,8 +32,6 @@ #define CONFIG_SYS_PROMPT "Peach-Pi # " #define CONFIG_IDENT_STRING " for Peach-Pi" -#define CONFIG_VIDEO_PARADE - /* Display */ #define CONFIG_LCD #ifdef CONFIG_LCD diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index beb65b007d8..f2594345c30 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -32,8 +32,6 @@ #define CONFIG_SYS_PROMPT "Peach-Pit # " #define CONFIG_IDENT_STRING " for Peach-Pit" -#define CONFIG_VIDEO_PARADE - /* DRAM Memory Banks */ #define CONFIG_NR_DRAM_BANKS 4 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 12dc5fd2fad..b994f2c7833 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -172,7 +172,6 @@ enum fdt_compat_id { COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ - COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_MEMORY_SPD, /* Memory SPD information */ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ diff --git a/include/parade.h b/include/parade.h deleted file mode 100644 index 887f56dcf26..00000000000 --- a/include/parade.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PARADE_H__ -#define __PARADE_H__ - -/* Initialize the Parade dP<->LVDS bridge if present */ -#ifdef CONFIG_VIDEO_PARADE -int parade_init(const void *blob); -#else -static inline int parade_init(const void *blob) { return -1; } -#endif - -#endif /* __PARADE_H__ */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 3d20f388e06..527916311b2 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -64,7 +64,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), - COMPAT(PARADE_PS8625, "parade,ps8625"), COMPAT(INTEL_MICROCODE, "intel,microcode"), COMPAT(MEMORY_SPD, "memory-spd"), COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"), -- cgit v1.3.1 From d1de41d7fa68b29510da1320d6646fcc19113af2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 3 Aug 2015 08:19:37 -0600 Subject: exynos: Add support for spring Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/exynos/Kconfig | 6 + arch/arm/dts/Makefile | 1 + arch/arm/dts/exynos5250-spring.dts | 588 +++++++++++++++++++++++++++++++++++++ board/samsung/smdk5250/Kconfig | 13 + board/samsung/smdk5250/MAINTAINERS | 6 + configs/spring_defconfig | 42 +++ include/configs/spring.h | 20 ++ 7 files changed, 676 insertions(+) create mode 100644 arch/arm/dts/exynos5250-spring.dts create mode 100644 configs/spring_defconfig create mode 100644 include/configs/spring.h (limited to 'include/configs') diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 4a7d82f74c1..37b89b00131 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -51,6 +51,12 @@ config TARGET_SNOW select OF_CONTROL select SPL_DISABLE_OF_CONTROL +config TARGET_SPRING + bool "Spring board" + select SUPPORT_SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + config TARGET_SMDK5420 bool "SMDK5420 board" select SUPPORT_SPL diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6355379cb..2df957cf56a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ + exynos5250-spring.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts new file mode 100644 index 00000000000..76d5323dc31 --- /dev/null +++ b/arch/arm/dts/exynos5250-spring.dts @@ -0,0 +1,588 @@ +/* + * Google Spring board device tree source + * + * Copyright (c) 2013 Google, Inc + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "exynos5250.dtsi" + +/ { + model = "Google Spring"; + compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; + + aliases { + i2c0 = "/i2c@12C60000"; + i2c1 = "/i2c@12C70000"; + i2c2 = "/i2c@12C80000"; + i2c3 = "/i2c@12C90000"; + i2c4 = "/i2c@12CA0000"; + i2c5 = "/i2c@12CB0000"; + i2c6 = "/i2c@12CC0000"; + i2c7 = "/i2c@12CD0000"; + i2c104 = &cros_ec_ldo_tunnel; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12000000"; + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + i2s = "/sound@3830000"; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + flash@0 { + spl { /* spl size override */ + size = <0x8000>; + }; + }; + + chosen { + bootargs = "console=tty1"; + stdout-path = "serial3:115200n8"; + }; + + board-rev { + compatible = "google,board-revision"; + google,board-rev-gpios = <&gpy4 0 0>, <&gpy4 1 0>, + <&gpy4 2 0>; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + /* MMC2 pins are used as GPIO for eDP bridge */ + status = "disabled"; + }; + + mmc@12230000 { + status = "disabled"; + }; + + ehci@12110000 { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; + }; + + spi@12d30000 { + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + compatible = "spi-flash"; + reg = <0>; + }; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1366>; + samsung,vl-row = <768>; + samsung,vl-width = <1366>; + samsung,vl-height = <768>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-hsp; + samsung,vl-vsp; + + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <5>; + samsung,vl-vbpd = <14>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <0>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + s5m8767-pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + wakeup-source; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ + + /* + * The following arrays of DVS voltages are not used, since we are + * not using GPIOs to control PMIC bucks, but they must be defined + * to please the driver. + */ + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", + "en32khz_cp", + "en32khz_bt"; + }; + + regulators { + ldo4_reg: LDO4 { + regulator-name = "P1.0V_LDO_OUT4"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo5_reg: LDO5 { + regulator-name = "P1.8V_LDO_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_mydp"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo17_reg: LDO17 { + regulator-name = "P1.2V_LDO_OUT17"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo25_reg: LDO25 { + regulator-name = "vdd_bridge"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + op_mode = <3>; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.2V_BUCK_OUT6"; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + regulator-always-on; + regulator-boot-on; + op_mode = <0>; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_ummc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + clock-frequency = <66000>; + + cros_ec: embedded-controller { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + wakeup-source; + u-boot,i2c-offset-len = <0>; + ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; + cros_ec_ldo_tunnel: cros-ec-ldo-tunnel { + compatible = "google,cros-ec-ldo-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + power-regulator { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + dcdc1 { + ti,enable-ext-control; + }; + dcdc2 { + ti,enable-ext-control; + }; + dcdc3 { + ti,enable-ext-control; + }; + fet1: fet1 { + regulator-name = "vcd_led"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet4 { + regulator-name = "sdcard"; + ti,overcurrent-wait = <3>; + }; + fet5 { + regulator-name = "camout"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet6: fet6 { + regulator-name = "lcd_vdd"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + ldo1 { + }; + ldo2 { + }; + }; + }; + }; + }; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + ps8622-bridge@8 { + compatible = "parade,ps8622"; + reg = <0x8>; + sleep-gpios = <&gpc3 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpc3 1 GPIO_ACTIVE_LOW>; + hotplug-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; + power-supply = <&ldo6_reg>; + parade,regs = /bits/ 8 < + 0x02 0xa1 0x01 /* HPD low */ + /* + * SW setting: [1:0] SW output 1.2V voltage is + * lower to 96% + */ + 0x04 0x14 0x01 + /* RCO SS setting: [5:4] = b01 0.5%, b10 1%, b11 1.5% */ + 0x04 0xe3 0x20 + 0x04 0xe2 0x80 /* [7] RCO SS enable */ + /* + * RPHY Setting: [3:2] CDR tune wait cycle before + * measure for fine tune b00: 1us, + * 01: 0.5us, 10:2us, 11:4us + */ + 0x04 0x8a 0x0c + 0x04 0x89 0x08 /* [3] RFD always on */ + /* + * CTN lock in/out: 20000ppm/80000ppm. Lock out 2 times + */ + 0x04 0x71 0x2d + /* 2.7G CDR settings */ + 0x04 0x7d 0x07 /* NOF=40LSB for HBR CDR setting */ + 0x04 0x7b 0x00 /* [1:0] Fmin=+4bands */ + 0x04 0x7a 0xfd /* [7:5] DCO_FTRNG=+-40% */ + /* + * 1.62G CDR settings: + * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 + */ + 0x04 0xc0 0x12 + 0x04 0xc1 0x92 /* Gitune=-37% */ + 0x04 0xc2 0x1c /* Fbstep=100% */ + 0x04 0x32 0x80 /* [7] LOS signal disable */ + /* RPIO Setting */ + /* [7:4] LVDS driver bias current 75% (250mV swing) */ + 0x04 0x00 0xb0 + /* [7:6] Right-bar GPIO output strength is 8mA */ + 0x04 0x15 0x40 + /* EQ Training State Machine Setting */ + 0x04 0x54 0x10 /* RCO calibration start */ + /* [4:0] MAX_LANE_COUNT set to one lane */ + 0x01 0x02 0x81 + /* [4:0] LANE_COUNT_SET set to one lane */ + 0x01 0x21 0x81 + 0x00 0x52 0x20 + 0x00 0xf1 0x03 /* HPD CP toggle enable */ + 0x00 0x62 0x41 + /* Counter number add 1ms counter delay */ + 0x00 0xf6 0x01 + /* + * [6]PWM function control by DPCD0040f[7], default + * is PWM block always works + */ + 0x00 0x77 0x06 + 0x00 0x4c 0x04 + /* + * 04h Adjust VTotal tolerance to fix the 30Hz no- + * display issue + * DPCD00400='h00 Parade OUI = 'h001cf8 + */ + 0x01 0xc0 0x00 + 0x01 0xc1 0x1c /* DPCD00401='h1c */ + 0x01 0xc2 0xf8 /* DPCD00402='hf8 */ + /* DPCD403~408 = ASCII code D2SLV5='h4432534c5635 */ + 0x01 0xc3 0x44 + 0x01 0xc4 0x32 /* DPCD404 */ + 0x01 0xc5 0x53 /* DPCD405 */ + 0x01 0xc6 0x4c /* DPCD406 */ + 0x01 0xc7 0x56 /* DPCD407 */ + 0x01 0xc8 0x35 /* DPCD408 */ + /* DPCD40A Initial Code major revision '01' */ + 0x01 0xca 0x01 + /* DPCD40B Initial Code minor revision '05' */ + 0x01 0xcb 0x05 + 0x01 0xa5 0xa0 /* DPCD720, Select internal PWM */ + /* + * 0xff for 100% PWM of brightness, 0h for 0% brightness + */ + 0x01 0xa7 0x00 + /* + * Set LVDS output as 6bit-VESA mapping, single LVDS + * channel + */ + 0x01 0xcc 0x13 + 0x02 0xb1 0x20 /* Enable SSC set by register */ + /* Set SSC enabled and +/-1% central spreading */ + 0x04 0x10 0x16 + 0x04 0x59 0x60 /* MPU Clock source: LC => RCO */ + 0x04 0x54 0x14 /* LC -> RCO */ + 0x02 0xa1 0x91>; /* HPD high */ + }; + + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98088-codec"; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/board/samsung/smdk5250/Kconfig b/board/samsung/smdk5250/Kconfig index 698ee9125c9..11ffaee5ce1 100644 --- a/board/samsung/smdk5250/Kconfig +++ b/board/samsung/smdk5250/Kconfig @@ -23,3 +23,16 @@ config SYS_CONFIG_NAME default "snow" endif + +if TARGET_SPRING + +config SYS_BOARD + default "smdk5250" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "spring" + +endif diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS index 070593e266e..cde966fdbf9 100644 --- a/board/samsung/smdk5250/MAINTAINERS +++ b/board/samsung/smdk5250/MAINTAINERS @@ -10,3 +10,9 @@ M: Akshay Saraswat S: Maintained F: include/configs/snow.h F: configs/snow_defconfig + +SPRING BOARD +M: Simon Glass +S: Maintained +F: include/configs/spring.h +F: configs/spring_defconfig diff --git a/configs/spring_defconfig b/configs/spring_defconfig new file mode 100644 index 00000000000..a3abb354703 --- /dev/null +++ b/configs/spring_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_SPRING=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SOUND=y +CONFIG_SPI_FLASH=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_KEYB=y +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98095=y +CONFIG_SOUND_WM8994=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_PMIC_TPS65090=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_I2C_COMPAT=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_MUX=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_ERRNO_STR=y +CONFIG_DM_PMIC_MAX77686=y +CONFIG_DM_REGULATOR_MAX77686=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_S5P=y +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BASE=0x12c30000 +CONFIG_I2C_CROS_EC_LDO=y +CONFIG_PMIC_S5M8767=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y diff --git a/include/configs/spring.h b/include/configs/spring.h new file mode 100644 index 00000000000..a692dfd7ec7 --- /dev/null +++ b/include/configs/spring.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SPRING_H +#define __CONFIG_SPRING_H + +#include +#include +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_PROMPT "spring # " +#define CONFIG_IDENT_STRING " for spring" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#endif /* __CONFIG_SPRING_H */ -- cgit v1.3.1