From fe258048a4568efa26cf459809851c3bcd61ea7d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Apr 2019 07:55:12 +0000 Subject: imx8: mek: move HUSH_PARSER to defconfig Move HUSH_PARSER to defconfig, otherwise meet " => run netboot Booting from net ... Unknown command 'if' - try 'help' Unknown command 'then' - try 'help' Unknown command 'else' - try 'help' Unknown command 'fi' - try 'help' Unknown command '0x80280000' - try 'help' Unknown command 'if' - try 'help' Unknown command 'then' - try 'help' Unknown command 'then' - try 'help' Unknown command 'else' - try 'help' Unknown command 'fi' - try 'help' Unknown command 'else' - try 'help' Unknown command 'fi' - try 'help' " Signed-off-by: Peng Fan --- include/configs/imx8qxp_mek.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 312e30dc6c1..1cff18e05e9 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -159,7 +159,6 @@ #define CONFIG_BAUDRATE 115200 /* Monitor Command Prompt */ -#define CONFIG_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 -- cgit v1.3.1 From fd1a2d7e778f0ca671dacecafc569cded1b32ec6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 11 Apr 2019 13:46:09 -0500 Subject: ARM: imx6q_logic: Allow optional arguments to cmd line This adds an extra, optional environmental variable called 'optargs' which if enabled allow additional parameters to be passed to the kernel (ie, quiet, cma=128M, etc.) Each script that setups the bootargs will just append this. Signed-off-by: Adam Ford --- include/configs/imx6_logic.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index ad45b106b05..dbf566522f3 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -46,11 +46,11 @@ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console},${baudrate}" \ - " root=PARTUUID=${uuid} rootwait rw\0 ${mtdparts}\0" \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ "nandargs=setenv bootargs console=${console},${baudrate}" \ - " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \ + " ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \ "ramargs=setenv bootargs console=${console},${baudrate}" \ - " root=/dev/ram rw ${mtdparts}\0" \ + " root=/dev/ram rw ${mtdparts} ${optargs}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...;" \ -- cgit v1.3.1 From c7d00f63d1d1c5e21ea4bf045370018638d0693e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 11 Apr 2019 15:24:33 -0500 Subject: ARM: omap3_logic: Enable UUID Instead of hardcoding the mmcroot to /dev/mmcblkX, use the UUID method. Signed-off-by: Adam Ford --- configs/omap35_logic_defconfig | 1 + configs/omap35_logic_somlv_defconfig | 1 + configs/omap3_logic_defconfig | 1 + configs/omap3_logic_somlv_defconfig | 1 + include/configs/omap3_logic.h | 6 ++++-- 5 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 5b5f3eb7b47..9a1596c89b4 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 396f3216995..961be133994 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index b38b6fd75a8..41fb0341b95 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index c6106c5d23a..c5e6a29e47e 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index fe557f91caa..9db9668703a 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -67,7 +67,7 @@ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcrootfstype=ext4 rootwait\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \ "nandrootfstype=ubifs rootwait\0" \ @@ -106,7 +106,8 @@ "ramargs=setenv bootargs "\ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ "mmcargs=setenv bootargs "\ - "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \ + "root=PARTUUID=${uuid} " \ + "rootfstype=${mmcrootfstype} rw\0" \ "nandargs=setenv bootargs "\ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ @@ -120,6 +121,7 @@ "loadfdt=mmc rescan; " \ "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ "mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \ + "run finduuid; "\ "run mmcargs; " \ "run common_bootargs; " \ "run dump_bootargs; " \ -- cgit v1.3.1 From e4b9f5244dcc9ecf37a862fa062f4d5b1a5eccff Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:46 +0200 Subject: ARM: defconfig: Move CONFIG_FSL_ESDHC to Kconfig The CONFIG_FSL_ESDHC is now enabled and defined in Kconfig, not in include/configs/kp_imx53.h Signed-off-by: Lukasz Majewski --- configs/kp_imx53_defconfig | 1 + include/configs/kp_imx53.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index cfe96fcce5e..4be67d17364 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" CONFIG_ENV_IS_IN_MMC=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_FEC_MXC=y diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 3ea75fa120c..f82dcd84267 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) /* MMC Configs */ -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 1 -- cgit v1.3.1 From 63984abc1d84bdaeb57c0e25127fa9cc948ab7fd Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:47 +0200 Subject: ARM: Remove non DM/DTS esdhc3 code from HSC|DDC board related files After switching to DM/DTS support of esdhc3 - the code in this patch can be removed. Signed-off-by: Lukasz Majewski --- board/k+p/kp_imx53/kp_imx53.c | 46 ------------------------------------------- include/configs/kp_imx53.h | 4 ---- 2 files changed, 50 deletions(-) (limited to 'include/configs') diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index ab17904c6e5..3c7f652eec3 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -13,8 +13,6 @@ #include #include #include -#include -#include #include #include #include "kp_id_rev.h" @@ -53,50 +51,6 @@ int board_ehci_hcd_init(int port) } #endif -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[] = { - {MMC_SDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* eMMC is always present */ -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - int ret; - - static const iomux_v3_cfg_t sd3_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - if (ret) - return ret; - - return 0; -} -#endif - static int power_init(void) { struct udevice *dev; diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index f82dcd84267..ca6ab0fabc7 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -15,10 +15,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - /* USB Configs */ #define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 -- cgit v1.3.1 From ddba5e5961b766ba3d7e97967e64745a3330edbe Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:48 +0200 Subject: ARM: kp_imx53: config: Do not use ${boardtype} to setup update wic file After unification of the rootfs for both HSC and DDC devices, only one, common wic file is necessary - without the distinction of specific board. Signed-off-by: Lukasz Majewski --- include/configs/kp_imx53.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index ca6ab0fabc7..9bbf590b727 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -52,7 +52,7 @@ "setexpr blkc ${blkc} + 1; " \ "mmc write ${loadaddr} 0x2 ${blkc}" \ "; fi\0" \ - "upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\ + "upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\ "if tftp ${loadaddr} ${wic_file}; then " \ "setexpr blkc ${filesize} / 0x200; " \ "setexpr blkc ${blkc} + 1; " \ -- cgit v1.3.1 From 52b239ccd11501ca233c419897849bdbc9731d43 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:54 +0200 Subject: ARM: config: Remove not needed CONFIG_MXC_USB_PORT define After i.MX5's EHCI conversion to DM, the CONFIG_MXC_USB_PORT is not needed anymore and should be removed. Signed-off-by: Lukasz Majewski --- include/configs/kp_imx53.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 9bbf590b727..d09608df35e 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -17,7 +17,6 @@ /* USB Configs */ #define CONFIG_USB_EHCI_MX5 -#define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -- cgit v1.3.1 From 400b972a7eb7756dcf111990d6d16187c30ae9db Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:55 +0200 Subject: Convert CONFIG_USB_EHCI_MX5 to Kconfig This converts the following to Kconfig: CONFIG_USB_EHCI_MX5 Signed-off-by: Lukasz Majewski --- configs/kp_imx53_defconfig | 1 + configs/m53menlo_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/mx53loco_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/usbarmory_defconfig | 1 + drivers/usb/host/Kconfig | 7 +++++++ include/configs/kp_imx53.h | 1 - include/configs/m53menlo.h | 1 - include/configs/mx51evk.h | 1 - include/configs/mx53cx9020.h | 1 - include/configs/mx53loco.h | 1 - include/configs/mx53ppd.h | 1 - include/configs/usbarmory.h | 1 - scripts/config_whitelist.txt | 1 - 15 files changed, 13 insertions(+), 8 deletions(-) (limited to 'include/configs') diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 45227c26d25..225be660195 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -45,4 +45,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=2 CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index e830b2c92e1..e10cb8ed8d4 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -58,6 +58,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_RTC_M41T62=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index dc0b3b3f779..78aa89d6513 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -26,6 +26,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 776fc8bab44..caf04ad8941 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -26,6 +26,7 @@ CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_MII=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 2a6183b77b5..2379ab8c66d 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MII=y CONFIG_RTC_S35392A=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index b1f872405b7..46f9996e18b 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -15,4 +15,5 @@ CONFIG_CMD_USB=y CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_OF_LIBFDT=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0fbc1158011..1c2212f547b 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -132,6 +132,13 @@ config USB_EHCI_MARVELL ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. +config USB_EHCI_MX5 + bool "Support for i.MX5 on-chip EHCI USB controller" + depends on ARCH_MX5 + default n + help + Enables support for the on-chip EHCI controller on i.MX5 SoCs. + config USB_EHCI_MX6 bool "Support for i.MX6 on-chip EHCI USB controller" depends on ARCH_MX6 diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index d09608df35e..a252e9003de 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 84d061339ec..82842d8426b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -118,7 +118,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 9bf9773c69d..f5fd01de220 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -61,7 +61,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 1e3ea88b77a..9bf5d9169b4 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -41,7 +41,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 2d18f05423b..4f179081a8a 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -38,7 +38,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index f002324fddc..2d6715cba26 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -37,7 +37,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 270f325a55e..128f02db66f 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_FSL_ESDHC_NUM 1 /* USB */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 421362d9532..d9caa2b8d4b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4504,7 +4504,6 @@ CONFIG_USB_EHCI_BASE_LIST CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY CONFIG_USB_EHCI_KIRKWOOD -CONFIG_USB_EHCI_MX5 CONFIG_USB_EHCI_MXC CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_SPEAR -- cgit v1.3.1 From 0d331c035a091c1c1af4180b40bd234e3b87e80a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 Mar 2019 02:32:49 +0000 Subject: imx: support i.MX8QM MEK board Add i.MX8QM MEK board support. Included a basic dts, enabled SPL FIT Boot log as below: U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) Normal Boot Trying to boot from MMC2_2 U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) CPU: NXP i.MX8QM RevB A53 at 142933 MHz Model: Freescale i.MX8QM MEK Board: iMX8QM MEK Build: SCFW 9330215b Boot: SD1 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Error: ethernet@5b040000 address not set. eth-1: ethernet@5b040000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 112 +++++++++++++++++++ arch/arm/dts/fsl-imx8qm-mek.dts | 184 ++++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 ++ board/freescale/imx8qm_mek/Kconfig | 14 +++ board/freescale/imx8qm_mek/MAINTAINERS | 6 ++ board/freescale/imx8qm_mek/Makefile | 8 ++ board/freescale/imx8qm_mek/README | 57 ++++++++++ board/freescale/imx8qm_mek/imx8qm_mek.c | 157 +++++++++++++++++++++++++++ board/freescale/imx8qm_mek/imximage.cfg | 19 ++++ board/freescale/imx8qm_mek/spl.c | 75 +++++++++++++ configs/imx8qm_mek_defconfig | 75 +++++++++++++ include/configs/imx8qm_mek.h | 176 ++++++++++++++++++++++++++++++ 13 files changed, 892 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qm-mek.dts create mode 100644 board/freescale/imx8qm_mek/Kconfig create mode 100644 board/freescale/imx8qm_mek/MAINTAINERS create mode 100644 board/freescale/imx8qm_mek/Makefile create mode 100644 board/freescale/imx8qm_mek/README create mode 100644 board/freescale/imx8qm_mek/imx8qm_mek.c create mode 100644 board/freescale/imx8qm_mek/imximage.cfg create mode 100644 board/freescale/imx8qm_mek/spl.c create mode 100644 configs/imx8qm_mek_defconfig create mode 100644 include/configs/imx8qm_mek.h (limited to 'include/configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5fe998914ad..ed99113d867 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -561,7 +561,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8) += \ + fsl-imx8qxp-mek.dtb \ + fsl-imx8qm-mek.dtb \ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi new file mode 100644 index 00000000000..5d50eb028e4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts new file mode 100644 index 00000000000..63908ba6bf1 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" +#include "fsl-imx8qm-mek-u-boot.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <4800>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4336a8c2369..c32f7dbb61e 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -32,8 +32,14 @@ config TARGET_IMX8QXP_MEK select BOARD_LATE_INIT select IMX8QXP +config TARGET_IMX8QM_MEK + bool "Support i.MX8QM MEK board" + select BOARD_LATE_INIT + select IMX8QM + endchoice source "board/freescale/imx8qxp_mek/Kconfig" +source "board/freescale/imx8qm_mek/Kconfig" endif diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig new file mode 100644 index 00000000000..93d7d5f9c57 --- /dev/null +++ b/board/freescale/imx8qm_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_MEK + +config SYS_BOARD + default "imx8qm_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qm_mek/MAINTAINERS b/board/freescale/imx8qm_mek/MAINTAINERS new file mode 100644 index 00000000000..115830df19b --- /dev/null +++ b/board/freescale/imx8qm_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QM MEK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx8qm_mek/ +F: include/configs/imx8qm_mek.h +F: configs/imx8qm_mek_defconfig diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile new file mode 100644 index 00000000000..bc9a1260bde --- /dev/null +++ b/board/freescale/imx8qm_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_mek.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README new file mode 100644 index 00000000000..c3523801ae9 --- /dev/null +++ b/board/freescale/imx8qm_mek/README @@ -0,0 +1,57 @@ +U-Boot for the NXP i.MX8QM EVK board + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qm/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmwares U-Boot folder : + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . + +Build U-Boot +============ +$ export ATF_LOAD_ADDR=0x80000000 +$ export BL33_LOAD_ADDR=0x80020000 +$ make imx8qm_mek_defconfig +$ make flash.bin +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch SW2: 1100. diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c new file mode 100644 index 00000000000..e69efc4dd62 --- /dev/null +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + int ret; + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + /* Power up UART0 */ + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (ret) + return ret; + + /* Enable UART0 clock root */ + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (ret) + return ret; + + setup_iomux_uart(); + + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 when the build info is not supported*/ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Board: iMX8QM MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + /* Power up base board */ + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); + + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QM"); +#endif + + return 0; +} diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg new file mode 100644 index 00000000000..7dc6b93eb58 --- /dev/null +++ b/board/freescale/imx8qm_mek/imximage.cfg @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c new file mode 100644 index 00000000000..95ce9f37e8b --- /dev/null +++ b/board/freescale/imx8qm_mek/spl.c @@ -0,0 +1,75 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig new file mode 100644 index 00000000000..238d44d1f58 --- /dev/null +++ b/configs/imx8qm_mek_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h new file mode 100644 index 00000000000..02c5d1c0547 --- /dev/null +++ b/include/configs/imx8qm_mek.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QM_MEK_H +#define __IMX8QM_MEK_H + +#include +#include + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8qxp-mek.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __IMX8QM_MEK_H */ -- cgit v1.3.1 From ce30382b4954c26d7c14b4a56d7f6dd94f7b5025 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 9 Apr 2019 17:24:10 +0200 Subject: apalis/colibri_imx6/imx6ull: make sure loadaddr does not collide Currently $loadaddr and $fdt_addr_r point to the same address. This might be not ideal for some distro boot scripts which make use of $loadaddr after loading the device tree. Make sure the two variables point to two different addresses. Moving $loadaddr is not entirly trivial since it is defined in mx6_common.h. Move $fdt_addr_r and $ramdisk_addr_r by 1MiB, which should be enough for scripts. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk --- include/configs/apalis_imx6.h | 4 ++-- include/configs/colibri-imx6ull.h | 4 ++-- include/configs/colibri_imx6.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include/configs') diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 96169f55f08..91054d8c05b 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -138,12 +138,12 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ - "fdt_addr_r=0x12000000\0" \ + "fdt_addr_r=0x12100000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ "pxefile_addr_r=0x17100000\0" \ - "ramdisk_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12200000\0" \ "scriptaddr=0x17000000\0" #define NFS_BOOTCMD \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 7cf550cf9eb..31248b14a10 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -48,12 +48,12 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x82000000\0" \ + "fdt_addr_r=0x82100000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x81000000\0" \ "pxefile_addr_r=0x87100000\0" \ - "ramdisk_addr_r=0x82100000\0" \ + "ramdisk_addr_r=0x82200000\0" \ "scriptaddr=0x87000000\0" #define NFS_BOOTCMD \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 803c9be0646..fecea95d32b 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -128,12 +128,12 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x12000000\0" \ + "fdt_addr_r=0x12100000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ "pxefile_addr_r=0x17100000\0" \ - "ramdisk_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12200000\0" \ "scriptaddr=0x17000000\0" #define NFS_BOOTCMD \ -- cgit v1.3.1 From 535800d33f41b25a265945d12280ef20038a6aaa Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 9 Apr 2019 17:24:15 +0200 Subject: colibri-imx6ull: migrate mmc to using driver model Migrate MMC to using driver model. Migrate USDHC to using pinctrl. While at it also add GPIO1_IO03__OSC32K_32K_OUT pin muxing. While at it also update copyright period. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk --- arch/arm/dts/imx6ull-colibri.dts | 15 +++++- board/toradex/colibri-imx6ull/colibri-imx6ull.c | 70 ------------------------- configs/colibri-imx6ull_defconfig | 1 + include/configs/colibri-imx6ull.h | 6 +-- 4 files changed, 17 insertions(+), 75 deletions(-) (limited to 'include/configs') diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts index 95c67be4382..0d416ebd10a 100644 --- a/arch/arm/dts/imx6ull-colibri.dts +++ b/arch/arm/dts/imx6ull-colibri.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2018 Toradex AG + * Copyright 2018-2019 Toradex AG */ /dts-v1/; @@ -11,6 +11,10 @@ model = "Toradex Colibri iMX6ULL"; compatible = "toradex,imx6ull-colibri", "fsl,imx6ull"; + aliases { + mmc0 = &usdhc1; + }; + chosen { stdout-path = &uart1; }; @@ -190,10 +194,18 @@ dr_mode = "host"; }; +/* Colibri MMC */ &usdhc1 { assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; }; &iomuxc { @@ -547,4 +559,3 @@ >; }; }; - diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 8493b1dfddb..c9af44e30e5 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -18,11 +18,9 @@ #include #include #include -#include #include #include #include -#include #include #include #include @@ -34,10 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ PAD_CTL_DSE_48ohm) @@ -56,19 +50,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - static iomux_v3_cfg_t const usb_cdet_pads[] = { MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -135,57 +116,6 @@ static int setup_lcd(void) } #endif -#ifdef CONFIG_FSL_ESDHC - -#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) - -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* USDHC1 is mmc0 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_FEC_MXC static int setup_fec(void) { diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index ce2c09338d2..69305323f21 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -50,6 +50,7 @@ CONFIG_DFU_NAND=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_NAND=y diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 31248b14a10..7a7a70e4570 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 Toradex AG + * Copyright 2018-2019 Toradex AG * * Configuration settings for the Colibri iMX6ULL module. * @@ -30,7 +30,7 @@ /* ENET1 */ #define IMX_FEC_BASE ENET2_BASE_ADDR -/* MMC Config*/ +/* MMC Config */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 1 @@ -182,4 +182,4 @@ #define CONFIG_VIDEO_BMP_LOGO #endif -#endif +#endif /* __COLIBRI_IMX6ULL_CONFIG_H */ -- cgit v1.3.1 From 5d67b73c1a58b6337e5681a68a7193e5c2f8718b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 9 Apr 2019 17:24:17 +0200 Subject: colibri-imx6ull: migrate fec to using driver model Migrate Ethernet FEC to using driver model. Drop PHY_MICREL_KSZ90X1 which slipped in from Apalis iMX6. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk --- arch/arm/dts/imx6ull-colibri.dts | 31 ++++++++++++++++--------------- configs/colibri-imx6ull_defconfig | 3 +-- include/configs/colibri-imx6ull.h | 4 ---- 3 files changed, 17 insertions(+), 21 deletions(-) (limited to 'include/configs') diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts index 91e48aab612..2f8865c29cc 100644 --- a/arch/arm/dts/imx6ull-colibri.dts +++ b/arch/arm/dts/imx6ull-colibri.dts @@ -80,6 +80,7 @@ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; }; +/* Ethernet */ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; @@ -233,6 +234,21 @@ }; &iomuxc { + pinctrl_enet2: enet2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + pinctrl_gpio1: gpio1-grp { fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ @@ -295,21 +311,6 @@ >; }; - pinctrl_enet2: enet2-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - >; - }; - pinctrl_ecspi1_cs: ecspi1-cs-grp { fsl,pins = < MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 0440b4ed94c..a24c87f3216 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -58,9 +58,8 @@ CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 7a7a70e4570..fc39e807b6a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -19,10 +19,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) /* Network */ -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - #define CONFIG_IP_DEFRAG #define CONFIG_TFTP_BLOCKSIZE 16352 #define CONFIG_TFTP_TSIZE -- cgit v1.3.1 From ef679d6ef52b5fe49d3f34ef25a491391b9aa764 Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Thu, 4 Apr 2019 14:00:56 +0200 Subject: pico-imx7d: Increase u-boot size for dfu request After DM conversion, the size of U-Boot binary to increase. Previous size is 480K after DM Conversion the new size is 557K So it's necessary to increase the dfu request for store u-boot-dtb.img in eMMC. Signed-off-by: Joris Offouga --- include/configs/pico-imx7d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 0f6d6b78945..04d316f1132 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -46,7 +46,7 @@ #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ - "u-boot raw 0x8a 0x400;" \ + "u-boot raw 0x8a 0x1000;" \ "/boot/zImage ext4 0 1;" \ "/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \ "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ -- cgit v1.3.1 From d776b07dc770c8b5078ddfe5984add1706c5073e Mon Sep 17 00:00:00 2001 From: Pierre-Jean Texier Date: Fri, 12 Apr 2019 22:36:36 +0200 Subject: warp7: Fix dfu_alt_info setting after DM conversion After DM conversion, U-Boot is larger than 512 KiB, so we need to increase the "size" of the dfu_alt_info setting. Signed-off-by: Pierre-Jean Texier Acked-by: Joris Offouga Reviewed-by: Fabio Estevam --- include/configs/warp7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 043f2861b62..4947597b405 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -39,7 +39,7 @@ #define CONFIG_SERIAL_TAG #define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ + "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_DFU_ENV_SETTINGS \ -- cgit v1.3.1 From 3b9ac5415084eadbd34a9d4d94e23d9935e73bd4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 15 Apr 2019 12:00:50 +0000 Subject: imx: 8qxp_mek: fix fdt_file and console Fix fdt_file and console to boot upstream Linux Kernel. Upstream linux use imx8qxp-mek.dtb, and pass lpuart32 to earlycon will not work for i.MX8QXP, only need to pass earlycon, check drivers/tty/serial/earlycon.c, " /* Just 'earlycon' is a valid param for devicetree and ACPI SPCR. */ " Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam --- include/configs/imx8qxp_mek.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 1cff18e05e9..5c83505ff02 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -65,11 +65,11 @@ "script=boot.scr\0" \ "image=Image\0" \ "panel=NULL\0" \ - "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "console=ttyLP0,${baudrate} earlycon\0" \ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=fsl-imx8qxp-mek.dtb\0" \ + "fdt_file=imx8qxp-mek.dtb\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ -- cgit v1.3.1 From d8d33b6d4dd2ecd2ea2a3d3ece9e22528d8fd15c Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Thu, 18 Apr 2019 00:04:09 +0200 Subject: imx: Add variscite DART-6UL Evaluation Kit Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-dart-6ul.dts | 39 ++++++ arch/arm/dts/imx6ull-dart-6ul.dtsi | 261 +++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 12 ++ board/variscite/dart_6ul/Kconfig | 12 ++ board/variscite/dart_6ul/MAINTAINERS | 8 ++ board/variscite/dart_6ul/Makefile | 4 + board/variscite/dart_6ul/README | 41 ++++++ board/variscite/dart_6ul/dart_6ul.c | 228 ++++++++++++++++++++++++++++++ board/variscite/dart_6ul/spl.c | 215 +++++++++++++++++++++++++++++ configs/variscite_dart6ul_defconfig | 55 ++++++++ include/configs/dart_6ul.h | 131 ++++++++++++++++++ 13 files changed, 1008 insertions(+) create mode 100644 arch/arm/dts/imx6ull-dart-6ul.dts create mode 100644 arch/arm/dts/imx6ull-dart-6ul.dtsi create mode 100644 board/variscite/dart_6ul/Kconfig create mode 100644 board/variscite/dart_6ul/MAINTAINERS create mode 100644 board/variscite/dart_6ul/Makefile create mode 100644 board/variscite/dart_6ul/README create mode 100644 board/variscite/dart_6ul/dart_6ul.c create mode 100644 board/variscite/dart_6ul/spl.c create mode 100644 configs/variscite_dart6ul_defconfig create mode 100644 include/configs/dart_6ul.h (limited to 'include/configs') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f58f8fb2359..0fa1f46129d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1637,6 +1637,7 @@ source "board/tcl/sl50/Kconfig" source "board/ucRobotics/bubblegum_96/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" +source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/xilinx/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e1bf714980d..08ae3aa46d5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -549,6 +549,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ + imx6ull-dart-6ul.dtb dtb-$(CONFIG_ARCH_MX6) += \ imx6-colibri.dtb diff --git a/arch/arm/dts/imx6ull-dart-6ul.dts b/arch/arm/dts/imx6ull-dart-6ul.dts new file mode 100644 index 00000000000..4cab1a048b8 --- /dev/null +++ b/arch/arm/dts/imx6ull-dart-6ul.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Parthiban Nallathambi + */ + +/dts-v1/; + +#include "imx6ull.dtsi" +#include "imx6ull-dart-6ul.dtsi" + +/ { + model = "Variscite DART-6UL Evaluation Kit"; + compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + +}; diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi new file mode 100644 index 00000000000..e96669f493b --- /dev/null +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Parthiban Nallathambi + */ + +/ { + model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM"; + compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull"; + + memory { + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio1: mdio1 { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio2: mdio2 { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "uboot-env"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; + + eeprom@50 { + compatible = "cat,24c32"; + reg = <0x50>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + bus-width = <0x4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0X1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index e782859b1e6..f513c4c06f7 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -161,6 +161,18 @@ config TARGET_COLIBRI_IMX6ULL select DM_THERMAL select MX6ULL +config TARGET_DART_6UL + bool "Variscite imx6ULL dart(DART-SOM-6ULL)" + select MX6ULL + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_DHCOMIMX6 bool "dh_imx6" select BOARD_EARLY_INIT_F diff --git a/board/variscite/dart_6ul/Kconfig b/board/variscite/dart_6ul/Kconfig new file mode 100644 index 00000000000..1765af1d828 --- /dev/null +++ b/board/variscite/dart_6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DART_6UL + +config SYS_BOARD + default "dart_6ul" + +config SYS_VENDOR + default "variscite" + +config SYS_CONFIG_NAME + default "dart_6ul" + +endif diff --git a/board/variscite/dart_6ul/MAINTAINERS b/board/variscite/dart_6ul/MAINTAINERS new file mode 100644 index 00000000000..339f93fa66f --- /dev/null +++ b/board/variscite/dart_6ul/MAINTAINERS @@ -0,0 +1,8 @@ +MX6UL_DART BOARD +M: Parthiban Nallathambi +S: Maintained +F: arch/arm/dts/imx6ull-dart-6ul.dts +F: arch/arm/dts/imx6ull-dart-6ul.dtsi +F: board/variscite/dart_6ul/ +F: configs/variscite_dart6ul_defconfig +F: include/configs/dart_6ul.h diff --git a/board/variscite/dart_6ul/Makefile b/board/variscite/dart_6ul/Makefile new file mode 100644 index 00000000000..48aa361bf2d --- /dev/null +++ b/board/variscite/dart_6ul/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := dart_6ul.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/variscite/dart_6ul/README b/board/variscite/dart_6ul/README new file mode 100644 index 00000000000..d76b997e228 --- /dev/null +++ b/board/variscite/dart_6ul/README @@ -0,0 +1,41 @@ +How to use U-Boot on variscite DART-6UL Evaluation Kit +------------------------------------------------------ + +- Configure and build U-Boot for DART-6UL iMX6ULL: + + $ make mrproper + $ make variscite_dart6ul_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 0 + +Boot from eMMC: +- if bootpart is not enabled by default, to enable under Linux + echo 0 >/sys/block/mmcblk1boot0/force_ro + mmc bootpart enable 1 1 /dev/mmcblk1boot0 + +- Flash the SPL and u-boot-dtb.img to mmcblk1boot0 + $ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Insert the micro SD card in the board and power it up. + +- U-Boot messages should come up. diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c new file mode 100644 index 00000000000..4765595af10 --- /dev/null +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2019 Variscite Ltd. + * Copyright (C) 2019 Parthiban Nallathambi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_NAND_MXS +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_ODE) +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, + ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, + ARRAY_SIZE(fec2_pads)); +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + +#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER) + /* USB Ethernet Gadget */ + usb_eth_initialize(bis); +#endif + return ret; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: Variscite DART-6UL Evaluation Kit\n"); + + return 0; +} diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c new file mode 100644 index 00000000000..f7e6ab63257 --- /dev/null +++ b/board/variscite/dart_6ul/spl.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2019 Variscite Ltd. + * Copyright (C) 2019 Parthiban Nallathambi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x414C0158, + .p0_mprddlctl = 0x40403A3A, + .p0_mpwrdlctl = 0x40405A56, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); + /* Enable Audio Clock for SOM codec */ + writel(0x01130100, (long *)CCM_CCOSR); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* setup GP timer */ + timer_init(); + + setup_iomux_uart(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig new file mode 100644 index 00000000000..a1cdd056191 --- /dev/null +++ b/configs/variscite_dart6ul_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x86000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_DART_6UL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul" +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Variscite" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_LZO=y diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h new file mode 100644 index 00000000000..fb1b899d712 --- /dev/null +++ b/include/configs/dart_6ul.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Variscite DART-6UL Evaluation Kit + * Copyright (C) 2019 Parthiban Nallathambi + */ +#ifndef __DART_6UL_H +#define __DART_6UL_H + +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x3 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth1" +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Environment settings */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + +/* Environment in SD */ +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define MMC_ROOTFS_DEV 0 +#define MMC_ROOTFS_PART 2 + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#define ENV_MMC \ + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ + "fitpart=1\0" \ + "bootdelay=3\0" \ + "silent=1\0" \ + "optargs=rw rootwait\0" \ + "mmcautodetect=yes\0" \ + "mmcrootfstype=ext4\0" \ + "mmcfit_name=fitImage\0" \ + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \ + "${mmcfit_name}\0" \ + "mmcargs=setenv bootargs " \ + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \ + "console=${console} rootfstype=${mmcrootfstype}\0" \ + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0,115200n8\0" \ + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "fit_addr=0x82000000\0" \ + ENV_MMC + +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include +#endif /* __DART_6UL_H */ -- cgit v1.3.1 From 0710726d047f559b17a64d8cce860639c635adfd Mon Sep 17 00:00:00 2001 From: Pierre-Jean Texier Date: Fri, 19 Apr 2019 20:34:11 +0200 Subject: warp7: Switch to DM Serial This commit switches to DM SERIAL for warp7 and warp7_bl33 defconfigs. Signed-off-by: Pierre-Jean Texier Signed-off-by: Joris Offouga Reviewed-by: Fabio Estevam --- arch/arm/dts/imx7s-warp.dts | 4 ++++ configs/warp7_bl33_defconfig | 2 ++ configs/warp7_defconfig | 2 ++ include/configs/warp7.h | 2 -- 4 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts index d28b7ec7155..4d87348f643 100644 --- a/arch/arm/dts/imx7s-warp.dts +++ b/arch/arm/dts/imx7s-warp.dts @@ -21,6 +21,10 @@ mmc0 = &usdhc3; }; + chosen { + stdout-path = &uart1; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&pinctrl_gpio>; diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 6eaf152bace..d34f76b3e83 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -38,6 +38,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 28aa06fa595..ae424ab7a0b 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -47,6 +47,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_OPTEE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 4947597b405..37649cf2c5f 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -24,8 +24,6 @@ #endif #endif -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) -- cgit v1.3.1 From 0d3912fcd41dc2a85891f78e8fc255a379323619 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 15 Apr 2019 11:01:57 +0200 Subject: colibri_imx6: use UUID for rootfs 1. Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs partition. This fixes the issue, when MMC controllers are probed in a different order in U-boot and Linux kernel. 2. Fix legacy USB command (both sdboot and usbboot can be used now). Tested-by: Marcel Ziswiler Signed-off-by: Igor Opaniuk --- configs/colibri_imx6_defconfig | 1 + include/configs/colibri_imx6.h | 58 ++++++++++++++++++++++++++++-------------- 2 files changed, 40 insertions(+), 19 deletions(-) (limited to 'include/configs') diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index bf05c688072..083588e02d2 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_UUID=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index fecea95d32b..129a42466d4 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -115,16 +115,22 @@ "imx6dl-colibri-cam-eval-v3.dtb fat 0 1" #define EMMC_BOOTCMD \ - "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \ + "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\ + "rw,noatime rootfstype=ext4 " \ "rootwait\0" \ - "emmcboot=run setup; " \ + "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ + "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \ + "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + "emmcbootpart=1\0" \ + "emmcdev=0\0" \ + "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ + "${fdt_addr_r} ${fdt_file} && " \ + "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \ + "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ + "emmcrootpart=2\0" #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ @@ -147,27 +153,40 @@ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define SD_BOOTCMD \ - "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \ - "rootwait\0" \ - "sdboot=run setup; " \ + "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \ + "rootfstype=ext4 rootwait\0" \ + "sdboot=run setup; run sdfinduuid; run set_sdargs; " \ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ "${vidargs}; echo Booting from SD card; " \ - "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ + "run sddtbload; load mmc ${sddev}:${sdbootpart} "\ + "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + "sdbootpart=1\0" \ + "sddev=1\0" \ + "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \ + "${fdt_addr_r} ${fdt_file} && setenv dtbparam \" - " \ + "${fdt_addr_r}\" && true\0" \ + "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ + "sdrootpart=2\0" #define USB_BOOTCMD \ - "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \ - "rootwait\0" \ - "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ + "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \ + "rootfstype=ext4 rootwait\0" \ + "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \ + "setenv bootargs ${defargs} ${setupargs} " \ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ - "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ + "run usbdtbload; " \ + "load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + "usbbootpart=1\0" \ + "usbdev=0\0" \ + "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \ + "${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && " \ + "true\0" \ + "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \ + "usbrootpart=2\0" #define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -186,6 +205,7 @@ MEM_LAYOUT_ENV_SETTINGS \ NFS_BOOTCMD \ SD_BOOTCMD \ + USB_BOOTCMD \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ -- cgit v1.3.1