From 6899b04cc54151a0fe40b6dc1d896e654b6cf11c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 28 Sep 2018 11:22:36 -0300 Subject: pico-imx6ul, pico-imx7d: Use eMMC user partition by default After discussing with TechNexion about how its default setting, it is better to install on the eMMC user partition by default, when using DFU, so it works out of box for majority of users. Reviewed-by: Fabio Estevam Signed-off-by: Otavio Salvador --- include/configs/pico-imx6ul.h | 4 ++-- include/configs/pico-imx7d.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 3d932055354..0fea2d65ddc 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -56,8 +56,8 @@ #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ - "spl raw 0x2 0x400 mmcpart 1;" \ - "u-boot raw 0x8a 0x400 mmcpart 1;" \ + "spl raw 0x2 0x400;" \ + "u-boot raw 0x8a 0x400;" \ "/boot/zImage ext4 0 1;" \ "/boot/imx6ul-pico-hobbit.dtb ext4 0 1;" \ "/boot/imx6ul-pico-pi.dtb ext4 0 1;" \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 0e770bf41f2..614be99d93b 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -45,8 +45,8 @@ #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ - "spl raw 0x2 0x400 mmcpart 1;" \ - "u-boot raw 0x8a 0x400 mmcpart 1;" \ + "spl raw 0x2 0x400;" \ + "u-boot raw 0x8a 0x400;" \ "/boot/zImage ext4 0 1;" \ "/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \ "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ -- cgit v1.3.1 From c066d3cbf1ce0ef4fc42c58e9709259a702dbfe0 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 28 Sep 2018 11:22:37 -0300 Subject: pico-imx6ul, pico-imx7d: Enable USB and PXE boot support This allow the use of a USB storage or PXE network booting as fallback, allowing for example for manufacturing installation of eMMC storage in an easy way. Reviewed-by: Fabio Estevam Signed-off-by: Otavio Salvador --- include/configs/pico-imx6ul.h | 2 ++ include/configs/pico-imx7d.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include/configs') diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 0fea2d65ddc..8082b74c9c5 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -103,6 +103,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 614be99d93b..2bc42a04a04 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -92,6 +92,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include -- cgit v1.3.1 From 787075e0692e36e793fa8a453a1b2dfc98def711 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Sep 2018 13:01:56 +0200 Subject: colibri_imx7: prime get_ram_size() using imx_ddr_size() Rather than passing a hardcoded maxsize to the generic get_ram_size() function use the i.MX 7 specific imx_ddr_size() function, which extracts the memory size at runtime by reading the DDR controller registers. This is a purely cosmetic change as the generic get_ram_size() function already took care of properly automatically detecting 256MB, 512MB or 1GB modules. Signed-off-by: Fabio Estevam Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam Acked-by: Stefan Agner --- board/toradex/colibri_imx7/colibri_imx7.c | 2 +- include/configs/colibri_imx7.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include/configs') diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 2b7591eb001..a4c99626b4f 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size()); return 0; } diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index ff6bd678cfa..02849ba35ff 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -14,7 +14,6 @@ #include "mx7_common.h" /*#define CONFIG_DBG_MONITOR*/ -#define PHYS_SDRAM_SIZE SZ_1G /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -- cgit v1.3.1 From be381cc4346c1d18a0624c93192ec9fe083522db Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 17 Sep 2018 14:16:14 -0300 Subject: configs: mx7: Remove CONFIG_DBG_MONITOR Remove all CONFIG_DBG_MONITOR references as it is not used anywhere. Signed-off-by: Fabio Estevam --- include/configs/cl-som-imx7.h | 2 -- include/configs/colibri-imx6ull.h | 1 - include/configs/colibri_imx7.h | 2 -- include/configs/mx7dsabresd.h | 1 - scripts/config_whitelist.txt | 1 - 5 files changed, 7 deletions(-) (limited to 'include/configs') diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 1b2eee3f18a..f84a11215e4 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -10,8 +10,6 @@ #include "mx7_common.h" -#define CONFIG_DBG_MONITOR - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Size of malloc() pool */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index f2db0394549..7cf550cf9eb 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -13,7 +13,6 @@ #include "mx6_common.h" #define CONFIG_IOMUX_LPSR -/* #define CONFIG_DBG_MONITOR*/ #define PHYS_SDRAM_SIZE SZ_512M /* Size of malloc() pool */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 02849ba35ff..c31cf2888a7 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -13,8 +13,6 @@ #include "mx7_common.h" -/*#define CONFIG_DBG_MONITOR*/ - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 87241ef4bfd..ad919a671fa 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -10,7 +10,6 @@ #include "mx7_common.h" -#define CONFIG_DBG_MONITOR #define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e805b1e6b36..5ca650ad5bc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -310,7 +310,6 @@ CONFIG_D2NET_V2 CONFIG_DA850_AM18X_EVM CONFIG_DA850_EVM_MAX_CPU_CLK CONFIG_DBGU -CONFIG_DBG_MONITOR CONFIG_DB_784MP_GP CONFIG_DCACHE CONFIG_DCACHE_OFF -- cgit v1.3.1 From 39cb4f3c25a1cafbe867d0951d2d54b475a68990 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 4 Oct 2018 21:24:14 +0200 Subject: arm: mx5: Add M53Menlo board Add Menlosystems M53 board, based on the M53 SoM. This board has Ethernet, USB host, USB gadget, UART and LCD on it. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/mach-imx/mx5/Kconfig | 6 + board/menlo/m53menlo/Kconfig | 15 ++ board/menlo/m53menlo/MAINTAINERS | 7 + board/menlo/m53menlo/Makefile | 9 + board/menlo/m53menlo/imximage.cfg | 91 +++++++ board/menlo/m53menlo/m53menlo.c | 513 ++++++++++++++++++++++++++++++++++++++ configs/m53menlo_defconfig | 60 +++++ include/configs/m53menlo.h | 246 ++++++++++++++++++ 8 files changed, 947 insertions(+) create mode 100644 board/menlo/m53menlo/Kconfig create mode 100644 board/menlo/m53menlo/MAINTAINERS create mode 100644 board/menlo/m53menlo/Makefile create mode 100644 board/menlo/m53menlo/imximage.cfg create mode 100644 board/menlo/m53menlo/m53menlo.c create mode 100644 configs/m53menlo_defconfig create mode 100644 include/configs/m53menlo.h (limited to 'include/configs') diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 051b15dbff1..29051c40f32 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -30,6 +30,11 @@ config TARGET_KP_IMX53 select MX53 imply CMD_DM +config TARGET_M53MENLO + bool "Support m53menlo" + select MX53 + select SUPPORT_SPL + config TARGET_MX51EVK bool "Support mx51evk" select BOARD_LATE_INIT @@ -89,6 +94,7 @@ source "board/freescale/mx53smd/Kconfig" source "board/ge/mx53ppd/Kconfig" source "board/inversepath/usbarmory/Kconfig" source "board/k+p/kp_imx53/Kconfig" +source "board/menlo/m53menlo/Kconfig" source "board/technologic/ts4800/Kconfig" endif diff --git a/board/menlo/m53menlo/Kconfig b/board/menlo/m53menlo/Kconfig new file mode 100644 index 00000000000..1953f5041b8 --- /dev/null +++ b/board/menlo/m53menlo/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M53MENLO + +config SYS_BOARD + default "m53menlo" + +config SYS_VENDOR + default "menlo" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "m53menlo" + +endif diff --git a/board/menlo/m53menlo/MAINTAINERS b/board/menlo/m53menlo/MAINTAINERS new file mode 100644 index 00000000000..7b783400607 --- /dev/null +++ b/board/menlo/m53menlo/MAINTAINERS @@ -0,0 +1,7 @@ +M53MENLO BOARD +M: Marek Vasut +M: Olaf Mandel +S: Maintained +F: board/menlo/m53menlo/ +F: include/configs/m53menlo.h +F: configs/m53menlo_defconfig diff --git a/board/menlo/m53menlo/Makefile b/board/menlo/m53menlo/Makefile new file mode 100644 index 00000000000..b4ab95a568b --- /dev/null +++ b/board/menlo/m53menlo/Makefile @@ -0,0 +1,9 @@ +# +# Menlosystems M53Menlo +# Copyright (C) 2012-2017 Marek Vasut +# Copyright (C) 2014-2017 Olaf Mandel +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := m53menlo.o diff --git a/board/menlo/m53menlo/imximage.cfg b/board/menlo/m53menlo/imximage.cfg new file mode 100644 index 00000000000..68b3eb5c1c3 --- /dev/null +++ b/board/menlo/m53menlo/imximage.cfg @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * M53 DRAM init values + * Copyright (C) 2012-2013 Marek Vasut + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include + +/* image version */ +IMAGE_VERSION 2 + + +/* Boot Offset 0x400, valid for both SD and NAND boot. */ +BOOT_OFFSET FLASH_OFFSET_STANDARD + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ + +DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ + +DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ + +DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ + +DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ + +DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ + +DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ + +DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ + +/* ESDCTL */ +DATA 4 0x63fd9088 0x32383535 +DATA 4 0x63fd9090 0x40383538 +DATA 4 0x63fd907c 0x0136014d +DATA 4 0x63fd9080 0x01510141 + +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x555952e3 +DATA 4 0x63fd9010 0xb68e8b63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c new file mode 100644 index 00000000000..6bdd6d5b234 --- /dev/null +++ b/board/menlo/m53menlo/m53menlo.c @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Menlosystems M53Menlo board + * + * Copyright (C) 2012-2017 Marek Vasut + * Copyright (C) 2014-2017 Olaf Mandel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static u32 mx53_dram_size[2]; + +ulong board_get_usable_ram_top(ulong total_size) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return PHYS_SDRAM_2 + mx53_dram_size[1]; +} + +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; + + return 0; +} + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart_pads[] = { + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + if (port == 0) { + /* USB OTG PWRON */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, + PAD_CTL_PKE | + PAD_CTL_DSE_HIGH)); + gpio_direction_output(IMX_GPIO_NR(1, 4), 0); + + /* USB OTG Over Current */ + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); + } else if (port == 1) { + /* USB Host PWRON */ + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, + PAD_CTL_PKE | + PAD_CTL_DSE_HIGH)); + gpio_direction_output(IMX_GPIO_NR(1, 2), 0); + + /* USB Host Over Current */ + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); + } + + return 0; +} +#endif + +static void setup_iomux_fec(void) +{ + static const iomux_v3_cfg_t fec_pads[] = { + /* MDIO pads */ + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + + /* FEC 0 pads */ + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + + /* FEC 1 pads */ + NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = { + MMC_SDHC1_BASE_ADDR, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); + gpio_direction_input(IMX_GPIO_NR(1, 1)); + + return !gpio_get_value(IMX_GPIO_NR(1, 1)); +} + +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + }; + + esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} +#endif + +#ifdef CONFIG_VIDEO +static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) +{ + static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + int ret; + + /* For ETM0430G0DH6 model, this must be enabled before the clock. */ + gpio_direction_output(IMX_GPIO_NR(6, 0), 1); + + /* + * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to + * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . + */ + ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK); + if (ret) + puts("IPU: Failed to configure LDB clock\n"); + + /* Configure CCM_CSCMR2 */ + clrsetbits_le32(&mxc_ccm->cscmr2, + (0x7 << 26) | BIT(10) | BIT(8), + (0x5 << 26) | BIT(10) | BIT(8)); + + /* Configure LDB_CTRL */ + writel(0x201, 0x53fa8008); +} + +static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev) +{ + /* For ETM0430G0DH6 model, this must be enabled before the clock. */ + gpio_direction_output(IMX_GPIO_NR(6, 0), 1); + + /* + * Set LVDS clock to 9 MHz for the display. The PLL4 is set to + * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . + */ + enable_lvds_clock(dev, 63); +} + +static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev) +{ + /* + * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to + * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . + */ + enable_lvds_clock(dev, 233); + + /* For ETM0700G0DH6 model, this may be enabled after the clock. */ + gpio_direction_output(IMX_GPIO_NR(6, 0), 1); +} + +static const char *lvds_compat_string; + +static int detect_lvds(struct display_info_t const *dev) +{ + u8 touchid[23]; + u8 *touchptr = &touchid[0]; + int ret; + + ret = i2c_set_bus_num(0); + if (ret) + return 0; + + /* Touchscreen is at address 0x38, ID register is 0xbb. */ + ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid)); + if (ret) + return 0; + + /* EP0430 prefixes the response with 0xbb, skip it. */ + if (*touchptr == 0xbb) + touchptr++; + + /* Skip the 'EP' prefix. */ + touchptr += 2; + + ret = !memcmp(touchptr, &dev->mode.name[7], 4); + if (ret) + lvds_compat_string = dev->mode.name; + + return ret; +} + +void board_preboot_os(void) +{ + /* Power off the LCD to prevent awful color flicker */ + gpio_direction_output(IMX_GPIO_NR(6, 0), 0); +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + if (lvds_compat_string) + do_fixup_by_path_string(blob, "/panel", "compatible", + lvds_compat_string); + + return 0; +} + +struct display_info_t const displays[] = { + { + .bus = 0, + .addr = 0, + .detect = detect_lvds, + .enable = enable_lvds_etm0430g0dh6, + .pixfmt = IPU_PIX_FMT_RGB666, + .mode = { + .name = "edt,etm0430g0dh6", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 111111, /* picosecond (9 MHz) */ + .left_margin = 2, + .right_margin = 2, + .upper_margin = 2, + .lower_margin = 2, + .hsync_len = 41, + .vsync_len = 10, + .sync = 0x40000000, + .vmode = FB_VMODE_NONINTERLACED + } + }, { + .bus = 0, + .addr = 0, + .detect = detect_lvds, + .enable = enable_lvds_etm0700g0dh6, + .pixfmt = IPU_PIX_FMT_RGB666, + .mode = { + .name = "edt,etm0700g0dh6", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30048, /* picosecond (33.28 MHz) */ + .left_margin = 40, + .right_margin = 88, + .upper_margin = 10, + .lower_margin = 33, + .hsync_len = 128, + .vsync_len = 2, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; + +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location default_splash_locations[] = { + { + .name = "mmc_fs", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:1", + }, +}; + +int splash_screen_prepare(void) +{ + return splash_source_load(default_splash_locations, + ARRAY_SIZE(default_splash_locations)); +} +#endif + +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t i2c_pads[] = { + /* I2C1 */ + NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL), + /* I2C2 */ + NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); +} + +static void setup_iomux_video(void) +{ + static const iomux_v3_cfg_t lcd_pads[] = { + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, + }; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); +} + +static void setup_iomux_nand(void) +{ + static const iomux_v3_cfg_t nand_pads[] = { + NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, + PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, + PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, + PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); +} + +static void m53_set_clock(void) +{ + int ret; + const u32 ref_clk = MXC_HCLK; + const u32 dramclk = 400; + u32 cpuclk; + + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, + PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ + cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; + + ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); + if (ret) { + printf("CPU: Switch peripheral clock to %dMHz failed\n", + dramclk); + } + + ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); +} + +static void m53_set_nand(void) +{ + u32 i; + + /* NAND flash is muxed on ATA pins */ + setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); + + /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ + for (i = 0x4; i < 0x94; i += 0x18) { + clrbits_le32(WEIM_BASE_ADDR + i, + WEIM_GCR2_MUX16_BYP_GRANT_MASK); + } + + mxc_set_clock(0, 33, MXC_NFC_CLK); + enable_nfc_clk(1); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + setup_iomux_i2c(); + setup_iomux_nand(); + setup_iomux_video(); + + m53_set_clock(); + + mxc_set_sata_internal_clock(); + + /* NAND clock @ 33MHz */ + m53_set_nand(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Menlosystems M53Menlo\n"); + + return 0; +} + +/* + * NAND SPL + */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + setup_iomux_nand(); + m53_set_clock(); + m53_set_nand(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} +#endif diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig new file mode 100644 index 00000000000..f59f4acabb0 --- /dev/null +++ b/configs/m53menlo_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX5=y +CONFIG_SYS_TEXT_BASE=0x71000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_M53MENLO=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +# CONFIG_CMD_BMODE is not set +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttymxc0,115200" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_DATE=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)" +CONFIG_CMD_UBI=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FSL_ESDHC=y +CONFIG_NAND=y +CONFIG_NAND_MXC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h new file mode 100644 index 00000000000..94214b135df --- /dev/null +++ b/include/configs/m53menlo.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Menlosystems M53Menlo configuration + * Copyright (C) 2012-2017 Marek Vasut + * Copyright (C) 2014-2017 Olaf Mandel + */ + +#ifndef __M53MENLO_CONFIG_H__ +#define __M53MENLO_CONFIG_H__ + +#include + +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x8ff00000 + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 +#endif + +/* + * NAND + */ +#define CONFIG_ENV_SIZE (16 * 1024) +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* Environment is in NAND */ +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */ +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#endif + +/* + * Ethernet on SOC (FEC) + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC0" +#endif + +/* + * I2C + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#endif + +/* + * SATA + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR +#define CONFIG_LBA48 +#endif + +/* + * LCD + */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASHIMAGE_GUARD +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* LVDS display */ +#define CONFIG_SYS_LDB_CLOCK 33260000 +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SPLASH_SOURCE + +/* IIM Fuses */ +#define CONFIG_FSL_IIM + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTFILE "boot/fitImage" +#define CONFIG_LOADADDR 0x70800000 +#define CONFIG_BOOTCOMMAND "run mmc_mmc" +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * NAND SPL + */ +#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" +#define CONFIG_SPL_TEXT_BASE 0x70008000 +#define CONFIG_SPL_PAD_TO 0x8000 +#define CONFIG_SPL_STACK 0x70004000 + +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +/* + * Extra Environments + */ +#define CONFIG_PREBOOT "run try_bootscript" +#define CONFIG_HOSTNAME "m53menlo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttymxc0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "rootpath=/srv/\0" \ + "kernel_addr_r=0x72000000\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "netdev=eth0\0" \ + "splashsource=mmc_fs\0" \ + "splashfile=usplash.bmp.gz\0" \ + "splashimage=0x88000000\0" \ + "splashpos=m,m\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc addmtd\0" \ + "mmcload=" \ + "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \ + "${kernel_addr_r} ${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \ + "rootwait\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:1 ${bootscript} ; then " \ + "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" + +#endif /* __M53MENLO_CONFIG_H__ */ -- cgit v1.3.1 From d0dd73974c613650cb0c3d32a734a954cedc9f8a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:37 +0200 Subject: imx: add i.MX8QXP MEK board support Add i.MX8QXP MEK board support Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246 ++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 13 ++ board/freescale/imx8qxp_mek/Kconfig | 14 ++ board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 +++++++++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 +++++++++++++++++++++ board/freescale/mx8mq_evk/README | 81 ++++++++++ configs/imx8qxp_mek_defconfig | 51 +++++++ include/configs/imx8qxp_mek.h | 157 +++++++++++++++++++ 11 files changed, 819 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/README create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 include/configs/imx8qxp_mek.h (limited to 'include/configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44ebc50bfab..61598bdfeb3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -452,6 +452,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ r8a7795-salvator-x.dtb \ diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts new file mode 100644 index 00000000000..09ea3b4a3af --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <3480>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_ioexp_rst: ioexp-rst-grp { + fsl,pins = < + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + status = "okay"; + + i2cswitch@71 { + compatible = "nxp,pca9646"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + + bb_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mfi_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2cexp1_i2c1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2cexp2_i2c1: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 28910c1509f..0d3a87cd744 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -10,4 +10,17 @@ config IMX8QXP config SYS_SOC default "imx8" +choice + prompt "i.MX8 board select" + optional + +config TARGET_IMX8QXP_MEK + bool "Support i.MX8QXP MEK board" + select BOARD_LATE_INIT + select IMX8QXP + +endchoice + +source "board/freescale/imx8qxp_mek/Kconfig" + endif diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig new file mode 100644 index 00000000000..b67300d816c --- /dev/null +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QXP_MEK + +config SYS_BOARD + default "imx8qxp_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qxp_mek/MAINTAINERS b/board/freescale/imx8qxp_mek/MAINTAINERS new file mode 100644 index 00000000000..e9bf0b35a34 --- /dev/null +++ b/board/freescale/imx8qxp_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QXP MEK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx8qxp_mek/ +F: include/configs/imx8qxp_mek.h +F: configs/imx8qxp_mek_defconfig diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile new file mode 100644 index 00000000000..f9ee8aeff36 --- /dev/null +++ b/board/freescale/imx8qxp_mek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_mek.o diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README new file mode 100644 index 00000000000..7f740894b20 --- /dev/null +++ b/board/freescale/imx8qxp_mek/README @@ -0,0 +1,72 @@ +U-Boot for the NXP i.MX8QXP EVK board + +Quick Start +=========== + +- Build U-Boot +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get mkimage tool +- Generate flash.bin using imx-mkimage +- Flash the binary into the SD card +- Boot + +Build U-Boot +============ + +$ make imx8qxp_mek_defconfig +$ make + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2 +$ make PLAT=imx8qxp bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-0.7.bin +$ chmod +x imx-sc-firmware-0.7.bin +$ ./imx-sc-firmware-0.7.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin +$ chmod +x firmware-imx-7.6.bin +$ ./firmware-imx-7.6.bin + +Get imx-mkimage tool +============================== +Download the imx-mkimage tool: + +$ git clone https://source.codeaurora.org/external/imx/imx-mkimage/ +$ cd imx-mkimage/ +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2 + + +Generate flash.bin using imx-mkimage +==================================== + +Copy the following binaries to imx-mkimage/iMX8M folder: + +$ cp imx-atf/build/imx8qxp/release/bl31.bin imx-mkimage/iMX8QX/ +$ cp u-boot/u-boot.bin imx-mkimage/iMX8QX/ + +Copy the following firmwares to imx-mkimage/iMX8 folder : + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img imx-mkimage/iMX8QX/ +$ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin imx-mkimage/iMX8QX/scfw_tcm.bin + +$ cd imx-mkimage/ +$ make SOC=iMX8QX flash + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=iMX8QX/flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch SW2: 1100. diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c new file mode 100644 index 00000000000..a4c587a3908 --- /dev/null +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + int ret; + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + /* Power up UART0 */ + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (ret) + return ret; + + /* Enable UART0 clock root */ + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + ret = dm_gpio_lookup_name("gpio@1a_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "bb_per_rst_b"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 when the build info is not supported*/ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Board: iMX8QXP MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QXP"); +#endif + + return 0; +} diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README new file mode 100644 index 00000000000..cd7e67eec5a --- /dev/null +++ b/board/freescale/mx8mq_evk/README @@ -0,0 +1,81 @@ +U-Boot for the NXP i.MX8MQ EVK board + +Quick Start +=========== + +- Build U-Boot +- Build the ARM Trusted firmware binary +- Get DDR firmware and mkimage tool +- Generate flash.bin using imx-mkimage +- Flash the binary into the SD card +- Boot + +Build U-Boot +============ + +$ make mx8mq_evk_defconfig +$ make + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.9.51_imx8m_beta +$ make PLAT=imx8mq bl31 + +Get the DDR firmware and mkimage tool +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin +$ chmod +x firmware-imx-7.2.bin +$ ./firmware-imx-7.2.bin + +Download the imx-mkimage tool: + +$ git clone https://source.codeaurora.org/external/imx/imx-mkimage/ +$ cd imx-mkimage/ +$ git checkout origin/imx_4.9.51_imx8m_beta + + +Generate flash.bin using imx-mkimage +==================================== + +Copy the following binaries to imx-mkimage/iMX8M folder: + +$ cp imx-atf/build/imx8mq/release/bl31.bin imx-mkimage/iMX8M/ +$ cp u-boot/u-boot-nodtb.bin imx-mkimage/iMX8M/ +$ cp u-boot/spl/u-boot-spl.bin imx-mkimage/iMX8M/ +$ cp u-boot/arch/arm/dts/fsl-imx8mq-evk.dtb imx-mkimage/iMX8M/ + +Copy the following firmwares to imx-mkimage/iMX8 folder : + +$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem.bin imx-mkimage/iMX8M/ +$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem.bin imx-mkimage/iMX8M/ +$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem.bin imx-mkimage/iMX8M/ +$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem.bin imx-mkimage/iMX8M/ + +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M. + +Before generating the flash.bin, transfer the mkimage generated by U-Boot to iMX8M folder: + +$ cp u-boot/tools/mkimage imx-mkimage/iMX8M/ +$ mv imx-mkimage/iMX8M/mkimage imx-mkimage/iMX8M/mkimage_uboot + +$ cd imx-mkimage/ +$ make SOC=iMX8M flash_spl_uboot + +Or for using HDMI: + +$ make SOC=iMX8M flash_hdmi_spl_uboot + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 33KB: + +$ sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==== +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig new file mode 100644 index 00000000000..73e9d93a8fd --- /dev/null +++ b/configs/imx8qxp_mek_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_BOOTDELAY=3 +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h new file mode 100644 index 00000000000..d34d174cac9 --- /dev/null +++ b/include/configs/imx8qxp_mek.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QXP_MEK_H +#define __IMX8QXP_MEK_H + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8qxp-mek.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __IMX8QXP_MEK_H */ -- cgit v1.3.1 From 517066a7094499712f7fc6f1d5c116427bdced08 Mon Sep 17 00:00:00 2001 From: Xiaoliang Yang Date: Thu, 18 Oct 2018 17:14:19 +0800 Subject: Kconfig: Convert CONFIG_IMX_WATCHDOG to Kconfig Move this option to Kconfig and tidy up the config file of eight boards which use it. Signed-off-by: Xiaoliang Yang --- configs/aristainetos2_defconfig | 1 + configs/aristainetos2b_defconfig | 1 + configs/aristainetos_defconfig | 1 + configs/dh_imx6_defconfig | 1 + configs/display5_defconfig | 1 + configs/display5_factory_defconfig | 1 + configs/ge_bx50v3_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/tqma6s_wru4_mmc_defconfig | 1 + configs/warp_defconfig | 1 + drivers/watchdog/Kconfig | 7 +++++++ include/configs/aristainetos-common.h | 3 --- include/configs/dh_imx6.h | 2 -- include/configs/display5.h | 2 -- include/configs/ge_bx50v3.h | 2 -- include/configs/kp_imx6q_tpc.h | 2 -- include/configs/mx53ppd.h | 2 -- include/configs/tqma6_wru4.h | 2 -- include/configs/warp.h | 2 -- scripts/config_whitelist.txt | 1 - 21 files changed, 18 insertions(+), 18 deletions(-) (limited to 'include/configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 5044a595fed..c55e39c9970 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -50,4 +50,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 66413824dab..95c30632c1c 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -50,4 +50,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index 6a31ee69c2e..4082b121cd3 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -49,4 +49,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 2cb716479fb..92b23778ef0 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -59,4 +59,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 697138eede3..ab5ec59343b 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -75,3 +75,4 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 5962b642b27..5d1c7462055 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -82,4 +82,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 729377d4381..c907779636a 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -41,5 +41,6 @@ CONFIG_CMD_E1000=y CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 84ca1ceb9bf..5ebbe1dc7c6 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -40,4 +40,5 @@ CONFIG_MII=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 7be5c041253..34328fd0162 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -37,4 +37,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index df4c87eea64..c1be7046477 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -65,4 +65,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 6a9c91e18ec..63eee273064 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -37,4 +37,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d545b3e0007..02f4e1e32fc 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -111,4 +111,11 @@ config XILINX_TB_WATCHDOG Select this to enable Xilinx Axi watchdog timer, which can be found on some Xilinx Microblaze Platforms. +config IMX_WATCHDOG + bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP" + select HW_WATCHDOG + help + Select this to enable the IMX and LSCH2 of Layerscape watchdog + driver. + endmenu diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index baddd1c330c..ca974c015f1 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -192,9 +192,6 @@ /* UBI support */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG - /* Framebuffer */ #define CONFIG_VIDEO_IPUV3 /* check this console not needed, after test remove it */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 6c833e7a27b..9231bd853f4 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -109,8 +109,6 @@ #endif /* Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 6d00699ebd0..1fb74691826 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -368,8 +368,6 @@ /* Commands */ /* Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000 /* ENV config */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index fad840b9b2b..e0e1f713efc 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -31,8 +31,6 @@ #define CONFIG_REVISION_TAG #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 #define CONFIG_MXC_UART diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 704383090f0..b6b27ee1d5e 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -67,8 +67,6 @@ #endif /* Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index bbd4cd78cd3..d2a8e6571af 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -22,8 +22,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index a945272595d..34f000f2145 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -17,8 +17,6 @@ #define CONSOLE_DEV "ttymxc3" /* Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 /* Config on-board RTC */ diff --git a/include/configs/warp.h b/include/configs/warp.h index f9c095dad3c..9aa8a48d3d8 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -26,8 +26,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */ #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5ca650ad5bc..fe82419d667 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -963,7 +963,6 @@ CONFIG_IMX_HDMI CONFIG_IMX_NAND CONFIG_IMX_OTP CONFIG_IMX_VIDEO_SKIP -CONFIG_IMX_WATCHDOG CONFIG_INETSPACE_V2 CONFIG_INITRD_TAG CONFIG_INIT_CRITICAL -- cgit v1.3.1 From a612e25e13d35656630440a191ddd851319737ff Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Wed, 5 Sep 2018 11:56:07 +0100 Subject: warp7: include: configs: set skip low level init If we have defined the OPTEE ram size and not OPTEE means that we are in the case where OPTEE is loaded already (maybe by ARM Trusted Firmware) and that most of the low level initialization is already done and that we may/should skip it doing them here. Signed-off-by: Rui Miguel Silva Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam Cc: u-boot@lists.denx.de --- include/configs/warp7.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/configs') diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 1b656a5aaf6..a391dfb5c10 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -13,6 +13,17 @@ #define PHYS_SDRAM_SIZE SZ_512M +/* + * If we have defined the OPTEE ram size and not OPTEE it means that we were + * launched by OPTEE, because of that we shall skip all the low level + * initialization since it was already done by ATF or OPTEE + */ +#ifdef CONFIG_OPTEE_TZDRAM_SIZE +#ifndef CONFIG_OPTEE +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#endif + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Size of malloc() pool */ -- cgit v1.3.1