From 3ca49c425f523d41bcec8a0eac24cce2d6a0da98 Mon Sep 17 00:00:00 2001 From: Po Liu Date: Wed, 26 Nov 2014 09:38:48 +0800 Subject: powerpc/c29xpcie: Add secure boot support Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu Signed-off-by: Mingkai.Hu Reviewed-by: York Sun --- include/configs/C29XPCIE.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index ecb3d7b25fd..e24b9233687 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -581,4 +581,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 37811ec2265bc56965ca0c1d9eb2ffa81aa8d9e9 Mon Sep 17 00:00:00 2001 From: harninder rai Date: Mon, 15 Dec 2014 12:58:45 +0530 Subject: powerpc/913x: Add config flag for bootdelay CONFIG_BOOTDELAY is missing from board header file. Add this macro to enable counting down of auto boot. Signed-off-by: Harninder Rai [York Sun: Add commit message] Reviewed-by: York Sun --- include/configs/BSC9131RDB.h | 1 + include/configs/BSC9132QDS.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index eeb0671ddb3..6aaaaa43f0f 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -433,6 +433,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index e8a8d299cd9..59a8d1b5d17 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -675,6 +675,7 @@ combinations. this should be removed later #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" -- cgit v1.3.1 From f49b8c1b5d9db6d349000b25312c672a1f6627b8 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Wed, 17 Dec 2014 15:42:54 +0800 Subject: mpc85xx/t102xrdb: convert deep sleep to generic board interface A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- board/freescale/t102xrdb/ddr.c | 19 +++++++++++++++++++ board/freescale/t102xrdb/spl.c | 7 +++++++ board/freescale/t102xrdb/t102xrdb.c | 23 +++++++++++------------ include/configs/T102xRDB.h | 21 ++++++++++++--------- 4 files changed, 49 insertions(+), 21 deletions(-) (limited to 'include/configs') diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index a20330b1d01..a2a8f4ccf04 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -136,6 +137,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -150,5 +164,10 @@ phys_size_t initdram(int board_type) /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index dd2dec44121..1a3a9964396 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -11,6 +11,7 @@ #include #include #include +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +43,12 @@ void board_init_f(ulong bootflag) console_init_f(); +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + /* initialize selected port with appropriate baud rate */ sys_clk = get_board_sys_clk(); plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f5c438ded3b..96457cf01a3 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -16,10 +16,10 @@ #include #include #include -#include #include #include "t102xrdb.h" #include "cpld.h" +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +55,16 @@ int checkboard(void) return 0; } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -131,14 +141,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 82b669ba6ed..e6222f3e179 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,7 +36,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg @@ -51,7 +54,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_FSL_LAW /* Use common FSL init code */ -#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -67,21 +70,21 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD @@ -91,12 +94,12 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD -- cgit v1.3.1 From e26416a3f1631b906776a4e965313b3269faf259 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 17 Dec 2014 16:51:08 +0800 Subject: powerpc/t1024rdb: Add support for T1024RDB-PB T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t102xrdb/cpld.h | 4 ++++ board/freescale/t102xrdb/eth_t102xrdb.c | 30 +++++++++++++++++++++++++++--- board/freescale/t102xrdb/t102xrdb.c | 31 ++++++++++++++++++++++++++++++- include/configs/T102xRDB.h | 2 ++ 4 files changed, 63 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h index 5a3100f6070..db50f818fbb 100644 --- a/board/freescale/t102xrdb/cpld.h +++ b/board/freescale/t102xrdb/cpld.h @@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 + +#define CPLD_PCIE_SGMII_MUX 0x80 +#define CPLD_OVERRIDE_BOOT_EN 0x01 +#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 2e400c4ebf1..f611ff07e98 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -21,6 +21,7 @@ #include #include #include +#include "../common/fman.h" int board_eth_init(bd_t *bis) { @@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis) /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + /* Set the on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { case 0x95: - /* 10G XFI with Aquantia PHY */ + /* set the on-board RGMII2 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + + /* set 10G XFI with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; + case 0x77: + case 0x135: + /* set the on-board 2.5G SGMII AQR105 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR); + break; default: printf("SerDes protocol 0x%x is not supported on T102xRDB\n", srds_s1); @@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; + case PHY_INTERFACE_MODE_SGMII_2500: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; default: break; } @@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) && + (port == FM1_DTSEC3)) { + fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); + fdt_setprop(fdt, offset, "phy-connection-type", + "sgmii-2500", 10); + fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); + } +} + void fdt_fixup_board_enet(void *fdt) { } diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 96457cf01a3..e196f12ac7a 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -27,6 +27,11 @@ int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; printf("Board: %sRDB, ", cpu->name); printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", @@ -50,11 +55,34 @@ int checkboard(void) #endif puts("SERDES Reference Clocks:\n"); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + if (srds_s1 == 0x95) + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + else + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); return 0; } +static void board_mux_lane(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 reg = CPLD_READ(misc_ctl_status); + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (srds_prtcl_s1 == 0x95) { + /* Route Lane B to PCIE */ + CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); + } else { + /* Route Lane B to SGMII */ + CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); + } + CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); +} + int board_early_init_f(void) { #if defined(CONFIG_DEEP_SLEEP) @@ -96,6 +124,7 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + board_mux_lane(); return 0; } diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e6222f3e179..bd40d6ac93c 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -762,8 +762,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 +#define SGMII_PHY1_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 #endif -- cgit v1.3.1 From 2c537642e98969e1810c6fdeff3099584f674a66 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Thu, 18 Dec 2014 09:55:07 +0800 Subject: mpc85xx/t102xqds: convert deep sleep to generic board interface A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- board/freescale/t102xqds/ddr.c | 19 +++++++++++++++++++ board/freescale/t102xqds/t102xqds.c | 23 +++++++++++------------ include/configs/T102xQDS.h | 3 +++ 3 files changed, 33 insertions(+), 12 deletions(-) (limited to 'include/configs') diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c index 46fc64e5280..2d4d10f351a 100644 --- a/board/freescale/t102xqds/ddr.c +++ b/board/freescale/t102xqds/ddr.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -152,6 +153,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -166,5 +180,10 @@ phys_size_t initdram(int board_type) /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index f3141b58e8d..708afcaebfa 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -19,10 +19,10 @@ #include #include #include -#include #include "../common/qixis.h" #include "t102xqds.h" #include "t102xqds_qixis.h" +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void) i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -395,14 +405,3 @@ void qixis_dump_switch(void) printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index c2bdbb99eda..3f02cede320 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -35,7 +35,10 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg -- cgit v1.3.1 From 7d0e97a2945c9da47ad4655f2e3de7e36b5cd7ac Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Thu, 18 Dec 2014 10:20:07 +0800 Subject: mpc85xx/t1040qds: convert deep sleep to generic board interface A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- board/freescale/t1040qds/ddr.c | 19 +++++++++++++++++++ board/freescale/t1040qds/t1040qds.c | 23 +++++++++++------------ include/configs/T1040QDS.h | 3 +++ 3 files changed, 33 insertions(+), 12 deletions(-) (limited to 'include/configs') diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 43f952f9c03..82402408a74 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -100,6 +101,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -112,5 +126,10 @@ phys_size_t initdram(int board_type) dram_size *= 0x100000; puts(" DDR: "); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 13285be42cf..eaca57fc5df 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -19,8 +19,8 @@ #include #include #include -#include +#include "../common/sleep.h" #include "../common/qixis.h" #include "t1040qds.h" #include "t1040qds_qixis.h" @@ -115,6 +115,16 @@ static void qe_board_setup(void) } } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -281,14 +291,3 @@ int board_need_mem_reset(void) { return 1; } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index b70bdfe5e79..5ebc8709aa1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -47,7 +47,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 -- cgit v1.3.1 From a83fccc2c979263ba88a6801130258124caca51a Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 21 Jan 2015 11:54:11 +0200 Subject: board/T1040qds: Add VSC9953 support for T1040qds board This patch configures and initializes the L2 switch on T1040QDS board. The L2 switch ports must be initialized according to the SerDes protocols. Signed-off-by: Codrin Ciubotariu --- board/freescale/t1040qds/eth.c | 91 ++++++++++++++++++++++++++++++++++++++++++ include/configs/T1040QDS.h | 6 +++ 2 files changed, 97 insertions(+) (limited to 'include/configs') diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 2f8e7536315..8c8293426bb 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/fman.h" #include "../common/qixis.h" @@ -439,6 +440,12 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; +#ifdef CONFIG_VSC9953 + int lane; + int phy_addr; + phy_interface_t phy_int; + struct mii_dev *bus; +#endif printf("Initializing Fman\n"); set_brdcfg9_for_gtx_clk(); @@ -493,6 +500,90 @@ int board_eth_init(bd_t *bis) } } +#ifdef CONFIG_VSC9953 + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + lane = -1; + phy_addr = 0; + phy_int = PHY_INTERFACE_MODE_NONE; + switch (i) { + case 0: + case 1: + case 2: + case 3: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A); + /* PHYs connected over QSGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + + i; + phy_int = PHY_INTERFACE_MODE_QSGMII; + break; + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_SW1_MAC1 + i); + + if (lane < 0) + break; + + /* PHYs connected over QSGMII */ + if (i != 3 || lane_to_slot[lane] == 7) + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + i; + else + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; + phy_int = PHY_INTERFACE_MODE_SGMII; + break; + case 4: + case 5: + case 6: + case 7: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B); + /* PHYs connected over QSGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + + i - 4; + phy_int = PHY_INTERFACE_MODE_QSGMII; + break; + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_SW1_MAC1 + i); + /* PHYs connected over SGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + i - 3; + phy_int = PHY_INTERFACE_MODE_SGMII; + } + break; + case 8: + if (serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1) < 0) + /* FM1@DTSEC1 is connected to SW1@PORT8 */ + vsc9953_port_enable(i); + break; + case 9: + if (serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC2) < 0) { + /* Enable L2 On MAC2 using SCFG */ + struct ccsr_scfg *scfg = (struct ccsr_scfg *) + CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, + in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(i); + } + break; + } + + if (lane >= 0) { + bus = mii_dev_for_muxval(lane_to_slot[lane]); + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_enable(i); + } + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + } + +#endif cpu_eth_init(bis); #endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5ebc8709aa1..92f5f56718c 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -692,6 +692,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif +/* Enable VSC9953 L2 Switch driver */ +#define CONFIG_VSC9953 +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 + /* * Dynamic MTD Partition support with mtdparts */ -- cgit v1.3.1 From db4a1767c09a4696792204d1cac33631cb38424e Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 21 Jan 2015 11:54:12 +0200 Subject: board/T1040rdb: Add VSC9953 support for T1040rdb board This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb. Signed-off-by: Codrin Ciubotariu --- board/freescale/t104xrdb/eth.c | 50 ++++++++++++++++++++++++++++++++++++++++++ include/configs/T104xRDB.h | 8 +++++++ 2 files changed, 58 insertions(+) (limited to 'include/configs') diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index f5c0ec80755..7581a4cdd44 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -6,11 +6,13 @@ #include #include +#include #include #include #include #include #include +#include #include "../common/fman.h" @@ -20,6 +22,11 @@ int board_eth_init(bd_t *bis) struct memac_mdio_info memac_mdio_info; unsigned int i; int phy_addr = 0; +#ifdef CONFIG_VSC9953 + phy_interface_t phy_int; + struct mii_dev *bus; +#endif + printf("Initializing Fman\n"); memac_mdio_info.regs = @@ -81,6 +88,49 @@ int board_eth_init(bd_t *bis) DEFAULT_FM_MDIO_NAME)); } +#ifdef CONFIG_VSC9953 + /* SerDes configured for QSGMII */ + if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { + for (i = 0; i < 4; i++) { + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; + phy_int = PHY_INTERFACE_MODE_QSGMII; + + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + vsc9953_port_enable(i); + } + } + if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { + for (i = 4; i < 8; i++) { + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; + phy_int = PHY_INTERFACE_MODE_QSGMII; + + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + vsc9953_port_enable(i); + } + } + + /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */ + if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) + vsc9953_port_enable(8); + + /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */ + if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { + /* Enable L2 On MAC2 using SCFG */ + struct ccsr_scfg *scfg = (struct ccsr_scfg *) + CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(9); + } +#endif + cpu_eth_init(bis); #endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 57cdf7213c4..d47f1be6851 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -726,6 +726,14 @@ #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +/* Enable VSC9953 L2 Switch driver on T1040 SoC */ +#ifdef CONFIG_T1040RDB +#define CONFIG_VSC9953 +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#endif + #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -- cgit v1.3.1