From 6b109a1304a03b35ad489e551964737ad80f6a82 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:21 -0600 Subject: siemens: Quote A/B flags in env tests The Siemens am33x-common, env-common and draco-etamin headers gate boot-partition selection logic on: if test -n ${A}; then ... if test -n ${B}; then ... A and B are flags that the upgrade machinery sets to mark "the other partition just became active". The default state is unset, in which case the expression expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the branch. Quote each variable so an unset A or B expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass --- include/configs/draco-etamin.h | 4 ++-- include/configs/siemens-am33x-common.h | 12 ++++++------ include/configs/siemens-env-common.h | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include/configs') diff --git a/include/configs/draco-etamin.h b/include/configs/draco-etamin.h index 6ae85b575b7..b1b403980b1 100644 --- a/include/configs/draco-etamin.h +++ b/include/configs/draco-etamin.h @@ -99,10 +99,10 @@ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ "fi;" \ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index a918dc1350c..da822556909 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -104,11 +104,11 @@ "then " \ "setenv upgrade_available 0;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv partitionset_active B; " \ "env delete A; " \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv partitionset_active A; " \ "env delete B; " \ "fi;" \ @@ -205,11 +205,11 @@ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \ "setenv nand_src_addr ${nand_src_addr_A};" \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \ "setenv nand_src_addr ${nand_src_addr_B};" \ "fi;" \ @@ -279,10 +279,10 @@ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ "fi;" \ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h index c028823e1eb..8ced77cc5e2 100644 --- a/include/configs/siemens-env-common.h +++ b/include/configs/siemens-env-common.h @@ -81,12 +81,12 @@ */ #define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; " \ + "if test -n \"${A}\"; " \ "then " \ "setenv partitionset_active B; " \ "env delete A; " \ "fi;" \ - "if test -n ${B}; "\ + "if test -n \"${B}\"; "\ "then " \ "setenv partitionset_active A; " \ "env delete B; " \ @@ -103,11 +103,11 @@ */ #define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; " \ + "if test -n \"${A}\"; " \ "then " \ "setenv mmc_part_nr 1;" \ "fi;" \ - "if test -n ${B}; " \ + "if test -n \"${B}\"; " \ "then " \ "setenv mmc_part_nr 2;" \ "fi;" \ -- cgit v1.3.1 From 2120834c25d525b754a8473565d4e0f9c158d806 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:22 -0600 Subject: beaglev_fire: Quote no_of_overlays in design test On beaglev_fire, design_overlays gates an overlay-application loop on: if test -n ${no_of_overlays}; then ... The default state is "no overlays", i.e. no_of_overlays unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the loop. Quote the variable so an unset no_of_overlays expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass --- include/configs/beaglev_fire.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/beaglev_fire.h b/include/configs/beaglev_fire.h index e3ee0f02f2d..8724a71504c 100644 --- a/include/configs/beaglev_fire.h +++ b/include/configs/beaglev_fire.h @@ -30,7 +30,7 @@ #define BOOTENV_DESIGN_OVERLAYS \ "design_overlays=" \ - "if test -n ${no_of_overlays}; then " \ + "if test -n \"${no_of_overlays}\"; then " \ "setenv inc 1; " \ "setenv idx 0; " \ "fdt resize ${dtbo_size}; " \ -- cgit v1.3.1 From 9458e39c6595e2e00a1d0a645676eaf935e783c7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:23 -0600 Subject: mccmon6: Quote recovery_status in bootcmd test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mccmon6 bootcmd starts with: if test -n ${recovery_status}; then run boot_recovery; ... The default state is "no recovery requested", i.e. recovery_status unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip recovery. Quote the variable so an unset recovery_status expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass Reviewed-by: Łukasz Majewski --- include/configs/mccmon6.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 9f401718bfb..0cf62d6bda8 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -88,7 +88,7 @@ "bootm $loadaddr};reset;" \ "fi\0" \ "bootcmd=" \ - "if test -n ${recovery_status}; then " \ + "if test -n \"${recovery_status}\"; then " \ "run boot_recovery;" \ "else " \ "if test ! -n ${boot_medium}; then " \ -- cgit v1.3.1 From 93d7dc20e80e33ace9b871de44877548642f86cb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:24 -0600 Subject: aristainetos2: Quote rescue_reason in rescueboot test The rescueboot script optionally runs a per-board rescue_reason hook with: if test -n ${rescue_reason}; then run rescue_reason; fi; The default state is "no rescue reason script", i.e. rescue_reason unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the run. Quote the variable so an unset rescue_reason expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher --- include/configs/aristainetos2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8a66b1275df..2078ebc5282 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -211,7 +211,7 @@ "${pubkey}\0" \ "rescueboot=echo Booting rescue system ...; " \ "run addmtd addmisc;" \ - "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ + "if test -n \"${rescue_reason}\"; then run rescue_reason;fi;" \ "run boot_board_type;" \ "if bootm ${fit_addr_r}; then ; " \ "else " \ -- cgit v1.3.1 From 5e41a5deb4b843808f3c892f2f54f1b9c76b3da1 Mon Sep 17 00:00:00 2001 From: James Hilliard Date: Mon, 11 May 2026 12:20:25 -0600 Subject: env: migrate static flags list to Kconfig Environment callbacks can already be configured from Kconfig with CONFIG_ENV_CALLBACK_LIST_STATIC, but static environment flags still require board headers to define CFG_ENV_FLAGS_LIST_STATIC. Add CONFIG_ENV_FLAGS_LIST_STATIC and use it as the only board-provided static environment flags list. Convert the remaining default-config users from CFG_ENV_FLAGS_LIST_STATIC to defconfig settings and drop the legacy header macro from ENV_FLAGS_LIST_STATIC. Move the environment flags format documentation out of README and into the developer environment documentation. Include the format in the Kconfig help as well. This lets boards configure writeable-list policy and type validation from defconfig without adding a config header solely for env flags. This preserves the behavior of default configs. Header-only cases that were inactive in upstream defconfigs are not converted into defconfig entries: iot2050 can add its list when enabling ENV_WRITEABLE_LIST, and smegw01 can add mmcdev:dw support if the unlocked SYS_BOOT_LOCKED=n configuration is needed. Signed-off-by: James Hilliard Reviewed-by: Tom Rini Reviewed-by: Simon Glass Reviewed-by: Alexander Sverdlin Reviewed-by: Walter Schweizer --- README | 45 +----------------------------------- configs/aristainetos2c_defconfig | 1 + configs/aristainetos2ccslb_defconfig | 1 + configs/hmibsc_defconfig | 1 + configs/imx6q_bosch_acc_defconfig | 1 + configs/imx8qxp_capricorn.config | 1 + configs/smegw01_defconfig | 1 + configs/socrates_defconfig | 1 + doc/develop/environment.rst | 40 ++++++++++++++++++++++++++++++++ env/Kconfig | 23 ++++++++++++++++++ include/configs/aristainetos2.h | 3 --- include/configs/capricorn-common.h | 13 ----------- include/configs/hmibsc.h | 4 ---- include/configs/imx6q-bosch-acc.h | 12 ---------- include/configs/iot2050.h | 8 ------- include/configs/smegw01.h | 15 ------------ include/configs/socrates.h | 2 -- include/env_flags.h | 6 +---- 18 files changed, 72 insertions(+), 106 deletions(-) (limited to 'include/configs') diff --git a/README b/README index 6836a917c79..664d88a5505 100644 --- a/README +++ b/README @@ -799,7 +799,7 @@ The following options need to be configured: The same can be accomplished in a more flexible way for any variable by configuring the type of access to allow for those variables in the ".flags" variable - or define CFG_ENV_FLAGS_LIST_STATIC. + or by setting CONFIG_ENV_FLAGS_LIST_STATIC. - Protected RAM: CFG_PRAM @@ -1106,49 +1106,6 @@ Configuration Settings: - CONFIG_SYS_FLASH_USE_BUFFER_WRITE Use buffered writes to flash. -- CONFIG_ENV_FLAGS_LIST_DEFAULT -- CFG_ENV_FLAGS_LIST_STATIC - Enable validation of the values given to environment variables when - calling env set. Variables can be restricted to only decimal, - hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, - the variables can also be restricted to IP address or MAC address. - - The format of the list is: - type_attribute = [s|d|x|b|i|m] - access_attribute = [a|r|o|c] - attributes = type_attribute[access_attribute] - entry = variable_name[:attributes] - list = entry[,list] - - The type attributes are: - s - String (default) - d - Decimal - x - Hexadecimal - b - Boolean ([1yYtT|0nNfF]) - i - IP address - m - MAC address - - The access attributes are: - a - Any (default) - r - Read-only - o - Write-once - c - Change-default - - - CONFIG_ENV_FLAGS_LIST_DEFAULT - Define this to a list (string) to define the ".flags" - environment variable in the default or embedded environment. - - - CFG_ENV_FLAGS_LIST_STATIC - Define this to a list (string) to define validation that - should be done if an entry is not found in the ".flags" - environment variable. To override a setting in the static - list, simply add an entry for the same variable name to the - ".flags" variable. - - If CONFIG_REGEX is defined, the variable_name above is evaluated as a - regular expression. This allows multiple variables to define the same - flags without explicitly listing them for each variable. - The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 6923d27f79a..6c44e670cbc 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_FLAGS_LIST_STATIC="ethaddr:mw,serial#:sw,board_type:sw,sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 3ffebb15375..5016646ef87 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_FLAGS_LIST_STATIC="ethaddr:mw,serial#:sw,board_type:sw,sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig index 1e3d744193d..c8fad154e31 100644 --- a/configs/hmibsc_defconfig +++ b/configs/hmibsc_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_OF_UPSTREAM is not set +CONFIG_ENV_FLAGS_LIST_STATIC="BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 6f0ef2eaee3..87cf676ed4c 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -74,6 +74,7 @@ CONFIG_EFI_PARTITION=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_ENV_FLAGS_LIST_STATIC="bootset:bw,clone_pending:bw,endurance_test:bw,env_persisted:bw,factory_reset:bw,fdtcontroladdr:xw,fitpart:dw,mmcpart:dw,production:bw,ustate:dw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 2bae5b1a862..91da5554db0 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -92,6 +92,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_FLAGS_LIST_STATIC="bootcount:dw,bootdelay:sw,bootlimit:dw,partitionset_active:sw,rastate:dw,sig_a:sw,sig_b:sw,target_env:sw,upgrade_available:dw,ustate:dw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 529836e7bdd..e5d4014d640 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_ENV_FLAGS_LIST_STATIC="mmcpart:dw,mmcpart_committed:dw,ustate:dw,bootcount:dw,bootlimit:dw,upgrade_available:dw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 217141cceda..79e40268c6b 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -66,6 +66,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe000000.nor_flash,nand0=socrates_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(system2),5120k(data),128k(env),128k(env-red),768k(u-boot);socrates_nand:256M(ubi-data1),-(ubi-data2)" # CONFIG_CMD_IRQ is not set CONFIG_OF_CONTROL=y +CONFIG_ENV_FLAGS_LIST_STATIC="ethaddr:mw,eth1addr:mw,system1_addr:xw,serial#:sw,ethact:sw,ethprime:sw" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xFFF00000 diff --git a/doc/develop/environment.rst b/doc/develop/environment.rst index e46cd39d601..a7ed4aab0a5 100644 --- a/doc/develop/environment.rst +++ b/doc/develop/environment.rst @@ -49,3 +49,43 @@ The signature of the callback functions is:: include/search.h The return value is 0 if the variable change is accepted and 1 otherwise. + +Flags for environment variables +------------------------------- + +Environment flags validate the values given to environment variables and +restrict how environment variables can be changed. + +The static list is configured with CONFIG_ENV_FLAGS_LIST_STATIC. The list +must be in the following format:: + + type_attribute = [s|d|x|b|i|m] + access_attribute = [a|r|o|c|w] + attributes = type_attribute[access_attribute] + entry = variable_name[:attributes] + list = entry[,list] + +The type attributes are: + +* s - String (default) +* d - Decimal +* x - Hexadecimal +* b - Boolean ([1yYtT|0nNfF]) +* i - IP address, if networking is enabled +* m - MAC address, if networking is enabled + +The access attributes are: + +* a - Any (default) +* r - Read-only +* o - Write-once +* c - Change-default +* w - Writeable, if CONFIG_ENV_WRITEABLE_LIST is enabled + +CONFIG_ENV_FLAGS_LIST_DEFAULT defines the ``.flags`` variable in the +default or embedded environment. Any association in ``.flags`` overrides +an association in the static list. + +If CONFIG_REGEX is defined, the variable name is evaluated as a regular +expression. This allows multiple variables to define the same flags without +explicitly listing them all. diff --git a/env/Kconfig b/env/Kconfig index 7abd82ab6f3..3c9aaeb1f16 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -34,6 +34,29 @@ config ENV_CALLBACK_LIST_STATIC If the callback name is not specified, then the callback is deleted. Spaces are also allowed anywhere in the list. +config ENV_FLAGS_LIST_STATIC + string "Static flags list" + default "" + help + The environment flags are associated with variables in a static + list. Define this list in the following format: + + type_attribute = [s|d|x|b|i|m] + access_attribute = [a|r|o|c|w] + attributes = type_attribute[access_attribute] + entry = variable_name[:attributes] + list = entry[,list] + + The type attributes are s for string, d for decimal, x for + hexadecimal and b for boolean. If networking is enabled, i can + be used for IP addresses and m for MAC addresses. + + The access attributes are a for any, r for read-only, o for + write-once and c for change-default. When CONFIG_ENV_WRITEABLE_LIST + is enabled, w can be used to mark variables as writable. + + Spaces are also allowed anywhere in the list. + config SAVEENV def_bool y if CMD_SAVEENV diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8a66b1275df..c0e5c72764e 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -413,7 +413,4 @@ /* UBI support */ -#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ - "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" - #endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index ee13d2ab950..7120a44d186 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -38,19 +38,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV -#ifdef CONFIG_ENV_WRITEABLE_LIST -#define CFG_ENV_FLAGS_LIST_STATIC \ - "bootcount:dw," \ - "bootdelay:sw," \ - "bootlimit:dw," \ - "partitionset_active:sw," \ - "rastate:dw," \ - "sig_a:sw,sig_b:sw," \ - "target_env:sw," \ - "upgrade_available:dw," \ - "ustate:dw" -#endif - /* Default location for tftp and bootm */ /* On CCP board, USDHC1 is for eMMC */ diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h index 950ec8b190d..ea9762ee448 100644 --- a/include/configs/hmibsc.h +++ b/include/configs/hmibsc.h @@ -8,8 +8,4 @@ #ifndef __CONFIGS_HMIBSC_H #define __CONFIGS_HMIBSC_H -/* PHY needs a longer aneg time */ - -#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" - #endif diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 84da8250684..e00cddfdac0 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -44,18 +44,6 @@ "then env set env_persisted 1; run save_env; fi;\0" \ "save_env=env save; env save\0" -#define CFG_ENV_FLAGS_LIST_STATIC \ - "bootset:bw," \ - "clone_pending:bw," \ - "endurance_test:bw," \ - "env_persisted:bw," \ - "factory_reset:bw," \ - "fdtcontroladdr:xw," \ - "fitpart:dw," \ - "mmcpart:dw," \ - "production:bw," \ - "ustate:dw" - #else /* SD Card boot */ #define ENV_EXTRA \ diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 5c58c7bbaab..fac4bbcd4ed 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -38,12 +38,4 @@ func(MMC, mmc, 0) \ BOOT_TARGET_USB(func) -#ifdef CONFIG_ENV_WRITEABLE_LIST -#define CFG_ENV_FLAGS_LIST_STATIC \ - "board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \ - "mlfb:sw,fw_version:sw,seboot_version:sw," \ - "m2_manual_config:sw," \ - "eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw" -#endif - #endif /* __CONFIG_IOT2050_H */ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 0aa25f9e2ea..c0ca5a7db2f 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -22,21 +22,6 @@ #define EXTRA_BOOTPARAMS #endif -#ifdef CONFIG_SYS_BOOT_LOCKED -#define EXTRA_ENV_FLAGS -#else -#define EXTRA_ENV_FLAGS "mmcdev:dw," -#endif - -#define CFG_ENV_FLAGS_LIST_STATIC \ - "mmcpart:dw," \ - "mmcpart_committed:dw," \ - "ustate:dw," \ - "bootcount:dw," \ - "bootlimit:dw," \ - "upgrade_available:dw," \ - EXTRA_ENV_FLAGS - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 006d649f6ed..68d177d4ca3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -108,8 +108,6 @@ */ #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,eth1addr:mw,system1_addr:xw,serial#:sw,ethact:sw,ethprime:sw" - /* pass open firmware flat tree */ #endif /* __CONFIG_H */ diff --git a/include/env_flags.h b/include/env_flags.h index 123fdbcb0ba..245dfdbd564 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -37,10 +37,6 @@ enum env_flags_varaccess { #define ENV_FLAGS_VARTYPE_LOC 0 #define ENV_FLAGS_VARACCESS_LOC 1 -#ifndef CFG_ENV_FLAGS_LIST_STATIC -#define CFG_ENV_FLAGS_LIST_STATIC "" -#endif - #if CONFIG_IS_ENABLED(NET) #ifdef CONFIG_REGEX #define ETHADDR_WILDCARD "\\d*" @@ -89,7 +85,7 @@ enum env_flags_varaccess { NET_FLAGS \ NET6_FLAGS \ SERIAL_FLAGS \ - CFG_ENV_FLAGS_LIST_STATIC + CONFIG_ENV_FLAGS_LIST_STATIC #ifdef CONFIG_CMD_ENV_FLAGS /* -- cgit v1.3.1 From 87ea6e67959099804faf4eb85d93a41f18db71c9 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:20 -0400 Subject: mach-sc5xx: sc573: Rename EZKIT board to EZLITE Rename the SC573 EZKIT board to EZLITE across the device tree, defconfig, board file, and related Kconfig/Makefile entries to match with release naming. EZKIT was used internally before the official product release. Signed-off-by: Caleb Ethridge Reviewed-by: Simon Glass --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/sc573-ezkit.dts | 253 ------------------------ arch/arm/dts/sc573-ezlite.dts | 253 ++++++++++++++++++++++++ arch/arm/mach-sc5xx/Kconfig | 8 +- arch/arm/mach-sc5xx/init/dmcinit.c | 2 +- board/adi/sc573-ezkit/Kconfig | 116 ----------- board/adi/sc573-ezkit/Makefile | 6 - board/adi/sc573-ezkit/sc573-ezkit.c | 21 -- board/adi/sc573-ezkit/sc573-ezkit.env | 15 -- board/adi/sc573-ezlite/Kconfig | 116 +++++++++++ board/adi/sc573-ezlite/Makefile | 6 + board/adi/sc573-ezlite/sc573-ezlite.c | 21 ++ board/adi/sc573-ezlite/sc573-ezlite.env | 15 ++ configs/sc573-ezkit_defconfig | 85 -------- configs/sc573-ezlite_defconfig | 85 ++++++++ doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml | 2 +- include/configs/sc573-ezkit.h | 18 -- include/configs/sc573-ezlite.h | 18 ++ 18 files changed, 521 insertions(+), 521 deletions(-) delete mode 100644 arch/arm/dts/sc573-ezkit.dts create mode 100644 arch/arm/dts/sc573-ezlite.dts delete mode 100644 board/adi/sc573-ezkit/Kconfig delete mode 100644 board/adi/sc573-ezkit/Makefile delete mode 100644 board/adi/sc573-ezkit/sc573-ezkit.c delete mode 100644 board/adi/sc573-ezkit/sc573-ezkit.env create mode 100644 board/adi/sc573-ezlite/Kconfig create mode 100644 board/adi/sc573-ezlite/Makefile create mode 100644 board/adi/sc573-ezlite/sc573-ezlite.c create mode 100644 board/adi/sc573-ezlite/sc573-ezlite.env delete mode 100644 configs/sc573-ezkit_defconfig create mode 100644 configs/sc573-ezlite_defconfig delete mode 100644 include/configs/sc573-ezkit.h create mode 100644 include/configs/sc573-ezlite.h (limited to 'include/configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d5dd0867622..1e8676284b7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1178,7 +1178,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \ imx8mm-cl-iot-gate-ied-tpm0.dtbo \ imx8mm-cl-iot-gate-ied-tpm1.dtbo -dtb-$(CONFIG_TARGET_SC573_EZKIT) += sc573-ezkit.dtb +dtb-$(CONFIG_TARGET_SC573_EZLITE) += sc573-ezlite.dtb dtb-$(CONFIG_TARGET_SC584_EZKIT) += sc584-ezkit.dtb dtb-$(CONFIG_TARGET_SC589_MINI) += sc589-mini.dtb dtb-$(CONFIG_TARGET_SC589_EZKIT) += sc589-ezkit.dtb diff --git a/arch/arm/dts/sc573-ezkit.dts b/arch/arm/dts/sc573-ezkit.dts deleted file mode 100644 index 4a3d1ed5c56..00000000000 --- a/arch/arm/dts/sc573-ezkit.dts +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -/dts-v1/; - -#include "sc5xx.dtsi" -#include "sc57x.dtsi" - -/ { - model = "ADI SC573-EZKIT"; - compatible = "adi,sc573-ezkit", "adi,sc57x"; -}; - -&i2c0 { - gpio_expander0: mcp23017@21 { - compatible = "microchip,mcp23017"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - bootph-pre-ram; - - eeprom { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-low; - line-name = "eeprom-en"; - bootph-pre-ram; - }; - - uart0-flow-en { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-low; - line-name = "uart0-flow-en"; - bootph-pre-ram; - }; - - mlb { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - output-low; - line-name = "mlb-en"; - bootph-pre-ram; - }; - - can0 { - gpio-hog; - gpios = <6 GPIO_ACTIVE_LOW>; - output-low; - line-name = "can0-en"; - bootph-pre-ram; - }; - - can1 { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "can1-en"; - bootph-pre-ram; - }; - - adau1962 { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-high; - line-name = "adau1962-en"; - bootph-pre-ram; - }; - - adau1979 { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-high; - line-name = "adau1979-en"; - bootph-pre-ram; - }; - - sd-wp-en { - gpio-hog; - gpios = <11 GPIO_ACTIVE_LOW>; - output-low; - line-name = "sd-wp-en"; - bootph-pre-ram; - }; - - spi2flash-cs { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - output-high; - line-name = "spi2flash-cs"; - bootph-pre-ram; - }; - - spi2d2-d3 { - gpio-hog; - gpios = <13 GPIO_ACTIVE_LOW>; - output-high; - line-name = "spi2d2-d3-en"; - bootph-pre-ram; - }; - - spdif-opt { - gpio-hog; - gpios = <14 GPIO_ACTIVE_LOW>; - output-low; - line-name = "spdif-optical-en"; - bootph-pre-ram; - }; - - spdif-dig { - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - output-low; - line-name = "spdif-digital-en"; - bootph-pre-ram; - }; - }; - - gpio_expander1: mcp23017@22 { - compatible = "microchip,mcp23017"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - bootph-pre-ram; - - pushbutton3 { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pushbutton3-en"; - bootph-pre-ram; - }; - - pushbutton2 { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pushbutton2-en"; - bootph-pre-ram; - }; - - pushbutton1 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pushbutton1-en"; - bootph-pre-ram; - }; - - leds { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "leds-en"; - bootph-pre-ram; - }; - - flg0 { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg0_loop"; - bootph-pre-ram; - }; - - flg1 { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg1_loop"; - bootph-pre-ram; - }; - - flg2 { - gpio-hog; - gpios = <6 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg2_loop"; - bootph-pre-ram; - }; - - flg3 { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg3_loop"; - bootph-pre-ram; - }; - - adau1977 { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-low; - line-name = "adau1977_en"; - bootph-pre-ram; - }; - - adau1977_fault_rst { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-low; - line-name = "adau1977_fault_rst_en"; - bootph-pre-ram; - }; - - thumbwheel { - gpio-hog; - gpios = <10 GPIO_ACTIVE_LOW>; - output-low; - line-name = "thumbwheel_oe"; - bootph-pre-ram; - }; - - engine_rpm { - gpio-hog; - gpios = <11 GPIO_ACTIVE_LOW>; - output-low; - line-name = "engine_rpm_oe"; - bootph-pre-ram; - }; - }; -}; - -ð0 { - snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('A', 5) GPIO_ACTIVE_LOW>; -}; - -&gpio0 { - emac0_phy_pwdn { - gpio-hog; - output-high; - gpios = ; - }; -}; - -&mmc { - status = "okay"; -}; - -&spi2 { - flash1: is25lp512@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor", "is25lp512"; - reg = <1>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-max-frequency = <10000000>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/sc573-ezlite.dts b/arch/arm/dts/sc573-ezlite.dts new file mode 100644 index 00000000000..57604d707f7 --- /dev/null +++ b/arch/arm/dts/sc573-ezlite.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +/dts-v1/; + +#include "sc5xx.dtsi" +#include "sc57x.dtsi" + +/ { + model = "ADI SC573-EZLITE"; + compatible = "adi,sc573-ezlite", "adi,sc57x"; +}; + +&i2c0 { + gpio_expander0: mcp23017@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + bootph-pre-ram; + + eeprom { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-low; + line-name = "eeprom-en"; + bootph-pre-ram; + }; + + uart0-flow-en { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "uart0-flow-en"; + bootph-pre-ram; + }; + + mlb { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "mlb-en"; + bootph-pre-ram; + }; + + can0 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "can0-en"; + bootph-pre-ram; + }; + + can1 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "can1-en"; + bootph-pre-ram; + }; + + adau1962 { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-high; + line-name = "adau1962-en"; + bootph-pre-ram; + }; + + adau1979 { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-high; + line-name = "adau1979-en"; + bootph-pre-ram; + }; + + sd-wp-en { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + output-low; + line-name = "sd-wp-en"; + bootph-pre-ram; + }; + + spi2flash-cs { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-high; + line-name = "spi2flash-cs"; + bootph-pre-ram; + }; + + spi2d2-d3 { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-high; + line-name = "spi2d2-d3-en"; + bootph-pre-ram; + }; + + spdif-opt { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + output-low; + line-name = "spdif-optical-en"; + bootph-pre-ram; + }; + + spdif-dig { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-low; + line-name = "spdif-digital-en"; + bootph-pre-ram; + }; + }; + + gpio_expander1: mcp23017@22 { + compatible = "microchip,mcp23017"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + bootph-pre-ram; + + pushbutton3 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pushbutton3-en"; + bootph-pre-ram; + }; + + pushbutton2 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pushbutton2-en"; + bootph-pre-ram; + }; + + pushbutton1 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pushbutton1-en"; + bootph-pre-ram; + }; + + leds { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "leds-en"; + bootph-pre-ram; + }; + + flg0 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg0_loop"; + bootph-pre-ram; + }; + + flg1 { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg1_loop"; + bootph-pre-ram; + }; + + flg2 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg2_loop"; + bootph-pre-ram; + }; + + flg3 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg3_loop"; + bootph-pre-ram; + }; + + adau1977 { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-low; + line-name = "adau1977_en"; + bootph-pre-ram; + }; + + adau1977_fault_rst { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-low; + line-name = "adau1977_fault_rst_en"; + bootph-pre-ram; + }; + + thumbwheel { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "thumbwheel_oe"; + bootph-pre-ram; + }; + + engine_rpm { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + output-low; + line-name = "engine_rpm_oe"; + bootph-pre-ram; + }; + }; +}; + +ð0 { + snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('A', 5) GPIO_ACTIVE_LOW>; +}; + +&gpio0 { + emac0_phy_pwdn { + gpio-hog; + output-high; + gpios = ; + }; +}; + +&mmc { + status = "okay"; +}; + +&spi2 { + flash1: is25lp512@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "is25lp512"; + reg = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <10000000>; + bootph-pre-ram; + }; +}; diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index 70fab57fb3c..e311a8adf9a 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -25,7 +25,7 @@ config SC57X bool "SC57x series" select COMMON_CLK_ADI_SC57X select CPU_V7A - select TARGET_SC573_EZKIT + select TARGET_SC573_EZLITE config SC58X bool "SC58x series" @@ -51,8 +51,8 @@ endchoice if SC57X -config TARGET_SC573_EZKIT - bool "Support SC573-EZKIT" +config TARGET_SC573_EZLITE + bool "Support SC573-EZLITE" endif @@ -600,6 +600,6 @@ source "board/adi/sc594-som-ezlite/Kconfig" source "board/adi/sc589-ezkit/Kconfig" source "board/adi/sc589-mini/Kconfig" source "board/adi/sc584-ezkit/Kconfig" -source "board/adi/sc573-ezkit/Kconfig" +source "board/adi/sc573-ezlite/Kconfig" endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c index 12052613feb..2026735cc21 100644 --- a/arch/arm/mach-sc5xx/init/dmcinit.c +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -101,7 +101,7 @@ #ifdef CONFIG_TARGET_SC584_EZKIT #define DMC_PADCTL2_VALUE 0x0078283C -#elif CONFIG_TARGET_SC573_EZKIT +#elif CONFIG_TARGET_SC573_EZLITE #define DMC_PADCTL2_VALUE 0x00782828 #elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT #define DMC_PADCTL2_VALUE 0x00783C3C diff --git a/board/adi/sc573-ezkit/Kconfig b/board/adi/sc573-ezkit/Kconfig deleted file mode 100644 index 328563c1296..00000000000 --- a/board/adi/sc573-ezkit/Kconfig +++ /dev/null @@ -1,116 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2024 - Analog Devices, Inc. - -if TARGET_SC573_EZKIT - -config SYS_BOARD - default "sc573-ezkit" - -config SYS_CONFIG_NAME - default "sc573-ezkit" - -config LDR_CPU - default "ADSP-SC573-0.0" - -config DEFAULT_DEVICE_TREE - default "sc573-ezkit" - -config ADI_IMAGE - default "tiny" - -config CUSTOM_SYS_INIT_SP_ADDR - default 0x8203f000 - -# SPI Flash - -config SF_DEFAULT_BUS - default 2 - -config SF_DEFAULT_CS - default 1 - -config SF_DEFAULT_SPEED - default 10000000 - -# Clocks - -config CGU0_DF_DIV - default 0 - -config CGU0_VCO_MULT - default 18 - -config CGU0_CCLK_DIV - default 1 - -config CGU0_SCLK_DIV - default 2 - -config CGU0_SCLK0_DIV - default 2 - -config CGU0_SCLK1_DIV - default 2 - -config CGU0_DCLK_DIV - default 2 - -config CGU0_OCLK_DIV - default 3 - -config CGU1_VCO_MULT - default 5 - -config CGU1_DF_DIV - default 0 - -config CGU1_CCLK_DIV - default 1 - -config CGU1_SCLK_DIV - default 2 - -config CGU1_SCLK0_DIV - default 2 - -config CGU1_SCLK1_DIV - default 2 - -config CGU1_DCLK_DIV - default 2 - -config CGU1_OCLK_DIV - default 3 - -config CDU0_CLKO0 - default 1 - -config CDU0_CLKO1 - default 1 - -config CDU0_CLKO2 - default 1 - -config CDU0_CLKO3 - default 1 - -config CDU0_CLKO4 - default 1 - -config CDU0_CLKO5 - default 1 - -config CDU0_CLKO6 - default 1 - -config CDU0_CLKO7 - default 5 - -config CDU0_CLKO8 - default 1 - -config CDU0_CLKO9 - default 1 - -endif diff --git a/board/adi/sc573-ezkit/Makefile b/board/adi/sc573-ezkit/Makefile deleted file mode 100644 index 0ea725b992b..00000000000 --- a/board/adi/sc573-ezkit/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2025 - Analog Devices, Inc. -# - -obj-y += sc573-ezkit.o diff --git a/board/adi/sc573-ezkit/sc573-ezkit.c b/board/adi/sc573-ezkit/sc573-ezkit.c deleted file mode 100644 index 464142b27a5..00000000000 --- a/board/adi/sc573-ezkit/sc573-ezkit.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2025 - Analog Devices, Inc. - */ - -#include -#include -#include -#include - -int board_phy_config(struct phy_device *phydev) -{ - fixup_dp83867_phy(phydev); - return 0; -} - -int board_init(void) -{ - sc5xx_enable_rgmii(); - return 0; -} diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env deleted file mode 100644 index e1ad4f3716f..00000000000 --- a/board/adi/sc573-ezkit/sc573-ezkit.env +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later+ */ -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -adi_image_offset=0xe0000 -loadaddr=CONFIG_SC5XX_LOADADDR - -#define USE_NFS -#define USE_SPI -#define USE_RAM -#define USE_MMC -#define USE_USB - -#include diff --git a/board/adi/sc573-ezlite/Kconfig b/board/adi/sc573-ezlite/Kconfig new file mode 100644 index 00000000000..f3b848ef0f7 --- /dev/null +++ b/board/adi/sc573-ezlite/Kconfig @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2024 - Analog Devices, Inc. + +if TARGET_SC573_EZLITE + +config SYS_BOARD + default "sc573-ezlite" + +config SYS_CONFIG_NAME + default "sc573-ezlite" + +config LDR_CPU + default "ADSP-SC573-0.0" + +config DEFAULT_DEVICE_TREE + default "sc573-ezlite" + +config ADI_IMAGE + default "tiny" + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x8203f000 + +# SPI Flash + +config SF_DEFAULT_BUS + default 2 + +config SF_DEFAULT_CS + default 1 + +config SF_DEFAULT_SPEED + default 10000000 + +# Clocks + +config CGU0_DF_DIV + default 0 + +config CGU0_VCO_MULT + default 18 + +config CGU0_CCLK_DIV + default 1 + +config CGU0_SCLK_DIV + default 2 + +config CGU0_SCLK0_DIV + default 2 + +config CGU0_SCLK1_DIV + default 2 + +config CGU0_DCLK_DIV + default 2 + +config CGU0_OCLK_DIV + default 3 + +config CGU1_VCO_MULT + default 5 + +config CGU1_DF_DIV + default 0 + +config CGU1_CCLK_DIV + default 1 + +config CGU1_SCLK_DIV + default 2 + +config CGU1_SCLK0_DIV + default 2 + +config CGU1_SCLK1_DIV + default 2 + +config CGU1_DCLK_DIV + default 2 + +config CGU1_OCLK_DIV + default 3 + +config CDU0_CLKO0 + default 1 + +config CDU0_CLKO1 + default 1 + +config CDU0_CLKO2 + default 1 + +config CDU0_CLKO3 + default 1 + +config CDU0_CLKO4 + default 1 + +config CDU0_CLKO5 + default 1 + +config CDU0_CLKO6 + default 1 + +config CDU0_CLKO7 + default 5 + +config CDU0_CLKO8 + default 1 + +config CDU0_CLKO9 + default 1 + +endif diff --git a/board/adi/sc573-ezlite/Makefile b/board/adi/sc573-ezlite/Makefile new file mode 100644 index 00000000000..77c55af6240 --- /dev/null +++ b/board/adi/sc573-ezlite/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2025 - Analog Devices, Inc. +# + +obj-y += sc573-ezlite.o diff --git a/board/adi/sc573-ezlite/sc573-ezlite.c b/board/adi/sc573-ezlite/sc573-ezlite.c new file mode 100644 index 00000000000..464142b27a5 --- /dev/null +++ b/board/adi/sc573-ezlite/sc573-ezlite.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2025 - Analog Devices, Inc. + */ + +#include +#include +#include +#include + +int board_phy_config(struct phy_device *phydev) +{ + fixup_dp83867_phy(phydev); + return 0; +} + +int board_init(void) +{ + sc5xx_enable_rgmii(); + return 0; +} diff --git a/board/adi/sc573-ezlite/sc573-ezlite.env b/board/adi/sc573-ezlite/sc573-ezlite.env new file mode 100644 index 00000000000..e1ad4f3716f --- /dev/null +++ b/board/adi/sc573-ezlite/sc573-ezlite.env @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later+ */ +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +adi_image_offset=0xe0000 +loadaddr=CONFIG_SC5XX_LOADADDR + +#define USE_NFS +#define USE_SPI +#define USE_RAM +#define USE_MMC +#define USE_USB + +#include diff --git a/configs/sc573-ezkit_defconfig b/configs/sc573-ezkit_defconfig deleted file mode 100644 index 4320c73fd39..00000000000 --- a/configs/sc573-ezkit_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_ARM_CACHE_WRITETHROUGH=y -CONFIG_ARCH_SC5XX=y -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SPL_GPIO=y -CONFIG_DM_GPIO=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 -CONFIG_SPL_SERIAL=y -CONFIG_SC5XX_LOADADDR=0x83000000 -CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 -CONFIG_CGU0_CLKOUTSEL=7 -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ramboot" -CONFIG_SYS_CBSIZE=512 -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_I2C=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_ELF is not set -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -# CONFIG_CMD_PINMUX is not set -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_SYS_DISABLE_AUTOLOAD=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_DNS=y -CONFIG_CMD_MII=y -# CONFIG_CMD_MDIO is not set -CONFIG_CMD_PING=y -CONFIG_CMD_WGET=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_ENV_OVERWRITE=y -CONFIG_USE_HOSTNAME=y -CONFIG_HOSTNAME="sc573-ezkit" -CONFIG_NET_RETRY_COUNT=20 -CONFIG_IP_DEFRAG=y -CONFIG_SPL_CLK=y -CONFIG_SPL_CLK_CCF=y -CONFIG_GPIO_HOG=y -CONFIG_SPL_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y -CONFIG_MCP230XX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_GPIO=y -CONFIG_SYS_I2C_ADI=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_SNPS=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_DW_ALTDESCRIPTOR=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_ADI_SPI3=y -CONFIG_SPL_TIMER=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_SC5XX=y -CONFIG_USB_MUSB_PIO_ONLY=y -CONFIG_USB_STORAGE=y -CONFIG_FAT_WRITE=y -# CONFIG_REGEX is not set diff --git a/configs/sc573-ezlite_defconfig b/configs/sc573-ezlite_defconfig new file mode 100644 index 00000000000..f6305451c27 --- /dev/null +++ b/configs/sc573-ezlite_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_ARM_CACHE_WRITETHROUGH=y +CONFIG_ARCH_SC5XX=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SPL_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_SERIAL=y +CONFIG_SC5XX_LOADADDR=0x83000000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_CGU0_CLKOUTSEL=7 +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ramboot" +CONFIG_SYS_CBSIZE=512 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_I2C=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_MII=y +# CONFIG_CMD_MDIO is not set +CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="sc573-ezlite" +CONFIG_NET_RETRY_COUNT=20 +CONFIG_IP_DEFRAG=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_MCP230XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_ADI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ADI_SPI3=y +CONFIG_SPL_TIMER=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_SC5XX=y +CONFIG_USB_MUSB_PIO_ONLY=y +CONFIG_USB_STORAGE=y +CONFIG_FAT_WRITE=y +# CONFIG_REGEX is not set diff --git a/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml b/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml index df976c7ae73..ae3b5e6092a 100644 --- a/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml +++ b/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml @@ -18,7 +18,7 @@ properties: oneOf: - description: SC57X Series Boards items: - - const: adi,sc573-ezkit + - const: adi,sc573-ezlite - const: adi,sc57x - description: SC58X Series Boards diff --git a/include/configs/sc573-ezkit.h b/include/configs/sc573-ezkit.h deleted file mode 100644 index 42e42f8150b..00000000000 --- a/include/configs/sc573-ezkit.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -#ifndef __CONFIG_SC573_EZKIT_H -#define __CONFIG_SC573_EZKIT_H - -/* - * Memory Settings - */ -#define MEM_MT41K128M16JT -#define MEM_DMC0 - -#define CFG_SYS_SDRAM_BASE 0x82000000 -#define CFG_SYS_SDRAM_SIZE 0xe000000 - -#endif diff --git a/include/configs/sc573-ezlite.h b/include/configs/sc573-ezlite.h new file mode 100644 index 00000000000..590a8f06fb5 --- /dev/null +++ b/include/configs/sc573-ezlite.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +#ifndef __CONFIG_SC573_EZLITE_H +#define __CONFIG_SC573_EZLITE_H + +/* + * Memory Settings + */ +#define MEM_MT41K128M16JT +#define MEM_DMC0 + +#define CFG_SYS_SDRAM_BASE 0x82000000 +#define CFG_SYS_SDRAM_SIZE 0xe000000 + +#endif -- cgit v1.3.1 From 4f8d6c8f417cbaf32585f2969bdccb0be480c18d Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 14:22:08 +0800 Subject: imx: Remove hardcoded watchdog base address macros The watchdog base addresses are now obtained from the devicetree via ofnode_* functions. Remove the hardcoded macro definitions as they are no longer needed. Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 -- arch/arm/include/asm/arch-imx9/imx-regs.h | 9 --------- include/configs/imx8ulp_evk.h | 2 -- include/configs/imx91_evk.h | 2 -- include/configs/imx91_frdm.h | 2 -- include/configs/imx93_evk.h | 3 --- include/configs/imx93_frdm.h | 3 --- include/configs/imx93_qsb.h | 2 -- include/configs/imx93_var_som.h | 3 --- include/configs/imx94_evk.h | 3 --- include/configs/imx95_evk.h | 2 -- include/configs/kontron-osm-s-mx93.h | 2 -- include/configs/mx7ulp_com.h | 3 --- include/configs/mx7ulp_evk.h | 3 --- include/configs/phycore_imx91_93.h | 3 --- include/configs/toradex-smarc-imx95.h | 2 -- 16 files changed, 46 deletions(-) (limited to 'include/configs') diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index a038cc1df33..f9c5e21c14f 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -20,8 +20,6 @@ #define SIM1_BASE_ADDR 0x29290000 -#define WDG3_RBASE 0x292a0000UL - #define SIM_SEC_BASE_ADDR 0x2802B000 #define CGC1_SOSCDIV_ADDR 0x292C0108 diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 2d084e5227a..fbf2e6a2b01 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -17,15 +17,6 @@ #define ANATOP_BASE_ADDR 0x44480000UL -#ifdef CONFIG_IMX94 -#define WDG3_BASE_ADDR 0x49220000UL -#define WDG4_BASE_ADDR 0x49230000UL -#else -#define WDG3_BASE_ADDR 0x42490000UL -#define WDG4_BASE_ADDR 0x424a0000UL -#endif -#define WDG5_BASE_ADDR 0x424b0000UL - #define GPIO2_BASE_ADDR 0x43810000UL #define GPIO3_BASE_ADDR 0x43820000UL #define GPIO4_BASE_ADDR 0x43840000UL diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index edfd6f70815..b4f80fb944b 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -30,6 +30,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_RBASE #endif diff --git a/include/configs/imx91_evk.h b/include/configs/imx91_evk.h index 9c5014fd0a5..13918e2b873 100644 --- a/include/configs/imx91_evk.h +++ b/include/configs/imx91_evk.h @@ -16,6 +16,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx91_frdm.h b/include/configs/imx91_frdm.h index 6d051ed88a5..480b3fb477a 100644 --- a/include/configs/imx91_frdm.h +++ b/include/configs/imx91_frdm.h @@ -20,6 +20,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index ffd72a38bcb..67774f54790 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -26,7 +26,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h index c98c10774cb..bcea360b399 100644 --- a/include/configs/imx93_frdm.h +++ b/include/configs/imx93_frdm.h @@ -20,7 +20,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h index a7b94f7ab57..350f094c2a6 100644 --- a/include/configs/imx93_qsb.h +++ b/include/configs/imx93_qsb.h @@ -16,6 +16,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h index 9dc10aea407..6a425e6d1ea 100644 --- a/include/configs/imx93_var_som.h +++ b/include/configs/imx93_var_som.h @@ -38,7 +38,4 @@ #define CFG_SYS_FSL_USDHC_NUM 2 -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h index f93c3c4e4a8..2623c13db06 100644 --- a/include/configs/imx94_evk.h +++ b/include/configs/imx94_evk.h @@ -18,7 +18,4 @@ #define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */ #define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx95_evk.h b/include/configs/imx95_evk.h index 3d22740b3f4..1fdc9ce21ef 100644 --- a/include/configs/imx95_evk.h +++ b/include/configs/imx95_evk.h @@ -23,6 +23,4 @@ #define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB (Totally 16GB) */ #endif -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/kontron-osm-s-mx93.h b/include/configs/kontron-osm-s-mx93.h index ab2b42298c8..fed75e6fa12 100644 --- a/include/configs/kontron-osm-s-mx93.h +++ b/include/configs/kontron-osm-s-mx93.h @@ -25,6 +25,4 @@ #define CFG_MXC_USB_FLAGS 0 #endif -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif /* __KONTRON_MX93_CONFIG_H */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index d27e9d2eaa1..501c3059cc3 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -15,9 +15,6 @@ #include "imx7ulp_spl.h" #endif -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG1_RBASE - #define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ /* UART */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index ace1eee70cf..21dbec837f0 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -11,9 +11,6 @@ #include #include -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG1_RBASE - #define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ /* UART */ diff --git a/include/configs/phycore_imx91_93.h b/include/configs/phycore_imx91_93.h index 02fa1d9b274..d1bf086546f 100644 --- a/include/configs/phycore_imx91_93.h +++ b/include/configs/phycore_imx91_93.h @@ -22,7 +22,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif /* __PHYCORE_IMX91_93_H */ diff --git a/include/configs/toradex-smarc-imx95.h b/include/configs/toradex-smarc-imx95.h index e1aebd70af2..8a880b96503 100644 --- a/include/configs/toradex-smarc-imx95.h +++ b/include/configs/toradex-smarc-imx95.h @@ -19,6 +19,4 @@ #define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) #define PHYS_SDRAM_2_SIZE SZ_6G -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif -- cgit v1.3.1 From 0b9897e7a41cb6d035956b5c7ca004be84feaa17 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 19 May 2026 14:24:06 +0200 Subject: board: tq: add TQMa6UL[L]x[L] SOM and MBa6ULx baseboard The TQMa6UL[L]x is a family of SoMs based on the i.MX6UL[L] SoCs. They are available either with board connectors or as LGA packages with solder balls. Add Support for the SoM and its combination with our MBa6ULx carrier board. For use with the MBa6ULx carrier board, the LGA variant is soldered onto an adapter board. Signed-off-by: Nora Schiffer Signed-off-by: Max Merchel --- arch/arm/mach-imx/mx6/Kconfig | 21 ++++ board/tq/MAINTAINERS | 2 +- board/tq/tqma6ul/Kconfig | 114 ++++++++++++++++++++ board/tq/tqma6ul/Makefile | 16 +++ board/tq/tqma6ul/spl.c | 128 +++++++++++++++++++++++ board/tq/tqma6ul/spl_mba6ul.c | 177 +++++++++++++++++++++++++++++++ board/tq/tqma6ul/spl_tqma6ul_ram.c | 209 +++++++++++++++++++++++++++++++++++++ board/tq/tqma6ul/tqma6ul.c | 184 ++++++++++++++++++++++++++++++++ board/tq/tqma6ul/tqma6ul.cfg | 23 ++++ board/tq/tqma6ul/tqma6ul.env | 47 +++++++++ board/tq/tqma6ul/tqma6ul.h | 25 +++++ board/tq/tqma6ul/tqma6ul_mba6ul.c | 138 ++++++++++++++++++++++++ doc/board/tq/index.rst | 1 + doc/board/tq/tqma6ul.rst | 105 +++++++++++++++++++ include/configs/tqma6ul.h | 53 ++++++++++ include/configs/tqma6ul_mba6ul.h | 19 ++++ 16 files changed, 1261 insertions(+), 1 deletion(-) create mode 100644 board/tq/tqma6ul/Kconfig create mode 100644 board/tq/tqma6ul/Makefile create mode 100644 board/tq/tqma6ul/spl.c create mode 100644 board/tq/tqma6ul/spl_mba6ul.c create mode 100644 board/tq/tqma6ul/spl_tqma6ul_ram.c create mode 100644 board/tq/tqma6ul/tqma6ul.c create mode 100644 board/tq/tqma6ul/tqma6ul.cfg create mode 100644 board/tq/tqma6ul/tqma6ul.env create mode 100644 board/tq/tqma6ul/tqma6ul.h create mode 100644 board/tq/tqma6ul/tqma6ul_mba6ul.c create mode 100644 doc/board/tq/tqma6ul.rst create mode 100644 include/configs/tqma6ul.h create mode 100644 include/configs/tqma6ul_mba6ul.h (limited to 'include/configs') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d198d9932f4..7ed4b24b751 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -633,6 +633,26 @@ config TARGET_TQMA6 imply CMD_SF imply CMD_DM +config TARGET_TQMA6UL + bool "TQ-Systems TQMa6UL[L]x" + depends on MX6UL || MX6ULL + select TQ_COMMON_SOM + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select OF_SYSTEM_SETUP + select DM + select DM_I2C + select SUPPORT_SPL + select SPL_SEPARATE_BSS if SPL + imply DM_GPIO + imply DM_MMC + imply DM_SPI if SPI + imply DM_SPI_FLASH if SPI + imply SPI + help + TQMa6UL[L]x is a TQ SoM with i.MX6UL/i.MX6ULL CPU + The SoM can be used on various baseboards. + config TARGET_UDOO bool "udoo" depends on MX6QDL @@ -739,6 +759,7 @@ source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tq/tqma6/Kconfig" +source "board/tq/tqma6ul/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS index b31c5793432..a04a36ba415 100644 --- a/board/tq/MAINTAINERS +++ b/board/tq/MAINTAINERS @@ -1,4 +1,4 @@ -TQMA6 +TQMA6 / TQMA6UL / TQMA6ULxL / TQMA6ULL / TQMA6ULLxL M: Max Merchel L: u-boot@ew.tq-group.com S: Maintained diff --git a/board/tq/tqma6ul/Kconfig b/board/tq/tqma6ul/Kconfig new file mode 100644 index 00000000000..5d85c68b359 --- /dev/null +++ b/board/tq/tqma6ul/Kconfig @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH , +# D-82229 Seefeld, Germany. +# Author: Marco Felsch, Markus Niebel, Max Merchel +# + +if TARGET_TQMA6UL + +config SYS_BOARD + default "tqma6ul" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma6ul_mba6ul" if MBA6UL + +choice + prompt "TQMa6UL module variant" + default TQMA6UL_VARIANT_STANDARD + help + Select the variant of the TQMa6UL SoM module being used. + By default, the variant with board-to-board connectors is used. + +config TQMA6UL_VARIANT_STANDARD + bool "standard module with board connector" + help + Select for SoM variant connector + with board to board connectors + +config TQMA6UL_VARIANT_LGA + bool "LGA module with solder balls" + help + Select for SoM variant LGA + with solder balls + +endchoice + +config TQMA6UL_RAM_256M + bool + +config TQMA6UL_RAM_512M + bool + +choice + prompt "TQMa6UL RAM configuration" + default TQMA6UL_RAM_MULTI + help + Select RAM configuration. Normally use default here but for + specific setup it is possible to use a single RAM size. + +config TQMA6UL_RAM_MULTI + bool "TQMa6ULx with 256/512 MB RAM - Single image" + select TQMA6UL_RAM_256M + select TQMA6UL_RAM_512M + help + Build a single U-Boot solely for variants + with 256/512 MB RAM. + +config TQMA6UL_RAM_SINGLE_256M + bool "TQMa6UL with 256 MB RAM" + select TQMA6UL_RAM_256M + help + Build U-Boot solely for variants + with 256 MB RAM. + +config TQMA6UL_RAM_SINGLE_512M + bool "TQMa6UL with 512 MB RAM" + select TQMA6UL_RAM_512M + help + Build U-Boot solely for variants + with 512 MB RAM. + +endchoice + +choice + prompt "TQMa6UL base board variant" + default MBA6UL + help + Select the baseboard variant for the TQMa6UL module. + By default the MBA6UL starterkit is used. + +config MBA6UL + bool "TQMa6UL on MBa6ULx Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SDMMC + select SYSINFO + select SYSINFO_TQ_EEPROM + select I2C_EEPROM + select MISC + select MXC_UART + imply DM_ETH + imply DM_GPIO + imply DM_MMC + imply DM_SERIAL + imply DM_SPI + imply OF_UPSTREAM + imply PHYLIB + imply PHY_SMSC + imply USB + imply USB_STORAGE + help + Select the MBa6ULx starterkit. + This is the default base board. + +endchoice + +config IMX_CONFIG + default "board/tq/tqma6ul/tqma6ul.cfg" + +source "board/tq/common/Kconfig" + +endif diff --git a/board/tq/tqma6ul/Makefile b/board/tq/tqma6ul/Makefile new file mode 100644 index 00000000000..f45ed4a15f6 --- /dev/null +++ b/board/tq/tqma6ul/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2021-2026 TQ-Systems GmbH , +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Matthias Schiffer, Max Merchel +# + +obj-y := tqma6ul.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += spl_tqma6ul_ram.o +obj-$(CONFIG_MBA6UL) += spl_mba6ul.o +else +obj-$(CONFIG_MBA6UL) += tqma6ul_mba6ul.o +endif diff --git a/board/tq/tqma6ul/spl.c b/board/tq/tqma6ul/spl.c new file mode 100644 index 00000000000..71c5134c4f6 --- /dev/null +++ b/board/tq/tqma6ul/spl.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +/* eMMC on USDHC2 */ +static const iomux_v3_cfg_t tqma6ul_usdhc2_pads[] = { + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg tqma6ul_usdhc2_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + /* eMMC/uSDHC2 is always present */ + ret = 1; + else + ret = tq_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + /* eMMC/uSDHC2 is never WP */ + ret = 0; + else + ret = tq_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6ul_usdhc2_pads, + ARRAY_SIZE(tqma6ul_usdhc2_pads)); + tqma6ul_usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + if (fsl_esdhc_initialize(bis, &tqma6ul_usdhc2_cfg)) + printf("Warning: failed to initialize eMMC dev\n"); + + tq_bb_board_mmc_init(bis); + + return 0; +} + +void board_init_f(ulong dummy) +{ + /* setup clock gating */ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup AXI */ + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + tq_som_ram_init(); +} diff --git a/board/tq/tqma6ul/spl_mba6ul.c b/board/tq/tqma6ul/spl_mba6ul.c new file mode 100644 index 00000000000..55beeac8fc9 --- /dev/null +++ b/board/tq/tqma6ul/spl_mba6ul.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +#define GPIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static const iomux_v3_cfg_t mba6ul_uart_pads[] = { + NEW_PAD_CTRL(MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, UART_PAD_CTRL), +}; + +static void mba6ul_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6ul_uart_pads, + ARRAY_SIZE(mba6ul_uart_pads)); +} + +/* SD card on USDHC1 */ +static const iomux_v3_cfg_t mba6ul_usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* WP */ + MX6_PAD_UART1_CTS_B__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_WP_GPIO IMX_GPIO_NR(1, 18) + +static struct fsl_esdhc_cfg mba6ul_usdhc1_cfg = { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, +}; + +int tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = !gpio_get_value(USDHC1_CD_GPIO); + + return ret; +} + +int tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = gpio_get_value(USDHC1_WP_GPIO); + + return ret; +} + +int tq_bb_board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba6ul_usdhc1_pads, + ARRAY_SIZE(mba6ul_usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1-cd"); + gpio_request(USDHC1_WP_GPIO, "usdhc1-wp"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_input(USDHC1_WP_GPIO); + + mba6ul_usdhc1_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + if (fsl_esdhc_initialize(bis, &mba6ul_usdhc1_cfg)) + puts("Warning: failed to initialize SD card\n"); + + return 0; +} + +int board_early_init_f(void) +{ + tq_bb_board_early_init_f(); + + mba6ul_setup_iomuxc_uart(); + + return 0; +} + +/* + * This is done per baseboard to allow different implementations + */ +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 imx6_bmode = (bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; + + /* USB boot */ + if (spl_boot_device() == BOOT_DEVICE_BOARD) { + printf("USB\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + return; + } + + switch (imx6_bmode) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC2 */ + printf("SD\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC - BOOT_DEVICE_MMC1 */ + printf("eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case IMX6_BMODE_QSPI: + /* QSPI - BOOT_DEVICE_SPI */ + printf("QSPI\n"); + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + case IMX6_BMODE_SERIAL_ROM: + /* SERIAL_ROM - BOOT_DEVICE_BOARD */ + printf("Serial ROM\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + default: + printf("WARNING: unknown boot device, fallback to eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + } +} + +int board_fit_config_name_match(const char *name) +{ + /* Longest FDT name */ + char dt[] = "imx6ull-tqma6ull2l-mba6ulx"; + enum tqma6ul_som_type somtype; + + somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx"); + if (somtype == tqma6ul_som_type_unknown) + return -EINVAL; + + if (!strcmp(name, dt)) + return -EINVAL; + + printf("Device tree: %s\n", name); + return 0; +} diff --git a/board/tq/tqma6ul/spl_tqma6ul_ram.c b/board/tq/tqma6ul/spl_tqma6ul_ram.c new file mode 100644 index 00000000000..c5d50890702 --- /dev/null +++ b/board/tq/tqma6ul/spl_tqma6ul_ram.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_som.h" + +static void tqma6ul_init_ddr_controller(u32 size) +{ + /* TQMa6ul DDR config */ + + /* reset DDR via Chip Select 0*/ + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x03180000); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000); + + debug("SPL: tqma6ul ddr iomux ....\n"); + + /* DDR IO TYPE: */ + tq_som_init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000); + tq_som_init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000); + /* CLOCK: */ + tq_som_init_write_reg(MX6_IOM_DRAM_SDCLK_0, 0x00000030); + /* Control: */ + tq_som_init_write_reg(MX6_IOM_DRAM_CAS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_RAS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000); + tq_som_init_write_reg(MX6_IOM_DRAM_SDODT0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDODT1, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_CTLDS, 0x00000030); + /* Data Strobes: */ + tq_som_init_write_reg(MX6_IOM_DDRMODE_CTL, 0x00020000); + tq_som_init_write_reg(MX6_IOM_DRAM_SDQS0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDQS1, 0x00000030); + /* Data: */ + tq_som_init_write_reg(MX6_IOM_GRP_DDRMODE, 0x00020000); + tq_som_init_write_reg(MX6_IOM_GRP_B0DS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_B1DS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030); + + debug("tqma6ul ddr controller registers ....\n"); + + /* MMDC_MDSCR - MMDC Core Special Command Register */ + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000); + + debug("tqma6ul ddr calibrations ....\n"); + + /* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */ + tq_som_init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003); + + switch (size) { + case SZ_512M: + if (IS_ENABLED(CONFIG_MX6UL)) { + debug("tqma6ul ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41580150); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E52); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4A); + + } else if (IS_ENABLED(CONFIG_MX6ULL)) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) { + debug("tqma6ull ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00090009); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x4140013C); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E26); + + } else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) { + debug("tqma6ull ddr calibration lga variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00050009); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41340130); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E28); + + } else { + pr_err("invalid/unsupported SoM variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */ + } else { + pr_err("ERROR: invalid/unsupported CPU variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_MX6UL) */ + break; + case SZ_256M: + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) { + debug("tqma6ul ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41480144); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E54); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E48); + + } else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) { + debug("tqma6ul ddr calibration lga variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00130003); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41540154); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40405050); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4C); + + } else { + pr_err("ERROR: invalid/unsupported SoM variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */ + break; + default: + pr_err("ERROR: invalid/unsupported RAM size ....\n"); + hang(); + break; + } + + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333); + + tq_som_init_write_reg(0x021B082C, 0xf3333333); /* MMDC_MPWRDQBY0DL */ + tq_som_init_write_reg(0x021B0830, 0xf3333333); /* MMDC_MPWRDQBY1DL */ + tq_som_init_write_reg(0x021B08C0, 0x00921012); /* MMDC_MPDCCR */ + + /* + * Complete calibration by forced measurement: + */ + tq_som_init_write_reg(MX6_MMDC_P0_MPMUR0, 0x00000800); + tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002002D); + + debug("tqma6ul ddr mmdc ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MDOTC, 0x00333030); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG0, 0x676B52F3); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB66D8B63); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB); + tq_som_init_write_reg(MX6_MMDC_P0_MDMISC, 0x00201740); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000); + tq_som_init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2); + tq_som_init_write_reg(MX6_MMDC_P0_MDOR, 0x006B1023); + + switch (size) { + case SZ_512M: + tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x0000004F); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x84180000); + break; + case SZ_256M: + tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x00000047); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000); + break; + default: + hang(); + break; + } + + debug("tqma6ul ddr cs0 ....\n"); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x02008032); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040); + tq_som_init_write_reg(MX6_MMDC_P0_MDREF, 0x00000800); + tq_som_init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00000227); + tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002552D); + tq_som_init_write_reg(MX6_MMDC_P0_MAPSR, 0x00011006); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00000000); +} + +void tq_som_ram_init(void) +{ + int i; + /* RAM sizes need to be in descending order */ + static const u32 ram_sizes[] = { +#if IS_ENABLED(CONFIG_TQMA6UL_RAM_512M) + SZ_512M, +#endif +#if IS_ENABLED(CONFIG_TQMA6UL_RAM_256M) + SZ_256M, +#endif + }; + + if (!is_mx6ul() && !is_mx6ull()) { + pr_err("ERROR: Not running on TQMa6UL[L]\n"); + hang(); + } + + for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) { + tqma6ul_init_ddr_controller(ram_sizes[i]); + if (tq_som_ram_check_size(ram_sizes[i])) + break; + } + + if (i < ARRAY_SIZE(ram_sizes)) { + debug("SPL: tqma6ul ddr init done ...\n"); + } else { + pr_err("ERROR: Invalid DDR RAM size\n"); + hang(); + } +} diff --git a/board/tq/tqma6ul/tqma6ul.c b/board/tq/tqma6ul/tqma6ul.c new file mode 100644 index 00000000000..999396f573d --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +int tq_bb_board_early_init_f(void) +{ + if (CONFIG_IS_ENABLED(FSL_QSPI)) + enable_qspi_clk(0); + + return 0; +} + +/** + * Checks if CPU (imx6ul or ima6ull) matches the one set for the image. + */ +static const char *check_cpu_variant(void) +{ + const char *cpu; + + if (is_mx6ul()) { + cpu = "ul"; + if (!IS_ENABLED(CONFIG_MX6UL)) + printf("*** ERROR: image not compiled for i.MX6UL!\n"); + } else if (is_mx6ull()) { + cpu = "ull"; + if (!IS_ENABLED(CONFIG_MX6ULL)) + printf("*** ERROR: image not compiled for i.MX6ULL!\n"); + } else { + printf("unknown CPU\n"); + return NULL; + } + + return cpu; +} + +/** + * Checks configuration for TQMa6UL SoM module variant. + */ +enum tqma6ul_som_type check_tqma6ul_variant(void) +{ + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return tqma6ul_som_type_ca; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return tqma6ul_som_type_lga; + + printf("unknown SoM variant\n"); + + return tqma6ul_som_type_unknown; +} + +/** + * Adjusts device tree name based on CPU variant. + */ +enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb) +{ + const char *tqma6ul_cpu, *tqma6ul_variant; + enum tqma6ul_som_type somtype; + u8 mx6ul_variant; + + tqma6ul_cpu = check_cpu_variant(); + if (!tqma6ul_cpu) + return tqma6ul_som_type_unknown; + + /* MX6UL1 vs MX6UL2 */ + mx6ul_variant = check_module_fused(MODULE_ENET2) ? 1 : 2; + + somtype = check_tqma6ul_variant(); + switch (somtype) { + case tqma6ul_som_type_ca: + tqma6ul_variant = ""; + break; + case tqma6ul_som_type_lga: + tqma6ul_variant = "l"; + break; + default: + return tqma6ul_som_type_unknown; + } + + snprintf(dt, dtsize, "imx6%s-tqma6%s%u%s-%s", + tqma6ul_cpu, tqma6ul_cpu, mx6ul_variant, tqma6ul_variant, mb); + + return somtype; +} + +#if !IS_ENABLED(CONFIG_SPL_BUILD) +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +const char *tq_som_get_modulename(void) +{ + if (is_mx6ul()) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return "TQMa6ULx"; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return "TQMa6ULxL"; + } + + if (is_mx6ull()) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return "TQMa6ULLx"; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return "TQMa6ULLxL"; + } + + return "Unknown"; +} + +int checkboard(void) +{ + printf("Board: %s on %s\n", tq_som_get_modulename(), + tq_bb_get_boardname()); + + return tq_bb_checkboard(); +} + +#if IS_ENABLED(CONFIG_CMD_BMODE) +static const struct boot_mode tqma6ul_board_boot_modes[] = { + /* 4 bit bus width */ + {"sd", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int tq_bb_board_late_init(void) +{ + if (IS_ENABLED(CONFIG_CMD_BMODE)) + add_board_boot_modes(tqma6ul_board_boot_modes); + + env_set_runtime("board_name", tq_som_get_modulename()); + + return 0; +} + +int tq_bb_checkboard(void) +{ + if (is_mx6ul()) { + if (!IS_ENABLED(CONFIG_MX6UL)) + printf("*** ERROR: image not compiled for i.MX6UL!\n"); + } else if (is_mx6ull()) { + if (!IS_ENABLED(CONFIG_MX6ULL)) + printf("*** ERROR: image not compiled for i.MX6ULL!\n"); + } else { + printf("*** ERROR: unknown CPU variant!\n"); + } + + return 0; +} + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int tq_bb_ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/tq/tqma6ul/tqma6ul.cfg b/board/tq/tqma6ul/tqma6ul.cfg new file mode 100644 index 00000000000..42821ae5c7a --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.cfg @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +#if IS_ENABLED(CONFIG_QSPI_BOOT) +BOOT_FROM qspi +#else +BOOT_FROM sd +#endif + +#if IS_ENABLED(CONFIG_IMX_HAB) +CSF CONFIG_CSF_SIZE +#endif diff --git a/board/tq/tqma6ul/tqma6ul.env b/board/tq/tqma6ul/tqma6ul.env new file mode 100644 index 00000000000..fa172caca23 --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6UL environment + */ + +#include + +board=tqma6ul +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6UL_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6UL_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6UL_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth1 +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6UL_INITRD_ADDRESS +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6UL_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6UL_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6UL_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6UL_SPI_UBOOT_START +uboot_spi_size=TQMA6UL_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6UL_MMC_UBOOT_SECTOR_START TQMA6UL_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/board/tq/tqma6ul/tqma6ul.h b/board/tq/tqma6ul/tqma6ul.h new file mode 100644 index 00000000000..595edc89e19 --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +enum tqma6ul_som_type { + /* unknown */ + tqma6ul_som_type_unknown, + /* connector module */ + tqma6ul_som_type_ca, + /* LGA Variant */ + tqma6ul_som_type_lga, +}; + +/** + * Checks configuration for TQMa6UL SoM module variant + */ +enum tqma6ul_som_type check_tqma6ul_variant(void); + +/** + * Adjusts device tree name based on CPU variant. + */ +enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb); diff --git a/board/tq/tqma6ul/tqma6ul_mba6ul.c b/board/tq/tqma6ul/tqma6ul_mba6ul.c new file mode 100644 index 00000000000..be78060cbda --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul_mba6ul.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +const char *tq_bb_get_boardname(void) +{ + return "MBa6ULx"; +} + +int board_early_init_f(void) +{ + return tq_bb_board_early_init_f(); +} + +static void mba6ul_setup_eth(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (check_module_fused(MODULE_ENET1)) { + printf("FEC1: disabled by fuses\n"); + } else { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + enable_fec_anatop_clock(0, ENET_50MHZ); + } + + if (check_module_fused(MODULE_ENET2)) { + printf("FEC2: disabled by fuses\n"); + } else { + /* + * Use 50M anatop loopback REF_CLK1 for ENET2, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + enable_fec_anatop_clock(1, ENET_50MHZ); + } + + enable_enet_clk(1); +} + +int board_init(void) +{ + return 0; +} + +static void mba6ul_set_fdt_file(void) +{ + /* Longest FDT name */ + char dt[] = "imx6ull-tqma6ull2l-mba6ulx.dtb"; + enum tqma6ul_som_type somtype; + + if (!env_get("fdtfile")) { + somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx.dtb"); + if (somtype == tqma6ul_som_type_unknown) + return; + + env_set_runtime("fdtfile", dt); + } +} + +int board_late_init(void) +{ + unsigned int bmode = + (imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; + + tq_bb_board_late_init(); + + printf("Boot: "); + + switch (bmode) { + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + printf("eMMC\n"); + env_set_runtime("boot_dev", "mmc"); + board_late_mmc_env_init(); + break; + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + printf("SD\n"); + env_set_runtime("boot_dev", "mmc"); + board_late_mmc_env_init(); + break; + case IMX6_BMODE_QSPI: + case IMX6_BMODE_NOR: + printf("QSPI\n"); + env_set_runtime("boot_dev", "qspi"); + break; + default: + printf("unhandled boot device %u\n", bmode); + } + + mba6ul_set_fdt_file(); + mba6ul_setup_eth(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + unsigned int port = (imx6_src_get_boot_mode() >> 11) & 0x3; + + switch (port) { + case 0: + /* SDHC1 - SD card on MBa6ULx */ + return 1; + + default: + /* Return eMMC device otherwise */ + return 0; + } +} + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return tq_bb_ft_board_setup(blob, bd); +} +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ diff --git a/doc/board/tq/index.rst b/doc/board/tq/index.rst index d6dc6101c2c..775957474e7 100644 --- a/doc/board/tq/index.rst +++ b/doc/board/tq/index.rst @@ -9,4 +9,5 @@ TQ-Systems .. toctree:: :maxdepth: 2 + tqma6ul tqma7 diff --git a/doc/board/tq/tqma6ul.rst b/doc/board/tq/tqma6ul.rst new file mode 100644 index 00000000000..2b346715642 --- /dev/null +++ b/doc/board/tq/tqma6ul.rst @@ -0,0 +1,105 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later or CC-BY-4.0 + +.. Copyright (c) 2017-2025 TQ-Systems GmbH , +.. D-82229 Seefeld, Germany. + +######################################## +U-Boot for the TQ-Systems TQMa6x modules +######################################## + +The following hardware revisions are supported: + +Modules: + ++------------+----------+ +| TQMa6ULx | REV.030x | ++------------+----------+ +| TQMa6ULLx | REV.030x | ++------------+----------+ +| TQMa6ULxL | REV.030x | ++------------+----------+ +| TQMa6ULLxL | REV.030x | ++------------+----------+ + +Mainboards: + ++----------+----------+ +| MBa6ULx | REV.020x | ++----------+----------+ + +Hardware on modules TQMa6ULx, TQMa6ULxL, TQMa6ULLx and TQMa6ULLxL + +- eMMC +- RTC +- PMIC +- SPI-NOR (optional) +- EEPROM +- Temperature sensor +- RAM (256 MiB / 512 MiB) + +Supported hardware on Starterkit MBa6ULx: + +- 2 Ethernet PHY connected to FEC0 / FEC1 (usage depends on CPU) +- SD-card slot +- UART +- USB + +Note: To change the Ethernet port to use for networking functionality, use the +U-Boot generic environment variable ``ethact``. + +.. code-block:: bash + + setenv ethact + +*********** +Boot source +*********** + +- SD/eMMC +- USB/SDP (with NXP UUU tool) +- SPI NOR (functional but requires additional prepended NXP header. + Not supported in U-Boot.) + +******** +Building +******** + +To build U-Boot for the TQ-Systems TQMa6L modules: + +.. code-block:: bash + + make ___defconfig + make + + +**som** is a placeholder for the module base variant: + ++------------+------------+----------------+ +| tqma6ulx | TQMa6ULx | i.MX6UL | ++------------+------------+----------------+ +| tqma6ullx | TQMa6ULLx | i.MX6ULL | ++------------+------------+----------------+ +| tqma6ulxl | TQMa6ULxL | i.MX6UL (lga) | ++------------+------------+----------------+ +| tqma6ullxl | TQMa6ULLxL | i.MX6ULL (lga) | ++------------+------------+----------------+ + +**baseboard** is a placeholder for the mainboard to compile for: + ++----------+----------+ +| mba6ul | MBa6ULx | ++----------+----------+ + +**boot** is a placeholder for the boot device: + ++------+---------+ +| mmc | SD/eMMC | ++------+---------+ +| spi | SPI-NOR | ++------+---------+ + +************ +Support Wiki +************ + +See `TQ Embedded Wiki for TQMa6ulx `_. diff --git a/include/configs/tqma6ul.h b/include/configs/tqma6ul.h new file mode 100644 index 00000000000..89bd8102500 --- /dev/null +++ b/include/configs/tqma6ul.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer, Max Merchel + * + * Configuration settings for the TQ-Systems TQMa6UL[L]x[L] SOM family. + */ + +#ifndef __TQMA6UL_CONFIG_H +#define __TQMA6UL_CONFIG_H + +#include + +#include "mx6_common.h" + +#define TQMA6UL_MMC_UBOOT_SECTOR_START 0x2 +#define TQMA6UL_MMC_UBOOT_SECTOR_COUNT 0x7fe + +#define TQMA6UL_SPI_FLASH_SECTOR_SIZE SZ_64K +#define TQMA6UL_SPI_UBOOT_START SZ_4K +#define TQMA6UL_SPI_UBOOT_SIZE 0xf0000 + +/* 128 MiB offset as suggested in ARM related Linux docs */ +#define TQMA6UL_FDT_ADDRESS 0x88000000 + +/* 256KiB above TQMA6UL_FDT_ADDRESS (TQMA6UL_FDT_ADDRESS + SZ_256K) */ +#define TQMA6UL_FDT_OVERLAY_ADDR 0x88040000 + +/* 16MiB above TQMA6UL_FDT_ADDRESS (TQMA6UL_FDT_ADDRESS + SZ_16M) */ +#define TQMA6UL_INITRD_ADDRESS 0x89000000 + +#ifndef __ASSEMBLY__ +static_assert(TQMA6UL_FDT_OVERLAY_ADDR == (TQMA6UL_FDT_ADDRESS + SZ_256K)); +static_assert(TQMA6UL_INITRD_ADDRESS == (TQMA6UL_FDT_ADDRESS + SZ_16M)); +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE + +/* u-boot.img base address for SPI-NOR boot */ +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + SZ_4K + CONFIG_SPL_PAD_TO) + +#define CFG_SYS_INIT_SP_OFFSET \ + (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_ADDR \ + (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET) + +#endif /* __TQMA6UL_CONFIG_H */ diff --git a/include/configs/tqma6ul_mba6ul.h b/include/configs/tqma6ul_mba6ul.h new file mode 100644 index 00000000000..b7a31b5ce26 --- /dev/null +++ b/include/configs/tqma6ul_mba6ul.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Nora Schiffer, Max Merchel + * + * Configuration settings for the TQ-Systems MBa6ULx carrier board for + * TQMa6UL[L]x[L] SOM family. + */ + +#ifndef __CONFIG_TQMA6UL_MBA6UL_H +#define __CONFIG_TQMA6UL_MBA6UL_H + +#include "tqma6ul.h" + +#define CFG_MXC_UART_BASE UART1_BASE +#define CFG_SYS_FSL_ESDHC_ADDR 0 + +#endif /* __CONFIG_TQMA6UL_MBA6UL_H */ -- cgit v1.3.1 From 818c06faa119f3101c9df24c0ef1b815c2abd929 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Thu, 14 May 2026 15:52:21 +0530 Subject: board: amd: Add capsule and FWU support Add configure_capsule_updates() supporting MMC, SD and QSPI/OSPI boot modes for DFU string generation. Add set_dfu_alt_info() for FWU multi-bank mode to generate DFU alt info from NOR flash MTD partitions. Add XILINX_BOOT_IMAGE_GUID for the capsule updatable firmware image. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260514102601.1759779-5-padmarao.begari@amd.com --- board/amd/versal2/board.c | 131 +++++++++++++++++++++++++++++++++++++++++- include/configs/amd_versal2.h | 5 ++ 2 files changed, 135 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 81daba1c5ef..ec28e60c410 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -1,17 +1,24 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ #include +#include +#include +#include #include +#include #include #include #include #include +#include +#include +#include #include #include #include @@ -26,6 +33,7 @@ #include "../../xilinx/common/board.h" #include +#include #include #include #include @@ -348,6 +356,10 @@ int board_late_init(void) int ret; u32 multiboot; + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && + !IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) + configure_capsule_updates(); + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; @@ -476,3 +488,120 @@ enum env_location env_get_location(enum env_operation op, int prio) } } #endif + +#define DFU_ALT_BUF_LEN SZ_1K + +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \ + !defined(CONFIG_FWU_MULTI_BANK_UPDATE) +static void mtd_found_part(u32 *base, u32 *size) +{ + struct mtd_info *part, *mtd; + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (!IS_ERR_OR_NULL(mtd)) { + list_for_each_entry(part, &mtd->partitions, node) { + debug("0x%012llx-0x%012llx : \"%s\"\n", + part->offset, part->offset + part->size, + part->name); + + if (*base >= part->offset && + *base < part->offset + part->size) { + debug("Found my partition: %d/%s\n", + part->index, part->name); + *base = part->offset; + *size = part->size; + break; + } + } + } +} + +void configure_capsule_updates(void) +{ + int bootseq = 0, len = 0; + u32 multiboot = versal2_multi_boot(); + u32 bootmode = versal2_get_bootmode(); + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + memset(buf, 0, DFU_ALT_BUF_LEN); + + multiboot = env_get_hex("multiboot", multiboot); + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + bootseq = mmc_get_env_dev(); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", + bootseq); + + if (multiboot) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "%04d", multiboot); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", + bootseq); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + case OSPI_MODE: + { + u32 base = multiboot * SZ_32K; + u32 size = 0x1500000; + u32 limit = size; + + mtd_found_part(&base, &limit); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw 0x%x 0x%x", + base, limit); + } + break; + default: + return; + } + + update_info.dfu_string = strdup(buf); + debug("Capsule DFU: %s\n", update_info.dfu_string); +} +#endif + +#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + int ret; + struct mtd_info *mtd; + + /* + * It is called multiple times for every image + * per bank that's why enough to set it up once. + */ + if (env_get("dfu_alt_info")) + return; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + memset(buf, 0, DFU_ALT_BUF_LEN); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} +#endif diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index fccc786219f..a07e12bd146 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -23,6 +23,11 @@ #define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } +/* GUID for capsule updatable firmware image */ +#define XILINX_BOOT_IMAGE_GUID \ + EFI_GUID(0xed9e7fcf, 0x47b3, 0x40cd, 0xb6, 0xe3, \ + 0x56, 0x5f, 0x14, 0x67, 0x6d, 0x82) + #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_ALT_INFO_RAM \ -- cgit v1.3.1 From 59e13ed8f6d8b030c6aaf7e2af77f073fecc3b30 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 19 Dec 2025 11:59:36 +1300 Subject: arm: mvebu: Add Allied Telesis x220 Add the Allied Telesis x220 board. There are a number of other variants with the same CPU block that are sold under some different brand names but the x220 was first. The x220 uses the AlleyCat3 switch chip with integrated ARMv7 CPU. Because of this it is reliant on a binary blob for the DDR training. In upstream u-boot this is replaced by an empty file. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-xp-atl-x220.dts | 162 +++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 7 ++ board/alliedtelesis/x220/.gitattributes | 1 + board/alliedtelesis/x220/.gitignore | 1 + board/alliedtelesis/x220/MAINTAINERS | 8 ++ board/alliedtelesis/x220/Makefile | 14 +++ board/alliedtelesis/x220/binary.0 | 11 +++ board/alliedtelesis/x220/kwbimage.cfg.in | 12 +++ board/alliedtelesis/x220/x220.c | 67 +++++++++++++ configs/x220_defconfig | 76 +++++++++++++++ doc/board/alliedtelesis/index.rst | 11 +++ doc/board/alliedtelesis/x220.rst | 39 ++++++++ doc/board/index.rst | 1 + include/configs/x220.h | 20 ++++ 15 files changed, 431 insertions(+) create mode 100644 arch/arm/dts/armada-xp-atl-x220.dts create mode 100644 board/alliedtelesis/x220/.gitattributes create mode 100644 board/alliedtelesis/x220/.gitignore create mode 100644 board/alliedtelesis/x220/MAINTAINERS create mode 100644 board/alliedtelesis/x220/Makefile create mode 100644 board/alliedtelesis/x220/binary.0 create mode 100644 board/alliedtelesis/x220/kwbimage.cfg.in create mode 100644 board/alliedtelesis/x220/x220.c create mode 100644 configs/x220_defconfig create mode 100644 doc/board/alliedtelesis/index.rst create mode 100644 doc/board/alliedtelesis/x220.rst create mode 100644 include/configs/x220.h (limited to 'include/configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b75f3ee4386..722a7a662b1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,6 +137,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-388-helios4.dtb \ armada-38x-controlcenterdc.dtb \ + armada-xp-atl-x220.dtb \ armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ diff --git a/arch/arm/dts/armada-xp-atl-x220.dts b/arch/arm/dts/armada-xp-atl-x220.dts new file mode 100644 index 00000000000..5b3307ed288 --- /dev/null +++ b/arch/arm/dts/armada-xp-atl-x220.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for x220 board + * + * Copyright (C) 2025 Allied Telesis Labs + */ + +/dts-v1/; +#include +#include "armada-xp-98dx3236.dtsi" +#include "mvebu-u-boot.dtsi" + +/ { + model = "x220"; + compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200"; + }; + + aliases { + i2c0 = &i2c0; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1340"; + reg = <0x68>; + }; + + adt7476a@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + sfpgpio: gpio@27 { + #address-cells = <2>; + #size-cells = <0>; + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; + + systemgpio: gpio@25 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9555"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + + nand-protect { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "nand-protect"; + }; + + usb-enable { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-enable"; + }; + + phy-reset { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "phy-reset"; + }; + + led-enable { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "led-enable"; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; +}; + +&nand_controller { + compatible = "marvell,armada370-nand-controller"; + label = "pxa3xx_nand-0"; + status = "okay"; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; + +&{/} { + boot-board { + compatible = "atl,boot-board"; + present-gpio = <&systemgpio 12 GPIO_ACTIVE_HIGH>; + override-gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; +}; + diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 4afaee234ea..0b4df8e7be9 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -226,6 +226,10 @@ config TARGET_X240 select ALLEYCAT_5 imply BOOTSTD_DEFAULTS +config TARGET_X220 + bool "Support Allied Telesis x220" + select 98DX3336 + config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" select 98DX3336 @@ -310,6 +314,7 @@ config SYS_BOARD default "x530" if TARGET_X530 default "x250" if TARGET_X250 default "x240" if TARGET_X240 + default "x220" if TARGET_X220 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -335,6 +340,7 @@ config SYS_CONFIG_NAME default "x530" if TARGET_X530 default "x250" if TARGET_X250 default "x240" if TARGET_X240 + default "x220" if TARGET_X220 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -360,6 +366,7 @@ config SYS_VENDOR default "alliedtelesis" if TARGET_X530 default "alliedtelesis" if TARGET_X250 default "alliedtelesis" if TARGET_X240 + default "alliedtelesis" if TARGET_X220 default "mikrotik" if TARGET_CRS3XX_98DX3236 default "Marvell" if TARGET_MVEBU_ALLEYCAT5 diff --git a/board/alliedtelesis/x220/.gitattributes b/board/alliedtelesis/x220/.gitattributes new file mode 100644 index 00000000000..2aeb4eee641 --- /dev/null +++ b/board/alliedtelesis/x220/.gitattributes @@ -0,0 +1 @@ +binary.0 binary diff --git a/board/alliedtelesis/x220/.gitignore b/board/alliedtelesis/x220/.gitignore new file mode 100644 index 00000000000..775b9346b85 --- /dev/null +++ b/board/alliedtelesis/x220/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/alliedtelesis/x220/MAINTAINERS b/board/alliedtelesis/x220/MAINTAINERS new file mode 100644 index 00000000000..63da2725f71 --- /dev/null +++ b/board/alliedtelesis/x220/MAINTAINERS @@ -0,0 +1,8 @@ +x220 BOARD +M: Chris Packham +S: Maintained +F: board/alliedtelesis/x220 +F: include/configs/x220.h +F: configs/x220_defconfig +F: arch/arm/dts/armada-xp-atl-x220.dts +F: doc/board/alliedtelesis/x220.rst diff --git a/board/alliedtelesis/x220/Makefile b/board/alliedtelesis/x220/Makefile new file mode 100644 index 00000000000..a74f0a76948 --- /dev/null +++ b/board/alliedtelesis/x220/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Allied Telesis Labs + +obj-y := x220.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/alliedtelesis/x220/binary.0 b/board/alliedtelesis/x220/binary.0 new file mode 100644 index 00000000000..8dd687286a0 --- /dev/null +++ b/board/alliedtelesis/x220/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/alliedtelesis/x220/kwbimage.cfg.in b/board/alliedtelesis/x220/kwbimage.cfg.in new file mode 100644 index 00000000000..8beda907ba4 --- /dev/null +++ b/board/alliedtelesis/x220/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2025 Allied Telesis Labs +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/alliedtelesis/x220/binary.0 0000005b 00000068 diff --git a/board/alliedtelesis/x220/x220.c b/board/alliedtelesis/x220/x220.c new file mode 100644 index 00000000000..7c9a73de9a2 --- /dev/null +++ b/board/alliedtelesis/x220/x220.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Allied Telesis Labs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define X220_GPP_OUT_ENA_LOW (~(BIT(12) | BIT(17) | BIT(18) | BIT(31))) +#define X220_GPP_OUT_ENA_MID (~(0)) +#define X220_GPP_OUT_VAL_LOW (BIT(12) | BIT(18)) +#define X220_GPP_OUT_VAL_MID 0x0 +#define X220_GPP_POL_LOW 0x0 +#define X220_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x44042222, MVEBU_MPP_BASE + 0x00); + writel(0x11000004, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x04444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000004, MVEBU_MPP_BASE + 0x10); + + /* Set GPP Out value */ + writel(X220_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(X220_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(X220_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(X220_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(X220_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(X220_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Disable MBUS Err Prop - in order to avoid data aborts */ + clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8)); + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: Allied Telesis x220\n"); + + return 0; +} +#endif diff --git a/configs/x220_defconfig b/configs/x220_defconfig new file mode 100644 index 00000000000..4318f5e6ef1 --- /dev/null +++ b/configs/x220_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/x220/kwbimage.cfg" +CONFIG_TEXT_BASE=0x00800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 +CONFIG_TARGET_X220=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-atl-x220" +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_MAXARGS=96 +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:112M(user),8M(errlog),8M(nand-bbt)" +CONFIG_CMD_UBI=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +# CONFIG_MMC is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_PXA3XX=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PCI_MVEBU=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_WDT=y +CONFIG_WDT_ORION=y diff --git a/doc/board/alliedtelesis/index.rst b/doc/board/alliedtelesis/index.rst new file mode 100644 index 00000000000..a8de2986609 --- /dev/null +++ b/doc/board/alliedtelesis/index.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026 Allied Telesis Labs + +Allied Telesis +============== + +.. toctree:: + :maxdepth: 2 + + x220 + diff --git a/doc/board/alliedtelesis/x220.rst b/doc/board/alliedtelesis/x220.rst new file mode 100644 index 00000000000..6ca5f61ec4e --- /dev/null +++ b/doc/board/alliedtelesis/x220.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026 Allied Telesis Labs + +x220 Platforms +============== + +Introduction +------------ + +The x220 has is a range of L2+ switches using the Marvell AlleyCat3 switch with +integrated ARMv7 CPU. It is also sold under some different brands for different +markets. + +- x220-52GP +- x220-52GT +- x220-28GS +- GS980M/52PS +- GS980M/52 +- x230-52 + +DDR Traning (binhdr) +-------------------- + +The AlleyCat3 uses a binary blob for it's DDR training. This is launched by +the built-in bootloader prior to U-Boot starting. + +To generate binary.0 from Marvell's bin_hdr.elf use the following command + +.. prompt:: bash $ + + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \ + board/alliedtelesis/x220/binary.0 + +Alternatively, it is possible to extract the binary.0 from an existing U-Boot +image + +.. prompt:: bash $ + + ./tools/dumpimage -T kwbimage -p 1 -o board/alliedtelesis/x220/binary.0 u-boot.kwb diff --git a/doc/board/index.rst b/doc/board/index.rst index fcb4224bae3..4103fef8d8f 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -10,6 +10,7 @@ Board-specific doc actions/index advantech/index andestech/index + alliedtelesis/index allwinner/index amlogic/index anbernic/index diff --git a/include/configs/x220.h b/include/configs/x220.h new file mode 100644 index 00000000000..3022ad491b7 --- /dev/null +++ b/include/configs/x220.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Allied Telesis Labs + */ + +#ifndef _CONFIG_X220_H +#define _CONFIG_X220_H + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_X220_H */ -- cgit v1.3.1 From 3457acc01465644fff255ccbcd65470b64d57184 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Fri, 8 May 2026 15:54:05 +0200 Subject: board: freebox: add Nodebox 10G board support Add board support for the Freebox Nodebox 10G based on the Marvell Armada 8040 SoC. This board features: - Quad-core ARMv8 AP806 with dual CP110 companions - eMMC storage via Xenon SDHCI controller - 1G SGMII Ethernet on CP0 lane 5 - I2C buses for peripheral access - NS16550 UART console at 115200 baud The implementation includes: - Device tree for the Nodebox 10G hardware - Dedicated board directory (board/freebox/nbx10g/) - Board-specific Kconfig and defconfig The U-Boot comphy bindings (phy-type/phy-speed) differ from the mainline Linux PHY framework bindings used by phy-mvebu-cp110-comphy, so U-Boot and the kernel each have their own device tree. Signed-off-by: Vincent Jardin Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-8040-nbx.dts | 259 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 9 ++ board/freebox/nbx10g/Kconfig | 12 ++ board/freebox/nbx10g/MAINTAINERS | 6 + board/freebox/nbx10g/Makefile | 3 + board/freebox/nbx10g/board.c | 53 ++++++++ configs/mvebu_nbx_88f8040_defconfig | 75 +++++++++++ include/configs/nbx10g.h | 29 ++++ 9 files changed, 447 insertions(+) create mode 100644 arch/arm/dts/armada-8040-nbx.dts create mode 100644 board/freebox/nbx10g/Kconfig create mode 100644 board/freebox/nbx10g/MAINTAINERS create mode 100644 board/freebox/nbx10g/Makefile create mode 100644 board/freebox/nbx10g/board.c create mode 100644 configs/mvebu_nbx_88f8040_defconfig create mode 100644 include/configs/nbx10g.h (limited to 'include/configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 722a7a662b1..c647379c5ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -163,6 +163,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-8040-clearfog-gt-8k.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \ + armada-8040-nbx.dtb \ armada-8040-puzzle-m801.dtb \ cn9130-db-A.dtb \ cn9130-db-B.dtb \ diff --git a/arch/arm/dts/armada-8040-nbx.dts b/arch/arm/dts/armada-8040-nbx.dts new file mode 100644 index 00000000000..b8b7298b4f5 --- /dev/null +++ b/arch/arm/dts/armada-8040-nbx.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for NBX board (Freebox Nodebox10G) + * Based on Marvell Armada 8040 SoC + * + * Copyright (C) 2024 + */ + +#include "armada-8040.dtsi" + +/ { + model = "NBX Armada 8040"; + compatible = "nbx,armada8040", "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + gpio0 = &ap_gpio0; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* 2GB */ + }; +}; + +/* AP806 UART - active */ +&uart0 { + status = "okay"; +}; + +/* AP806 pinctrl */ +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* AP806 on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* CP0 pinctrl */ +&cp0_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins + * [32,34] GE_MDIO/MDC + * [35-36] I2C1 + * [37-38] I2C0 + * [57-58] MSS I2C + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 7 0 7 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 2 2 0 + 0 0 0 >; + + cp0_smi_pins: cp0-smi-pins { + marvell,pins = <32 34>; + marvell,function = <7>; + }; +}; + +/* CP0 I2C0 */ +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CP0 I2C1 */ +&cp0_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CP0 MSS I2C0 - Management SubSystem I2C (pins 57-58, func 2) */ +&cp0_mss_i2c0 { + status = "okay"; +}; + +/* CP0 MDIO for PHY */ +&cp0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_smi_pins>; + + nbx_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +/* CP0 ComPhy - SerDes configuration */ +&cp0_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0-3: Unconnected + * Lane 4: SFI (10G Ethernet) + * Lane 5: SGMII2 (1G Ethernet) + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + phy-speed = ; + }; + phy5 { + phy-type = ; + phy-speed = ; + }; +}; + +/* CP0 Ethernet - only eth2 (MAC3) is active via SGMII */ +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth2 { + status = "okay"; + phy = <&nbx_phy0>; + phy-mode = "sgmii"; +}; + +/* CP0 UTMI PHY for USB */ +&cp0_utmi { + status = "okay"; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_utmi1 { + status = "okay"; +}; + +/* CP0 USB3 Host controllers */ +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +/* CP1 pinctrl */ +&cp1_pinctl { + /* + * MPP Bus: + * [0-26] = Unconfigured + * [27-28] GE_MDIO/MDC + * [29-30] MSS I2C + * [31] = Unconfigured + * [32-62] = 0xff: Keep default CP1_shared_pins + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 + 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; + + cp1_mss_i2c_pins: cp1-mss-i2c-pins { + marvell,pins = <29 30>; + marvell,function = <8>; + }; +}; + +/* CP1 MSS I2C0 - Management SubSystem I2C (pins 29-30, func 8) */ +&cp1_mss_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_mss_i2c_pins>; +}; + +/* CP1 ComPhy - SerDes configuration */ +&cp1_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: PCIe x1 + * Lane 1: USB3 Host + * Lane 2-3: Unconnected + * Lane 4: SFI (10G Ethernet) + * Lane 5: Unconnected + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + phy-speed = ; + }; + phy5 { + phy-type = ; + }; +}; + +/* CP1 PCIe x1 on lane 0 */ +&cp1_pcie0 { + status = "okay"; +}; + +/* CP1 USB3 Host on lane 1 */ +&cp1_usb3_0 { + status = "okay"; +}; + +/* CP1 UTMI PHY for USB */ +&cp1_utmi { + status = "okay"; +}; + +&cp1_utmi0 { + status = "okay"; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0b4df8e7be9..3465ccfc151 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -166,6 +166,14 @@ config TARGET_MVEBU_ARMADA_8K select BOARD_LATE_INIT imply SCSI +config TARGET_NBX10G + bool "Support Freebox Nodebox 10G" + select ARMADA_8K + select BOARD_LATE_INIT + help + Enable support for the Freebox Nodebox 10G board based on the + Marvell Armada 8040 SoC with dual CP110 companion chips. + config TARGET_MVEBU_ALLEYCAT5 bool "Support AlleyCat 5 platforms" select ALLEYCAT_5 @@ -515,5 +523,6 @@ config ARMADA_32BIT_SYSCON_SYSRESET source "board/solidrun/clearfog/Kconfig" source "board/kobol/helios4/Kconfig" +source "board/freebox/nbx10g/Kconfig" endif diff --git a/board/freebox/nbx10g/Kconfig b/board/freebox/nbx10g/Kconfig new file mode 100644 index 00000000000..18a169761b7 --- /dev/null +++ b/board/freebox/nbx10g/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NBX10G + +config SYS_BOARD + default "nbx10g" + +config SYS_VENDOR + default "freebox" + +config SYS_CONFIG_NAME + default "nbx10g" + +endif diff --git a/board/freebox/nbx10g/MAINTAINERS b/board/freebox/nbx10g/MAINTAINERS new file mode 100644 index 00000000000..2e31eed45b9 --- /dev/null +++ b/board/freebox/nbx10g/MAINTAINERS @@ -0,0 +1,6 @@ +NBX10G BOARD +M: Vincent Jardin +S: Maintained +F: board/freebox/nbx10g/ +F: configs/mvebu_nbx_88f8040_defconfig +F: arch/arm/dts/armada-8040-nbx* diff --git a/board/freebox/nbx10g/Makefile b/board/freebox/nbx10g/Makefile new file mode 100644 index 00000000000..bf83bdf63ee --- /dev/null +++ b/board/freebox/nbx10g/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := board.o diff --git a/board/freebox/nbx10g/board.c b/board/freebox/nbx10g/board.c new file mode 100644 index 00000000000..7d16010ec7e --- /dev/null +++ b/board/freebox/nbx10g/board.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2018 Freebox SA + * Copyright (C) 2026 Free Mobile, Vincent Jardin + * + * Freebox Nodebox 10G board support + */ + +#include +#include +#include + +/* Management PHY reset GPIO */ +#define NBX_PHY_RESET_GPIO 83 + +/* Nodebox 10G ASCII art logo */ +static const char * const nbx_logo = + " _ _ _ _ __ ___ _____\n" + " | \\ | | | | | | /_ |/ _ \\ / ____|\n" + " | \\| | ___ __| | ___| |__ _____ __ | | | | | | __\n" + " | . ` |/ _ \\ / _` |/ _ \\ '_ \\ / _ \\ \\/ / | | | | | | |_ |\n" + " | |\\ | (_) | (_| | __/ |_) | (_) > < | | |_| | |__| |\n" + " |_| \\_|\\___/ \\__,_|\\___|_.__/ \\___/_/\\_\\ |_|\\___/ \\_____|\n"; + +int checkboard(void) +{ + printf("%s\n", nbx_logo); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + int ret; + + /* Reset the management PHY */ + ret = gpio_request(NBX_PHY_RESET_GPIO, "phy-reset"); + if (ret) { + printf("Failed to request PHY reset GPIO: %d\n", ret); + return 0; + } + + gpio_direction_output(NBX_PHY_RESET_GPIO, 0); + mdelay(100); + gpio_set_value(NBX_PHY_RESET_GPIO, 1); + mdelay(100); + + return 0; +} diff --git a/configs/mvebu_nbx_88f8040_defconfig b/configs/mvebu_nbx_88f8040_defconfig new file mode 100644 index 00000000000..85a3086d6a0 --- /dev/null +++ b/configs/mvebu_nbx_88f8040_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 +CONFIG_TARGET_NBX10G=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x180000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-nbx" +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_PCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_EFI_LOADER is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo (CRC warning is normal: no env saved yet)" +CONFIG_SYS_PBSIZE=1048 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="nodebox10G>> " +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_NBX_EMMCBOOT=y +CONFIG_CMD_NBX_FBXSERIAL=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_MISC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +# CONFIG_SPI_FLASH is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_PHY=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/nbx10g.h b/include/configs/nbx10g.h new file mode 100644 index 00000000000..bd083b7e7d8 --- /dev/null +++ b/include/configs/nbx10g.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2018 Freebox SA + * Copyright (C) 2026 Free Mobile, Vincent Jardin + * + * Configuration for Freebox Nodebox 10G + */ + +#ifndef _CONFIG_NBX10G_H +#define _CONFIG_NBX10G_H + +#include "mvebu_armada-8k.h" + +/* Override environment settings for NBX */ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + "hostname=nodebox10G\0" \ + "ethrotate=no\0" \ + "image_addr=0x7000000\0" \ + "image_name=Image.nodebox10G\0" \ + "fdt_addr=0x6f00000\0" \ + "fdt_name=nodebox10G.dtb\0" \ + "console=ttyS0,115200\0" \ + "tftpboot=setenv bootargs console=${console} bank=tftp; " \ + "dhcp ${image_addr} ${image_name}; " \ + "tftp ${fdt_addr} ${fdt_name}; " \ + "booti ${image_addr} - ${fdt_addr}\0" + +#endif /* _CONFIG_NBX10G_H */ -- cgit v1.3.1 From 3f1821162638acc34b47b6c68f3bc8bab365c08d Mon Sep 17 00:00:00 2001 From: Siu Ming Tong Date: Wed, 27 May 2026 19:38:37 -0700 Subject: grm: axiado: Add AX3005 based SCM3005 board support Introduce mach-axiado to support Axiado SoC-based boards. This adds the platform Kconfig and build infrastructure, along with initial SCM3005 board support using the AX3005 SoC. Introduces AXIADO_AX3005, which selects ARM64, driver model, GIC-v3, and Zynq UART. TARGET_SCM3005 selects ARCH_AXIADO, allowing future SoC variants to share the platform configuration. Secondary cores use spin-table boot. ft_board_setup() corrects the cpu-release-addr in the FDT, which arch_fixup_fdt() overwrites with the post-relocation address. Add U-Boot board support for the Axiado AX3005 based targets, a quad-core ARM Cortex-A53 (ARMv8) platform. Tested-by: Siu Ming Tong Signed-off-by: Karthikeyan Mitran Signed-off-by: Siu Ming Tong --- MAINTAINERS | 11 +++ arch/arm/Kconfig | 9 +++ arch/arm/mach-axiado/Kconfig | 22 ++++++ arch/arm/mach-axiado/Makefile | 6 ++ arch/arm/mach-axiado/scm3005/Kconfig | 11 +++ board/axiado/scm3005/Kconfig | 15 ++++ board/axiado/scm3005/Makefile | 5 ++ board/axiado/scm3005/scm3005.c | 128 +++++++++++++++++++++++++++++++++++ configs/ax3005_scm3005_defconfig | 74 ++++++++++++++++++++ include/configs/ax3005-scm3005.h | 29 ++++++++ 10 files changed, 310 insertions(+) create mode 100644 arch/arm/mach-axiado/Kconfig create mode 100644 arch/arm/mach-axiado/Makefile create mode 100644 arch/arm/mach-axiado/scm3005/Kconfig create mode 100644 board/axiado/scm3005/Kconfig create mode 100644 board/axiado/scm3005/Makefile create mode 100644 board/axiado/scm3005/scm3005.c create mode 100644 configs/ax3005_scm3005_defconfig create mode 100644 include/configs/ax3005-scm3005.h (limited to 'include/configs') diff --git a/MAINTAINERS b/MAINTAINERS index 056902f6ef2..0659d299fde 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -213,6 +213,17 @@ F: drivers/reset/reset-ast2500.c F: drivers/watchdog/ast_wdt.c N: aspeed +ARM AXIADO AX3005 SCM3005 +M: Siu Ming Tong +M: Karthikeyan Mitran +M: Prasad Bolisetty +S: Maintained +F: arch/arm/dts/ax3005* +F: arch/arm/mach-axiado/ +F: board/axiado/scm3005/ +F: configs/ax3005_scm3005_defconfig +F: include/configs/ax3005-scm3005.h + ARM BROADCOM BCM283X / BCM27XX M: Matthias Brugger M: Peter Robinson diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f624675eadf..3fcedee739f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2152,6 +2152,13 @@ config ARCH_ASPEED select OF_CONTROL imply CMD_DM +config ARCH_AXIADO + bool "Support Axiado SoCs" + select AXIADO_AX3005 + help + Support for Axiado AX-series SoCs such as the AX3005. + These ARM64 SoCs are used in BMC and security applications. + config TARGET_DURIAN bool "Support Phytium Durian Platform" select ARM64 @@ -2293,6 +2300,8 @@ source "arch/arm/mach-aspeed/Kconfig" source "arch/arm/mach-at91/Kconfig" +source "arch/arm/mach-axiado/Kconfig" + source "arch/arm/mach-bcm283x/Kconfig" source "arch/arm/mach-bcmbca/Kconfig" diff --git a/arch/arm/mach-axiado/Kconfig b/arch/arm/mach-axiado/Kconfig new file mode 100644 index 00000000000..12ad44070eb --- /dev/null +++ b/arch/arm/mach-axiado/Kconfig @@ -0,0 +1,22 @@ +if ARCH_AXIADO + +config SYS_ARCH + default "arm" + +config SYS_SOC + default "axiado" + +config AXIADO_AX3005 + bool + select ARM64 + select ARMV8_SWITCH_TO_EL1 + select DM + select DM_SERIAL + select GICV3 + select ZYNQ_SERIAL + select MMC_SDHCI_AXIADO + select PHY_AXIADO_EMMC + +source "arch/arm/mach-axiado/scm3005/Kconfig" + +endif diff --git a/arch/arm/mach-axiado/Makefile b/arch/arm/mach-axiado/Makefile new file mode 100644 index 00000000000..2acd5466dd9 --- /dev/null +++ b/arch/arm/mach-axiado/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). +# + +obj-$(CONFIG_AXIADO_AX3005) += scm3005/ diff --git a/arch/arm/mach-axiado/scm3005/Kconfig b/arch/arm/mach-axiado/scm3005/Kconfig new file mode 100644 index 00000000000..fc74aa0871b --- /dev/null +++ b/arch/arm/mach-axiado/scm3005/Kconfig @@ -0,0 +1,11 @@ +if AXIADO_AX3005 + +config TARGET_SCM3005 + bool "Support Axiado AX3005 SCM3005" + help + Support for the Axiado AX3005 SCM3005 board. + Based on the Axiado AX3005 quad-core ARMv8 Cortex-A53 SoC. + +source "board/axiado/scm3005/Kconfig" + +endif diff --git a/board/axiado/scm3005/Kconfig b/board/axiado/scm3005/Kconfig new file mode 100644 index 00000000000..d6f4f311f55 --- /dev/null +++ b/board/axiado/scm3005/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SCM3005 + +config SYS_BOARD + string + default "scm3005" + +config SYS_VENDOR + string + default "axiado" + +config SYS_CONFIG_NAME + string + default "ax3005-scm3005" + +endif diff --git a/board/axiado/scm3005/Makefile b/board/axiado/scm3005/Makefile new file mode 100644 index 00000000000..3d35713bab9 --- /dev/null +++ b/board/axiado/scm3005/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + +obj-y := scm3005.o diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c new file mode 100644 index 00000000000..4643ba4a55c --- /dev/null +++ b/board/axiado/scm3005/scm3005.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region axiado_ax3005_mem_map[] = { + { /* Peripherals including UART */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + { .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, + { + 0, + } +}; + +struct mm_region *mem_map = axiado_ax3005_mem_map; + +/* + * Accept any FIT configuration name - the board loads a single FIT image + * and the first matching config is used. + */ +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +/* + * ft_board_setup - restore cpu-release-addr after relocation + * + * arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr + * with U-Boot's relocated address. Restore the pre-relocation physical + * address so secondary cores spin on the correct location. + */ +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int cpus_offset, offset; + const char *prop; + int ret; + u64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off; + + cpus_offset = fdt_path_offset(blob, "/cpus"); + if (cpus_offset < 0) + return 0; + + for (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0; + offset = fdt_next_subnode(blob, offset)) { + prop = fdt_getprop(blob, offset, "device_type", NULL); + if (!prop || strcmp(prop, "cpu")) + continue; + + prop = fdt_getprop(blob, offset, "enable-method", NULL); + if (!prop || strcmp(prop, "spin-table")) + continue; + + ret = fdt_setprop_u64(blob, offset, "cpu-release-addr", + cpu_release_addr); + if (ret) { + printf("WARNING: Failed to restore cpu-release-addr\n"); + return ret; + } + } + + return 0; +} + +/* + * dram_init - DDR is initialized by firmware, just setting size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); + return 0; +} + +/* + * the SOC uses single bank, non-interleaving + */ +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + return 0; +} + +/* + * timer_init - enable the AX3005 platform system timer + * + * CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using + * CONFIG_COUNTER_FREQUENCY from the defconfig. + * + * SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control + * register — writing SYS_TIMER_ENABLE starts the counter that feeds + * the ARM generic timer. + */ +int timer_init(void) +{ + writel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL); + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + /* For later ARM_PSCI_FW or watchdog reset */ +} diff --git a/configs/ax3005_scm3005_defconfig b/configs/ax3005_scm3005_defconfig new file mode 100644 index 00000000000..5dd72d87220 --- /dev/null +++ b/configs/ax3005_scm3005_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_AXIADO=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_TEXT_BASE=0x80000000 +CONFIG_SYS_MONITOR_BASE=0x80000000 +CONFIG_SYS_LOAD_ADDR=0x80100000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_SYS_BOOTM_LEN=0x20000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x5000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_COUNTER_FREQUENCY=1000000000 +CONFIG_ARMV8_MULTIENTRY=y +CONFIG_ARMV8_SET_SMPEN=y +CONFIG_ARMV8_SPIN_TABLE=y +CONFIG_SYS_CUSTOM_LDSCRIPT=y +CONFIG_SYS_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds" +CONFIG_BOOTDELAY=5 +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="ax3005-scm3005.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Axiado> " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press \"\" to stop autobooting in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyPS3,115200 maxcpus=4 nr_cpus=4 earlycon hugepages=16 root=/dev/ram rw phram.phram=ramrofs,0x80B00000,0x6400000" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="bootm ${loadaddr}" +CONFIG_SYS_VENDOR="axiado" +CONFIG_SYS_BOARD="scm3005" +CONFIG_SYS_CONFIG_NAME="ax3005-scm3005" +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="ax3005-scm3005" +CONFIG_MULTI_DTB_FIT=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_DM_MMC=y +# CONFIG_SUPPORT_EMMC_BOOT is not set +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_TARGET_SCM3005=y +CONFIG_CLK=y +CONFIG_LZMA=y +CONFIG_XZ=y +CONFIG_ZYNQ_SERIAL=y +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/include/configs/ax3005-scm3005.h b/include/configs/ax3005-scm3005.h new file mode 100644 index 00000000000..4eead2910c8 --- /dev/null +++ b/include/configs/ax3005-scm3005.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +#ifndef __AX3005_SCM3005_H +#define __AX3005_SCM3005_H + +#include + +#define GICD_BASE 0x40400000 +#define GICR_BASE 0x40500000 + +#define SYS_TIMER_CTRL 0x48016000 +#define SYS_TIMER_ENABLE 0x1 +#define SYS_TIMER_DISABLE 0x0 + +/* DRAM: 2 GB at 0x80000000 */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_2G +#define CFG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + SZ_1M) + +#define CFG_SYS_MAXARGS 64 +#define CFG_SYS_BARGSIZE CFG_SYS_CBSIZE + +#define CFG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +#endif /* __AX3005_SCM3005_H */ -- cgit v1.3.1 From b941dc47398b93aea37b9139d6816610ad78352f Mon Sep 17 00:00:00 2001 From: "Markus Schneider-Pargmann (TI)" Date: Mon, 1 Jun 2026 11:30:38 +0200 Subject: include: configs: am335x_evm: Enable vidconsole Enable vidconsole for the am335x-evm board. Reviewed-by: Kory Maincent Signed-off-by: Markus Schneider-Pargmann (TI) --- include/configs/am335x_evm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index d2164b41d6d..babf065bc3e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -83,6 +83,8 @@ "fdtfile=undefined\0" \ "finduuid=part uuid mmc 0:2 uuid\0" \ "console=ttyO0,115200n8\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "partitions=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=bootloader,start=384K,size=1792K," \ -- cgit v1.3.1 From 196b1fe9bf80959648cf54b2e36c08dfd24fc1ad Mon Sep 17 00:00:00 2001 From: Bastien Curutchet Date: Mon, 8 Jun 2026 15:12:00 +0200 Subject: configs: omap4: remove unused boot target devices This include file isn't used since the omap4 support has been dropped. Since this support is about to be reintroduced, this file is going to be used again. The upcoming support is minimal and doesn't include network, therefore leaving PXE and DHCP in the BOOT_TARGET_DEVICES list would lead to build errors. Remove PXE and DHCP from the list of BOOT_TARGET_DEVICES. Remove the LEGACY_MMC macros and the findfdt script that looks for no-longer supported boards. Remove the empty #ifdef XPL_BUILD Signed-off-by: Bastien Curutchet --- include/configs/ti_omap4_common.h | 40 --------------------------------------- 1 file changed, 40 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 7a333090b18..e4b84719c86 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -35,25 +35,9 @@ /* * Environment setup */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) #include #include @@ -73,30 +57,6 @@ "uimageboot=echo Booting from mmc${mmcdev} ...; " \ "run args_mmc; " \ "bootm ${loadaddr}\0" \ - "findfdt="\ - "if test $board_name = sdp4430; then " \ - "setenv fdtfile omap4-sdp.dtb; fi; " \ - "if test $board_name = panda; then " \ - "setenv fdtfile omap4-panda.dtb; fi;" \ - "if test $board_name = panda-a4; then " \ - "setenv fdtfile omap4-panda-a4.dtb; fi;" \ - "if test $board_name = panda-es; then " \ - "setenv fdtfile omap4-panda-es.dtb; fi;" \ - "if test $board_name = duovero; then " \ - "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ BOOTENV -/* - * Defines for SPL - * It is known that this will break HS devices. Since the current size of - * SPL is overlapped with public stack and breaking non HS devices to boot. - * So moving TEXT_BASE down to non-HS limit. - */ - -#ifdef CONFIG_XPL_BUILD -/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ -#endif - #endif /* __CONFIG_TI_OMAP4_COMMON_H */ -- cgit v1.3.1 From 1174c99ab421168221be372bd83a4143bf5f167d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 17 Jun 2026 10:48:19 +0300 Subject: treewide: move bi_dram[] from bd to gd Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP) --- api/api_platform.c | 4 +- arch/arm/cpu/armv8/cache_v8.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 118 ++++++++++----------- arch/arm/lib/bootm-fdt.c | 5 +- arch/arm/lib/bootm.c | 4 +- arch/arm/lib/cache-cp15.c | 9 +- arch/arm/lib/image.c | 2 +- arch/arm/mach-airoha/an7581/init.c | 8 +- arch/arm/mach-apple/board.c | 4 +- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-imx/ele_ahab.c | 7 +- arch/arm/mach-imx/imx8/ahab.c | 7 +- arch/arm/mach-imx/imx8/cpu.c | 44 ++++---- arch/arm/mach-imx/imx8m/soc.c | 24 ++--- arch/arm/mach-imx/imx8ulp/soc.c | 20 ++-- arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++--- arch/arm/mach-imx/imx9/soc.c | 24 ++--- arch/arm/mach-imx/mx5/mx53_dram.c | 8 +- arch/arm/mach-imx/spl.c | 4 +- arch/arm/mach-k3/k3-ddr.c | 4 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 4 +- arch/arm/mach-mvebu/armada3700/cpu.c | 10 +- arch/arm/mach-mvebu/armada8k/dram.c | 10 +- arch/arm/mach-mvebu/dram.c | 6 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap-cache.c | 5 +- arch/arm/mach-omap2/omap3/emif4.c | 8 +- arch/arm/mach-omap2/omap3/sdrc.c | 8 +- arch/arm/mach-owl/soc.c | 4 +- arch/arm/mach-renesas/memmap-gen3.c | 8 +- arch/arm/mach-renesas/memmap-rzg2l.c | 4 +- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 +- arch/arm/mach-rockchip/sdram.c | 42 ++++---- arch/arm/mach-snapdragon/board.c | 16 +-- arch/arm/mach-socfpga/board.c | 5 +- arch/arm/mach-socfpga/misc_arria10.c | 7 +- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 +- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 +- arch/arm/mach-tegra/board2.c | 14 +-- arch/arm/mach-tegra/cboot.c | 4 +- arch/arm/mach-uniphier/dram_init.c | 6 +- arch/arm/mach-uniphier/fdt-fixup.c | 8 +- arch/arm/mach-versal-net/cpu.c | 8 +- arch/arm/mach-versal/cpu.c | 16 +-- arch/arm/mach-versal2/cpu.c | 7 +- arch/arm/mach-zynqmp/cpu.c | 8 +- arch/mips/mach-octeon/dram.c | 4 +- arch/riscv/cpu/k1/dram.c | 12 +-- arch/sandbox/cpu/spl.c | 4 +- arch/x86/cpu/coreboot/sdram.c | 4 +- arch/x86/cpu/efi/payload.c | 4 +- arch/x86/cpu/efi/sdram.c | 4 +- arch/x86/cpu/intel_common/mrc.c | 4 +- arch/x86/cpu/ivybridge/sdram_nop.c | 4 +- arch/x86/cpu/qemu/dram.c | 8 +- arch/x86/cpu/quark/dram.c | 4 +- arch/x86/cpu/slimbootloader/sdram.c | 4 +- arch/x86/cpu/tangier/sdram.c | 4 +- arch/x86/lib/bootm.c | 5 +- arch/x86/lib/fsp/fsp_dram.c | 18 ++-- board/CZ.NIC/turris_1x/turris_1x.c | 42 ++++---- board/armltd/corstone1000/corstone1000.c | 4 +- board/armltd/integrator/integrator.c | 4 +- board/armltd/total_compute/total_compute.c | 6 +- board/armltd/vexpress/vexpress_common.c | 8 +- board/atmel/common/video_display.c | 2 +- board/atmel/sam9x60_curiosity/sam9x60_curiosity.c | 2 +- board/atmel/sam9x75_curiosity/sam9x75_curiosity.c | 2 +- board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 2 +- .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 2 +- .../atmel/sama5d29_curiosity/sama5d29_curiosity.c | 2 +- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 2 +- .../atmel/sama7d65_curiosity/sama7d65_curiosity.c | 2 +- .../atmel/sama7g54_curiosity/sama7g54_curiosity.c | 2 +- board/axiado/scm3005/scm3005.c | 4 +- board/broadcom/bcmns3/ns3.c | 4 +- board/compulab/cm_fx6/cm_fx6.c | 28 ++--- board/elgin/elgin_rv1108/elgin_rv1108.c | 4 +- board/esd/meesc/meesc.c | 4 +- board/friendlyarm/nanopi2/board.c | 10 +- board/ge/mx53ppd/mx53ppd.c | 8 +- board/hisilicon/hikey/hikey.c | 24 ++--- board/hisilicon/hikey960/hikey960.c | 4 +- board/hisilicon/poplar/poplar.c | 4 +- board/k+p/kp_imx53/kp_imx53.c | 4 +- board/keymile/pg-wcom-ls102xa/ddr.c | 4 +- board/kontron/sl28/sl28.c | 4 +- board/kontron/sl28/spl_atf.c | 6 +- board/liebherr/btt/btt.c | 2 +- board/menlo/m53menlo/m53menlo.c | 8 +- board/nuvoton/arbel_evb/arbel_evb.c | 26 ++--- board/nxp/imxrt1020-evk/imxrt1020-evk.c | 2 +- board/nxp/imxrt1050-evk/imxrt1050-evk.c | 2 +- board/nxp/imxrt1170-evk/imxrt1170-evk.c | 2 +- board/nxp/ls1021aqds/ddr.c | 4 +- board/nxp/ls1028a/ls1028a.c | 10 +- board/nxp/ls1043aqds/ls1043aqds.c | 8 +- board/nxp/ls1043ardb/ls1043ardb.c | 8 +- board/nxp/ls1046afrwy/ls1046afrwy.c | 8 +- board/nxp/ls1046aqds/ls1046aqds.c | 8 +- board/nxp/ls1046ardb/ls1046ardb.c | 8 +- board/nxp/ls1088a/ls1088a.c | 6 +- board/nxp/ls2080aqds/ls2080aqds.c | 14 +-- board/nxp/ls2080ardb/ls2080ardb.c | 14 +-- board/nxp/lx2160a/lx2160a.c | 6 +- board/phytec/phycore_am62x/phycore-am62x.c | 26 ++--- board/phytec/phycore_am64x/phycore-am64x.c | 18 ++-- board/phytium/durian/durian.c | 4 +- board/phytium/pe2201/pe2201.c | 4 +- board/raspberrypi/rpi/rpi.c | 4 +- board/renesas/common/rcar64-common.c | 6 +- board/renesas/genmai/genmai.c | 4 +- board/renesas/sparrowhawk/sparrowhawk.c | 8 +- board/ronetix/pm9261/pm9261.c | 4 +- board/ronetix/pm9263/pm9263.c | 4 +- board/ronetix/pm9g45/pm9g45.c | 4 +- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 6 +- board/samsung/exynos-mobile/exynos-mobile.c | 4 +- board/samsung/goni/goni.c | 12 +-- board/samsung/smdkc100/smdkc100.c | 4 +- board/samsung/smdkv310/smdkv310.c | 16 +-- board/siemens/iot2050/board.c | 16 +-- board/socionext/developerbox/developerbox.c | 6 +- board/st/stih410-b2260/board.c | 4 +- board/ste/stemmy/stemmy.c | 4 +- board/ti/dra7xx/evm.c | 8 +- board/ti/ks2_evm/board.c | 4 +- board/toradex/colibri_imx7/colibri_imx7.c | 8 +- board/toradex/verdin-am62/verdin-am62.c | 2 +- board/toradex/verdin-am62p/verdin-am62p.c | 2 +- board/traverse/ten64/ten64.c | 6 +- board/xilinx/zynq/cmds.c | 6 +- board/xilinx/zynqmp/zynqmp.c | 4 +- boot/image-board.c | 2 +- boot/image-fdt.c | 4 +- cmd/bdinfo.c | 12 +-- cmd/ti/ddr4.c | 8 +- cmd/ufetch.c | 4 +- common/board_f.c | 10 +- common/init/handoff.c | 10 +- drivers/bootcount/bootcount_ram.c | 4 +- drivers/ddr/altera/sdram_agilex.c | 4 +- drivers/ddr/altera/sdram_agilex5.c | 18 ++-- drivers/ddr/altera/sdram_agilex7m.c | 4 +- drivers/ddr/altera/sdram_arria10.c | 12 +-- drivers/ddr/altera/sdram_n5x.c | 4 +- drivers/ddr/altera/sdram_s10.c | 4 +- drivers/ddr/altera/sdram_soc64.c | 28 ++--- drivers/mmc/mvebu_mmc.c | 4 +- drivers/net/mvgbe.c | 4 +- drivers/pci/pci-uclass.c | 8 +- drivers/usb/host/ehci-marvell.c | 4 +- drivers/video/meson/meson_vpu.c | 8 +- drivers/video/sunxi/sunxi_de2.c | 2 +- drivers/video/sunxi/sunxi_display.c | 2 +- include/asm-generic/global_data.h | 7 ++ include/asm-generic/u-boot.h | 4 - include/configs/m53menlo.h | 4 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 4 +- include/configs/mx53ppd.h | 4 +- include/fdtdec.h | 7 +- include/init.h | 2 +- lib/fdtdec.c | 23 ++-- lib/lmb.c | 19 ++-- test/cmd/bdinfo.c | 7 +- 167 files changed, 707 insertions(+), 714 deletions(-) (limited to 'include/configs') diff --git a/api/api_platform.c b/api/api_platform.c index d5cbcd6e201..d4edf3a20fe 100644 --- a/api/api_platform.c +++ b/api/api_platform.c @@ -21,8 +21,8 @@ int platform_sys_info(struct sys_info *si) si->clk_cpu = gd->cpu_clk; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - platform_set_mr(si, gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size, MR_ATTR_DRAM); + platform_set_mr(si, gd->dram[i].start, + gd->dram[i].size, MR_ATTR_DRAM); platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6c85022556a..e59528e576e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs) } for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - mem_map[index].virt = gd->bd->bi_dram[i].start; - mem_map[index].phys = gd->bd->bi_dram[i].start; - mem_map[index].size = gd->bd->bi_dram[i].size; + mem_map[index].virt = gd->dram[i].start; + mem_map[index].phys = gd->dram[i].start; + mem_map[index].size = gd->dram[i].size; mem_map[index].attrs = attrs; index++; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cbeac6d4383..88adcf35432 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,16 +538,16 @@ static inline void final_mmu_setup(void) */ switch (final_map[index].virt) { case CFG_SYS_FSL_DRAM_BASE1: - final_map[index].virt = gd->bd->bi_dram[0].start; - final_map[index].phys = gd->bd->bi_dram[0].start; - final_map[index].size = gd->bd->bi_dram[0].size; + final_map[index].virt = gd->dram[0].start; + final_map[index].phys = gd->dram[0].start; + final_map[index].size = gd->dram[0].size; break; #ifdef CFG_SYS_FSL_DRAM_BASE2 case CFG_SYS_FSL_DRAM_BASE2: #if (CONFIG_NR_DRAM_BANKS >= 2) - final_map[index].virt = gd->bd->bi_dram[1].start; - final_map[index].phys = gd->bd->bi_dram[1].start; - final_map[index].size = gd->bd->bi_dram[1].size; + final_map[index].virt = gd->dram[1].start; + final_map[index].phys = gd->dram[1].start; + final_map[index].size = gd->dram[1].size; #else final_map[index].size = 0; #endif @@ -556,9 +556,9 @@ static inline void final_mmu_setup(void) #ifdef CFG_SYS_FSL_DRAM_BASE3 case CFG_SYS_FSL_DRAM_BASE3: #if (CONFIG_NR_DRAM_BANKS >= 3) - final_map[index].virt = gd->bd->bi_dram[2].start; - final_map[index].phys = gd->bd->bi_dram[2].start; - final_map[index].size = gd->bd->bi_dram[2].size; + final_map[index].virt = gd->dram[2].start; + final_map[index].phys = gd->dram[2].start; + final_map[index].size = gd->dram[2].size; #else final_map[index].size = 0; #endif @@ -1396,10 +1396,10 @@ static int tfa_dram_init_banksize(void) } debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); - gd->bd->bi_dram[i].start = res.a1; - gd->bd->bi_dram[i].size = res.a2; + gd->dram[i].start = res.a1; + gd->dram[i].size = res.a2; - dram_size -= gd->bd->bi_dram[i].size; + dram_size -= gd->dram[i].size; i++; } while (dram_size); @@ -1410,24 +1410,24 @@ static int tfa_dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1464,30 +1464,30 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - + gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; + gd->dram[1].size = gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; - gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->dram[2].size = gd->dram[1].size - CONFIG_SYS_DDR_BLOCK2_SIZE; - gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; } #endif } else { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; } #ifdef CFG_SYS_MEM_RESERVE_SECURE - if (gd->bd->bi_dram[0].size > + if (gd->dram[0].size > CFG_SYS_MEM_RESERVE_SECURE) { - gd->bd->bi_dram[0].size -= + gd->dram[0].size -= CFG_SYS_MEM_RESERVE_SECURE; - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; + gd->arch.secure_ram = gd->dram[0].start + + gd->dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } @@ -1496,24 +1496,24 @@ int dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1535,8 +1535,8 @@ int dram_init_banksize(void) CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; + gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->dram[2].size = dp_ddr_size; } else { puts("Not detected"); } @@ -1567,8 +1567,8 @@ void lmb_arch_add_memory(void) if (i == 2) continue; /* skip DP-DDR */ #endif - ram_start = gd->bd->bi_dram[i].start; - ram_size = gd->bd->bi_dram[i].size; + ram_start = gd->dram[i].start; + ram_size = gd->dram[i].size; #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram >= ram_start && gd->arch.resv_ram < ram_start + ram_size) diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 2671f9a0ebf..a82ceeaf22f 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob) { __maybe_unused int ret = 0; #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; #ifdef CONFIG_ARMV7_NONSEC ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); if (ret) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1cde655bc80..9a115cc6078 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd) params->hdr.tag = ATAG_MEM; params->hdr.size = tag_size (tag_mem32); - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; + params->u.mem.start = gd->dram[i].start; + params->u.mem.size = gd->dram[i].size; params = tag_next (params); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 947012f2996..28bb6fd36c8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, __weak void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - /* bd->bi_dram is available only after relocation */ + /* gd->dram is available only after relocation */ if ((gd->flags & GD_FLG_RELOC) == 0) return; debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT; + i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) + + (gd->dram[bank].size >> MMU_SECTION_SHIFT); i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1f672eee2c8..2268661de93 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else - dst = gd->bd->bi_dram[0].start; + dst = gd->dram[0].start; *relocated_addr = ALIGN(dst, SZ_2M) + text_offset; diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c index ab32706a79d..f33527ca129 100644 --- a/arch/arm/mach-airoha/an7581/init.c +++ b/arch/arm/mach-airoha/an7581/init.c @@ -23,12 +23,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = gd->ram_base + SZ_2G; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 20054f54089..e74a5a76919 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -807,8 +807,8 @@ void build_mem_map(void) ; /* Align RAM mapping to page boundaries */ - base = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size; + base = gd->dram[0].start; + size = gd->dram[0].size; size += (base - ALIGN_DOWN(base, SZ_4K)); base = ALIGN_DOWN(base, SZ_4K); size = ALIGN(size, SZ_4K); diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 07125eac7cd..2281686d633 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -33,8 +33,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 86b11bdf2ac..e1284833ac5 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -311,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 71a3b341913..34712747fa3 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -111,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f4738e3fda8..b52675d8aba 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank) phys_size_t size; while (current_bank > 0) { - if (gd->bd->bi_dram[current_bank - 1].start > - gd->bd->bi_dram[current_bank].start) { - start = gd->bd->bi_dram[current_bank - 1].start; - size = gd->bd->bi_dram[current_bank - 1].size; - - gd->bd->bi_dram[current_bank - 1].start = - gd->bd->bi_dram[current_bank].start; - gd->bd->bi_dram[current_bank - 1].size = - gd->bd->bi_dram[current_bank].size; - - gd->bd->bi_dram[current_bank].start = start; - gd->bd->bi_dram[current_bank].size = size; + if (gd->dram[current_bank - 1].start > + gd->dram[current_bank].start) { + start = gd->dram[current_bank - 1].start; + size = gd->dram[current_bank - 1].size; + + gd->dram[current_bank - 1].start = + gd->dram[current_bank].start; + gd->dram[current_bank - 1].size = + gd->dram[current_bank].size; + + gd->dram[current_bank].start = start; + gd->dram[current_bank].size = size; } current_bank--; } @@ -643,24 +643,24 @@ int dram_init_banksize(void) continue; if (start >= phys_sdram_1_start && start <= end1) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end1) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end1 - start; + gd->dram[i].size = end1 - start; dram_bank_sort(i); i++; } else if (start >= phys_sdram_2_start && start <= end2) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end2) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end2 - start; + gd->dram[i].size = end2 - start; dram_bank_sort(i); i++; @@ -670,10 +670,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = phys_sdram_1_start; - gd->bd->bi_dram[0].size = phys_sdram_1_size; - gd->bd->bi_dram[1].start = phys_sdram_2_start; - gd->bd->bi_dram[1].size = phys_sdram_2_size; + gd->dram[0].start = phys_sdram_1_start; + gd->dram[0].size = phys_sdram_1_size; + gd->dram[1].start = phys_sdram_2_start; + gd->dram[1].size = phys_sdram_2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 498bbe6704f..e600fd6b33e 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -224,11 +224,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8m_mem_map[entry].phys = gd->dram[i].start; + imx8m_mem_map[entry].virt = gd->dram[i].start; + imx8m_mem_map[entry].size = gd->dram[i].size; imx8m_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); @@ -290,24 +290,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -315,8 +315,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index ccdb949a9da..6d6f3b81aca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -512,11 +512,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size; imx8ulp_arm64_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size); @@ -568,24 +568,24 @@ int dram_init_banksize(void) if (ret) return ret; - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_size; + gd->dram[bank].size = sdram_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 123c1d51a4d..82b3cdffeea 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -356,11 +356,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx9_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx9_mem_map[entry].phys = gd->dram[i].start; + imx9_mem_map[entry].virt = gd->dram[i].start; + imx9_mem_map[entry].size = gd->dram[i].size; imx9_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx9_mem_map[entry].phys, imx9_mem_map[entry].size); @@ -453,24 +453,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -478,8 +478,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 6576ecefd5f..0c731e76329 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -367,11 +367,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx93_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].phys = gd->dram[i].start; + imx93_mem_map[entry].virt = gd->dram[i].start; + imx93_mem_map[entry].size = gd->dram[i].size; imx93_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx93_mem_map[entry].phys, imx93_mem_map[entry].size); @@ -445,24 +445,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -470,8 +470,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index 180a745d435..5f7709e00b0 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -35,11 +35,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 57ae81c7834..1029c1e4e85 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = imx_ddr_size(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = imx_ddr_size(); return 0; } diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c index 6e3e60cdc86..35c30b1a16f 100644 --- a/arch/arm/mach-k3/k3-ddr.c +++ b/arch/arm/mach-k3/k3-ddr.c @@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index be2d9a25bf9..3ebb4294bdd 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 17525691e68..38d9b40f482 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void) * build_mem_map. */ if (last_end == dram_wins[win].base) { - gd->bd->bi_dram[bank - 1].size += size; + gd->dram[bank - 1].size += size; last_end += size; } else { if (bank == CONFIG_NR_DRAM_BANKS) { @@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void) return -ENOBUFS; } - gd->bd->bi_dram[bank].start = dram_wins[win].base; - gd->bd->bi_dram[bank].size = size; + gd->dram[bank].start = dram_wins[win].base; + gd->dram[bank].size = size; last_end = dram_wins[win].base + size; ++bank; } @@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void) * the rest with zeros. */ for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) { - gd->bd->bi_dram[bank].start = 0; - gd->bd->bi_dram[bank].size = 0; + gd->dram[bank].start = 0; + gd->dram[bank].size = 0; } return 0; diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index fd58551d0e3..af37dfa2252 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } - gd->bd->bi_dram[0].size = max_bank0_size; + gd->dram[0].size = max_bank0_size; if (CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = gd->ram_size - max_bank0_size; } return 0; diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index c00c6b9b3fc..41eaaa24bd0 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -294,11 +294,11 @@ int dram_init_banksize(void) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); - gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); + gd->dram[i].start = mvebu_sdram_bar(i); + gd->dram[i].size = mvebu_sdram_bs(i); /* Clip the banksize to 1GiB if it exceeds the max size */ - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; if (size > MVEBU_SDRAM_SIZE_MAX) mvebu_sdram_bs_set(i, 0x40000000); } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 8699cf46b67..729533d02d4 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,8 +80,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 200a08fa5c8..f08a9b263f6 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -53,11 +53,10 @@ void enable_caches(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 049eedfeb65..67e14d70e92 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -150,10 +150,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 24fae484369..c4187369c29 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -222,10 +222,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 0130cad7678..e316c2cc40e 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,8 +50,8 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index d24419f5daa..f7dc2be6cca 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -70,8 +70,8 @@ void enable_caches(void) /* Generate entires for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) @@ -114,8 +114,8 @@ void enable_caches(void) /* Generate entires for DRAM in 64bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 3b3c6f7cde9..5981b3c9c4d 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -67,8 +67,8 @@ void enable_caches(void) /* Generate entries for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eedce7b9b08..c8de1a21024 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -243,14 +243,14 @@ int arch_cpu_init(void) int rockchip_dram_init_banksize_fixup(struct bd_info *bd) { - size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + size_t ram_top = gd->dram[1].start + gd->dram[1].size; if (ram_top > DRAM_GAP_START) { - bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start; if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { - bd->bi_dram[2].start = DRAM_GAP_END; - bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + gd->dram[2].start = DRAM_GAP_END; + gd->dram[2].size = ram_top - gd->dram[2].start; } } diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index ea0e3621af7..f0923186fa6 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void) /* * Rockchip guaranteed DDR_MEM is ordered so no need to worry about - * bi_dram order. + * dram order. */ for (i = 0, j = 0; i < ddr_info->count; i++, j++) { phys_size_t size = ddr_info->bank[(i + ddr_info->count)]; @@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void) * split the region in two, one for before the * reserved memory area and one for after. */ - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = rsrv_start - start_addr; + gd->dram[j].start = start_addr; + gd->dram[j].size = rsrv_start - start_addr; j++; @@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void) return -ENOMEM; } - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = size; + gd->dram[j].start = start_addr; + gd->dram[j].size = size; } return 0; @@ -309,15 +309,15 @@ int dram_init_banksize(void) ret); /* Reserve 2M for ATF bl31 */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; + gd->dram[0].size = top - gd->dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ if (ram_top > SZ_4G && top < SZ_4G) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = ram_top - gd->dram[1].start; } else if (ram_top > SZ_4G && top == SZ_4G) { - gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; + gd->dram[0].size = ram_top - gd->dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -327,23 +327,23 @@ int dram_init_banksize(void) TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = tos_parameter->tee_mem.phy_addr - CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + gd->dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].size = top - gd->dram[1].start; } else { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x2000000; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].start = CFG_SYS_SDRAM_BASE + + gd->dram[0].size + 0x2000000; + gd->dram[1].size = top - gd->dram[1].start; } #else - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = top - gd->dram[0].start; #endif #endif diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 829a0109ac7..35735f1551c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2) } /* This has to be done post-relocation since gd->bd isn't preserved */ -static void qcom_configure_bi_dram(void) +static void qcom_configure_dram(void) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; - gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + gd->dram[i].start = prevbl_ddr_banks[i].start; + gd->dram[i].size = prevbl_ddr_banks[i].size; } } int dram_init_banksize(void) { - qcom_configure_bi_dram(); + qcom_configure_dram(); return 0; } @@ -594,15 +594,15 @@ static void build_mem_map(void) */ mem_map[0].phys = 0x1000; mem_map[0].virt = mem_map[0].phys; - mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys; + mem_map[0].size = gd->dram[0].start - mem_map[0].phys; mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) { - mem_map[i].phys = gd->bd->bi_dram[j].start; + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) { + mem_map[i].phys = gd->dram[j].start; mem_map[i].virt = mem_map[i].phys; - mem_map[i].size = gd->bd->bi_dram[j].size; + mem_map[i].size = gd->dram[j].size; mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_INNER_SHARE; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 4d7f0b9a79c..b202ca258bc 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images) void lmb_arch_add_memory(void) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) - lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + if (gd->dram[i].size) + lmb_add(gd->dram[i].start, gd->dram[i].size); } } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7e0f3875b7c..338f73d6e73 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,7 +246,6 @@ int qspi_flash_software_reset(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; u32 start, size; int i; @@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank) * The default implementation of this function allows the DRAM dcache * to be enabled only after relocation. However, to speed up ECC * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram * is set first). */ - start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; for (i = start; i < start + size; i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 835eaf48dfa..76c324b55ae 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data, dev->mtd = mtd; break; case STM32PROG_RAM: - first_addr = gd->bd->bi_dram[0].start; - last_addr = first_addr + gd->bd->bi_dram[0].size; + first_addr = gd->dram[0].start; + last_addr = first_addr + gd->dram[0].size; dev->erase_size = 1; break; default: diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 252aef1852e..4d81c70b230 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -52,7 +52,6 @@ u32 get_bootauth(void) */ void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; phys_addr_t start; phys_addr_t addr; @@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank) size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); #endif } else if (gd->flags & GD_FLG_RELOC) { - /* bd->bi_dram is available only after relocation */ - start = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + /* gd->dram is available only after relocation */ + start = gd->dram[bank].start; + size = gd->dram[bank].size; use_lmb = true; } else { /* mark cacheable and executable the beggining of the DDR */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 396851c5bd8..1763f95ace4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -393,18 +393,18 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } else #endif { - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; @@ -418,7 +418,7 @@ int dram_init_banksize(void) * carve-out, as mentioned above. * * This function is called before dram_init_banksize(), so we can't simply - * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. + * return gd->dram[1].start + gd->dram[1].size. */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index e2342b2aece..ff15fa28eb5 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void) } for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; - gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + gd->dram[i].start = tegra_mem_map[1 + i].virt; + gd->dram[i].size = tegra_mem_map[1 + i].size; } return 0; diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 0e1164a2680..ae495808dec 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -280,9 +280,9 @@ int dram_init_banksize(void) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i < ARRAY_SIZE(gd->bd->bi_dram)) { - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (i < ARRAY_SIZE(gd->dram)) { + gd->dram[i].start = dram_map[i].base; + gd->dram[i].size = dram_map[i].size; } if (!dram_map[i].size) diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c index dfa32fdd48b..4e1de15cd98 100644 --- a/arch/arm/mach-uniphier/fdt-fixup.c +++ b/arch/arm/mach-uniphier/fdt-fixup.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include @@ -20,6 +21,7 @@ */ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) { + DECLARE_GLOBAL_DATA_PTR; unsigned long rsv_addr; const unsigned long rsv_size = 64; int i, ret; @@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) uniphier_get_soc_id() != UNIPHIER_LD20_ID) return 0; - for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { - if (!bd->bi_dram[i].size) + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { + if (!gd->dram[i].size) continue; - rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; + rsv_addr = gd->dram[i].start + gd->dram[i].size; rsv_addr -= rsv_size; ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index d088e440f63..78ead1f45f6 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -69,12 +69,12 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 363ce3007fd..0dd5cc153c4 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -82,21 +82,21 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; #if defined(CONFIG_VERSAL_NO_DDR) - if (gd->bd->bi_dram[i].start < 0x80000000UL || - gd->bd->bi_dram[i].start > 0x100000000UL) { + if (gd->dram[i].start < 0x80000000UL || + gd->dram[i].start > 0x100000000UL) { printf("Ignore caches over %llx/%llx\n", - gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size); + gd->dram[i].start, + gd->dram[i].size); continue; } #endif - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index a81609cdec7..f65c231bdab 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info * * Transfers DRAM bank information from the global versal2_mem_map[] - * array to bd->bi_dram[] for passing memory configuration to the + * array to gd->dram[] for passing memory configuration to the * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical * address and size are copied. * @@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) */ void fill_bd_mem_info(void) { - struct bd_info *bd = gd->bd; int banks = VERSAL2_MEM_MAP_USED; for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { if (!versal2_mem_map[banks].size) break; - bd->bi_dram[i].start = versal2_mem_map[banks].phys; - bd->bi_dram[i].size = versal2_mem_map[banks].size; + gd->dram[i].start = versal2_mem_map[banks].phys; + gd->dram[i].size = versal2_mem_map[banks].size; banks++; } } diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 5f194aaff9a..3dc47e5d48e 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -92,12 +92,12 @@ void mem_map_fill(void) #if !defined(CONFIG_ZYNQMP_NO_DDR) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; + zynqmp_mem_map[banks].virt = gd->dram[i].start; + zynqmp_mem_map[banks].phys = gd->dram[i].start; + zynqmp_mem_map[banks].size = gd->dram[i].size; zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 5b1311d8b5b..817728aa569 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -41,8 +41,8 @@ int dram_init(void) * No DDR init yet -> run in L2 cache */ gd->ram_size = (4 << 20); - gd->bd->bi_dram[0].size = gd->ram_size; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = gd->ram_size; + gd->dram[1].size = 0; } return 0; diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index cc1e903c9dd..2893bc6b99a 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -56,12 +56,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; @@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - start[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + start[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 1668b58d3fb..460013f933b 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image); int dram_init_banksize(void) { /* These are necessary so TFTP can use LMBs to check its load address */ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index cc1edd7badd..81604ee12fb 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -91,8 +91,8 @@ int dram_init_banksize(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; if (memrange->type == CB_MEM_RAM) { - gd->bd->bi_dram[j].start = memrange->base; - gd->bd->bi_dram[j].size = memrange->size; + gd->dram[j].start = memrange->base; + gd->dram[j].size = memrange->size; j++; if (j >= CONFIG_NR_DRAM_BANKS) break; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 6845ce72ff9..b86d50b2cab 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -123,8 +123,8 @@ int dram_init_banksize(void) if (desc->type != EFI_CONVENTIONAL_MEMORY || (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) continue; - gd->bd->bi_dram[num_banks].start = desc->physical_start; - gd->bd->bi_dram[num_banks].size = desc->num_pages << + gd->dram[num_banks].start = desc->physical_start; + gd->dram[num_banks].size = desc->num_pages << EFI_PAGE_SHIFT; num_banks++; } diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 6fe40071140..e09fce8bb1b 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -24,8 +24,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = efi_get_ram_base(); - gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE; + gd->dram[0].start = efi_get_ram_base(); + gd->dram[0].size = CONFIG_EFI_RAM_SIZE; return 0; } diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index baa1f0e32d6..11ce97b5143 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void) if (area->start >= 1ULL << 32) continue; - gd->bd->bi_dram[num_banks].start = area->start; - gd->bd->bi_dram[num_banks].size = area->size; + gd->dram[num_banks].start = area->start; + gd->dram[num_banks].size = area->size; num_banks++; } } diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index d20c9a2a379..a5e81dfada5 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = 1ULL << 31; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index ba3638e6acc..3cba04f2c3e 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -69,13 +69,13 @@ int dram_init_banksize(void) { u64 high_mem_size; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = qemu_get_low_memory_size(); + gd->dram[0].start = 0; + gd->dram[0].size = qemu_get_low_memory_size(); high_mem_size = qemu_get_high_memory_size(); if (high_mem_size) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = high_mem_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = high_mem_size; } return 0; diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 34e576940d4..34fdb7e026a 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -169,8 +169,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index 75ca5273625..5aa4f6d3e07 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -129,8 +129,8 @@ int dram_init_banksize(void) return 0; /* simply use a single bank to have whole size for now */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 6192f2296b8..6ce96b0569b 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -160,8 +160,8 @@ static int sfi_get_bank_size(void) if (mentry->type != SFI_MEM_CONV) continue; - gd->bd->bi_dram[bank].start = mentry->phys_start; - gd->bd->bi_dram[bank].size = mentry->pages << 12; + gd->dram[bank].start = mentry->phys_start; + gd->dram[bank].size = mentry->pages << 12; bank++; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index cde4fbf3557..e054f42fa86 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void) #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) int arch_fixup_memory_node(void *blob) { - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 730721dc176..a45e4060ef2 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -64,8 +64,8 @@ int dram_init_banksize(void) update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); @@ -89,21 +89,21 @@ int dram_init_banksize(void) mtrr_top = max(mtrr_top, res_desc->phys_start + res_desc->len); } else { - gd->bd->bi_dram[bank].start = res_desc->phys_start; - gd->bd->bi_dram[bank].size = res_desc->len; + gd->dram[bank].start = res_desc->phys_start; + gd->dram[bank].size = res_desc->len; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, res_desc->len); log_debug("ram %llx %llx\n", - gd->bd->bi_dram[bank].start, - gd->bd->bi_dram[bank].size); + gd->dram[bank].start, + gd->dram[bank].size); } } /* Add the memory below 4GB */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = low_end; + gd->dram[0].start = 0; + gd->dram[0].size = low_end; /* * Set up an MTRR to the top of low, reserved memory. This is necessary @@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries, #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) int handoff_arch_save(struct spl_handoff *ho) { - ho->arch.usable_ram_top = gd->bd->bi_dram[0].size; + ho->arch.usable_ram_top = gd->dram[0].size; ho->arch.hob_list = gd->arch.hob_list; return 0; diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c index 2f9557a4170..32535ed6ee0 100644 --- a/board/CZ.NIC/turris_1x/turris_1x.c +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -42,9 +42,9 @@ int dram_init_banksize(void) static_assert(CONFIG_NR_DRAM_BANKS >= 3); - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - size -= gd->bd->bi_dram[0].size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); + size -= gd->dram[0].size; /* Note: This address space is not mapped via TLB entries in U-Boot */ @@ -68,16 +68,16 @@ int dram_init_banksize(void) if (size > 0) { /* Free space between PCIe bus 3 MEM and NOR */ - gd->bd->bi_dram[1].start = 0xc0200000; - gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start); - size -= gd->bd->bi_dram[1].size; + gd->dram[1].start = 0xc0200000; + gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start); + size -= gd->dram[1].size; } if (size > 0) { /* Free space between NOR and NAND */ - gd->bd->bi_dram[2].start = 0xf0000000; - gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start); - size -= gd->bd->bi_dram[2].size; + gd->dram[2].start = 0xf0000000; + gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start); + size -= gd->dram[2].size; } #else puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n"); @@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd) if (!env_get("bootm_low") && !env_get("bootm_size")) { for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) { - start[count] = gd->bd->bi_dram[count].start; - size[count] = gd->bd->bi_dram[count].size; + start[count] = gd->dram[count].start; + size[count] = gd->dram[count].size; if (!size[count]) break; } @@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void) size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size -= gd->bd->bi_dram[i].size; + size -= gd->dram[i].size; if (size == 0) return; e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3); - if (e.index < 0 && gd->bd->bi_dram[1].size > 0) { + if (e.index < 0 && gd->dram[1].size > 0) { /* * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller * is inactive, which is the case for Turris 1.0 boards. So @@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(bank_size, ""); printf(" of PCIe 3 MEM for DDR RAM\n"); - gd->bd->bi_dram[1].start -= bank_size; - gd->bd->bi_dram[1].size += bank_size; + gd->dram[1].start -= bank_size; + gd->dram[1].size += bank_size; size -= bank_size; if (size == 0) return; @@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size2, ""); printf(" of PCIe 2 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start2; - gd->bd->bi_dram[i].size = min(size, free_size2); - size -= gd->bd->bi_dram[i].start; + gd->dram[i].start = free_start2; + gd->dram[i].size = min(size, free_size2); + size -= gd->dram[i].start; i++; if (size == 0) return; @@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size1, ""); printf(" of PCIe 1 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start1; - gd->bd->bi_dram[i].size = min(size, free_size1); - size -= gd->bd->bi_dram[i].size; + gd->dram[i].start = free_start1; + gd->dram[i].size = min(size, free_size1); + size -= gd->dram[i].size; i++; if (size == 0) return; diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 16d0e679c3e..eb0f9c06849 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -86,8 +86,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index eaf87e3bfe3..6cd24bf25fb 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -170,7 +170,7 @@ extern void dram_query(void); PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ /* We only have one bank of RAM, set it to whatever was detected */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 12bb6defab2..057e916ab1b 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -89,9 +89,9 @@ void build_mem_map(void) * The first node is for I/O device, start from node 1 for * updating DRAM info. */ - mem_map[i + 1].virt = gd->bd->bi_dram[i].start; - mem_map[i + 1].phys = gd->bd->bi_dram[i].start; - mem_map[i + 1].size = gd->bd->bi_dram[i].size; + mem_map[i + 1].virt = gd->dram[i].start; + mem_map[i + 1].phys = gd->dram[i].start; + mem_map[i + 1].size = gd->dram[i].size; mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; } diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 3833af59b09..87e53f64e06 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -79,11 +79,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); return 0; diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 77188820581..7cb492b2da6 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -40,7 +40,7 @@ int at91_video_show_board_info(void) dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; + dram_size += gd->dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 43797d625e9..b19ae3b4b03 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -66,7 +66,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c index 364b6a3e24b..5c35239a90a 100644 --- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -45,7 +45,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 858061bf9f9..33ae6a76bf7 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -64,7 +64,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 19341d325bd..0e2d5592753 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -58,7 +58,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index 8759ff6f01a..1a17db1bd5b 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c0862f58606..b48e8fe7697 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -63,7 +63,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c index 764c8f035c9..cdf2793b643 100644 --- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -52,7 +52,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index b05c9754c96..02543d8e99f 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { // Address of boot parameters - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c index 4643ba4a55c..b2df6d89cd8 100644 --- a/board/axiado/scm3005/scm3005.c +++ b/board/axiado/scm3005/scm3005.c @@ -96,8 +96,8 @@ int dram_init(void) */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index bb2f1e4f62a..2683f46f41c 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -176,8 +176,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M); - gd->bd->bi_dram[0].size = SZ_16M; + gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M); + gd->dram[0].size = SZ_16M; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index e20350dc5d5..5bc4d3248bd 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -666,34 +666,34 @@ int misc_init_r(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[1].start = PHYS_SDRAM_2; switch (gd->ram_size) { case 0x10000000: /* DDR_16BIT_256MB */ - gd->bd->bi_dram[0].size = 0x10000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x10000000; + gd->dram[1].size = 0; break; case 0x20000000: /* DDR_32BIT_512MB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0; break; case 0x40000000: if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0x20000000; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0x20000000; } else { /* DDR_64BIT_1GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0; } break; case 0x80000000: /* DDR_64BIT_2GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0x40000000; break; case 0xEFF00000: /* DDR_64BIT_4GB */ - gd->bd->bi_dram[0].size = 0x70000000; - gd->bd->bi_dram[1].size = 0x7FF00000; + gd->dram[0].size = 0x70000000; + gd->dram[1].size = 0x7FF00000; break; } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 9fea4f86d5a..33f7ec6d048 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -66,8 +66,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0x60000000; - gd->bd->bi_dram[0].size = 0x8000000; + gd->dram[0].start = 0x60000000; + gd->dram[0].size = 0x8000000; return 0; } diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index dce69abdfd1..3d76c936073 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -141,8 +141,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index eb10cd5143d..5e560a7f927 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -532,17 +532,17 @@ int dram_init_banksize(void) /* set global data memory */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) - gd->bd->bi_dram[0].size -= 0x20000000; + gd->dram[0].size -= 0x20000000; /* Number of Memory Chips */ if ((reg_val & 0x3) > 1) { - gd->bd->bi_dram[1].start = 0x80000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[1].start = 0x80000000; + gd->dram[1].size = 0x40000000; } return 0; } diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cb9b88a1a58..d3a385bf6b7 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -71,11 +71,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 5e60ab9d7b7..ba0465cf96f 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -456,23 +456,23 @@ int dram_init_banksize(void) * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = 0x05e00000; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = 0x05e00000; - gd->bd->bi_dram[1].start = 0x05f00000; - gd->bd->bi_dram[1].size = 0x00001000; + gd->dram[1].start = 0x05f00000; + gd->dram[1].size = 0x00001000; - gd->bd->bi_dram[2].start = 0x05f02000; - gd->bd->bi_dram[2].size = 0x00efd000; + gd->dram[2].start = 0x05f02000; + gd->dram[2].size = 0x00efd000; - gd->bd->bi_dram[3].start = 0x06e00000; - gd->bd->bi_dram[3].size = 0x0060f000; + gd->dram[3].start = 0x06e00000; + gd->dram[3].size = 0x0060f000; - gd->bd->bi_dram[4].start = 0x07410000; - gd->bd->bi_dram[4].size = 0x1aaf0000; + gd->dram[4].start = 0x07410000; + gd->dram[4].size = 0x1aaf0000; - gd->bd->bi_dram[5].start = 0x22000000; - gd->bd->bi_dram[5].size = 0x1c000000; + gd->dram[5].start = 0x22000000; + gd->dram[5].size = 0x1c000000; return 0; } diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index fb56762fff6..e7908d4c048 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -74,8 +74,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index c3ea080ff75..dbab67d6f65 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -87,8 +87,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; - gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; + gd->dram[0].start = KERNEL_TEXT_OFFSET; + gd->dram[0].size = gd->ram_size - gd->dram[0].start; return 0; } diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index efb7b49cbe0..07668bae7a9 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -39,8 +39,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 51938a1b4d8..e37d4e767db 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,8 +84,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 8a9502037fb..ce778bc0849 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < nbanks; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } fdt_fixup_memory_banks(blob, base, size, nbanks); diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index 0710316a48b..cc741dea504 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start; - dram_regions_info.region[i].size = gd->bd->bi_dram[i].size; - dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size; + dram_regions_info.region[i].addr = gd->dram[i].start; + dram_regions_info.region[i].size = gd->dram[i].size; + dram_regions_info.total_dram_size += gd->dram[i].size; } bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index e1ff041c54f..ba922b43064 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -239,7 +239,7 @@ int spl_start_uboot(void) static const char *get_board_name(void) { - if (gd->bd->bi_dram[0].size == SZ_128M) + if (gd->dram[0].size == SZ_128M) return STR_BTTC; return STR_BTT3; diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index fc76d5765fa..5e76942783f 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -69,11 +69,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 05c4dd187fe..68d516c7db8 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) { phys_size_t ram_size = gd->ram_size; - gd->bd->bi_dram[0].start = 0; + gd->dram[0].start = 0; #if defined(CONFIG_SYS_MEM_TOP_HIDE) ram_size += CONFIG_SYS_MEM_TOP_HIDE; @@ -69,25 +69,25 @@ int dram_init_banksize(void) case DRAM_1GB_SIZE: case DRAM_2GB_ECC_SIZE: case DRAM_2GB_SIZE: - gd->bd->bi_dram[0].size = ram_size; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = ram_size; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; case DRAM_4GB_ECC_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE - + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE - (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE); break; case DRAM_4GB_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE; break; default: - gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = DRAM_1GB_SIZE; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; } diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c index 11dbef84688..6843b33679d 100644 --- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c index 056489932ac..19d068fc626 100644 --- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -78,7 +78,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c index 047aea8181a..3afd5ae2136 100644 --- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c index fd897e832c8..8d07f6110ce 100644 --- a/board/nxp/ls1021aqds/ddr.c +++ b/board/nxp/ls1021aqds/ddr.c @@ -192,8 +192,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index 196e25931f3..e1e83137f4d 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -149,7 +149,7 @@ int board_early_init_f(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -202,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index 0f115c16232..dba93add698 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c index bba041065b5..678c529cf55 100644 --- a/board/nxp/ls1043ardb/ls1043ardb.c +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0..6c35c0a4347 100644 --- a/board/nxp/ls1046afrwy/ls1046afrwy.c +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 679b0b2235f..ddd9993986f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c index 83b280f7646..6677e271029 100644 --- a/board/nxp/ls1046ardb/ls1046ardb.c +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 5783dd8a403..1b477e83676 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -830,7 +830,7 @@ int board_init(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -959,8 +959,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c index aba0560181a..325dc817aaf 100644 --- a/board/nxp/ls2080aqds/ls2080aqds.c +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -253,12 +253,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index d08598d1c62..9dec818280b 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -359,12 +359,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) size = calloc(total_memory_banks, sizeof(u64)); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index b7a6ccf46aa..10729dfaf24 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -573,7 +573,7 @@ void detail_board_ddr_info(void) puts("\nDDR "); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; + ddr_size += gd->dram[i].size; print_size(ddr_size, ""); print_ddr_info(0); } @@ -808,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 3cdcbf2ecc9..6df521d789f 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -93,7 +93,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -101,34 +101,34 @@ int dram_init_banksize(void) ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; case EEPROM_RAM_SIZE_4GB: /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR upper region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; + gd->dram[1].start = 0x880000000; + gd->dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -186,8 +186,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 114aa217023..5e077872152 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -66,7 +66,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -74,21 +74,21 @@ int dram_init_banksize(void) ram_size = phytec_get_am64_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -109,8 +109,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 9fc63febdac..a738e3542e2 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -31,8 +31,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index 6824454cdf4..421e193e730 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -44,8 +44,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index b0a1484c0fa..885c660a289 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -356,9 +356,9 @@ int dram_init_banksize(void) /* Update gd->ram_size to reflect total RAM across all banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (gd->bd->bi_dram[i].size == 0) + if (gd->dram[i].size == 0) break; - total_size += gd->bd->bi_dram[i].size; + total_size += gd->dram[i].size; } gd->ram_size = total_size; diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index 3d537be4d02..09667d46d99 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -49,15 +49,15 @@ int dram_init_banksize(void) return 0; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start != 0x48000000) + if (gd->dram[bank].start != 0x48000000) continue; /* * If this U-Boot runs in EL3, make the bottom 128 MiB * available for loading of follow up firmware blobs. */ - gd->bd->bi_dram[bank].start -= 0x8000000; - gd->bd->bi_dram[bank].size += 0x8000000; + gd->dram[bank].start -= 0x8000000; + gd->dram[bank].size += 0x8000000; break; } diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c index 8153aed15e3..9245bf348f8 100644 --- a/board/renesas/genmai/genmai.c +++ b/board/renesas/genmai/genmai.c @@ -43,7 +43,7 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index a229542ba7e..1503de675d5 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void) /* 16 GiB device, adjust memory map. */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start == 0x480000000ULL) - gd->bd->bi_dram[bank].size = 0x180000000ULL; - else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) - gd->bd->bi_dram[bank].size = 0x200000000ULL; + if (gd->dram[bank].start == 0x480000000ULL) + gd->dram[bank].size = 0x180000000ULL; + else if (gd->dram[bank].start == 0x600000000ULL) + gd->dram[bank].size = 0x200000000ULL; } } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 1f78654b685..7a0a93c1afe 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -103,8 +103,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index cc58e0f3a38..0ff49dceb9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -97,8 +97,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5d5edd9f253..b5664296a81 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -150,8 +150,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index e70b4a82687..130136e8596 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -67,8 +67,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index eed1c2450fa..da3510023c4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -115,7 +115,7 @@ int board_init(void) ulong size = CONFIG_SYS_MEM_TOP_HIDE; gd->ram_size -= size; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; + gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; #endif exynos_init(); @@ -143,8 +143,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c index 6b2b1523663..d91e2e7d3f2 100644 --- a/board/samsung/exynos-mobile/exynos-mobile.c +++ b/board/samsung/exynos-mobile/exynos-mobile.c @@ -346,8 +346,8 @@ int dram_init_banksize(void) unsigned int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mem_map[i + 1].phys; - gd->bd->bi_dram[i].size = mem_map[i + 1].size; + gd->dram[i].start = mem_map[i + 1].phys; + gd->dram[i].size = mem_map[i + 1].size; } return 0; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index a1047f3fd2a..96a411233d1 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -43,12 +43,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = PHYS_SDRAM_2_SIZE; + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = PHYS_SDRAM_3_SIZE; return 0; } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 7d0b0fcb0ae..7e992c23a1b 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -56,8 +56,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 5a4874b29cd..f013893b465 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,17 +57,17 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, + gd->dram[3].start = PHYS_SDRAM_4; + gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); return 0; diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 79cf34b40eb..69d3b9d61d3 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -397,20 +397,20 @@ int dram_init_banksize(void) if (gd->ram_size > SZ_2G) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = SZ_2G; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = SZ_2G; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->dram[1].size = gd->ram_size - SZ_2G; } else { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 556a9ed527e..a7bd08f69ad 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -170,11 +170,11 @@ int dram_init_banksize(void) struct draminfo_entry *ent = synquacer_draminfo->entry; int i; - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { if (i < synquacer_draminfo->nr_regions) { debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; + gd->dram[i].start = ent[i].base; + gd->dram[i].size = ent[i].size; } } diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index f5174720434..a1b0265d5ac 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -18,8 +18,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 826c002907d..66330184af8 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -70,8 +70,8 @@ int dram_init_banksize(void) if (t->hdr.tag != ATAG_MEM) continue; - gd->bd->bi_dram[bank].start = t->u.mem.start; - gd->bd->bi_dram[bank].size = t->u.mem.size; + gd->dram[bank].start = t->u.mem.start; + gd->dram[bank].size = t->u.mem.size; if (++bank == CONFIG_NR_DRAM_BANKS) break; } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 0966db2bb62..6f1fed43e36 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -643,11 +643,11 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); if (ram_size > CFG_MAX_MEM_MAPPED) { - gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; + gd->dram[1].start = 0x200000000; + gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index a92aa5cfc67..43330993955 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) } nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; + start[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; /* adjust memory start address for LPAE */ if (lpae) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 69a8a18d3a7..c63812bd966 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) * Reserve 1MB of memory for M4 (1MiB is also the minimum * alignment for Linux due to MMU section size restrictions). */ - start[0] = gd->bd->bi_dram[0].start; + start[0] = gd->dram[0].start; size[0] = SZ_256M - SZ_1M; /* If needed, create a second entry for memory beyond 256M */ - if (gd->bd->bi_dram[0].size > SZ_256M) { - start[1] = gd->bd->bi_dram[0].start + SZ_256M; - size[1] = gd->bd->bi_dram[0].size - SZ_256M; + if (gd->dram[0].size > SZ_256M) { + start[1] = gd->dram[0].start + SZ_256M; + size[1] = gd->dram[0].size - SZ_256M; areas = 2; } diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 19ac2ae9313..26af1af2069 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -44,7 +44,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 1234b3887c6..ec7775e06a7 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -78,7 +78,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index ac8c9a9a81a..5c45f9932c5 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -148,7 +148,7 @@ int fsl_initdram(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -277,8 +277,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; /* reduce size if reserved memory is within this bank */ if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i)) size[i] = gd->arch.resv_ram - base[i]; diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 05ecb75406b..d8eff203a56 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr) * This validation is just for PS DDR. * TODO: Update this for PL DDR check as well. */ - if (part_load_addr < gd->bd->bi_dram[0].start && + if (part_load_addr < gd->dram[0].start && ((part_load_addr + part_data_len) > - (gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size))) { + (gd->dram[0].start + + gd->dram[0].size))) { printf("INVALID_LOAD_ADDRESS_FAIL\n"); return -1; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index eb41f84c198..a12c039d8c9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -279,8 +279,8 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); mem_map_fill(); diff --git a/boot/image-board.c b/boot/image-board.c index 265f29d44ff..67938fdd200 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -118,7 +118,7 @@ phys_addr_t env_get_bootm_low(void) #if defined(CFG_SYS_SDRAM_BASE) return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) - return gd->bd->bi_dram[0].start; + return gd->dram[0].start; #else return 0; #endif diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 1150131a11e..9e0e0f93edd 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -260,8 +260,8 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) of_start = NULL; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* DRAM bank addresses are too low, skip it. */ if (start + size < low) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ddf77303735..bf1eca75904 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -77,15 +77,15 @@ void bdinfo_print_mhz(const char *name, unsigned long hz) printf("%-12s= %6s MHz\n", name, strmhz(buf, hz)); } -static void print_bi_dram(const struct bd_info *bd) +static void print_dram(const struct bd_info *bd) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { bdinfo_print_num_l("DRAM bank", i); - bdinfo_print_num_ll("-> start", bd->bi_dram[i].start); - bdinfo_print_num_ll("-> size", bd->bi_dram[i].size); + bdinfo_print_num_ll("-> start", gd->dram[i].start); + bdinfo_print_num_ll("-> size", gd->dram[i].size); } } } @@ -144,7 +144,7 @@ static int bdinfo_print_all(struct bd_info *bd) bdinfo_print_num_l("bd address", (ulong)bd); #endif bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params); - print_bi_dram(bd); + print_dram(bd); bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart); bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize); bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset); @@ -199,7 +199,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) print_eth(); return CMD_RET_SUCCESS; case 'm': - print_bi_dram(bd); + print_dram(bd); return CMD_RET_SUCCESS; default: return CMD_RET_USAGE; diff --git a/cmd/ti/ddr4.c b/cmd/ti/ddr4.c index a8d71d11a91..36277cc154c 100644 --- a/cmd/ti/ddr4.c +++ b/cmd/ti/ddr4.c @@ -227,10 +227,10 @@ static int do_ddr4_ecc_inject(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - if (!((start_addr >= gd->bd->bi_dram[0].start && - (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) || - (start_addr >= gd->bd->bi_dram[1].start && - (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) { + if (!((start_addr >= gd->dram[0].start && + (start_addr <= (gd->dram[0].start + gd->dram[0].size - 1))) || + (start_addr >= gd->dram[1].start && + (start_addr <= (gd->dram[1].start + gd->dram[1].size - 1))))) { puts("Address is not in the DDR range\n"); return CMD_RET_FAILURE; } diff --git a/cmd/ufetch.c b/cmd/ufetch.c index e7b5d773f5e..763ab42c48a 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -202,8 +202,8 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, printf("CPU: " RESET CONFIG_SYS_ARCH " (%d cores, 1 in use)\n", n_cpus); break; case MEMORY: - for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++) - size += gd->bd->bi_dram[j].size; + for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->dram[j].size; j++) + size += gd->dram[j].size; printf("Memory:" RESET " "); print_size(size, "\n"); break; diff --git a/common/board_f.c b/common/board_f.c index fdb3577fec0..a3abec35271 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -222,11 +222,11 @@ static int show_dram_config(void) debug("\nRAM Configuration:\n"); for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; debug("Bank #%d: %llx ", i, - (unsigned long long)(gd->bd->bi_dram[i].start)); + (unsigned long long)(gd->dram[i].start)); #ifdef DEBUG - print_size(gd->bd->bi_dram[i].size, "\n"); + print_size(gd->dram[i].size, "\n"); #endif } debug("\nDRAM: "); @@ -244,8 +244,8 @@ static int show_dram_config(void) __weak int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/common/init/handoff.c b/common/init/handoff.c index a7cd065fb38..a4d9d14393b 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -12,14 +12,13 @@ DECLARE_GLOBAL_DATA_PTR; void handoff_save_dram(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; ho->ram_size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ho->ram_bank[i].start = bd->bi_dram[i].start; - ho->ram_bank[i].size = bd->bi_dram[i].size; + ho->ram_bank[i].start = gd->dram[i].start; + ho->ram_bank[i].size = gd->dram[i].size; } } @@ -30,11 +29,10 @@ void handoff_load_dram_size(struct spl_handoff *ho) void handoff_load_dram_banks(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - bd->bi_dram[i].start = ho->ram_bank[i].start; - bd->bi_dram[i].size = ho->ram_bank[i].size; + gd->dram[i].start = ho->ram_bank[i].start; + gd->dram[i].size = ho->ram_bank[i].size; } } diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 33e157b865a..f726d9ab016 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -27,7 +27,7 @@ void bootcount_store(ulong a) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]); @@ -50,7 +50,7 @@ ulong bootcount_load(void) int i, tmp; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); counter = readl(&save_addr[0]); diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index b36a765a5de..2d2b72cf766 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -104,7 +104,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -ENXIO; @@ -158,7 +158,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_set_firewall(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index ee66c72157a..d14e4bc5dcc 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -302,7 +302,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, gd->bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); ret = -ENXIO; @@ -345,19 +345,19 @@ int sdram_mmr_init_full(struct udevice *dev) for (i = 0; i < config_dram_banks; i++) { remaining_size = hw_size - size_counter; if (remaining_size <= dram_bank_info[i].max_size) { - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = remaining_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = remaining_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + i, gd->dram[i].start, gd->dram[i].size); break; } - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = dram_bank_info[i].max_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = dram_bank_info[i].max_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); - size_counter += gd->bd->bi_dram[i].size; + i, gd->dram[i].start, gd->dram[i].size); + size_counter += gd->dram[i].size; } gd->ram_size = hw_size; @@ -408,7 +408,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: firewall init success\n"); - priv->info.base = gd->bd->bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c index 9b3cc5c7b86..e4d522202d8 100644 --- a/drivers/ddr/altera/sdram_agilex7m.c +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -375,7 +375,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); @@ -484,7 +484,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index c281f711fdf..9cc809b8001 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -674,9 +674,9 @@ static void sdram_size_check(void) debug("DDR: Running SDRAM size sanity check\n"); - ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, - gd->bd->bi_dram[0].size); - if (ram_check != gd->bd->bi_dram[0].size) { + ram_check = get_ram_size((long *)gd->dram[0].start, + gd->dram[0].size); + if (ram_check != gd->dram[0].size) { puts("DDR: SDRAM size check failed!\n"); hang(); } @@ -719,14 +719,14 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); - if (gd->ram_size != gd->bd->bi_dram[0].size) { + if (gd->ram_size != gd->dram[0].size) { printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", - gd->bd->bi_dram[0].size >> 20); + gd->dram[0].size >> 20); printf(" mismatch with hardware (%ld MiB).\n", gd->ram_size >> 20); } - if (gd->bd->bi_dram[0].size > gd->ram_size) { + if (gd->dram[0].size > gd->ram_size) { printf("DDR: Error: DRAM size from device tree is greater\n"); printf(" than hardware size.\n"); hang(); diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 17ec6afa82b..900d4f59989 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2279,7 +2279,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { debug("%s: Failed to decode memory node\n", __func__); return -1; @@ -2287,7 +2287,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; sdram_size_check(&bd); diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4ac4c79e0ac..6664090f86a 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -285,7 +285,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -1; @@ -328,7 +328,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_size_check(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8ee7049b164..93df3d1812a 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -150,8 +150,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) icache_enable(); - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; + start_addr = gd->dram[0].start; + size = gd->dram[0].size; /* Initialize small block for page table */ memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); @@ -174,8 +174,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) if (bank >= CONFIG_NR_DRAM_BANKS) break; - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + start_addr = gd->dram[bank].start; + size = gd->dram[bank].size; } dcache_disable(); @@ -198,12 +198,12 @@ void sdram_size_check(struct bd_info *bd) phys_addr_t start = 0; phys_size_t remaining_size; - start = bd->bi_dram[bank].start; - remaining_size = bd->bi_dram[bank].size; + start = gd->dram[bank].start; + remaining_size = gd->dram[bank].size; debug("Checking bank %d: start=0x%llx, size=0x%llx\n", bank, start, remaining_size); - while (ram_check < bd->bi_dram[bank].size) { + while (ram_check < gd->dram[bank].size) { phys_size_t size, test_size, detected_size; size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); @@ -232,7 +232,7 @@ void sdram_size_check(struct bd_info *bd) } ram_check += detected_size; - remaining_size = bd->bi_dram[bank].size - ram_check; + remaining_size = gd->dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -292,10 +292,10 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) u32 lower, upper; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -322,7 +322,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting non-secure MPU limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); @@ -354,10 +354,10 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) phys_size_t value; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -376,7 +376,7 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 5af1953cd14..89d511c1a6f 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if (size && attrib) { mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_CTRL_DATA(size, diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 107a33aa9f5..4dc738980cb 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -256,8 +256,8 @@ static void set_dram_access(struct mvgbe_registers *regs) win_param.access_ctrl = EWIN_ACCESS_FULL; win_param.high_addr = 0; /* Get bank base and size */ - win_param.base_addr = gd->bd->bi_dram[i].start; - win_param.size = gd->bd->bi_dram[i].size; + win_param.base_addr = gd->dram[i].start; + win_param.size = gd->dram[i].size; if (win_param.size == 0) win_param.enable = 0; else diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f58d542ef75..4bdd1f7477f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1126,14 +1126,14 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - phys_addr_t start = bd->bi_dram[i].start; + if (gd->dram[i].size) { + phys_addr_t start = gd->dram[i].start; if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY)) - start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start); + start = virt_to_phys((void *)(uintptr_t)gd->dram[i].start); pci_set_region(hose->regions + hose->region_count++, - start, start, bd->bi_dram[i].size, + start, start, gd->dram[i].size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } } diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 794a4168913..38ee17f063d 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -222,8 +222,8 @@ static void usb_brg_adrdec_setup(int index) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if ((size) && (attrib)) writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, attrib, MVCPU_WIN_ENABLE), diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743..a686faf9f58 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -81,8 +81,8 @@ cvbs: meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * ((1 << VPU_MAX_LOG2_BPP) / 8) + MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); - meson_fb.base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - meson_fb.fb_size; + meson_fb.base = gd->dram[0].start + + gd->dram[0].size - meson_fb.fb_size; /* Override the framebuffer address */ uc_plat->base = meson_fb.base; @@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt) * at the end of the RAM and we strip this portion from the kernel * allowed region */ - mem_start = gd->bd->bi_dram[0].start; - mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; + mem_start = gd->dram[0].start; + mem_size = gd->dram[0].size - meson_fb.fb_size; ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); if (ret) { eprintf("Cannot setup simplefb: Error reserving memory\n"); diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a69..ab36ee1595b 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = de2_plat->base - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2..fa492c661db 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob) * and e.g. Linux refuses to iomap RAM on ARM, see: * linux/arch/arm/mm/ioremap.c around line 301. */ - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = sunxi_display->fb_addr - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index ba6a10cf2ad..ad7ebb1bbc9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -457,6 +457,13 @@ struct global_data { */ struct upl *upl; #endif + /** + * @dram: array describing DRAM banks (start address and size for each bank) + */ + struct { /* RAM configuration */ + phys_addr_t start; + phys_size_t size; + } dram[CONFIG_NR_DRAM_BANKS]; }; #ifndef DO_DEPS_ONLY static_assert(sizeof(struct global_data) == GD_SIZE); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 8c619c1b74a..931fe2f3274 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -59,10 +59,6 @@ struct bd_info { #endif ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ - struct { /* RAM configuration */ - phys_addr_t start; - phys_size_t size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; }; #endif /* __ASSEMBLY__ */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a6aafb51854..36e330887cd 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -15,9 +15,9 @@ * Memory configurations */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 2bd1426c7d9..e823611d2e4 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -51,9 +51,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 14095b99f03..acd6eb6f8ac 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -86,9 +86,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 3707de254e1..65babf50546 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -81,9 +81,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/fdtdec.h b/include/fdtdec.h index 46eaa0da63c..51d9f14a9f2 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { }; struct bd_info; +struct global_data; /** * enum fdt_source_t - indicates where the devicetree came from @@ -974,7 +975,7 @@ int fdtdec_setup_mem_size_base(void); int fdtdec_setup_mem_size_base_lowest(void); /** - * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram + * fdtdec_setup_memory_banksize() - decode and populate gd->dram * * Decode the /memory 'reg' property to determine the address and size of the * memory banks. Use this data to populate the global data board info with the @@ -1256,12 +1257,12 @@ int board_fdt_blob_setup(void **fdtp); * @param basep Returns base address of first memory bank (NULL to * ignore) * @param sizep Returns total memory size (NULL to ignore) - * @param bd Updated with the memory bank information (NULL to skip) + * @param gd_ptr Updated with the memory bank information (NULL to skip) * Return: 0 if OK, -ve on error */ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd); + struct global_data *gd_ptr); /** * fdtdec_get_srcname() - Get the name of where the devicetree comes from diff --git a/include/init.h b/include/init.h index c31ebd83b85..23466d3f153 100644 --- a/include/init.h +++ b/include/init.h @@ -80,7 +80,7 @@ int dram_init(void); * dram_init_banksize() - Set up DRAM bank sizes * * This can be implemented by boards to set up the DRAM bank information in - * gd->bd->bi_dram(). It is called just before relocation, after dram_init() + * gd->dram[] It is called just before relocation, after dram_init() * is called. * * If this is not provided, a default implementation will try to set up a diff --git a/lib/fdtdec.c b/lib/fdtdec.c index d0a84b5034b..b91e067106d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1142,14 +1143,14 @@ int fdtdec_setup_memory_banksize(void) if (ret != 0) return -EINVAL; - gd->bd->bi_dram[bank].start = (phys_addr_t)res.start; - gd->bd->bi_dram[bank].size = + gd->dram[bank].start = (phys_addr_t)res.start; + gd->dram[bank].size = (phys_size_t)(res.end - res.start + 1); debug("%s: DRAM Bank #%d: start = %pap, size = %pap\n", __func__, bank, - &gd->bd->bi_dram[bank].start, - &gd->bd->bi_dram[bank].size); + &gd->dram[bank].start, + &gd->dram[bank].size); } return 0; @@ -1930,7 +1931,7 @@ int fdtdec_resetup(int *rescan) int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd) + gd_t *gd_ptr) { int addr_cells, size_cells; const u32 *cell, *end; @@ -1982,8 +1983,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } /* Note: if no matching subnode was found we use the parent node */ - if (bd) { - memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) * + if (gd_ptr) { + memset(gd_ptr->dram, '\0', sizeof(gd_ptr->dram[0]) * CONFIG_NR_DRAM_BANKS); } @@ -1999,8 +2000,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, if (addr_cells == 2) addr += (u64)fdt32_to_cpu(*cell++) << 32UL; addr += fdt32_to_cpu(*cell++); - if (bd) - bd->bi_dram[bank].start = addr; + if (gd_ptr) + gd_ptr->dram[bank].start = addr; if (basep && !bank) *basep = (phys_addr_t)addr; @@ -2022,8 +2023,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } } - if (bd) - bd->bi_dram[bank].size = size; + if (gd_ptr) + gd_ptr->dram[bank].size = size; total_size += size; } diff --git a/lib/lmb.c b/lib/lmb.c index 779df35eb9c..77440a48486 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -555,12 +555,12 @@ static void lmb_reserve_uboot_region(void) #endif for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - rsv_start < gd->bd->bi_dram[bank].start) + if (!gd->dram[bank].size || + rsv_start < gd->dram[bank].start) continue; /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; + bank_end = gd->dram[bank].start + + gd->dram[bank].size - 1; if (rsv_start > bank_end) continue; if (bank_end > end) @@ -615,7 +615,6 @@ static void lmb_add_memory(void) phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; - struct bd_info *bd = gd->bd; if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP)) return lmb_arch_add_memory(); @@ -625,22 +624,22 @@ static void lmb_add_memory(void) ram_top = 0x100000000ULL; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size = bd->bi_dram[i].size; + size = gd->dram[i].size; if (size) { - lmb_add(bd->bi_dram[i].start, size); + lmb_add(gd->dram[i].start, size); if (!IS_ENABLED(CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP)) continue; - bank_end = bd->bi_dram[i].start + size; + bank_end = gd->dram[i].start + size; /* * Reserve memory above ram_top as * no-overwrite so that it cannot be * allocated */ - if (bd->bi_dram[i].start >= ram_top) - lmb_reserve(bd->bi_dram[i].start, size, + if (gd->dram[i].start >= ram_top) + lmb_reserve(gd->dram[i].start, size, LMB_NOOVERWRITE); else if (bank_end > ram_top) lmb_reserve(ram_top, bank_end - ram_top, diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 7f4f1868c6a..7b7fb0894dd 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -138,16 +138,15 @@ static int lmb_test_dump_all(struct unit_test_state *uts) static int bdinfo_check_mem(struct unit_test_state *uts) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { ut_assertok(test_num_l(uts, "DRAM bank", i)); ut_assertok(test_num_ll(uts, "-> start", - bd->bi_dram[i].start)); + gd->dram[i].start)); ut_assertok(test_num_ll(uts, "-> size", - bd->bi_dram[i].size)); + gd->dram[i].size)); } } -- cgit v1.3.1 From 599fd74e0c5ac8e0c420b7a48b619d36dcf211d9 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 10 Jun 2026 13:24:22 +0000 Subject: mx7ulp_evk: Move environment variables to .env file Move the board environment from CFG_EXTRA_ENV_SETTINGS in the config header to board/nxp/mx7ulp_evk/mx7ulp_evk.env for better maintainability. The file is named after CONFIG_SYS_BOARD so it is selected automatically without setting CONFIG_ENV_SOURCE_FILE. The generated default environment is unchanged. This was verified by comparing the output of scripts/get_default_envs.sh before and after the change, which produced identical results. Signed-off-by: Aristo Chen Reviewed-by: Peng Fan --- board/nxp/mx7ulp_evk/mx7ulp_evk.env | 59 ++++++++++++++++++++++++++++++++++ include/configs/mx7ulp_evk.h | 63 ------------------------------------- 2 files changed, 59 insertions(+), 63 deletions(-) create mode 100644 board/nxp/mx7ulp_evk/mx7ulp_evk.env (limited to 'include/configs') diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env new file mode 100644 index 00000000000..f5a384a61de --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttyLP0 +initrd_high=0xffffffff +fdt_file=imx7ulp-evk.dtb +fdt_addr=0x63000000 +boot_fdt=try +earlycon=lpuart32,0x402D0010 +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + usb start; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 21dbec837f0..f36265f13e6 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -24,69 +24,6 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyLP0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ - "fdt_addr=0x63000000\0" \ - "boot_fdt=try\0" \ - "earlycon=lpuart32,0x402D0010\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "usb start; "\ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K -- cgit v1.3.1 From 4377bd764ca861479a33683457f3ecac7317dd16 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 10 Jun 2026 13:24:23 +0000 Subject: mx6ullevk: Move environment variables to .env file Move the board environment from CFG_EXTRA_ENV_SETTINGS in the config header to board/nxp/mx6ullevk/mx6ullevk.env for better maintainability. The file is named after CONFIG_SYS_BOARD so it is selected automatically without setting CONFIG_ENV_SOURCE_FILE. Drop the now unused linux/stringify.h include. The generated default environment is unchanged. This was verified by comparing the output of scripts/get_default_envs.sh before and after the change, which produced identical results. Signed-off-by: Aristo Chen Reviewed-by: Peng Fan --- board/nxp/mx6ullevk/mx6ullevk.env | 69 ++++++++++++++++++++++++++++++++++++ include/configs/mx6ullevk.h | 73 --------------------------------------- 2 files changed, 69 insertions(+), 73 deletions(-) create mode 100644 board/nxp/mx6ullevk/mx6ullevk.env (limited to 'include/configs') diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env new file mode 100644 index 00000000000..0fce3aaaa4e --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.env @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttymxc0 +initrd_high=0xffffffff +fdt_file=undefined +fdt_addr=0x83000000 +boot_fdt=try +ip_dyn=yes +videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdt_file = undefined; then + if test $board_name = ULZ-EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ulz-14x14-evk.dtb; + fi; + if test $board_name = EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ull-14x14-evk.dtb; + fi; + if test $fdt_file = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 88b535e1bd0..a535163fd19 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -9,7 +9,6 @@ #include #include -#include #include "mx6_common.h" #include @@ -23,78 +22,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - /* Miscellaneous configurable options */ /* Physical Memory Map */ -- cgit v1.3.1 From 8d21d74bdf1f43ba2e50234cbf37429b8b065b72 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 10 Jun 2026 13:24:24 +0000 Subject: mx6sabre: Move environment variables to .env files Move the shared environment from CFG_EXTRA_ENV_SETTINGS in mx6sabre_common.h to a common text environment fragment in include/env/nxp/mx6sabre_common.env. The mx6sabresd and mx6sabreauto board environments include this fragment and add their own console setting, which is the only board specific difference between them. The eMMC firmware update variables remain guarded by CONFIG_SUPPORT_EMMC_BOOT inside the fragment. The now unused CONSOLE_DEV defines and the linux/stringify.h include are dropped. The generated default environment is unchanged for both boards. This was verified by comparing the output of scripts/get_default_envs.sh before and after the change, which produced identical results. Signed-off-by: Aristo Chen Reviewed-by: Peng Fan --- board/nxp/mx6sabreauto/mx6sabreauto.env | 5 ++ board/nxp/mx6sabresd/mx6sabresd.env | 5 ++ include/configs/mx6sabre_common.h | 122 -------------------------------- include/configs/mx6sabreauto.h | 1 - include/configs/mx6sabresd.h | 1 - include/env/nxp/mx6sabre_common.env | 114 +++++++++++++++++++++++++++++ 6 files changed, 124 insertions(+), 124 deletions(-) create mode 100644 board/nxp/mx6sabreauto/mx6sabreauto.env create mode 100644 board/nxp/mx6sabresd/mx6sabresd.env create mode 100644 include/env/nxp/mx6sabre_common.env (limited to 'include/configs') diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env new file mode 100644 index 00000000000..31a16905ef5 --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc3 + +#include diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env new file mode 100644 index 00000000000..3608e931665 --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc0 + +#include diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ef2848b71f3..d3a57a10a16 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -8,133 +8,11 @@ #ifndef __MX6QSABRE_COMMON_CONFIG_H #define __MX6QSABRE_COMMON_CONFIG_H -#include - #include "mx6_common.h" /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev} 1; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdtfile = undefined; then " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ - "fi;\0" \ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index e491af3e927..b5602def87d 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -9,7 +9,6 @@ #define __MX6SABREAUTO_CONFIG_H #define CFG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e34947c94d0..1ea08f835dd 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -9,7 +9,6 @@ #define __MX6SABRESD_CONFIG_H #define CFG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" #include "mx6sabre_common.h" diff --git a/include/env/nxp/mx6sabre_common.env b/include/env/nxp/mx6sabre_common.env new file mode 100644 index 00000000000..5346cd4e953 --- /dev/null +++ b/include/env/nxp/mx6sabre_common.env @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +fdtfile=undefined +fdt_addr=0x18000000 +boot_fdt=try +ip_dyn=yes +dfuspi=dfu 0 sf 0:0:10000000:0 +dfu_alt_info_spl=spl raw 0x400 +dfu_alt_info_img=u-boot raw 0x10000 +dfu_alt_info=spl raw 0x400 +initrd_high=0xffffffff +splashimage=CONFIG_SYS_LOAD_ADDR +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +finduuid=part uuid mmc ${mmcdev}:2 uuid +update_sd_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if mmc dev ${mmcdev}; then + if ${get_cmd} ${update_sd_firmware_filename}; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#ifdef CONFIG_SUPPORT_EMMC_BOOT +emmcdev=2 +update_emmc_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if ${get_cmd} ${update_sd_firmware_filename}; then + if mmc dev ${emmcdev} 1; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#endif +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw +loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || + load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile} +mmcboot=echo Booting from mmc ...; + run finduuid; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdtfile}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdtfile = undefined; then + if test $board_name = SABREAUTO && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabreauto.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabresd.dtb; + fi; + if test $fdtfile = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; -- cgit v1.3.1 From 3ac3708d168e1f85616817aae077326a6786ab59 Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Thu, 11 Jun 2026 15:47:48 +0200 Subject: board: toradex: add initial support for aquila imx95 Add initial U-Boot support for Aquila iMX95 SoM. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Signed-off-by: Franz Schnyder Reviewed-by: Francesco Dolcini --- arch/arm/dts/imx95-aquila-dev-u-boot.dtsi | 40 + arch/arm/dts/imx95-aquila-dev.dts | 389 +++++++++ arch/arm/dts/imx95-aquila.dtsi | 1160 +++++++++++++++++++++++++++ arch/arm/mach-imx/imx9/Kconfig | 5 + board/toradex/aquila-imx95/Kconfig | 36 + board/toradex/aquila-imx95/MAINTAINERS | 11 + board/toradex/aquila-imx95/Makefile | 8 + board/toradex/aquila-imx95/aquila-imx95.c | 23 + board/toradex/aquila-imx95/aquila-imx95.env | 20 + board/toradex/aquila-imx95/spl.c | 75 ++ configs/aquila-imx95_defconfig | 186 +++++ doc/board/toradex/aquila-imx95.rst | 175 ++++ doc/board/toradex/index.rst | 1 + include/configs/aquila-imx95.h | 28 + 14 files changed, 2157 insertions(+) create mode 100644 arch/arm/dts/imx95-aquila-dev-u-boot.dtsi create mode 100644 arch/arm/dts/imx95-aquila-dev.dts create mode 100644 arch/arm/dts/imx95-aquila.dtsi create mode 100644 board/toradex/aquila-imx95/Kconfig create mode 100644 board/toradex/aquila-imx95/MAINTAINERS create mode 100644 board/toradex/aquila-imx95/Makefile create mode 100644 board/toradex/aquila-imx95/aquila-imx95.c create mode 100644 board/toradex/aquila-imx95/aquila-imx95.env create mode 100644 board/toradex/aquila-imx95/spl.c create mode 100644 configs/aquila-imx95_defconfig create mode 100644 doc/board/toradex/aquila-imx95.rst create mode 100644 include/configs/aquila-imx95.h (limited to 'include/configs') diff --git a/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi new file mode 100644 index 00000000000..92ec0d3efa3 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usb3 { + bootph-pre-ram; +}; + +&usb3_dwc3 { + bootph-pre-ram; + compatible = "fsl,imx95a-dwc3", "fsl,imx8mq-dwc3", "snps,dwc3"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + diff --git a/arch/arm/dts/imx95-aquila-dev.dts b/arch/arm/dts/imx95-aquila-dev.dts new file mode 100644 index 00000000000..3df17700b63 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include +#include +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Development Board"; + compatible = "toradex,aquila-imx95-dev", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 as RS485 */ +&lpuart7 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-aquila.dtsi b/arch/arm/dts/imx95-aquila.dtsi new file mode 100644 index 00000000000..69dc962a24a --- /dev/null +++ b/arch/arm/dts/imx95-aquila.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + */ + +#include +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + can3 = &flexcan4; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + i2c0 = &lpi2c3; + i2c1 = &lpi2c2; + i2c2 = &i3c2; + i2c3 = &lpi2c8; + i2c4 = &lpi2c4; + i2c6 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart3; + serial1 = &lpuart7; + serial2 = &lpuart1; + serial3 = &lpuart2; + usb0 = &usb3; + usb1 = &usb2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# */ + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + wakeup-source; + linux,code = ; + }; + }; + + clk_dsi2dp_refclk: clock-dsi2dp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>; + clocks = <&clk_dsi2dp_refclk>; + #clock-cells = <0>; + /* CTRL_DP_CLK_EN */ + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clk_serdes_eth_ref: clock-serdes-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY */ + enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + reg_dp_1p2v: regulator-dp-1p2v { + compatible = "regulator-fixed"; + /* CTRL_DP_BRIDGE_EN */ + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_1p8v>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_1_EN */ + gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_2_EN */ + gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_H_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + /* PMIC_SD_1_VSEL */ + gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PMIC_SD_1_VSEL"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan4>; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_8bit>, + <&pinctrl_qspi_cs1>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_C24", /* 10 */ + "", + "AQUILA_B17", + "CTRL_GPIO_EXP_INT#", + "AQUILA_B18"; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "AQUILA_B42", + "", + "AQUILA_B43"; +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_A11", + "", /* 20 */ + "AQUILA_B57", + "AQUILA_B19"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "AQUILA_C22", + "AQUILA_C21", + "AQUILA_C20", + "", /* 20 */ + "", + "", + "AQUILA_C23", + "AQUILA_D23", + "AQUILA_D24", + "", + "AQUILA_D25"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "AQUILA_B44", + "AQUILA_B45"; +}; + +/* Aquila I2C_2 */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <100000>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* On-module I2C - I2C_SOM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C38", /* 0 */ + "PCIE_2_RESET#", + "AQUILA_B77", + "USB_2_H_EN", + "BT_DISABLE#", + "WIFI_DISABLE#", + "CTRL_ETH_REF_CLK_STBY", + "CTRL_DP_BRIDGE_EN"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C1", /* 0 */ + "AQUILA_C2", + "AQUILA_C3", + "AQUILA_C4", + "AQUILA_C36", + "AQUILA_B74", + "AQUILA_B75", + "USB_2_H_OC#", + "AQUILA_B81", + "PMIC_SD_1_VSEL", + "ETH_1_INT#", /* 10 */ + "CTRL_TPM_INT#", + "SPI_2_CS2_TPM", + "PCIE_WAKE_WIFI#", + "WIFI_WAKE_BT", + "WIFI_WAKEUP_HOST"; + }; + + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_refclk_en>; + clock-names = "refclk"; + vcc-supply = <®_dp_1p2v>; + vcca-supply = <®_dp_1p2v>; + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila SPI_2 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi4's per-clock (2x the max speed) is 24 MHz. + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Aquila UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Aquila UART_1 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Aquila UART_2 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>; +}; + +/* On-module Wi-Fi or Aquila PCIE_2 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Aquila PWM_1 */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Aquila PWM_2 */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; +}; + +/* Aquila USB_1 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Aquila SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = ; /* Aquila D6 */ + }; + + pinctrl_ctrl_dp_clk_en: dpclkengrp { + fsl,pins = ; /* CTRL_DP_CLK_EN */ + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_emdio: emdiogrp { + fsl,pins = , /* Aquila B90 */ + ; /* Aquila B89 */ + }; + + /* Aquila ETH_1 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = , /* ENET1_TX_CTL */ + , /* ENET1_TXC */ + , /* ENET1_TDO */ + , /* ENET1_TD1 */ + , /* ENET1_TD2 */ + , /* ENET1_TD3 */ + , /* ENET1_RX_CTL */ + , /* ENET1_RXC */ + , /* ENET1_RD0 */ + , /* ENET1_RD1 */ + , /* ENET1_RD2 */ + ; /* ENET1_RD3 */ + }; + + /* Aquila CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , /* Aquila B48 */ + ; /* Aquila B49 */ + }; + + /* Aquila CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , /* Aquila B50 */ + ; /* Aquila B51 */ + }; + + /* Aquila CAN_3 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = , /* Aquila B53 */ + ; /* Aquila B54 */ + }; + + /* Aquila CAN_4 */ + pinctrl_flexcan4: flexcan4grp { + fsl,pins = , /* Aquila B55 */ + ; /* Aquila B56 */ + }; + + /* Aquila QSPI_1 (4 bit) */ + pinctrl_flexspi1_4bit: flexspi14bitgrp { + fsl,pins = , /* Aquila B65 */ + , /* Aquila B68 */ + , /* Aquila B67 */ + , /* Aquila B61 */ + , /* Aquila B60 */ + ; /* Aquila B63 */ + }; + + /* Aquila QSPI_1 (8 bit) */ + pinctrl_flexspi1_8bit: flexspi18bitgrp { + fsl,pins = , /* Aquila B65 */ + , /* Aquila B68 */ + , /* Aquila B67 */ + , /* Aquila B61 */ + , /* Aquila B60 */ + , /* Aquila B70 */ + , /* Aquila B71 */ + , /* Aquila B72 */ + , /* Aquila B73 */ + ; /* Aquila B63 */ + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_1: gpio1grp { + fsl,pins = ; /* Aquila D23 */ + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_2: gpio2grp { + fsl,pins = ; /* Aquila D24 */ + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_3: gpio3grp { + fsl,pins = ; /* Aquila D25 */ + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_4: gpio4grp { + fsl,pins = ; /* Aquila C20 */ + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_5: gpio5grp { + fsl,pins = ; /* Aquila C21 */ + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_6: gpio6grp { + fsl,pins = ; /* Aquila C22 */ + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_7: gpio7grp { + fsl,pins = ; /* Aquila C23 */ + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_8: gpio8grp { + fsl,pins = ; /* Aquila C24 */ + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_9_csi_1: gpio9csi1grp { + fsl,pins = ; /* Aquila B17 */ + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: gpio10csi1grp { + fsl,pins = ; /* Aquila B18 */ + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: gpio11csi1grp { + fsl,pins = ; /* Aquila A11*/ + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: gpio12csi1grp { + fsl,pins = ; /* Aquila B19 */ + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: gpio17dsi1grp { + fsl,pins = ; /* Aquila B42 */ + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: gpio18dsi1grp { + fsl,pins = ; /* Aquila B43 */ + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: gpio19dsi1grp { + fsl,pins = ; /* Aquila B44 */ + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: gpio20dsi1grp { + fsl,pins = ; /* Aquila B45 */ + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: gpio21dpgrp { + fsl,pins = ; /* Aquila B57 */ + }; + + pinctrl_ctrl_gpio_exp_int: gpioexpintgrp { + fsl,pins = ; /* CTRL_GPIO_EXP_INT# */ + }; + + /* Aquila I2C_2 */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = , /* Aquila C17 */ + ; /* Aquila C16 */ + }; + + /* Aquila I2C_1 as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = , /* Aquila D8 */ + ; /* Aquila D7 */ + }; + + /* Aquila I2C_1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , /* Aquila D8 */ + ; /* Aquila D7 */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = , /* I2C_SOM_SDA */ + ; /* I2C_SOM_SCL */ + }; + + /* On-module I2C */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , /* I2C_SOM_SDA */ + ; /* I2C_SOM_SCL */ + }; + + /* Aquila I2C_4_CSI1 as GPIO */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = , /* Aquila A12 */ + ; /* Aquila A13 */ + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , /* Aquila A12 */ + ; /* Aquila A13 */ + }; + + /* Aquila I2C_6 as GPIO */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = , /* Aquila C18 */ + ; /* Aquila C19 */ + }; + + /* Aquila I2C_6 */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = , /* Aquila C18 */ + ; /* Aquila C19 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */ + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = , /* Aquila C5/B40 */ + ; /* Aquila C6/B41 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 */ + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = , /* Aquila C5/B40 */ + ; /* Aquila C6/B41 */ + }; + + /* Aquila SPI_2 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = , /* Aquila D16 */ + , /* Aquila D15 */ + , /* Aquila D17 */ + ; /* Aquila D14 */ + }; + + /* Aquila SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = , /* Aquila D9 */ + , /* Aquila D10 */ + , /* Aquila D11 */ + ; /* Aquila D12 */ + }; + + /* Aquila PCIE_1 */ + pinctrl_pcie0: pcie0grp { + fsl,pins = ; /* Aquila C37 */ + }; + + /* Aquila PCIE_2 */ + pinctrl_pcie1: pcie1grp { + fsl,pins = ; /* Aquila C34 */ + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_qspi_cs1: qspics1grp { + fsl,pins = ; /* Aquila B66 */ + }; + + /* Aquila QSPI_1_CS2# as GPIO */ + pinctrl_qspi_cs2_gpio: qspics2gpiogrp { + fsl,pins = ; /* Aquila B62 */ + }; + + /* Aquila I2S_1 */ + pinctrl_sai2: sai2grp { + fsl,pins = , /* Aquila B21 */ + , /* Aquila B20 */ + , /* Aquila B23 */ + ; /* Aquila B22 */ + }; + + pinctrl_sai2_mclk: sai2mclkgrp { + fsl,pins = ; /* Aquila B24 */ + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: sd1cdgpiogrp { + fsl,pins = ; /* Aquila A1 */ + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: sd1pwrengpiogrp { + fsl,pins = ; /* Aquila A6 */ + }; + + /* Aquila PWM_1 */ + pinctrl_pwm1: tpm3ch3grp { + fsl,pins = ; /* Aquila C25 */ + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp { + fsl,pins = ; /* Aquila B46 */ + }; + + /* Aquila PWM_3_DSI */ + pinctrl_pwm3_dsi: tpm5ch0grp { + fsl,pins = ; /* Aquila B46 */ + }; + + /* Aquila PWM_4_DP */ + pinctrl_pwm4_dp: tpm5ch3grp { + fsl,pins = ; /* Aquila B58 */ + }; + + /* Aquila PWM_2 */ + pinctrl_pwm2: tpm6ch0grp { + fsl,pins = ; /* Aquila C26 */ + }; + + /* Aquila UART_3 */ + pinctrl_uart1: uart1grp { + fsl,pins = , /* Aquila D20 */ + ; /* Aquila D19 */ + }; + + /* Aquila UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = , /* Aquila D22 */ + ; /* Aquila D21 */ + }; + + /* Aquila UART_1 */ + pinctrl_uart3: uart3grp { + fsl,pins = , /* Aquila B37 */ + , /* Aquila B35 */ + , /* Aquila B36 */ + ; /* Aquila B38 */ + }; + + /* Aquila UART_2 */ + pinctrl_uart7: uart7grp { + fsl,pins = , /* Aquila B33 */ + , /* Aquila B31 */ + , /* Aquila B32 */ + ; /* Aquila B34 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , /* eMMC_CLK */ + , /* eMMC_CMD */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + ; /* eMMC_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , /* eMMC_CLK */ + , /* eMMC_CMD */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + ; /* eMMC_STROBE */ + }; + + /* Aquila SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; +}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index ee22e411cd6..cbd0078ba2a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -173,6 +173,10 @@ config TARGET_IMX943_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_AQUILA_IMX95 + bool "Support Toradex Aquila iMX95" + select IMX95 + config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 @@ -206,6 +210,7 @@ source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" +source "board/toradex/aquila-imx95/Kconfig" source "board/toradex/smarc-imx95/Kconfig" source "board/toradex/verdin-imx95/Kconfig" source "board/nxp/imx952_evk/Kconfig" diff --git a/board/toradex/aquila-imx95/Kconfig b/board/toradex/aquila-imx95/Kconfig new file mode 100644 index 00000000000..5936946e1af --- /dev/null +++ b/board/toradex/aquila-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_AQUILA_IMX95 + +config SYS_BOARD + default "aquila-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "aquila-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/aquila-imx95/MAINTAINERS b/board/toradex/aquila-imx95/MAINTAINERS new file mode 100644 index 00000000000..d2a74a53f5e --- /dev/null +++ b/board/toradex/aquila-imx95/MAINTAINERS @@ -0,0 +1,11 @@ +Aquila iMX95 +F: arch/arm/dts/imx95-aquila.dtsi +F: arch/arm/dts/imx95-aquila-dev.dts +F: arch/arm/dts/imx95-aquila-dev-u-boot.dtsi +F: board/toradex/aquila-imx95/ +F: configs/aquila-imx95_defconfig +F: doc/board/toradex/aquila-imx95.rst +F: include/configs/aquila-imx95.h +M: Francesco Dolcini +S: Maintained +W: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 diff --git a/board/toradex/aquila-imx95/Makefile b/board/toradex/aquila-imx95/Makefile new file mode 100644 index 00000000000..caaf09465c8 --- /dev/null +++ b/board/toradex/aquila-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += aquila-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c new file mode 100644 index 00000000000..0c6473e4b3a --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.env b/board/toradex/aquila-imx95/aquila-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/aquila-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/configs/aquila-imx95_defconfig b/configs/aquila-imx95_defconfig new file mode 100644 index 00000000000..bb3d475ef4d --- /dev/null +++ b/configs/aquila-imx95_defconfig @@ -0,0 +1,186 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx95-aquila-dev" +CONFIG_TARGET_AQUILA_IMX95=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204d6000 +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTDELAY=1 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -b" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n \"${fdtfile}\" || setenv fdtfile imx95-aquila-${fdt_board}.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set +CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="Aquila iMX95 # " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_VERSION_VARIABLE=y +CONFIG_PROT_UDP=y +CONFIG_IP_DEFRAG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x90400000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_SM_CPU=y +CONFIG_IMX_SM_LMM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_IMX=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_SDP_LOADADDR=0x90400000 +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_SHA1 is not set +CONFIG_LZO=y diff --git a/doc/board/toradex/aquila-imx95.rst b/doc/board/toradex/aquila-imx95.rst new file mode 100644 index 00000000000..edd40252657 --- /dev/null +++ b/doc/board/toradex/aquila-imx95.rst @@ -0,0 +1,175 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Toradex Aquila iMX95 Module +=========================== + +- SoM: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 +- Carrier board: https://www.toradex.com/products/carrier-board/aquila-development-board-kit + +Quick Start +----------- + +- Setup environment +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: console + + $ export TOOLS= + $ export CROSS_COMPILE_32=arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=aarch64-none-linux-gnu- + +Get ahab-container.img +---------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: `$srctree` is the U-Boot source directory +Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/ + $ cd imx-oei-toradex + + $ make board=toradex-aquila-imx95 oei=ddr DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/ddr/oei-m33-ddr.bin $(srctree) + + $ make board=toradex-aquila-imx95 oei=tcm DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/tcm/oei-m33-tcm.bin $(srctree) + +The Makefile will set `DDR_CONFIG` automatically based on the selected silicon +revision. + +Get and Build the System Manager Image +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/ + $ cd imx-sm-toradex + $ make config=aquila-imx95 all + $ cp build/aquila-imx95/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx95 bl31 + $ cp build/imx95/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ make aquila-imx95_defconfig + $ make + +Flash to eMMC +------------- + +.. code-block:: console + + > tftpboot ${loadaddr} flash.bin + > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt} + +As a convenience, instead of the last two commands, one may also use the update +U-Boot wrapper: + +.. code-block:: console + + > run update_uboot + +Boot +---- + +Boot sequence is: + +* SPL ---> ATF (TF-A) ---> U-Boot proper + +Output: + +.. code-block:: console + + U-Boot SPL 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + SYS Boot reason: por, origin: -1, errid: -1 + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + Trying to boot from MMC1 + Load image from MMC/SD 0xd2800 + NOTICE: BL31: v2.10.0 (release):lf-6.6.52-2.2.1-dirty + NOTICE: BL31: Built : 06:40:36, Jul 7 2025 + + + U-Boot 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + + CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data + DRAM: 7.8 GiB + Core: 321 devices, 30 uclasses, devicetree: separate + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + MMC: FSL_SDHC: 0, FSL_SDHC: 1 + Loading Environment from MMC... Reading from MMC(0)... OK + In: serial@44380000 + Out: serial@44380000 + Err: serial@44380000 + Model: Toradex 0098 Aquila iMX95 Hexa 8GB WB IT V1.0A + Serial#: 12594391 + + BuildInfo: + - ELE firmware version 2.0.2-c110ba4b + + Net: WARNING: no MAC address assigned for MAC0 + imx_get_mac_from_fuse: fuse read err: 0 + eth0: enetc-0 [PRIME] + Hit any key to stop autoboot: 0 + Aquila iMX95 # diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 2a45bde6991..c5955ea1ad8 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -8,6 +8,7 @@ Toradex apalis-imx8 aquila-am69 + aquila-imx95 colibri_imx7 colibri-imx8x smarc-imx8mp diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h new file mode 100644 index 00000000000..07d09d138cb --- /dev/null +++ b/include/configs/aquila-imx95.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) Toradex */ + +#ifndef __AQUILA_IMX95_H +#define __AQUILA_IMX95_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +#define SZ_6G _AC(0x180000000, ULL) + +/* first 256MB reserved for firmware */ +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define PHYS_SDRAM_2_SIZE SZ_6G + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif -- cgit v1.3.1 From b62b55ba4b2d1cabd6bb0943685c3115f6ee8bd3 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 17:43:09 +0800 Subject: arm: aspeed: add ASPEED AST2700 SoC family support Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35) Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th generation BMC and uses a dual-die architecture: SoC0 (the "CPU" die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000, while SoC1 (the "IO" die) hosts the peripherals and its own SCU at 0x14c02000. This commit adds: - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*) - arm64 MMU map covering the SoC device window and the DRAM region at 0x4_0000_0000 (up to 8 GiB) - lowlevel_init.S for early CPU bring-up - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants) and reset cause (cold reset, EXT reset, WDT reset) - board_common: dram_init via UCLASS_RAM, AHBC timeout init - platform: env_get_location() that selects SPI/eMMC based on the IO-die HW strap; arch_misc_init() that exposes ${boot_device} and ${verify} to the boot script - SCU0/SCU1 register layout header (scu_ast2700.h) - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h for the AST2700 EVB board The defconfig depends on ast2700-evb.dts, which is introduced in a subsequent patch; this commit must be applied with the remaining series for evb-ast2700_defconfig to build. Signed-off-by: Ryan Chen --- MAINTAINERS | 1 + arch/arm/include/asm/arch-aspeed/platform.h | 30 +- arch/arm/include/asm/arch-aspeed/scu_ast2700.h | 514 +++++++++++++++++++++++++ arch/arm/mach-aspeed/Kconfig | 11 + arch/arm/mach-aspeed/Makefile | 1 + arch/arm/mach-aspeed/ast2700/Kconfig | 36 ++ arch/arm/mach-aspeed/ast2700/Makefile | 2 + arch/arm/mach-aspeed/ast2700/arm64-mmu.c | 43 +++ arch/arm/mach-aspeed/ast2700/board_common.c | 90 +++++ arch/arm/mach-aspeed/ast2700/cpu-info.c | 114 ++++++ arch/arm/mach-aspeed/ast2700/lowlevel_init.S | 132 +++++++ arch/arm/mach-aspeed/ast2700/platform.c | 64 +++ board/aspeed/evb_ast2700/Kconfig | 13 + board/aspeed/evb_ast2700/Makefile | 1 + board/aspeed/evb_ast2700/evb_ast2700.c | 5 + configs/evb-ast2700_defconfig | 160 ++++++++ include/configs/evb_ast2700.h | 58 +++ 17 files changed, 1274 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2700.h create mode 100644 arch/arm/mach-aspeed/ast2700/Kconfig create mode 100644 arch/arm/mach-aspeed/ast2700/Makefile create mode 100644 arch/arm/mach-aspeed/ast2700/arm64-mmu.c create mode 100644 arch/arm/mach-aspeed/ast2700/board_common.c create mode 100644 arch/arm/mach-aspeed/ast2700/cpu-info.c create mode 100644 arch/arm/mach-aspeed/ast2700/lowlevel_init.S create mode 100644 arch/arm/mach-aspeed/ast2700/platform.c create mode 100644 board/aspeed/evb_ast2700/Kconfig create mode 100644 board/aspeed/evb_ast2700/Makefile create mode 100644 board/aspeed/evb_ast2700/evb_ast2700.c create mode 100644 configs/evb-ast2700_defconfig create mode 100644 include/configs/evb_ast2700.h (limited to 'include/configs') diff --git a/MAINTAINERS b/MAINTAINERS index 571af196465..8da42bfdc60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -224,6 +224,7 @@ F: drivers/ram/aspeed/ F: drivers/reset/reset-ast2500.c F: drivers/watchdog/ast_wdt.c N: aspeed +N: ast2700 ARM BROADCOM BCM283X / BCM27XX M: Matthias Brugger diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h index 589abd4a3f6..82699c03c00 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -18,8 +18,36 @@ #define ASPEED_DRAM_BASE 0x80000000 #define ASPEED_SRAM_BASE 0x10000000 #define ASPEED_SRAM_SIZE 0x16000 +#elif defined(CONFIG_ASPEED_AST2700) +#define ASPEED_CPU_AHBC_BASE 0x12000000 +#define ASPEED_CPU_REVISION_ID 0x12C02000 +#define ASPEED_CPU_SCU_BASE 0x12C02000 +#define ASPEED_CPU_HW_STRAP1 0x12C02010 +#define ASPEED_CPU_RESET_LOG1 0x12C02050 +#define ASPEED_CPU_RESET_LOG2 0x12C02060 +#define ASPEED_CPU_RESET_LOG3 0x12C02070 +#define ASPEED_MAC_COUNT 3 +#define ASPEED_DRAM_BASE 0x400000000 +#define ASPEED_SRAM_BASE 0x10000000 +#define ASPEED_SRAM_SIZE 0x20000 +#define ASPEED_FMC_REG_BASE 0x14000000 +#define ASPEED_FMC_CS0_BASE 0x100000000 +#define ASPEED_FMC_CS0_SIZE 0x80000000 +#define ASPEED_IO_MAC0_BASE 0x14050000 +#define ASPEED_IO_MAC1_BASE 0x14060000 +#define ASPEED_IO_AHBC_BASE 0x140b0000 +#define ASPEED_IO_REVISION_ID 0x14C02000 +#define CHIP_AST2700A1_ID_MASK BIT(16) +#define ASPEED_IO_SCU_BASE 0x14C02000 +#define ASPEED_IO_HW_STRAP1 0x14C02010 +#define ASPEED_IO_RESET_LOG1 0x14C02050 +#define ASPEED_IO_RESET_LOG2 0x14C02060 +#define ASPEED_IO_RESET_LOG3 0x14C02070 +#define ASPEED_IO_RESET_LOG4 0x14C02080 +#define ASPEED_IO_GPIO_BASE 0x14C0B000 +#define ASPEED_WDTA_BASE 0x14C37400 #else -#err "Unrecognized Aspeed platform." +#error "Unrecognized Aspeed platform." #endif #endif diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2700.h b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h new file mode 100644 index 00000000000..b973fcc6610 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h @@ -0,0 +1,514 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SCU_AST2700_H +#define _ASM_ARCH_SCU_AST2700_H + +#include + +/* SoC0 SCU Register */ +#define SCU_CPU_REVISION_ID_HW GENMASK(23, 16) +#define SCU_CPU_REVISION_ID_EFUSE GENMASK(15, 8) + +#define SCU_CPU_HWSTRAP_DIS_RVAS BIT(30) +#define SCU_CPU_HWSTRAP_DP_SRC BIT(29) +#define SCU_CPU_HWSTRAP_DAC_SRC BIT(28) +#define SCU_CPU_HWSTRAP_VRAM_SIZE GENMASK(11, 10) +#define SCU_CPU_HWSTRAP_DIS_CPU BIT(0) + +#define SCU_CPU_MISC_DP_RESET_SRC BIT(11) +#define SCU_CPU_MISC_XDMA_CLIENT_EN BIT(4) +#define SCU_CPU_MISC_2D_CLIENT_EN BIT(3) + +#define SCU_CPU_RST_SSP BIT(30) +#define SCU_CPU_RST_DPMCU BIT(29) +#define SCU_CPU_RST_DP BIT(28) +#define SCU_CPU_RST_XDMA1 BIT(26) +#define SCU_CPU_RST_XDMA0 BIT(25) +#define SCU_CPU_RST_EMMC BIT(17) +#define SCU_CPU_RST_EN_DP_PCI BIT(15) +#define SCU_CPU_RST_CRT BIT(13) +#define SCU_CPU_RST_RVAS1 BIT(10) +#define SCU_CPU_RST_RVAS0 BIT(9) +#define SCU_CPU_RST_2D BIT(7) +#define SCU_CPU_RST_VIDEO BIT(6) +#define SCU_CPU_RST_SOC BIT(5) +#define SCU_CPU_RST_DDRPHY BIT(1) + +#define SCU_CPU_RST2_VGA BIT(12) +#define SCU_CPU_RST2_E2M1 BIT(11) +#define SCU_CPU_RST2_E2M0 BIT(10) +#define SCU_CPU_RST2_TSP BIT(9) + +#define SCU_CPU_VGA_FUNC_DAC_OUTPUT GENMASK(11, 10) +#define SCU_CPU_VGA_FUNC_DP_OUTPUT GENMASK(9, 8) +#define SCU_CPU_VGA_FUNC_DAC_DISABLE BIT(7) + +#define SCU_CPU_PCI_MISC0C_FB_SIZE GENMASK(4, 0) + +#define SCU_CPU_PCI_MISC70_EN_XHCI BIT(3) +#define SCU_CPU_PCI_MISC70_EN_EHCI BIT(2) +#define SCU_CPU_PCI_MISC70_EN_IPMI BIT(1) +#define SCU_CPU_PCI_MISC70_EN_VGA BIT(0) + +#define SCU_CPU_HPLL_P GENMASK(22, 19) +#define SCU_CPU_HPLL_N GENMASK(18, 13) +#define SCU_CPU_HPLL_M GENMASK(12, 0) + +#define SCU_CPU_HPLL2_LOCK BIT(31) +#define SCU_CPU_HPLL2_BWADJ GENMASK(11, 0) + +#define SCU_CPU_SSP_TSP_RESET_STS BIT(8) +#define SCU_CPU_SSP_TSP_SRAM_SD BIT(7) +#define SCU_CPU_SSP_TSP_SRAM_DSLP BIT(6) +#define SCU_CPU_SSP_TSP_SRAM_SLP BIT(5) +#define SCU_CPU_SSP_TSP_NIDEN BIT(4) +#define SCU_CPU_SSP_TSP_DBGEN BIT(3) +#define SCU_CPU_SSP_TSP_DBG_ENABLE BIT(2) +#define SCU_CPU_SSP_TSP_RESET BIT(1) +#define SCU_CPU_SSP_TSP_ENABLE BIT(0) + +/* SoC1 SCU Register */ +#define SCU_IO_HWSTRAP_UFS BIT(23) +#define SCU_IO_HWSTRAP_EMMC BIT(11) +#define SCU_IO_HWSTRAP_SECBOOT BIT(5) +#define SCU_IO_HWSTRAP_LTPI0_EN BIT(3) +#define SCU_IO_HWSTRAP_LTPI1_EN BIT(1) + +/* CLK information */ +#define CLKIN_25M 25000000UL + +#define SCU_CPU_CLKGATE1_RVAS1 BIT(28) +#define SCU_CPU_CLKGATE1_RVAS0 BIT(25) +#define SCU_CPU_CLKGATE1_E2M1 BIT(19) +#define SCU_CPU_CLKGATE1_DP BIT(18) +#define SCU_CPU_CLKGATE1_DAC BIT(17) +#define SCU_CPU_CLKGATE1_E2M0 BIT(12) +#define SCU_CPU_CLKGATE1_VGA1 BIT(10) +#define SCU_CPU_CLKGATE1_VGA0 BIT(5) + +/* + * Clock divider/multiplier configuration struct. + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + * + */ +union ast2700_pll_reg { + u32 w; + struct { + uint16_t m : 13; /* bit[12:0] */ + uint8_t n : 6; /* bit[18:13] */ + uint8_t p : 4; /* bit[22:19] */ + uint8_t off : 1; /* bit[23] */ + uint8_t bypass : 1; /* bit[24] */ + uint8_t reset : 1; /* bit[25] */ + uint8_t reserved : 6; /* bit[31:26] */ + } b; +}; + +struct ast2700_pll_cfg { + union ast2700_pll_reg reg; + unsigned int ext_reg; +}; + +struct ast2700_pll_desc { + u32 in; + u32 out; + struct ast2700_pll_cfg cfg; +}; + +struct aspeed_clks { + ulong id; + const char *name; +}; + +#ifndef __ASSEMBLY__ +struct ast2700_scu0 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 rsv_0x30[8]; /* 0x030 ~ 0x4C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 rsv_0x80[8]; /* 0x080 ~ 0x9C */ + u32 probe_sig_select; /* 0x0A0 */ + u32 probe_sig_enable1; /* 0x0A4 */ + u32 probe_sig_enable2; /* 0x0A8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC[5]; /* 0x0CC ~ 0x0DC */ + u32 free_counter_read_low; /* 0x0E0 */ + u32 free_counter_read_high; /* 0x0E4 */ + u32 rsv_0xE8[2]; /* 0x0E8 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF8[10]; /* 0x0F8 ~ 0x11C */ + u32 ssp_ctrl_1; /* 0x120 */ + u32 ssp_ctrl_2; /* 0x124 */ + u32 ssp_ctrl_3; /* 0x128 */ + u32 ssp_ctrl_4; /* 0x12C */ + u32 ssp_ctrl_5; /* 0x130 */ + u32 ssp_ctrl_6; /* 0x134 */ + u32 ssp_ctrl_7; /* 0x138 */ + u32 rsv_0x13c[1]; /* 0x13C */ + u32 ssp_remap0_base; /* 0x140 */ + u32 ssp_remap0_size; /* 0x144 */ + u32 ssp_remap1_base; /* 0x148 */ + u32 ssp_remap1_size; /* 0x14c */ + u32 ssp_remap2_base; /* 0x150 */ + u32 ssp_remap2_size; /* 0x154 */ + u32 rsv_0x158[2]; /* 0x158 ~ 0x15C */ + u32 tsp_ctrl_1; /* 0x160 */ + u32 rsv_0x164[1]; /* 0x164 */ + u32 tsp_ctrl_3; /* 0x168 */ + u32 tsp_ctrl_4; /* 0x16C */ + u32 tsp_ctrl_5; /* 0x170 */ + u32 tsp_ctrl_6; /* 0x174 */ + u32 tsp_ctrl_7; /* 0x178 */ + u32 rsv_0x17c[6]; /* 0x17C ~ 0x190 */ + u32 tsp_remap_size; /* 0x194 */ + u32 rsv_0x198[26]; /* 0x198 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst1_lock; /* 0x210 */ + u32 modrst1_prot1; /* 0x214 */ + u32 modrst1_prot2; /* 0x218 */ + u32 modrst1_prot3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl; /* 0x240 */ + u32 clkgate_clr; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock; /* 0x250 */ + u32 clkgate_secure1; /* 0x254 */ + u32 clkgate_secure2; /* 0x258 */ + u32 clkgate_secure3; /* 0x25c */ + u32 rsv_0x260[8]; /* 0x260 */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 clk_sel3; /* 0x288 */ + u32 rsv_0x28c; /* 0x28c */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 clk_sel3_lock; /* 0x298 */ + u32 rsv_0x29c; /* 0x29c */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 clk_sel1_secure3; /* 0x2a8 */ + u32 rsv_0x2ac; /* 0x2ac */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 clk_sel2_secure3; /* 0x2b8 */ + u32 rsv_0x2bc; /* 0x2bc */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 clk_sel3_secure3; /* 0x2c8 */ + u32 rsv_0x2cc[9]; /* 0x2cc */ + u32 extrst_sel; /* 0x2f0 */ + u32 rsv_0x2f4[3]; /* 0x2f4 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 dpll; /* 0x308 */ + u32 dpll_ext; /* 0x30C */ + u32 mpll; /* 0x310 */ + u32 mpll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 d1clk_para; /* 0x320 */ + u32 rsv_0x324[3]; /* 0x324 ~ 0x32C */ + u32 d2clk_para; /* 0x330 */ + u32 rsv_0x334[3]; /* 0x334 ~ 0x33C */ + u32 crt1clk_para; /* 0x340 */ + u32 rsv_0x344[3]; /* 0x344 ~ 0x34C */ + u32 crt2clk_para; /* 0x350 */ + u32 rsv_0x354[3]; /* 0x354 ~ 0x35C */ + u32 mphyclk_para; /* 0x360 */ + u32 rsv_0x364[7]; /* 0x364 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x368 */ + u32 clkduty_meas_res; /* 0x38c */ + u32 rsv_0x390[4]; /* 0x390 ~ 0x39C */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 prog_delay_ring_ctrl0; /* 0x3a8 */ + u32 prog_delay_ring_ctrl1; /* 0x3ac */ + u32 freq_counter_readback; /* 0x3b0 */ + u32 rsv_0x3b4[19]; /* 0x3b4 */ + u32 pinmux1; /* 0x400 */ + u32 pinmux2; /* 0x404 */ + u32 pinmux3; /* 0x408 */ + u32 rsv_0x40c; /* 0x40C */ + u32 pinmux4; /* 0x410 */ + u32 vga_func_ctrl; /* 0x414 */ + u32 rsv_0x418[2]; /* 0x418 */ + u32 pinmux_lock0; /* 0x420 */ + u32 pinmux_lock1; /* 0x424 */ + u32 pinmux_lock2; /* 0x428 */ + u32 rsv_0x42c; + u32 pinmux_lock3; /* 0x430 */ + u32 pinmux_lock4; /* 0x434 */ + u32 rsv_0x438[18]; + u32 gpio18d0_ioctrl; /* 0x480 */ + u32 gpio18d1_ioctrl; /* 0x484 */ + u32 gpio18d2_ioctrl; /* 0x488 */ + u32 gpio18d3_ioctrl; /* 0x48c */ + u32 gpio18d4_ioctrl; /* 0x490 */ + u32 gpio18d5_ioctrl; /* 0x494 */ + u32 gpio18d6_ioctrl; /* 0x498 */ + u32 gpio18d7_ioctrl; /* 0x49c */ + u32 gpio18e0_ioctrl; /* 0x4a0 */ + u32 gpio18e1_ioctrl; /* 0x4a4 */ + u32 gpio18e2_ioctrl; /* 0x4a8 */ + u32 gpio18e3_ioctrl; /* 0x4ac */ + u32 jtag_ioctrl; /* 0x4b0 */ + u32 uart_ioctrl; /* 0x4b4 */ + u32 misc_ioctrl; /* 0x4b8 */ + u32 rsv_0x4bc[17]; /* 0x4bc ~ 0x4fc */ + u32 pinmux_seucre0_0; /* 0x500 */ + u32 pinmux_seucre0_1; /* 0x504 */ + u32 pinmux_seucre0_2; /* 0x508 */ + u32 rsv_0x50c; + u32 pinmux_seucre0_3; /* 0x510 */ + u32 pinmux_seucre0_4; /* 0x514 */ + u32 rsv_0x518[58]; + u32 pinmux_seucre1_0; /* 0x600 */ + u32 pinmux_seucre1_1; /* 0x604 */ + u32 pinmux_seucre1_2; /* 0x608 */ + u32 rsv_0x60c; + u32 pinmux_seucre1_3; /* 0x610 */ + u32 pinmux_seucre1_4; /* 0x614 */ + u32 rsv_0x618[58]; + u32 pinmux_seucre2_0; /* 0x700 */ + u32 pinmux_seucre2_1; /* 0x704 */ + u32 pinmux_seucre2_2; /* 0x708 */ + u32 rsv_0x70c; + u32 pinmux_seucre2_3; /* 0x710 */ + u32 pinmux_seucre2s_4; /* 0x714 */ + u32 rsv_0x718[26]; + u32 cpu_scratch[96]; /* 0x780 ~ 0x8FC */ + u32 vga0_scratch1[4]; /* 0x900 ~ 0x90C */ + u32 vga1_scratch1[4]; /* 0x910 ~ 0x91C */ + u32 vga0_scratch2[8]; /* 0x920 ~ 0x93C */ + u32 vga1_scratch2[8]; /* 0x940 ~ 0x95C */ + u32 pci_cfg1[3]; /* 0x960 ~ 0x968 */ + u32 rsv_0x96c; /* 0x96C */ + u32 pcie_cfg1; /* 0x970 */ + u32 mmio_decode1; /* 0x974 */ + u32 reloc_ctrl_decode1[2]; /* 0x978 ~ 0x97C */ + u32 rsv_0x980[4]; /* 0x980 ~ 0x98C */ + u32 mbox_decode1; /* 0x990 */ + u32 shared_sram_decode1[2];/* 0x994 ~ 0x998 */ + u32 rsv_0x99c; /* 0x99C */ + u32 pci_cfg2[3]; /* 0x9A0 ~ 0x9A8 */ + u32 rsv_0x9ac; /* 0x9AC */ + u32 pcie_cfg2; /* 0x9B0 */ + u32 mmio_decode2; /* 0x9B4 */ + u32 reloc_ctrl_decode2[2]; /* 0x9B8 ~ 0x9BC */ + u32 rsv_0x9c0[4]; /* 0x9C0 ~ 0x9CC */ + u32 mbox_decode2; /* 0x9D0 */ + u32 shared_sram_decode2[2];/* 0x9D4 ~ 0x9D8 */ + u32 rsv_0x9dc[9]; /* 0x9DC ~ 0x9FC */ + u32 pci0_misc[32]; /* 0xA00 ~ 0xA7C */ + u32 pci1_misc[32]; /* 0xA80 ~ 0xAFC */ +}; + +struct ast2700_scu1 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 hwstrap2; /* 0x030 */ + u32 hwstrap2_clr; /* 0x034 */ + u32 rsv_0x38[2]; /* 0x038 ~ 0x03C */ + u32 hwstrap2_lock; /* 0x040 */ + u32 hwstrap2_sec1; /* 0x044 */ + u32 hwstrap2_sec2; /* 0x048 */ + u32 hwstrap2_sec3; /* 0x04C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 sysrest_log4; /* 0x080 */ + u32 sysrest_log4_sec1; /* 0x084 */ + u32 sysrest_log4_sec2; /* 0x088 */ + u32 sysrest_log4_sec3; /* 0x08C */ + u32 rsv_0x90[7]; /* 0x090 ~ 0xA8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC; /* 0x0CC */ + u32 dac_ctrl; /* 0x0D0 */ + u32 dac_crc_ctrl; /* 0x0D4 */ + u32 rsv_0xD8[2]; /* 0x0D8 ~ 0x0DC */ + u32 video_input_ctrl; /* 0x0E0 */ + u32 rsv_0xE4[3]; /* 0x0E4 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF0[2]; /* 0x0F8 ~ 0x0FC */ + u32 rsv_0x100[32]; /* 0x100 ~ 0x17C */ + u32 scratch[32]; /* 0x180 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst_lock1; /* 0x210 */ + u32 modrst1_sec1; /* 0x214 */ + u32 modrst1_sec2; /* 0x218 */ + u32 modrst1_sec3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl1; /* 0x240 */ + u32 clkgate_clr1; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock1; /* 0x250 */ + u32 clkgate_secure11; /* 0x254 */ + u32 clkgate_secure12; /* 0x258 */ + u32 clkgate_secure13; /* 0x25c */ + u32 clkgate_ctrl2; /* 0x260 */ + u32 clkgate_clr2; /* 0x264 */ + u32 rsv_0x268[2]; /* 0x268 */ + u32 clkgate_lock2; /* 0x270 */ + u32 clkgate_secure21; /* 0x274 */ + u32 clkgate_secure22; /* 0x278 */ + u32 clkgate_secure23; /* 0x27c */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 rsv_0x288[2]; /* 0x288 */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 rsv_0x298[2]; /* 0x298 */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 rsv_0x2a8[2]; /* 0x2a8 */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 rsv_0x2b8[2]; /* 0x2b8 */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 rsv_0x2c8[10]; /* 0x2c8 */ + u32 extrst_sel1; /* 0x2f0 */ + u32 extrst_sel2; /* 0x2f4 */ + u32 rsv_0x2f8[2]; /* 0x2f8 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 rsv_0x308[2]; /* 0x308 ~ 0x30C */ + u32 apll; /* 0x310 */ + u32 apll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 dpll; /* 0x320 */ + u32 dpll_ext; /* 0x324 */ + u32 rsv_0x328[2]; /* 0x328 ~ 0x32C */ + u32 uxclk_ctrl; /* 0x330 */ + u32 huxclk_ctrl; /* 0x334 */ + u32 rsv_0x338[18]; /* 0x338 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x388 */ + u32 rsv_0x38c; /* 0x38c */ + u32 mac_delay; /* 0x390 */ + u32 mac_100m_delay; /* 0x394 */ + u32 mac_10m_delay; /* 0x398 */ + u32 rsv_0x39c; /* 0x39c */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 rsv_0x3a8[2]; /* 0x3a8 ~ 0x3aC */ + u32 usb_ctrl; /* 0x3b0 */ + u32 usb_lock; /* 0x3b4 */ + u32 usb_secure1; /* 0x3b8 */ + u32 usb_secure2; /* 0x3bc */ + u32 usb_secure3; /* 0x3c0 */ + u32 rsv_0x3c4[15]; /* 0x3c4 ~ 0x3fc */ + u32 pinumx1; /* 0x400 */ + u32 pinumx2; /* 0x404 */ + u32 pinumx3; /* 0x408 */ + u32 pinumx4; /* 0x40c */ + u32 pinumx5; /* 0x410 */ + u32 pinumx6; /* 0x414 */ + u32 pinumx7; /* 0x418 */ + u32 pinumx8; /* 0x41c */ + u32 pinumx9; /* 0x420 */ + u32 pinumx10; /* 0x424 */ + u32 pinumx11; /* 0x428 */ + u32 pinumx12; /* 0x42c */ + u32 pinumx13; /* 0x430 */ + u32 pinumx14; /* 0x434 */ + u32 pinumx15; /* 0x438 */ + u32 pinumx16; /* 0x43c */ + u32 pinumx17; /* 0x440 */ + u32 pinumx18; /* 0x444 */ + u32 pinumx19; /* 0x448 */ + u32 pinumx20; /* 0x44c */ + u32 pinumx21; /* 0x450 */ + u32 pinumx22; /* 0x454 */ + u32 pinumx23; /* 0x458 */ + u32 pinumx24; /* 0x45c */ + u32 pinumx25; /* 0x460 */ + u32 pinumx26; /* 0x464 */ + u32 pinumx27; /* 0x468 */ + u32 rsv_0x46c[4]; /* 0x46c ~ 0x478 */ + u32 pinumx31; /* 0x47c */ + u32 pull_down_dis[8]; /* 0x480 ~ 0x49c */ + u32 pin_conf; /* 0x4a0 */ + u32 rsv_0x4a4[7]; /* 0x4a4 ~ 0x4bc */ + u32 io_driving0; /* 0x4c0 */ + u32 io_driving1; /* 0x4c4 */ + u32 io_driving2; /* 0x4c8 */ + u32 io_driving3; /* 0x4cc */ + u32 io_driving4; /* 0x4d0 */ + u32 io_driving5; /* 0x4d4 */ + u32 io_driving6; /* 0x4d8 */ + u32 io_driving7; /* 0x4dc */ + u32 io_driving8; /* 0x4e0 */ +}; + +#endif +#endif diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index c88b1e59366..f4b038ebd9e 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -36,9 +36,20 @@ config ASPEED_AST2600 It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. +config ASPEED_AST2700 + bool "Support Aspeed AST2700 SoC" + select ARM64 + select SYS_ARCH_TIMER + help + Support for the Aspeed AST2700, an arm64 (Cortex-A35) Baseboard + Management Controller (BMC) SoC. This is the 8th-generation BMC + SoC family from Aspeed and features a dual-die architecture + (CPU die + I/O die) connected via an internal coherent bus. + endchoice source "arch/arm/mach-aspeed/ast2500/Kconfig" source "arch/arm/mach-aspeed/ast2600/Kconfig" +source "arch/arm/mach-aspeed/ast2700/Kconfig" endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile index 42599c125b8..d0b4eb74c6c 100644 --- a/arch/arm/mach-aspeed/Makefile +++ b/arch/arm/mach-aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o obj-$(CONFIG_ASPEED_AST2500) += ast2500/ obj-$(CONFIG_ASPEED_AST2600) += ast2600/ +obj-$(CONFIG_ASPEED_AST2700) += ast2700/ diff --git a/arch/arm/mach-aspeed/ast2700/Kconfig b/arch/arm/mach-aspeed/ast2700/Kconfig new file mode 100644 index 00000000000..3dd68db76db --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Kconfig @@ -0,0 +1,36 @@ +if ASPEED_AST2700 + +config SYS_CPU + default "armv8" + +config SPI_KERNEL_FIT_ADDR + hex "SPI address of kernel FIT image" + default 0x100420000 + help + Address in the SPI flash where the kernel FIT image is stored. + Used by the bootspi command to load and boot the kernel image + from the SPI flash on AST2700 platforms. + +choice + prompt "AST2700 board select" + depends on ASPEED_AST2700 + default TARGET_EVB_AST2700 + help + Select the AST2700 board model. Each board option configures + the board-specific Kconfig, defaults and devicetree. + +config TARGET_EVB_AST2700 + bool "EVB-AST2700" + depends on ASPEED_AST2700 + select ARCH_MISC_INIT + help + EVB-AST2700 is Aspeed evaluation board for AST2700A0 chip. + It has 512M of RAM, 32M of SPI flash, two Ethernet ports, + 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot, + 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. + +endchoice + +source "board/aspeed/evb_ast2700/Kconfig" + +endif diff --git a/arch/arm/mach-aspeed/ast2700/Makefile b/arch/arm/mach-aspeed/ast2700/Makefile new file mode 100644 index 00000000000..38bd52f3d5d --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o board_common.o arm64-mmu.o platform.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o diff --git a/arch/arm/mach-aspeed/ast2700/arm64-mmu.c b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c new file mode 100644 index 00000000000..a068e6ede97 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include + +static struct mm_region aspeed2700_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x2C0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, + { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = aspeed2700_mem_map; + +u64 get_page_table_size(void) +{ + return 0x80000; +} diff --git a/arch/arm/mach-aspeed/ast2700/board_common.c b/arch/arm/mach-aspeed/ast2700/board_common.c new file mode 100644 index 00000000000..6d2160bbca4 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/board_common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AHBC_GROUP(x) (0x40 * (x)) +#define AHBC_HREADY_WAIT_CNT_REG 0x34 +#define AHBC_HREADY_WAIT_CNT_MAX 0x3f + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + struct udevice *dev; + struct ram_info ram; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("cannot get DRAM driver\n"); + debug("cannot get DRAM driver\n"); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + debug("cannot get DRAM information\n"); + return ret; + } + + gd->ram_size = ram.size; + + return 0; +} + +static void ahbc_init(void) +{ + u32 reg_val; + int i; + + reg_val = readl(ASPEED_CPU_REVISION_ID); + if (FIELD_GET(SCU_CPU_REVISION_ID_HW, reg_val)) + return; + + /* CPU-die AHBC timeout counter */ + for (i = 0; i < 4; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_CPU_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); + + /* IO-die AHBC timeout counter */ + for (i = 0; i < 8; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_IO_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); +} + +int board_init(void) +{ + struct udevice *dev; + int i = 0; + int ret; + + ahbc_init(); + + /* + * Loop over all MISC uclass drivers to call the comphy code + * and init all CP110 devices enabled in the DT + */ + while (1) { + /* Call the comphy code via the MISC uclass driver */ + ret = uclass_get_device(UCLASS_MISC, i++, &dev); + + /* We're done, once no further CP110 device is found */ + if (ret) + break; + } + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/cpu-info.c b/arch/arm/mach-aspeed/ast2700/cpu-info.c new file mode 100644 index 00000000000..7f29c4d8c33 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/cpu-info.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + * Ryan Chen + */ + +#include +#include +#include +#include + +/* SoC mapping Table */ +#define SOC_ID(str, rev) { .name = str, .rev_id = rev, } + +struct soc_id { + const char *name; + u64 rev_id; +}; + +static struct soc_id soc_map_table[] = { + SOC_ID("AST2750-A0", 0x0600000306000003), + SOC_ID("AST2700-A0", 0x0600010306000103), + SOC_ID("AST2720-A0", 0x0600020306000203), + SOC_ID("AST2750-A1", 0x0601000306010003), + SOC_ID("AST2700-A1", 0x0601010306010103), + SOC_ID("AST2720-A1", 0x0601020306010203), + SOC_ID("AST2750-A2", 0x0602000306020003), + SOC_ID("AST2700-A2", 0x0602010306020103), + SOC_ID("AST2720-A2", 0x0602020306020203), +}; + +void ast2700_print_soc_id(void) +{ + int i; + u64 rev_id; + + rev_id = readl(ASPEED_CPU_REVISION_ID); + rev_id = ((u64)readl(ASPEED_IO_REVISION_ID) << 32) | rev_id; + + for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { + if (rev_id == soc_map_table[i].rev_id) + break; + } + if (i == ARRAY_SIZE(soc_map_table)) + printf("Unknown-SOC: %llx\n", rev_id); + else + printf("SOC: %4s\n", soc_map_table[i].name); +} + +#define SYS_DRAM_ECCRST BIT(3) +#define SYS_ABRRST BIT(2) +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +#define WDT_RST_BIT_MASK(s) (GENMASK(3, 0) << (s)) +#define BIT_WDT_FULL(s) (BIT(0) << (s)) +#define BIT_WDT_ARM(s) (BIT(1) << (s)) +#define BIT_WDT_SOC(s) (BIT(2) << (s)) +#define BIT_WDT_SW(s) (BIT(3) << (s)) + +void ast2700_print_wdtrst_info(void) +{ + u32 wdt_rst = readl(ASPEED_IO_RESET_LOG4); + int i; + + for (i = 0; i < 8; i++) { + if (wdt_rst & WDT_RST_BIT_MASK(i * 4)) { + printf("RST: WDT%d ", i); + if (wdt_rst & BIT_WDT_SOC(i * 4)) { + printf("SOC "); + writel(BIT_WDT_SOC(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_FULL(i * 4)) { + printf("FULL "); + writel(BIT_WDT_FULL(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_ARM(i * 4)) { + printf("ARM "); + writel(BIT_WDT_ARM(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_SW(i * 4)) { + printf("SW "); + writel(BIT_WDT_SW(i * 4), ASPEED_IO_RESET_LOG4); + } + printf("\n"); + } + } +} + +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +void ast2700_print_sysrst_info(void) +{ + u32 sys_rst = readl(ASPEED_CPU_RESET_LOG1); + + if (sys_rst & SYS_SRST) { + printf("RST: Power On\n"); + writel(SYS_SRST, ASPEED_CPU_RESET_LOG1); + } else if (sys_rst & SYS_EXTRST) { + printf("RST: EXTRST\n"); + writel(SYS_EXTRST, ASPEED_CPU_RESET_LOG1); + } else { + ast2700_print_wdtrst_info(); + } +} + +int print_cpuinfo(void) +{ + ast2700_print_soc_id(); + ast2700_print_sysrst_info(); + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/lowlevel_init.S b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S new file mode 100644 index 00000000000..9b78fed0b26 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) ASPEED Technology Inc. + */ +#include +#include + +/* + * SMP mailbox + * +-----------------------+ 0x40 + * | | + * | mailbox insn. for | + * | cpuN GO sign polling | + * | | + * +-----------------------+ 0x20 + * | cpu3 entrypoint | + * +-----------------------+ 0x18 + * | cpu2 entrypoint | + * +-----------------------+ 0x10 + * | cpu1 entrypoint | + * +-----------------------+ 0x8 + * | reserved | + * +-----------------------+ 0x4 + * | mailbox ready | + * +-----------------------+ SCU_CPU + 0x780 + */ + +#define SCU_CPU_BASE 0x12c02000 +#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) +#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) +#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) +#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) +#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0) + +ENTRY(lowlevel_init) + /* backup LR */ + mov x29, lr + +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* reset SMP mailbox ASAP */ + ldr x0, =SCU_CPU_SMP_READY + str wzr, [x0] + + /* + * get cpu core id + * + * ast2700 has 1-cluster, 4-cores CPU topology. + * Affinity level 0 in MPIDR is sufficient. + */ + mrs x4, mpidr_el1 + ands x4, x4, #0xff + + /* cpu0 is the primary core to setup SMP mailbox */ + beq do_primary_core_setup + + /* hold cpuN until mailbox is ready */ + ldr x0, =SCU_CPU_SMP_READY + movz w1, #0xcafe + movk w1, #0xbabe, lsl #16 + +poll_mailbox_ready: + wfe + ldr w2, [x0] + cmp w1, w2 + bne poll_mailbox_ready + + /* + * parameters for relocated SMP go polling insn. + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ + add x5, x0, x4, lsl #3 + + /* jump to the polling loop in SMP mailbox, no return */ + ldr x0, =SCU_CPU_SMP_POLLINSN + br x0 + +do_primary_core_setup: + /* relocate mailbox insn. for cpuN to poll for SMP go signal */ + adr x0, smp_mbox_insn + adr x1, smp_mbox_insn_end + ldr x2, =SCU_CPU_SMP_POLLINSN + +relocate_smp_mbox_insn: + ldr w3, [x0], #0x4 + str w3, [x2], #0x4 + cmp x0, x1 + bne relocate_smp_mbox_insn + + /* reset cpuN entrypoints */ + ldr x0, =SCU_CPU_SMP_EP1 + str xzr, [x0], #8 + str xzr, [x0], #8 + str xzr, [x0] + + /* notify cpuN that SMP mailbox is ready */ + movz w0, #0xcafe + movk w0, #0xbabe, lsl #16 + ldr x1, =SCU_CPU_SMP_READY + str w0, [x1] + + sev +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + /* back to arch calling code */ + mov lr, x29 + ret +ENDPROC(lowlevel_init) + +/* + * insn. inside mailbox to poll SMP go signal. + * + * Note that this code will be relocated, any absolute + * addressing should NOT be used. + */ +smp_mbox_insn: + /* + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ +poll_smp_mbox_go: + wfe + ldr x0, [x5] + cmp x0, xzr + beq poll_smp_mbox_go + + /* jump to secondary core entrypoint */ + br x0 + +smp_mbox_insn_end: + /* should never reach */ + b . diff --git a/arch/arm/mach-aspeed/ast2700/platform.c b/arch/arm/mach-aspeed/ast2700/platform.c new file mode 100644 index 00000000000..9cca85766f6 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/platform.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum env_location env_loc = ENVL_UNKNOWN; + u32 strap = readl(ASPEED_IO_HW_STRAP1); + + if (prio) + return env_loc; + + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) { + env_loc = ENVL_NOWHERE; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && + !(strap & SCU_IO_HWSTRAP_EMMC)) { + env_loc = ENVL_SPI_FLASH; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) && + (strap & SCU_IO_HWSTRAP_EMMC) && + !(strap & SCU_IO_HWSTRAP_UFS)) { + env_loc = ENVL_MMC; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) { + /* + * This tree does not carry an ENV_IS_IN_UFS backend yet. + * Fall back to SPI flash when that backend exists. + */ + env_loc = ENVL_SPI_FLASH; + } else { + env_loc = ENVL_NOWHERE; + } + + return env_loc; +} + +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_ARCH_MISC_INIT)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_EMMC)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_UFS)) + env_set("boot_device", "ufs"); + else + env_set("boot_device", "mmc"); + } else { + env_set("boot_device", "spi"); + } + + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_SECBOOT)) + env_set("verify", "yes"); + else + env_set("verify", "no"); + } + + return 0; +} diff --git a/board/aspeed/evb_ast2700/Kconfig b/board/aspeed/evb_ast2700/Kconfig new file mode 100644 index 00000000000..ede9eb7fb85 --- /dev/null +++ b/board/aspeed/evb_ast2700/Kconfig @@ -0,0 +1,13 @@ +if TARGET_EVB_AST2700 + +config SYS_BOARD + default "evb_ast2700" + +config SYS_VENDOR + default "aspeed" + +config SYS_CONFIG_NAME + string "board configuration name" + default "evb_ast2700" + +endif diff --git a/board/aspeed/evb_ast2700/Makefile b/board/aspeed/evb_ast2700/Makefile new file mode 100644 index 00000000000..0c29700f5a9 --- /dev/null +++ b/board/aspeed/evb_ast2700/Makefile @@ -0,0 +1 @@ +obj-y += evb_ast2700.o diff --git a/board/aspeed/evb_ast2700/evb_ast2700.c b/board/aspeed/evb_ast2700/evb_ast2700.c new file mode 100644 index 00000000000..b34aa6e1682 --- /dev/null +++ b/board/aspeed/evb_ast2700/evb_ast2700.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + diff --git a/configs/evb-ast2700_defconfig b/configs/evb-ast2700_defconfig new file mode 100644 index 00000000000..d0733e14c67 --- /dev/null +++ b/configs/evb-ast2700_defconfig @@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_POSITION_INDEPENDENT=y +# CONFIG_INIT_SP_RELATIVE is not set +CONFIG_ARM_SMCCC=y +CONFIG_ARCH_ASPEED=y +CONFIG_TEXT_BASE=0x400000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_ASPEED_AST2700=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x403000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="ast2700-evb" +CONFIG_DM_RESET=y +CONFIG_SYS_LOAD_ADDR=0x403000000 +CONFIG_DEBUG_UART_BASE=0x14c33b00 +CONFIG_DEBUG_UART_CLOCK=1846154 +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_CRYPTO=y +CONFIG_ENV_ADDR=0x400000 +CONFIG_SYS_PCI_64BIT=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_SYS_MEMTEST_START=0x403000000 +CONFIG_SYS_MEMTEST_END=0x403001000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +# CONFIG_BOOTMETH_EFILOADER is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS12,115200n8 root=/dev/ram rw earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="echo Boot from ${boot_device}; if test ${boot_device} = mmc; then run bootmmc; fi; if test ${boot_device} = spi; then run bootspi; fi; if test ${boot_device} = ufs; then run bootufs; fi;" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTFLOW is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_UFS=y +CONFIG_CMD_NCSI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_CMD_CYCLIC is not set +CONFIG_DOS_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_MMC_USE_DT=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="ast2700-evb" +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_HASH=y +CONFIG_DFU_RAM=y +CONFIG_GPIO_HOG=y +CONFIG_ASPEED_G7_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AST2600=y +# CONFIG_INPUT is not set +CONFIG_DM_MAILBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_DM_MDIO=y +CONFIG_FTGMAC100=y +CONFIG_ASPEED_MDIO=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_AIROHA=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_NCSI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_DIRMAP=y +CONFIG_SPI_ASPEED_SMC=y +CONFIG_SYSRESET=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASPEED" +CONFIG_USB_GADGET_VENDOR_NUM=0x2245 +CONFIG_USB_GADGET_PRODUCT_NUM=0x2700 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_UFS=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +# CONFIG_WDT_ASPEED is not set +CONFIG_ECDSA=y +CONFIG_ECDSA_VERIFY=y +CONFIG_TPM=y +CONFIG_LZ4=y +CONFIG_LZMA=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/include/configs/evb_ast2700.h b/include/configs/evb_ast2700.h new file mode 100644 index 00000000000..6b73eddc1af --- /dev/null +++ b/include/configs/evb_ast2700.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Extra ENV for Boot Command */ +#define STR_HELPER(n) #n +#define STR(n) STR_HELPER(n) + +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootspi=fdt addr ${fdtspiaddr} && " \ + "fdt header get fitsize totalsize && " \ + "cp.b ${fdtspiaddr} ${loadaddr} ${fitsize} && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootside=a\0" \ + "rootfs=rofs-a\0" \ + "setmmcargs=setenv bootargs ${bootargs} " \ + "rootwait root=PARTLABEL=${rootfs}\0" \ + "boota=setenv bootpart 2; setenv rootfs rofs-a; " \ + "run setmmcargs; " \ + "ext4load mmc 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootb=setenv bootpart 3; setenv rootfs rofs-b; " \ + "run setmmcargs; " \ + "ext4load mmc 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootmmc=if test \"${bootside}\" = \"b\"; " \ + "then run bootb; run boota; " \ + "else run boota; run bootb; fi\0" \ + "setufsargs=setenv bootargs ${bootargs} " \ + "rootwait root=PARTLABEL=${rootfs}\0" \ + "ufsboota=setenv bootpart 2; setenv rootfs rofs-a; " \ + "run setufsargs; " \ + "ext4load scsi 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "ufsbootb=setenv bootpart 3; setenv rootfs rofs-b; " \ + "run setufsargs; " \ + "ext4load scsi 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootufs=if test \"${bootside}\" = \"b\"; " \ + "then run ufsbootb; run ufsboota; " \ + "else run ufsboota; run ufsbootb; fi\0" \ + "verify=no\0" \ + "" +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 8d3963a0971caa4b0b16c1e531cee5eeea20c865 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 1 Jul 2026 06:21:25 +0000 Subject: ls1028ardb: Move environment variables to .env file Move the bulk of the board environment from CFG_EXTRA_ENV_SETTINGS in ls1028ardb.h to board/nxp/ls1028a/ls1028ardb.env. Because the board directory is shared with ls1028aqds, the file is selected through CONFIG_ENV_SOURCE_FILE rather than the SYS_BOARD default. The distro_bootcmd machinery cannot be expressed in a .env file. The BOOTENV macro expands to environment text with embedded NUL separators, and the board overrides three distro variables (boot_scripts, boot_a_script and scan_dev_for_boot_part) that must follow BOOTENV to take effect. BOOTENV and those three overrides therefore remain in CFG_EXTRA_ENV_SETTINGS, which is concatenated after the .env text, while every other variable moves to the .env file. The resulting default environment is functionally unchanged for both the ls1028ardb_tfa and ls1028ardb_tfa_SECURE_BOOT defconfigs. This was verified with an order aware comparison of the default environment before and after the change. The only difference is that three accidental double spaces in xspi_bootcmd, sd_bootcmd and emmc_bootcmd collapse to single spaces, because the preprocessor normalises whitespace in the now unquoted text, which does not affect command parsing. Signed-off-by: Aristo Chen Signed-off-by: Peng Fan --- board/nxp/ls1028a/ls1028ardb.env | 49 ++++++++++++++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + include/configs/ls1028ardb.h | 99 ++++++---------------------- 4 files changed, 71 insertions(+), 79 deletions(-) create mode 100644 board/nxp/ls1028a/ls1028ardb.env (limited to 'include/configs') diff --git a/board/nxp/ls1028a/ls1028ardb.env b/board/nxp/ls1028a/ls1028ardb.env new file mode 100644 index 00000000000..dc1cb01e50a --- /dev/null +++ b/board/nxp/ls1028a/ls1028ardb.env @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +board=ls1028ardb +hwconfig=fsl_ddr:bank_intlv=auto +fdtfile=fsl-ls1028a-rdb.dtb +image=Image +extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0 +othbootargs=video=1920x1080-32@60 cma=640M +ramdisk_addr=0x800000 +ramdisk_size=0x2000000 +bootm_size=0x10000000 +kernel_addr=0x01000000 +scriptaddr=0x80000000 +scripthdraddr=0x80080000 +fdtheader_addr_r=0x80100000 +kernelheader_addr_r=0x80200000 +load_addr=0xa0000000 +kernel_addr_r=0x81000000 +fdt_addr_r=0x90000000 +ramdisk_addr_r=0xa0000000 +kernel_start=0x1000000 +kernelheader_start=0x600000 +kernel_load=0xa0000000 +kernel_size=0x2800000 +kernelheader_size=0x40000 +kernel_addr_sd=0x8000 +kernel_size_sd=0x14000 +kernelhdr_addr_sd=0x3000 +kernelhdr_size_sd=0x20 +console=ttyS0,115200 +console_dbg=earlycon=uart8250,mmio,0x21c0500 +boot_script_hdr=hdr_ls1028ardb_bs.out +xspi_bootcmd=echo Trying load from FlexSPI flash ...;sf probe 0:0 && sf read $load_addr + $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r + $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm + $load_addr#$board +xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;sf probe 0:0 && sf read + $load_addr 0x940000 0x30000 && hdp load $load_addr 0x2000 +sd_bootcmd=echo Trying load from SD ...;mmc dev 0;mmcinfo; mmc read $load_addr $kernel_addr_sd + $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd + $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$board +sd_hdploadcmd=echo Trying load HDP firmware from SD..;mmc dev 0;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 +emmc_bootcmd=echo Trying load from EMMC ..;mmc dev 1;mmcinfo; mmc read $load_addr + $kernel_addr_sd $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r + $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm + $load_addr#$board +emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;mmc dev 1;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 6917fe7783b..a8c7c89c9d3 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SOURCE_FILE="ls1028ardb" CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index f1c13afbb2e..ca19d6035ee 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SOURCE_FILE="ls1028ardb" CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 613abc50567..1811825baeb 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -50,85 +50,26 @@ /* Initial environment variables */ #ifndef SPL_NO_ENV #undef CFG_EXTRA_ENV_SETTINGS -#define CFG_EXTRA_ENV_SETTINGS \ - "board=ls1028ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "fdtfile=fsl-ls1028a-rdb.dtb\0" \ - "image=Image\0" \ - "extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0\0" \ - "othbootargs=video=1920x1080-32@60 cma=640M\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "bootm_size=0x10000000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x600000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x3000\0" \ - "kernelhdr_size_sd=0x20\0" \ - "console=ttyS0,115200\0" \ - "console_dbg=earlycon=uart8250,mmio,0x21c0500\0" \ - BOOTENV \ - "boot_scripts=ls1028ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "boot_scripts=ls1028ardb_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$board\0" \ - "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ - "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ - "&& hdp load $load_addr 0x2000\0" \ - "sd_bootcmd=echo Trying load from SD ...;" \ - "mmc dev 0;mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ - "mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmc dev 1;mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ - "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" #endif #endif /* __LS1028A_RDB_H */ -- cgit v1.3.1