From a179217e68e5c0c91004b1084e04091a80a6bb7e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 May 2023 14:52:14 +0100 Subject: faraday: remove orphaned header file Commit 11232139e399 ("nds32: Remove the architecture") removed the nds32 architecture, and with it the last user of the Faraday AHB controller header file. Consequently remove that header file as well. This was found because the inclusion guard was misspelled. Signed-off-by: Andre Przywara Reviewed-by: Tom Rini --- include/faraday/ftahbc020s.h | 46 -------------------------------------------- 1 file changed, 46 deletions(-) delete mode 100644 include/faraday/ftahbc020s.h (limited to 'include/faraday') diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h deleted file mode 100644 index e628156c151..00000000000 --- a/include/faraday/ftahbc020s.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation - */ - -/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ -#ifndef __FTAHBC020S_H -#define __FTAHBC202S_H - -/* Registers Offsets */ - -/* - * AHB Slave BSR, offset: n * 4, n=0~31 - */ -#ifndef __ASSEMBLY__ -struct ftahbc02s { - unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ - unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ - unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ - unsigned int cr; /* 0x88 - Ctrl Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register - */ -#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) -#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) -/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ -#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ - -/* - * FTAHBC020S_PCR - Priority Control Register - */ -#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ - -/* - * FTAHBC020S_CR - Interrupt Control Register - */ -#define FTAHBC020S_CR_INTSTS (1 << 24) -#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) -#define FTAHBC020S_CR_INTSMASK (1 << 16) -#define FTAHBC020S_CR_REMAP (1 << 0) - -#endif /* __FTAHBC020S_H */ -- cgit v1.2.3 From f1671205fa44084b334027a267c86e5be2ea7c1a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 May 2023 12:34:47 -0400 Subject: include: Remove unused header files As part of various code clean-ups we have on occasion missed removing unused header files. None of these files are referenced anywhere else at this point. Signed-off-by: Tom Rini --- include/faraday/ftpci100.h | 84 -------------------------- include/faraday/ftsdmc020.h | 90 ---------------------------- include/faraday/ftsdmc021.h | 139 -------------------------------------------- 3 files changed, 313 deletions(-) delete mode 100644 include/faraday/ftpci100.h delete mode 100644 include/faraday/ftsdmc020.h delete mode 100644 include/faraday/ftsdmc021.h (limited to 'include/faraday') diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h deleted file mode 100644 index 8801bd13508..00000000000 --- a/include/faraday/ftpci100.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation - * - * Copyright (C) 2010 Andes Technology Corporation - * Gavin Guo, Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation - */ - -#ifndef __FTPCI100_H -#define __FTPCI100_H - -/* AHB Control Registers */ -#include -struct ftpci100_ahbc { - unsigned int iosize; /* 0x00 - I/O Space Size Signal */ - unsigned int prot; /* 0x04 - AHB Protection */ - unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ - unsigned int conf; /* 0x28 - PCI Configuration */ - unsigned int data; /* 0x2c - PCI Configuration DATA */ -}; - -/* - * FTPCI100_IOSIZE_REG's constant definitions - */ -#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ - -/* - * PCI Configuration Register - */ -#define PCI_INT_MASK 0x4c -#define PCI_MEM_BASE_SIZE1 0x50 -#define PCI_MEM_BASE_SIZE2 0x54 -#define PCI_MEM_BASE_SIZE3 0x58 - -/* - * PCI_INT_MASK's bit definitions - */ -#define PCI_INTA_ENABLE (1 << 22) -#define PCI_INTB_ENABLE (1 << 23) -#define PCI_INTC_ENABLE (1 << 24) -#define PCI_INTD_ENABLE (1 << 25) - -/* - * PCI_MEM_BASE_SIZE1's constant definitions - */ -#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ - -#define FTPCI100_MAX_FUNCTIONS 20 -#define PCI_IRQ_LINES 4 - -#define MAX_BUS_NUM 256 -#define MAX_DEV_NUM 32 -#define MAX_FUN_NUM 8 - -#define PCI_MAX_BAR_PER_FUNC 6 - -/* - * PCI_MEM_SIZE - */ -#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) - -/* This definition is used by pci_ftpci_init() */ -#define FTPCI100_BRIDGE_VENDORID 0x159b -#define FTPCI100_BRIDGE_DEVICEID 0x4321 - -void pci_ftpci_init(void); - -struct pcibar { - unsigned int size; - unsigned int addr; -}; - -struct pci_config { - unsigned int bus; - unsigned int dev; /* device */ - unsigned int func; - unsigned int pin; - unsigned short v_id; /* vendor id */ - unsigned short d_id; /* device id */ - struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; -}; - -#endif diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h deleted file mode 100644 index d74da16ef28..00000000000 --- a/include/faraday/ftsdmc020.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h deleted file mode 100644 index e0e5eb339e1..00000000000 --- a/include/faraday/ftsdmc021.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin - */ - -/* - * FTSDMC021 - SDRAM Controller - */ -#ifndef __FTSDMC021_H -#define __FTSDMC021_H - -#ifndef __ASSEMBLY__ -#include -struct ftsdmc021 { - unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ - unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ - unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ - unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ - unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ - unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ - unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ - unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ - unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ - unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ - unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ - unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ - unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ - unsigned int frr; /* 0x34 - Flush Request Register */ - unsigned int ebisr; /* 0x38 - EBI Support Register */ - unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ - unsigned int crr; /* 0x100 - Controller Revision Reg */ - unsigned int cfr; /* 0x104 - Controller Feature Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Timing Parameter 1 Register - */ -#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ -#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ -#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ -#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ -#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ -#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parameter 2 Register - */ -#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ -/* b(16:19) - Initial Refresh Times */ -#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) -/* b(20:23) - Initial Pre-Charge Times */ -#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * SDRAM Configuration Register 1 - */ -#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ -#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ -#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ -#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ -/* b(16) MA2T: Double Memory Address Cycle Enable */ -#define FTSDMC021_CR1_MA2T(x) (1 << 16) -/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ -#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) - -/* - * Configuration Register 2 - */ -#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ -#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ -#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ -#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ -#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ -#define FTSDMC021_CR2_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC021_BANK_ENABLE (1 << 12) - -/* 12-bit base address of external bank. - * Default value is 0x800. - * The 12-bit equals to the haddr[31:20] of AHB address bus. */ -#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) - -/* - * Read Arbitration Grant Window Register - */ -#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) -#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) -#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) -#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) -#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) -#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) -#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) -#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) - -/* - * Flush Request Register - */ -#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) -#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ - -/* - * External Bus Interface Support Register (EBISR) - */ -#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ -#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ -#define FTSDMC021_EBISR_POPREC (1 << 13) -#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ - -/* - * Controller Revision Register (CRR, Read Only) - */ -#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) -#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) -#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) - -/* - * Controller Feature Register (CFR, Read Only) - */ -#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) -#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) -#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) -#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) -#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) -#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) -#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) -#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) -#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) -#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) -#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) - -#endif /* __FTSDMC021_H */ -- cgit v1.2.3