From de5e5cea022ab44006ff1edf45a39f0943fb9dff Mon Sep 17 00:00:00 2001 From: Chris Zankel Date: Wed, 10 Aug 2016 18:36:43 +0300 Subject: xtensa: add support for the xtensa processor architecture [1/2] The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: Chris Zankel Signed-off-by: Max Filippov Reviewed-by: Simon Glass Reviewed-by: Tom Rini --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/image.h') diff --git a/include/image.h b/include/image.h index 734def31178..64da7226490 100644 --- a/include/image.h +++ b/include/image.h @@ -200,6 +200,7 @@ enum { IH_ARCH_ARM64, /* ARM64 */ IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ + IH_ARCH_XTENSA, /* Xtensa */ IH_ARCH_COUNT, }; -- cgit v1.2.3