From 7a67bc55b91d3763b32c463e5ccbf95de6040d31 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 22 Dec 2023 14:45:58 +0900 Subject: mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28 Some macro definitions used in Infineon(Cypress) S25 and S28 series are redundant and some have inconsistent prefix. This patch removes redundant ones and renames some to have same prefix as others. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- include/linux/mtd/spi-nor.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2861b73edbc..f9a55c8e740 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -136,14 +136,6 @@ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */ -#define SPINOR_OP_RDAR 0x65 /* Read any register */ -#define SPINOR_OP_WRAR 0x71 /* Write any register */ -#define SPINOR_REG_ADDR_STR1V 0x00800000 -#define SPINOR_REG_ADDR_CFR1V 0x00800002 -#define SPINOR_REG_ADDR_CFR3V 0x00800004 -#define SPINOR_REG_ADDR_ARCFN 0x00000006 -#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ -#define CFR3V_PGMBUF BIT(4) /* Program buffer size */ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ @@ -189,6 +181,9 @@ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_OP_S28_SE_4K 0x21 +#define SPINOR_REG_CYPRESS_ARCFN 0x00000006 +#define SPINOR_REG_CYPRESS_STR1V 0x00800000 +#define SPINOR_REG_CYPRESS_CFR1V 0x00800002 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 -- cgit v1.2.3 From a3a5cc7613ebbbd647ddd0555e0c9a23c340318e Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 22 Dec 2023 14:45:59 +0900 Subject: mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28 s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector layout (32 x 4KB sectors overlaid at bottom address) and doing same thing. Consolidate them into single helper named s25_s28_erase_non_uniform(). Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- include/linux/mtd/spi-nor.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f9a55c8e740..ebe38306a1d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -180,7 +180,6 @@ /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ -#define SPINOR_OP_S28_SE_4K 0x21 #define SPINOR_REG_CYPRESS_ARCFN 0x00000006 #define SPINOR_REG_CYPRESS_STR1V 0x00800000 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 -- cgit v1.2.3 From 9901312e09af0bf51e35628cd8547637c103ed6c Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 22 Dec 2023 14:46:01 +0900 Subject: mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28 Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode. Instead, it supports CLPEF(0x82) which has the same functionality as CLSR. spansion_sr_ready() is for multi-die package parts including S28HS02GT, so we need to use CLPEF instead of CLSR. This change does not affect to S25x02GT which uses spansion_sr_ready() as S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30). Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- include/linux/mtd/spi-nor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index ebe38306a1d..8a94e120372 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -180,6 +180,7 @@ /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ +#define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */ #define SPINOR_REG_CYPRESS_ARCFN 0x00000006 #define SPINOR_REG_CYPRESS_STR1V 0x00800000 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 -- cgit v1.2.3 From e70ac288708c006251a80b7b69fc49423f19e454 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 22 Dec 2023 14:46:05 +0900 Subject: mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable() Enabling Octal DTR mode in multi-die package parts requires reister setup for each die. That can be done by simple for-loop. write_enable() takes effect to all die at once so we can call it before the loop. Besides we can replace spi_mem_exec_op() calls with spansion_read/write_any_reg(). And finally, we must mask CFR2V[7:4] when changing dummy cycles, as CFR2V[7] indicates current addressing mode and that should be 1 (4-byte address mode) for multi-die package parts. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- include/linux/mtd/spi-nor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 8a94e120372..d1dbf3eadbf 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -185,6 +185,7 @@ #define SPINOR_REG_CYPRESS_STR1V 0x00800000 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ -- cgit v1.2.3