From da16d72efd004e046b8b4f98a662afd4bef09206 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 20 Jan 2023 12:28:22 +0900 Subject: mtd: spi-nor-core: Make CFRx reg fields generic Cypress defines two flavors of configuration registers, volatile and non volatile, and both use the same bit fields. Rename the bitfields in the configuration registers so that they can be used for both flavors. Suggested-by: Tudor Ambarus Signed-off-by: Takahiro Kuwano Reviewed-by: Tudor Ambarus Reviewed-by: Dhruva Gole Reviewed-by: Jagan Teki --- include/linux/mtd/spi-nor.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2fb4595fc75..605cddef4d0 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -189,15 +189,15 @@ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_OP_S28_SE_4K 0x21 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 -#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 -#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ -#define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */ +#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ +#define SPINOR_REG_CYPRESS_CFR3_UNISECT BIT(3) /* Uniform sector mode */ #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ SPINOR_REG_CYPRESS_CFR5_OPI) #define SPINOR_OP_CYPRESS_RD_FAST 0xee -- cgit v1.2.3