From 7edf5c45f0d7f78ba370013cf513e3e8356c5202 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Feb 2017 16:21:52 +0800 Subject: serial: lpuart: add i.MX7ULP support Add i.MX7ULP support. The buadrate calculation on i.MX7ULP is different,so add a new setbrg function for i.MX7ULP. Add a enum lpuart_devtype for runtime check for different platforms. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Bhuvanchandra DV Cc: York Sun Cc: Shaohui Xie Cc: Alison Wang --- include/fsl_lpuart.h | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 include/fsl_lpuart.h (limited to 'include') diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h new file mode 100644 index 00000000000..4643ee79ee9 --- /dev/null +++ b/include/fsl_lpuart.h @@ -0,0 +1,72 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifdef CONFIG_ARCH_MX7ULP +struct lpuart_fsl_reg32 { + u32 verid; + u32 param; + u32 global; + u32 pincfg; + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl_reg32 { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#endif + +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; + +/* Used on i.MX7ULP */ +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000) +#define LPUART_BAUD_OSR_MASK (0x1F000000) +#define LPUART_BAUD_OSR_SHIFT (24) +#define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000) +#define LPUART_BAUD_SBR_MASK (0x1FFF) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_SBNS_MASK (0x2000U) -- cgit v1.3.1 From fa2f20d3c05c5163cf51cc536273177b6103e3eb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Feb 2017 16:21:54 +0800 Subject: arm: dts: add i.MX7ULP dtsi file Add i.MX7ULP dtsi file. Add clock and pinfun header files. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/dts/imx7ulp-pinfunc.h | 882 ++++++++++++++++++++++++++++++ arch/arm/dts/imx7ulp.dtsi | 598 ++++++++++++++++++++ include/dt-bindings/clock/imx7ulp-clock.h | 161 ++++++ 3 files changed, 1641 insertions(+) create mode 100644 arch/arm/dts/imx7ulp-pinfunc.h create mode 100644 arch/arm/dts/imx7ulp.dtsi create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h (limited to 'include') diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h new file mode 100644 index 00000000000..b1b6a71f2cd --- /dev/null +++ b/arch/arm/dts/imx7ulp-pinfunc.h @@ -0,0 +1,882 @@ +/* + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_ULP1_PINFUNC_H +#define __DTS_ULP1_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + * + * !!! IMPORTANT NOTE !!! + * + * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first + * two values are defined as same value. Extra non-zero mux2_reg value within the tuple + * means that there's additional mux2 control register that must be configured to + * mux2_val accordingly to fetch desired pin functionality on ULP1 device. + * + */ + +#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 +#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 +#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 +#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1 +#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 +#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1 +#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1 +#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1 +#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0 +#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 +#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1 +#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1 +#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1 +#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1 +#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1 +#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0 +#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 +#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1 +#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1 +#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1 +#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1 +#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1 +#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0 +#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 +#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1 +#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 +#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1 +#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1 +#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1 +#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0 +#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 +#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1 +#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1 +#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1 +#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1 +#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1 +#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1 +#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1 +#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1 +#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0 +#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0 +#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 +#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1 +#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1 +#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1 +#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1 +#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 +#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0 +#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 +#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 +#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1 +#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 +#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1 +#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1 +#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 +#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 +#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1 +#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1 +#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1 +#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1 +#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1 +#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1 +#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1 +#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2 +#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0 +#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 +#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1 +#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1 +#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1 +#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1 +#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1 +#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1 +#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2 +#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1 +#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1 +#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1 +#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2 +#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0 +#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 +#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 +#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1 +#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1 +#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1 +#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1 +#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2 +#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0 +#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 +#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 +#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2 +#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 +#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2 +#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1 +#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1 +#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2 +#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1 +#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1 +#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0 +#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 +#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 +#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2 +#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2 +#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2 +#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1 +#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1 +#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0 +#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 +#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 +#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2 +#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 +#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2 +#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2 +#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1 +#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0 +#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 +#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 +#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 +#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 +#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2 +#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2 +#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2 +#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2 +#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1 +#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1 +#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0 +#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 +#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 +#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2 +#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2 +#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2 +#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2 +#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1 +#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0 +#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 +#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 +#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2 +#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 +#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2 +#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2 +#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1 +#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 +#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 +#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 +#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2 +#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2 +#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2 +#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2 +#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1 +#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0 +#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2 +#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2 +#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1 +#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 +#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 +#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 +#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2 +#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2 +#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2 +#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2 +#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 +#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 +#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 +#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 +#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1 +#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 +#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1 +#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2 +#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 +#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0 +#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 +#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 +#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 +#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1 +#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1 +#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1 +#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2 +#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1 +#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0 +#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 +#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 +#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 +#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 +#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 +#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3 +#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3 +#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2 +#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2 +#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2 +#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0 +#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 +#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 +#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 +#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3 +#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3 +#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2 +#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2 +#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3 +#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3 +#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2 +#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0 +#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 +#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 +#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0 +#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 +#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3 +#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3 +#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3 +#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2 +#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 +#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 +#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 +#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0 +#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 +#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3 +#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3 +#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3 +#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2 +#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2 +#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2 +#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2 +#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0 +#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0 +#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0 +#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3 +#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3 +#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3 +#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2 +#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2 +#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0 +#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0 +#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3 +#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3 +#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3 +#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2 +#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0 +#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0 +#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0 +#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3 +#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3 +#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3 +#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2 +#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0 +#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0 +#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0 +#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3 +#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3 +#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3 +#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2 +#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0 +#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0 +#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3 +#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3 +#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3 +#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2 +#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3 +#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3 +#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0 +#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0 +#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0 +#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0 +#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3 +#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3 +#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3 +#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2 +#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3 +#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3 +#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0 +#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 +#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 +#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 +#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 +#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 +#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 +#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 +#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 +#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 +#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 +#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 +#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 +#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 +#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 +#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 +#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 +#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 +#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 +#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 +#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 +#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 +#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 +#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 +#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 +#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 +#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 +#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 +#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 +#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 +#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 +#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 +#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 +#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 +#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 +#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 +#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 +#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 +#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 +#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 +#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 +#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 +#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 +#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 +#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 +#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 +#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 +#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 +#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 +#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 +#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 +#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 +#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 + +#endif /* __DTS_ULP1_PINFUNC_H */ diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi new file mode 100644 index 00000000000..5497734a215 --- /dev/null +++ b/arch/arm/dts/imx7ulp.dtsi @@ -0,0 +1,598 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "skeleton.dtsi" +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + usbphy0 = &usbphy1; + i2c0 = &lpi2c4; + i2c1 = &lpi2c5; + i2c2 = &lpi2c6; + i2c3 = &lpi2c7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xC000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + rpmsg_reserved: rpmsg@9FFF0000 { + no-map; + reg = <0x9FF00000 0x100000>; + }; + + }; + + intc: interrupt-controller@40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + sirc: clock@2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + }; + + firc: clock@3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "firc"; + }; + + upll: clock@4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <480000000>; + clock-output-names = "upll"; + }; + + mpll: clock@5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <480000000>; + clock-output-names = "mpll"; + }; + }; + + sram: sram@20000000 { + compatible = "fsl,lpm-sram"; + reg = <0x1fffc000 0x4000>; + }; + + ahbbridge0: ahb-bridge0@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + edma0: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "nxp,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>; + }; + + mu: mu@40220000 { + compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu"; + reg = <0x40220000 0x1000>; + interrupts = , + ; + status = "okay"; + }; + + nmi: nmi@40220000 { + compatible = "fsl,imx7ulp-nmi"; + reg = <0x40220000 0x1000>; + interrupts = ; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7ulp-rpmsg"; + memory-region = <&rpmsg_reserved>; + status = "disabled"; + }; + + snvs: snvs@40230000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x40230000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = ; + clock-names = "snvs-rtc"; + clocks = <&clks IMX7ULP_CLK_SNVS>; + }; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPTPM5>; + }; + + lpit: 1@40270000 { + compatible = "fsl,imx-lpit"; + reg = <0x40270000 0x1000>; + interrupts = ; + /* clocks = <&lpclk>;*/ + clocks = <&clks IMX7ULP_CLK_LPIT1>; + assigned-clock-rates = <48000000>; + assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + }; + + lpi2c4: lpi2c4@402B0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402B0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: lpi2c4@402C0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402C0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C5>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi2: lpspi@40290000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPSPI2>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi3: lpspi@402A0000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x402A0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPSPI3>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart4: serial@402D0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402D0000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial@402E0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402E0000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 20>, <&edma0 0 19>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + usbotg1: usb@40330000 { + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x40330000 0x200>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_USB0>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@40330200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x40330200 0x200>; + }; + + usbphy1: usbphy@0x40350000 { + compatible = "fsl,imx7ulp-usbphy", + "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x40350000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_USB_PHY>; + nxp,sim = <&sim>; + }; + + usdhc0: usdhc@40370000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC0>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc1: usdhc@40380000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + wdog1: wdog@403D0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403D0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_WDG1>; + assigned-clocks = <&clks IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + /* + * As the 1KHz LPO clock rate is not trimed,the actually clock + * is about 667Hz, so the init timeout 60s should set 40*1000 + * in the TOVAL register. + */ + timeout-sec = <40>; + }; + + wdog2: wdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_WDG2>; + assigned-clocks = <&clks IMX7ULP_CLK_WDG2>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + timeout-sec = <40>; + }; + + clks: scg1@403E0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403E0000 0x10000>; + clocks = <&ckil>, <&osc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "ckil", "osc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, + <&clks IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + }; + + pcc2: pcc2@403F0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403F0000 0x10000>; + }; + + pmc1: pmc1@40400000 { + compatible = "fsl,imx7ulp-pmc1"; + reg = <0x40400000 0x1000>; + }; + + smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; + + }; + + ahbbridge1: ahb-bridge1@40800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + lpi2c6: lpi2c6@40A40000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40A40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C6>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: lpi2c7@40A50000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40A50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C7>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@40A60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A60000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART6>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 22>, <&edma0 0 21>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart7: serial@40A70000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A70000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPUART7>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <50000000>; + dmas = <&edma0 0 24>, <&edma0 0 23>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lcdif: lcdif@40AA0000 { + compatible = "fsl,imx7ulp-lcdif"; + reg = <0x40aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_LCDIF>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "axi", "pix", "disp_axi"; + status = "disabled"; + }; + + mipi_dsi: mipi_dsi@40A90000 { + compatible = "fsl,imx7ulp-mipi-dsi"; + reg = <0x40A90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_DSI>; + clock-names = "mipi_dsi_clk"; + sim = <&sim>; + status = "disabled"; + }; + + mmdc: mmdc@40ab0000 { + compatible = "fsl,imx7ulp-mmdc"; + reg = <0x40ab0000 0x4000>; + }; + + pcc3: pcc3@40B30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40B30000 0x10000>; + }; + + iomuxc: iomuxc@4103D000 { + compatible = "fsl,imx7ulp-iomuxc-0"; + reg = <0x4103D000 0x1000>; + fsl,mux_mask = <0xf00>; + status = "disabled"; + }; + + iomuxc1: iomuxc1@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc-1"; + reg = <0x40ac0000 0x1000>; + fsl,mux_mask = <0xf00>; + }; + + gpio0: gpio@40ae0000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40ae0000 0x1000 0x400F0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 0 32>; + }; + + gpio1: gpio@40af0000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40af0000 0x1000 0x400F0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 32 32>; + }; + + gpio2: gpio@40b00000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40b00000 0x1000 0x400F0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + gpio3: gpio@40b10000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40b10000 0x1000 0x400F00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 96 32>; + }; + + pmc0: pmc0@410a1000 { + compatible = "fsl,imx7ulp-pmc0"; + reg = <0x410a1000 0x1000>; + }; + + sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; + + qspi1: qspi@410A5000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-qspi"; + reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + gpu: gpu@41800000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x41800000 0x80000>, <0x41880000 0x80000>, + <0x60000000 0x40000000>, <0x0 0x4000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = , + ; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX7ULP_CLK_GPU3D>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_GPU_DIV>, + <&clks IMX7ULP_CLK_GPU2D>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu2d_shader_clk", "gpu2d_axi_clk"; + }; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; +}; diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h new file mode 100644 index 00000000000..0a955df4ad8 --- /dev/null +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +#define __DT_BINDINGS_CLOCK_IMX7ULP_H + +#define IMX7ULP_CLK_DUMMY 0 +#define IMX7ULP_CLK_CKIL 1 +#define IMX7ULP_CLK_OSC 2 +#define IMX7ULP_CLK_FIRC 3 + +/* SCG1 */ +#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +#define IMX7ULP_CLK_SPLL 6 +#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +#define IMX7ULP_CLK_SPLL_PFD0 9 +#define IMX7ULP_CLK_SPLL_PFD1 10 +#define IMX7ULP_CLK_SPLL_PFD2 11 +#define IMX7ULP_CLK_SPLL_PFD3 12 +#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +#define IMX7ULP_CLK_SPLL_SEL 14 +#define IMX7ULP_CLK_APLL_PRE_SEL 15 +#define IMX7ULP_CLK_APLL_PRE_DIV 16 +#define IMX7ULP_CLK_APLL 17 +#define IMX7ULP_CLK_APLL_POST_DIV1 18 +#define IMX7ULP_CLK_APLL_POST_DIV2 19 +#define IMX7ULP_CLK_APLL_PFD0 20 +#define IMX7ULP_CLK_APLL_PFD1 21 +#define IMX7ULP_CLK_APLL_PFD2 22 +#define IMX7ULP_CLK_APLL_PFD3 23 +#define IMX7ULP_CLK_APLL_PFD_SEL 24 +#define IMX7ULP_CLK_APLL_SEL 25 +#define IMX7ULP_CLK_UPLL 26 +#define IMX7ULP_CLK_SYS_SEL 27 +#define IMX7ULP_CLK_CORE_DIV 28 +#define IMX7ULP_CLK_BUS_DIV 29 +#define IMX7ULP_CLK_PLAT_DIV 30 +#define IMX7ULP_CLK_DDR_SEL 31 +#define IMX7ULP_CLK_DDR_DIV 32 +#define IMX7ULP_CLK_NIC_SEL 33 +#define IMX7ULP_CLK_NIC0_DIV 34 +#define IMX7ULP_CLK_GPU_DIV 35 +#define IMX7ULP_CLK_NIC1_DIV 36 +#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +#define IMX7ULP_CLK_NIC1_EXT_DIV 38 + +/* PCG2 */ +#define IMX7ULP_CLK_DMA1 39 +#define IMX7ULP_CLK_RGPIO2P1 40 +#define IMX7ULP_CLK_FLEXBUS 41 +#define IMX7ULP_CLK_SEMA42_1 42 +#define IMX7ULP_CLK_DMA_MUX1 43 +#define IMX7ULP_CLK_SNVS 44 +#define IMX7ULP_CLK_CAAM 45 +#define IMX7ULP_CLK_LPTPM4 46 +#define IMX7ULP_CLK_LPTPM5 47 +#define IMX7ULP_CLK_LPIT1 48 +#define IMX7ULP_CLK_LPSPI2 49 +#define IMX7ULP_CLK_LPSPI3 50 +#define IMX7ULP_CLK_LPI2C4 51 +#define IMX7ULP_CLK_LPI2C5 52 +#define IMX7ULP_CLK_LPUART4 53 +#define IMX7ULP_CLK_LPUART5 54 +#define IMX7ULP_CLK_FLEXIO1 55 +#define IMX7ULP_CLK_USB0 56 +#define IMX7ULP_CLK_USB1 57 +#define IMX7ULP_CLK_USB_PHY 58 +#define IMX7ULP_CLK_USB_PL301 59 +#define IMX7ULP_CLK_USDHC0 60 +#define IMX7ULP_CLK_USDHC1 61 +#define IMX7ULP_CLK_WDG1 62 +#define IMX7ULP_CLK_WDG2 63 + +/* PCG3 */ +#define IMX7ULP_CLK_LPTPM6 64 +#define IMX7ULP_CLK_LPTPM7 65 +#define IMX7ULP_CLK_LPI2C6 66 +#define IMX7ULP_CLK_LPI2C7 67 +#define IMX7ULP_CLK_LPUART6 68 +#define IMX7ULP_CLK_LPUART7 69 +#define IMX7ULP_CLK_VIU 70 +#define IMX7ULP_CLK_DSI 71 +#define IMX7ULP_CLK_LCDIF 72 +#define IMX7ULP_CLK_MMDC 73 +#define IMX7ULP_CLK_PCTLC 74 +#define IMX7ULP_CLK_PCTLD 75 +#define IMX7ULP_CLK_PCTLE 76 +#define IMX7ULP_CLK_PCTLF 77 +#define IMX7ULP_CLK_GPU3D 78 +#define IMX7ULP_CLK_GPU2D 79 + +#define IMX7ULP_CLK_MIPI_PLL 80 +#define IMX7ULP_CLK_SIRC 81 + +#define IMX7ULP_CLK_SCG1_CLKOUT 82 + +#define IMX7ULP_CLK_END 83 + +/*cm4 clocks*/ +#define IMX7ULP_CM4_CLK_DUMMY 0 +#define IMX7ULP_CM4_CLK_CKIL 1 +#define IMX7ULP_CM4_CLK_OSC 2 +#define IMX7ULP_CM4_CLK_FIRC 3 +#define IMX7ULP_CM4_CLK_SIRC 4 + +/* SCG0 */ +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5 +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6 +#define IMX7ULP_CM4_CLK_SPLL 7 +#define IMX7ULP_CM4_CLK_SPLL_VCO 8 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10 +#define IMX7ULP_CM4_CLK_SPLL_PFD0 11 +#define IMX7ULP_CM4_CLK_SPLL_PFD1 12 +#define IMX7ULP_CM4_CLK_SPLL_PFD2 13 +#define IMX7ULP_CM4_CLK_SPLL_PFD3 14 +#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15 +#define IMX7ULP_CM4_CLK_SPLL_PFD 16 +#define IMX7ULP_CM4_CLK_SPLL_SEL 17 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19 +#define IMX7ULP_CM4_CLK_APLL 20 +#define IMX7ULP_CM4_CLK_APLL_VCO 21 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23 +#define IMX7ULP_CM4_CLK_APLL_PFD0 24 +#define IMX7ULP_CM4_CLK_APLL_PFD1 25 +#define IMX7ULP_CM4_CLK_APLL_PFD2 26 +#define IMX7ULP_CM4_CLK_APLL_PFD3 27 +#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28 +#define IMX7ULP_CM4_CLK_APLL_PFD 29 +#define IMX7ULP_CM4_CLK_APLL_SEL 30 +#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31 +#define IMX7ULP_CM4_CLK_SYS_SEL 32 +#define IMX7ULP_CM4_CLK_CORE_DIV 33 +#define IMX7ULP_CM4_CLK_BUS_DIV 34 +#define IMX7ULP_CM4_CLK_PLAT_DIV 35 +#define IMX7ULP_CM4_CLK_SLOW_DIV 36 + +#define IMX7ULP_CM4_CLK_SAI0_SEL 37 +#define IMX7ULP_CM4_CLK_SAI0_DIV 38 +#define IMX7ULP_CM4_CLK_SAI0_ROOT 39 +#define IMX7ULP_CM4_CLK_SAI0_IPG 40 +#define IMX7ULP_CM4_CLK_SAI1_SEL 41 +#define IMX7ULP_CM4_CLK_SAI1_DIV 42 +#define IMX7ULP_CM4_CLK_SAI1_ROOT 43 +#define IMX7ULP_CM4_CLK_SAI1_IPG 44 + +#define IMX7ULP_CLK_SCG0_CLKOUT 45 + +#define IMX7ULP_CM4_CLK_END 46 + +#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ -- cgit v1.3.1 From 77fa04577acbb07753ec4800f2a0410d8d37fe61 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Feb 2017 16:21:56 +0800 Subject: imx: imx7ulp: add EVK board support Add EVK board support. Add the evk dts file. LOG: U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800) CPU: Freescale i.MX7ULP rev1.0 at 500 MHz Reset cause: POR Boot mode: Dual boot Model: NXP i.MX7ULP EVK DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial@402D0000 Out: serial@402D0000 Err: serial@402D0000 Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx7ulp/Kconfig | 11 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7ulp-evk.dts | 426 ++++++++++++++++++++++++++++++++ arch/arm/dts/imx7ulp-uboot.dtsi | 43 ++++ board/freescale/mx7ulp_evk/Kconfig | 12 + board/freescale/mx7ulp_evk/MAINTAINERS | 7 + board/freescale/mx7ulp_evk/Makefile | 10 + board/freescale/mx7ulp_evk/imximage.cfg | 137 ++++++++++ board/freescale/mx7ulp_evk/mx7ulp_evk.c | 48 ++++ board/freescale/mx7ulp_evk/plugin.S | 224 +++++++++++++++++ configs/mx7ulp_evk_defconfig | 17 ++ configs/mx7ulp_evk_plugin_defconfig | 18 ++ include/configs/mx7ulp_evk.h | 109 ++++++++ 13 files changed, 1064 insertions(+) create mode 100644 arch/arm/dts/imx7ulp-evk.dts create mode 100644 arch/arm/dts/imx7ulp-uboot.dtsi create mode 100644 board/freescale/mx7ulp_evk/Kconfig create mode 100644 board/freescale/mx7ulp_evk/MAINTAINERS create mode 100644 board/freescale/mx7ulp_evk/Makefile create mode 100644 board/freescale/mx7ulp_evk/imximage.cfg create mode 100644 board/freescale/mx7ulp_evk/mx7ulp_evk.c create mode 100644 board/freescale/mx7ulp_evk/plugin.S create mode 100644 configs/mx7ulp_evk_defconfig create mode 100644 configs/mx7ulp_evk_plugin_defconfig create mode 100644 include/configs/mx7ulp_evk.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx7ulp/Kconfig b/arch/arm/cpu/armv7/mx7ulp/Kconfig index 85efd6d5d88..1bdc85a9a03 100644 --- a/arch/arm/cpu/armv7/mx7ulp/Kconfig +++ b/arch/arm/cpu/armv7/mx7ulp/Kconfig @@ -3,4 +3,15 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp" +choice + prompt "MX7ULP board select" + optional + +config TARGET_MX7ULP_EVK + bool "Support mx7ulp EVK board" + +endchoice + +source "board/freescale/mx7ulp_evk/Kconfig" + endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 231ebfa7db8..7be5c02d1c5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -320,6 +320,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ dtb-$(CONFIG_MX7) += imx7-colibri.dtb +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts new file mode 100644 index 00000000000..e56b7226e6f --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -0,0 +1,426 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; + stdout-path = &lpuart4; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3b: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VSD_3V3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon_usb1>; + }; + + pf1550-rpmsg { + compatible = "fsl,pf1550-rpmsg"; + sw1_reg: SW1 { + regulator-name = "SW1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: SW2 { + regulator-name = "SW2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: SW3 { + regulator-name = "SW3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: VREFDDR { + regulator-name = "VREFDDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7ulp-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */ + ULP1_PAD_PTC1__PTC1 0x20100 + ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */ + ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */ + ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */ + ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */ + >; + }; + + pinctrl_backlight: backlight_grp { + fsl,pins = < + ULP1_PAD_PTF2__PTF2 0x20100 + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + ULP1_PAD_PTC4__LPI2C5_SCL 0x527 + ULP1_PAD_PTC5__LPI2C5_SDA 0x527 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + ULP1_PAD_PTC19__PTC19 0x20103 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + ULP1_PAD_PTC3__LPUART4_RX 0x400 + ULP1_PAD_PTC2__LPUART4_TX 0x400 + >; + }; + + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + ULP1_PAD_PTE10__LPUART6_TX 0x400 + ULP1_PAD_PTE11__LPUART6_RX 0x400 + ULP1_PAD_PTE9__LPUART6_RTS_B 0x400 + ULP1_PAD_PTE8__LPUART6_CTS_B 0x400 + ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */ + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + ULP1_PAD_PTF14__LPUART7_TX 0x400 + ULP1_PAD_PTF15__LPUART7_RX 0x400 + ULP1_PAD_PTF13__LPUART7_RTS_B 0x400 + ULP1_PAD_PTF12__LPUART7_CTS_B 0x400 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + ULP1_PAD_PTD1__SDHC0_CMD 0x843 + ULP1_PAD_PTD2__SDHC0_CLK 0x10843 + ULP1_PAD_PTD7__SDHC0_D3 0x843 + ULP1_PAD_PTD8__SDHC0_D2 0x843 + ULP1_PAD_PTD9__SDHC0_D1 0x843 + ULP1_PAD_PTD10__SDHC0_D0 0x843 + >; + }; + + pinctrl_usdhc0_8bit: usdhc0grp_8bit { + fsl,pins = < + ULP1_PAD_PTD1__SDHC0_CMD 0x843 + ULP1_PAD_PTD2__SDHC0_CLK 0x843 + ULP1_PAD_PTD3__SDHC0_D7 0x843 + ULP1_PAD_PTD4__SDHC0_D6 0x843 + ULP1_PAD_PTD5__SDHC0_D5 0x843 + ULP1_PAD_PTD6__SDHC0_D4 0x843 + ULP1_PAD_PTD7__SDHC0_D3 0x843 + ULP1_PAD_PTD8__SDHC0_D2 0x843 + ULP1_PAD_PTD9__SDHC0_D1 0x843 + ULP1_PAD_PTD10__SDHC0_D0 0x843 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + ULP1_PAD_PTF12__LPI2C7_SCL 0x527 + ULP1_PAD_PTF13__LPI2C7_SDA 0x527 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + ULP1_PAD_PTF16__LPSPI3_SIN 0x300 + ULP1_PAD_PTF17__LPSPI3_SOUT 0x300 + ULP1_PAD_PTF18__LPSPI3_SCK 0x300 + ULP1_PAD_PTF19__LPSPI3_PCS0 0x300 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + ULP1_PAD_PTC0__PTC0 0x30100 + >; + }; + + pinctrl_extcon_usb1: extcon1grp { + fsl,pins = < + ULP1_PAD_PTC8__PTC8 0x30103 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + ULP1_PAD_PTE3__SDHC1_CMD 0x843 + ULP1_PAD_PTE2__SDHC1_CLK 0x843 + ULP1_PAD_PTE1__SDHC1_D0 0x843 + ULP1_PAD_PTE0__SDHC1_D1 0x843 + ULP1_PAD_PTE5__SDHC1_D2 0x843 + ULP1_PAD_PTE4__SDHC1_D3 0x843 + >; + }; + + pinctrl_usdhc1_rst: usdhc1grp_rst { + fsl,pins = < + ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */ + >; + }; + }; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c5>; + status = "okay"; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + }; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + +&lpuart4 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&lpuart6 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart6>; + status = "okay"; +}; + +&lpuart7 { /* Uart test */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; + status = "disabled"; +}; + +&rpmsg{ + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + extcon = <0>, <&extcon_usb1>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + vqmmc-supply = <&vldo2_reg>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7ulp-uboot.dtsi b/arch/arm/dts/imx7ulp-uboot.dtsi new file mode 100644 index 00000000000..712cec49219 --- /dev/null +++ b/arch/arm/dts/imx7ulp-uboot.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&soc { + u-boot,dm-pre-reloc; +}; + +&ahbbridge0 { + u-boot,dm-pre-reloc; +}; + +&ahbbridge1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&iomuxc1 { + u-boot,dm-pre-reloc; +}; + +&lpuart4 { + u-boot,dm-pre-reloc; +}; + +&lpuart5 { + u-boot,dm-pre-reloc; +}; + +&lpuart6 { + u-boot,dm-pre-reloc; +}; + +&lpuart7 { + u-boot,dm-pre-reloc; +}; diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig new file mode 100644 index 00000000000..ff448311f9d --- /dev/null +++ b/board/freescale/mx7ulp_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX7ULP_EVK + +config SYS_BOARD + default "mx7ulp_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7ulp_evk" + +endif diff --git a/board/freescale/mx7ulp_evk/MAINTAINERS b/board/freescale/mx7ulp_evk/MAINTAINERS new file mode 100644 index 00000000000..1aa26445632 --- /dev/null +++ b/board/freescale/mx7ulp_evk/MAINTAINERS @@ -0,0 +1,7 @@ +MX7ULPEVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/mx7ulp_evk/ +F: include/configs/mx7ulp_evk.h +F: configs/mx7ulp_evk_defconfig +F: configs/mx7ulp_evk_plugin_defconfig diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile new file mode 100644 index 00000000000..5e19eb48592 --- /dev/null +++ b/board/freescale/mx7ulp_evk/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7ulp_evk.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg new file mode 100644 index 00000000000..e4e4cb3b217 --- /dev/null +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00dc 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00140000 +DATA 4 0x403E0510 0x00000004 +DATA 4 0x403E0514 0x00000002 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x8080801E +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00dc 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x40404040 +DATA 4 0x40AB0850 0x40404040 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB082C 0xf3333333 +DATA 4 0x40AB0830 0xf3333333 +DATA 4 0x40AB0834 0xf3333333 +DATA 4 0x40AB0838 0xf3333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x292C42F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DB +DATA 4 0x40AB0018 0x00211718 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3190000 + +DATA 4 0x40AB001C 0x00008050 +DATA 4 0x40AB001C 0x00008058 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x04028038 +DATA 4 0x40AB001C 0x83018030 +DATA 4 0x40AB001C 0x83018038 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x01038038 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310000 +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB0404 0x00011006 +DATA 4 0x40AB001C 0x00000000 +#endif diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c new file mode 100644 index 00000000000..361871525ef --- /dev/null +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, + ARRAY_SIZE(lpuart4_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S new file mode 100644 index 00000000000..9eab36520a5 --- /dev/null +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.macro imx7ulp_ddr_freq_decrease + ldr r2, =0x403f0000 + ldr r3, =0x00000000 + str r3, [r2, #0xdc] + + ldr r2, =0x403e0000 + ldr r3, =0x01000020 + str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500] + ldr r3, =0x80808080 + str r3, [r2, #0x50c] + ldr r3, =0x00140000 + str r3, [r2, #0x508] + ldr r3, =0x00000004 + str r3, [r2, #0x510] + ldr r3, =0x00000002 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x8080801E + str r3, [r2, #0x50c] + + ldr r3, =0x00000040 +wait2: + ldr r4, [r2, #0x50c] + and r4, r3 + cmp r4, r3 + bne wait2 + + ldr r3, =0x00000001 + str r3, [r2, #0x30] + ldr r3, =0x11000020 + str r3, [r2, #0x40] + + ldr r2, =0x403f0000 + ldr r3, =0x42000000 + str r3, [r2, #0xdc] + +.endm + +.macro imx7ulp_evk_ddr_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x00000180 + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x40404040 + str r1, [r0, #0x848] + ldr r1, =0x40404040 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82c] + ldr r1, =0xf3333333 + str r1, [r0, #0x830] + ldr r1, =0xf3333333 + str r1, [r0, #0x834] + ldr r1, =0xf3333333 + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x292C42F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DB + str r1, [r0, #0x14] + ldr r1, =0x00211718 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000003F + str r1, [r0, #0x40] + ldr r1, =0xC3190000 + str r1, [r0, #0x0] + + ldr r1, =0x00008050 + str r1, [r0, #0x1c] + ldr r1, =0x00008058 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0x003F8038 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x04028038 + str r1, [r0, #0x1c] + ldr r1, =0x83018030 + str r1, [r0, #0x1c] + ldr r1, =0x83018038 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + ldr r1, =0x01038038 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1310000 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + +.macro imx7ulp_clock_gating +.endm + +.macro imx7ulp_qos_setting +.endm + +.macro imx7ulp_ddr_setting + imx7ulp_evk_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig new file mode 100644 index 00000000000..8c7446b8e26 --- /dev/null +++ b/configs/mx7ulp_evk_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_I2C=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_LPI2C_IMX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig new file mode 100644 index 00000000000..87a93247524 --- /dev/null +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_I2C=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_LPI2C_IMX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h new file mode 100644 index 00000000000..2604232d397 --- /dev/null +++ b/include/configs/mx7ulp_evk.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7ULP EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7ULP_EVK_CONFIG_H +#define __MX7ULP_EVK_CONFIG_H + +#include +#include + +/*Uncomment it to use secure boot*/ +/*#define CONFIG_SECURE_BOOT*/ + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_8K + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*#define CONFIG_REVISION_TAG*/ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F + +/* UART */ +#define LPUART_BASE LPUART4_RBASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_8K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_TEXT_BASE 0x67800000 +#define PHYS_SDRAM 0x60000000 +#define PHYS_SDRAM_SIZE SZ_1G +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_CMD_BOOTZ + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_END 0x9E000000 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 04cb0d3e3fcee139fdf84b4d0da28bc1a184fa1d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Feb 2017 16:21:57 +0800 Subject: imx: mx7ulp_evk: enable mmc/regulator support Enable MMC support. The fsl sdhc driver needs regulator to enable power, so enable regulator support. And bootcmd and more env. Signed-off-by: Peng Fan Cc: Stefano Babic --- configs/mx7ulp_evk_defconfig | 8 ++++ configs/mx7ulp_evk_plugin_defconfig | 8 ++++ include/configs/mx7ulp_evk.h | 91 ++++++++++++++++++++++++++++++++++++- 3 files changed, 106 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 8c7446b8e26..ea2a0cf2a58 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -15,3 +15,11 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CMD_GPIO=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 87a93247524..d4c36d9c00f 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -16,3 +16,11 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CMD_GPIO=y diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 2604232d397..f6e4b3bc789 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -28,7 +28,21 @@ #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_CMD_FAT @@ -91,6 +105,81 @@ #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_END 0x9E000000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7ulp-evk.dtb\0" \ + "fdt_addr=0x63000000\0" \ + "boot_fdt=try\0" \ + "earlycon=lpuart32,0x402D0010\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "usb start; "\ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v1.3.1 From 85392deda184a57e8b61c1e524288bed3f81d400 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:32:53 +0530 Subject: configs: imx6: Don't define USDHC2_BASE_ADDR USDHC base address will assigned by SPL using fsl_esdhc_initialize and u-boot with devicetree, hence no remove base address assignment in config files. Cc: Matteo Lisi Cc: Michael Trimarchi Reviewed-by: Stefano Babic Signed-off-by: Jagan Teki --- include/configs/imx6qdl_icore.h | 2 +- include/configs/imx6ul_geam.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index eb83d237ed8..5a28b15afc7 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -147,7 +147,7 @@ #ifdef CONFIG_FSL_USDHC # define CONFIG_SYS_MMC_ENV_DEV 0 # define CONFIG_SYS_FSL_USDHC_NUM 1 -# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif /* NAND */ diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 23fa3ee1628..8bffacde4df 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -145,7 +145,7 @@ #ifdef CONFIG_FSL_USDHC # define CONFIG_SYS_MMC_ENV_DEV 0 # define CONFIG_SYS_FSL_USDHC_NUM 1 -# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif /* NAND */ -- cgit v1.3.1 From e9dfa1e1e521218fc893cea6731f482cfd2193d4 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:32:54 +0530 Subject: arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support Boot from MMC: ------------- U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33) Trying to boot from MMC1 U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 33C Reset cause: POR Model: Engicam Is.IoT MX6UL Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 isiotmx6ul> Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/cpu/armv7/mx6/Kconfig | 10 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-isiot-mmc.dts | 50 +++++++ arch/arm/dts/imx6ul-isiot.dtsi | 92 +++++++++++++ board/engicam/isiotmx6ul/Kconfig | 12 ++ board/engicam/isiotmx6ul/MAINTAINERS | 8 ++ board/engicam/isiotmx6ul/Makefile | 6 + board/engicam/isiotmx6ul/README | 28 ++++ board/engicam/isiotmx6ul/isiotmx6ul.c | 246 ++++++++++++++++++++++++++++++++++ configs/imx6ul_isiot_mmc_defconfig | 36 +++++ include/configs/imx6ul_isiot.h | 142 ++++++++++++++++++++ 11 files changed, 632 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-isiot-mmc.dts create mode 100644 arch/arm/dts/imx6ul-isiot.dtsi create mode 100644 board/engicam/isiotmx6ul/Kconfig create mode 100644 board/engicam/isiotmx6ul/MAINTAINERS create mode 100644 board/engicam/isiotmx6ul/Makefile create mode 100644 board/engicam/isiotmx6ul/README create mode 100644 board/engicam/isiotmx6ul/isiotmx6ul.c create mode 100644 configs/imx6ul_isiot_mmc_defconfig create mode 100644 include/configs/imx6ul_isiot.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 744d67ab862..928cdb49bc1 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -241,6 +241,15 @@ config TARGET_MX6UL_GEAM select DM_MMC select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6UL_ISIOT + bool "Support Engicam Is.IoT MX6UL" + select MX6UL + select OF_CONTROL + select DM + select DM_GPIO + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL config TARGET_MX6ULL_14X14_EVK bool "Support mx6ull_14x14_evk" @@ -362,6 +371,7 @@ source "board/embest/mx6boards/Kconfig" source "board/engicam/geam6ul/Kconfig" source "board/engicam/icorem6/Kconfig" source "board/engicam/icorem6_rqs/Kconfig" +source "board/engicam/isiotmx6ul/Kconfig" source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7be5c02d1c5..a4a4b1e008a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -316,7 +316,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6q-icore.dtb \ imx6q-icore-rqs.dtb \ imx6sx-sabreauto.dtb \ - imx6ul-geam-kit.dtb + imx6ul-geam-kit.dtb \ + imx6ul-isiot-mmc.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb diff --git a/arch/arm/dts/imx6ul-isiot-mmc.dts b/arch/arm/dts/imx6ul-isiot-mmc.dts new file mode 100644 index 00000000000..bb5086a68af --- /dev/null +++ b/arch/arm/dts/imx6ul-isiot-mmc.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul-isiot.dtsi" + +/ { + model = "Engicam Is.IoT MX6UL MMC Starterkit"; + compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +}; diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi new file mode 100644 index 00000000000..6108a1af5e7 --- /dev/null +++ b/arch/arm/dts/imx6ul-isiot.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include +#include "imx6ul.dtsi" + +/ { + memory { + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; +}; diff --git a/board/engicam/isiotmx6ul/Kconfig b/board/engicam/isiotmx6ul/Kconfig new file mode 100644 index 00000000000..213ffad8b6a --- /dev/null +++ b/board/engicam/isiotmx6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6UL_ISIOT + +config SYS_BOARD + default "isiotmx6ul" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "imx6ul_isiot" + +endif diff --git a/board/engicam/isiotmx6ul/MAINTAINERS b/board/engicam/isiotmx6ul/MAINTAINERS new file mode 100644 index 00000000000..558e5163e6c --- /dev/null +++ b/board/engicam/isiotmx6ul/MAINTAINERS @@ -0,0 +1,8 @@ +ISIOTMX6UL BOARD +M: Jagan Teki +S: Maintained +F: board/engicam/isiotmx6ul +F: include/configs/imx6ul_isiot.h +F: configs/imx6ul_isiot_mmc_defconfig +F: arch/arm/dts/imx6ul-isiot.dtsi +F: arch/arm/dts/imx6ul-isiot-mmc.dts diff --git a/board/engicam/isiotmx6ul/Makefile b/board/engicam/isiotmx6ul/Makefile new file mode 100644 index 00000000000..f4f8c780ae7 --- /dev/null +++ b/board/engicam/isiotmx6ul/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2016 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := isiotmx6ul.o diff --git a/board/engicam/isiotmx6ul/README b/board/engicam/isiotmx6ul/README new file mode 100644 index 00000000000..1d177ac625a --- /dev/null +++ b/board/engicam/isiotmx6ul/README @@ -0,0 +1,28 @@ +How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit: +----------------------------------------------------- + +- Configure U-Boot for Engicam Is.IoT MX6UL + +$ make mrproper +$ make imx6ul_isiot_mmc_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot-dtb.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot-dtb.img image into the micro SD card: + +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +MMC Boot: JM3 Closed + +- Connect the Serial cable between the Starter Kit and the PC for the console. +(J28 is the Linux Serial console connector) + +- Insert the micro SD card in the board, power it up and U-Boot messages should +come up. diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c new file mode 100644 index 00000000000..b1372d097aa --- /dev/null +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include +#include + +#include +#include + +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include +#include + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif /* CONFIG_FSL_ESDHC */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00c03f3f, &ccm->CCGR0); + writel(0xfcffff00, &ccm->CCGR1); + writel(0x0cffffcc, &ccm->CCGR2); + writel(0x3f3c3030, &ccm->CCGR3); + writel(0xff00fffc, &ccm->CCGR4); + writel(0x033f30ff, &ccm->CCGR5); + writel(0x00c00fff, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx6ul_isiot_mmc_defconfig b/configs/imx6ul_isiot_mmc_defconfig new file mode 100644 index 00000000000..66eb59f5638 --- /dev/null +++ b/configs/imx6ul_isiot_mmc_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6UL_ISIOT=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-mmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="isiotmx6ul> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h new file mode 100644 index 00000000000..aba43fc65eb --- /dev/null +++ b/include/configs/imx6ul_isiot.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * Configuration settings for the Engicam Is.IoT MX6UL Starter Kits. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX6UL_ISIOT_CONFIG_H +#define __IMX6UL_ISIOT_CONFIG_H + +#include +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE SZ_128K + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +/* Environment in MMC */ +# if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_ENV_OFFSET 0x100000 +# endif +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=uImage\0" \ + "fit_image=fit.itb\0" \ + "splashpos=m,m\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x87800000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \ + "fitboot=echo Booting FIT image from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi\0" + +# define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +/* FIT */ +#ifdef CONFIG_FIT +# define CONFIG_HASH_VERIFY +# define CONFIG_SHA1 +# define CONFIG_SHA256 +# define CONFIG_IMAGE_FORMAT_LEGACY +#endif + +/* UART */ +#ifdef CONFIG_MXC_UART +# define CONFIG_MXC_UART_BASE UART1_BASE +#endif + +/* MMC */ +#ifdef CONFIG_FSL_USDHC +# define CONFIG_SYS_MMC_ENV_DEV 0 +# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#endif + +/* SPL */ +#ifdef CONFIG_SPL +# define CONFIG_SPL_MMC_SUPPORT + +# include "imx6_spl.h" +# ifdef CONFIG_SPL_BUILD +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif +#endif + +#endif /* __IMX6UL_ISIOT_CONFIG_H */ -- cgit v1.3.1 From 0421a164de22aeb02c6831d0a997853a36f0b963 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:32:58 +0530 Subject: imx6: isiotmx6ul: Add FEC support Add FEC support for Engicam Is.IoT MX6UL module. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/cpu/armv7/mx6/Kconfig | 1 + configs/imx6ul_isiot_mmc_defconfig | 3 +++ include/configs/imx6ul_isiot.h | 10 ++++++++++ 3 files changed, 14 insertions(+) (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 3de1be5b1b0..0bceaac9b05 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -246,6 +246,7 @@ config TARGET_MX6UL_ISIOT select MX6UL select OF_CONTROL select DM + select DM_ETH select DM_GPIO select DM_I2C select DM_MMC diff --git a/configs/imx6ul_isiot_mmc_defconfig b/configs/imx6ul_isiot_mmc_defconfig index 7a7be23a0a6..8ecdd8e5691 100644 --- a/configs/imx6ul_isiot_mmc_defconfig +++ b/configs/imx6ul_isiot_mmc_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y @@ -32,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y # CONFIG_BLK is not set CONFIG_SYS_I2C_MXC=y # CONFIG_DM_MMC_OPS is not set +CONFIG_FEC_MXC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index aba43fc65eb..5a3e05abcc8 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -128,6 +128,16 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +# define CONFIG_FEC_MXC_PHYADDR 0 +# define CONFIG_FEC_XCV_TYPE RMII + +# define CONFIG_MII +# define CONFIG_PHYLIB +# define CONFIG_PHY_SMSC +#endif + /* SPL */ #ifdef CONFIG_SPL # define CONFIG_SPL_MMC_SUPPORT -- cgit v1.3.1 From 6788a7e4e9b587a1d9d3c401e7caca65bb6bd5d1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:32:59 +0530 Subject: imx6: isiotmx6ul: Add NAND support Add NAND support for Engicam Is.IoT MX6UL board. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-isiot-nand.dts | 50 +++++++++++++++++++++++++ board/engicam/isiotmx6ul/MAINTAINERS | 2 + board/engicam/isiotmx6ul/isiotmx6ul.c | 69 +++++++++++++++++++++++++++++++++++ configs/imx6ul_isiot_nand_defconfig | 39 ++++++++++++++++++++ include/configs/imx6ul_isiot.h | 25 ++++++++++++- 6 files changed, 186 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx6ul-isiot-nand.dts create mode 100644 configs/imx6ul_isiot_nand_defconfig (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a4a4b1e008a..9012f69ceeb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -317,7 +317,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6q-icore-rqs.dtb \ imx6sx-sabreauto.dtb \ imx6ul-geam-kit.dtb \ - imx6ul-isiot-mmc.dtb + imx6ul-isiot-mmc.dtb \ + imx6ul-isiot-nand.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb diff --git a/arch/arm/dts/imx6ul-isiot-nand.dts b/arch/arm/dts/imx6ul-isiot-nand.dts new file mode 100644 index 00000000000..12a35284285 --- /dev/null +++ b/arch/arm/dts/imx6ul-isiot-nand.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul-isiot.dtsi" + +/ { + model = "Engicam Is.IoT MX6UL NAND Starterkit"; + compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +}; diff --git a/board/engicam/isiotmx6ul/MAINTAINERS b/board/engicam/isiotmx6ul/MAINTAINERS index 558e5163e6c..f4dcfbde173 100644 --- a/board/engicam/isiotmx6ul/MAINTAINERS +++ b/board/engicam/isiotmx6ul/MAINTAINERS @@ -4,5 +4,7 @@ S: Maintained F: board/engicam/isiotmx6ul F: include/configs/imx6ul_isiot.h F: configs/imx6ul_isiot_mmc_defconfig +F: configs/imx6ul_isiot_nand_defconfig F: arch/arm/dts/imx6ul-isiot.dtsi F: arch/arm/dts/imx6ul-isiot-mmc.dts +F: arch/arm/dts/imx6ul-isiot-nand.dts diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index b1372d097aa..20c8aa71473 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -37,11 +37,80 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_NAND_MXS + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif /* CONFIG_NAND_MXS */ + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif return 0; } diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig new file mode 100644 index 00000000000..2af146f405d --- /dev/null +++ b/configs/imx6ul_isiot_nand_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6UL_ISIOT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" +CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-nand.dtb" +CONFIG_SPL=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="isiotmx6ul> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_NAND_MXS=y +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index 5a3e05abcc8..b1378485fe9 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -27,6 +27,10 @@ /* Environment in MMC */ # if defined(CONFIG_ENV_IS_IN_MMC) # define CONFIG_ENV_OFFSET 0x100000 +/* Environment in NAND */ +# elif defined(CONFIG_ENV_IS_IN_NAND) +# define CONFIG_ENV_OFFSET 0x400000 +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -128,6 +132,21 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif +/* NAND */ +#ifdef CONFIG_NAND_MXS +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 +# define CONFIG_SYS_NAND_5_ADDR_CYCLE +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +/* APBH DMA */ +# define CONFIG_APBH_DMA +# define CONFIG_APBH_DMA_BURST +# define CONFIG_APBH_DMA_BURST8 +#endif + /* Ethernet */ #ifdef CONFIG_FEC_MXC # define CONFIG_FEC_MXC_PHYADDR 0 @@ -140,7 +159,11 @@ /* SPL */ #ifdef CONFIG_SPL -# define CONFIG_SPL_MMC_SUPPORT +# ifdef CONFIG_NAND_MXS +# define CONFIG_SPL_NAND_SUPPORT +# else +# define CONFIG_SPL_MMC_SUPPORT +# endif # include "imx6_spl.h" # ifdef CONFIG_SPL_BUILD -- cgit v1.3.1 From 949cfefbdd54b0db83874347afd6e02348b9372d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:33:00 +0530 Subject: imx6: isiotmx6ul: Add nandboot env support Add config options for booting Linux from NAND in UBI format. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- configs/imx6ul_isiot_nand_defconfig | 1 + include/configs/imx6ul_isiot.h | 32 +++++++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 2af146f405d..d1a9fad5c46 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_PROMPT="isiotmx6ul> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index b1378485fe9..10311d04dd7 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -48,9 +48,12 @@ "mmcdev=0\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ + "ubiargs=setenv bootargs console=${console},${baudrate} " \ + "ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ @@ -75,8 +78,21 @@ "fi; " \ "else " \ "bootm; " \ - "fi\0" + "fi\0" \ + "nandboot=echo Booting from nand ...; " \ + "if mtdparts; then " \ + "echo Starting nand boot ...; " \ + "else " \ + "mtdparts default; " \ + "fi; " \ + "run ubiargs; " \ + "nand read ${loadaddr} kernel 0x800000; " \ + "nand read ${fdt_addr} dtb 0x100000; " \ + "bootm ${loadaddr} - ${fdt_addr}\0" +#ifdef CONFIG_NAND_MXS +# define CONFIG_BOOTCOMMAND "run nandboot" +#else # define CONFIG_BOOTCOMMAND \ "if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -91,6 +107,7 @@ "fi; " \ "fi; " \ "fi" +#endif /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -141,6 +158,19 @@ # define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE # define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 +/* MTD device */ +# define CONFIG_MTD_DEVICE +# define CONFIG_CMD_MTDPARTS +# define CONFIG_MTD_PARTITIONS +# define MTDIDS_DEFAULT "nand0=gpmi-nand" +# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:2m(spl),2m(uboot)," \ + "1m(env),8m(kernel),1m(dtb),-(rootfs)" + +/* UBI */ +# define CONFIG_CMD_UBIFS +# define CONFIG_RBTREE +# define CONFIG_LZO + /* APBH DMA */ # define CONFIG_APBH_DMA # define CONFIG_APBH_DMA_BURST -- cgit v1.3.1 From 7cf22dc8d87285ba4f82f8a0a9d7b0c33c1b9d74 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:45:17 +0530 Subject: i.MX6UL: isiot: Add eMMC boot support Boot from eMMC: -------------- U-Boot SPL 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27) Trying to boot from MMC2 U-Boot 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 36C Reset cause: POR Model: Engicam Is.IoT MX6UL eMMC Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial switch to partitions #0, OK mmc1(part 0) is current device Cc: Matteo Lisi Cc: Michael Trimarchi Reviewed by: Stefano Babic Signed-off-by: Jagan Teki --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ul-isiot-emmc.dts | 77 +++++++++++++++++++++++++++++++++++ board/engicam/isiotmx6ul/MAINTAINERS | 2 + board/engicam/isiotmx6ul/isiotmx6ul.c | 26 +++++++++++- configs/imx6ul_isiot_emmc_defconfig | 39 ++++++++++++++++++ include/configs/imx6ul_isiot.h | 2 +- 6 files changed, 145 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx6ul-isiot-emmc.dts create mode 100644 configs/imx6ul_isiot_emmc_defconfig (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9012f69ceeb..1f0ac36ae25 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -317,6 +317,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6q-icore-rqs.dtb \ imx6sx-sabreauto.dtb \ imx6ul-geam-kit.dtb \ + imx6ul-isiot-emmc.dtb \ imx6ul-isiot-mmc.dtb \ imx6ul-isiot-nand.dtb diff --git a/arch/arm/dts/imx6ul-isiot-emmc.dts b/arch/arm/dts/imx6ul-isiot-emmc.dts new file mode 100644 index 00000000000..677de964732 --- /dev/null +++ b/arch/arm/dts/imx6ul-isiot-emmc.dts @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul-isiot.dtsi" + +/ { + model = "Engicam Is.IoT MX6UL eMMC Starterkit"; + compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + bus-width = <8>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070 + >; + }; +}; diff --git a/board/engicam/isiotmx6ul/MAINTAINERS b/board/engicam/isiotmx6ul/MAINTAINERS index f4dcfbde173..c30cfe7c7d7 100644 --- a/board/engicam/isiotmx6ul/MAINTAINERS +++ b/board/engicam/isiotmx6ul/MAINTAINERS @@ -4,7 +4,9 @@ S: Maintained F: board/engicam/isiotmx6ul F: include/configs/imx6ul_isiot.h F: configs/imx6ul_isiot_mmc_defconfig +F: configs/imx6ul_isiot_emmc_defconfig F: configs/imx6ul_isiot_nand_defconfig F: arch/arm/dts/imx6ul-isiot.dtsi F: arch/arm/dts/imx6ul-isiot-mmc.dts +F: arch/arm/dts/imx6ul-isiot-emmc.dts F: arch/arm/dts/imx6ul-isiot-nand.dts diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index 07dd50186ff..9cde4fc8f23 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -153,10 +153,24 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) -struct fsl_esdhc_cfg usdhc_cfg[1] = { +struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC1_BASE_ADDR, 0, 4}, + {USDHC2_BASE_ADDR, 0, 8}, }; int board_mmc_getcd(struct mmc *mmc) @@ -168,6 +182,9 @@ int board_mmc_getcd(struct mmc *mmc) case USDHC1_BASE_ADDR: ret = !gpio_get_value(USDHC1_CD_GPIO); break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; } return ret; @@ -181,6 +198,7 @@ int board_mmc_init(bd_t *bis) * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) * mmc0 USDHC1 + * mmc1 USDHC2 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { @@ -190,6 +208,12 @@ int board_mmc_init(bd_t *bis) gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; default: printf("Warning - USDHC%d controller not supporting\n", i + 1); diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig new file mode 100644 index 00000000000..94fe80866dc --- /dev/null +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6UL_ISIOT=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="isiotmx6ul> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index 10311d04dd7..1b0e43636ed 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -145,7 +145,7 @@ /* MMC */ #ifdef CONFIG_FSL_USDHC # define CONFIG_SYS_MMC_ENV_DEV 0 -# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_USDHC_NUM 2 # define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif -- cgit v1.3.1 From 2e2a8dc635f5ca3be9d96759a905ede73f1baf33 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:45:18 +0530 Subject: i.MX6UL: isiot: Add modeboot env via board_late_init Add runtime, modeboot env which is setting mmcboot, or nandboot based on the bootdevice so-that conditional macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should be avoided in config files. Cc: Matteo Lisi Cc: Michael Trimarchi Reviewed by: Stefano Babic Signed-off-by: Jagan Teki --- board/engicam/isiotmx6ul/isiotmx6ul.c | 21 ++++++++++++++++++++ configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx6ul_isiot_mmc_defconfig | 1 + configs/imx6ul_isiot_nand_defconfig | 1 + include/configs/imx6ul_isiot.h | 36 ++++++++++++++++------------------- 5 files changed, 40 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index 9cde4fc8f23..0e607e0da07 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -103,6 +103,27 @@ static void setup_gpmi_nand(void) } #endif /* CONFIG_NAND_MXS */ +int board_late_init(void) +{ + switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> + IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + setenv("modeboot", "mmcboot"); + break; + case IMX6_BMODE_NAND: + setenv("modeboot", "nandboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + int board_init(void) { /* Address of boot parameters */ diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 94fe80866dc..4c3664f320f 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -37,3 +37,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_BOARD_LATE_INIT=y diff --git a/configs/imx6ul_isiot_mmc_defconfig b/configs/imx6ul_isiot_mmc_defconfig index 8ecdd8e5691..ea2d378dff8 100644 --- a/configs/imx6ul_isiot_mmc_defconfig +++ b/configs/imx6ul_isiot_mmc_defconfig @@ -39,3 +39,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_BOARD_LATE_INIT=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 6f1a05471f9..f02a2ac242b 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -40,3 +40,4 @@ CONFIG_PINCTRL_IMX6=y CONFIG_SYS_I2C_MXC=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_BOARD_LATE_INIT=y diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index 1b0e43636ed..7258fed79b7 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -64,8 +64,7 @@ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ + "_mmcboot=run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ "bootm ${loadaddr} - ${fdt_addr}; " \ @@ -79,6 +78,20 @@ "else " \ "bootm; " \ "fi\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run _mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi\0" \ "nandboot=echo Booting from nand ...; " \ "if mtdparts; then " \ "echo Starting nand boot ...; " \ @@ -90,24 +103,7 @@ "nand read ${fdt_addr} dtb 0x100000; " \ "bootm ${loadaddr} - ${fdt_addr}\0" -#ifdef CONFIG_NAND_MXS -# define CONFIG_BOOTCOMMAND "run nandboot" -#else -# define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadfit; then " \ - "run fitboot; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi" -#endif +#define CONFIG_BOOTCOMMAND "run $modeboot" /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 -- cgit v1.3.1 From 0dd259a1b13554947d813ed315dc860cee67fb8e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:45:19 +0530 Subject: i.MX6UL: isiot: Add mmc_late_init Let the runtime code can set the mmcdev and mmcroot based on the devno using mmc_get_env_dev instead of defining separately in build-time configs using mmc_late_init func. Cc: Matteo Lisi Cc: Michael Trimarchi Reviewed by: Stefano Babic Signed-off-by: Jagan Teki --- board/engicam/isiotmx6ul/isiotmx6ul.c | 22 ++++++++++++++++++++++ include/configs/imx6ul_isiot.h | 2 -- 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index 0e607e0da07..b96e4ce8967 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -7,6 +7,7 @@ */ #include +#include #include #include @@ -103,6 +104,24 @@ static void setup_gpmi_nand(void) } #endif /* CONFIG_NAND_MXS */ +#ifdef CONFIG_ENV_IS_IN_MMC +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + int board_late_init(void) { switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> @@ -111,6 +130,9 @@ int board_late_init(void) case IMX6_BMODE_ESD: case IMX6_BMODE_MMC: case IMX6_BMODE_EMMC: +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif setenv("modeboot", "mmcboot"); break; case IMX6_BMODE_NAND: diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index 7258fed79b7..4009648628f 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -45,9 +45,7 @@ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x87800000\0" \ "boot_fdt=try\0" \ - "mmcdev=0\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ -- cgit v1.3.1 From ffa11c33811b610a6ad2b029debc1159a52805de Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:45:23 +0530 Subject: imx6: icorem6_rqs: Add eMMC boot support Boot from eMMC: -------------- U-Boot SPL 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21) Trying to boot from MMC2 U-Boot 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21 +0100) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial switch to partitions #0, OK mmc1(part 0) is current device Net: No ethernet found. Hit any key to stop autoboot: 0 Booting from mmc ... switch to partitions #0, OK mmc1(part 0) is current device Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/icorem6_rqs/icorem6_rqs.c | 24 ++++++++++++++++++++++-- include/configs/imx6qdl_icore_rqs.h | 2 +- 2 files changed, 23 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index e3c520fedf3..175bda58605 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -77,8 +77,22 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; -struct fsl_esdhc_cfg usdhc_cfg[1] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1, 4}, + {USDHC4_BASE_ADDR, 1, 8}, }; int board_mmc_getcd(struct mmc *mmc) @@ -88,6 +102,7 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC3_BASE_ADDR: + case USDHC4_BASE_ADDR: ret = 1; break; } @@ -102,7 +117,8 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) - * mmc0 USDHC3 + * mmc0 USDHC3 + * mmc1 USDHC4 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { @@ -110,6 +126,10 @@ int board_mmc_init(bd_t *bis) SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; default: printf("Warning - USDHC%d controller not supporting\n", i + 1); diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h index 6f7195d9016..cd94c5fa9cc 100644 --- a/include/configs/imx6qdl_icore_rqs.h +++ b/include/configs/imx6qdl_icore_rqs.h @@ -124,7 +124,7 @@ /* MMC */ #ifdef CONFIG_FSL_USDHC # define CONFIG_SYS_MMC_ENV_DEV 0 -# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_USDHC_NUM 2 # define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif -- cgit v1.3.1 From 8c998a85a3df9cabf9701835b82ccbbfcdf9ee36 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:45:24 +0530 Subject: i.MX6Q: icorem6_rqs: Add modeboot env via board_late_init Add runtime, modeboot env which is setting mmcboot based on the bootdevice so-that conditional macros for MMC via CONFIG_BOOTCOMMAND should be avoided in config files. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/icorem6_rqs/icorem6_rqs.c | 18 ++++++++++++++++++ configs/imx6dl_icore_rqs_mmc_defconfig | 1 + configs/imx6q_icore_rqs_mmc_defconfig | 1 + include/configs/imx6qdl_icore_rqs.h | 32 ++++++++++++++++---------------- 4 files changed, 36 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index 175bda58605..cc7f897f632 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -45,6 +45,24 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> + IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + setenv("modeboot", "mmcboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + int dram_init(void) { gd->ram_size = imx_ddr_size(); diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig index 64fa2ec7cd3..f521292bbf8 100644 --- a/configs/imx6dl_icore_rqs_mmc_defconfig +++ b/configs/imx6dl_icore_rqs_mmc_defconfig @@ -38,3 +38,4 @@ CONFIG_FEC_MXC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y +CONFIG_BOARD_LATE_INIT=y diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig index 6bbdfa8981f..6bd3387b8ec 100644 --- a/configs/imx6q_icore_rqs_mmc_defconfig +++ b/configs/imx6q_icore_rqs_mmc_defconfig @@ -38,3 +38,4 @@ CONFIG_FEC_MXC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y +CONFIG_BOARD_LATE_INIT=y diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h index cd94c5fa9cc..c62c1d421e7 100644 --- a/include/configs/imx6qdl_icore_rqs.h +++ b/include/configs/imx6qdl_icore_rqs.h @@ -56,8 +56,7 @@ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ + "_mmcboot=run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ "bootm ${loadaddr} - ${fdt_addr}; " \ @@ -70,23 +69,24 @@ "fi; " \ "else " \ "bootm; " \ - "fi\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadfit; then " \ - "run fitboot; " \ + "fi\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run _mmcboot; " \ + "fi; " \ "fi; " \ "fi; " \ - "fi; " \ - "fi" + "fi\0" + +#define CONFIG_BOOTCOMMAND "run $modeboot" /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 -- cgit v1.3.1 From d98fd1323c7e4ad687bfdc002a8a7e7d9e8ab144 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 24 Feb 2017 15:45:25 +0530 Subject: i.MX6Q: icorem6_rqs: Add mmc_late_init Let the runtime code can set the mmcdev and mmcroot based on the devno using mmc_get_env_dev instead of defining separately in build-time configs using mmc_late_init func. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/icorem6_rqs/icorem6_rqs.c | 22 ++++++++++++++++++++++ include/configs/imx6qdl_icore_rqs.h | 2 -- 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index cc7f897f632..04fb0c2028b 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -7,6 +7,7 @@ */ #include +#include #include #include @@ -45,6 +46,24 @@ int board_init(void) return 0; } +#ifdef CONFIG_ENV_IS_IN_MMC +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + int board_late_init(void) { switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> @@ -53,6 +72,9 @@ int board_late_init(void) case IMX6_BMODE_ESD: case IMX6_BMODE_MMC: case IMX6_BMODE_EMMC: +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif setenv("modeboot", "mmcboot"); break; default: diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h index c62c1d421e7..3358320e66f 100644 --- a/include/configs/imx6qdl_icore_rqs.h +++ b/include/configs/imx6qdl_icore_rqs.h @@ -40,9 +40,7 @@ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ - "mmcdev=0\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ -- cgit v1.3.1 From d4b349e41ba3f7ade9cde6b9fd96a735c29bfcca Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 28 Feb 2017 16:37:32 +0100 Subject: arm: imx6: tqma6: use CONFIG_TQM6x for SOM specific settings We have a Kconfig name for the module types. Let's Use it. Some feature selections and configurations are based on the module. Module selection selects the CPU type. Signed-off-by: Markus Niebel --- board/tqc/tqma6/tqma6_mba6.c | 13 +++++++------ include/configs/tqma6.h | 8 ++++---- 2 files changed, 11 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index 1c5b95304b5..0be7845cc38 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -54,19 +54,19 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#if defined(CONFIG_MX6Q) +#if defined(CONFIG_TQMA6Q) #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac -#elif defined(CONFIG_MX6S) +#elif defined(CONFIG_TQMA6S) #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 #else -#error "need to define target CPU" +#error "need to select module" #endif @@ -243,14 +243,15 @@ int board_phy_config(struct phy_device *phydev) { /* * optimized pad skew values depends on CPU variant on the TQMa6x module: - * i.MX6Q/D or i.MX6DL/S + * CONFIG_TQMA6Q: i.MX6Q/D + * CONFIG_TQMA6S: i.MX6S */ -#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#if defined(CONFIG_TQMA6Q) #define MBA6X_KSZ9031_CTRL_SKEW 0x0032 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff #define MBA6X_KSZ9031_RX_SKEW 0x3333 #define MBA6X_KSZ9031_TX_SKEW 0x2036 -#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#elif defined(CONFIG_TQMA6S) #define MBA6X_KSZ9031_CTRL_SKEW 0x0030 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff #define MBA6X_KSZ9031_RX_SKEW 0x3333 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 1c0a762d694..2a63686f5dc 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -18,17 +18,17 @@ /* #endif */ /* place code in last 4 MiB of RAM */ -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#if defined(CONFIG_TQMA6S) #define CONFIG_SYS_TEXT_BASE 0x2fc00000 -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#elif defined(CONFIG_TQMA6Q) #define CONFIG_SYS_TEXT_BASE 0x4fc00000 #endif #include "mx6_common.h" -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#if defined(CONFIG_TQMA6S) #define PHYS_SDRAM_SIZE (512u * SZ_1M) -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#elif defined(CONFIG_TQMA6Q) #define PHYS_SDRAM_SIZE (1024u * SZ_1M) #endif -- cgit v1.3.1 From 468fb1e4dfa805a86ff46b3875d9f6a08b34dbf8 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 28 Feb 2017 16:37:33 +0100 Subject: arm: imx6: tqma6: add support for TQMa6DL variant This adds support for TQMa6DL using i.MX6DL and 1GiB DRAM Since The module will use the same devicetree, we patch the ram size in ft_board_setup. Signed-off-by: Markus Niebel --- board/tqc/tqma6/Kconfig | 7 +++ board/tqc/tqma6/README | 3 + board/tqc/tqma6/tqma6.c | 7 +++ board/tqc/tqma6/tqma6_mba6.c | 5 +- board/tqc/tqma6/tqma6dl.cfg | 125 +++++++++++++++++++++++++++++++++++++ configs/tqma6dl_mba6_mmc_defconfig | 34 ++++++++++ configs/tqma6dl_mba6_spi_defconfig | 35 +++++++++++ include/configs/tqma6.h | 10 +-- include/configs/tqma6_mba6.h | 5 +- 9 files changed, 223 insertions(+), 8 deletions(-) create mode 100644 board/tqc/tqma6/tqma6dl.cfg create mode 100644 configs/tqma6dl_mba6_mmc_defconfig create mode 100644 configs/tqma6dl_mba6_spi_defconfig (limited to 'include') diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig index 5dafa3822a9..6df41342865 100644 --- a/board/tqc/tqma6/Kconfig +++ b/board/tqc/tqma6/Kconfig @@ -22,6 +22,12 @@ config TQMA6Q help select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM +config TQMA6DL + bool "TQMa6DL" + select MX6DL + help + select TQMa6DL with i.MX6DL and 1GiB DRAM + config TQMA6S bool "TQMa6S" select MX6S @@ -70,6 +76,7 @@ endchoice config IMX_CONFIG default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q + default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S endif diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README index 2c012e7b75f..c47cb21eebb 100644 --- a/board/tqc/tqma6/README +++ b/board/tqc/tqma6/README @@ -21,6 +21,7 @@ To build U-Boot for the TQ Systems TQMa6 modules: x is a placeholder for the CPU variant q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +dl - means i.MX6DL: TQMa6DL (i.MX6DL) s - means i.MX6S: TQMa6S (i.MX6S) baseboard is a placeholder for the boot device @@ -31,5 +32,7 @@ This gives the following configurations: tqma6q_mba6_mmc_config tqma6q_mba6_spi_config +tqma6dl_mba6_mmc_config +tqma6dl_mba6_spi_config tqma6s_mba6_mmc_config tqma6s_mba6_spi_config diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 49917c1d64b..fdb0fa11b00 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -269,8 +269,15 @@ int checkboard(void) * Device Tree Support */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#define MODELSTRLEN 32u int ft_board_setup(void *blob, bd_t *bd) { + char modelstr[MODELSTRLEN]; + + snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + do_fixup_by_path_string(blob, "/", "model", modelstr); + fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); /* bring in eMMC dsr settings */ do_fixup_by_path_u32(blob, "/soc/aips-bus@02100000/usdhc@02198000", diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index 0be7845cc38..43349ade1d4 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR; #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac -#elif defined(CONFIG_TQMA6S) +#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 @@ -245,13 +245,14 @@ int board_phy_config(struct phy_device *phydev) * optimized pad skew values depends on CPU variant on the TQMa6x module: * CONFIG_TQMA6Q: i.MX6Q/D * CONFIG_TQMA6S: i.MX6S + * CONFIG_TQMA6DL: i.MX6DL */ #if defined(CONFIG_TQMA6Q) #define MBA6X_KSZ9031_CTRL_SKEW 0x0032 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff #define MBA6X_KSZ9031_RX_SKEW 0x3333 #define MBA6X_KSZ9031_TX_SKEW 0x2036 -#elif defined(CONFIG_TQMA6S) +#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) #define MBA6X_KSZ9031_CTRL_SKEW 0x0030 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff #define MBA6X_KSZ9031_RX_SKEW 0x3333 diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg new file mode 100644 index 00000000000..716033f3fb2 --- /dev/null +++ b/board/tqc/tqma6/tqma6dl.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014 - 2015 Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6DL DDR config Rev. 0100E */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig new file mode 100644 index 00000000000..6e4e6f7c443 --- /dev/null +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TQMA6=y +CONFIG_TQMA6DL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig new file mode 100644 index 00000000000..9cd54811e14 --- /dev/null +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TQMA6=y +CONFIG_TQMA6DL=y +CONFIG_TQMA6X_SPI_BOOT=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2a63686f5dc..e72332cd1ba 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -1,7 +1,7 @@ /* - * Copyright (C) 2013, 2014 Markus Niebel + * Copyright (C) 2013, 2014, 2017 Markus Niebel * - * Configuration settings for the TQ Systems TQMa6 module. + * Configuration settings for the TQ Systems TQMa6 module. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,7 +20,7 @@ /* place code in last 4 MiB of RAM */ #if defined(CONFIG_TQMA6S) #define CONFIG_SYS_TEXT_BASE 0x2fc00000 -#elif defined(CONFIG_TQMA6Q) +#elif defined(CONFIG_TQMA6Q) || defined(CONFIG_TQMA6DL) #define CONFIG_SYS_TEXT_BASE 0x4fc00000 #endif @@ -28,8 +28,10 @@ #if defined(CONFIG_TQMA6S) #define PHYS_SDRAM_SIZE (512u * SZ_1M) +#elif defined(CONFIG_TQMA6DL) +#define PHYS_SDRAM_SIZE (SZ_1G) #elif defined(CONFIG_TQMA6Q) -#define PHYS_SDRAM_SIZE (1024u * SZ_1M) +#define PHYS_SDRAM_SIZE (SZ_1G) #endif #define CONFIG_MXC_UART diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 265aa4a7c01..3d6e4383e1e 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -1,7 +1,8 @@ /* - * Copyright (C) 2013 - 2015 Markus Niebel + * Copyright (C) 2013 - 2017 Markus Niebel * - * Configuration settings for the TQ Systems TQMa6 module. + * Configuration settings for the TQ Systems TQMa6 module on + * MBa6 starter kit * * SPDX-License-Identifier: GPL-2.0+ */ -- cgit v1.3.1 From cb11a28aad37e6e348d72057003c2c93180ce5f7 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 21 Feb 2017 22:45:20 +0100 Subject: MCCMON6: defconfig: Move 'quiet' console parameter to 'console' env variable Signed-off-by: Lukasz Majewski --- include/configs/mccmon6.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 8f1eddfd624..7bda977c972 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -118,7 +118,7 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ + "console=ttymxc0,115200 quiet\0" \ "fdtfile=imx6q-mccmon6.dtb\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -148,7 +148,7 @@ "boot_nor=" \ "setenv kernelnor 0x08180000;" \ "setenv dtbnor 0x09980000;" \ - "setenv bootargs console=${console} quiet " \ + "setenv bootargs console=${console} " \ ""MTDPARTS_DEFAULT" " \ "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ -- cgit v1.3.1 From 77f29293f1413f634bf52c29da643404e3ab92a6 Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Tue, 7 Mar 2017 14:33:25 +0100 Subject: arm: i.MX6UL: add Armadeus Systems OPOS6UL SoM and OPOS6ULDev carrier board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet phy. OPOS6ULDev is carrier board for the OPOS6UL. U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09) Trying to boot from MMC1 U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100) CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 40C Reset cause: POR Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Video: 800x480x18 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Sébastien Szymanski Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/mx6/Kconfig | 15 ++ arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/opos6ul.c | 302 +++++++++++++++++++++++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-opos6ul.dtsi | 192 +++++++++++++++ arch/arm/dts/imx6ul-opos6uldev.dts | 412 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/opos6ul.h | 16 ++ board/armadeus/opos6uldev/Kconfig | 15 ++ board/armadeus/opos6uldev/MAINTAINERS | 6 + board/armadeus/opos6uldev/Makefile | 6 + board/armadeus/opos6uldev/board.c | 125 ++++++++++ configs/opos6uldev_defconfig | 85 +++++++ include/configs/opos6uldev.h | 219 +++++++++++++++++ 13 files changed, 1396 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/mx6/opos6ul.c create mode 100644 arch/arm/dts/imx6ul-opos6ul.dtsi create mode 100644 arch/arm/dts/imx6ul-opos6uldev.dts create mode 100644 arch/arm/include/asm/arch-mx6/opos6ul.h create mode 100644 board/armadeus/opos6uldev/Kconfig create mode 100644 board/armadeus/opos6uldev/MAINTAINERS create mode 100644 board/armadeus/opos6uldev/Makefile create mode 100644 board/armadeus/opos6uldev/board.c create mode 100644 configs/opos6uldev_defconfig create mode 100644 include/configs/opos6uldev.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 0bceaac9b05..190e5c6ec78 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -46,6 +46,16 @@ config MX6UL_LITESOM select DM_THERMAL select SUPPORT_SPL +config MX6UL_OPOS6UL + bool + select MX6UL + select BOARD_LATE_INIT + select DM + select DM_GPIO + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config MX6ULL bool select MX6UL @@ -263,6 +273,10 @@ config TARGET_MX6ULL_14X14_EVK config TARGET_NITROGEN6X bool "nitrogen6x" +config TARGET_OPOS6ULDEV + bool "Armadeus OPOS6ULDev board" + select MX6UL_OPOS6UL + config TARGET_OT1200 bool "Bachmann OT1200" select SUPPORT_SPL @@ -361,6 +375,7 @@ config SYS_SOC source "board/ge/bx50v3/Kconfig" source "board/advantech/dms-ba16/Kconfig" source "board/aristainetos/Kconfig" +source "board/armadeus/opos6uldev/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index 024f7031ad6..c183eb4a2fb 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -11,3 +11,4 @@ obj-y := soc.o clock.o obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o +obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o diff --git a/arch/arm/cpu/armv7/mx6/opos6ul.c b/arch/arm/cpu/armv7/mx6/opos6ul.c new file mode 100644 index 00000000000..ea2f0ec2513 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/opos6ul.c @@ -0,0 +1,302 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FEC_MXC +#include + +#define MDIO_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm \ +) + +#define ENET_PAD_CTRL_PU ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm \ +) + +#define ENET_PAD_CTRL_PD ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm \ +) + +#define ENET_CLK_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ +) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + /* PHY Int */ + MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + /* PHY Reset */ + MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct gpio_desc rst; + int ret; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + ret = dm_gpio_lookup_name("GPIO4_2", &rst); + if (ret) { + printf("Cannot get GPIO4_2\n"); + return ret; + } + + ret = dm_gpio_request(&rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_2\n"); + return ret; + } + + dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT); + dm_gpio_set_value(&rst, 0); + udelay(1000); + dm_gpio_set_value(&rst, 1); + + return fecmxc_initialize(bis); +} +#endif /* CONFIG_FEC_MXC */ + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int __weak opos6ul_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr2); + + /* In bootstrap don't use the env vars */ + if (((reg & 0x3000000) >> 24) == 0x1) { + set_default_env(NULL); + setenv("preboot", ""); + } + + return opos6ul_board_late_init(); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + return cfg->esdhc_base == USDHC1_BASE_ADDR; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include +#include + +#define USDHC_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \ +) + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 8}, +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1500, + .trcmin = 5250, + .trasmin = 3750, +}; + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + int reg = readl(&fuse->gp1); + + /* 512MB of RAM */ + if (reg & 0x1) { + mem_ddr.density = 4; + mem_ddr.rowaddr = 15; + mem_ddr.trcd = 1375; + mem_ddr.trcmin = 4875; + mem_ddr.trasmin = 3500; + } + + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + opos6ul_setup_uart_debug(); + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1f0ac36ae25..372e05ecffa 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -319,7 +319,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6ul-geam-kit.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-mmc.dtb \ - imx6ul-isiot-nand.dtb + imx6ul-isiot-nand.dtb \ + imx6ul-opos6uldev.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb diff --git a/arch/arm/dts/imx6ul-opos6ul.dtsi b/arch/arm/dts/imx6ul-opos6ul.dtsi new file mode 100644 index 00000000000..51095df33a9 --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6ul.dtsi @@ -0,0 +1,192 @@ +/* + * Copyright 2017 Armadeus Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" + +/ { + memory { + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-reset-duration = <1>; + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; + }; +}; + +/* Bluetooth */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + uart-has-rtscts; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + /* INT# */ + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 + /* RST# */ + MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 + /* BT_REG_ON */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 + /* WL_REG_ON */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 + /* WL_IRQ */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts b/arch/arm/dts/imx6ul-opos6uldev.dts new file mode 100644 index 00000000000..0e59ee57fd5 --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6uldev.dts @@ -0,0 +1,412 @@ +/* + * Copyright 2017 Armadeus Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul-opos6ul.dtsi" + +/ { + model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board"; + compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 191000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_5v>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user-button { + label = "User button"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + user-led { + label = "User"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + onewire { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_w1>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg1_vbus: regulator-usbotg1vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg1vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg2_vbus: regulator-usbotg2vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg2vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <®_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <5000000>; + }; + + spidev1: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock_frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock_frequency = <400000>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + lcd-supply = <®_3v3>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + timing0: timing0 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xffff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + vbus-supply = <®_usbotg1_vbus>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbotg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0 + MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0 + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0 + MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0 + MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_w1: w1grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h new file mode 100644 index 00000000000..b5363850d23 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/opos6ul.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__ +#define __ARCH_ARM_MX6UL_OPOS6UL_H__ + +int opos6ul_board_late_init(void); + +#ifdef CONFIG_SPL_BUILD +void opos6ul_setup_uart_debug(void); +#endif + +#endif diff --git a/board/armadeus/opos6uldev/Kconfig b/board/armadeus/opos6uldev/Kconfig new file mode 100644 index 00000000000..beca37dfb38 --- /dev/null +++ b/board/armadeus/opos6uldev/Kconfig @@ -0,0 +1,15 @@ +if TARGET_OPOS6ULDEV + +config SYS_BOARD + default "opos6uldev" + +config SYS_VENDOR + default "armadeus" + +config SYS_CONFIG_NAME + default "opos6uldev" + +config IMX_CONFIG + default "arch/arm/imx-common/spl_sd.cfg" + +endif diff --git a/board/armadeus/opos6uldev/MAINTAINERS b/board/armadeus/opos6uldev/MAINTAINERS new file mode 100644 index 00000000000..e46c66942d5 --- /dev/null +++ b/board/armadeus/opos6uldev/MAINTAINERS @@ -0,0 +1,6 @@ +OPOS6ULDev BOARD +M: Sébastien Szymanski +S: Maintained +F: board/armadeus/opos6uldev/ +F: include/configs/opos6uldev.h +F: configs/opos6uldev_defconfig diff --git a/board/armadeus/opos6uldev/Makefile b/board/armadeus/opos6uldev/Makefile new file mode 100644 index 00000000000..fd14fd75a6d --- /dev/null +++ b/board/armadeus/opos6uldev/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2017 Armadeus Systems +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c new file mode 100644 index 00000000000..500d0bd2dfd --- /dev/null +++ b/board/armadeus/opos6uldev/board.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_VIDEO_MXS +#define LCD_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \ +) + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +int setup_lcd(void) +{ + struct gpio_desc backlight; + int ret; + + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Set Brightness to high */ + ret = dm_gpio_lookup_name("GPIO4_10", &backlight); + if (ret) { + printf("Cannot get GPIO4_10\n"); + return ret; + } + + ret = dm_gpio_request(&backlight, "backlight"); + if (ret) { + printf("Cannot request GPIO4_10\n"); + return ret; + } + + dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT); + dm_gpio_set_value(&backlight, 1); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int opos6ul_board_late_init(void) +{ +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define UART_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ +) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void opos6ul_setup_uart_debug(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig new file mode 100644 index 00000000000..5c3a3f6e5d0 --- /dev/null +++ b/configs/opos6uldev_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_OPOS6ULDEV=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev" +CONFIG_BOOTDELAY=5 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="BIOS> " +CONFIG_CMD_CONFIG=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_BLK is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_PWRSEQ=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Armadeus Systems" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h new file mode 100644 index 00000000000..e5ab06777aa --- /dev/null +++ b/include/configs/opos6uldev.h @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * Configuration settings for the OPOS6ULDev board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OPOS6ULDEV_CONFIG_H +#define __OPOS6ULDEV_CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_GPIO +#undef CONFIG_DM_MMC + +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 << 20) + +/* Miscellaneous configurable options */ +#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB */ +#ifdef CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_MII +#endif + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_SPLASH_SOURCE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif + +/* Environment is stored in the eMMC boot partition */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_ENV_SIZE (10 * 1024) +#define CONFIG_ENV_OFFSET (1024 * 1024) /* 1 MB */ +#define CONFIG_ENV_OFFSET_REDUND (1536 * 1024) /* 512KB from CONFIG_ENV_OFFSET */ + +#define CONFIG_ENV_VERSION 100 +#define CONFIG_BOARD_NAME opos6ul +#define ACFG_CONSOLE_DEV ttymxc0 +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" +#define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," __stringify(CONFIG_BAUDRATE) +#define CONFIG_PREBOOT "run check_env" +#define CONFIG_BOOTCOMMAND "run emmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ + "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ + "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ + "fdt_addr=0x88000000\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_name=" __stringify(CONFIG_BOARD_NAME) "dev\0" \ + "initrd_high=0xffffffff\0" \ + "ip_dyn=yes\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ + "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ + "check_env=if test -n ${flash_env_version}; " \ + "then env default env_version; " \ + "else env set flash_env_version ${env_version}; env save; " \ + "fi; " \ + "if itest ${flash_env_version} != ${env_version}; then " \ + "echo \"*** Warning - Environment version" \ + " change suggests: run flash_reset_env; reset\"; " \ + "env default flash_reset_env; " \ + "else exit; fi; \0" \ + "flash_reset_env=env default -f -a && saveenv && " \ + "echo Environment variables erased!\0" \ + "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ + "flash_uboot_spl=" \ + "if mmc dev 0 1; then " \ + "setexpr sz ${filesize} / 0x200; " \ + "setexpr sz ${sz} + 1; " \ + "if mmc write ${loadaddr} 0x2 ${sz}; then " \ + "echo Flashing of U-boot SPL succeed; " \ + "else echo Flashing of U-boot SPL failed; " \ + "fi; " \ + "fi;\0" \ + "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ + "flash_uboot_img=" \ + "if mmc dev 0 1; then " \ + "setexpr sz ${filesize} / 0x200; " \ + "setexpr sz ${sz} + 1; " \ + "if mmc write ${loadaddr} 0x8a ${sz}; then " \ + "echo Flashing of U-boot image succeed; " \ + "else echo Flashing of U-boot image failed; " \ + "fi; " \ + "fi;\0" \ + "update_uboot=run download_uboot_spl flash_uboot_spl " \ + "download_uboot_img flash_uboot_img\0" \ + "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ + "flash_kernel=" \ + "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ + "echo kernel update succeed; " \ + "else echo kernel update failed; " \ + "fi;\0" \ + "update_kernel=run download_kernel flash_kernel\0" \ + "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ + "flash_dtb=" \ + "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ + "echo dtb update succeed; " \ + "else echo dtb update in failed; " \ + "fi;\0" \ + "update_dtb=run download_dtb flash_dtb\0" \ + "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ + "flash_rootfs=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ + "echo Flashing of rootfs image succeed; " \ + "else echo Flashing of rootfs image failed; " \ + "fi; " \ + "fi;\0" \ + "update_rootfs=run download_rootfs flash_rootfs\0" \ + "flash_failsafe=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ + "echo Flashing of rootfs image in failsafe partition succeed; " \ + "else echo Flashing of rootfs image in failsafe partition failed; " \ + "fi; " \ + "fi;\0" \ + "update_failsafe=run download_rootfs flash_failsafe\0" \ + "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ + "flash_userdata=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ + "echo Flashing of user_data image succeed; " \ + "else echo Flashing of user_data image failed; " \ + "fi; " \ + "fi;\0" \ + "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ + "erase_userdata=" \ + "if mmc dev 0 0; then " \ + "echo Erasing eMMC User Data partition, no way out...; " \ + "mw ${loadaddr} 0 0x200000; " \ + "mmc write ${loadaddr} 0 0x1000; " \ + "mmc write ${loadaddr} 0x800 0x1000; " \ + "mmc write ${loadaddr} 0x40800 0x1000; " \ + "mmc write ${loadaddr} 0x440800 0x1000; " \ + "fi;" \ + "mmc rescan\0" \ + "update_all=run update_rootfs update_uboot\0" \ + "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ + "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "emmcboot=run initargs; run addmmcargs; " \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ + "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ + "bootz ${loadaddr} - ${fdt_addr};\0" \ + "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ + "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "nfsboot=run initargs; run addnfsargs addipargs; " \ + "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ + "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ + "bootz ${loadaddr} - ${fdt_addr};\0" + +#endif /* __OPOS6ULDEV_CONFIG_H */ -- cgit v1.3.1 From 9af131e3550bdc18b823c093b6a32346a7909569 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 9 Mar 2017 17:17:51 -0800 Subject: colibri_imx7/colibri_imx6/apalis_imx6: limit bootm memory Limit memory used for relocation of FDT or initrd. This is required to make sure that relocated artifacts are within lowmem. If fdt_high or initrd_high are not set, U-Boot automatically relocates artifacts to the end of memory. But this area won't be part of lowmem and hence will not be accessible by the kernel during early boot. With VM split set to 2G/2G (i.MX default), only the 2GB Apalis iMX6 is affected by that issue. With VM split set to 3G/1G (ARM default) also modules with 1GB of memory are affected. With the latter the amount of lowmem will be 760MiB. The value must also not exceed available memory! Use a safe value of 512MiB for Apalis and 256MiB for Colibri. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- include/configs/apalis_imx6.h | 1 + include/configs/colibri_imx6.h | 1 + include/configs/colibri_imx7.h | 1 + 3 files changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 9c899e40b0b..c5db7f2b6b8 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -197,6 +197,7 @@ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x20000000\0" \ "fdt_addr_r=0x12000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 2fbadf25225..924b40fea5c 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -172,6 +172,7 @@ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ "fdt_addr_r=0x12000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 3da4211e9be..80eeae46c2d 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -61,6 +61,7 @@ #define CONFIG_SERVERIP 192.168.10.1 #define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ -- cgit v1.3.1 From 640957042d8f878d093f37aadc04f6d08a7252a1 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 9 Mar 2017 17:17:54 -0800 Subject: colibri_imx7: use device-tree for MTD partitions Use device-tree fixup to communicate the MTD partitions to the kernel. Remove mtdparts from the kernel command line. Signed-off-by: Stefan Agner --- board/toradex/colibri_imx7/colibri_imx7.c | 13 +++++++++++++ configs/colibri_imx7_defconfig | 1 + include/configs/colibri_imx7.h | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index a106b3bed3f..b2b12e45199 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -16,10 +16,13 @@ #include #include #include +#include #include +#include #include #include #include +#include #include #include #include @@ -421,6 +424,16 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) + static struct node_info nodes[] = { + { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return ft_common_board_setup(blob, bd); } #endif diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 2d75b276138..ce600565962 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -55,3 +55,4 @@ CONFIG_G_DNL_MANUFACTURER="Toradex" CONFIG_G_DNL_VENDOR_NUM=0x1b67 CONFIG_G_DNL_PRODUCT_NUM=0x4000 CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 80eeae46c2d..4de866836d1 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -120,7 +120,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "setup=setenv setupargs " \ "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} consoleblank=0 ${mtdparts}\0" \ + ",${baudrate}n8 ${memargs} consoleblank=0\0" \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb && " \ "fatload ${interface} 0:1 ${loadaddr} " \ -- cgit v1.3.1 From 38045f54478f8272aa21079fc75cc647ab0b9179 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 9 Mar 2017 17:17:55 -0800 Subject: colibri_imx7: split and resize firmware MTD partition Use two separate partitions for the two firmware instances. Also resize them to be of the same size which also makes the start of the UBI partition nicely aligned to 0x400000. In order to detect the new MTD layout and whether we run a U-Boot with the new BCB format or not, introduce a variable called "updlevel" which we can use in update/upgrade scripts. Signed-off-by: Stefan Agner Acked-by: Max Krummenacher --- include/configs/colibri_imx7.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 4de866836d1..a0b18d22690 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -127,6 +127,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "splashpos=m,m\0" \ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "updlevel=2\0" /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP @@ -161,8 +162,8 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ #define CONFIG_ENV_OFFSET (8 * SZ_64K) #elif defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) #define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #endif @@ -189,7 +190,8 @@ #define MTDIDS_DEFAULT "nand0=gpmi-nand" #define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:" \ "512k(mx7-bcb)," \ - "3584k(u-boot)ro," \ + "1536k(u-boot1)ro," \ + "1536k(u-boot2)ro," \ "512k(u-boot-env)," \ "-(ubi)" -- cgit v1.3.1 From f7d9fcd15634216392130cbd84757b0e706a171a Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 13 Mar 2017 08:51:02 -0700 Subject: imx: ventana: config: add gzwrite support Signed-off-by: Tim Harvey Reviewed-by: Stefano Babic --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 24e31506207..31b3010b764 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -143,6 +143,7 @@ #define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ #define CONFIG_CMD_GSC #define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ +#define CONFIG_CMD_UNZIP /* gzwrite */ #define CONFIG_RBTREE /* Ethernet support */ -- cgit v1.3.1 From 79942c4ffc51ba036886848b0b0a23fcba503930 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 13 Mar 2017 08:51:04 -0700 Subject: imx: ventana: use mmc_root in boot scripts Signed-off-by: Tim Harvey Reviewed-by: Stefano Babic --- include/configs/gw_ventana.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 31b3010b764..d51bcc9e24e 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -296,14 +296,14 @@ "fi\0" \ \ "uimage=uImage\0" \ - "mmc_root=/dev/mmcblk0p1 rootfstype=${fs} rootwait rw\0" \ + "mmc_root=mmcblk0p1\0" \ "mmc_boot=" \ "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ "mmc dev ${disk} && mmc rescan && " \ "setenv dtype mmc; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mmcblk0p1 rootfstype=${fs} " \ + "root=/dev/${mmc_root} rootfstype=${fs} " \ "rootwait rw ${video} ${extra}; " \ "if run loadfdt; then " \ "bootm ${loadaddr} - ${fdt_addr}; " \ -- cgit v1.3.1 From 7966b43778f2556ecbda2275f1296934071224b2 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 13 Mar 2017 18:41:36 -0700 Subject: ARM: vf610: move to standard arch/board approach Move Freescale/NXP Vybrid to a standard arch/board approach, similar to what has been done to i.MX 6 earlier in commit 89ebc82137be ("ARM: mx6: move to a standard arch/board approach"). Signed-off-by: Stefan Agner --- arch/arm/Kconfig | 29 ++++------------------------- arch/arm/cpu/armv7/vf610/Kconfig | 36 ++++++++++++++++++++++++++++++++++++ board/freescale/vf610twr/Kconfig | 3 --- board/phytec/pcm052/Kconfig | 6 ------ board/toradex/colibri_vf/Kconfig | 6 ------ configs/bk4r1_defconfig | 1 + configs/colibri_vf_defconfig | 1 + configs/pcm052_defconfig | 1 + configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig | 1 + include/configs/colibri_vf.h | 1 - include/configs/pcm052.h | 2 -- include/configs/vf610twr.h | 2 -- 13 files changed, 45 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/vf610/Kconfig (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e8cdefa5f54..b1f78520d09 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -786,31 +786,11 @@ config TARGET_TS4800 select CPU_V7 select SYS_FSL_ERRATUM_ESDHC_A001 -config TARGET_VF610TWR - bool "Support vf610twr" +config ARCH_VF610 + bool "Freescale Vybrid" select CPU_V7 select SYS_FSL_ERRATUM_ESDHC111 -config TARGET_COLIBRI_VF - bool "Support Colibri VF50/61" - select BOARD_LATE_INIT - select CPU_V7 - select SYS_FSL_ERRATUM_ESDHC111 - -config TARGET_PCM052 - bool "Support pcm-052" - select CPU_V7 - select SYS_FSL_ERRATUM_ESDHC111 - select SYS_FSL_ERRATUM_ESDHC135 - select SYS_FSL_ERRATUM_ESDHC_A001 - -config TARGET_BK4R1 - bool "Support BK4r1" - select CPU_V7 - select SYS_FSL_ERRATUM_ESDHC111 - select SYS_FSL_ERRATUM_ESDHC135 - select SYS_FSL_ERRATUM_ESDHC_A001 - config ARCH_ZYNQ bool "Xilinx Zynq Platform" select BOARD_LATE_INIT @@ -1197,6 +1177,8 @@ source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-uniphier/Kconfig" +source "arch/arm/cpu/armv7/vf610/Kconfig" + source "arch/arm/mach-zynq/Kconfig" source "arch/arm/cpu/armv7/Kconfig" @@ -1253,7 +1235,6 @@ source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" source "board/freescale/mx53smd/Kconfig" source "board/freescale/s32v234evb/Kconfig" -source "board/freescale/vf610twr/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" @@ -1262,7 +1243,6 @@ source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" -source "board/phytec/pcm052/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" @@ -1286,7 +1266,6 @@ source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" -source "board/toradex/colibri_vf/Kconfig" source "board/technologic/ts4600/Kconfig" source "board/technologic/ts4800/Kconfig" source "board/vscom/baltos/Kconfig" diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig new file mode 100644 index 00000000000..13905b5281f --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/Kconfig @@ -0,0 +1,36 @@ +if ARCH_VF610 + +config VF610 + bool + default y + +choice + prompt "Vybrid board select" + +config TARGET_VF610TWR + bool "TWR-VF65GS10-DS5" + +config TARGET_COLIBRI_VF + bool "Colibri VF50/61" + select BOARD_LATE_INIT + +config TARGET_PCM052 + bool "PCM-052" + select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_ESDHC_A001 + +config TARGET_BK4R1 + bool "BK4r1" + select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_ESDHC_A001 + +endchoice + +config SYS_SOC + default "vf610" + +source "board/freescale/vf610twr/Kconfig" +source "board/phytec/pcm052/Kconfig" +source "board/toradex/colibri_vf/Kconfig" + +endif diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig index ef091d6b2bf..3b90ed67fe6 100644 --- a/board/freescale/vf610twr/Kconfig +++ b/board/freescale/vf610twr/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "freescale" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "vf610twr" diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index 212f9942944..4fde21c586d 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "phytec" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "pcm052" @@ -26,9 +23,6 @@ config SYS_BOARD config SYS_VENDOR default "phytec" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "bk4r1" diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig index bf9bb0146e5..5f7129dd359 100644 --- a/board/toradex/colibri_vf/Kconfig +++ b/board/toradex/colibri_vf/Kconfig @@ -1,17 +1,11 @@ if TARGET_COLIBRI_VF -config SYS_CPU - default "armv7" - config SYS_BOARD default "colibri_vf" config SYS_VENDOR default "toradex" -config SYS_SOC - default "vf610" - config SYS_CONFIG_NAME default "colibri_vf" diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 964cfed2a7b..37a92bc33a1 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_VF610=y CONFIG_TARGET_BK4R1=y CONFIG_DEFAULT_DEVICE_TREE="bk4r1" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index c107710ce00..9d94c61897d 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_VF610=y CONFIG_TARGET_COLIBRI_VF=y CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index fbd78410512..b925aac022c 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_VF610=y CONFIG_TARGET_PCM052=y CONFIG_DEFAULT_DEVICE_TREE="pcm052" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 3f5db8b671a..12f269662f2 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_VF610=y CONFIG_TARGET_VF610TWR=y CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index c78f71659e6..a313910decb 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_VF610=y CONFIG_TARGET_VF610TWR=y CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index bfd5fbd8d73..6d05f930d36 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -14,7 +14,6 @@ #include -#define CONFIG_VF610 #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_FSL_CLK diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 49090498dac..ba3b9750de0 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -11,8 +11,6 @@ #include -#define CONFIG_VF610 - #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index dde3a114aaf..b6407e94712 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -11,8 +11,6 @@ #include -#define CONFIG_VF610 - #define CONFIG_SYS_FSL_CLK #define CONFIG_MACH_TYPE 4146 -- cgit v1.3.1 From d883fcc6bbb2fcc3df90857fee99c2f543a0289c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 13 Mar 2017 08:51:09 -0700 Subject: imx: ventana: add EMMC configuration Prepare for boards with EMMC instead of NAND flash Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/README | 17 +++++++---- configs/gwventana_defconfig | 64 --------------------------------------- configs/gwventana_emmc_defconfig | 63 ++++++++++++++++++++++++++++++++++++++ configs/gwventana_nand_defconfig | 64 +++++++++++++++++++++++++++++++++++++++ include/configs/gw_ventana.h | 8 +++-- 5 files changed, 143 insertions(+), 73 deletions(-) delete mode 100644 configs/gwventana_defconfig create mode 100644 configs/gwventana_emmc_defconfig create mode 100644 configs/gwventana_nand_defconfig (limited to 'include') diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index f3f8998aae6..57c64a1b2ad 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -30,7 +30,12 @@ will build the following artifacts from U-Boot source: To build U-Boot for the Gateworks Ventana product family: - make gwventana_config +For NAND FLASH based boards: + make gwventana_nand_config + make + +For EMMC FLASH based boards: + make gwventana_emmc_config make @@ -99,11 +104,11 @@ This information is taken from: More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. -3.1. boot from micro-SD ------------------------ +3.1. boot from MMC (eMMC/microSD) +--------------------------------- When the IMX6 eFUSE settings have been factory programmed to boot from -micro-SD the SPL will be loaded from offset 0x400 (1KB). Once the SPL is +MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is booted, it will load and execute U-Boot (u-boot.img) from offset 69KB on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR). @@ -111,11 +116,11 @@ While it is technically possible to enable the SPL to be able to load U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to use raw micro-SD access to keep the code-size and boot time of the SPL down. -For these reasons a micro-SD that will be used as an IMX6 primary boot +For these reasons an MMC device that will be used as an IMX6 primary boot device must be carefully partitioned and prepared. The following shell commands are executed on a Linux host (adjust DEV to the -block storage device of your micro-SD): +block storage device of your MMC, ie /dev/mmcblk0): DEV=/dev/sdc # zero out 1MB of device diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig deleted file mode 100644 index adc7ec84497..00000000000 --- a/configs/gwventana_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_GW_VENTANA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_VIDEO=y -CONFIG_SPL_STACK_R_ADDR=0x18000000 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" -CONFIG_BOOTDELAY=3 -# CONFIG_SYS_STDIO_DEREGISTER is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Ventana > " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_UBI=y -CONFIG_DM=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_SERIAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_G_DNL_MANUFACTURER="Gateworks" -CONFIG_G_DNL_VENDOR_NUM=0x0525 -CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig new file mode 100644 index 00000000000..96d76e45168 --- /dev/null +++ b/configs/gwventana_emmc_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_GW_VENTANA=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" +CONFIG_BOOTDELAY=3 +# CONFIG_SYS_STDIO_DEREGISTER is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Ventana > " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_UBI=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Gateworks" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig new file mode 100644 index 00000000000..6cc58970cd2 --- /dev/null +++ b/configs/gwventana_nand_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_GW_VENTANA=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" +CONFIG_BOOTDELAY=3 +# CONFIG_SYS_STDIO_DEREGISTER is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Ventana > " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_UBI=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Gateworks" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index d51bcc9e24e..1606f204ce9 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -68,7 +68,7 @@ #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #endif -#else +#elif defined(CONFIG_SPL_NAND_SUPPORT) /* Enable NAND support */ #define CONFIG_CMD_NAND #define CONFIG_CMD_NAND_TRIMFFS @@ -227,9 +227,11 @@ /* Persistent Environment Config */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined(CONFIG_SPL_NAND_SUPPORT) + #define CONFIG_ENV_IS_IN_NAND #else -#define CONFIG_ENV_IS_IN_NAND + #define CONFIG_ENV_IS_IN_MMC #endif #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 -- cgit v1.3.1