From 1ba62f10172ead798a8176435cfffff2f79f21c5 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 29 Feb 2012 12:36:51 +0000 Subject: powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- include/configs/P1010RDB.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f2d33668d8d..08fc4e84276 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -181,7 +181,7 @@ /* DDR Setup */ #define CONFIG_FSL_DDR3 -#define CONFIG_DDR_RAW_TIMING +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 3098c5acfe5..a8db06f05db 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -227,7 +227,7 @@ /* DDR Setup */ #define CONFIG_FSL_DDR3 -#define CONFIG_DDR_RAW_TIMING +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 -- cgit v1.3.1 From c9b2feafaaf0a7998347589f9a29f7169873af6e Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 28 Feb 2012 23:28:07 +0000 Subject: powerpc/p2041rdb: add NAND and NAND boot support New P2041RDB board will add a NAND chip, so add support for NAND and NAND boot. Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- boards.cfg | 1 + include/configs/P2041RDB.h | 54 +++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 52 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index 3cf75c3151b..1986da9cd9b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -742,6 +742,7 @@ P2020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freesca P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH P2041RDB powerpc mpc85xx p2041rdb freescale +P2041RDB_NAND powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index da98f8f0274..501726ca4cb 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -186,10 +186,11 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM \ +#define CONFIG_SYS_FLASH_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ - | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) +#define CONFIG_SYS_FLASH_OR_PRELIM \ + ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) #define CONFIG_FSL_CPLD #define CPLD_BASE 0xffdf0000 /* CPLD registers */ @@ -221,6 +222,53 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_RAMBOOT #endif +#define CONFIG_NAND_FSL_ELBC +/* Nand Flash */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2< Date: Tue, 28 Feb 2012 23:28:40 +0000 Subject: powerpc/p2041rdb: add env in NAND support Add env in NAND support when boot from NAND. Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- include/configs/P2041RDB.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 501726ca4cb..fe39d4e6e6b 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -96,6 +96,11 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ -- cgit v1.3.1 From fd0451e4ba3503c4ab14d88888ddda11f2a540d7 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:15 +0000 Subject: powerpc/corenet_ds: Correct the compilation errors about ENV When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE. Signed-off-by: Liu Gang --- include/configs/corenet_ds.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 77dd0a2d1e1..fd8291e854e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -97,6 +97,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- cgit v1.3.1 From 5ffa88eca78b7260788b898b69b7d17d9508268f Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:17 +0000 Subject: powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 ++-- arch/powerpc/cpu/mpc8xxx/srio.c | 51 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 61 +++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 3 ++ boards.cfg | 3 ++ include/configs/corenet_ds.h | 18 +++++++++++ 6 files changed, 140 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_srio.h (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c35ab..97a7fe1b979 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -48,8 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void srio_init(void); - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -443,6 +442,9 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); +#ifdef CONFIG_SRIOBOOT_MASTER + srio_boot_master(); +#endif #endif #if defined(CONFIG_MP) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e46d328067d..77fa32f6976 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -21,6 +21,10 @@ #include #include #include +#include + +#define SRIO_PORT_ACCEPT_ALL 0x10000001 +#define SRIO_IB_ATMU_AR 0x80f55000 #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -84,3 +88,50 @@ void srio_init(void) setbits_be32(&gur->devdisr, _DEVDISR_RMU); } } + +#ifdef CONFIG_SRIOBOOT_MASTER +void srio_boot_master(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + /* set port accept-all */ + out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr, + SRIO_PORT_ACCEPT_ALL); + + debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window5 for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window 5 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window4 for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window 4 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); +} +#endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h new file mode 100644 index 00000000000..e4cd9b6544d --- /dev/null +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -0,0 +1,61 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_SRIO_H_ +#define _FSL_SRIO_H_ + +enum atmu_size { + ATMU_SIZE_4K = 0xb, + ATMU_SIZE_8K, + ATMU_SIZE_16K, + ATMU_SIZE_32K, + ATMU_SIZE_64K, + ATMU_SIZE_128K, + ATMU_SIZE_256K, + ATMU_SIZE_512K, + ATMU_SIZE_1M, + ATMU_SIZE_2M, + ATMU_SIZE_4M, + ATMU_SIZE_8M, + ATMU_SIZE_16M, + ATMU_SIZE_32M, + ATMU_SIZE_64M, + ATMU_SIZE_128M, + ATMU_SIZE_256M, + ATMU_SIZE_512M, + ATMU_SIZE_1G, + ATMU_SIZE_2G, + ATMU_SIZE_4G, + ATMU_SIZE_8G, + ATMU_SIZE_16G, + ATMU_SIZE_32G, + ATMU_SIZE_64G, +}; + +#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1) +#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) + +extern void srio_init(void); +#ifdef CONFIG_SRIOBOOT_MASTER +extern void srio_boot_master(void); +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c4d241b7efb..632e3c1669d 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2507,6 +2507,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) @@ -2580,6 +2581,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) #define CONFIG_SYS_FSL_FM2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) +#define CONFIG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/boards.cfg b/boards.cfg index 1986da9cd9b..4821dfb27df 100644 --- a/boards.cfg +++ b/boards.cfg @@ -751,6 +751,7 @@ P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -758,11 +759,13 @@ P4080DS powerpc mpc85xx corenet_ds freesca P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index fd8291e854e..a31ccc29464 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -374,6 +374,24 @@ #endif #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * SRIOBOOT - MASTER + */ +#ifdef CONFIG_SRIOBOOT_MASTER +/* master port for srioboot*/ +#define CONFIG_SRIOBOOT_MASTER_PORT 0 +/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +#endif + /* * eSPI - Enhanced SPI */ -- cgit v1.3.1 From 292dc6c50107a5bef1084c53c36598dde177a116 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:18 +0000 Subject: powerpc/corenet_ds: Slave module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- README | 6 ++++++ board/freescale/common/p_corenet/law.c | 9 +++++++++ board/freescale/common/p_corenet/tlb.c | 9 +++++++++ boards.cfg | 3 +++ drivers/net/fm/fm.c | 2 ++ include/configs/corenet_ds.h | 28 ++++++++++++++++++++++++++++ 6 files changed, 57 insertions(+) (limited to 'include') diff --git a/README b/README index 43074cf65f8..da15105617e 100644 --- a/README +++ b/README @@ -3462,6 +3462,12 @@ within that device. Specifies that QE/FMAN firmware is located on the primary SPI device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. +- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE + Specifies that QE/FMAN firmware is located in the remote (master) + memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which + can be mapped from slave TLB->slave LAW->slave SRIO outbound window + ->master inbound window->master LAW->the ucode address in master's + NOR flash. Building the Software: ====================== diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 09ef5615d26..1fbab4d9684 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -48,6 +48,15 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), +#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), +#endif +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 6a0026a2cf7..a8c8b3c3a86 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIOBOOT_SLAVE) + /* + * SRIOBOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR, + CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/boards.cfg b/boards.cfg index 4821dfb27df..7194e089606 100644 --- a/boards.cfg +++ b/boards.cfg @@ -752,6 +752,7 @@ P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER +P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -760,12 +761,14 @@ P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER +P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER +P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 0b8c33fb7a3..49c74c278ae 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) + void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; #endif /* Upload the Fman microcode if it's present */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a31ccc29464..8ff1408c607 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -33,6 +33,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -392,6 +401,15 @@ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull #endif +/* + * SRIOBOOT - SLAVE + */ +#ifdef CONFIG_SRIOBOOT_SLAVE +/* slave port for srioboot */ +#define CONFIG_SRIOBOOT_SLAVE_PORT0 +/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#endif + /* * eSPI - Enhanced SPI */ @@ -512,6 +530,16 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO outbound window->master inbound window->master LAW-> + * the ucode address in master's NOR flash. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR NULL #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 -- cgit v1.3.1 From 3f1af81b80576bb696cc0ea2169541ee13902ce0 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:19 +0000 Subject: powerpc/corenet_ds: Slave uploads ucode when boot from SRIO When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- arch/powerpc/cpu/mpc8xxx/srio.c | 25 +++++++++++++++++++++---- board/freescale/common/p_corenet/law.c | 4 ++++ board/freescale/common/p_corenet/tlb.c | 10 ++++++++++ include/configs/corenet_ds.h | 12 +++++++++++- 4 files changed, 46 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 77fa32f6976..e593f22b106 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -100,8 +100,8 @@ void srio_boot_master(void) debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", CONFIG_SRIOBOOT_MASTER_PORT); - /* configure inbound window5 for slave's u-boot image */ - debug("SRIOBOOT - MASTER: Inbound window 5 for slave's image; " + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, @@ -117,8 +117,8 @@ void srio_boot_master(void) SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); - /* configure inbound window4 for slave's u-boot image */ - debug("SRIOBOOT - MASTER: Inbound window 4 for slave's image; " + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, @@ -133,5 +133,22 @@ void srio_boot_master(void) .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's ucode */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar, + CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar, + CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); } #endif diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 1fbab4d9684..c4566ddd4f7 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -52,9 +52,13 @@ struct law_entry law_table[] = { #if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), #elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), #endif #endif }; diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index a8c8b3c3a86..da2162728fd 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -147,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE + /* + * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode + * and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 17, BOOKE_PAGESZ_1M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 8ff1408c607..093c2c04b12 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -399,6 +399,13 @@ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +/* + * for slave UCODE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ #endif /* @@ -408,6 +415,9 @@ /* slave port for srioboot */ #define CONFIG_SRIOBOOT_SLAVE_PORT0 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR) #endif /* @@ -539,7 +549,7 @@ * the ucode address in master's NOR flash. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR NULL +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 -- cgit v1.3.1 From 0a85a9e70593a9cd90fbbbdaad8443e31a9dd5a3 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:20 +0000 Subject: powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface. NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- README | 18 ++++++++++ arch/powerpc/cpu/mpc8xxx/srio.c | 17 +++++++++ common/Makefile | 1 + common/cmd_nvedit.c | 3 +- common/env_remote.c | 79 +++++++++++++++++++++++++++++++++++++++++ include/configs/corenet_ds.h | 13 +++++++ 6 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 common/env_remote.c (limited to 'include') diff --git a/README b/README index da15105617e..a0536a4b597 100644 --- a/README +++ b/README @@ -3026,6 +3026,24 @@ to save the current settings. environment area within the total memory of your DataFlash placed at the specified address. +- CONFIG_ENV_IS_IN_REMOTE: + + Define this if you have a remote memory space which you + want to use for the local device's environment. + + - CONFIG_ENV_ADDR: + - CONFIG_ENV_SIZE: + + These two #defines specify the address and size of the + environment area within the remote memory space. The + local device can get the environment from remote memory + space by SRIO or other links. + +BE CAREFUL! For some special cases, the local device can not use +"saveenv" command. For example, the local device will get the +environment stored in a remote NOR flash by SRIO link, but it can +not erase, write this NOR flash by SRIO interface. + - CONFIG_ENV_IS_IN_NAND: Define this if you have a NAND device which you want to use diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e593f22b106..5694561eba5 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -150,5 +150,22 @@ void srio_boot_master(void) .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); + + /* configure inbound window for slave's ENV */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; " + "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n", + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar, + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } #endif diff --git a/common/Makefile b/common/Makefile index d9f10f3f6e8..6e23baaf614 100644 --- a/common/Makefile +++ b/common/Makefile @@ -59,6 +59,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o +COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o # command diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index b1494dcb0ce..e1ccdd8f7e2 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -66,9 +66,10 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CONFIG_ENV_IS_IN_NVRAM) && \ !defined(CONFIG_ENV_IS_IN_ONENAND) && \ !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \ + !defined(CONFIG_ENV_IS_IN_REMOTE) && \ !defined(CONFIG_ENV_IS_NOWHERE) # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\ -SPI_FLASH|MG_DISK|NVRAM|MMC|FAT} or CONFIG_ENV_IS_NOWHERE +SPI_FLASH|MG_DISK|NVRAM|MMC|FAT|REMOTE} or CONFIG_ENV_IS_NOWHERE #endif #define XMK_STR(x) #x diff --git a/common/env_remote.c b/common/env_remote.c new file mode 100644 index 00000000000..3bf0f957b3a --- /dev/null +++ b/common/env_remote.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include +#include +#include + +char *env_name_spec = "Remote"; + +#ifdef ENV_IS_EMBEDDED +env_t *env_ptr = &environment; +#else /* ! ENV_IS_EMBEDDED */ +env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; +#endif /* ENV_IS_EMBEDDED */ + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0 +#endif + +uchar env_get_char_spec(int index) +{ + return *((uchar *)(gd->env_addr + index)); +} + +int env_init(void) +{ + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; + return 0; + } + + gd->env_addr = (ulong)default_environment; + gd->env_valid = 0; + return 0; +} + +#ifdef CONFIG_CMD_SAVEENV +int saveenv(void) +{ +#ifdef CONFIG_SRIOBOOT_SLAVE + printf("Can not support the 'saveenv' when boot from SRIO!\n"); + return 1; +#else + return 0; +#endif +} +#endif /* CONFIG_CMD_SAVEENV */ + +void env_relocate_spec(void) +{ +#ifndef ENV_IS_EMBEDDED + env_import((char *)env_ptr, 1); +#endif +} diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 093c2c04b12..aa8b384d669 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -77,7 +77,9 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_SRIOBOOT_SLAVE #define CONFIG_ENV_IS_NOWHERE +#endif #else #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -106,6 +108,10 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_ENV_IS_NOWHERE) #define CONFIG_ENV_SIZE 0x2000 #else @@ -406,6 +412,13 @@ #define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull #define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull #define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ +/* + * for slave ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ #endif /* -- cgit v1.3.1 From 5056c8e068e30c73d3653f0b2cabbae46174a165 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:21 +0000 Subject: powerpc/corenet_ds: Slave core in holdoff when boot from SRIO When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface. Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 + arch/powerpc/cpu/mpc8xxx/srio.c | 125 ++++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 3 + include/configs/corenet_ds.h | 4 ++ 4 files changed, 135 insertions(+) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 97a7fe1b979..2cd5db7c59b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -444,6 +444,9 @@ skip_l2: srio_init(); #ifdef CONFIG_SRIOBOOT_MASTER srio_boot_master(); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF + srio_boot_master_release_slave(); +#endif #endif #endif diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 5694561eba5..c7f394972bf 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -25,6 +25,12 @@ #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 +#define SRIO_OB_ATMU_AR_MAINT 0x80077000 +#define SRIO_OB_ATMU_AR_RW 0x80045000 +#define SRIO_LCSBA1CSR_OFFSET 0x5c +#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ +#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ +#define SRIO_LCSBA1CSR 0x60000000 #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -168,4 +174,123 @@ void srio_boot_master(void) SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } + +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +void srio_boot_master_release_slave(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + u32 escsr; + debug("SRIOBOOT - MASTER: " + "Check the port status and release slave core ...\n"); + + escsr = in_be32((void *)&srio->lp_serial + .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr); + if (escsr & 0x2) { + if (escsr & 0x10100) { + debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + } else { + debug("SRIOBOOT - MASTER: " + "Port [ %d ] is ready, now release slave's core ...\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* + * configure outbound window + * with maintenance attribute to set slave's LCSBA1CSR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtar, 0); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowar, + SRIO_OB_ATMU_AR_MAINT + | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); + + /* + * configure outbound window + * with R/W attribute to set slave's BRR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtar, + SRIO_LCSBA1CSR >> 9); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO2_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO1_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowar, + SRIO_OB_ATMU_AR_RW + | atmu_size_mask(SRIO_RW_WIN_SIZE)); + + /* + * Set the LCSBA1CSR register in slave + * by the maint-outbound window + */ + if (CONFIG_SRIOBOOT_MASTER_PORT) { + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } else { + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } + debug("SRIOBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } + } else + debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", + CONFIG_SRIOBOOT_MASTER_PORT); +} +#endif #endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index e4cd9b6544d..a905a266c4d 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -57,5 +57,8 @@ enum atmu_size { extern void srio_init(void); #ifdef CONFIG_SRIOBOOT_MASTER extern void srio_boot_master(void); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +extern void srio_boot_master_release_slave(void); +#endif #endif #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index aa8b384d669..8ed37a58c20 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -419,6 +419,10 @@ #define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +/* slave core release by master*/ +#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF +#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ #endif /* -- cgit v1.3.1 From befb7d9f3c3de6b237f1f30ea5f91b24aed4992a Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Sun, 11 Mar 2012 16:15:04 +0000 Subject: PowerPC: correct the SATA for p1/p2 rdb-pc platform For p1/p2 rdb-pc platform, use the PCIe-SATA Silicon Image SATA controller. Therefore, the SATA driver will use sata_sil, instead sata_sil3114. Signed-off-by: Jerry Huang CC: Andy Fleming --- include/configs/p1_p2_rdb_pc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a8db06f05db..9f2951d6879 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -184,7 +184,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_CMD_SATA -#define CONFIG_SATA_SIL3114 +#define CONFIG_SATA_SIL #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_LIBATA #define CONFIG_LBA48 -- cgit v1.3.1