From 97205eeab4d1a785340052657673c56f2d440db7 Mon Sep 17 00:00:00 2001 From: "jerry.huang@nxp.com" Date: Tue, 15 Nov 2016 10:47:52 +0800 Subject: fsl/usb: enable usb feature for ls1046ardb Enable usb feature for ls1046ardb Signed-off-by: Changming Huang Reviewed-by: York Sun --- include/configs/ls1046ardb.h | 12 ++++++++++++ include/linux/usb/xhci-fsl.h | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2fe8fc1a440..f0719ad2a16 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -211,6 +211,18 @@ #define CONFIG_SPI_FLASH_BAR #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 15cac40e9d1..1fa31613bbd 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -62,7 +62,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -- cgit v1.2.3 From 8808aeb7a93dc36973f3a421e00d8e32318b0352 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:18 +0800 Subject: arm: ls1021a: Enable PCIe in defconfigs The patch enables PCIe in ls1021a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls1021aiot.h | 19 ------------------- include/configs/ls1021aqds.h | 16 ---------------- include/configs/ls1021atwr.h | 16 ---------------- 3 files changed, 51 deletions(-) (limited to 'include') diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index ae8ee2412fc..e270f426ffa 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -232,31 +232,12 @@ #endif /* PCIe */ -#define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ -/* Use common FSL Layerscape PCIe code */ -#define CONFIG_PCIE_LAYERSCAPE #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ - #ifdef CONFIG_PCI -#define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6f857a75ad4..f1d197592ba 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -500,24 +500,8 @@ unsigned long get_board_ddr_clk(void); /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ - #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b48cd0062be..6aff6b5276b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -370,24 +370,8 @@ /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ - #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI -- cgit v1.2.3 From 41873d1571613230faab17286fe40e1b192e6c2d Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:19 +0800 Subject: arm: ls1012a: Enable PCIe and E1000 in defconfigs The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls1012aqds.h | 16 ---------------- include/configs/ls1012ardb.h | 16 ---------------- 2 files changed, 32 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b5b4d7eeb5e..4d9a8141e76 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -154,24 +154,8 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index f35fd31cae3..23214e75323 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -67,24 +67,8 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI -- cgit v1.2.3 From be6430dc7a4be7818a924050c10fe5336231667e Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:20 +0800 Subject: armv8: ls1043a: Enable PCIe and E1000 in defconfigs The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 3e704640ed7..ff521ab5cc2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -118,27 +118,10 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ - #ifdef CONFIG_PCI #define CONFIG_NET_MULTI -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif -- cgit v1.2.3 From 2acfda1292ecc1942cdcc4cae0e719ebdbd5d7d7 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:22 +0800 Subject: armv8: ls2080a: Enable PCIe in defconfigs The patch enables PCIe in ls2080a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 22 ---------------------- include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - 3 files changed, 24 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 2cae9668c44..805457d89ab 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -171,29 +171,7 @@ unsigned long long get_qixis_addr(void); #endif /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ -#ifdef CONFIG_LS2080A #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" -#endif - -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ /* Command line configuration */ #define CONFIG_CMD_ENV diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 37d5704a724..171b77f1272 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -347,7 +347,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 713e86b41ef..feeb9620408 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -291,7 +291,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW -- cgit v1.2.3 From 19538f306b230fabb4f7244bf802eda7dee28bc7 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 13 Dec 2016 14:54:24 +0800 Subject: kconfig: move FSL_PCIE_COMPAT to platform Kconfig Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: York Sun --- include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls2080a_common.h | 3 --- 6 files changed, 8 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 4d9a8141e76..45da2af26fb 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -154,7 +154,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 23214e75323..7e4e480dc3f 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -67,7 +67,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f1d197592ba..1b4b4471482 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -500,7 +500,6 @@ unsigned long get_board_ddr_clk(void); /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6aff6b5276b..b54c4d3ce1f 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -370,7 +370,6 @@ /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index ff521ab5cc2..740d2d63b9e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -118,7 +118,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" #ifdef CONFIG_PCI #define CONFIG_NET_MULTI diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 805457d89ab..eb628fd495b 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -170,9 +170,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif -/* PCIe */ -#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" - /* Command line configuration */ #define CONFIG_CMD_ENV -- cgit v1.2.3 From 9e0bb4c1d9560cf8af0657939d01d7da8ef0f342 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 26 Dec 2016 12:15:08 +0530 Subject: arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls1012afrdm.h | 5 +++++ include/configs/ls1012aqds.h | 4 ++++ include/configs/ls1012ardb.h | 4 ++++ include/configs/ls1021aiot.h | 3 +++ include/configs/ls1021aqds.h | 3 +++ include/configs/ls1021atwr.h | 3 +++ include/configs/ls1043aqds.h | 4 ++++ include/configs/ls1043ardb.h | 4 ++++ include/configs/ls1046aqds.h | 4 ++++ include/configs/ls1046ardb.h | 4 ++++ include/configs/ls2080aqds.h | 3 +++ include/configs/ls2080ardb.h | 3 +++ 12 files changed, 44 insertions(+) (limited to 'include') diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index f6f88e84c73..94f7460eabf 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -42,6 +42,11 @@ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 45da2af26fb..fa1ed73719d 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -153,6 +153,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_NET_MULTI diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 7e4e480dc3f..d2dc5ea90cb 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -66,6 +66,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_NET_MULTI diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index e270f426ffa..9c3b163cabb 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -179,6 +179,9 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1b4b4471482..031dce7604f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -397,6 +397,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b54c4d3ce1f..1f179f40c8d 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -298,6 +298,9 @@ #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 561a05a12ce..431c8f8a911 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -100,6 +100,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 71c26bdcdab..36df3316fc2 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -310,6 +310,10 @@ #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #include #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 29e0aa5ee1e..3618a06cbca 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -143,6 +143,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index f0719ad2a16..8a8f942e0d8 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -237,6 +237,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ "$kernel_start $kernel_size;" \ "bootm $kernel_load" diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 171b77f1272..5a54c1f4015 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -63,6 +63,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index feeb9620408..7f78fd82f72 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -71,6 +71,9 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ -- cgit v1.2.3 From 904110c7ac801b99029b2bca4765c792c9eac582 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 10 Jan 2017 16:44:15 +0800 Subject: armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls1012a_common.h | 6 ++---- include/configs/ls1043a_common.h | 3 +-- include/configs/ls1046a_common.h | 3 +-- include/configs/ls2080aqds.h | 2 -- include/configs/ls2080ardb.h | 1 - 5 files changed, 4 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 20f0c6143ca..910835e03f1 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40100000 -#define CONFIG_SYS_FSL_CLK -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 125000000 +#define CONFIG_SYS_CLK_FREQ 125000000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 @@ -82,7 +80,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 740d2d63b9e..47b6ef7876c 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -11,7 +11,6 @@ #define CONFIG_FSL_LAYERSCAPE #define CONFIG_LS1043A #define CONFIG_MP -#define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include @@ -42,7 +41,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 40e6af8127f..4a910d161cd 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -10,7 +10,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_MP -#define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include @@ -41,7 +40,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 5a54c1f4015..c39e9cf14e4 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -14,8 +14,6 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#define CONFIG_SYS_FSL_CLK - #ifdef CONFIG_FSL_QSPI #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 7f78fd82f72..5626d884f90 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,7 +32,6 @@ unsigned long get_board_sys_clk(void); #endif -#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -- cgit v1.2.3 From 3564208e013d34eb0dab58d2f1561feee3f5735d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 10 Jan 2017 16:44:16 +0800 Subject: armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index eb628fd495b..32d56aede23 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -97,7 +97,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- cgit v1.2.3 From 9ed44787f60a93d440824130dee0ae53500e1b83 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Fri, 6 Jan 2017 15:58:57 +0530 Subject: LS2080A: Add validation of MC & DPC images. Add secure boot validation of MC, DPC images using esbc_validate command. Signed-off-by: Sumit Garg Signed-off-by: Udit Agarwal Reviewed-by: York Sun --- include/configs/ls2080aqds.h | 21 ++++++++++++++++++++- include/configs/ls2080ardb.h | 30 ++++++++++++++++++++++++++++-- 2 files changed, 48 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index c39e9cf14e4..e8f2e49a4ce 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -364,6 +364,7 @@ unsigned long get_board_ddr_clk(void); /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_SECURE_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ @@ -375,8 +376,26 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ + "mcinitcmd=esbc_validate 0x580c80000;" \ + "esbc_validate 0x580cc0000;" \ + "fsl_mc start mc 0x580300000" \ " 0x580800000 \0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" +#endif /* CONFIG_SECURE_BOOT */ + #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 5626d884f90..bbcbd660505 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -329,6 +329,7 @@ unsigned long get_board_sys_clk(void); /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_SECURE_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "scriptaddr=0x80800000\0" \ @@ -346,9 +347,34 @@ unsigned long get_board_sys_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" \ + "mcinitcmd=esbc_validate 0x580c80000;" \ + "esbc_validate 0x580cc0000;" \ + "fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" \ BOOTENV +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "fdtfile=fsl-ls2080a-rdb.dtb\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" \ + BOOTENV +#endif + #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ -- cgit v1.2.3 From 762161b04ade62be5c708ff167f5fdde2e61fa9c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:08:57 +0800 Subject: pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic This patch adds a simple pmic driver for the mc34vr500 pmic which is used in conjunction with the fsl T1 and LS1 series SoC. Signed-off-by: Hou Zhiqiang Reviewed-by: Jaehoon Chung Reviewed-by: York Sun --- include/power/mc34vr500_pmic.h | 166 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 include/power/mc34vr500_pmic.h (limited to 'include') diff --git a/include/power/mc34vr500_pmic.h b/include/power/mc34vr500_pmic.h new file mode 100644 index 00000000000..df4985ace74 --- /dev/null +++ b/include/power/mc34vr500_pmic.h @@ -0,0 +1,166 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Hou Zhiqiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MC34VR500_H_ +#define __MC34VR500_H_ + +#include + +#define MC34VR500_I2C_ADDR 0x08 + +/* Drivers name */ +#define MC34VR500_REGULATOR_DRIVER "mc34vr500_regulator" + +/* Register map */ +enum { + MC34VR500_DEVICEID = 0x00, + + MC34VR500_SILICONREVID = 0x03, + MC34VR500_FABID, + MC34VR500_INTSTAT0, + MC34VR500_INTMASK0, + MC34VR500_INTSENSE0, + MC34VR500_INTSTAT1, + MC34VR500_INTMASK1, + MC34VR500_INTSENSE1, + + MC34VR500_INTSTAT4 = 0x11, + MC34VR500_INTMASK4, + MC34VR500_INTSENSE4, + + MC34VR500_PWRCTL = 0x1B, + + MC34VR500_SW1VOLT = 0x2E, + MC34VR500_SW1STBY, + MC34VR500_SW1OFF, + MC34VR500_SW1MODE, + MC34VR500_SW1CONF, + MC34VR500_SW2VOLT, + MC34VR500_SW2STBY, + MC34VR500_SW2OFF, + MC34VR500_SW2MODE, + MC34VR500_SW2CONF, + + MC34VR500_SW3VOLT = 0x3C, + MC34VR500_SW3STBY, + MC34VR500_SW3OFF, + MC34VR500_SW3MODE, + MC34VR500_SW3CONF, + + MC34VR500_SW4VOLT = 0x4A, + MC34VR500_SW4STBY, + MC34VR500_SW4OFF, + MC34VR500_SW4MODE, + MC34VR500_SW4CONF, + + MC34VR500_REFOUTCRTRL = 0x6A, + + MC34VR500_LDO1CTL = 0x6D, + MC34VR500_LDO2CTL, + MC34VR500_LDO3CTL, + MC34VR500_LDO4CTL, + MC34VR500_LDO5CTL, + + MC34VR500_PAGE_REGISTER = 0x7F, + + /* Internal RAM */ + MC34VR500_SW1_VOLT = 0xA8, + MC34VR500_SW1_SEQ, + MC34VR500_SW1_CONFIG, + + MC34VR500_SW2_VOLT = 0xAC, + MC34VR500_SW2_SEQ, + MC34VR500_SW2_CONFIG, + + MC34VR500_SW3_VOLT = 0xB0, + MC34VR500_SW3_SEQ, + MC34VR500_SW3_CONFIG, + + MC34VR500_SW4_VOLT = 0xB8, + MC34VR500_SW4_SEQ, + MC34VR500_SW4_CONFIG, + + MC34VR500_REFOUT_SEQ = 0xC4, + + MC34VR500_LDO1_VOLT = 0xCC, + MC34VR500_LDO1_SEQ, + + MC34VR500_LDO2_VOLT = 0xD0, + MC34VR500_LDO2_SEQ, + + MC34VR500_LDO3_VOLT = 0xD4, + MC34VR500_LDO3_SEQ, + + MC34VR500_LDO4_VOLT = 0xD8, + MC34VR500_LDO4_SEQ, + + MC34VR500_LDO5_VOLT = 0xDC, + MC34VR500_LDO5_SEQ, + + MC34VR500_PU_CONFIG1 = 0xE0, + + MC34VR500_TBB_POR = 0xE4, + + MC34VR500_PWRGD_EN = 0xE8, + + MC34VR500_NUM_OF_REGS, +}; + +/* Registor offset based on SWxVOLT register */ +#define MC34VR500_VOLT_OFFSET 0 +#define MC34VR500_STBY_OFFSET 1 +#define MC34VR500_OFF_OFFSET 2 +#define MC34VR500_MODE_OFFSET 3 +#define MC34VR500_CONF_OFFSET 4 + +#define SW_MODE_MASK 0xf +#define SW_MODE_SHIFT 0 + +#define LDO_VOL_MASK 0xf +#define LDO_EN (1 << 4) +#define LDO_MODE_SHIFT 4 +#define LDO_MODE_MASK (1 << 4) +#define LDO_MODE_OFF 0 +#define LDO_MODE_ON 1 + +#define REFOUTEN (1 << 4) + +/* + * Regulator Mode Control + * + * OFF: The regulator is switched off and the output voltage is discharged. + * PFM: In this mode, the regulator is always in PFM mode, which is useful + * at light loads for optimized efficiency. + * PWM: In this mode, the regulator is always in PWM mode operation + * regardless of load conditions. + * APS: In this mode, the regulator moves automatically between pulse + * skipping mode and PWM mode depending on load conditions. + * + * SWxMODE[3:0] + * Normal Mode | Standby Mode | value + * OFF OFF 0x0 + * PWM OFF 0x1 + * PFM OFF 0x3 + * APS OFF 0x4 + * PWM PWM 0x5 + * PWM APS 0x6 + * APS APS 0x8 + * APS PFM 0xc + * PWM PFM 0xd + */ +#define OFF_OFF 0x0 +#define PWM_OFF 0x1 +#define PFM_OFF 0x3 +#define APS_OFF 0x4 +#define PWM_PWM 0x5 +#define PWM_APS 0x6 +#define APS_APS 0x8 +#define APS_PFM 0xc +#define PWM_PFM 0xd + +int power_mc34vr500_init(unsigned char bus); +#endif /* __MC34VR500_PMIC_H_ */ -- cgit v1.2.3 From 4394ad1227e5752b13fefa99846cb7073f4dd42b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:08:58 +0800 Subject: pmic: pmic_mc34vr500: Add APIs to set/get SWx volt Signed-off-by: Hou Zhiqiang Reviewed-by: Jaehoon Chung Reviewed-by: York Sun --- include/power/mc34vr500_pmic.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/power/mc34vr500_pmic.h b/include/power/mc34vr500_pmic.h index df4985ace74..b0b143a5919 100644 --- a/include/power/mc34vr500_pmic.h +++ b/include/power/mc34vr500_pmic.h @@ -162,5 +162,14 @@ enum { #define APS_PFM 0xc #define PWM_PFM 0xd +enum swx { + SW1 = 0, + SW2, + SW3, + SW4, +}; + +int mc34vr500_get_sw_volt(uint8_t sw); +int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt); int power_mc34vr500_init(unsigned char bus); #endif /* __MC34VR500_PMIC_H_ */ -- cgit v1.2.3 From 031acdbae89515371f794d01df819b490ff7ca9c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:09:00 +0800 Subject: armv8/fsl_lsch2: Add chip power supply voltage setup Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 1404c579360..b8de46bb42e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -173,6 +173,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_V0PT9_EN 0x40000000 #define DDR_CDR1_ODT_SHIFT 17 #define DDR_CDR1_ODT_MASK 0x6 #define DDR_CDR2_ODT_MASK 0x1 -- cgit v1.2.3 From dccef2ec01cdf5403d78223fd60a4ccd761ae6b0 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:09:01 +0800 Subject: ls1046ardb: Add support power initialization Add the chip power supply voltage initialization on LS1046ARDB. Add function power_init_board(), and it will initialize the PMIC and call the chip power initialization function. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls1046ardb.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 8a8f942e0d8..2bfd83c758f 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -164,6 +164,12 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define I2C_RETIMER_ADDR 0x18 +/* PMIC */ +#define CONFIG_POWER +#ifdef CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + /* * Environment */ -- cgit v1.2.3 From 0897eb2ced0579ee58b7d50076faa93605e33ed1 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 16 Jan 2017 17:31:47 +0800 Subject: kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 3 --- include/configs/ls1046ardb.h | 4 ---- 2 files changed, 7 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 36df3316fc2..3657f21dfbe 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -10,9 +10,6 @@ #include "ls1043a_common.h" #if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#define SEC_FIRMWARE_ERET_ADDR_REVERT - #define CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2bfd83c758f..08c5441807b 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -10,10 +10,6 @@ #include "ls1046a_common.h" #if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_ARMV8_PSCI -#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024) - #define CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 -- cgit v1.2.3 From 0541527bde7d2df155fc9691115d234fa7a3f603 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 16 Jan 2017 17:31:49 +0800 Subject: kconfig: fsl PPA: move CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 7 ------- include/configs/ls1046ardb.h | 7 ------- 2 files changed, 14 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 3657f21dfbe..0054d1643ea 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,13 +9,6 @@ #include "ls1043a_common.h" -#if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_SYS_LS_PPA_FW_IN_XIP -#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP -#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 -#endif -#endif - #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 #else diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 08c5441807b..24843dc9ba7 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,13 +9,6 @@ #include "ls1046a_common.h" -#if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_SYS_LS_PPA_FW_IN_XIP -#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP -#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 -#endif -#endif - #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_TEXT_BASE 0x82000000 #else -- cgit v1.2.3