From d53b7074ebcad4a69aa80502df46f4dfd35c18de Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 25 Jul 2024 09:46:03 +0000 Subject: rockchip: px30/rk3326: Use soc dtsi files from dts/upstream The commit f087f7fd277d ("rockchip: px30/rk3326: migrate to OF_UPSTREAM") migrated px30/rk3326 boards to use OF_UPSTREAM, however the soc dtsi and dt-bindings files remained. Remove the remaining px30/rk3326 soc dtsi and dt-bindings to ensure the files from dts/upstream is used. The gpio-ranges props is moved to u-boot.dtsi files and a ethernet0 alias is added to px30-firefly, they are missing in the dts/upstream files. No changes are expected with this. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz --- include/dt-bindings/clock/px30-cru.h | 389 --------------------------------- include/dt-bindings/power/px30-power.h | 27 --- 2 files changed, 416 deletions(-) delete mode 100644 include/dt-bindings/clock/px30-cru.h delete mode 100644 include/dt-bindings/power/px30-power.h (limited to 'include') diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h deleted file mode 100644 index e5e59690b5f..00000000000 --- a/include/dt-bindings/clock/px30-cru.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H -#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_NPLL 4 -#define APLL_BOOST_H 5 -#define APLL_BOOST_L 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define USB480M 14 -#define SCLK_PDM 15 -#define SCLK_I2S0_TX 16 -#define SCLK_I2S0_TX_OUT 17 -#define SCLK_I2S0_RX 18 -#define SCLK_I2S0_RX_OUT 19 -#define SCLK_I2S1 20 -#define SCLK_I2S1_OUT 21 -#define SCLK_I2S2 22 -#define SCLK_I2S2_OUT 23 -#define SCLK_UART1 24 -#define SCLK_UART2 25 -#define SCLK_UART3 26 -#define SCLK_UART4 27 -#define SCLK_UART5 28 -#define SCLK_I2C0 29 -#define SCLK_I2C1 30 -#define SCLK_I2C2 31 -#define SCLK_I2C3 32 -#define SCLK_I2C4 33 -#define SCLK_PWM0 34 -#define SCLK_PWM1 35 -#define SCLK_SPI0 36 -#define SCLK_SPI1 37 -#define SCLK_TIMER0 38 -#define SCLK_TIMER1 39 -#define SCLK_TIMER2 40 -#define SCLK_TIMER3 41 -#define SCLK_TIMER4 42 -#define SCLK_TIMER5 43 -#define SCLK_TSADC 44 -#define SCLK_SARADC 45 -#define SCLK_OTP 46 -#define SCLK_OTP_USR 47 -#define SCLK_CRYPTO 48 -#define SCLK_CRYPTO_APK 49 -#define SCLK_DDRC 50 -#define SCLK_ISP 51 -#define SCLK_CIF_OUT 52 -#define SCLK_RGA_CORE 53 -#define SCLK_VOPB_PWM 54 -#define SCLK_NANDC 55 -#define SCLK_SDIO 56 -#define SCLK_EMMC 57 -#define SCLK_SFC 58 -#define SCLK_SDMMC 59 -#define SCLK_OTG_ADP 60 -#define SCLK_GMAC_SRC 61 -#define SCLK_GMAC 62 -#define SCLK_GMAC_RX_TX 63 -#define SCLK_MAC_REF 64 -#define SCLK_MAC_REFOUT 65 -#define SCLK_MAC_OUT 66 -#define SCLK_SDMMC_DRV 67 -#define SCLK_SDMMC_SAMPLE 68 -#define SCLK_SDIO_DRV 69 -#define SCLK_SDIO_SAMPLE 70 -#define SCLK_EMMC_DRV 71 -#define SCLK_EMMC_SAMPLE 72 -#define SCLK_GPU 73 -#define SCLK_PVTM 74 -#define SCLK_CORE_VPU 75 -#define SCLK_GMAC_RMII 76 -#define SCLK_UART2_SRC 77 -#define SCLK_NANDC_DIV 78 -#define SCLK_NANDC_DIV50 79 -#define SCLK_SDIO_DIV 80 -#define SCLK_SDIO_DIV50 81 -#define SCLK_EMMC_DIV 82 -#define SCLK_EMMC_DIV50 83 - -/* dclk gates */ -#define DCLK_VOPB 150 -#define DCLK_VOPL 151 - -/* aclk gates */ -#define ACLK_GPU 170 -#define ACLK_BUS_PRE 171 -#define ACLK_CRYPTO 172 -#define ACLK_VI_PRE 173 -#define ACLK_VO_PRE 174 -#define ACLK_VPU 175 -#define ACLK_PERI_PRE 176 -#define ACLK_GMAC 178 -#define ACLK_CIF 179 -#define ACLK_ISP 180 -#define ACLK_VOPB 181 -#define ACLK_VOPL 182 -#define ACLK_RGA 183 -#define ACLK_GIC 184 -#define ACLK_DCF 186 -#define ACLK_DMAC 187 - -/* hclk gates */ -#define HCLK_BUS_PRE 240 -#define HCLK_CRYPTO 241 -#define HCLK_VI_PRE 242 -#define HCLK_VO_PRE 243 -#define HCLK_VPU 244 -#define HCLK_PERI_PRE 245 -#define HCLK_MMC_NAND 246 -#define HCLK_SDMMC 247 -#define HCLK_USB 248 -#define HCLK_CIF 249 -#define HCLK_ISP 250 -#define HCLK_VOPB 251 -#define HCLK_VOPL 252 -#define HCLK_RGA 253 -#define HCLK_NANDC 254 -#define HCLK_SDIO 255 -#define HCLK_EMMC 256 -#define HCLK_SFC 257 -#define HCLK_OTG 258 -#define HCLK_HOST 259 -#define HCLK_HOST_ARB 260 -#define HCLK_PDM 261 -#define HCLK_I2S0 262 -#define HCLK_I2S1 263 -#define HCLK_I2S2 264 - -/* pclk gates */ -#define PCLK_BUS_PRE 320 -#define PCLK_DDR 321 -#define PCLK_VO_PRE 322 -#define PCLK_GMAC 323 -#define PCLK_MIPI_DSI 324 -#define PCLK_MIPIDSIPHY 325 -#define PCLK_MIPICSIPHY 326 -#define PCLK_USB_GRF 327 -#define PCLK_DCF 328 -#define PCLK_UART1 329 -#define PCLK_UART2 330 -#define PCLK_UART3 331 -#define PCLK_UART4 332 -#define PCLK_UART5 333 -#define PCLK_I2C0 334 -#define PCLK_I2C1 335 -#define PCLK_I2C2 336 -#define PCLK_I2C3 337 -#define PCLK_I2C4 338 -#define PCLK_PWM0 339 -#define PCLK_PWM1 340 -#define PCLK_SPI0 341 -#define PCLK_SPI1 342 -#define PCLK_SARADC 343 -#define PCLK_TSADC 344 -#define PCLK_TIMER 345 -#define PCLK_OTP_NS 346 -#define PCLK_WDT_NS 347 -#define PCLK_GPIO1 348 -#define PCLK_GPIO2 349 -#define PCLK_GPIO3 350 -#define PCLK_ISP 351 -#define PCLK_CIF 352 -#define PCLK_OTP_PHY 353 - -#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) - -/* pmu-clocks indices */ - -#define PLL_GPLL 1 - -#define SCLK_RTC32K_PMU 4 -#define SCLK_WIFI_PMU 5 -#define SCLK_UART0_PMU 6 -#define SCLK_PVTM_PMU 7 -#define PCLK_PMU_PRE 8 -#define SCLK_REF24M_PMU 9 -#define SCLK_USBPHY_REF 10 -#define SCLK_MIPIDSIPHY_REF 11 - -#define XIN24M_DIV 12 - -#define PCLK_GPIO0_PMU 20 -#define PCLK_UART0_PMU 21 - -#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_GPU 18 -#define SRST_GPU_NIU 19 -#define SRST_UPCTL2 20 -#define SRST_UPCTL2_A 21 -#define SRST_UPCTL2_P 22 -#define SRST_MSCH 23 -#define SRST_MSCH_P 24 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRGRF_p 28 -#define SRST_AXI_SPLIT_A 29 -#define SRST_AXI_CMD_A 30 -#define SRST_AXI_CMD_P 31 - -#define SRST_DDRPHY 32 -#define SRST_DDRPHYDIV 33 -#define SRST_DDRPHY_P 34 -#define SRST_VPU_A 36 -#define SRST_VPU_NIU_A 37 -#define SRST_VPU_H 38 -#define SRST_VPU_NIU_H 39 -#define SRST_VI_NIU_A 40 -#define SRST_VI_NIU_H 41 -#define SRST_ISP_H 42 -#define SRST_ISP 43 -#define SRST_CIF_A 44 -#define SRST_CIF_H 45 -#define SRST_CIF_PCLKIN 46 -#define SRST_MIPICSIPHY_P 47 - -#define SRST_VO_NIU_A 48 -#define SRST_VO_NIU_H 49 -#define SRST_VO_NIU_P 50 -#define SRST_VOPB_A 51 -#define SRST_VOPB_H 52 -#define SRST_VOPB 53 -#define SRST_PWM_VOPB 54 -#define SRST_VOPL_A 55 -#define SRST_VOPL_H 56 -#define SRST_VOPL 57 -#define SRST_RGA_A 58 -#define SRST_RGA_H 59 -#define SRST_RGA 60 -#define SRST_MIPIDSI_HOST_P 61 -#define SRST_MIPIDSIPHY_P 62 -#define SRST_VPU_CORE 63 - -#define SRST_PERI_NIU_A 64 -#define SRST_USB_NIU_H 65 -#define SRST_USB2OTG_H 66 -#define SRST_USB2OTG 67 -#define SRST_USB2OTG_ADP 68 -#define SRST_USB2HOST_H 69 -#define SRST_USB2HOST_ARB_H 70 -#define SRST_USB2HOST_AUX_H 71 -#define SRST_USB2HOST_EHCI 72 -#define SRST_USB2HOST 73 -#define SRST_USBPHYPOR 74 -#define SRST_USBPHY_OTG_PORT 75 -#define SRST_USBPHY_HOST_PORT 76 -#define SRST_USBPHY_GRF 77 -#define SRST_CPU_BOOST_P 78 -#define SRST_CPU_BOOST 79 - -#define SRST_MMC_NAND_NIU_H 80 -#define SRST_SDIO_H 81 -#define SRST_EMMC_H 82 -#define SRST_SFC_H 83 -#define SRST_SFC 84 -#define SRST_SDCARD_NIU_H 85 -#define SRST_SDMMC_H 86 -#define SRST_NANDC_H 89 -#define SRST_NANDC 90 -#define SRST_GMAC_NIU_A 92 -#define SRST_GMAC_NIU_P 93 -#define SRST_GMAC_A 94 - -#define SRST_PMU_NIU_P 96 -#define SRST_PMU_SGRF_P 97 -#define SRST_PMU_GRF_P 98 -#define SRST_PMU 99 -#define SRST_PMU_MEM_P 100 -#define SRST_PMU_GPIO0_P 101 -#define SRST_PMU_UART0_P 102 -#define SRST_PMU_CRU_P 103 -#define SRST_PMU_PVTM 104 -#define SRST_PMU_UART 105 -#define SRST_PMU_NIU_H 106 -#define SRST_PMU_DDR_FAIL_SAVE 107 -#define SRST_PMU_CORE_PERF_A 108 -#define SRST_PMU_CORE_GRF_P 109 -#define SRST_PMU_GPU_PERF_A 110 -#define SRST_PMU_GPU_GRF_P 111 - -#define SRST_CRYPTO_NIU_A 112 -#define SRST_CRYPTO_NIU_H 113 -#define SRST_CRYPTO_A 114 -#define SRST_CRYPTO_H 115 -#define SRST_CRYPTO 116 -#define SRST_CRYPTO_APK 117 -#define SRST_BUS_NIU_H 120 -#define SRST_USB_NIU_P 121 -#define SRST_BUS_TOP_NIU_P 122 -#define SRST_INTMEM_A 123 -#define SRST_GIC_A 124 -#define SRST_ROM_H 126 -#define SRST_DCF_A 127 - -#define SRST_DCF_P 128 -#define SRST_PDM_H 129 -#define SRST_PDM 130 -#define SRST_I2S0_H 131 -#define SRST_I2S0_TX 132 -#define SRST_I2S1_H 133 -#define SRST_I2S1 134 -#define SRST_I2S2_H 135 -#define SRST_I2S2 136 -#define SRST_UART1_P 137 -#define SRST_UART1 138 -#define SRST_UART2_P 139 -#define SRST_UART2 140 -#define SRST_UART3_P 141 -#define SRST_UART3 142 -#define SRST_UART4_P 143 - -#define SRST_UART4 144 -#define SRST_UART5_P 145 -#define SRST_UART5 146 -#define SRST_I2C0_P 147 -#define SRST_I2C0 148 -#define SRST_I2C1_P 149 -#define SRST_I2C1 150 -#define SRST_I2C2_P 151 -#define SRST_I2C2 152 -#define SRST_I2C3_P 153 -#define SRST_I2C3 154 -#define SRST_PWM0_P 157 -#define SRST_PWM0 158 -#define SRST_PWM1_P 159 - -#define SRST_PWM1 160 -#define SRST_SPI0_P 161 -#define SRST_SPI0 162 -#define SRST_SPI1_P 163 -#define SRST_SPI1 164 -#define SRST_SARADC_P 165 -#define SRST_SARADC 166 -#define SRST_TSADC_P 167 -#define SRST_TSADC 168 -#define SRST_TIMER_P 169 -#define SRST_TIMER0 170 -#define SRST_TIMER1 171 -#define SRST_TIMER2 172 -#define SRST_TIMER3 173 -#define SRST_TIMER4 174 -#define SRST_TIMER5 175 - -#define SRST_OTP_NS_P 176 -#define SRST_OTP_NS_SBPI 177 -#define SRST_OTP_NS_USR 178 -#define SRST_OTP_PHY_P 179 -#define SRST_OTP_PHY 180 -#define SRST_WDT_NS_P 181 -#define SRST_GPIO1_P 182 -#define SRST_GPIO2_P 183 -#define SRST_GPIO3_P 184 -#define SRST_SGRF_P 185 -#define SRST_GRF_P 186 -#define SRST_I2S0_RX 191 - -#endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h deleted file mode 100644 index 30917a99ad2..00000000000 --- a/include/dt-bindings/power/px30-power.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ -#define __DT_BINDINGS_POWER_PX30_POWER_H__ - -/* VD_CORE */ -#define PX30_PD_A35_0 0 -#define PX30_PD_A35_1 1 -#define PX30_PD_A35_2 2 -#define PX30_PD_A35_3 3 -#define PX30_PD_SCU 4 - -/* VD_LOGIC */ -#define PX30_PD_USB 5 -#define PX30_PD_DDR 6 -#define PX30_PD_SDCARD 7 -#define PX30_PD_CRYPTO 8 -#define PX30_PD_GMAC 9 -#define PX30_PD_MMC_NAND 10 -#define PX30_PD_VPU 11 -#define PX30_PD_VO 12 -#define PX30_PD_VI 13 -#define PX30_PD_GPU 14 - -/* VD_PMU */ -#define PX30_PD_PMU 15 - -#endif -- cgit v1.3.1 From c308148a3e30ac97423d3f956589bfe321114e66 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 25 Jul 2024 09:46:04 +0000 Subject: rockchip: Use files from dts/upstream Most Rockchip aarch64 targets have now migrated to use OF_UPSTREAM, however a few of the old dtsi and dt-bindings files still remain. Remove remaining common dtsi and header files that can be included directly from dts/upstream to prevent possible issues when future tags from devicetree-binding is merged. No changes is expected with this. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz --- arch/arm/dts/rockchip-pinconf.dtsi | 344 --------------------------- include/dt-bindings/clock/rockchip,rk808.h | 11 - include/dt-bindings/soc/rockchip,boot-mode.h | 16 -- include/dt-bindings/soc/rockchip,vop2.h | 18 -- 4 files changed, 389 deletions(-) delete mode 100644 arch/arm/dts/rockchip-pinconf.dtsi delete mode 100644 include/dt-bindings/clock/rockchip,rk808.h delete mode 100644 include/dt-bindings/soc/rockchip,boot-mode.h delete mode 100644 include/dt-bindings/soc/rockchip,vop2.h (limited to 'include') diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi deleted file mode 100644 index 5c645437b50..00000000000 --- a/arch/arm/dts/rockchip-pinconf.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -&pinctrl { - /omit-if-no-ref/ - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - /omit-if-no-ref/ - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - /omit-if-no-ref/ - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { - bias-disable; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { - bias-disable; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { - bias-disable; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { - bias-disable; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { - bias-disable; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { - bias-disable; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { - bias-disable; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { - bias-disable; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { - bias-disable; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { - bias-disable; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { - bias-disable; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { - bias-disable; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { - bias-disable; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { - bias-disable; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { - bias-disable; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { - bias-disable; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { - bias-pull-up; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { - bias-pull-up; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { - bias-pull-up; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { - bias-pull-up; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { - bias-pull-up; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { - bias-pull-up; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { - bias-pull-up; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { - bias-pull-up; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { - bias-pull-up; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { - bias-pull-up; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { - bias-pull-up; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { - bias-pull-up; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { - bias-pull-up; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { - bias-pull-up; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { - bias-pull-up; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { - bias-pull-up; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { - bias-pull-down; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { - bias-pull-down; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { - bias-pull-down; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { - bias-pull-down; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { - bias-pull-down; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { - bias-pull-down; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { - bias-pull-down; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { - bias-pull-down; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { - bias-pull-down; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { - bias-pull-down; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { - bias-pull-down; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { - bias-pull-down; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { - bias-pull-down; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { - bias-pull-down; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { - bias-pull-down; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { - bias-pull-down; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_smt: pcfg-pull-up-smt { - bias-pull-up; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_down_smt: pcfg-pull-down-smt { - bias-pull-down; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { - bias-disable; - drive-strength = <0>; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_output_high: pcfg-output-high { - output-high; - }; - - /omit-if-no-ref/ - pcfg_output_low: pcfg-output-low { - output-low; - }; -}; diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 1a873432f96..00000000000 --- a/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h deleted file mode 100644 index 4b0914c0989..00000000000 --- a/include/dt-bindings/soc/rockchip,boot-mode.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ROCKCHIP_BOOT_MODE_H -#define __ROCKCHIP_BOOT_MODE_H - -/*high 24 bits is tag, low 8 bits is type*/ -#define REBOOT_FLAG 0x5242C300 -/* normal boot */ -#define BOOT_NORMAL (REBOOT_FLAG + 0) -/* enter bootloader rockusb mode */ -#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) -/* enter recovery */ -#define BOOT_RECOVERY (REBOOT_FLAG + 3) - /* enter fastboot mode */ -#define BOOT_FASTBOOT (REBOOT_FLAG + 9) - -#endif diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h deleted file mode 100644 index 668f199df9f..00000000000 --- a/include/dt-bindings/soc/rockchip,vop2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ - -#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -#define __DT_BINDINGS_ROCKCHIP_VOP2_H - -#define ROCKCHIP_VOP2_EP_RGB0 1 -#define ROCKCHIP_VOP2_EP_HDMI0 2 -#define ROCKCHIP_VOP2_EP_EDP0 3 -#define ROCKCHIP_VOP2_EP_MIPI0 4 -#define ROCKCHIP_VOP2_EP_LVDS0 5 -#define ROCKCHIP_VOP2_EP_MIPI1 6 -#define ROCKCHIP_VOP2_EP_LVDS1 7 -#define ROCKCHIP_VOP2_EP_HDMI1 8 -#define ROCKCHIP_VOP2_EP_EDP1 9 -#define ROCKCHIP_VOP2_EP_DP0 10 -#define ROCKCHIP_VOP2_EP_DP1 11 - -#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ -- cgit v1.3.1 From d27c3431ae7e2394843a09a1d36a78f22fa8b50f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 2 Aug 2024 23:00:28 +0200 Subject: board: rockchip: Add Radxa ROCK 5 ITX The Rock 5 ITX is a board in ITX form factor using the RK3588 SoC It can be powered either by 12V, ATX power-supply or PoE. Notable peripherals are the 4 SATA ports, M.2 M-Key slot, M.2 E-key slot, 2*2.5Gb PCIe-connected Ethernet NICs. Display options are 2*HDMI, DP via USB-c, eDP + 2*DSI via PCB connectors. USB ports are 4*USB3 + 2*USB2 on the back panel and 2-port front-panel connector. Schematics for the board can be found on - https://dl.radxa.com/rock5/5itx/radxa_rock_5_itx_X1100_schematic.pdf - https://dl.radxa.com/rock5/5itx/v1110/radxa_rock_5itx_v1110_schematic.pdf The naming scheme with the dashes follows Dragan's comment on the mainline devicetree commit: "the name of this board deviates from the standard Radxa naming scheme, which is something like "ROCK " thus, "rock-5a" is fine, but it should be "rock-5-itx", simply because there's a space between "5" and "ITX" in "ROCK 5 ITX" Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang Signed-off-by: Kever Yang --- arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi | 22 ++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 29 ++++++++ board/radxa/rock-5-itx-rk3588/Kconfig | 12 ++++ board/radxa/rock-5-itx-rk3588/MAINTAINERS | 8 +++ configs/rock-5-itx-rk3588_defconfig | 111 +++++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/rock-5-itx-rk3588.h | 15 ++++ 7 files changed, 198 insertions(+) create mode 100644 arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi create mode 100644 board/radxa/rock-5-itx-rk3588/Kconfig create mode 100644 board/radxa/rock-5-itx-rk3588/MAINTAINERS create mode 100644 configs/rock-5-itx-rk3588_defconfig create mode 100644 include/configs/rock-5-itx-rk3588.h (limited to 'include') diff --git a/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi new file mode 100644 index 00000000000..1e5c2674e49 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&vcc3v3_mkey { + regulator-always-on; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 72c5e569fb8..a76a470cc98 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -208,6 +208,34 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_ROCK_5_ITX_RK3588 + bool "Radxa ROCK-5-ITX RK3588 board" + select BOARD_LATE_INIT + help + Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board + Computer) by Radxa in the ITX formfactor. + + There are variants depending on the DRAM size : from 4G up to 32G. + + Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 4/8/16/24/32GB memory LPDDR5 + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + eMMC + uSD slot (up to 128GB) + M.2 M-key and M.2 E-key connector + 4x SATA + 2x USB 2.0 + 4x USB 3.0 Type-A, 2x USB 2.0 Panel, 1x USB 3.0 Type-C + 2x HDMI 2.1 output, 1x HDMI input + DP via Type-C + 2x DSI via PCB connector + 2x 2.5 Gbps Ethernet port + Front-panel connectors for audio and case-power, -leds + Powered by either 12V, ATX power-supply or PoE + config TARGET_SIGE7_RK3588 bool "ArmSoM Sige7 RK3588 board" select BOARD_LATE_INIT @@ -343,6 +371,7 @@ source "board/pine64/quartzpro64-rk3588/Kconfig" source "board/turing/turing-rk1-rk3588/Kconfig" source "board/radxa/rock5a-rk3588s/Kconfig" source "board/radxa/rock5b-rk3588/Kconfig" +source "board/radxa/rock-5-itx-rk3588/Kconfig" source "board/rockchip/evb_rk3588/Kconfig" source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" diff --git a/board/radxa/rock-5-itx-rk3588/Kconfig b/board/radxa/rock-5-itx-rk3588/Kconfig new file mode 100644 index 00000000000..f7a7666d531 --- /dev/null +++ b/board/radxa/rock-5-itx-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROCK_5_ITX_RK3588 + +config SYS_BOARD + default "rock-5-itx-rk3588" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock-5-itx-rk3588" + +endif diff --git a/board/radxa/rock-5-itx-rk3588/MAINTAINERS b/board/radxa/rock-5-itx-rk3588/MAINTAINERS new file mode 100644 index 00000000000..1c4f24306a0 --- /dev/null +++ b/board/radxa/rock-5-itx-rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +ROCK-5-ITX-RK3588 +M: Heiko Stuebner +R: Jonas Karlman +S: Maintained +F: board/radxa/rock-5-itx-rk3588 +F: include/configs/rock-5-itx-rk3588.h +F: configs/rock-5-itx-rk3588_defconfig +F: arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig new file mode 100644 index 00000000000..bb9f148692a --- /dev/null +++ b/configs/rock-5-itx-rk3588_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-rock-5-itx" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ROCK5B_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5-itx.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 7523c01f777..0f9cb404d93 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -134,6 +134,7 @@ List of mainline supported Rockchip boards: - Generic RK3588S/RK3588 (generic-rk3588) - Indiedroid Nova (nova-rk3588s) - Pine64 QuartzPro64 (quartzpro64-rk3588) + - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) diff --git a/include/configs/rock-5-itx-rk3588.h b/include/configs/rock-5-itx-rk3588.h new file mode 100644 index 00000000000..bc0f9e72bc5 --- /dev/null +++ b/include/configs/rock-5-itx-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Heiko Stuebner + */ + +#ifndef __ROCK_5_ITX_RK3588_H +#define __ROCK_5_ITX_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif /* __ROCK_5_ITX_RK3588_H */ -- cgit v1.3.1