From 0aa2930ca192a8738d1da8222fc6ac21d7c19182 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:13 +0300 Subject: clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- include/k3-clk.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/k3-clk.h (limited to 'include') diff --git a/include/k3-clk.h b/include/k3-clk.h new file mode 100644 index 00000000000..fc84378d03f --- /dev/null +++ b/include/k3-clk.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com + * Tero Kristo + */ + +#ifndef __K3_CLK_H__ +#define __K3_CLK_H__ + +#include + +struct clk *clk_register_ti_pll(const char *name, const char *parent_name, + void __iomem *reg); + +#endif /* __K3_CLK_H__ */ -- cgit v1.2.3