From ee422142f454d54f0ed39a2cbf083ff12e98a3e1 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:20 +0200 Subject: MIPS: add initial infrastructure for Broadcom MIPS SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- include/configs/bmips_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/configs/bmips_common.h (limited to 'include') diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h new file mode 100644 index 00000000000..d2b05d44c8b --- /dev/null +++ b/include/configs/bmips_common.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_COMMON_H +#define __CONFIG_BMIPS_COMMON_H + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0xa0000000 +#define CONFIG_SYS_MEMTEST_END 0xa2000000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#endif /* __CONFIG_BMIPS_COMMON_H */ -- cgit v1.3.1 From e30d2bd40eaed27c5cead1b6e337e66f2b84d30e Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:21 +0200 Subject: MIPS: add support for Broadcom MIPS BCM6358 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6358.dtsi | 98 ++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 18 ++++++- arch/mips/mach-bmips/include/ioremap.h | 45 ++++++++++++++++ include/configs/bmips_bcm6358.h | 30 +++++++++++ 4 files changed, 190 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/brcm,bcm6358.dtsi create mode 100644 arch/mips/mach-bmips/include/ioremap.h create mode 100644 include/configs/bmips_bcm6358.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi new file mode 100644 index 00000000000..48322fb1438 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6358"; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@fffe0100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@fffe0120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@fffe1200 { + compatible = "brcm,bcm6358-mc"; + reg = <0xfffe1200 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 4f4d351f2cc..03cba72f0a4 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -2,7 +2,23 @@ menu "Broadcom MIPS platforms" depends on ARCH_BMIPS config SYS_SOC - default "none" + default "bcm6358" if SOC_BMIPS_BCM6358 + +choice + prompt "Broadcom MIPS SoC select" + +config SOC_BMIPS_BCM6358 + bool "BMIPS BCM6358 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6358 family including BCM6358 and BCM6359. + +endchoice choice prompt "Boot mode" diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h new file mode 100644 index 00000000000..404690e4db3 --- /dev/null +++ b/arch/mips/mach-bmips/include/ioremap.h @@ -0,0 +1,45 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_BMIPS_IOREMAP_H +#define __ASM_MACH_BMIPS_IOREMAP_H + +#include + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_bmips_internal_registers(phys_addr_t offset) +{ +#if defined(CONFIG_SOC_BMIPS_BCM6358) + if (offset >= 0xfffe0000) + return 1; +#endif + + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_bmips_internal_registers(offset)) + return (void __iomem *)offset; + + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_bmips_internal_registers((unsigned long)addr); +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_BMIPS_IOREMAP_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h new file mode 100644 index 00000000000..5d018a34814 --- /dev/null +++ b/include/configs/bmips_bcm6358.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6358_H +#define __CONFIG_BMIPS_BCM6358_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6358_H */ -- cgit v1.3.1 From 4a2b2724a214de764cc9250d85043f32cdd43ab9 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:22 +0200 Subject: MIPS: add BMIPS Huawei HG556a board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/Makefile | 1 + arch/mips/dts/huawei,hg556a.dts | 31 ++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 ++++++++++ board/huawei/hg556a/Kconfig | 12 ++++++++++ board/huawei/hg556a/MAINTAINERS | 6 +++++ board/huawei/hg556a/Makefile | 5 ++++ board/huawei/hg556a/hg556a.c | 7 ++++++ configs/huawei_hg556a_ram_defconfig | 47 +++++++++++++++++++++++++++++++++++++ include/configs/huawei_hg556a.h | 20 ++++++++++++++++ 9 files changed, 141 insertions(+) create mode 100644 arch/mips/dts/huawei,hg556a.dts create mode 100644 board/huawei/hg556a/Kconfig create mode 100644 board/huawei/hg556a/MAINTAINERS create mode 100644 board/huawei/hg556a/Makefile create mode 100644 board/huawei/hg556a/hg556a.c create mode 100644 configs/huawei_hg556a_ram_defconfig create mode 100644 include/configs/huawei_hg556a.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 30fcc2b91e6..1843b773123 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts new file mode 100644 index 00000000000..6775909a03e --- /dev/null +++ b/arch/mips/dts/huawei,hg556a.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "Huawei EchoLife HG556a"; + compatible = "huawei,hg556a", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 03cba72f0a4..0300ae35a8b 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -20,6 +20,16 @@ config SOC_BMIPS_BCM6358 endchoice +choice + prompt "Board select" + +config BOARD_HUAWEI_HG556A + bool "Huawei EchoLife HG556a" + depends on SOC_BMIPS_BCM6358 + select BMIPS_SUPPORTS_BOOT_RAM + +endchoice + choice prompt "Boot mode" @@ -36,4 +46,6 @@ endchoice config BMIPS_SUPPORTS_BOOT_RAM bool +source "board/huawei/hg556a/Kconfig" + endmenu diff --git a/board/huawei/hg556a/Kconfig b/board/huawei/hg556a/Kconfig new file mode 100644 index 00000000000..88622d0e681 --- /dev/null +++ b/board/huawei/hg556a/Kconfig @@ -0,0 +1,12 @@ +if BOARD_HUAWEI_HG556A + +config SYS_BOARD + default "hg556a" + +config SYS_VENDOR + default "huawei" + +config SYS_CONFIG_NAME + default "huawei_hg556a" + +endif diff --git a/board/huawei/hg556a/MAINTAINERS b/board/huawei/hg556a/MAINTAINERS new file mode 100644 index 00000000000..3ead7e4dd8a --- /dev/null +++ b/board/huawei/hg556a/MAINTAINERS @@ -0,0 +1,6 @@ +HUAWEI HG556A BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/huawei/hg556a/ +F: include/configs/huawei_hg556a.h +F: configs/huawei_hg556a_ram_defconfig diff --git a/board/huawei/hg556a/Makefile b/board/huawei/hg556a/Makefile new file mode 100644 index 00000000000..ace0ed3efd9 --- /dev/null +++ b/board/huawei/hg556a/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += hg556a.o diff --git a/board/huawei/hg556a/hg556a.c b/board/huawei/hg556a/hg556a.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/huawei/hg556a/hg556a.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig new file mode 100644 index 00000000000..ca00c4d6756 --- /dev/null +++ b/configs/huawei_hg556a_ram_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_HUAWEI_HG556A=y +CONFIG_CFI_FLASH=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_FLASH=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM6358=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_PROMPT="HG556a # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h new file mode 100644 index 00000000000..ab64518e0b1 --- /dev/null +++ b/include/configs/huawei_hg556a.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 -- cgit v1.3.1 From 6471a225e708f550077d0f6c6c1b9e8773b5e9d6 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:23 +0200 Subject: MIPS: add support for Broadcom MIPS BCM6328 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6328.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 ++++++ include/configs/bmips_bcm6328.h | 25 ++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm6328.dtsi create mode 100644 include/configs/bmips_bcm6328.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi new file mode 100644 index 00000000000..b2872399673 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6328"; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000068 { + compatible = "syscon"; + reg = <0x10000068 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 0300ae35a8b..467ba5bd1c9 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -2,11 +2,23 @@ menu "Broadcom MIPS platforms" depends on ARCH_BMIPS config SYS_SOC + default "bcm6328" if SOC_BMIPS_BCM6328 default "bcm6358" if SOC_BMIPS_BCM6358 choice prompt "Broadcom MIPS SoC select" +config SOC_BMIPS_BCM6328 + bool "BMIPS BCM6328 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6328 family including BCM63281 and BCM63283. + config SOC_BMIPS_BCM6358 bool "BMIPS BCM6358 family" select SUPPORTS_BIG_ENDIAN diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h new file mode 100644 index 00000000000..41c7838a232 --- /dev/null +++ b/include/configs/bmips_bcm6328.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6328_H +#define __CONFIG_BMIPS_BCM6328_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6328_H */ -- cgit v1.3.1 From 0642f485dc7b22e147ec85180af1f524c04b46ce Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:24 +0200 Subject: MIPS: add BMIPS Comtrend AR-5387un board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/Makefile | 1 + arch/mips/dts/comtrend,ar-5387un.dts | 27 ++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 6 +++++ board/comtrend/ar5387un/Kconfig | 12 +++++++++ board/comtrend/ar5387un/MAINTAINERS | 6 +++++ board/comtrend/ar5387un/Makefile | 5 ++++ board/comtrend/ar5387un/ar-5387un.c | 7 ++++++ configs/comtrend_ar5387un_ram_defconfig | 44 +++++++++++++++++++++++++++++++++ include/configs/comtrend_ar5387un.h | 17 +++++++++++++ 9 files changed, 125 insertions(+) create mode 100644 arch/mips/dts/comtrend,ar-5387un.dts create mode 100644 board/comtrend/ar5387un/Kconfig create mode 100644 board/comtrend/ar5387un/MAINTAINERS create mode 100644 board/comtrend/ar5387un/Makefile create mode 100644 board/comtrend/ar5387un/ar-5387un.c create mode 100644 configs/comtrend_ar5387un_ram_defconfig create mode 100644 include/configs/comtrend_ar5387un.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 1843b773123..0805819fa76 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts new file mode 100644 index 00000000000..73f3be457c2 --- /dev/null +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6328.dtsi" + +/ { + model = "Comtrend AR-5387un"; + compatible = "comtrend,ar5387-un", "brcm,bcm6328"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 467ba5bd1c9..e3ffcb7cf59 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -35,6 +35,11 @@ endchoice choice prompt "Board select" +config BOARD_COMTREND_AR5387UN + bool "Comtrend AR-5387un" + depends on SOC_BMIPS_BCM6328 + select BMIPS_SUPPORTS_BOOT_RAM + config BOARD_HUAWEI_HG556A bool "Huawei EchoLife HG556a" depends on SOC_BMIPS_BCM6358 @@ -58,6 +63,7 @@ endchoice config BMIPS_SUPPORTS_BOOT_RAM bool +source "board/comtrend/ar5387un/Kconfig" source "board/huawei/hg556a/Kconfig" endmenu diff --git a/board/comtrend/ar5387un/Kconfig b/board/comtrend/ar5387un/Kconfig new file mode 100644 index 00000000000..45ab7e2844a --- /dev/null +++ b/board/comtrend/ar5387un/Kconfig @@ -0,0 +1,12 @@ +if BOARD_COMTREND_AR5387UN + +config SYS_BOARD + default "ar5387un" + +config SYS_VENDOR + default "comtrend" + +config SYS_CONFIG_NAME + default "comtrend_ar5387un" + +endif diff --git a/board/comtrend/ar5387un/MAINTAINERS b/board/comtrend/ar5387un/MAINTAINERS new file mode 100644 index 00000000000..bcaac64db09 --- /dev/null +++ b/board/comtrend/ar5387un/MAINTAINERS @@ -0,0 +1,6 @@ +COMTREND AR-5387UN BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/comtrend/ar-5387un/ +F: include/configs/comtrend_ar5387un.h +F: configs/comtrend_ar5387un_ram_defconfig diff --git a/board/comtrend/ar5387un/Makefile b/board/comtrend/ar5387un/Makefile new file mode 100644 index 00000000000..9de1cd2ba2d --- /dev/null +++ b/board/comtrend/ar5387un/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ar-5387un.o diff --git a/board/comtrend/ar5387un/ar-5387un.c b/board/comtrend/ar5387un/ar-5387un.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/comtrend/ar5387un/ar-5387un.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig new file mode 100644 index 00000000000..c95a369ec61 --- /dev/null +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_COMTREND_AR5387UN=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM6328=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_NO_FLASH=y +CONFIG_SYS_PROMPT="AR-5387un # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h new file mode 100644 index 00000000000..5d8f968c4d8 --- /dev/null +++ b/include/configs/comtrend_ar5387un.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP -- cgit v1.3.1 From 6a235bb87bfe4a80554c07b2da3679f12167083d Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:25 +0200 Subject: MIPS: add support for Broadcom MIPS BCM63268 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm63268.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 13 ++++++ include/configs/bmips_bcm63268.h | 25 ++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm63268.dtsi create mode 100644 include/configs/bmips_bcm63268.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi new file mode 100644 index 00000000000..3d810473ec6 --- /dev/null +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63268"; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@10000180 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000180 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@100001a0 { + compatible = "brcm,bcm6345-uart"; + reg = <0x100001a0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e3ffcb7cf59..b461b79226f 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -4,6 +4,7 @@ menu "Broadcom MIPS platforms" config SYS_SOC default "bcm6328" if SOC_BMIPS_BCM6328 default "bcm6358" if SOC_BMIPS_BCM6358 + default "bcm63268" if SOC_BMIPS_BCM63268 choice prompt "Broadcom MIPS SoC select" @@ -30,6 +31,18 @@ config SOC_BMIPS_BCM6358 help This supports BMIPS BCM6358 family including BCM6358 and BCM6359. +config SOC_BMIPS_BCM63268 + bool "BMIPS BCM63268 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM63268 family including BCM63168, BCM63169, + BCM63268 and BCM63269. + endchoice choice diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h new file mode 100644 index 00000000000..ac0a6700f7c --- /dev/null +++ b/include/configs/bmips_bcm63268.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM63268_H +#define __CONFIG_BMIPS_BCM63268_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM63268_H */ -- cgit v1.3.1 From 77ca99d1a0d9fd46046d417b4247edb4e1b05d4e Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 25 Apr 2017 00:39:26 +0200 Subject: MIPS: add BMIPS Comtrend VR-3032u board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/Makefile | 1 + arch/mips/dts/comtrend,vr-3032u.dts | 27 +++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 6 +++++ board/comtrend/vr3032u/Kconfig | 12 ++++++++++ board/comtrend/vr3032u/MAINTAINERS | 6 +++++ board/comtrend/vr3032u/Makefile | 5 ++++ board/comtrend/vr3032u/vr-3032u.c | 7 ++++++ configs/comtrend_vr3032u_ram_defconfig | 44 ++++++++++++++++++++++++++++++++++ include/configs/comtrend_vr3032u.h | 17 +++++++++++++ 9 files changed, 125 insertions(+) create mode 100644 arch/mips/dts/comtrend,vr-3032u.dts create mode 100644 board/comtrend/vr3032u/Kconfig create mode 100644 board/comtrend/vr3032u/MAINTAINERS create mode 100644 board/comtrend/vr3032u/Makefile create mode 100644 board/comtrend/vr3032u/vr-3032u.c create mode 100644 configs/comtrend_vr3032u_ram_defconfig create mode 100644 include/configs/comtrend_vr3032u.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 0805819fa76..4c02c48c111 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb +dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts new file mode 100644 index 00000000000..67153040316 --- /dev/null +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm63268.dtsi" + +/ { + model = "Comtrend VR-3032u"; + compatible = "comtrend,vr-3032u", "brcm,bcm63268"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index b461b79226f..d1684486a85 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -53,6 +53,11 @@ config BOARD_COMTREND_AR5387UN depends on SOC_BMIPS_BCM6328 select BMIPS_SUPPORTS_BOOT_RAM +config BOARD_COMTREND_VR3032U + bool "Comtrend VR-3032u board" + depends on SOC_BMIPS_BCM63268 + select BMIPS_SUPPORTS_BOOT_RAM + config BOARD_HUAWEI_HG556A bool "Huawei EchoLife HG556a" depends on SOC_BMIPS_BCM6358 @@ -77,6 +82,7 @@ config BMIPS_SUPPORTS_BOOT_RAM bool source "board/comtrend/ar5387un/Kconfig" +source "board/comtrend/vr3032u/Kconfig" source "board/huawei/hg556a/Kconfig" endmenu diff --git a/board/comtrend/vr3032u/Kconfig b/board/comtrend/vr3032u/Kconfig new file mode 100644 index 00000000000..6f552cf22a0 --- /dev/null +++ b/board/comtrend/vr3032u/Kconfig @@ -0,0 +1,12 @@ +if BOARD_COMTREND_VR3032U + +config SYS_BOARD + default "vr3032u" + +config SYS_VENDOR + default "comtrend" + +config SYS_CONFIG_NAME + default "comtrend_vr3032u" + +endif diff --git a/board/comtrend/vr3032u/MAINTAINERS b/board/comtrend/vr3032u/MAINTAINERS new file mode 100644 index 00000000000..833d7da4afa --- /dev/null +++ b/board/comtrend/vr3032u/MAINTAINERS @@ -0,0 +1,6 @@ +COMTREND VR-3032U BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/comtrend/vr-3032u/ +F: include/configs/comtrend_vr-3032u.h +F: configs/comtrend_vr3032u_ram_defconfig diff --git a/board/comtrend/vr3032u/Makefile b/board/comtrend/vr3032u/Makefile new file mode 100644 index 00000000000..9e6203132f5 --- /dev/null +++ b/board/comtrend/vr3032u/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += vr-3032u.o diff --git a/board/comtrend/vr3032u/vr-3032u.c b/board/comtrend/vr3032u/vr-3032u.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/comtrend/vr3032u/vr-3032u.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig new file mode 100644 index 00000000000..c62ef0c1703 --- /dev/null +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_COMTREND_VR3032U=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM63268=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_NO_FLASH=y +CONFIG_SYS_PROMPT="VR-3032u # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h new file mode 100644 index 00000000000..d45f8b32daf --- /dev/null +++ b/include/configs/comtrend_vr3032u.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP -- cgit v1.3.1 From a186d2630bd92d952c953f24c412b492265289ff Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 20:11:32 +0200 Subject: mips: bmips: add NeufBox 4 (Sercomm) board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This serves as an example for bcm6358-leds. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/sfr,nb4-ser.dts | 93 +++++++++++++++++++++++++++++++++++++++ board/sfr/nb4_ser/Kconfig | 12 +++++ board/sfr/nb4_ser/MAINTAINERS | 6 +++ board/sfr/nb4_ser/Makefile | 5 +++ board/sfr/nb4_ser/nb4-ser.c | 7 +++ configs/sfr_nb4-ser_ram_defconfig | 52 ++++++++++++++++++++++ include/configs/sfr_nb4_ser.h | 20 +++++++++ 7 files changed, 195 insertions(+) create mode 100644 arch/mips/dts/sfr,nb4-ser.dts create mode 100644 board/sfr/nb4_ser/Kconfig create mode 100644 board/sfr/nb4_ser/MAINTAINERS create mode 100644 board/sfr/nb4_ser/Makefile create mode 100644 board/sfr/nb4_ser/nb4-ser.c create mode 100644 configs/sfr_nb4-ser_ram_defconfig create mode 100644 include/configs/sfr_nb4_ser.h (limited to 'include') diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts new file mode 100644 index 00000000000..f2092e9f999 --- /dev/null +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "SFR NeufBox 4 (Sercomm) Board"; + compatible = "sfr,nb4-ser", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + traffic_white { + label = "NB4-SER:white:traffic"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + service_blue { + label = "NB4-SER:blue:service"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + }; + + wifi_white { + label = "NB4-SER:white:wifi"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + service_red { + label = "NB4-SER:red:service"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + service_green { + label = "NB4-SER:green:service"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,clk-div = <1>; + + led@0 { + reg = <0>; + active-low; + label = "NB4-SER:white:alarm"; + }; + + led@2 { + reg = <2>; + active-low; + label = "NB4-SER:white:tv"; + }; + + led@3 { + reg = <3>; + active-low; + label = "NB4-SER:white:tel"; + }; + + led@4 { + reg = <4>; + active-low; + label = "NB4-SER:white:adsl"; + }; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/board/sfr/nb4_ser/Kconfig b/board/sfr/nb4_ser/Kconfig new file mode 100644 index 00000000000..78aefb547f0 --- /dev/null +++ b/board/sfr/nb4_ser/Kconfig @@ -0,0 +1,12 @@ +if BOARD_SFR_NB4_SER + +config SYS_BOARD + default "nb4_ser" + +config SYS_VENDOR + default "sfr" + +config SYS_CONFIG_NAME + default "sfr_nb4_ser" + +endif diff --git a/board/sfr/nb4_ser/MAINTAINERS b/board/sfr/nb4_ser/MAINTAINERS new file mode 100644 index 00000000000..bf80267f046 --- /dev/null +++ b/board/sfr/nb4_ser/MAINTAINERS @@ -0,0 +1,6 @@ +SFR NEUFBOX 4 SERCOMM BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/sfr/nb4_ser/ +F: include/configs/sfr_nb4_ser.h +F: configs/sfr_nb4-ser_ram_defconfig diff --git a/board/sfr/nb4_ser/Makefile b/board/sfr/nb4_ser/Makefile new file mode 100644 index 00000000000..f3b1404f7c5 --- /dev/null +++ b/board/sfr/nb4_ser/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += nb4-ser.o diff --git a/board/sfr/nb4_ser/nb4-ser.c b/board/sfr/nb4_ser/nb4-ser.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/sfr/nb4_ser/nb4-ser.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig new file mode 100644 index 00000000000..8b885e328b4 --- /dev/null +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_GPIO=y +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_SFR_NB4_SER=y +CONFIG_CFI_FLASH=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_FLASH=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_BCM6358=y +CONFIG_LED_GPIO=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM6358=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_PROMPT="NB4-SER # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h new file mode 100644 index 00000000000..ab64518e0b1 --- /dev/null +++ b/include/configs/sfr_nb4_ser.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 -- cgit v1.3.1 From 70789bd2a5d885671f5256b5c2717fec30ac3fe7 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 20:13:02 +0200 Subject: mips: bmips: add bcm6345-clk driver support for BCM6358 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6358.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6358-clock.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index edd0002c9b5..369c2401891 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "skeleton.dtsi" @@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; }; pflash: nor@1e000000 { diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h new file mode 100644 index 00000000000..ff2232123b9 --- /dev/null +++ b/include/dt-bindings/clock/bcm6358-clock.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +#define __DT_BINDINGS_CLOCK_BCM6358_H + +#define BCM6358_CLK_ENET 4 +#define BCM6358_CLK_ADSL 5 +#define BCM6358_CLK_PCM 8 +#define BCM6358_CLK_SPI 9 +#define BCM6358_CLK_USBS 10 +#define BCM6358_CLK_SAR 11 +#define BCM6358_CLK_EMUSB 17 +#define BCM6358_CLK_ENET0 18 +#define BCM6358_CLK_ENET1 19 +#define BCM6358_CLK_USBSU 20 +#define BCM6358_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ -- cgit v1.3.1 From 5b14e13c24f6a26fc30147404af8c570530f0a8d Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 20:13:03 +0200 Subject: mips: bmips: add bcm6345-clk driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6328.dtsi | 7 +++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/clock/bcm6328-clock.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index a5b43ae6e33..6b5c5dd7342 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "skeleton.dtsi" @@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; }; ubus { diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h new file mode 100644 index 00000000000..5d0fc115e7e --- /dev/null +++ b/include/dt-bindings/clock/bcm6328-clock.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +#define __DT_BINDINGS_CLOCK_BCM6328_H + +#define BCM6328_CLK_PHYMIPS 0 +#define BCM6328_CLK_ADSL_QPROC 1 +#define BCM6328_CLK_ADSL_AFE 2 +#define BCM6328_CLK_ADSL 3 +#define BCM6328_CLK_MIPS 4 +#define BCM6328_CLK_SAR 5 +#define BCM6328_CLK_PCM 6 +#define BCM6328_CLK_USBD 7 +#define BCM6328_CLK_USBH 8 +#define BCM6328_CLK_HSSPI 9 +#define BCM6328_CLK_PCIE 10 +#define BCM6328_CLK_ROBOSW 11 + +#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ -- cgit v1.3.1 From 969ebdb9306e3aa731fb96be64f5f96e9457b234 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 20:13:04 +0200 Subject: mips: bmips: add bcm6345-clk driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm63268.dtsi | 13 ++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/bcm63268-clock.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 11c67291679..4d020246cfb 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "skeleton.dtsi" @@ -43,6 +44,18 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + timer_clk: timer-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + }; }; ubus { diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h new file mode 100644 index 00000000000..23818da1a0e --- /dev/null +++ b/include/dt-bindings/clock/bcm63268-clock.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +#define __DT_BINDINGS_CLOCK_BCM63268_H + +#define BCM63268_CLK_GLESS 0 +#define BCM63268_CLK_VDSL_QPROC 1 +#define BCM63268_CLK_VDSL_AFE 2 +#define BCM63268_CLK_VDSL 3 +#define BCM63268_CLK_MIPS 4 +#define BCM63268_CLK_WLAN_OCP 5 +#define BCM63268_CLK_DECT 6 +#define BCM63268_CLK_FAP0 7 +#define BCM63268_CLK_FAP1 8 +#define BCM63268_CLK_SAR 9 +#define BCM63268_CLK_ROBOSW 10 +#define BCM63268_CLK_PCM 11 +#define BCM63268_CLK_USBD 12 +#define BCM63268_CLK_USBH 13 +#define BCM63268_CLK_IPSEC 14 +#define BCM63268_CLK_SPI 15 +#define BCM63268_CLK_HSSPI 16 +#define BCM63268_CLK_PCIE 17 +#define BCM63268_CLK_PHYMIPS 18 +#define BCM63268_CLK_GMAC 19 +#define BCM63268_CLK_NAND 20 +#define BCM63268_CLK_TBUS 27 +#define BCM63268_CLK_ROBOSW250 31 + +#define BCM63268_TCLK_EPHY1 0 +#define BCM63268_TCLK_EPHY2 1 +#define BCM63268_TCLK_EPHY3 2 +#define BCM63268_TCLK_GPHY 3 +#define BCM63268_TCLK_DSL 4 +#define BCM63268_TCLK_WO_EPHY 5 +#define BCM63268_TCLK_WO_DSL 6 +#define BCM63268_TCLK_FAP1 11 +#define BCM63268_TCLK_FAP2 15 +#define BCM63268_TCLK_UTO_50 16 +#define BCM63268_TCLK_UTO_EXT 17 +#define BCM63268_TCLK_USB_REF 18 +#define BCM63268_TCLK_SW_RST 29 +#define BCM63268_TCLK_HW_RST 30 +#define BCM63268_TCLK_POR_RST 31 + +#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ -- cgit v1.3.1 From efe8b9d0122e5ab25f7284a36a716cd6610e8ad4 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 3 May 2017 15:10:22 +0200 Subject: mips: bmips: add bcm6345-rst driver support for BCM6358 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 resets. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6358.dtsi | 7 +++++++ include/dt-bindings/reset/bcm6358-reset.h | 21 +++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6358-reset.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 369c2401891..df75988c823 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -80,6 +81,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@fffe0034 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0034 0x4>; + #reset-cells = <1>; + }; + gpio1: gpio-controller@fffe0080 { compatible = "brcm,bcm6345-gpio"; reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h new file mode 100644 index 00000000000..4b3cff3e491 --- /dev/null +++ b/include/dt-bindings/reset/bcm6358-reset.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6358_H +#define __DT_BINDINGS_RESET_BCM6358_H + +#define BCM6358_RST_SPI 0 +#define BCM6358_RST_ENET 2 +#define BCM6358_RST_MPI 3 +#define BCM6358_RST_EPHY 6 +#define BCM6358_RST_SAR 7 +#define BCM6358_RST_USBH 12 +#define BCM6358_RST_PCM 13 +#define BCM6358_RST_ADSL 14 + +#endif /* __DT_BINDINGS_RESET_BCM6358_H */ -- cgit v1.3.1 From 78118211fb61df2f6427dc0ea7a65c97c20b3d11 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 3 May 2017 15:10:23 +0200 Subject: mips: bmips: add bcm6345-rst driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6328.dtsi | 7 +++++++ include/dt-bindings/reset/bcm6328-reset.h | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6328-reset.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 6b5c5dd7342..9b76a2322ce 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -58,6 +59,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + pll_cntl: syscon@10000068 { compatible = "syscon"; reg = <0x10000068 0x4>; diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h new file mode 100644 index 00000000000..c144ad2a787 --- /dev/null +++ b/include/dt-bindings/reset/bcm6328-reset.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6328_H +#define __DT_BINDINGS_RESET_BCM6328_H + +#define BCM6328_RST_SPI 0 +#define BCM6328_RST_EPHY 1 +#define BCM6328_RST_SAR 2 +#define BCM6328_RST_ENETSW 3 +#define BCM6328_RST_USBS 4 +#define BCM6328_RST_USBH 5 +#define BCM6328_RST_PCM 6 +#define BCM6328_RST_PCIE_CORE 7 +#define BCM6328_RST_PCIE 8 +#define BCM6328_RST_PCIE_EXT 9 +#define BCM6328_RST_PCIE_HARD 10 + +#endif /* __DT_BINDINGS_RESET_BCM6328_H */ -- cgit v1.3.1 From 02bb1fa09ed4caec6d2aa6565fac62087016b306 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 3 May 2017 15:10:24 +0200 Subject: mips: bmips: add bcm6345-rst driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm63268.dtsi | 7 +++++++ include/dt-bindings/reset/bcm63268-reset.h | 32 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 include/dt-bindings/reset/bcm63268-reset.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 4d020246cfb..8ff13c10fe1 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -76,6 +77,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + gpio1: gpio-controller@100000c0 { compatible = "brcm,bcm6345-gpio"; reg = <0x100000c0 0x4>, <0x100000c8 0x4>; diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h new file mode 100644 index 00000000000..1373884b361 --- /dev/null +++ b/include/dt-bindings/reset/bcm63268-reset.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM63268_H +#define __DT_BINDINGS_RESET_BCM63268_H + +#define BCM63268_RST_SPI 0 +#define BCM63268_RST_IPSEC 1 +#define BCM63268_RST_EPHY 2 +#define BCM63268_RST_SAR 3 +#define BCM63268_RST_ENETSW 4 +#define BCM63268_RST_USBS 5 +#define BCM63268_RST_USBH 6 +#define BCM63268_RST_PCM 7 +#define BCM63268_RST_PCIE_CORE 8 +#define BCM63268_RST_PCIE 9 +#define BCM63268_RST_PCIE_EXT 10 +#define BCM63268_RST_WLAN_SHIM 11 +#define BCM63268_RST_DDR_PHY 12 +#define BCM63268_RST_FAP0 13 +#define BCM63268_RST_WLAN_UBUS 14 +#define BCM63268_RST_DECT 15 +#define BCM63268_RST_FAP1 16 +#define BCM63268_RST_PCIE_HARD 17 +#define BCM63268_RST_GPHY 18 + +#endif /* __DT_BINDINGS_RESET_BCM63268_H */ -- cgit v1.3.1 From 9a5cb22fda01327384e8dabb775cfb2615dbbe10 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 20:28:37 +0200 Subject: mips: bmips: add bcm6328-power-domain driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas --- arch/mips/dts/brcm,bcm6328.dtsi | 7 +++++++ .../dt-bindings/power-domain/bcm6328-power-domain.h | 21 +++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/power-domain/bcm6328-power-domain.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 9b76a2322ce..4adc83fcb43 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include "skeleton.dtsi" @@ -111,6 +112,12 @@ status = "disabled"; }; + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x1000>; diff --git a/include/dt-bindings/power-domain/bcm6328-power-domain.h b/include/dt-bindings/power-domain/bcm6328-power-domain.h new file mode 100644 index 00000000000..006806c9358 --- /dev/null +++ b/include/dt-bindings/power-domain/bcm6328-power-domain.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6328_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6328_H + +#define BCM6328_PWR_ADSL2_MIPS 0 +#define BCM6328_PWR_ADSL2_PHY 1 +#define BCM6328_PWR_ADSL2_AFE 2 +#define BCM6328_PWR_SAR 3 +#define BCM6328_PWR_PCM 4 +#define BCM6328_PWR_USBD 5 +#define BCM6328_PWR_USBH 6 +#define BCM6328_PWR_PCIE 7 +#define BCM6328_PWR_ROBOSW 8 +#define BCM6328_PWR_EPHY 9 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6328_H */ -- cgit v1.3.1 From a1b5e5e7c164868cff1b5c53a8ed70640512b42e Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sun, 7 May 2017 20:28:38 +0200 Subject: mips: bmips: add bcm6328-power-domain driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas --- arch/mips/dts/brcm,bcm63268.dtsi | 7 ++++++ .../power-domain/bcm63268-power-domain.h | 25 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/power-domain/bcm63268-power-domain.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 8ff13c10fe1..3d0f8e0ea14 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include "skeleton.dtsi" @@ -118,6 +119,12 @@ status = "disabled"; }; + periph_pwr: power-controller@1000184c { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x1000184c 0x4>; + #power-domain-cells = <1>; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>; diff --git a/include/dt-bindings/power-domain/bcm63268-power-domain.h b/include/dt-bindings/power-domain/bcm63268-power-domain.h new file mode 100644 index 00000000000..d9eba4418e5 --- /dev/null +++ b/include/dt-bindings/power-domain/bcm63268-power-domain.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM63268_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM63268_H + +#define BCM63268_PWR_SAR 0 +#define BCM63268_PWR_IPSEC 1 +#define BCM63268_PWR_MIPS 2 +#define BCM63268_PWR_DECT 3 +#define BCM63268_PWR_USBH 4 +#define BCM63268_PWR_USBD 5 +#define BCM63268_PWR_ROBOSW 6 +#define BCM63268_PWR_PCM 7 +#define BCM63268_PWR_PERIPH 8 +#define BCM63268_PWR_VDSL_PHY 9 +#define BCM63268_PWR_VDSL_MIPS 10 +#define BCM63268_PWR_FAP 11 +#define BCM63268_PWR_PCIE 12 +#define BCM63268_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM63268_H */ -- cgit v1.3.1