From 97b17ecae8161bbe259d22fb50b39e549971e22a Mon Sep 17 00:00:00 2001 From: Brian Sune Date: Wed, 28 Jan 2026 22:18:15 +0800 Subject: Add CoreCourse socfpga Board - AC501 CoreCourse Altera GEN5 Cyclone V board do support different size and formfactor. Now introducing AC501 C5 to mainstream u-boot This is a UBGA-484 based board with basic feature. More info on [1] [1] https://corecourse.cn/forum.php?mod=viewthread&tid=27704&highlight=AC501 Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee --- include/configs/socfpga_ac501soc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/configs/socfpga_ac501soc.h (limited to 'include') diff --git a/include/configs/socfpga_ac501soc.h b/include/configs/socfpga_ac501soc.h new file mode 100644 index 00000000000..703520e7cb8 --- /dev/null +++ b/include/configs/socfpga_ac501soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune + */ +#ifndef __CONFIG_CORESOURCE_AC501SOC_H__ +#define __CONFIG_CORESOURCE_AC501SOC_H__ + +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_CORESOURCE_AC501SOC_H__ */ -- cgit v1.2.3 From 3d1dc5b79fe80b16eae2738e7f753752befa5881 Mon Sep 17 00:00:00 2001 From: Brian Sune Date: Wed, 28 Jan 2026 22:18:16 +0800 Subject: Add CoreCourse socfpga Board - AC550 CoreCourse Altera GEN5 Cyclone V board do support different size and formfactor. Now introducing AC550 C5 to mainstream u-boot This is a more complex and unified board with feature. More info on [1] [1] https://corecourse.cn/forum.php?mod=viewthread&tid=29788&extra=page%3D1 Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee --- include/configs/socfpga_ac550soc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/configs/socfpga_ac550soc.h (limited to 'include') diff --git a/include/configs/socfpga_ac550soc.h b/include/configs/socfpga_ac550soc.h new file mode 100644 index 00000000000..48e02d61dc5 --- /dev/null +++ b/include/configs/socfpga_ac550soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune + */ +#ifndef __CONFIG_CORESOURCE_AC550SOC_H__ +#define __CONFIG_CORESOURCE_AC550SOC_H__ + +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_CORESOURCE_AC550SOC_H__ */ -- cgit v1.2.3 From 62f7a94602094617ac384839ed695c2906893a88 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Fri, 13 Feb 2026 20:27:23 +0800 Subject: Replace TARGET namespace and cleanup properly TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile --- include/configs/socfpga_common.h | 4 ++-- include/configs/socfpga_soc64_common.h | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2acfdc7df4a..36d6bfb3d03 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -11,10 +11,10 @@ * Memory configurations */ #define PHYS_SDRAM_1 0x0 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 3d09a06f63e..4d333c63ad9 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -41,7 +41,7 @@ /* * U-Boot run time memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_SYS_INIT_RAM_ADDR 0x0 #define CFG_SYS_INIT_RAM_SIZE 0x80000 #else @@ -118,7 +118,7 @@ #include -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ @@ -182,7 +182,7 @@ "smc_fid_wr=0xC2000008\0" \ "smc_fid_upd=0xC2000009\0 " \ BOOTENV -#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ +#endif /*#IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)*/ #else @@ -245,7 +245,7 @@ /* * External memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0x80000000 @@ -270,7 +270,7 @@ /* * L4 Watchdog */ -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) -- cgit v1.2.3