From 21871138b7686b36dd8ae97cab5dc1e9c5c6e183 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 20 Jul 2015 20:49:59 +0300 Subject: arm: rmobile: Add Stout board support Stout is an entry level development board based on R-Car H2 SoC (R8A7790) This commit supports the following peripherals: - SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD Signed-off-by: Vladimir Barinov Signed-off-by: Nobuhiro Iwamatsu --- include/configs/stout.h | 112 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 include/configs/stout.h (limited to 'include') diff --git a/include/configs/stout.h b/include/configs/stout.h new file mode 100644 index 00000000000..87ea5309480 --- /dev/null +++ b/include/configs/stout.h @@ -0,0 +1,112 @@ +/* + * include/configs/stout.h + * This file is Stout board configuration. + * + * Copyright (C) 2015 Renesas Electronics Europe GmbH + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __STOUT_H +#define __STOUT_H + +#undef DEBUG +#define CONFIG_R8A7790 +#define CONFIG_RMOBILE_BOARD_STRING "Stout" + +#include "rcar-gen2-common.h" + +/* #define CONFIG_BOARD_LATE_INIT */ + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0xB0000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE8080000 +#endif + +/* STACK */ +#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_SCIF_A + +/* SPI */ +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_RCAR +#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 +#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) +#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) +#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF, SCIFA0 */ +#define CONFIG_SMSTP2_ENA 0x00002010 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 + +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + +#endif /* __STOUT_H */ -- cgit v1.3.1 From 6312e9aab8672a06caf5cbd7fd88b620d7122949 Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Tue, 25 Aug 2015 13:55:41 +0200 Subject: board/BuR: simplify default IP-setup on B&R boards. To simplify and having a common default IP-setup on all B&R boards we introduce an environment variable "brdefaultip" which does following. Test if ${ipaddr} is empty, if yes it set's up some defaults: - ipaddr : 192.168.60.1 - netmask : 255.255.255.0 - gatewayip: 192.168.60.254 - serverip : 192.168.60.254 This environment is ran from CONFIG_PREBOOT. All other "tricks" are dropped. Signed-off-by: Hannes Schmelzer Reviewed-by: Tom Rini Acked-by: Joe Hershberger --- board/BuR/kwb/board.c | 10 ---------- include/configs/bur_am335x_common.h | 12 +++++------- 2 files changed, 5 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 640aca4cdec..039ec207c26 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -283,16 +283,6 @@ int board_late_init(void) } /* setup vxworks bootline */ char *vxworksbootline = (char *)VXWORKS_BOOTLINE; - - /* setup default IP, in case if there is nothing in environment */ - if (!getenv("ipaddr")) { - setenv("ipaddr", "192.168.60.1"); - setenv("netmask", "255.255.255.0"); - setenv("serverip", "192.168.60.254"); - setenv("gatewayip", "192.168.60.254"); - puts("net: had no IP! made default setup.\n"); - } - sprintf(vxworksbootline, "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x", DEFAULT_BOOTLINE, diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 838ef1f00a2..c6960920b2b 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,18 +14,16 @@ /* ------------------------------------------------------------------------- */ #define BUR_COMMON_ENV \ "usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \ -"defaultip=192.168.60.253\0" \ -"defaultsip=192.168.60.254\0" \ +"brdefaultip=if test -r ${ipaddr}; then; else" \ +" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ +" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ "netconsole=echo switching to network console ...; " \ -"if dhcp; then setenv ncip ${serverip}; " \ -"else " \ -"setenv ncip 192.168.60.254; setenv serverip 192.168.60.254; " \ -"setenv gatewayip 192.168.60.254; setenv ipaddr 192.168.60.1; " \ -"fi; " \ +"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ "setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ "setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ "setenv stdout nc;setenv stdin nc;setenv stderr nc\0" +#define CONFIG_PREBOOT "run brdefaultip" #define CONFIG_CMD_TIME #define CONFIG_SYS_GENERIC_BOARD -- cgit v1.3.1 From 8ebaaed22b1d0d9dfa60d7e7e69b8628a8a34245 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 28 Aug 2015 13:35:06 +0530 Subject: ti_omap4_common: use ext4 fs as default. All TI SoCs expect filesystem to be ext4, omap4_common is the only one with ext3. move omap4 to ext4 so that we can start consolidating MMC arguments. Signed-off-by: Lokesh Vutla --- include/configs/ti_omap4_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 2eaa3b61b4c..6139246daa2 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -92,7 +92,7 @@ "vram=16M\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "vram=${vram} " \ "root=${mmcroot} " \ -- cgit v1.3.1 From 85d17be374678ec37fd1e55db994a942e400dc80 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 28 Aug 2015 13:35:07 +0530 Subject: ti_armv7_common: env: Consolidate MMC args Define default mmc args in ti_armv7_common.h so that all TI platforms can reuse. Reported-by: Yan Liu Signed-off-by: Lokesh Vutla --- include/configs/am335x_evm.h | 10 ++-------- include/configs/am43xx_evm.h | 10 ++-------- include/configs/ti_armv7_common.h | 8 ++++++++ include/configs/ti_omap4_common.h | 12 +++--------- include/configs/ti_omap5_common.h | 11 ++--------- 5 files changed, 17 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e89c49e1e3a..3cf768e662d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -70,6 +70,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "boot_fdt=try\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ @@ -80,15 +81,8 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "spiroot=/dev/mtdblock4 rw\0" \ "spirootfstype=jffs2\0" \ "spisrcaddr=0xe0000\0" \ @@ -112,7 +106,7 @@ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcloados=run mmcargs; " \ + "mmcloados=run args_mmc; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ "bootz ${loadaddr} - ${fdtaddr}; " \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 15fa3e3fece..d868442acb5 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -216,6 +216,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ @@ -225,18 +226,11 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ "usbroot=/dev/sda2 rw\0" \ "usbrootfstype=ext4 rootwait\0" \ "usbdev=0\0" \ "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "usbargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${usbroot} " \ @@ -268,7 +262,7 @@ "if run loadimage; then " \ "run loadfdt; " \ "echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi;\0" \ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 18fca02c4c3..1a4b6d9900a 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -58,6 +58,14 @@ "ramdisk_addr_r=0x88080000\0" \ "bootm_size=0x10000000\0" +#define DEFAULT_MMC_TI_ARGS \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "args_mmc=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" + /* * Default to a quick boot delay. */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 6139246daa2..1cd7dae85b3 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -83,6 +83,7 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "console=ttyO2,115200n8\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ @@ -90,13 +91,6 @@ "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ @@ -106,10 +100,10 @@ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootz ${loadaddr} - ${fdtaddr}\0" \ "uimageboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootm ${loadaddr}\0" \ "findfdt="\ "if test $board_name = sdp4430; then " \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 1c1f8c0830d..189ea7e9140 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -70,6 +70,7 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "console=" CONSOLEDEV ",115200n8\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ @@ -80,14 +81,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ "dofastboot=0\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ @@ -110,7 +103,7 @@ "if run loadimage; then " \ "run loadfdt; " \ "echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi;\0" \ -- cgit v1.3.1 From 437bc42e7ff930dc4d4bd47199d2e823cf84bf4c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 28 Aug 2015 13:35:08 +0530 Subject: ti_armv7_common: env: Use partuuid for detecting mmc root fs Linux kernel can enumerate mmc sd as either mmcblk0 or mmcblk1. But u-boot default environment assumes that sd always populates as mmcblk0. With this the root fs is not being mounted when mmc sd is enumerated as mmcblk1. So use partuuid to update root= option in default environment. Reported-by: Yan Liu Signed-off-by: Lokesh Vutla --- include/configs/ti_armv7_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1a4b6d9900a..6dc65158994 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -61,9 +61,10 @@ #define DEFAULT_MMC_TI_ARGS \ "mmcdev=0\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "args_mmc=setenv bootargs console=${console} " \ + "finduuid=part uuid mmc 0:2 uuid\0" \ + "args_mmc=run finduuid;setenv bootargs console=${console} " \ "${optargs} " \ - "root=${mmcroot} " \ + "root=PARTUUID=${uuid} rw " \ "rootfstype=${mmcrootfstype}\0" /* -- cgit v1.3.1 From 679d4456e97bfe96a45e8ec36758b579ba9a46c3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:18:55 -0600 Subject: arm: Remove balloon3 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - arch/arm/include/asm/mach-types.h | 13 -- board/balloon3/Kconfig | 9 -- board/balloon3/MAINTAINERS | 6 - board/balloon3/Makefile | 9 -- board/balloon3/balloon3.c | 221 ---------------------------------- configs/balloon3_defconfig | 6 - include/configs/balloon3.h | 242 -------------------------------------- 8 files changed, 511 deletions(-) delete mode 100644 board/balloon3/Kconfig delete mode 100644 board/balloon3/MAINTAINERS delete mode 100644 board/balloon3/Makefile delete mode 100644 board/balloon3/balloon3.c delete mode 100644 configs/balloon3_defconfig delete mode 100644 include/configs/balloon3.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8085a24de2e..a501f158347 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -662,10 +662,6 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL -config TARGET_BALLOON3 - bool "Support balloon3" - select CPU_PXA - config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -809,7 +805,6 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" -source "board/balloon3/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index e72184bd948..b1caa16928c 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -197,7 +197,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_SMDK2412 1009 #define MACH_TYPE_SMDK2413 1022 #define MACH_TYPE_AML_M5900 1024 -#define MACH_TYPE_BALLOON3 1029 #define MACH_TYPE_ECBAT91 1072 #define MACH_TYPE_ONEARM 1075 #define MACH_TYPE_SMDK2443 1084 @@ -3332,18 +3331,6 @@ extern unsigned int __machine_arch_type; # define machine_is_aml_m5900() (0) #endif -#ifdef CONFIG_MACH_BALLOON3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON3 -# endif -# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -#else -# define machine_is_balloon3() (0) -#endif - #ifdef CONFIG_MACH_ECBAT91 # ifdef machine_arch_type # undef machine_arch_type diff --git a/board/balloon3/Kconfig b/board/balloon3/Kconfig deleted file mode 100644 index 53b7a9a5c7e..00000000000 --- a/board/balloon3/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_BALLOON3 - -config SYS_BOARD - default "balloon3" - -config SYS_CONFIG_NAME - default "balloon3" - -endif diff --git a/board/balloon3/MAINTAINERS b/board/balloon3/MAINTAINERS deleted file mode 100644 index df9a5bbcfaa..00000000000 --- a/board/balloon3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BALLOON3 BOARD -M: Marek Vasut -S: Maintained -F: board/balloon3/ -F: include/configs/balloon3.h -F: configs/balloon3_defconfig diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile deleted file mode 100644 index d7fb5e036e4..00000000000 --- a/board/balloon3/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Balloon3 Support -# -# Copyright (C) 2010 Marek Vasut -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := balloon3.o diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c deleted file mode 100644 index 458d90c8715..00000000000 --- a/board/balloon3/balloon3.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Balloon3 Support - * - * Copyright (C) 2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void balloon3_init_fpga(void); - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of balloon3 */ - gd->bd->bi_arch_number = MACH_TYPE_BALLOON3; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Init the FPGA */ - balloon3_init_fpga(); - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -} - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (readl(UHCHR) & UHCHR_FSBIR) - ; - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); - writel(readl(UHCRHDA) | 0x100, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - - return; -} -#endif - -#if defined(CONFIG_FPGA) -/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */ -int fpga_pgm_fn(int nassert, int nflush, int cookie) -{ - if (nassert) - writel(0x80, GPCR3); - else - writel(0x80, GPSR3); - if (nflush) - writel(0x100, GPCR3); - else - writel(0x100, GPSR3); - return nassert; -} - -/* Check GPIO83 -- INITB */ -int fpga_init_fn(int cookie) -{ - return !(readl(GPLR2) & 0x80000); -} - -/* Check GPIO84 -- BUSY */ -int fpga_busy_fn(int cookie) -{ - return !(readl(GPLR2) & 0x100000); -} - -/* Check GPIO111 -- DONE */ -int fpga_done_fn(int cookie) -{ - return readl(GPLR3) & 0x8000; -} - -/* Configure GPIO104 as GPIO and deassert it */ -int fpga_pre_config_fn(int cookie) -{ - writel(readl(GAFR3_L) & ~0x30000, GAFR3_L); - writel(0x100, GPCR3); - return 0; -} - -/* Configure GPIO104 as nSKTSEL */ -int fpga_post_config_fn(int cookie) -{ - writel(readl(GAFR3_L) | 0x10000, GAFR3_L); - return 0; -} - -/* Toggle RDnWR */ -int fpga_wr_fn(int nassert_write, int flush, int cookie) -{ - udelay(1000); - - if (nassert_write) - writel(0x100, GPCR3); - else - writel(0x100, GPSR3); - - return nassert_write; -} - -/* Write program to the FPGA */ -int fpga_wdata_fn(uchar data, int flush, int cookie) -{ - writeb(data, 0x10f00000); - return 0; -} - -/* Toggle Clock pin -- NO-OP */ -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - return assert_clk; -} - -/* Toggle ChipSelect pin -- NO-OP */ -int fpga_cs_fn(int assert_clk, int flush, int cookie) -{ - return assert_clk; -} - -xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - NULL, /* err */ - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - NULL, /* rdata */ - fpga_wdata_fn, - fpga_busy_fn, - NULL, /* abort */ - fpga_post_config_fn, -}; - -xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, - (void *)&balloon3_fpga_fns, 0); - -/* Initialize the FPGA */ -void balloon3_init_fpga(void) -{ - fpga_init(); - fpga_add(fpga_xilinx, &fpga); -} -#else -void balloon3_init_fpga(void) {} -#endif /* CONFIG_FPGA */ diff --git a/configs/balloon3_defconfig b/configs/balloon3_defconfig deleted file mode 100644 index bf524ce8687..00000000000 --- a/configs/balloon3_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BALLOON3=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h deleted file mode 100644 index 124a7663d60..00000000000 --- a/include/configs/balloon3.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Balloon3 configuration file - * - * Copyright (C) 2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_BALLOON3 1 /* Balloon3 board */ - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOOTCOMMAND \ - "fpga load 0x0 0x50000 0x62638; " \ - "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "bootm 0xd0000;" -#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_STUART 1 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#undef CONFIG_CMD_ENV -#define CONFIG_CMD_USB -#define CONFIG_CMD_FPGA_LOADMK -#undef CONFIG_LCD - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048) - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_IS_IN_FLASH -#else -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_SYS_MONITOR_BASE 0x000000 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd -#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e -#define CONFIG_SYS_GPSR2_VAL 0x7131c000 -#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff - -#define CONFIG_SYS_GPCR0_VAL 0x0 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPCR3_VAL 0x0 - -#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02 -#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7 -#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff -#define CONFIG_SYS_GPDR3_VAL 0x000201fe - -#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b -#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa -#define CONFIG_SYS_GAFR3_L_VAL 0x54510003 -#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0xffffffff -#define CONFIG_SYS_CCCR 0x00000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8 -#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 -#define CONFIG_SYS_MSC2_VAL 0x74a42491 -#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3 -#define CONFIG_SYS_MDREFR_VAL 0x001d8018 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_BALLOON3LCD -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3" -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#endif - -/* - * FPGA - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN3 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_WAIT 1000 -#define CONFIG_MAX_FPGA_DEVICES 1 -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From af7f884ba1e6a1afbf2a75247d1bcd262d4314b2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:18:56 -0600 Subject: arm: Remove eukrea boards These boards have not been converted to generic board by the deadline. Remove all cpu9260 and cpuat91 boards. Signed-off-by: Simon Glass --- arch/arm/include/asm/mach-types.h | 37 --- arch/arm/mach-at91/Kconfig | 10 - board/eukrea/cpu9260/Kconfig | 12 - board/eukrea/cpu9260/MAINTAINERS | 13 - board/eukrea/cpu9260/Makefile | 17 -- board/eukrea/cpu9260/cpu9260.c | 158 ------------ board/eukrea/cpu9260/led.c | 139 ----------- board/eukrea/cpuat91/Kconfig | 12 - board/eukrea/cpuat91/MAINTAINERS | 7 - board/eukrea/cpuat91/Makefile | 8 - board/eukrea/cpuat91/cpuat91.c | 75 ------ configs/cpu9260_128M_defconfig | 11 - configs/cpu9260_defconfig | 11 - configs/cpu9260_nand_128M_defconfig | 11 - configs/cpu9260_nand_defconfig | 11 - configs/cpu9G20_128M_defconfig | 11 - configs/cpu9G20_defconfig | 11 - configs/cpu9G20_nand_128M_defconfig | 11 - configs/cpu9G20_nand_defconfig | 11 - configs/cpuat91_defconfig | 13 - configs/cpuat91_ram_defconfig | 13 - include/configs/cpu9260.h | 485 ------------------------------------ include/configs/cpuat91.h | 222 ----------------- 23 files changed, 1309 deletions(-) delete mode 100644 board/eukrea/cpu9260/Kconfig delete mode 100644 board/eukrea/cpu9260/MAINTAINERS delete mode 100644 board/eukrea/cpu9260/Makefile delete mode 100644 board/eukrea/cpu9260/cpu9260.c delete mode 100644 board/eukrea/cpu9260/led.c delete mode 100644 board/eukrea/cpuat91/Kconfig delete mode 100644 board/eukrea/cpuat91/MAINTAINERS delete mode 100644 board/eukrea/cpuat91/Makefile delete mode 100644 board/eukrea/cpuat91/cpuat91.c delete mode 100644 configs/cpu9260_128M_defconfig delete mode 100644 configs/cpu9260_defconfig delete mode 100644 configs/cpu9260_nand_128M_defconfig delete mode 100644 configs/cpu9260_nand_defconfig delete mode 100644 configs/cpu9G20_128M_defconfig delete mode 100644 configs/cpu9G20_defconfig delete mode 100644 configs/cpu9G20_nand_128M_defconfig delete mode 100644 configs/cpu9G20_nand_defconfig delete mode 100644 configs/cpuat91_defconfig delete mode 100644 configs/cpuat91_ram_defconfig delete mode 100644 include/configs/cpu9260.h delete mode 100644 include/configs/cpuat91.h (limited to 'include') diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index b1caa16928c..55a543ac787 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -150,7 +150,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_INTELMOTE2 775 #define MACH_TYPE_TRIZEPS4 776 #define MACH_TYPE_PNX4008 782 -#define MACH_TYPE_CPUAT91 787 #define MACH_TYPE_IQ81340SC 799 #define MACH_TYPE_IQ81340MC 801 #define MACH_TYPE_MICRO9 811 @@ -2767,18 +2766,6 @@ extern unsigned int __machine_arch_type; # define machine_is_pnx4008() (0) #endif -#ifdef CONFIG_MACH_CPUAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT91 -# endif -# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -#else -# define machine_is_cpuat91() (0) -#endif - #ifdef CONFIG_MACH_IQ81340SC # ifdef machine_arch_type # undef machine_arch_type @@ -5035,30 +5022,6 @@ extern unsigned int __machine_arch_type; # define machine_is_omap_zoom2() (0) #endif -#ifdef CONFIG_MACH_CPUAT9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9260 -# endif -# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) -#else -# define machine_is_cpuat9260() (0) -#endif - -#ifdef CONFIG_MACH_EUKREA_CPUIMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX27 -# endif -# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27) -#else -# define machine_is_eukrea_cpuimx27() (0) -#endif - #ifdef CONFIG_MACH_ACS5K # ifdef machine_arch_type # undef machine_arch_type diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index f9f148d4963..01a8d459d86 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -12,10 +12,6 @@ config TARGET_EB_CPUX9K2 bool "Support eb_cpux9k2" select CPU_ARM920T -config TARGET_CPUAT91 - bool "Support cpuat91" - select CPU_ARM920T - config TARGET_AT91SAM9260EK bool "Atmel at91sam9260 reference board" select CPU_ARM926EJS @@ -115,10 +111,6 @@ config TARGET_OTC570 bool "Support otc570" select CPU_ARM926EJS -config TARGET_CPU9260 - bool "Support cpu9260" - select CPU_ARM926EJS - config TARGET_CORVUS bool "Support corvus" select CPU_ARM926EJS @@ -152,14 +144,12 @@ source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/BuS/eb_cpux9k2/Kconfig" -source "board/eukrea/cpuat91/Kconfig" source "board/bluewater/snapper9260/Kconfig" source "board/BuS/vl_ma2sc/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" source "board/esd/otc570/Kconfig" -source "board/eukrea/cpu9260/Kconfig" source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" diff --git a/board/eukrea/cpu9260/Kconfig b/board/eukrea/cpu9260/Kconfig deleted file mode 100644 index 90d21245579..00000000000 --- a/board/eukrea/cpu9260/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPU9260 - -config SYS_BOARD - default "cpu9260" - -config SYS_VENDOR - default "eukrea" - -config SYS_CONFIG_NAME - default "cpu9260" - -endif diff --git a/board/eukrea/cpu9260/MAINTAINERS b/board/eukrea/cpu9260/MAINTAINERS deleted file mode 100644 index fb5aee80d53..00000000000 --- a/board/eukrea/cpu9260/MAINTAINERS +++ /dev/null @@ -1,13 +0,0 @@ -CPU9260 BOARD -M: Eric Benard -S: Maintained -F: board/eukrea/cpu9260/ -F: include/configs/cpu9260.h -F: configs/cpu9260_defconfig -F: configs/cpu9260_128M_defconfig -F: configs/cpu9260_nand_defconfig -F: configs/cpu9260_nand_128M_defconfig -F: configs/cpu9G20_defconfig -F: configs/cpu9G20_128M_defconfig -F: configs/cpu9G20_nand_defconfig -F: configs/cpu9G20_nand_128M_defconfig diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile deleted file mode 100644 index e34792ac428..00000000000 --- a/board/eukrea/cpu9260/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop -# Ilko Iliev -# -# (C) Copyright 2009 -# Eric Benard -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += cpu9260.o -obj-y += led.o diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c deleted file mode 100644 index 01ecccb8c94..00000000000 --- a/board/eukrea/cpu9260/cpu9260.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * Ilko Iliev - * - * (C) Copyright 2009-2011 - * Eric Benard - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -#ifdef CONFIG_CMD_NAND -static void cpu9260_nand_hw_init(void) -{ - unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC; - at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* Enable CS3 */ - csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; - writel(csa, &matrix->csa); - - /* Configure SMC CS3 for NAND/SmartMedia */ -#if defined(CONFIG_CPU9G20) - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), - &smc->cs[3].mode); -#elif defined(CONFIG_CPU9260) - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); -#endif - - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - - /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); - - /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -#ifdef CONFIG_MACB -static void cpu9260_macb_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - - at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); - - at91_phy_reset(); - - at91_macb_hw_init(); -} -#endif - -int board_early_init_f(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - writel((1 << ATMEL_ID_PIOA) | - (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), - &pmc->pcer); - - at91_seriald_hw_init(); - - return 0; -} - - -int board_init(void) -{ - /* arch number of the board */ -#if defined(CONFIG_CPU9G20) - gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20; -#elif defined(CONFIG_CPU9260) - gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_CMD_NAND - cpu9260_nand_hw_init(); -#endif -#ifdef CONFIG_MACB - cpu9260_macb_hw_init(); -#endif -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); -#endif - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0); -#endif - return rc; -} diff --git a/board/eukrea/cpu9260/led.c b/board/eukrea/cpu9260/led.c deleted file mode 100644 index 0cfe0a69fbc..00000000000 --- a/board/eukrea/cpu9260/led.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * (C) Copyright 2009 - * Eric Benard - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF, - STATUS_LED_OFF, STATUS_LED_OFF}; - -void coloured_LED_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - - at91_set_pio_output(CONFIG_RED_LED, 1); - at91_set_pio_output(CONFIG_GREEN_LED, 1); - at91_set_pio_output(CONFIG_YELLOW_LED, 1); - at91_set_pio_output(CONFIG_BLUE_LED, 1); - - at91_set_pio_value(CONFIG_RED_LED, 1); - at91_set_pio_value(CONFIG_GREEN_LED, 1); - at91_set_pio_value(CONFIG_YELLOW_LED, 1); - at91_set_pio_value(CONFIG_BLUE_LED, 1); -} - -void red_led_off(void) -{ - at91_set_pio_value(CONFIG_RED_LED, 1); - saved_state[STATUS_LED_RED] = STATUS_LED_OFF; -} - -void green_led_off(void) -{ - at91_set_pio_value(CONFIG_GREEN_LED, 1); - saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF; -} - -void yellow_led_off(void) -{ - at91_set_pio_value(CONFIG_YELLOW_LED, 1); - saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF; -} - -void blue_led_off(void) -{ - at91_set_pio_value(CONFIG_BLUE_LED, 1); - saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; -} - -void red_led_on(void) -{ - at91_set_pio_value(CONFIG_RED_LED, 0); - saved_state[STATUS_LED_RED] = STATUS_LED_ON; -} - -void green_led_on(void) -{ - at91_set_pio_value(CONFIG_GREEN_LED, 0); - saved_state[STATUS_LED_GREEN] = STATUS_LED_ON; -} - -void yellow_led_on(void) -{ - at91_set_pio_value(CONFIG_YELLOW_LED, 0); - saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON; -} - -void blue_led_on(void) -{ - at91_set_pio_value(CONFIG_BLUE_LED, 0); - saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; -} - -void __led_init(led_id_t mask, int state) -{ - __led_set(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) - blue_led_off(); - else - blue_led_on(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) - red_led_off(); - else - red_led_on(); - } else if (STATUS_LED_GREEN == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN]) - green_led_off(); - else - green_led_on(); - } else if (STATUS_LED_YELLOW == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW]) - yellow_led_off(); - else - yellow_led_on(); - } -} - -void __led_set(led_id_t mask, int state) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == state) - blue_led_on(); - else - blue_led_off(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == state) - red_led_on(); - else - red_led_off(); - } else if (STATUS_LED_GREEN == mask) { - if (STATUS_LED_ON == state) - green_led_on(); - else - green_led_off(); - } else if (STATUS_LED_YELLOW == mask) { - if (STATUS_LED_ON == state) - yellow_led_on(); - else - yellow_led_off(); - } -} diff --git a/board/eukrea/cpuat91/Kconfig b/board/eukrea/cpuat91/Kconfig deleted file mode 100644 index 27b005cdf4e..00000000000 --- a/board/eukrea/cpuat91/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPUAT91 - -config SYS_BOARD - default "cpuat91" - -config SYS_VENDOR - default "eukrea" - -config SYS_CONFIG_NAME - default "cpuat91" - -endif diff --git a/board/eukrea/cpuat91/MAINTAINERS b/board/eukrea/cpuat91/MAINTAINERS deleted file mode 100644 index 1f6bc798dc3..00000000000 --- a/board/eukrea/cpuat91/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -CPUAT91 BOARD -M: Eric Benard -S: Maintained -F: board/eukrea/cpuat91/ -F: include/configs/cpuat91.h -F: configs/cpuat91_defconfig -F: configs/cpuat91_ram_defconfig diff --git a/board/eukrea/cpuat91/Makefile b/board/eukrea/cpuat91/Makefile deleted file mode 100644 index 59b80c267c7..00000000000 --- a/board/eukrea/cpuat91/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd at denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cpuat91.o diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c deleted file mode 100644 index ec0ce0b205c..00000000000 --- a/board/eukrea/cpuat91/cpuat91.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2006-2010 Eukrea Electromatique - * Eric Benard - * based on at91rm9200dk.c which is : - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - /* arch number of CPUAT91-Board */ - gd->bd->bi_arch_number = MACH_TYPE_CPUAT91; - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - return 0; -} - - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - return at91emac_register(bis, (u32) ATMEL_BASE_EMAC); -} -#endif - -#ifdef CONFIG_SYS_I2C_SOFT -void i2c_init_board(void) -{ - u32 pin; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - writel(1 << AT91_ID_PIOA, &pmc->pcer); - pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - writel(pin, &pio->pioa.idr); - writel(pin, &pio->pioa.pudr); - writel(pin, &pio->pioa.per); - writel(pin, &pio->pioa.oer); - writel(pin, &pio->pioa.sodr); -} -#endif diff --git a/configs/cpu9260_128M_defconfig b/configs/cpu9260_128M_defconfig deleted file mode 100644 index 187fcedaa1a..00000000000 --- a/configs/cpu9260_128M_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9260=> " diff --git a/configs/cpu9260_defconfig b/configs/cpu9260_defconfig deleted file mode 100644 index 4b50505311c..00000000000 --- a/configs/cpu9260_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9260" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9260=> " diff --git a/configs/cpu9260_nand_128M_defconfig b/configs/cpu9260_nand_128M_defconfig deleted file mode 100644 index 797fb85d1fc..00000000000 --- a/configs/cpu9260_nand_128M_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9260=> " diff --git a/configs/cpu9260_nand_defconfig b/configs/cpu9260_nand_defconfig deleted file mode 100644 index 8d155d065b0..00000000000 --- a/configs/cpu9260_nand_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9260=> " diff --git a/configs/cpu9G20_128M_defconfig b/configs/cpu9G20_128M_defconfig deleted file mode 100644 index 650c93446ed..00000000000 --- a/configs/cpu9G20_128M_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9G20=> " diff --git a/configs/cpu9G20_defconfig b/configs/cpu9G20_defconfig deleted file mode 100644 index 997eec54f4f..00000000000 --- a/configs/cpu9G20_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9G20=> " diff --git a/configs/cpu9G20_nand_128M_defconfig b/configs/cpu9G20_nand_128M_defconfig deleted file mode 100644 index 6d62732eeec..00000000000 --- a/configs/cpu9G20_nand_128M_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9G20=> " diff --git a/configs/cpu9G20_nand_defconfig b/configs/cpu9G20_nand_defconfig deleted file mode 100644 index 52f916f605a..00000000000 --- a/configs/cpu9G20_nand_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPU9260=y -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="CPU9G20=> " diff --git a/configs/cpuat91_defconfig b/configs/cpuat91_defconfig deleted file mode 100644 index 10b8ad2bec6..00000000000 --- a/configs/cpuat91_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPUAT91=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="CPUAT91=> " diff --git a/configs/cpuat91_ram_defconfig b/configs/cpuat91_ram_defconfig deleted file mode 100644 index 188c2b91f88..00000000000 --- a/configs/cpuat91_ram_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_CPUAT91=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h deleted file mode 100644 index 82f4fe7d3cc..00000000000 --- a/include/configs/cpu9260.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * Ilko Iliev - * - * (C) Copyright 2009 - * Eric Benard - * - * Configuration settings for the Eukrea CPU9260 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* to be removed once maemory-map.h is fixed */ -#define AT91_BASE_SYS 0xffffe800 -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) - -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -#if defined(CONFIG_CPU9G20) -#define CONFIG_AT91SAM9G20 -#elif defined(CONFIG_CPU9260) -#define CONFIG_AT91SAM9260 -#else -#error "Unknown board" -#endif - -#include - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#if defined(CONFIG_NANDBOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x23f00000 -#else -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#endif - -/* clocks */ -#if defined(CONFIG_CPU9G20) -#define MASTER_PLL_DIV 0x01 -#define MASTER_PLL_MUL 0x2B -#elif defined(CONFIG_CPU9260) -#define MASTER_PLL_DIV 0x09 -#define MASTER_PLL_MUL 0x61 -#endif - -/* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) -#endif - -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_6 | \ - AT91_PMC_PDIV_2) -#define CONFIG_SYS_MCKR2_VAL \ - CONFIG_SYS_MCKR1_VAL -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -#endif - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 - -/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \ - AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V) - -/* SDRAM */ -/* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x287 -/* SDRAMC_CR - Configuration register*/ -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_SDRC_CR_VAL_64MB \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (9 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (3 << 20) | /* Row to Column Delay */ \ - (6 << 24) | /* Active to Precharge Delay */ \ - (10 << 28)) /* Exit Self Refresh to Active Delay */ - -#define CONFIG_SYS_SDRC_CR_VAL_128MB \ - (AT91_SDRAMC_NC_10 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (9 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (3 << 20) | /* Row to Column Delay */ \ - (6 << 24) | /* Active to Precharge Delay */ \ - (10 << 28)) /* Exit Self Refresh to Active Delay */ -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_SDRC_CR_VAL_64MB \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (8 << 28)) /* Exit Self Refresh to Active Delay */ - -#define CONFIG_SYS_SDRC_CR_VAL_128MB \ - (AT91_SDRAMC_NC_10 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (8 << 28)) /* Exit Self Refresh to Active Delay */ -#endif - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit */ -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ - AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \ - AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | \ - AT91_SMC_MODE_TDF_CYCLE(3)) -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ - AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \ - AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | \ - AT91_SMC_MODE_TDF_CYCLE(2)) -#endif - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_CR_PROCRST | \ - AT91_RSTC_MR_ERSTL(1) | \ - AT91_RSTC_MR_ERSTL(2)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xfff) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xfff)) - -/* - * Hardware drivers - */ -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_AT91_GPIO -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MII - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M) -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB -#else -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) -#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB -#endif - -/* NAND flash */ -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) - -/* NOR flash */ -#if defined(CONFIG_NANDBOOT) -#define CONFIG_SYS_NO_FLASH -#else -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_2 0x12000000 -#define CONFIG_SYS_FLASH_BANKS_LIST \ - { PHYS_FLASH_1, PHYS_FLASH_2 } -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT (255+4) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* LEDS */ -/* Status LED */ -#define CONFIG_STATUS_LED -#define CONFIG_BOARD_SPECIFIC_LED -#define STATUS_LED_RED 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_YELLOW 2 -#define STATUS_LED_BLUE 3 -/* Red */ -#define STATUS_LED_BIT STATUS_LED_RED -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* Green */ -#define STATUS_LED_BIT1 STATUS_LED_GREEN -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -/* Yellow */ -#define STATUS_LED_BIT2 STATUS_LED_YELLOW -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) -/* Blue */ -#define STATUS_LED_BIT3 STATUS_LED_BLUE -#define STATUS_LED_STATE3 STATUS_LED_ON -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) -/* Optional value */ -#define STATUS_LED_BOOT STATUS_LED_BIT - -#define CONFIG_RED_LED AT91_PIO_PORTC, 11 -#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12 -#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7 -#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9 - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20" -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#endif -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) - -#if defined(CONFIG_NANDBOOT) -#define CONFIG_SYS_USE_NANDFLASH -#undef CONFIG_SYS_USE_FLASH -#else -#define CONFIG_SYS_USE_FLASH -#undef CONFIG_SYS_USE_NANDFLASH -#endif - -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_BASEDIR "cpu9G20" -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_BASEDIR "cpu9260" -#endif - -#if defined(CONFIG_SYS_USE_FLASH) -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" -#define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:" \ - "256k(u-boot)ro," \ - "128k(u-boot-env)ro," \ - "1792k(kernel)," \ - "-(rootfs);" \ - "atmel_nand:-(nand)" - -#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "partition=nand0,0\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ - "run ramargs;bootm 22000000\0" \ - "flashboot=run ramargs;bootm 0x10060000\0" \ - "basedir=" CONFIG_SYS_BASEDIR "\0" \ - "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \ - "off 0x10000000 0x1003ffff;erase 0x10000000 " \ - "0x1003ffff;cp.b 0x24000000 0x10000000 " \ - "$(filesize)\0" \ - "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \ - " 0x10060000 0x1021ffff;erase 0x10060000 " \ - "0x1021ffff;cp.b 0x24000000 0x10060000 " \ - "$(filesize)\0" \ - "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \ - "protect off 0x10220000 0x13ffffff;erase " \ - "0x10220000 0x13ffffff;cp.b 0x24000000 " \ - "0x10220000 $(filesize)\0" \ - "" -#elif defined(CONFIG_NANDBOOT) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define MTDIDS_DEFAULT "nand0=atmel_nand" -#define MTDPARTS_DEFAULT \ - "mtdparts=atmel_nand:" \ - "128k(bootstrap)ro," \ - "256k(u-boot)ro," \ - "128k(u-boot-env)ro," \ - "128k(u-boot-env2)ro," \ - "2M(kernel)," \ - "-(rootfs)" - -#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \ - "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "partition=nand0,5\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ - "run ramargs;bootm 22000000\0" \ - "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \ - "0x200000; bootm 0x22000000\0" \ - "basedir=" CONFIG_SYS_BASEDIR "\0" \ - "u-boot=u-boot-eukrea-cpu9260.bin\0" \ - "kernel=uImage-eukrea-cpu9260.bin\0" \ - "rootfs=image-eukrea-cpu9260.ubi\0" \ - "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \ - "nand erase 20000 40000; " \ - "nand write ${loadaddr} 20000 40000\0" \ - "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \ - "nand erase a0000 200000; " \ - "nand write ${loadaddr} a0000 200000\0" \ - "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \ - "nand erase 2a0000 fd60000; " \ - "nand write ${loadaddr} 2a0000 ${filesize}\0" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SILENT_CONSOLE -#define CONFIG_NETCONSOLE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ - GENERATED_GBL_DATA_SIZE) - -#endif diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h deleted file mode 100644 index 29cd842cecc..00000000000 --- a/include/configs/cpuat91.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * CPUAT91 by (C) Copyright 2006-2010 Eric Benard - * eric@eukrea.com - * - * Configuration settings for the CPUAT91 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_CPUAT91_H -#define _CONFIG_CPUAT91_H - -#include - -#ifdef CONFIG_RAMBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x21F00000 -#else -#define CONFIG_BOOTDELAY 1 -#define CONFIG_SYS_TEXT_BASE 0 -#endif - -#define AT91C_XTAL_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - -#define CONFIG_AT91RM9200 -#define CONFIG_CPUAT91 -#define USE_920T_MMU - -#include /* needed for port definitions */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_BOARD_EARLY_INIT_F - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR -/* flash */ -#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 -#define CONFIG_SYS_MC_PUP_VAL 0x00000000 -#define CONFIG_SYS_MC_PUER_VAL 0x00000000 -#define CONFIG_SYS_MC_ASR_VAL 0x00000000 -#define CONFIG_SYS_MC_AASR_VAL 0x00000000 -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */ - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0/* ignored in arm */ - -#undef CONFIG_HARD_I2C -#define AT91_PIN_SDA (1<<25) -#define AT91_PIN_SCL (1<<26) - -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - -#define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); -#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); -#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) -#define I2C_SDA(bit) \ - if (bit) \ - writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ - else \ - writel(AT91_PMX_AA_TWD, &pio->pioa.codr); -#define I2C_SCL(bit) \ - if (bit) \ - writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ - else \ - writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); - -#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_CACHE -#undef CONFIG_CMD_USB -#undef CONFIG_CMD_DHCP - -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#endif - -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) - -#define CONFIG_DRIVER_AT91EMAC -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RMII -#define CONFIG_MII -#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_KS8721_PHY - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_PROTECTION -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define PHYS_FLASH_SIZE (16 * 1024 * 1024) -#define CONFIG_SYS_FLASH_BANKS_LIST \ - { PHYS_FLASH_1 } - -#if defined(CONFIG_CMD_USB) -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_AT91C_PQFP_UHPBU -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#endif - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) -#define CONFIG_ENV_SECT_SIZE (128 * 1024) - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_DEVICE_NULLDEV -#define CONFIG_SILENT_CONSOLE - -#define CONFIG_VERSION_VARIABLE - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:" \ - "128k(u-boot)ro," \ - "128k(u-boot-env)," \ - "1792k(kernel)," \ - "-(rootfs)" - -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200" - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdid=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \ - "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \ - "10000000 ${filesize}\0" \ - "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \ - "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \ - "10040000 ${filesize}\0" \ - "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \ - "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \ - "21000000 10200000 ${filesize}\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "flashboot=run ramargs;bootm 10040000\0" \ - "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ - "bootm 21000000\0" -#endif /* _CONFIG_CPUAT91_H */ -- cgit v1.3.1 From 7495e41ba6420b6a5fd8928cded32d789d4c1639 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:18:58 -0600 Subject: arm: Remove snowball and u8500_href boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 10 - arch/arm/include/asm/mach-types.h | 26 -- board/st-ericsson/snowball/Kconfig | 15 - board/st-ericsson/snowball/MAINTAINERS | 6 - board/st-ericsson/snowball/Makefile | 9 - board/st-ericsson/snowball/db8500_pins.h | 745 ------------------------------- board/st-ericsson/snowball/snowball.c | 340 -------------- board/st-ericsson/u8500/Kconfig | 15 - board/st-ericsson/u8500/MAINTAINERS | 6 - board/st-ericsson/u8500/Makefile | 9 - board/st-ericsson/u8500/gpio.c | 331 -------------- board/st-ericsson/u8500/u8500_href.c | 477 -------------------- configs/snowball_defconfig | 13 - configs/u8500_href_defconfig | 13 - include/configs/snowball.h | 232 ---------- include/configs/u8500_href.h | 198 -------- 16 files changed, 2445 deletions(-) delete mode 100644 board/st-ericsson/snowball/Kconfig delete mode 100644 board/st-ericsson/snowball/MAINTAINERS delete mode 100644 board/st-ericsson/snowball/Makefile delete mode 100644 board/st-ericsson/snowball/db8500_pins.h delete mode 100644 board/st-ericsson/snowball/snowball.c delete mode 100644 board/st-ericsson/u8500/Kconfig delete mode 100644 board/st-ericsson/u8500/MAINTAINERS delete mode 100644 board/st-ericsson/u8500/Makefile delete mode 100644 board/st-ericsson/u8500/gpio.c delete mode 100644 board/st-ericsson/u8500/u8500_href.c delete mode 100644 configs/snowball_defconfig delete mode 100644 configs/u8500_href_defconfig delete mode 100644 include/configs/snowball.h delete mode 100644 include/configs/u8500_href.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a501f158347..34c20e9eb50 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -564,18 +564,10 @@ config ARCH_SUNXI select USB_STORAGE select USB_KEYBOARD -config TARGET_SNOWBALL - bool "Support snowball" - select CPU_V7 - config TARGET_TS4800 bool "Support TS4800" select CPU_V7 -config TARGET_U8500_HREF - bool "Support u8500_href" - select CPU_V7 - config TARGET_VF610TWR bool "Support vf610twr" select CPU_V7 @@ -868,8 +860,6 @@ source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" -source "board/st-ericsson/snowball/Kconfig" -source "board/st-ericsson/u8500/Kconfig" source "board/st/stm32f429-discovery/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 55a543ac787..d51be0b1d2f 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -402,7 +402,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_IGEP0020 2344 #define MACH_TYPE_NUC932EVB 2356 #define MACH_TYPE_OPENRD_CLIENT 2361 -#define MACH_TYPE_U8500 2368 #define MACH_TYPE_MX51_EFIKASB 2370 #define MACH_TYPE_MARVELL_JASPER 2382 #define MACH_TYPE_FLINT 2383 @@ -974,7 +973,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_RHINO 3360 #define MACH_TYPE_ARMLEX4210 3361 #define MACH_TYPE_SWARCOEXTMODEM 3362 -#define MACH_TYPE_SNOWBALL 3363 #define MACH_TYPE_PCM049 3364 #define MACH_TYPE_VIGOR 3365 #define MACH_TYPE_OSLO_AMUNDSEN 3366 @@ -5754,18 +5752,6 @@ extern unsigned int __machine_arch_type; # define machine_is_openrd_client() (0) #endif -#ifdef CONFIG_MACH_U8500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U8500 -# endif -# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) -#else -# define machine_is_u8500() (0) -#endif - #ifdef CONFIG_MACH_MX51_EFIKASB # ifdef machine_arch_type # undef machine_arch_type @@ -12618,18 +12604,6 @@ extern unsigned int __machine_arch_type; # define machine_is_swarcoextmodem() (0) #endif -#ifdef CONFIG_MACH_SNOWBALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNOWBALL -# endif -# define machine_is_snowball() (machine_arch_type == MACH_TYPE_SNOWBALL) -#else -# define machine_is_snowball() (0) -#endif - #ifdef CONFIG_MACH_PCM049 # ifdef machine_arch_type # undef machine_arch_type diff --git a/board/st-ericsson/snowball/Kconfig b/board/st-ericsson/snowball/Kconfig deleted file mode 100644 index 0b3a0cca6ce..00000000000 --- a/board/st-ericsson/snowball/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_SNOWBALL - -config SYS_BOARD - default "snowball" - -config SYS_VENDOR - default "st-ericsson" - -config SYS_SOC - default "u8500" - -config SYS_CONFIG_NAME - default "snowball" - -endif diff --git a/board/st-ericsson/snowball/MAINTAINERS b/board/st-ericsson/snowball/MAINTAINERS deleted file mode 100644 index 132fc524bae..00000000000 --- a/board/st-ericsson/snowball/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SNOWBALL BOARD -M: Mathieu Poirier -S: Maintained -F: board/st-ericsson/snowball/ -F: include/configs/snowball.h -F: configs/snowball_defconfig diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile deleted file mode 100644 index f0605e2bcd3..00000000000 --- a/board/st-ericsson/snowball/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) ST-Ericsson SA 2009 -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ccflags-y += -D__RELEASE -D__STN_8500 - -obj-y := snowball.o diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h deleted file mode 100644 index e339cb86e24..00000000000 --- a/board/st-ericsson/snowball/db8500_pins.h +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. - * The purpose is that GPIO config found in kernel should work by simply - * copy-paste it to U-boot. - * - * Ported to U-boot by: - * Copyright (C) 2010 Joakim Axelsson - ** - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent - */ - -#ifndef __DB8500_PINS_H -#define __DB8500_PINS_H - -#include - -#define GPIO0_GPIO PIN_CFG(0, GPIO) -#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) -#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) -#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) - -#define GPIO1_GPIO PIN_CFG(1, GPIO) -#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) -#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) -#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) - -#define GPIO2_GPIO PIN_CFG(2, GPIO) -#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) -#define GPIO2_NONE PIN_CFG(2, ALT_B) -#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) - -#define GPIO3_GPIO PIN_CFG(3, GPIO) -#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) -#define GPIO3_NONE PIN_CFG(3, ALT_B) -#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) - -#define GPIO4_GPIO PIN_CFG(4, GPIO) -#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) -#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) -#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) - -#define GPIO5_GPIO PIN_CFG(5, GPIO) -#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) -#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) -#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) - -#define GPIO6_GPIO PIN_CFG(6, GPIO) -#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) -#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) -#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) - -#define GPIO7_GPIO PIN_CFG(7, GPIO) -#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) -#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) -#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) - -#define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) -#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) - -#define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) -#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) - -#define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) -#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) -#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) - -#define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) -#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) -#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) - -#define GPIO12_GPIO PIN_CFG(12, GPIO) -#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) -#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) - -#define GPIO13_GPIO PIN_CFG(13, GPIO) -#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) - -#define GPIO14_GPIO PIN_CFG(14, GPIO) -#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) - -#define GPIO15_GPIO PIN_CFG(15, GPIO) -#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) -#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) - -#define GPIO16_GPIO PIN_CFG(16, GPIO) -#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) -#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) -#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) - -#define GPIO17_GPIO PIN_CFG(17, GPIO) -#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) -#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) -#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) - -#define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) -#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) -#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) - -#define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) -#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) -#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) - -#define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) -#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) -#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) - -#define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) -#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) -#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) - -#define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) -#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) -#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) - -#define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) -#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) -#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) - -#define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) -#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) -#define GPIO24_MS_BS PIN_CFG(24, ALT_C) - -#define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) -#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) -#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) - -#define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) -#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) -#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) - -#define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) -#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) -#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) - -#define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) -#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) -#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) - -#define GPIO29_GPIO PIN_CFG(29, GPIO) -#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) -#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) -#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) - -#define GPIO30_GPIO PIN_CFG(30, GPIO) -#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) -#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) -#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) - -#define GPIO31_GPIO PIN_CFG(31, GPIO) -#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) -#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) -#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) - -#define GPIO32_GPIO PIN_CFG(32, GPIO) -#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) -#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) -#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) - -#define GPIO33_GPIO PIN_CFG(33, GPIO) -#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) -#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) -#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) - -#define GPIO34_GPIO PIN_CFG(34, GPIO) -#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) -#define GPIO34_NONE PIN_CFG(34, ALT_B) -#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) - -#define GPIO35_GPIO PIN_CFG(35, GPIO) -#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) -#define GPIO35_NONE PIN_CFG(35, ALT_B) -#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) - -#define GPIO36_GPIO PIN_CFG(36, GPIO) -#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) -#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) -#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) - -#define GPIO64_GPIO PIN_CFG(64, GPIO) -#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) -#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) -#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) - -#define GPIO65_GPIO PIN_CFG(65, GPIO) -#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) -#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) -#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) - -#define GPIO66_GPIO PIN_CFG(66, GPIO) -#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) -#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) -#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) - -#define GPIO67_GPIO PIN_CFG(67, GPIO) -#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) -#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) -#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) - -#define GPIO68_GPIO PIN_CFG(68, GPIO) -#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) -#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) -#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) - -#define GPIO69_GPIO PIN_CFG(69, GPIO) -#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) -#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) -#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) - -#define GPIO70_GPIO PIN_CFG(70, GPIO) -#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) -#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) -#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) - -#define GPIO71_GPIO PIN_CFG(71, GPIO) -#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) -#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) -#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) - -#define GPIO72_GPIO PIN_CFG(72, GPIO) -#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) -#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) -#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) - -#define GPIO73_GPIO PIN_CFG(73, GPIO) -#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) -#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) -#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) - -#define GPIO74_GPIO PIN_CFG(74, GPIO) -#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) -#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) -#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) - -#define GPIO75_GPIO PIN_CFG(75, GPIO) -#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) -#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) -#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) - -#define GPIO76_GPIO PIN_CFG(76, GPIO) -#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) -#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) -#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) - -#define GPIO77_GPIO PIN_CFG(77, GPIO) -#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) -#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) -#define GPIO77_NONE PIN_CFG(77, ALT_C) - -#define GPIO78_GPIO PIN_CFG(78, GPIO) -#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) -#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) -#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) - -#define GPIO79_GPIO PIN_CFG(79, GPIO) -#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) -#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) -#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) - -#define GPIO80_GPIO PIN_CFG(80, GPIO) -#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) -#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) -#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) - -#define GPIO81_GPIO PIN_CFG(81, GPIO) -#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) -#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) -#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) - -#define GPIO82_GPIO PIN_CFG(82, GPIO) -#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) -#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) - -#define GPIO83_GPIO PIN_CFG(83, GPIO) -#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) -#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) - -#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) -#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) -#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) - -#define GPIO85_GPIO PIN_CFG(85, GPIO) -#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) -#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) - -#define GPIO86_GPIO PIN_CFG(86, GPIO) -#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) -#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) -#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) - -#define GPIO87_GPIO PIN_CFG(87, GPIO) -#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) -#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) -#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) - -#define GPIO88_GPIO PIN_CFG(88, GPIO) -#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) -#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) -#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) - -#define GPIO89_GPIO PIN_CFG(89, GPIO) -#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) -#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) -#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) - -#define GPIO90_GPIO PIN_CFG(90, GPIO) -#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) -#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) -#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) - -#define GPIO91_GPIO PIN_CFG(91, GPIO) -#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) -#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) -#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) - -#define GPIO92_GPIO PIN_CFG(92, GPIO) -#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) -#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) -#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) - -#define GPIO93_GPIO PIN_CFG(93, GPIO) -#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) -#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) -#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) - -#define GPIO94_GPIO PIN_CFG(94, GPIO) -#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) -#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) -#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) - -#define GPIO95_GPIO PIN_CFG(95, GPIO) -#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) -#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) -#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) - -#define GPIO96_GPIO PIN_CFG(96, GPIO) -#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) -#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) -#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) - -#define GPIO97_GPIO PIN_CFG(97, GPIO) -#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) -#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) -#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) - -#define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) -#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) - -#define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) -#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) - -#define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) -#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) -#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) - -#define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) -#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) - -#define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) -#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) - -#define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) -#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) - -#define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) -#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) - -#define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) -#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) - -#define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) -#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) - -#define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) -#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) - -#define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) -#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) - -#define GPIO139_GPIO PIN_CFG(139, GPIO) -#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) -#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) -#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) - -#define GPIO140_GPIO PIN_CFG(140, GPIO) -#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) -#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) -#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) - -#define GPIO141_GPIO PIN_CFG(141, GPIO) -#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) -#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) -#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) - -#define GPIO142_GPIO PIN_CFG(142, GPIO) -#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) -#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) -#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) - -#define GPIO143_GPIO PIN_CFG(143, GPIO) -#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) - -#define GPIO144_GPIO PIN_CFG(144, GPIO) -#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) - -#define GPIO145_GPIO PIN_CFG(145, GPIO) -#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) - -#define GPIO146_GPIO PIN_CFG(146, GPIO) -#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) - -#define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) - -#define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) - -#define GPIO149_GPIO PIN_CFG(149, GPIO) -#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) -#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) -#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) - -#define GPIO150_GPIO PIN_CFG(150, GPIO) -#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) -#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) - -#define GPIO151_GPIO PIN_CFG(151, GPIO) -#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) -#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) -#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) - -#define GPIO152_GPIO PIN_CFG(152, GPIO) -#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) -#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) -#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) - -#define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) -#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) -#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) - -#define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) -#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) -#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) - -#define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) -#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) -#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) - -#define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) -#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) -#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) - -#define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) -#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) -#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) - -#define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) -#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) -#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) - -#define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) -#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) -#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) - -#define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) -#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) -#define GPIO160_NONE PIN_CFG(160, ALT_C) - -#define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) -#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) -#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) - -#define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) -#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) -#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) - -#define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) -#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) -#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) - -#define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) -#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) -#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) - -#define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) -#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) -#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) - -#define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) -#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) -#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) - -#define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) -#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) -#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) - -#define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) -#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) -#define GPIO168_NONE PIN_CFG(168, ALT_C) - -#define GPIO169_GPIO PIN_CFG(169, GPIO) -#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) -#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) -#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) - -#define GPIO170_GPIO PIN_CFG(170, GPIO) -#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) -#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) -#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) - -#define GPIO171_GPIO PIN_CFG(171, GPIO) -#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) -#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) -#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) - -#define GPIO192_GPIO PIN_CFG(192, GPIO) -#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) - -#define GPIO193_GPIO PIN_CFG(193, GPIO) -#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) - -#define GPIO194_GPIO PIN_CFG(194, GPIO) -#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) - -#define GPIO195_GPIO PIN_CFG(195, GPIO) -#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) - -#define GPIO196_GPIO PIN_CFG(196, GPIO) -#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) - -#define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) - -#define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) - -#define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) - -#define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) - -#define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) - -#define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) -#define GPIO202_PWL PIN_CFG(202, ALT_B) -#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) - -#define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) - -#define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) - -#define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) - -#define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) - -#define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) - -#define GPIO208_GPIO PIN_CFG(208, GPIO) -#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) - -#define GPIO209_GPIO PIN_CFG(209, GPIO) -#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) -#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) - -#define GPIO210_GPIO PIN_CFG(210, GPIO) -#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) - -#define GPIO211_GPIO PIN_CFG(211, GPIO) -#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) - -#define GPIO212_GPIO PIN_CFG(212, GPIO) -#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) -#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) - -#define GPIO213_GPIO PIN_CFG(213, GPIO) -#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) -#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) - -#define GPIO214_GPIO PIN_CFG(214, GPIO) -#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) -#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) - -#define GPIO215_GPIO PIN_CFG(215, GPIO) -#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) -#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) -#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) - -#define GPIO216_GPIO PIN_CFG(216, GPIO) -#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) -#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) -#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) - -#define GPIO217_GPIO PIN_CFG(217, GPIO) -#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) -#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) -#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) - -#define GPIO218_GPIO PIN_CFG(218, GPIO) -#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) -#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) -#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) - -#define GPIO219_GPIO PIN_CFG(219, GPIO) -#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) -#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) - -#define GPIO220_GPIO PIN_CFG(220, GPIO) -#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) -#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) -#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) - -#define GPIO221_GPIO PIN_CFG(221, GPIO) -#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) -#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) - -#define GPIO222_GPIO PIN_CFG(222, GPIO) -#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) -#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) - -#define GPIO223_GPIO PIN_CFG(223, GPIO) -#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) -#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) -#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) - -#define GPIO224_GPIO PIN_CFG(224, GPIO) -#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) -#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) -#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) - -#define GPIO225_GPIO PIN_CFG(225, GPIO) -#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) -#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) -#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) - -#define GPIO226_GPIO PIN_CFG(226, GPIO) -#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) -#define GPIO226_PWL PIN_CFG(226, ALT_B) -#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) - -#define GPIO227_GPIO PIN_CFG(227, GPIO) -#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) - -#define GPIO228_GPIO PIN_CFG(228, GPIO) -#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) - -#define GPIO229_GPIO PIN_CFG(229, GPIO) -#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) -#define GPIO229_PWL PIN_CFG(229, ALT_B) -#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) - -#define GPIO230_GPIO PIN_CFG(230, GPIO) -#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) -#define GPIO230_PWL PIN_CFG(230, ALT_B) -#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) - -#define GPIO256_GPIO PIN_CFG(256, GPIO) -#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) - -#define GPIO257_GPIO PIN_CFG(257, GPIO) -#define GPIO257_USB_STP PIN_CFG(257, ALT_A) - -#define GPIO258_GPIO PIN_CFG(258, GPIO) -#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) -#define GPIO258_NONE PIN_CFG(258, ALT_B) -#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) - -#define GPIO259_GPIO PIN_CFG(259, GPIO) -#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) - -#define GPIO260_GPIO PIN_CFG(260, GPIO) -#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) - -#define GPIO261_GPIO PIN_CFG(261, GPIO) -#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) - -#define GPIO262_GPIO PIN_CFG(262, GPIO) -#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) - -#define GPIO263_GPIO PIN_CFG(263, GPIO) -#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) - -#define GPIO264_GPIO PIN_CFG(264, GPIO) -#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) - -#define GPIO265_GPIO PIN_CFG(265, GPIO) -#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) - -#define GPIO266_GPIO PIN_CFG(266, GPIO) -#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) - -#define GPIO267_GPIO PIN_CFG(267, GPIO) -#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) - -#endif diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c deleted file mode 100644 index c3061e20d95..00000000000 --- a/board/st-ericsson/snowball/snowball.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MMC -#include "../../../drivers/mmc/arm_pl180_mmci.h" -#endif -#include "db8500_pins.h" - -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - -/* - * Memory controller register - */ -#define DMC_BASE_ADDR 0x80156000 -#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) - -/* - * GPIO pin config common for MOP500/HREF boards - */ -unsigned long gpio_cfg_common[] = { - /* I2C */ - GPIO147_I2C0_SCL, - GPIO148_I2C0_SDA, - GPIO16_I2C1_SCL, - GPIO17_I2C1_SDA, - GPIO10_I2C2_SDA, - GPIO11_I2C2_SCL, - GPIO229_I2C3_SDA, - GPIO230_I2C3_SCL, - - /* SSP0, to AB8500 */ - GPIO143_SSP0_CLK, - GPIO144_SSP0_FRM, - GPIO145_SSP0_RXD | PIN_PULL_DOWN, - GPIO146_SSP0_TXD, - - /* MMC0 (MicroSD card) */ - GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, - GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, - GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, - GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, - GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, - GPIO23_MC0_CLK | PIN_OUTPUT_LOW, - GPIO24_MC0_CMD | PIN_INPUT_PULLUP, - GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, - GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, - GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, - GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, - - /* MMC4 (On-board eMMC) */ - GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, - GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, - GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, - GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, - GPIO201_MC4_CMD | PIN_INPUT_PULLUP, - GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, - GPIO203_MC4_CLK | PIN_OUTPUT_LOW, - GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, - GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, - GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, - GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, - - /* UART2, console */ - GPIO29_U2_RXD | PIN_INPUT_PULLUP, - GPIO30_U2_TXD | PIN_OUTPUT_HIGH, - GPIO31_U2_CTSn | PIN_INPUT_PULLUP, - GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, - - /* - * USB, pin 256-267 USB, Is probably already setup correctly from - * BootROM/boot stages, but we don't trust that and set it up anyway - */ - GPIO256_USB_NXT, - GPIO257_USB_STP, - GPIO258_USB_XCLK, - GPIO259_USB_DIR, - GPIO260_USB_DAT7, - GPIO261_USB_DAT6, - GPIO262_USB_DAT5, - GPIO263_USB_DAT4, - GPIO264_USB_DAT3, - GPIO265_USB_DAT2, - GPIO266_USB_DAT1, - GPIO267_USB_DAT0, -}; - -unsigned long gpio_cfg_snowball[] = { - /* MMC0 (MicroSD card) */ - GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ - GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ - GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ - - /* eMMC */ - GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ - - /* LAN */ - GPIO131_SM_ADQ8, - GPIO132_SM_ADQ9, - GPIO133_SM_ADQ10, - GPIO134_SM_ADQ11, - GPIO135_SM_ADQ12, - GPIO136_SM_ADQ13, - GPIO137_SM_ADQ14, - GPIO138_SM_ADQ15, - - /* RSTn_LAN */ - GPIO141_GPIO | PIN_OUTPUT_HIGH, -}; - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init(void) -{ - /* - * Setup board (bd) and board-info (bi). - * bi_arch_number: Unique id for this board. It will passed in r1 to - * Linux startup code and is the machine_id. - * bi_boot_params: Where this board expects params. - */ - gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; - gd->bd->bi_boot_params = 0x00000100; - - /* Configure GPIO pins needed by U-boot */ - db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common)); - - db8500_gpio_config_pins(gpio_cfg_snowball, - ARRAY_SIZE(gpio_cfg_snowball)); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->ram_size = gd->bd->bi_dram[0].size = - get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - return 0; -} - -static int raise_ab8500_gpio16(void) -{ - int ret; - - /* selection */ - ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG); - if (ret < 0) - goto out; - - ret |= 0x80; - ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret); - if (ret < 0) - goto out; - - /* direction */ - ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG); - if (ret < 0) - goto out; - - ret |= 0x80; - ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret); - if (ret < 0) - goto out; - - /* out */ - ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG); - if (ret < 0) - goto out; - - ret |= 0x80; - ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret); - -out: - return ret; -} - -static int raise_ab8500_gpio26(void) -{ - int ret; - - /* selection */ - ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG); - if (ret < 0) - goto out; - - ret |= 0x2; - ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret); - if (ret < 0) - goto out; - - /* out */ - ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG); - if (ret < 0) - goto out; - - ret |= 0x2; - ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret); - -out: - return ret; -} - -int board_late_init(void) -{ - /* enable 3V3 for LAN controller */ - if (raise_ab8500_gpio26() >= 0) { - /* Turn on FSMC device */ - writel(0x1, 0x8000f000); - writel(0x1, 0x8000f008); - - /* setup FSMC for LAN controler */ - writel(0x305b, 0x80000000); - - /* run at the highest possible speed */ - writel(0x01010210, 0x80000004); - } else - printf("error: can't raise GPIO26\n"); - - /* enable 3v6 for GBF chip */ - if ((raise_ab8500_gpio16() < 0)) - printf("error: cant' raise GPIO16\n"); - - /* empty UART RX FIFO */ - while (tstc()) - (void) getc(); - - return 0; -} - -#ifdef CONFIG_MMC -/* - * emmc_host_init - initialize the emmc controller. - * Configure GPIO settings, set initial clock and power for emmc slot. - * Initialize mmc struct and register with mmc framework. - */ -static int emmc_host_init(void) -{ - struct pl180_mmc_host *host; - - host = malloc(sizeof(struct pl180_mmc_host)); - if (!host) - return -ENOMEM; - memset(host, 0, sizeof(*host)); - - host->base = (struct sdi_registers *)CFG_EMMC_BASE; - host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON; - host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | - SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; - strcpy(host->name, "EMMC"); - host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; - host->voltages = VOLTAGE_WINDOW_MMC; - host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); - host->clock_max = ARM_MCLK / 2; - host->clock_in = ARM_MCLK; - host->version2 = 1; - - return arm_pl180_mmci_init(host); -} - -/* - * mmc_host_init - initialize the external mmc controller. - * Configure GPIO settings, set initial clock and power for mmc slot. - * Initialize mmc struct and register with mmc framework. - */ -static int mmc_host_init(void) -{ - struct pl180_mmc_host *host; - u32 sdi_u32; - - host = malloc(sizeof(struct pl180_mmc_host)); - if (!host) - return -ENOMEM; - memset(host, 0, sizeof(*host)); - - host->base = (struct sdi_registers *)CFG_MMC_BASE; - sdi_u32 = 0xBF; - writel(sdi_u32, &host->base->power); - host->pwr_init = 0xBF; - host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | - SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; - strcpy(host->name, "MMC"); - host->caps = MMC_MODE_8BIT; - host->b_max = 0; - host->voltages = VOLTAGE_WINDOW_SD; - host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); - host->clock_max = ARM_MCLK / 2; - host->clock_in = ARM_MCLK; - host->version2 = 1; - - return arm_pl180_mmci_init(host); -} - -/* - * board_mmc_init - initialize all the mmc/sd host controllers. - * Called by generic mmc framework. - */ -int board_mmc_init(bd_t *bis) -{ - int error; - - (void) bis; - - error = emmc_host_init(); - if (error) { - printf("emmc_host_init() %d\n", error); - return -1; - } - - u8500_mmc_power_init(); - - error = mmc_host_init(); - if (error) { - printf("mmc_host_init() %d\n", error); - return -1; - } - - return 0; -} -#endif /* CONFIG_MMC */ diff --git a/board/st-ericsson/u8500/Kconfig b/board/st-ericsson/u8500/Kconfig deleted file mode 100644 index 909f30db4b6..00000000000 --- a/board/st-ericsson/u8500/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_U8500_HREF - -config SYS_BOARD - default "u8500" - -config SYS_VENDOR - default "st-ericsson" - -config SYS_SOC - default "u8500" - -config SYS_CONFIG_NAME - default "u8500_href" - -endif diff --git a/board/st-ericsson/u8500/MAINTAINERS b/board/st-ericsson/u8500/MAINTAINERS deleted file mode 100644 index e2581eb2e4b..00000000000 --- a/board/st-ericsson/u8500/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -U8500 BOARD -#M: - -S: Maintained -F: board/st-ericsson/u8500/ -F: include/configs/u8500_href.h -F: configs/u8500_href_defconfig diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile deleted file mode 100644 index d6c4280475a..00000000000 --- a/board/st-ericsson/u8500/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) ST-Ericsson SA 2009 -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ccflags-y += -D__RELEASE -D__STN_8500 - -obj-y := u8500_href.o gpio.o diff --git a/board/st-ericsson/u8500/gpio.c b/board/st-ericsson/u8500/gpio.c deleted file mode 100644 index 2ddc7af48b8..00000000000 --- a/board/st-ericsson/u8500/gpio.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -static struct gpio_register *addr_gpio_register[] = { - (void *)U8500_GPIO_0_BASE, - (void *)U8500_GPIO_1_BASE, - (void *)U8500_GPIO_2_BASE, - (void *)U8500_GPIO_3_BASE, - (void *)U8500_GPIO_4_BASE, - (void *)U8500_GPIO_5_BASE, - (void *)U8500_GPIO_6_BASE, - (void *)U8500_GPIO_7_BASE, - (void *)U8500_GPIO_8_BASE, -}; - -struct gpio_altfun_data altfun_table[] = { - { - .altfun = GPIO_ALT_I2C_0, - .start = 147, - .end = 148, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_I2C_1, - .start = 16, - .end = 17, - .cont = 0, - .type = GPIO_ALTF_B, - }, - { - .altfun = GPIO_ALT_I2C_2, - .start = 10, - .end = 11, - .cont = 0, - .type = GPIO_ALTF_B, - }, - { - .altfun = GPIO_ALT_I2C_3, - .start = 229, - .end = 230, - .cont = 0, - .type = GPIO_ALTF_C, - }, - { - .altfun = GPIO_ALT_UART_0_MODEM, - .start = 0, - .end = 3, - .cont = 1, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_UART_0_MODEM, - .start = 33, - .end = 36, - .cont = 0, - .type = GPIO_ALTF_C, - }, - { - .altfun = GPIO_ALT_UART_1, - .start = 4, - .end = 7, - .cont = 0, - .type = - GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_UART_2, - .start = 18, - .end = 19, - .cont = 1, - .type = GPIO_ALTF_B, - }, - { - .altfun = GPIO_ALT_UART_2, - .start = 29, - .end = 32, - .cont = 0, - .type = GPIO_ALTF_C, - }, - { - .altfun = GPIO_ALT_MSP_0, - .start = 12, - .end = 17, - .cont = 1, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_MSP_0, - .start = 21, - .end = 21, - .cont = 0, - .type = GPIO_ALTF_B, - }, - { - .altfun = GPIO_ALT_MSP_1, - .start = 33, - .end = 36, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_MSP_2, - .start = 192, - .end = 196, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_LCD_PANEL, - .start = 64, - .end = 93, - .cont = 1, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_LCD_PANEL, - .start = 150, - .end = 171, - .cont = 0, - .type = GPIO_ALTF_B, - }, - { - .altfun = GPIO_ALT_SD_CARD0, - .start = 18, - .end = 28, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_MM_CARD0, - .start = 18, - .end = 32, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_USB_OTG, - .start = 256, - .end = 267, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_EMMC, - .start = 197, - .end = 207, - .cont = 0, - .type = GPIO_ALTF_A, - }, - { - .altfun = GPIO_ALT_POP_EMMC, - .start = 128, - .end = 138, - .cont = 0, - .type = GPIO_ALTF_A, - }, -}; - -/* - * Static Function declarations - */ -enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config) -{ - struct gpio_register *p_gpio_register = - addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - enum gpio_error error = GPIO_OK; - u32 temp_reg; - - switch (config->mode) { - case GPIO_ALTF_A: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - break; - case GPIO_ALTF_B: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - break; - case GPIO_ALTF_C: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - break; - case GPIO_MODE_SOFTWARE: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - - switch (config->direction) { - case GPIO_DIR_INPUT: - writel(mask, &p_gpio_register->gpio_dirc); - break; - case GPIO_DIR_OUTPUT: - writel(mask, &p_gpio_register->gpio_dirs); - break; - case GPIO_DIR_LEAVE_UNCHANGED: - break; - default: - return GPIO_INVALID_PARAMETER; - } - - break; - case GPIO_MODE_LEAVE_UNCHANGED: - break; - default: - return GPIO_INVALID_PARAMETER; - } - return error; -} - -enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name) -{ - struct gpio_register *p_gpio_register = - addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - enum gpio_error error = GPIO_OK; - u32 temp_reg; - - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - writel(mask, &p_gpio_register->gpio_dirc); - - return error; -} - -struct gpio_config altfun_pinconfig; -enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func, - int which_altfunc, char *dev_name) -{ - int i, j, start, end; - enum gpio_error error = -1; - - for (i = 0; i < ARRAY_SIZE(altfun_table); i++) { - if (altfun_table[i].altfun != alt_func) - continue; - - start = altfun_table[i].start; - end = altfun_table[i].end; - for (j = start; j <= end; j++) { - if (which_altfunc == GPIO_ALTF_FIND) - altfun_pinconfig.mode = altfun_table[i].type; - else - altfun_pinconfig.mode = which_altfunc; - altfun_pinconfig.direction = GPIO_DIR_OUTPUT; - altfun_pinconfig.dev_name = dev_name; - - if (which_altfunc != GPIO_ALTF_DISABLE) - error = gpio_setpinconfig(j, &altfun_pinconfig); - else - error = gpio_resetgpiopin(j, dev_name); - if (!error) - continue; - printf("GPIO %d configuration failure (nmdk_error:%d)", - j, error); - error = GPIO_INVALID_PARAMETER; - return error; - } - - if (!altfun_table[i].cont) - break; - } - return error; -} - -int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name) -{ - struct gpio_register *p_gpio_register = - addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - - switch (value) { - case GPIO_DATA_HIGH: - writel(mask, &p_gpio_register->gpio_dats); - break; - case GPIO_DATA_LOW: - writel(mask, &p_gpio_register->gpio_datc); - break; - default: - printf("Invalid value passed in %s", __FUNCTION__); - return GPIO_INVALID_PARAMETER; - } - return GPIO_OK; -} - -int gpio_readpin(int pin_id, enum gpio_data *rv) -{ - struct gpio_register *p_gpio_register = - addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - - if ((readl(&p_gpio_register->gpio_dat) & mask) != 0) - *rv = GPIO_DATA_HIGH; - else - *rv = GPIO_DATA_LOW; - return GPIO_OK; -} - -int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name) -{ - return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name); -} - -int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name) -{ - return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name); -} diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c deleted file mode 100644 index 9df499b1dcf..00000000000 --- a/board/st-ericsson/u8500/u8500_href.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MMC -#include "../../../drivers/mmc/arm_pl180_mmci.h" -#endif - -#define NOMADIK_PER4_BASE (0x80150000) -#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000) -#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000) - -/* Power, Reset, Clock Management Unit */ -/* - * SVA: Smart Video Accelerator - * SIA: Smart Imaging Accelerator - * SGA: Smart Graphic accelerator - * B2R2: Graphic blitter - */ -#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000) -#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004) -#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008) -#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C) -#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010) -#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014) -#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) -#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) -#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) -#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) -#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028) -#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) -#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) -#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) -#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) -#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) -#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) -#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074) -#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078) - -#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080) -#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084) -#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088) -#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C) -#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114) - -#define PRCM_TCR (PRCMU_BASE + 0x1C8) - -/* - * Memory controller register - */ -#define DMC_BASE_ADDR 0x80156000 -#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) - -int board_id; /* set in board_late_init() */ - -/* PLLs for clock management registers */ -enum { - GATED = 0, - PLLSOC0, /* pllsw = 001, ffs() = 1 */ - PLLSOC1, /* pllsw = 010, ffs() = 2 */ - PLLDDR, /* pllsw = 100, ffs() = 3 */ - PLLARM, -}; - -static struct pll_freq_regs { - int idx; /* index fror pll_name and pll_khz arrays */ - uint32_t addr; -} pll_freq_regs[] = { - {PLLSOC0, PRCM_PLLSOC0_FREQ_REG}, - {PLLSOC1, PRCM_PLLSOC1_FREQ_REG}, - {PLLDDR, PRCM_PLLDDR_FREQ_REG}, - {PLLARM, PRCM_PLLARM_FREQ_REG}, - {0, 0}, -}; - -static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"}; -static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */ - -static struct clk_mgt_regs { - uint32_t addr; - uint32_t val; - const char *descr; -} clk_mgt_regs[] = { - /* register content taken from bootrom settings */ - {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */ - {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */ - {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */ - {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */ - {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */ - {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */ - {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */ - {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */ - {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */ - {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */ - {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */ - {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */ - {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */ - {0, 0, NULL}, -}; - -static void init_regs(void); - -DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_early_init_f(void) -{ - init_regs(); - return 0; -} - -int board_init(void) -{ - uint32_t unused_cols_rows; - unsigned int nrows; - unsigned int ncols; - - gd->bd->bi_arch_number = 0x1A4; - gd->bd->bi_boot_params = 0x00000100; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - - /* - * Assumption: 2 CS active, both CS have same layout. - * 15 rows max, 11 cols max (controller spec). - * memory chip has 8 banks, I/O width 32 bit. - * The correct way would be to read MR#8: I/O width and density, - * but this requires locking against the PRCMU firmware. - * Simplified approach: - * Read number of unused rows and columns from mem controller. - * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes - */ - unused_cols_rows = readl(DMC_CTL_97); - nrows = 15 - (unused_cols_rows & 0x07); - ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); - gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4; - - icache_enable(); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_SIZE_1; - - return 0; -} - -unsigned int addr_vall_arr[] = { - 0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */ - 0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */ - 0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */ - 0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */ - 0x80157020, 0x00000150, /* I2C 48MHz clock */ - 0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */ - 0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */ - 0xA03DF000, 0x0000000D, /* Clock for MTU Timers */ - 0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */ - 0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ - 0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ - 0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */ - 0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */ - 0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */ - 0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */ - 0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */ - 0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */ - 0x801571E4, 0x0000000C, /* PRCMU settings for B2R2, - PRCM_APE_RESETN_SET_REG */ - 0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */ - 0xA03FF000, 0x00000003, /* USB */ - 0xA03FF008, 0x00000001, /* USB */ - 0xA03FE00C, 0x00000000, /* USB */ - 0xA03FE020, 0x00000FFF, /* USB */ - 0xA03FE024, 0x00000000 /* USB */ -}; - -#ifdef CONFIG_BOARD_LATE_INIT -/* - * called after all initialisation were done, but before the generic - * mmc_initialize(). - */ -int board_late_init(void) -{ - uchar byte; - - /* - * Determine and set board_id environment variable - * 0: mop500, 1: href500 - * Above boards have different GPIO expander chips which we can - * distinguish by the chip id. - * - * The board_id environment variable is needed for the Linux bootargs. - */ - (void) i2c_set_bus_num(0); - (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1); - if (byte == 0x01) { - board_id = 0; - setenv("board_id", "0"); - } else { - board_id = 1; - setenv("board_id", "1"); - } -#ifdef CONFIG_MMC - u8500_mmc_power_init(); - - /* - * config extended GPIO pins for level shifter and - * SDMMC_ENABLE - */ - if (board_id == 0) { - /* MOP500 */ - byte = 0x0c; - (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1); - (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1); - } else { - /* HREF */ - /* set the direction of GPIO KPY9 and KPY10 */ - byte = 0x06; - (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1); - /* must be a multibyte access */ - (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1, - (uchar []) {0x06, 0x06}, 2); - } -#endif /* CONFIG_MMC */ - /* - * Create a memargs variable which points uses either the memargs256 or - * memargs512 environment variable, depending on the memory size. - * memargs is used to build the bootargs, memargs256 and memargs512 are - * stored in the environment. - */ - if (gd->bd->bi_dram[0].size == 0x10000000) { - setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}"); - setenv("mem", "256M"); - } else { - setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}"); - setenv("mem", "512M"); - } - - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ - -static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits) -{ - writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats); - writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis); -} - -static void init_regs(void) -{ - /* FIXME Remove magic register array settings for ED also */ - struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE; - - /* Enable timers */ - writel(1 << 17, &prcmu->tcr); - - u8500_prcmu_enable(&prcmu->per1clk_mgt); - u8500_prcmu_enable(&prcmu->per2clk_mgt); - u8500_prcmu_enable(&prcmu->per3clk_mgt); - u8500_prcmu_enable(&prcmu->per5clk_mgt); - u8500_prcmu_enable(&prcmu->per6clk_mgt); - u8500_prcmu_enable(&prcmu->per7clk_mgt); - - u8500_prcmu_enable(&prcmu->uartclk_mgt); - u8500_prcmu_enable(&prcmu->i2cclk_mgt); - - u8500_prcmu_enable(&prcmu->sdmmcclk_mgt); - - u8500_clock_enable(1, 9, -1); /* GPIO0 */ - - u8500_clock_enable(2, 11, -1); /* GPIO1 */ - - u8500_clock_enable(3, 8, -1); /* GPIO2 */ - u8500_clock_enable(5, 1, -1); /* GPIO3 */ - - u8500_clock_enable(3, 6, 6); /* UART2 */ - - gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0"); - u8500_clock_enable(3, 3, 3); /* I2C0 */ - - early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000); - gpio_altfuncenable(GPIO_ALT_UART_2, "UART2"); - - early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0); - gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC"); - - early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0); - gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD"); - - u8500_clock_enable(1, 5, 5); /* SDI0 */ - u8500_clock_enable(2, 4, 2); /* SDI4 */ - - u8500_clock_enable(6, 7, -1); /* MTU0 */ - u8500_clock_enable(3, 4, 4); /* SDI2 */ - - early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff); - gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC"); - - /* - * Enabling clocks for all devices which are AMBA devices in the - * kernel. Otherwise they will not get probe()'d because the - * peripheral ID register will not be powered. - */ - - /* XXX: some of these differ between ED/V1 */ - - u8500_clock_enable(1, 1, 1); /* UART1 */ - u8500_clock_enable(1, 0, 0); /* UART0 */ - - u8500_clock_enable(3, 2, 2); /* SSP1 */ - u8500_clock_enable(3, 1, 1); /* SSP0 */ - - u8500_clock_enable(2, 8, -1); /* SPI0 */ - u8500_clock_enable(2, 5, 3); /* MSP2 */ -} - -#ifdef CONFIG_MMC -static int u8500_mmci_board_init(void) -{ - enum gpio_error error; - struct gpio_register *gpio_base_address; - - gpio_base_address = (void *)(U8500_GPIO_0_BASE); - gpio_base_address->gpio_dats |= 0xFFC0000; - gpio_base_address->gpio_pdis &= ~0xFFC0000; - - /* save the GPIO0 AFSELA register */ - error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC"); - if (error != GPIO_OK) { - printf("u8500_mmci_board_init() gpio_altfuncenable failed\n"); - return -ENODEV; - } - return 0; -} - -int board_mmc_init(bd_t *bd) -{ - struct pl180_mmc_host *host; - - if (u8500_mmci_board_init()) - return -ENODEV; - - host = malloc(sizeof(struct pl180_mmc_host)); - if (!host) - return -ENOMEM; - memset(host, 0, sizeof(*host)); - - strcpy(host->name, "MMC"); - host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; - host->pwr_init = INIT_PWR; - host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; - host->voltages = VOLTAGE_WINDOW_MMC; - host->caps = 0; - host->clock_in = ARM_MCLK; - host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); - host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; - - return arm_pl180_mmci_init(host); -} -#endif - - -/* - * get_pll_freq_khz - return PLL frequency in kHz - */ -static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg) -{ - uint32_t idf, ldf, odf, seldiv, phi; - - /* - * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0 - * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1 - * where: - * IDF=R(2:0) (when R=000, IDF=1d) - * LDF = 2*D(7:0) (D must be greater than or equal to 6) - * ODF = N(5:0) (when N=000000, 0DF=1d) - */ - - idf = (freq_reg & 0x70000) >> 16; - ldf = (freq_reg & 0xff) * 2; - odf = (freq_reg & 0x3f00) >> 8; - seldiv = (freq_reg & 0x01000000) >> 24; - phi = (inclk_khz * ldf) / (2 * odf * idf); - if (seldiv) - phi = phi/2; - - return phi; -} - -int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uint32_t inclk_khz; - uint32_t reg, phi; - uint32_t clk_khz; - unsigned int clk_sel; - struct clk_mgt_regs *clks = clk_mgt_regs; - struct pll_freq_regs *plls = pll_freq_regs; - - /* - * Go through list of PLLs. - * Initialise pll out frequency array (pll_khz) and print frequency. - */ - inclk_khz = 38400; /* 38.4 MHz */ - while (plls->addr) { - reg = readl(plls->addr); - phi = get_pll_freq_khz(inclk_khz, reg); - pll_khz[plls->idx] = phi; - printf("%s PLL out frequency: %d.%d Mhz\n", - pll_name[plls->idx], phi/1000, phi % 1000); - plls++; - } - - /* check ARM clock source */ - reg = readl(PRCM_ARM_CHGCLKREQ_REG); - printf("A9 running on %s\n", - (reg & 1) ? "external clock" : "ARM PLL"); - - /* go through list of clk_mgt_reg */ - printf("\n%19s %9s %7s %9s enabled\n", - "name(addr)", "value", "PLL", "CLK[MHz]"); - while (clks->addr) { - reg = readl(clks->addr); - - /* convert bit position into array index */ - clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */ - - if (reg & 0x200) - clk_khz = 38400; /* CLK38 is set */ - else if ((reg & 0x1f) == 0) - /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */ - clk_khz = 0; - else - clk_khz = pll_khz[clk_sel] / (reg & 0x1f); - - printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n", - clks->descr, clks->addr, reg, pll_name[clk_sel], - clk_khz / 1000, clk_khz % 1000, - (reg & 0x100) ? "ena" : "dis"); - clks++; - } - - return 0; -} - -U_BOOT_CMD( - clkinfo, 1, 1, do_clkinfo, - "print clock info", - "" -); diff --git a/configs/snowball_defconfig b/configs/snowball_defconfig deleted file mode 100644 index e73bc48af11..00000000000 --- a/configs/snowball_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_SNOWBALL=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="U8500 $ " diff --git a/configs/u8500_href_defconfig b/configs/u8500_href_defconfig deleted file mode 100644 index 0aebc7846d9..00000000000 --- a/configs/u8500_href_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_U8500_HREF=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="U8500 $ " diff --git a/include/configs/snowball.h b/include/configs/snowball.h deleted file mode 100644 index de03e76ba19..00000000000 --- a/include/configs/snowball.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * #define DEBUG 1 - */ - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SNOWBALL -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOARD_LATE_INIT - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_U8500 - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF - -/*----------------------------------------------------------------------- - * Size of environment and malloc() pool - */ -/* - * If you use U-Boot as crash kernel, make sure that it does not overwrite - * information saved by kexec during panic. Kexec expects the start - * address of the executable 32K above "crashkernel" address. - */ -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_CMD_ENV -#define CONFIG_ENV_OFFSET 0x0118000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ - -/* - * PL011 Configuration - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_SERIAL_RLCR -#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT - -/* - * U8500 UART registers base for 3 serial devices - */ -#define CFG_UART0_BASE 0x80120000 -#define CFG_UART1_BASE 0x80121000 -#define CFG_UART2_BASE 0x80007000 -#define CFG_SERIAL0 CFG_UART0_BASE -#define CFG_SERIAL1 CFG_UART1_BASE -#define CFG_SERIAL2 CFG_UART2_BASE -#define CONFIG_PL011_CLOCK 38400000 -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ - (void *)CFG_SERIAL2 } -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Devices and file systems - */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION - -/* - * Commands - */ -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 1 -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ -"mmc dev 1; " \ - "if run loadbootscript; " \ - "then run bootscript; " \ - "else " \ - "if run mmcload; " \ - "then run mmcboot; " \ - "else " \ - "mmc dev 0; " \ - "if run emmcloadbootscript; " \ - "then run bootscript; " \ - "else " \ - "if run emmcload; " \ - "then run emmcboot; " \ - "else " \ - "echo No media to boot from; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi; " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=0x00100000\0" \ - "console=ttyAMA2,115200n8\0" \ - "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \ - "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript " \ - "from mmc ...; source ${loadaddr}\0" \ - "memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \ - "hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \ - "memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \ - "mem=64M@160M mem_mali=32M@224M " \ - "pmem_hwb=128M@256M mem=128M@384M\0" \ - "memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \ - "hwmem=168M@M160M mem=48M@328M " \ - "mem_issw=1M@383M mem=640M@384M\0" \ - "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \ - "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \ - "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \ - "commonargs=setenv bootargs console=${console} " \ - "vmalloc=300M\0" \ - "emmcargs=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p3 " \ - "rootwait\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console}\0" \ - "emmcboot=echo Booting from eMMC ...; " \ - "run commonargs emmcargs memargs; " \ - "bootm ${loadaddr}\0" \ - "mmcargs=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk1p2 " \ - "rootwait earlyprintk\0" \ - "mmcboot=echo Booting from external MMC ...; " \ - "run commonargs mmcargs memargs; " \ - "bootm ${loadaddr}\0" \ - "fdt_high=0x2BC00000\0" \ - "stdout=serial,usbtty\0" \ - "stdin=serial,usbtty\0" \ - "stderr=serial,usbtty\0" - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SETUP_MEMORY_TAGS 2 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ - -/* - * additions for new relocation code - */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* landing address before relocation */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x0 -#endif - -/* - * MMC related configs - */ -#define CONFIG_ARM_PL180_MMCI -#define MMC_BLOCK_SIZE 512 -#define CFG_EMMC_BASE 0x80114000 -#define CFG_MMC_BASE 0x80126000 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_NO_FLASH - -/* - * base register values for U8500 - */ -#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ - - -/* - * U8500 GPIO register base for 9 banks - */ -#define CONFIG_DB8500_GPIO -#define CFG_GPIO_0_BASE 0x8012E000 -#define CFG_GPIO_1_BASE 0x8012E080 -#define CFG_GPIO_2_BASE 0x8000E000 -#define CFG_GPIO_3_BASE 0x8000E080 -#define CFG_GPIO_4_BASE 0x8000E100 -#define CFG_GPIO_5_BASE 0x8000E180 -#define CFG_GPIO_6_BASE 0x8011E000 -#define CFG_GPIO_7_BASE 0x8011E080 -#define CFG_GPIO_8_BASE 0xA03FE000 - -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h deleted file mode 100644 index a8cc0306cb1..00000000000 --- a/include/configs/u8500_href.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_U8500 - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -/* - * Size of malloc() pool - */ -#ifdef CONFIG_BOOT_SRAM -#define CONFIG_ENV_SIZE (32*1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) -#else -#define CONFIG_ENV_SIZE (128*1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#endif - -/* - * PL011 Configuration - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_SERIAL_RLCR -#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT - -/* - * U8500 UART registers base for 3 serial devices - */ -#define CFG_UART0_BASE 0x80120000 -#define CFG_UART1_BASE 0x80121000 -#define CFG_UART2_BASE 0x80007000 -#define CFG_SERIAL0 CFG_UART0_BASE -#define CFG_SERIAL1 CFG_UART1_BASE -#define CFG_SERIAL2 CFG_UART2_BASE -#define CONFIG_PL011_CLOCK 38400000 -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ - (void *)CFG_SERIAL2 } -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Devices and file systems - */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION - -/* - * Commands - */ -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_I2C - -#ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 1 -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "run emmcboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=0x00100000\0" \ - "console=ttyAMA2,115200n8\0" \ - "memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \ - "pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \ - "memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \ - "pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \ - "pmem_hwb=54M@256M mem=202M@310M\0" \ - "commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \ - "init=init " \ - "board_id=${board_id} " \ - "logo.${logo} " \ - "startup_graphics=${startup_graphics}\0" \ - "emmcargs=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 " \ - "rootdelay=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console}\0" \ - "emmcboot=echo Booting from eMMC ...; " \ - "run commonargs emmcargs addcons memargs;" \ - "mmc read 0 ${loadaddr} 0xA0000 0x4000;" \ - "bootm ${loadaddr}\0" \ - "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \ - "source ${loadaddr}\0" \ - "loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \ - "usbtty=cdc_acm\0" \ - "stdout=serial,usbtty\0" \ - "stdin=serial,usbtty\0" \ - "stderr=serial,usbtty\0" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SETUP_MEMORY_TAGS 2 -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ - -/* - * I2C - */ -#define CONFIG_U8500_I2C -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */ -#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000 -#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000 -#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000 -#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000 -#define CONFIG_SYS_U8500_I2C_BUS_MAX 4 - -#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */ -#define CONFIG_TC35892_GPIO - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ -#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */ - -/* - * additions for new relocation code - */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* landing address before relocation */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x0 -#endif - -/* - * MMC related configs - * NB Only externa SD slot is currently supported - */ -#define MMC_BLOCK_SIZE 512 -#define CONFIG_ARM_PL180_MMCI -#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */ -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 -#define CONFIG_MMC_DEV_NUM 1 - -#define CONFIG_CMD_ENV -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET 0x13F80000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_NO_FLASH - -/* - * base register values for U8500 - */ -#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock - management unit */ -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 6761946fb716255c32908059de1e2a0d0e05afb1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:18:59 -0600 Subject: arm: Remove unmaintained davinci boards These boards have not been converted to generic board by the deadline. Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie, sffsdr, sonata. Signed-off-by: Simon Glass --- arch/arm/mach-davinci/Kconfig | 38 +----- board/davinci/dm355evm/Kconfig | 12 -- board/davinci/dm355evm/MAINTAINERS | 6 - board/davinci/dm355evm/Makefile | 10 -- board/davinci/dm355evm/config.mk | 11 -- board/davinci/dm355evm/dm355evm.c | 144 ------------------- board/davinci/dm355leopard/Kconfig | 12 -- board/davinci/dm355leopard/MAINTAINERS | 6 - board/davinci/dm355leopard/Makefile | 10 -- board/davinci/dm355leopard/config.mk | 6 - board/davinci/dm355leopard/dm355leopard.c | 86 ------------ board/davinci/dm365evm/Kconfig | 12 -- board/davinci/dm365evm/MAINTAINERS | 6 - board/davinci/dm365evm/Makefile | 10 -- board/davinci/dm365evm/config.mk | 11 -- board/davinci/dm365evm/dm365evm.c | 139 ------------------- board/davinci/dm6467evm/Kconfig | 12 -- board/davinci/dm6467evm/MAINTAINERS | 7 - board/davinci/dm6467evm/Makefile | 10 -- board/davinci/dm6467evm/config.mk | 2 - board/davinci/dm6467evm/dm6467evm.c | 76 ----------- board/davinci/dvevm/Kconfig | 12 -- board/davinci/dvevm/MAINTAINERS | 6 - board/davinci/dvevm/Makefile | 11 -- board/davinci/dvevm/board_init.S | 16 --- board/davinci/dvevm/config.mk | 39 ------ board/davinci/dvevm/dvevm.c | 91 ------------ board/davinci/schmoogie/Kconfig | 12 -- board/davinci/schmoogie/MAINTAINERS | 6 - board/davinci/schmoogie/Makefile | 11 -- board/davinci/schmoogie/board_init.S | 16 --- board/davinci/schmoogie/config.mk | 39 ------ board/davinci/schmoogie/schmoogie.c | 119 ---------------- board/davinci/sffsdr/Kconfig | 12 -- board/davinci/sffsdr/MAINTAINERS | 6 - board/davinci/sffsdr/Makefile | 11 -- board/davinci/sffsdr/board_init.S | 16 --- board/davinci/sffsdr/config.mk | 23 ---- board/davinci/sffsdr/sffsdr.c | 132 ------------------ board/davinci/sonata/Kconfig | 12 -- board/davinci/sonata/MAINTAINERS | 6 - board/davinci/sonata/Makefile | 11 -- board/davinci/sonata/board_init.S | 87 ------------ board/davinci/sonata/config.mk | 39 ------ board/davinci/sonata/sonata.c | 87 ------------ configs/davinci_dm355evm_defconfig | 9 -- configs/davinci_dm355leopard_defconfig | 9 -- configs/davinci_dm365evm_defconfig | 9 -- configs/davinci_dm6467Tevm_defconfig | 9 -- configs/davinci_dm6467evm_defconfig | 10 -- configs/davinci_dvevm_defconfig | 9 -- configs/davinci_schmoogie_defconfig | 9 -- configs/davinci_sffsdr_defconfig | 9 -- configs/davinci_sonata_defconfig | 7 - include/configs/davinci_dm355evm.h | 195 -------------------------- include/configs/davinci_dm355leopard.h | 140 ------------------- include/configs/davinci_dm365evm.h | 220 ------------------------------ include/configs/davinci_dm6467evm.h | 138 ------------------- include/configs/davinci_dvevm.h | 216 ----------------------------- include/configs/davinci_schmoogie.h | 136 ------------------ include/configs/davinci_sffsdr.h | 129 ------------------ include/configs/davinci_sonata.h | 187 ------------------------- 62 files changed, 3 insertions(+), 2884 deletions(-) delete mode 100644 board/davinci/dm355evm/Kconfig delete mode 100644 board/davinci/dm355evm/MAINTAINERS delete mode 100644 board/davinci/dm355evm/Makefile delete mode 100644 board/davinci/dm355evm/config.mk delete mode 100644 board/davinci/dm355evm/dm355evm.c delete mode 100644 board/davinci/dm355leopard/Kconfig delete mode 100644 board/davinci/dm355leopard/MAINTAINERS delete mode 100644 board/davinci/dm355leopard/Makefile delete mode 100644 board/davinci/dm355leopard/config.mk delete mode 100644 board/davinci/dm355leopard/dm355leopard.c delete mode 100644 board/davinci/dm365evm/Kconfig delete mode 100644 board/davinci/dm365evm/MAINTAINERS delete mode 100644 board/davinci/dm365evm/Makefile delete mode 100644 board/davinci/dm365evm/config.mk delete mode 100644 board/davinci/dm365evm/dm365evm.c delete mode 100644 board/davinci/dm6467evm/Kconfig delete mode 100644 board/davinci/dm6467evm/MAINTAINERS delete mode 100644 board/davinci/dm6467evm/Makefile delete mode 100644 board/davinci/dm6467evm/config.mk delete mode 100644 board/davinci/dm6467evm/dm6467evm.c delete mode 100644 board/davinci/dvevm/Kconfig delete mode 100644 board/davinci/dvevm/MAINTAINERS delete mode 100644 board/davinci/dvevm/Makefile delete mode 100644 board/davinci/dvevm/board_init.S delete mode 100644 board/davinci/dvevm/config.mk delete mode 100644 board/davinci/dvevm/dvevm.c delete mode 100644 board/davinci/schmoogie/Kconfig delete mode 100644 board/davinci/schmoogie/MAINTAINERS delete mode 100644 board/davinci/schmoogie/Makefile delete mode 100644 board/davinci/schmoogie/board_init.S delete mode 100644 board/davinci/schmoogie/config.mk delete mode 100644 board/davinci/schmoogie/schmoogie.c delete mode 100644 board/davinci/sffsdr/Kconfig delete mode 100644 board/davinci/sffsdr/MAINTAINERS delete mode 100644 board/davinci/sffsdr/Makefile delete mode 100644 board/davinci/sffsdr/board_init.S delete mode 100644 board/davinci/sffsdr/config.mk delete mode 100644 board/davinci/sffsdr/sffsdr.c delete mode 100644 board/davinci/sonata/Kconfig delete mode 100644 board/davinci/sonata/MAINTAINERS delete mode 100644 board/davinci/sonata/Makefile delete mode 100644 board/davinci/sonata/board_init.S delete mode 100644 board/davinci/sonata/config.mk delete mode 100644 board/davinci/sonata/sonata.c delete mode 100644 configs/davinci_dm355evm_defconfig delete mode 100644 configs/davinci_dm355leopard_defconfig delete mode 100644 configs/davinci_dm365evm_defconfig delete mode 100644 configs/davinci_dm6467Tevm_defconfig delete mode 100644 configs/davinci_dm6467evm_defconfig delete mode 100644 configs/davinci_dvevm_defconfig delete mode 100644 configs/davinci_schmoogie_defconfig delete mode 100644 configs/davinci_sffsdr_defconfig delete mode 100644 configs/davinci_sonata_defconfig delete mode 100644 include/configs/davinci_dm355evm.h delete mode 100644 include/configs/davinci_dm355leopard.h delete mode 100644 include/configs/davinci_dm365evm.h delete mode 100644 include/configs/davinci_dm6467evm.h delete mode 100644 include/configs/davinci_dvevm.h delete mode 100644 include/configs/davinci_schmoogie.h delete mode 100644 include/configs/davinci_sffsdr.h delete mode 100644 include/configs/davinci_sonata.h (limited to 'include') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 681270ddd2e..4997b2ce54d 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -18,36 +18,12 @@ config TARGET_DA850EVM bool "DA850 EVM board" select SUPPORT_SPL -config TARGET_OMAPL138_LCDK - bool "OMAPL138 LCDK" - select SUPPORT_SPL - -config TARGET_DAVINCI_DM355EVM - bool "DM355 EVM board" - -config TARGET_DAVINCI_DM355LEOPARD - bool "DM355 Leopard board" - -config TARGET_DAVINCI_DM365EVM - bool "DM365 EVM board" - -config TARGET_DAVINCI_DM6467EVM - bool "DM6467 EVM board" - -config TARGET_DAVINCI_DVEVM - bool "DVEVM board" - config TARGET_EA20 bool "EA20 board" -config TARGET_DAVINCI_SCHMOOGIE - bool "Schmoogie board" - -config TARGET_DAVINCI_SFFSDR - bool "SFFSDR board" - -config TARGET_DAVINCI_SONATA - bool "Sonata board" +config TARGET_OMAPL138_LCDK + bool "OMAPL138 LCDK" + select SUPPORT_SPL config TARGET_CALIMAIN bool "Calimain board" @@ -60,15 +36,7 @@ config SYS_SOC source "board/enbw/enbw_cmc/Kconfig" source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" -source "board/davinci/dm355evm/Kconfig" -source "board/davinci/dm355leopard/Kconfig" -source "board/davinci/dm365evm/Kconfig" -source "board/davinci/dm6467evm/Kconfig" -source "board/davinci/dvevm/Kconfig" source "board/davinci/ea20/Kconfig" -source "board/davinci/schmoogie/Kconfig" -source "board/davinci/sffsdr/Kconfig" -source "board/davinci/sonata/Kconfig" source "board/omicron/calimain/Kconfig" endif diff --git a/board/davinci/dm355evm/Kconfig b/board/davinci/dm355evm/Kconfig deleted file mode 100644 index ec2c27623de..00000000000 --- a/board/davinci/dm355evm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_DM355EVM - -config SYS_BOARD - default "dm355evm" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_dm355evm" - -endif diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS deleted file mode 100644 index c017e097178..00000000000 --- a/board/davinci/dm355evm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DM355EVM BOARD -#M: Sandeep Paulraj -S: Orphan (since 2014-08) -F: board/davinci/dm355evm/ -F: include/configs/davinci_dm355evm.h -F: configs/davinci_dm355evm_defconfig diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile deleted file mode 100644 index bcb7e6fed54..00000000000 --- a/board/davinci/dm355evm/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dm355evm.o diff --git a/board/davinci/dm355evm/config.mk b/board/davinci/dm355evm/config.mk deleted file mode 100644 index 9a063000c32..00000000000 --- a/board/davinci/dm355evm/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Spectrum Digital DM355 EVM board -# dm355evm board has 1 bank of 128 MB DDR RAM -# Physical Address: 8000'0000 to 8800'0000 -# -# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# - -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c deleted file mode 100644 index e5a958f7e0c..00000000000 --- a/board/davinci/dm355evm/dm355evm.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2009 David Brownell - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_DAVINCI_MMC -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * With the DM355 EVM, u-boot is *always* a third stage loader, - * unless a JTAG debugger handles the first two stages: - * - * - 1st stage is ROM Boot Loader (RBL), which searches for a - * second stage loader in one of three places based on SW7: - * NAND (with MMC/SD fallback), MMC/SD, or UART. - * - * - 2nd stage is User Boot Loader (UBL), using at most 30KB - * of on-chip SRAM, responsible for lowlevel init, and for - * loading the third stage loader into DRAM. - * - * - 3rd stage, that's us! - */ - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* We expect the UBL to have handled "lowlevel init", which - * involves setting up at least: - * - clocks - * + PLL1 (for ARM and peripherals) and PLL2 (for DDR) - * + clock divisors for those PLLs - * + LPSC_DDR module enabled - * + LPSC_TIMER0 module (still) enabled - * - EMIF - * + DDR init and timings - * + AEMIF timings (for NAND and DM9000) - * - pinmux - * - * Some of that is repeated here, mostly as a precaution. - */ - - /* AEMIF: Some "address" lines are available as GPIOs. A3..A13 - * could be too if we used A12 as a GPIO during NAND chipselect - * (and Linux did too), letting us control the LED on A7/GPIO61. - */ - REG(PINMUX2) = 0x0c08; - - /* UART0 may still be in SyncReset if we didn't boot from UART */ - davinci_enable_uart0(); - - /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */ - lpsc_on(DAVINCI_LPSC_TPCC); - lpsc_on(DAVINCI_LPSC_TPTC0); - lpsc_on(DAVINCI_LPSC_TPTC1); - - return 0; -} - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif - -#ifdef CONFIG_NAND_DAVINCI - -static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *this = mtd->priv; - unsigned long wbase = (unsigned long) this->IO_ADDR_W; - unsigned long rbase = (unsigned long) this->IO_ADDR_R; - - if (chip == 1) { - __set_bit(14, &wbase); - __set_bit(14, &rbase); - } else { - __clear_bit(14, &wbase); - __clear_bit(14, &rbase); - } - this->IO_ADDR_W = (void *)wbase; - this->IO_ADDR_R = (void *)rbase; -} - -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - nand->select_chip = nand_dm355evm_select_chip; - return 0; -} - -#endif - -#ifdef CONFIG_DAVINCI_MMC -static struct davinci_mmc mmc_sd0 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, - .input_clk = 108000000, - .host_caps = MMC_MODE_4BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_1, -}; - -#ifdef CONFIG_DAVINCI_MMC_SD1 -static struct davinci_mmc mmc_sd1 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, - .input_clk = 108000000, - .host_caps = MMC_MODE_4BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_1, -}; -#endif - -int board_mmc_init(bd_t *bis) -{ - int err; - - /* Add slot-0 to mmc subsystem */ - err = davinci_mmc_init(bis, &mmc_sd0); - if (err) - return err; - -#ifdef CONFIG_DAVINCI_MMC_SD1 - /* Add slot-1 to mmc subsystem */ - err = davinci_mmc_init(bis, &mmc_sd1); -#endif - - return err; -} -#endif diff --git a/board/davinci/dm355leopard/Kconfig b/board/davinci/dm355leopard/Kconfig deleted file mode 100644 index ab4230a637a..00000000000 --- a/board/davinci/dm355leopard/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_DM355LEOPARD - -config SYS_BOARD - default "dm355leopard" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_dm355leopard" - -endif diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS deleted file mode 100644 index ed04d4354bd..00000000000 --- a/board/davinci/dm355leopard/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DM355LEOPARD BOARD -#M: Sandeep Paulraj -S: Orphan (since 2014-08) -F: board/davinci/dm355leopard/ -F: include/configs/davinci_dm355leopard.h -F: configs/davinci_dm355leopard_defconfig diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile deleted file mode 100644 index 7035429c921..00000000000 --- a/board/davinci/dm355leopard/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dm355leopard.o diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk deleted file mode 100644 index 28ff3f3d97f..00000000000 --- a/board/davinci/dm355leopard/config.mk +++ /dev/null @@ -1,6 +0,0 @@ -# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# - -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c deleted file mode 100644 index 53902f996c7..00000000000 --- a/board/davinci/dm355leopard/dm355leopard.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - struct davinci_gpio *gpio01_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK01; - struct davinci_gpio *gpio23_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK23; - struct davinci_gpio *gpio67_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK67; - - gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* GIO 9 & 10 are used for IO */ - writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3); - - /* Interrupt set GIO 9 */ - writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN); - - /* set GIO 9 input */ - writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir); - - /* Both edge trigger GIO 9 */ - writel((readl(&gpio01_base->set_rising) | (1 << 9)), - &gpio01_base->set_rising); - writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir); - - /* output low */ - writel((readl(&gpio01_base->set_data) & ~(1 << 5)), - &gpio01_base->set_data); - - /* set GIO 10 output */ - writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir); - - /* output high */ - writel((readl(&gpio01_base->set_data) | (1 << 10)), - &gpio01_base->set_data); - - /* set GIO 32 output */ - writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir); - - /* output High */ - writel((readl(&gpio23_base->set_data) | (1 << 0)), - &gpio23_base->set_data); - - /* Enable UART1 MUX Lines */ - writel((readl(PINMUX0) & ~3), PINMUX0); - writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir); - writel((readl(&gpio67_base->set_data) | (1 << 6)), - &gpio67_base->set_data); - - return 0; -} - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif - -#ifdef CONFIG_NAND_DAVINCI -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - - return 0; -} -#endif diff --git a/board/davinci/dm365evm/Kconfig b/board/davinci/dm365evm/Kconfig deleted file mode 100644 index 724c7b6204c..00000000000 --- a/board/davinci/dm365evm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_DM365EVM - -config SYS_BOARD - default "dm365evm" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_dm365evm" - -endif diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS deleted file mode 100644 index 97c3ed3b69d..00000000000 --- a/board/davinci/dm365evm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DM365EVM BOARD -#M: Sandeep Paulraj -S: Orphan (since 2014-08) -F: board/davinci/dm365evm/ -F: include/configs/davinci_dm365evm.h -F: configs/davinci_dm365evm_defconfig diff --git a/board/davinci/dm365evm/Makefile b/board/davinci/dm365evm/Makefile deleted file mode 100644 index d35d81c2bfd..00000000000 --- a/board/davinci/dm365evm/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dm365evm.o diff --git a/board/davinci/dm365evm/config.mk b/board/davinci/dm365evm/config.mk deleted file mode 100644 index 7b1e900e8c6..00000000000 --- a/board/davinci/dm365evm/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Spectrum Digital DM365 EVM board -# DM365 EVM board has 1 bank of 128 MB DDR RAM -# Physical Address: 8000'0000 to 8800'0000 -# -# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# - -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c deleted file mode 100644 index 24bec56d568..00000000000 --- a/board/davinci/dm365evm/dm365evm.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_DAVINCI_MMC -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -int board_eth_init(bd_t *bis) -{ - uint8_t eeprom_enetaddr[6]; - int i; - struct davinci_gpio *gpio1_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK01; - - /* Configure PINMUX 3 to enable EMAC pins */ - writel((readl(PINMUX3) | 0x1affff), PINMUX3); - - /* Configure GPIO20 as output */ - writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir); - - /* Toggle GPIO 20 */ - for (i = 0; i < 20; i++) { - /* GPIO 20 low */ - writel((readl(&gpio1_base->out_data) & ~(1 << 20)), - &gpio1_base->out_data); - - udelay(1000); - - /* GPIO 20 high */ - writel((readl(&gpio1_base->out_data) | (1 << 20)), - &gpio1_base->out_data); - } - - /* Configure I2C pins so that EEPROM can be read */ - writel((readl(PINMUX3) | 0x01400000), PINMUX3); - - /* Read Ethernet MAC address from EEPROM */ - if (dvevm_read_mac_address(eeprom_enetaddr)) - davinci_sync_env_enetaddr(eeprom_enetaddr); - - davinci_emac_initialize(); - - return 0; -} -#endif - -#ifdef CONFIG_NAND_DAVINCI -static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *this = mtd->priv; - unsigned long wbase = (unsigned long) this->IO_ADDR_W; - unsigned long rbase = (unsigned long) this->IO_ADDR_R; - - if (chip == 1) { - __set_bit(14, &wbase); - __set_bit(14, &rbase); - } else { - __clear_bit(14, &wbase); - __clear_bit(14, &rbase); - } - this->IO_ADDR_W = (void *)wbase; - this->IO_ADDR_R = (void *)rbase; -} - -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - nand->select_chip = nand_dm365evm_select_chip; - return 0; -} -#endif - -#ifdef CONFIG_DAVINCI_MMC -static struct davinci_mmc mmc_sd0 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, - .input_clk = 121500000, - .host_caps = MMC_MODE_4BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_2, -}; - -#ifdef CONFIG_DAVINCI_MMC_SD1 -static struct davinci_mmc mmc_sd1 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, - .input_clk = 121500000, - .host_caps = MMC_MODE_4BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_2, -}; -#endif - -int board_mmc_init(bd_t *bis) -{ - int err; - - /* Add slot-0 to mmc subsystem */ - err = davinci_mmc_init(bis, &mmc_sd0); - if (err) - return err; - -#ifdef CONFIG_DAVINCI_MMC_SD1 -#define PUPDCTL1 0x01c4007c - /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */ - writel((readl(PINMUX4) | 0x55400000), PINMUX4); - writel((readl(PINMUX0) | 0x00010000), PINMUX0); - - /* Configure MMC/SD pins as pullup */ - writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1); - - /* Add slot-1 to mmc subsystem */ - err = davinci_mmc_init(bis, &mmc_sd1); -#endif - - return err; -} -#endif diff --git a/board/davinci/dm6467evm/Kconfig b/board/davinci/dm6467evm/Kconfig deleted file mode 100644 index 56d2ab487d6..00000000000 --- a/board/davinci/dm6467evm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_DM6467EVM - -config SYS_BOARD - default "dm6467evm" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_dm6467evm" - -endif diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS deleted file mode 100644 index 8ca53c43c80..00000000000 --- a/board/davinci/dm6467evm/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -DM6467EVM BOARD -#M: Sandeep Paulraj -S: Orphan (since 2014-08) -F: board/davinci/dm6467evm/ -F: include/configs/davinci_dm6467evm.h -F: configs/davinci_dm6467evm_defconfig -F: configs/davinci_dm6467Tevm_defconfig diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile deleted file mode 100644 index acbbdd50323..00000000000 --- a/board/davinci/dm6467evm/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dm6467evm.o diff --git a/board/davinci/dm6467evm/config.mk b/board/davinci/dm6467evm/config.mk deleted file mode 100644 index 37510438900..00000000000 --- a/board/davinci/dm6467evm/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c deleted file mode 100644 index e51cc9e6389..00000000000 --- a/board/davinci/dm6467evm/dm6467evm.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define REV_DM6467EVM 0 -#define REV_DM6467TEVM 1 -/* - * get_board_rev() - setup to pass kernel board revision information - * Returns: - * bit[0-3] System clock frequency - * 0000b - 27 MHz - * 0001b - 33 MHz - */ -u32 get_board_rev(void) -{ - -#ifdef CONFIG_DAVINCI_DM6467TEVM - return REV_DM6467TEVM; -#else - return REV_DM6467EVM; -#endif - -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - lpsc_on(DAVINCI_DM646X_LPSC_TIMER0); - lpsc_on(DAVINCI_DM646X_LPSC_UART0); - lpsc_on(DAVINCI_DM646X_LPSC_I2C); - lpsc_on(DAVINCI_DM646X_LPSC_EMAC); - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0x80000c0; - - /* Select UART function on UART0 */ - REG(PINMUX0) &= ~(0x0000003f << 18); - REG(PINMUX1) &= ~(0x00000003); - - return 0; -} - -#if defined(CONFIG_DRIVER_TI_EMAC) - -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#ifdef CONFIG_NAND_DAVINCI -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - - return 0; -} -#endif diff --git a/board/davinci/dvevm/Kconfig b/board/davinci/dvevm/Kconfig deleted file mode 100644 index 3f0ef822157..00000000000 --- a/board/davinci/dvevm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_DVEVM - -config SYS_BOARD - default "dvevm" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_dvevm" - -endif diff --git a/board/davinci/dvevm/MAINTAINERS b/board/davinci/dvevm/MAINTAINERS deleted file mode 100644 index a718b900508..00000000000 --- a/board/davinci/dvevm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DVEVM BOARD -#M: - -S: Maintained -F: board/davinci/dvevm/ -F: include/configs/davinci_dvevm.h -F: configs/davinci_dvevm_defconfig diff --git a/board/davinci/dvevm/Makefile b/board/davinci/dvevm/Makefile deleted file mode 100644 index 7ade3259683..00000000000 --- a/board/davinci/dvevm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dvevm.o -obj-y += board_init.o diff --git a/board/davinci/dvevm/board_init.S b/board/davinci/dvevm/board_init.S deleted file mode 100644 index ded0590084f..00000000000 --- a/board/davinci/dvevm/board_init.S +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Board-specific low level initialization code. Called at the very end - * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no - * initialization required. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl dv_board_init -dv_board_init: - - mov pc, lr diff --git a/board/davinci/dvevm/config.mk b/board/davinci/dvevm/config.mk deleted file mode 100644 index ed807072313..00000000000 --- a/board/davinci/dvevm/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Swaminathan -# -# Davinci EVM board (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Davinci EVM has 1 bank of 256 MB DDR RAM -# Physical Address: -# 8000'0000 to 9000'0000 -# -# Copyright (C) 2007 Sergey Kubushyn -# -# Visioneering Corp. Sonata board (ARM926EJS) cpu -# -# Sonata board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 8800'0000 -# -# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu -# -# Schmoogie board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 8800'0000 -# -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# -# we load ourself to 8108 '0000 -# -# - -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c deleted file mode 100644 index c34bde4fa60..00000000000 --- a/board/davinci/dvevm/dvevm.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * ----------------------------------------------------------------- - * - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - * ---------------------------------------------------------------------------- - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* Configure AEMIF pins (although this should be configured at boot time - * with pull-up/pull-down resistors) */ - REG(PINMUX0) = 0x00000c1f; - - davinci_errata_workarounds(); - - /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_GPIO); - lpsc_on(DAVINCI_LPSC_USB); - -#if !defined(CONFIG_SYS_USE_DSPLINK) - /* Powerup the DSP */ - dsp_on(); -#endif /* CONFIG_SYS_USE_DSPLINK */ - - davinci_enable_uart0(); - davinci_enable_emac(); - davinci_enable_i2c(); - - lpsc_on(DAVINCI_LPSC_TIMER1); - timer_init(); - - return(0); -} - -int misc_init_r(void) -{ - uint8_t video_mode; - uint8_t eeprom_enetaddr[6]; - - /* Read Ethernet MAC address from EEPROM if available. */ - if (dvevm_read_mac_address(eeprom_enetaddr)) - davinci_sync_env_enetaddr(eeprom_enetaddr); - - i2c_read(0x39, 0x00, 1, &video_mode, 1); - - setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc")); - - return(0); -} - -#ifdef CONFIG_USB_DAVINCI - -/* IO Expander I2C address and USB VBUS enable mask */ -#define IOEXP_I2C_ADDR 0x3A -#define IOEXP_VBUSEN_MASK 1 - -/* - * This function enables USB VBUS by writting to IO expander using I2C. - * Note that the I2C is already initialized at this stage. This - * function is used by davinci specific USB wrapper code. - */ -void enable_vbus(void) -{ - uchar data; /* IO Expander data to enable VBUS */ - - /* Write to IO expander to enable VBUS */ - i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1); - data &= ~IOEXP_VBUSEN_MASK; - i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1); -} -#endif diff --git a/board/davinci/schmoogie/Kconfig b/board/davinci/schmoogie/Kconfig deleted file mode 100644 index 35810755f96..00000000000 --- a/board/davinci/schmoogie/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_SCHMOOGIE - -config SYS_BOARD - default "schmoogie" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_schmoogie" - -endif diff --git a/board/davinci/schmoogie/MAINTAINERS b/board/davinci/schmoogie/MAINTAINERS deleted file mode 100644 index 808e7fc0468..00000000000 --- a/board/davinci/schmoogie/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SCHMOOGIE BOARD -#M: - -S: Maintained -F: board/davinci/schmoogie/ -F: include/configs/davinci_schmoogie.h -F: configs/davinci_schmoogie_defconfig diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile deleted file mode 100644 index e170d551ff2..00000000000 --- a/board/davinci/schmoogie/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := schmoogie.o -obj-y += board_init.o diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S deleted file mode 100644 index ded0590084f..00000000000 --- a/board/davinci/schmoogie/board_init.S +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Board-specific low level initialization code. Called at the very end - * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no - * initialization required. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl dv_board_init -dv_board_init: - - mov pc, lr diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk deleted file mode 100644 index ed807072313..00000000000 --- a/board/davinci/schmoogie/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Swaminathan -# -# Davinci EVM board (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Davinci EVM has 1 bank of 256 MB DDR RAM -# Physical Address: -# 8000'0000 to 9000'0000 -# -# Copyright (C) 2007 Sergey Kubushyn -# -# Visioneering Corp. Sonata board (ARM926EJS) cpu -# -# Sonata board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 8800'0000 -# -# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu -# -# Schmoogie board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 8800'0000 -# -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# -# we load ourself to 8108 '0000 -# -# - -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c deleted file mode 100644 index 741afc4df3f..00000000000 --- a/board/davinci/schmoogie/schmoogie.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * ----------------------------------------------------------------- - * - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - * ---------------------------------------------------------------------------- - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* Configure AEMIF pins (although this should be configured at boot time - * with pull-up/pull-down resistors) */ - REG(PINMUX0) = 0x00000c1f; - - davinci_errata_workarounds(); - - /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_GPIO); - -#if !defined(CONFIG_SYS_USE_DSPLINK) - /* Powerup the DSP */ - dsp_on(); -#endif /* CONFIG_SYS_USE_DSPLINK */ - - davinci_enable_uart0(); - davinci_enable_emac(); - davinci_enable_i2c(); - - lpsc_on(DAVINCI_LPSC_TIMER1); - timer_init(); - - return(0); -} - -int misc_init_r(void) -{ - u_int8_t tmp[20], buf[10]; - int i = 0; - - /* Set serial number from UID chip */ - const u_int8_t crc_tbl[256] = { - 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, - 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, - 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, - 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, - 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, - 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62, - 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, - 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, - 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, - 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, - 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58, - 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, - 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, - 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, - 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, - 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, - 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f, - 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, - 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, - 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50, - 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, - 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, - 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1, - 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, - 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, - 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, - 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, - 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, - 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a, - 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, - 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, - 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 - }; - - /* Set serial number from UID chip */ - if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) { - printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR); - setenv("serial#", "FAILED"); - } else { - if (buf[0] != 0x70) { - /* Device Family Code */ - printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR); - setenv("serial#", "FAILED"); - } - } - /* Now check CRC */ - tmp[0] = 0; - for (i = 0; i < 8; i++) - tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; - - if (tmp[0] != 0) { - printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR); - setenv("serial#", "FAILED"); - } else { - /* CRC OK, set "serial" env variable */ - sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x", - buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); - setenv("serial#", (char *)&tmp[0]); - } - - return(0); -} diff --git a/board/davinci/sffsdr/Kconfig b/board/davinci/sffsdr/Kconfig deleted file mode 100644 index dc48f3118c1..00000000000 --- a/board/davinci/sffsdr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_SFFSDR - -config SYS_BOARD - default "sffsdr" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_sffsdr" - -endif diff --git a/board/davinci/sffsdr/MAINTAINERS b/board/davinci/sffsdr/MAINTAINERS deleted file mode 100644 index 5c7e1324a9f..00000000000 --- a/board/davinci/sffsdr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SFFSDR BOARD -#M: - -S: Maintained -F: board/davinci/sffsdr/ -F: include/configs/davinci_sffsdr.h -F: configs/davinci_sffsdr_defconfig diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile deleted file mode 100644 index 4ab30a4061f..00000000000 --- a/board/davinci/sffsdr/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := sffsdr.o -obj-y += board_init.o diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S deleted file mode 100644 index ded0590084f..00000000000 --- a/board/davinci/sffsdr/board_init.S +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Board-specific low level initialization code. Called at the very end - * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no - * initialization required. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl dv_board_init -dv_board_init: - - mov pc, lr diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk deleted file mode 100644 index 4fe900799dd..00000000000 --- a/board/davinci/sffsdr/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# Copyright (C) 2008 Lyrtech -# Copyright (C) 2008 Philip Balister, OpenSDR -# -# Lyrtech SFF SDR board (ARM926EJS) cpu -# -# SFF SDR board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 87FF'FFFF -# -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# -# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0, -# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc). -# -# we load ourself to 8400'0000 to provide at least 32MB spacing -# between us and the Integrity kernel image -CONFIG_SYS_TEXT_BASE = 0x84000000 diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c deleted file mode 100644 index f6ab91e6ff5..00000000000 --- a/board/davinci/sffsdr/sffsdr.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Copyright (C) 2008 Lyrtech - * Copyright (C) 2008 Philip Balister, OpenSDR - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * - * Copyright (C) 2004 Texas Instruments. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ -#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ - -#define INTEGRITY_SYSCFG_OFFSET 0x7E8 -#define INTEGRITY_CHECKWORD_OFFSET 0x7F8 -#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - davinci_errata_workarounds(); - - /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_GPIO); - -#if !defined(CONFIG_SYS_USE_DSPLINK) - /* Powerup the DSP */ - dsp_on(); -#endif /* CONFIG_SYS_USE_DSPLINK */ - - davinci_enable_uart0(); - davinci_enable_emac(); - davinci_enable_i2c(); - - lpsc_on(DAVINCI_LPSC_TIMER1); - timer_init(); - - return(0); -} - -/* Read ethernet MAC address from Integrity data structure inside EEPROM. - * Returns 1 if found, 0 otherwise. - */ -static int sffsdr_read_mac_address(uint8_t *buf) -{ - u_int32_t value, mac[2], address; - - /* Read Integrity data structure checkword. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) - goto err; - if (value != INTEGRITY_CHECKWORD_VALUE) - return 0; - - /* Read SYSCFG structure offset. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) - goto err; - address = 0x800 + (int) value; /* Address of SYSCFG structure. */ - - /* Read NET CONFIG structure offset. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) - goto err; - address = 0x800 + (int) value; /* Address of NET CONFIG structure. */ - address += 12; /* Address of NET INTERFACE CONFIG structure. */ - - /* Read NET INTERFACE CONFIG 2 structure offset. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) - goto err; - address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE - * CONFIG 2 structure. */ - - /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) - goto err; - - buf[0] = mac[0] >> 24; - buf[1] = mac[0] >> 16; - buf[2] = mac[0] >> 8; - buf[3] = mac[0]; - buf[4] = mac[1] >> 24; - buf[5] = mac[1] >> 16; - - return 1; /* Found */ - -err: - printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); - return 0; -} - -/* Platform dependent initialisation. */ -int misc_init_r(void) -{ - uint8_t i2cbuf; - uint8_t eeprom_enetaddr[6]; - - /* EMIF-A CS3 configuration for FPGA. */ - REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; - - /* Configure I2C switch (PCA9543) to enable channel 0. */ - i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0; - if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0, - CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { - printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR); - return 1; - } - - /* Read Ethernet MAC address from EEPROM if available. */ - if (sffsdr_read_mac_address(eeprom_enetaddr)) - davinci_sync_env_enetaddr(eeprom_enetaddr); - - return(0); -} diff --git a/board/davinci/sonata/Kconfig b/board/davinci/sonata/Kconfig deleted file mode 100644 index 4440d95bc27..00000000000 --- a/board/davinci/sonata/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DAVINCI_SONATA - -config SYS_BOARD - default "sonata" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "davinci_sonata" - -endif diff --git a/board/davinci/sonata/MAINTAINERS b/board/davinci/sonata/MAINTAINERS deleted file mode 100644 index 40659e5210f..00000000000 --- a/board/davinci/sonata/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SONATA BOARD -#M: - -S: Maintained -F: board/davinci/sonata/ -F: include/configs/davinci_sonata.h -F: configs/davinci_sonata_defconfig diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile deleted file mode 100644 index 92e1a180c01..00000000000 --- a/board/davinci/sonata/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := sonata.o -obj-y += board_init.o diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S deleted file mode 100644 index 0a47ad5ebbd..00000000000 --- a/board/davinci/sonata/board_init.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Board-specific low level initialization code. Called at the very end - * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no - * initialization required. - * - * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer - * Sonata boards, AFAIK, don't use this so it's just return by default. Ask - * Visioneering if they reinvented the wheel once again to make sure :) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl dv_board_init -dv_board_init: -#ifdef SONATA_BOARD_GPIOWP - /* Set PINMUX0 to enable GPIO4 */ - ldr r0, _PINMUX0 - ldr r1, GPIO4_EN_MASK - ldr r2, [r0] - and r2, r2, r1 - str r2, [r0] - - /* Enable GPIO LPSC module */ - ldr r0, PTSTAT - -gpio_ptstat_loop1: - ldr r2, [r0] - tst r2, $0x00000001 - bne gpio_ptstat_loop1 - - ldr r1, MDCTL_GPIO - ldr r2, [r1] - and r2, r2, $0xfffffff8 - orr r2, r2, $0x00000003 - str r2, [r1] - - orr r2, r2, $0x00000200 - str r2, [r1] - - ldr r1, PTCMD - mov r2, $0x00000001 - str r2, [r1] - -gpio_ptstat_loop2: - ldr r2, [r0] - tst r2, $0x00000001 - bne gpio_ptstat_loop2 - - ldr r0, MDSTAT_GPIO -gpio_mdstat_loop: - ldr r2, [r0] - and r2, r2, $0x0000001f - teq r2, $0x00000003 - bne gpio_mdstat_loop - - /* GPIO4 -> output */ - ldr r0, GPIO_DIR01 - mov r1, $0x10 - ldr r2, [r0] - bic r2, r2, r0 - str r2, [r0] - - /* Set it to 0 (Write Protect) */ - ldr r0, GPIO_CLR_DATA01 - str r1, [r0] -#endif - - mov pc, lr - -#ifdef SONATA_BOARD_GPIOWP -.ltorg - -GPIO4_EN_MASK: - .word 0xf77fffff -MDCTL_GPIO: - .word 0x01c41a68 -MDSTAT_GPIO: - .word 0x01c41868 -GPIO_DIR01: - .word 0x01c67010 -GPIO_CLR_DATA01: - .word 0x01c6701c -#endif diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk deleted file mode 100644 index ed807072313..00000000000 --- a/board/davinci/sonata/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Swaminathan -# -# Davinci EVM board (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Davinci EVM has 1 bank of 256 MB DDR RAM -# Physical Address: -# 8000'0000 to 9000'0000 -# -# Copyright (C) 2007 Sergey Kubushyn -# -# Visioneering Corp. Sonata board (ARM926EJS) cpu -# -# Sonata board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 8800'0000 -# -# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu -# -# Schmoogie board has 1 bank of 128 MB DDR RAM -# Physical Address: -# 8000'0000 to 8800'0000 -# -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# -# we load ourself to 8108 '0000 -# -# - -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SYS_TEXT_BASE = 0x81080000 diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c deleted file mode 100644 index f5c3258de56..00000000000 --- a/board/davinci/sonata/sonata.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * ----------------------------------------------------------------- - * - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - * ---------------------------------------------------------------------------- - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* Configure AEMIF pins (although this should be configured at boot time - * with pull-up/pull-down resistors) */ - REG(PINMUX0) = 0x00000c1f; - - davinci_errata_workarounds(); - - /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_GPIO); - -#if !defined(CONFIG_SYS_USE_DSPLINK) - /* Powerup the DSP */ - dsp_on(); -#endif /* CONFIG_SYS_USE_DSPLINK */ - - davinci_enable_uart0(); - davinci_enable_emac(); - davinci_enable_i2c(); - - lpsc_on(DAVINCI_LPSC_TIMER1); - timer_init(); - - return(0); -} - -int misc_init_r(void) -{ - uint8_t eeprom_enetaddr[6]; - - /* Read Ethernet MAC address from EEPROM if available. */ - if (dvevm_read_mac_address(eeprom_enetaddr)) - davinci_sync_env_enetaddr(eeprom_enetaddr); - - return(0); -} - -#ifdef CONFIG_NAND_DAVINCI - -/* Set WP on deselect, write enable on select */ -static void nand_sonata_select_chip(struct mtd_info *mtd, int chip) -{ -#define GPIO_SET_DATA01 0x01c67018 -#define GPIO_CLR_DATA01 0x01c6701c -#define GPIO_NAND_WP (1 << 4) -#ifdef SONATA_BOARD_GPIOWP - if (chip < 0) { - REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; - } else { - REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; - } -#endif -} - -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - nand->select_chip = nand_sonata_select_chip; - return 0; -} - -#endif /* CONFIG_NAND_DAVINCI */ diff --git a/configs/davinci_dm355evm_defconfig b/configs/davinci_dm355evm_defconfig deleted file mode 100644 index 4513ce4c025..00000000000 --- a/configs/davinci_dm355evm_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_DM355EVM=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="DM355 EVM # " diff --git a/configs/davinci_dm355leopard_defconfig b/configs/davinci_dm355leopard_defconfig deleted file mode 100644 index 7945605e166..00000000000 --- a/configs/davinci_dm355leopard_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_DM355LEOPARD=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="DM355 LEOPARD # " diff --git a/configs/davinci_dm365evm_defconfig b/configs/davinci_dm365evm_defconfig deleted file mode 100644 index 3550e75180f..00000000000 --- a/configs/davinci_dm365evm_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_DM365EVM=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="DM36x EVM # " diff --git a/configs/davinci_dm6467Tevm_defconfig b/configs/davinci_dm6467Tevm_defconfig deleted file mode 100644 index 3749b81ac51..00000000000 --- a/configs/davinci_dm6467Tevm_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_DM6467EVM=y -CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/davinci_dm6467evm_defconfig b/configs/davinci_dm6467evm_defconfig deleted file mode 100644 index b2021afddc0..00000000000 --- a/configs/davinci_dm6467evm_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_DM6467EVM=y -CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="DM6467 EVM > " diff --git a/configs/davinci_dvevm_defconfig b/configs/davinci_dvevm_defconfig deleted file mode 100644 index 7c6f03eaf32..00000000000 --- a/configs/davinci_dvevm_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_DVEVM=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/davinci_schmoogie_defconfig b/configs/davinci_schmoogie_defconfig deleted file mode 100644 index 2fb4d9f22e8..00000000000 --- a/configs/davinci_schmoogie_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_SCHMOOGIE=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/davinci_sffsdr_defconfig b/configs/davinci_sffsdr_defconfig deleted file mode 100644 index 633b4a81850..00000000000 --- a/configs/davinci_sffsdr_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_SFFSDR=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/davinci_sonata_defconfig b/configs/davinci_sonata_defconfig deleted file mode 100644 index 697ce0622b0..00000000000 --- a/configs/davinci_sonata_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DAVINCI_SONATA=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot > " diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h deleted file mode 100644 index 72296a03ddb..00000000000 --- a/include/configs/davinci_dm355evm.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2009 David Brownell - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM355 EVM board */ -#define DAVINCI_DM355EVM - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SOC_DM355 - -/* Memory Info */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ - -/* Serial Driver info: UART0 for console */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Ethernet: external DM9000 */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x04014000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ - -/* NAND: socketed, two chipselects, normally 2 GBytes */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } -/* socket has two chipselects, nCE0 gated by address BIT(14) */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 - -/* SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#define CONFIG_DAVINCI_MMC_SD1 -#define CONFIG_MMC_MBLOCK - -/* USB: OTG connector */ -/* NYET -- #define CONFIG_USB_DAVINCI */ - -/* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MMC -#endif - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#endif - -#ifdef CONFIG_USB_DAVINCI -#define CONFIG_USB_MUSB_HCD -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#else -#undef CONFIG_USB_MUSB_HCD -#undef CONFIG_CMD_USB -#undef CONFIG_USB_STORAGE -#endif - -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* U-Boot general configuration */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x3C0000 -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_CMD_ENV -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ -#define CONFIG_ENV_IS_IN_MMC -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND \ - "dhcp;bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200n8 " \ - "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP - -#define CONFIG_NET_RETRY_COUNT 10 - -/* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ -#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ - - -/* NAND configuration ... socketed with two chipselects. It normally comes - * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other - * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC - * pretty much demands the 4-bit ECC support.) You can of course swap in - * other parts, including small page ones. - * - * This presents a single read-only partition for all bootloader stuff. - * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and - * some extra space to help cope with bad blocks in that data. Linux - * shouldn't care about its detailed layout, and will probably want to use - * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to - * override this default partitioning using MTDPARTS and cmdlinepart. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -/* Use same layout for 128K/256K blocks; allow some bad blocks */ -#define PART_BOOT "2m(bootloader)ro," -#else -/* Assume 16K erase blocks; allow a few bad ones. */ -#define PART_BOOT "512k(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h deleted file mode 100644 index e3ff9431dc9..00000000000 --- a/include/configs/davinci_dm355leopard.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define DAVINCI_DM355LEOPARD - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SOC_DM355 /* DM355 based board */ - -/* Memory Info */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ - -/* Serial Driver info: UART0 for console */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Ethernet: external DM9000 */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x04000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 16) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 - -/* NAND */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_HW_ECC - -#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#endif - -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* U-Boot general configuration */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x3C0000 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE -#endif - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "dhcp;bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200n8 " \ - "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP - -#define CONFIG_NET_RETRY_COUNT 10 - -/* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ -#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ - -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -#define PART_BOOT "2m(bootloader)ro," -#else -/* Assume 16K erase blocks; allow a few bad ones. */ -#define PART_BOOT "512k(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h deleted file mode 100644 index bbc801b4db9..00000000000 --- a/include/configs/davinci_dm365evm.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM365 EVM board */ -#define DAVINCI_DM365EVM - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SOC_DM365 - -/* Memory Info */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ - -/* Serial Driver info: UART0 for console */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* EEPROM definitions for EEPROM on DM365 EVM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* Network Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ - -/* NAND: socketed, two chipselects, normally 2 GBytes */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } -/* socket has two chipselects, nCE0 gated by address BIT(14) */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 - -/* SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#define CONFIG_DAVINCI_MMC_SD1 -#define CONFIG_MMC_MBLOCK - -#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000 -#define PINMUX4_USBDRVBUS_BITSET 0x2000 - -/* USB Configuration */ -#define CONFIG_USB_DAVINCI -#define CONFIG_USB_MUSB_HCD - -#ifdef CONFIG_USB_DAVINCI -#define CONFIG_CMD_USB /* include support for usb */ -#define CONFIG_CMD_STORAGE /* include support for usb */ -#define CONFIG_CMD_FAT /* include support for FAT/storage*/ -#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/ -#endif - -#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */ -#define CONFIG_CMD_USB /* include support for usb cmd */ -#define CONFIG_USB_STORAGE /* MSC class support */ -#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ -#define CONFIG_CMD_FAT /* inclue support for FAT/storage */ -#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */ - -#ifdef CONFIG_USB_KEYBOARD /* HID class support */ -#define CONFIG_SYS_USB_EVENT_POLL - -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ -#endif /* CONFIG_USB_MUSB_HCD */ - -#ifdef CONFIG_USB_MUSB_UDC -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "DM365VM" -#endif /* CONFIG_USB_MUSB_UDC */ - -/* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MMC -#endif - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#endif - -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* U-Boot general configuration */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP - -#ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x3C0000 -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_CMD_ENV -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ -#define CONFIG_ENV_IS_IN_MMC -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND \ - "dhcp;bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200n8 " \ - "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP - -/* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ -#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ - - -/* NAND configuration issocketed with two chipselects just like the DM355 EVM. - * It normally comes with a 2GByte SLC part with 2KB pages - * (and 128KB erase blocks); other - * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC - * pretty much demands the 4-bit ECC support.) You can of course swap in - * other parts, including small page ones. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -/* Use same layout for 128K/256K blocks; allow some bad blocks */ -#define PART_BOOT "2m(bootloader)ro," -#else -/* Assume 16K erase blocks; allow a few bad ones. */ -#define PART_BOOT "512k(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h deleted file mode 100644 index 6346422b498..00000000000 --- a/include/configs/davinci_dm6467evm.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM6467 EVM board */ -#define DAVINCI_DM6467EVM -#define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_NAND_SMALLPAGE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* SoC Configuration */ - -/* Clock rates detection */ -#ifndef __ASSEMBLY__ -extern unsigned int davinci_arm_clk_get(void); -#endif - -/* Arm Clock frequency */ -#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get() -/* Timer Input clock freq */ -#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2) -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SOC_DM646X - -/* EEPROM definitions for EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ -#define CONFIG_REVISION_TAG - -/* Serial Driver info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* I2C Configuration */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 - -/* Network & Ethernet Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* Flash & Environment */ -#define CONFIG_SYS_NO_FLASH -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_MASK_CLE 0x80000 -#define CONFIG_SYS_NAND_MASK_ALE 0x40000 -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, } -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_ENV_OFFSET 0 -#else -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */ -#endif - -/* U-Boot general configuration */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm" -#define CONFIG_BOOTARGS \ - "mem=120M console=ttyS0,115200n8 " \ - "root=/dev/hda1 rw noinitrd ip=dhcp" - -/* U-Boot commands */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_CMD_NAND -#endif - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h deleted file mode 100644 index 15d815084b4..00000000000 --- a/include/configs/davinci_dvevm.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Define this to make U-Boot skip low level initialization when loaded - * by initial bootloader. Not required by NAND U-Boot version but IS - * required for a NOR version used to burn the real NOR U-Boot into - * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive - * so it is NOT possible to build a U-Boot with both NAND and NOR routines. - * NOR U-Boot is loaded directly from Flash so it must perform all the - * low level initialization itself. NAND version is loaded by an initial - * bootloader (UBL in TI-ese) that performs such an initialization so it's - * skipped in NAND version. The third DaVinci boot mode loads a bootloader - * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) - * performing low level init prior to loading. All that means we can NOT use - * NAND version to put U-Boot into NOR because it doesn't have NOR support and - * we can NOT use NOR version because it performs low level initialization - * effectively destroying itself in DDR memory. That's why a separate NOR - * version with this define is needed. It is loaded via UART, then one uses - * it to somehow download a proper NOR version built WITHOUT this define to - * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze - * NOR support into the initial bootloader so it won't be needed but DaVinci - * static RAM might be too small for this (I have something like 2Kbytes left - * as of now, without NOR support) so this might've not happened... - * -#define CONFIG_NOR_UART_BOOT - */ - -/*=======*/ -/* Board */ -/*=======*/ -#define DV_EVM -#define CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_SYS_USE_NAND -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/*====================================================*/ -/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ -/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ -/*====================================================*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ - -#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/*===================*/ -/* I2C Configuration */ -/*===================*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ -/* Network & Ethernet Configuration */ -/*==================================*/ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#ifdef CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT \ - "nand0=davinci_nand.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)" -#else -#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#elif defined(CONFIG_SYS_USE_NOR) -#ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#else -#undef CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */ -#endif -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_DAVINCI -/*===================*/ -/* Linux Information */ -/*===================*/ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000" -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_CMD_NAND -#elif defined(CONFIG_SYS_USE_NOR) -#define CONFIG_CMD_JFFS2 -#else -#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" -#endif -/*==========================*/ -/* USB MSC support (if any) */ -/*==========================*/ -#ifdef CONFIG_USB_DAVINCI -#define CONFIG_CMD_USB -#ifdef CONFIG_USB_MUSB_HCD -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_STORAGE -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL -#define CONFIG_PREBOOT "usb start" -#endif -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h deleted file mode 100644 index bc5e1ca6972..00000000000 --- a/include/configs/davinci_schmoogie.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*=======*/ -/* Board */ -/*=======*/ -#define SCHMOOGIE -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_USE_NAND -#define MACH_TYPE_SCHMOOGIE 1255 -#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE - -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ -#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/*===================*/ -/* I2C Configuration */ -/*===================*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ -/* Network & Ethernet Configuration */ -/*==================================*/ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_OVERWRITE_ETHADDR_ONCE -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/*=====================*/ -/* Board related stuff */ -/*=====================*/ -#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ -#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ -#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */ -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -/*===================*/ -/* Linux Information */ -/*===================*/ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NAND -#undef CONFIG_CMD_EEPROM - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h deleted file mode 100644 index e7193887225..00000000000 --- a/include/configs/davinci_sffsdr.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Copyright (C) 2008 Lyrtech - * Copyright (C) 2008 Philip Balister, OpenSDR - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board */ -#define SFFSDR -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ -/* SoC Configuration */ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ -#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/* Serial Driver info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/* Network & Ethernet Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_OVERWRITE_ETHADDR_ONCE -/* Flash & Environment */ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/* I2C switch definitions for PCA9543 chip */ -#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 -#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ -#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ -/* U-Boot general configuration */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel - * load address. */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, - * may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -/* Linux Information */ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=56M " \ - "console=ttyS0,115200n8 " \ - "root=/dev/nfs rw noinitrd ip=dhcp " \ - "nfsroot=${serverip}:/nfsroot/sffsdr " \ - "eth0=${ethaddr}" -#define CONFIG_BOOTCOMMAND \ - "nand read 87A00000 100000 300000;" \ - "bootelf 87A00000" -/* U-Boot commands */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_NAND -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */ - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h deleted file mode 100644 index b85c988b5d8..00000000000 --- a/include/configs/davinci_sonata.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Define this to make U-Boot skip low level initialization when loaded - * by initial bootloader. Not required by NAND U-Boot version but IS - * required for a NOR version used to burn the real NOR U-Boot into - * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive - * so it is NOT possible to build a U-Boot with both NAND and NOR routines. - * NOR U-Boot is loaded directly from Flash so it must perform all the - * low level initialization itself. NAND version is loaded by an initial - * bootloader (UBL in TI-ese) that performs such an initialization so it's - * skipped in NAND version. The third DaVinci boot mode loads a bootloader - * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) - * performing low level init prior to loading. All that means we can NOT use - * NAND version to put U-Boot into NOR because it doesn't have NOR support and - * we can NOT use NOR version because it performs low level initialization - * effectively destroying itself in DDR memory. That's why a separate NOR - * version with this define is needed. It is loaded via UART, then one uses - * it to somehow download a proper NOR version built WITHOUT this define to - * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze - * NOR support into the initial bootloader so it won't be needed but DaVinci - * static RAM might be too small for this (I have something like 2Kbytes left - * as of now, without NOR support) so this might've not happened... - * -#define CONFIG_NOR_UART_BOOT - */ - -/*=======*/ -/* Board */ -/*=======*/ -#define SONATA_BOARD -#define CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_SYS_USE_NOR -#define MACH_TYPE_SONATA 1254 -#define CONFIG_MACH_TYPE MACH_TYPE_SONATA -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SOC_DM644X -/*====================================================*/ -/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ -/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ -/*====================================================*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ -#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ -#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/*===================*/ -/* I2C Configuration */ -/*===================*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ -/* Network & Ethernet Configuration */ -/*==================================*/ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */ -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_SYS_NAND_BASE 0x02000000 -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#elif defined(CONFIG_SYS_USE_NOR) -#ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#else -#undef CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2) -#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */ -#endif -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -/*===================*/ -/* Linux Information */ -/*===================*/ -#define LINUX_BOOT_PARAM_ADDR 0x80000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000" -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_CMD_NAND -#elif defined(CONFIG_SYS_USE_NOR) -#define CONFIG_CMD_JFFS2 -#else -#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" -#endif - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 5ff33d040421395298334a6e76167417135bde24 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:01 -0600 Subject: arm: Remove dig297 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/omap3/Kconfig | 4 - board/comelit/dig297/Kconfig | 12 -- board/comelit/dig297/MAINTAINERS | 6 - board/comelit/dig297/Makefile | 8 - board/comelit/dig297/dig297.c | 182 ------------------- board/comelit/dig297/dig297.h | 367 --------------------------------------- configs/dig297_defconfig | 10 -- include/configs/dig297.h | 268 ---------------------------- 8 files changed, 857 deletions(-) delete mode 100644 board/comelit/dig297/Kconfig delete mode 100644 board/comelit/dig297/MAINTAINERS delete mode 100644 board/comelit/dig297/Makefile delete mode 100644 board/comelit/dig297/dig297.c delete mode 100644 board/comelit/dig297/dig297.h delete mode 100644 configs/dig297_defconfig delete mode 100644 include/configs/dig297.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index cda38e1387a..83cb7fff42a 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -79,9 +79,6 @@ config TARGET_ECO5PK bool "ECO5PK" select SUPPORT_SPL -config TARGET_DIG297 - bool "DIG297" - config TARGET_TRICORDER bool "Tricorder" select SUPPORT_SPL @@ -143,7 +140,6 @@ source "board/logicpd/zoom1/Kconfig" source "board/ti/am3517crane/Kconfig" source "board/pandora/Kconfig" source "board/8dtech/eco5pk/Kconfig" -source "board/comelit/dig297/Kconfig" source "board/corscience/tricorder/Kconfig" source "board/htkw/mcx/Kconfig" source "board/logicpd/omap3som/Kconfig" diff --git a/board/comelit/dig297/Kconfig b/board/comelit/dig297/Kconfig deleted file mode 100644 index 6dccaff5b0c..00000000000 --- a/board/comelit/dig297/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DIG297 - -config SYS_BOARD - default "dig297" - -config SYS_VENDOR - default "comelit" - -config SYS_CONFIG_NAME - default "dig297" - -endif diff --git a/board/comelit/dig297/MAINTAINERS b/board/comelit/dig297/MAINTAINERS deleted file mode 100644 index 318374e2568..00000000000 --- a/board/comelit/dig297/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DIG297 BOARD -M: Luca Ceresoli -S: Maintained -F: board/comelit/dig297/ -F: include/configs/dig297.h -F: configs/dig297_defconfig diff --git a/board/comelit/dig297/Makefile b/board/comelit/dig297/Makefile deleted file mode 100644 index 1c85b63bf36..00000000000 --- a/board/comelit/dig297/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dig297.o diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c deleted file mode 100644 index 9d4c41b00b3..00000000000 --- a/board/comelit/dig297/dig297.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2011 Comelit Group SpA - * Luca Ceresoli - * - * Based on board/ti/beagle/beagle.c: - * (C) Copyright 2004-2008 - * Texas Instruments, - * - * Author : - * Sunil Kumar - * Shashi Ranjan - * - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dig297.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_NET -static void setup_net_chip(void); - -#define NET_LAN9221_RESET_GPIO 12 - -/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */ -#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT) -#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \ - CSRDOFFTIME(7) | \ - ADVONTIME(1)) -#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \ - ADVRDOFFTIME(2) | \ - ADVONTIME(1)) -#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \ - WEONTIME(1) | \ - OEOFFTIME(7)| \ - OEONTIME(1)) -#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \ - RDACCESSTIME(6) | \ - WRCYCLETIME(0x1D) | \ - RDCYCLETIME(0x1D)) -#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \ - WRACCESSTIME(0x1D) | \ - WRDATAONADMUXBUS(3)) - -static const u32 gpmc_lan_config[] = { - NET_LAN9220_GPMC_CONFIG1, - NET_LAN9220_GPMC_CONFIG2, - NET_LAN9220_GPMC_CONFIG3, - NET_LAN9220_GPMC_CONFIG4, - NET_LAN9220_GPMC_CONFIG5, - NET_LAN9220_GPMC_CONFIG6, - /* CONFIG7: computed by enable_gpmc_cs_config() */ -}; -#endif /* CONFIG_CMD_NET */ - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE; - struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; - - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - - /* - * GPIO list - * - 159 OUT (GPIO5+31): reset for remote camera interface connector. - * - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn). - * - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn). - */ - - /* Configure GPIOs to output */ - writel(~(GPIO19 | GPIO20), &gpio1_base->oe); - writel(~(GPIO31), &gpio5_base->oe); - - /* Set GPIO values */ - writel((GPIO19 | GPIO20), &gpio1_base->setdataout); - writel(0, &gpio5_base->setdataout); - -#if defined(CONFIG_CMD_NET) - setup_net_chip(); -#endif - - dieid_num_r(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DIG297(); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - -#ifdef CONFIG_CMD_NET -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - /* Configure GPMC registers */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - /* Make GPIO 12 as output pin and send a magic pulse through it */ - if (!gpio_request(NET_LAN9221_RESET_GPIO, "")) { - gpio_direction_output(NET_LAN9221_RESET_GPIO, 0); - gpio_set_value(NET_LAN9221_RESET_GPIO, 1); - udelay(1); - gpio_set_value(NET_LAN9221_RESET_GPIO, 0); - udelay(31000); /* Should be >= 30ms according to datasheet */ - gpio_set_value(NET_LAN9221_RESET_GPIO, 1); - } -} -#endif /* CONFIG_CMD_NET */ - -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - return rc; -} diff --git a/board/comelit/dig297/dig297.h b/board/comelit/dig297/dig297.h deleted file mode 100644 index 8edfc099f35..00000000000 --- a/board/comelit/dig297/dig297.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - * (C) Copyright 2011 Comelit Group SpA - * Luca Ceresoli - * - * Based on board/ti/beagle/beagle.h: - * (C) Copyright 2008 - * Dirk Behme - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _DIG297_H_ -#define _DIG297_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 DIG297 board", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DIG297() \ -/*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\ -/*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\ - /* GPMC_nCS1/2: not available on CUS package*/\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ - MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\ - /* GPMC_WAIT2: not available on CUS package*/\ - MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\ - /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - /* GPMC_WAIT1: not available on CUS package*/\ -/*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ -/*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ -/*Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ -/*Expansion card */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ -/*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ -/*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ - MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ -/*Modem Interface */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ -/*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ -/* USB EHCI (port 2) */\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ -/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\ - /* - * McSPI1_CLK. - * IEN needed fot the McSPI to "receive" the clock and be able to - * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/ - * omap_applications_processors/f/42/p/29444/102394.aspx#102394 - */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\ - MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\ -/* MCSPI2: to HIMAX TFT controller.*/\ - MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\ - /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\ - MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\ - MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\ - MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\ -/* GPIO */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\ - MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\ - MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\ - MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\ - MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\ -/*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */ - -#endif diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig deleted file mode 100644 index 4c2c9828e52..00000000000 --- a/configs/dig297_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_ARM=y -CONFIG_OMAP34XX=y -CONFIG_TARGET_DIG297=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="DIG297# " diff --git a/include/configs/dig297.h b/include/configs/dig297.h deleted file mode 100644 index 98205adde03..00000000000 --- a/include/configs/dig297.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * (C) Copyright 2011 Comelit Group SpA - * Luca Ceresoli - * - * Based on omap3_beagle.h: - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * Configuration settings for the Comelit DIG297 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#ifdef MACH_TYPE_OMAP3_CPS -#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this." -#else -#define MACH_TYPE_OMAP3_CPS 2751 -#endif -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -#define CONFIG_SYS_TEXT_BASE 0x80008000 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include /* get chip and board defs */ -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */ - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration: UART3 (ttyO2) - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION - -/* library portions to compile in */ -#define CONFIG_RBTREE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_LZO - -/* commands to include */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_UBI /* UBI Support */ -#define CONFIG_CMD_UBIFS /* UBIFS Support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\ - "128k(uboot-env),3m(kernel),252m(ubi)" - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER -#define CONFIG_TWL4030_LED - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - -#if defined(CONFIG_CMD_NET) -/* - * SMSC9220 Ethernet - */ - -#define CONFIG_SMC911X -#define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 - -#endif /* (CONFIG_CMD_NET) */ - -/* Environment information */ -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "partition=nand0,3\0"\ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=ubi0:rootfs ro\0" \ - "nandrootfstype=ubifs\0" \ - "nfspath=/srv/nfs\0" \ - "tftpfilename=uImage\0" \ - "gatewayip=0.0.0.0\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}::off\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "ubi.mtd=3 " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}::off\0" \ - "netargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${nfspath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}::off\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 100000 300000; " \ - "bootm ${loadaddr}\0" \ - "netboot=echo Booting from network ...; " \ - "run netargs; " \ - "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \ - "bootm ${loadaddr}\0" \ - "resetenv=nand erase e0000 20000\0"\ - -#define CONFIG_BOOTCOMMAND \ - "run nandboot" - -#define CONFIG_AUTO_COMPLETE -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE boot_flash_base - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_IS_IN_NAND -#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 5522f12b3c5224b19e84a501936830830e00c1ce Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:02 -0600 Subject: arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards These board have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/mach-at91/Kconfig | 5 - board/BuS/eb_cpux9k2/Kconfig | 12 -- board/BuS/eb_cpux9k2/MAINTAINERS | 7 - board/BuS/eb_cpux9k2/Makefile | 8 - board/BuS/eb_cpux9k2/cpux9k2.c | 373 ------------------------------------ configs/eb_cpux9k2_defconfig | 5 - configs/eb_cpux9k2_ram_defconfig | 5 - include/configs/eb_cpux9k2.h | 400 --------------------------------------- 8 files changed, 815 deletions(-) delete mode 100644 board/BuS/eb_cpux9k2/Kconfig delete mode 100644 board/BuS/eb_cpux9k2/MAINTAINERS delete mode 100644 board/BuS/eb_cpux9k2/Makefile delete mode 100644 board/BuS/eb_cpux9k2/cpux9k2.c delete mode 100644 configs/eb_cpux9k2_defconfig delete mode 100644 configs/eb_cpux9k2_ram_defconfig delete mode 100644 include/configs/eb_cpux9k2.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 01a8d459d86..de06416da51 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -8,10 +8,6 @@ config TARGET_AT91RM9200EK bool "Atmel AT91RM9200 evaluation kit" select CPU_ARM920T -config TARGET_EB_CPUX9K2 - bool "Support eb_cpux9k2" - select CPU_ARM920T - config TARGET_AT91SAM9260EK bool "Atmel at91sam9260 reference board" select CPU_ARM926EJS @@ -143,7 +139,6 @@ source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" -source "board/BuS/eb_cpux9k2/Kconfig" source "board/bluewater/snapper9260/Kconfig" source "board/BuS/vl_ma2sc/Kconfig" source "board/calao/usb_a9263/Kconfig" diff --git a/board/BuS/eb_cpux9k2/Kconfig b/board/BuS/eb_cpux9k2/Kconfig deleted file mode 100644 index e2a787a1a85..00000000000 --- a/board/BuS/eb_cpux9k2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EB_CPUX9K2 - -config SYS_BOARD - default "eb_cpux9k2" - -config SYS_VENDOR - default "BuS" - -config SYS_CONFIG_NAME - default "eb_cpux9k2" - -endif diff --git a/board/BuS/eb_cpux9k2/MAINTAINERS b/board/BuS/eb_cpux9k2/MAINTAINERS deleted file mode 100644 index 81c4349ac91..00000000000 --- a/board/BuS/eb_cpux9k2/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -EB_CPUX9K2 BOARD -M: Jens Scharsig -S: Maintained -F: board/BuS/eb_cpux9k2/ -F: include/configs/eb_cpux9k2.h -F: configs/eb_cpux9k2_defconfig -F: configs/eb_cpux9k2_ram_defconfig diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile deleted file mode 100644 index b2ec389ab91..00000000000 --- a/board/BuS/eb_cpux9k2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cpux9k2.o diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c deleted file mode 100644 index 3880a068972..00000000000 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * BuS Elektronik GmbH & Co. KG - * Jens Scharsig - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_STATUS_LED -#include -#endif - -#ifdef CONFIG_VIDEO -#include - -extern unsigned long display_width; -extern unsigned long display_height; -#endif - -#ifdef CONFIG_CMD_NAND -void cpux9k2_nand_hw_init(void); -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - /* Correct IRDA resistor problem / Set PA23_TXD in Output */ - writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer); - - gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2; - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); -#endif -#ifdef CONFIG_CMD_NAND - cpux9k2_nand_hw_init(); -#endif - return 0; -} - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - return 0; -} - -#ifdef CONFIG_MISC_INIT_R - -int misc_init_r(void) -{ - uchar mac[8]; - uchar tm; - uchar midx; - uchar macn6, macn7; - - if (getenv("ethaddr") == NULL) { - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uchar *) &mac, sizeof(mac)) != 0) { - puts("Error reading MAC from EEPROM\n"); - } else { - tm = 0; - macn6 = 0; - macn7 = 0xFF; - for (midx = 0; midx < 6; midx++) { - if ((mac[midx] != 0) && (mac[midx] != 0xFF)) - tm++; - macn6 += mac[midx]; - macn7 ^= mac[midx]; - } - if ((macn6 != mac[6]) || (macn7 != mac[7])) - tm = 0; - if (tm) - eth_setenv_enetaddr("ethaddr", mac); - else - puts("Error: invalid MAC at EEPROM\n"); - } - } - gd->jt->do_reset = do_reset; - -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - return 0; -} -#endif - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ - udelay(10000); - eth_init(); -} -#endif - -/* - * DRAM initialisations - */ - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -/* - * Ethernet initialisations - */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC); - return rc; -} -#endif - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if defined(CONFIG_CMD_NAND) - -#define MASK_ALE (1 << 22) /* our ALE is AD22 */ -#define MASK_CLE (1 << 21) /* our CLE is AD21 */ - -void cpux9k2_nand_hw_init(void) -{ - unsigned long csr; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC; - - /* Setup Smart Media, fitst enable the address range of CS3 */ - writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa); - - /* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */ - csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) | - AT91_SMC_CSR_NWS(3) | - AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 | - AT91_SMC_CSR_WSEN; - writel(csr, &mc->smc.csr[3]); - - writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr); - writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, - &pio->pioc.pdr); - - /* Configure PC2 as input (signal Nand READY ) */ - writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per); - writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */ - writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr); - - /* PIOC clock enabling */ - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); -} - -static void board_nand_hwcontrol(struct mtd_info *mtd, - int cmd, unsigned int ctrl) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); - - if (ctrl & NAND_CLE) - IO_ADDR_W |= MASK_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= MASK_ALE; - - if ((ctrl & NAND_NCE)) - writel(1, &pio->pioc.codr); - else - writel(1, &pio->pioc.sodr); - - this->IO_ADDR_W = (void *) IO_ADDR_W; - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int board_nand_dev_ready(struct mtd_info *mtd) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0); -} - -int board_nand_init(struct nand_chip *nand) -{ - cpux9k2_nand_hw_init(); - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = board_nand_hwcontrol; - nand->dev_ready = board_nand_dev_ready; - nand->chip_delay = 20; - return 0; -} - -#endif - -#if defined(CONFIG_VIDEO) -/* - * drv_video_init - * FUNCTION: initialize VCxK device - */ - -int drv_video_init(void) -{ -#ifdef CONFIG_SPLASH_SCREEN - unsigned long splash; -#endif - char *s; - unsigned long csr; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC; - - printf("Init Video as "); - s = getenv("displaywidth"); - if (s != NULL) - display_width = simple_strtoul(s, NULL, 10); - else - display_width = 256; - s = getenv("displayheight"); - if (s != NULL) - display_height = simple_strtoul(s, NULL, 10); - else - display_height = 256; - printf("%ld x %ld pixel matrix\n", display_width, display_height); - - /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */ - csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) | - AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) | - AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 | - AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN; - writel(csr, &mc->smc.csr[2]); - writel(1 << ATMEL_ID_PIOB, &pmc->pcer); - - vcxk_init(display_width, display_height); -#ifdef CONFIG_SPLASH_SCREEN - s = getenv("splashimage"); - if (s != NULL) { - splash = simple_strtoul(s, NULL, 16); - printf("use splashimage: %lx\n", splash); - video_display_bitmap(splash, 0, 0); - } -#endif - return 0; -} -#endif - -#ifdef CONFIG_SYS_I2C_SOFT - -void i2c_init_board(void) -{ - u32 pin; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - writel(1 << ATMEL_ID_PIOA, &pmc->pcer); - pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK; - writel(pin, &pio->pioa.idr); - writel(pin, &pio->pioa.pudr); - writel(pin, &pio->pioa.per); - writel(pin, &pio->pioa.oer); - writel(pin, &pio->pioa.sodr); -} - -#endif - -/*--------------------------------------------------------------------------*/ - -#ifdef CONFIG_STATUS_LED - -void __led_toggle(led_id_t mask) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - if (readl(&pio->piod.odsr) & mask) - writel(mask, &pio->piod.codr); - else - writel(mask, &pio->piod.codr); -} - -void __led_init(led_id_t mask, int state) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */ - /* Disable peripherals on LEDs */ - writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per); - /* Enable pins as outputs */ - writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer); - /* Turn all LEDs OFF */ - writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr); - - __led_set(mask, state); -} - -void __led_set(led_id_t mask, int state) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - if (state == STATUS_LED_ON) - writel(mask, &pio->piod.codr); - else - writel(mask, &pio->piod.sodr); -} - -#endif - -/*---------------------------------------------------------------------------*/ - -int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = 0; - ulong side; - ulong bright; - - switch (argc) { - case 3: - side = simple_strtoul(argv[1], NULL, 10); - bright = simple_strtoul(argv[2], NULL, 10); - if ((side >= 0) && (side <= 3) && - (bright >= 0) && (bright <= 1000)) { - vcxk_setbrightness(side, bright); - rcode = 0; - } else { - printf("parameters out of range\n"); - printf("Usage:\n%s\n", cmdtp->usage); - rcode = 1; - } - break; - default: - printf("Usage:\n%s\n", cmdtp->usage); - rcode = 1; - break; - } - return rcode; -} - -/*---------------------------------------------------------------------------*/ - -U_BOOT_CMD( - bright, 3, 0, do_brightness, - "bright - sets the display brightness\n", - " <0..1000>\n side: 0/3=both; 1=first; 2=second\n" -); - -/* EOF cpu9k2.c */ diff --git a/configs/eb_cpux9k2_defconfig b/configs/eb_cpux9k2_defconfig deleted file mode 100644 index 6a6f3cd2c2e..00000000000 --- a/configs/eb_cpux9k2_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_EB_CPUX9K2=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/eb_cpux9k2_ram_defconfig b/configs/eb_cpux9k2_ram_defconfig deleted file mode 100644 index 47c2178f169..00000000000 --- a/configs/eb_cpux9k2_ram_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_EB_CPUX9K2=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h deleted file mode 100644 index d27f7e0452d..00000000000 --- a/include/configs/eb_cpux9k2.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * BuS Elektronik GmbH & Co. KG - * Jens Scharsig - * - * Configuation settings for the EB+CPUx9K2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_EB_CPUx9K2_H_ -#define _CONFIG_EB_CPUx9K2_H_ - -/*--------------------------------------------------------------------------*/ - -#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */ -#define USE_920T_MMU - -#define CONFIG_VERSION_VARIABLE -#define CONFIG_IDENT_STRING " on EB+CPUx9K2" - -#include /* needed for port definitions */ - -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F - -#define MACH_TYPE_EB_CPUX9K2 1977 -#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_DCACHE_OFF - -/*--------------------------------------------------------------------------*/ -#ifndef CONFIG_RAMBOOT -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#else -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x21800000 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ -#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000 - -#define CONFIG_BOOT_RETRY_TIME 30 -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -/* - * ARM asynchronous clock - */ - -#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */ -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */ - -/* - * Size of malloc() pool - */ - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* - * sdram - */ - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \ - CONFIG_SYS_MALLOC_LEN) - -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -/* - * Command line configuration - */ -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_I2C_CMD_TREE -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_UBI -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_UBIFS - -#define CONFIG_SYS_LONGHELP - -/* - * MTD defines - */ - -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "physmap-flash.0:" \ - "512k(U-Boot)," \ - "128k(Env)," \ - "128k(Splash)," \ - "4M(Kernel)," \ - "384k(MiniFS)," \ - "-(FS)" \ - ";" \ - "atmel_nand:" \ - "1M(emergency)," \ - "-(data)" -/* - * Hardware drivers - */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_AT91C_PQFP_UHPBUG -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_EFI_PARTITION - -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" - -/* - * UART/CONSOLE - */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0/* ignored in arm */ - -/* - * network - */ - -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_RESET_PHY_R 1 - -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_DRIVER_AT91EMAC_QUIET 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#define CONFIG_MII 1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * I2C-Bus - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 - -/* Software I2C driver configuration */ - -#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */ -#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */ - -#define CONFIG_SYS_I2C_INIT_BOARD - -#define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr); -#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder); -#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0) -#define I2C_SDA(bit) \ - if (bit) \ - writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \ - else \ - writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr); -#define I2C_SCL(bit) \ - if (bit) \ - writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \ - else \ - writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr); - -#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED) - -/* I2C-RTC */ - -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/* EEPROM */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -/* FLASH organization */ - -/* NOR-FLASH */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_ERASE_TOUT 6000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 - -/* NAND */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 - -/* Status LED's */ - -#define CONFIG_STATUS_LED 1 -#define CONFIG_BOARD_SPECIFIC_LED 1 - -#define STATUS_LED_BOOT 1 -#define STATUS_LED_ACTIVE 0 - -#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */ -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */ -#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */ -#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */ -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4) - -#define CONFIG_VIDEO 1 - -/* Options */ - -#ifdef CONFIG_VIDEO - -#define CONFIG_VIDEO_VCXK 1 - -#define CONFIG_SPLASH_SCREEN 1 - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4 -#define CONFIG_SYS_VCXK_BASE 0x30000000 - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3) -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr - -#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5) -#define CONFIG_SYS_VCXK_ENABLE_PORT piob -#define CONFIG_SYS_VCXK_ENABLE_DDR oer - -#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2) -#define CONFIG_SYS_VCXK_REQUEST_PORT piob -#define CONFIG_SYS_VCXK_REQUEST_DDR oer - -#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4) -#define CONFIG_SYS_VCXK_INVERT_PORT piob -#define CONFIG_SYS_VCXK_INVERT_DDR oer - -#define CONFIG_SYS_VCXK_RESET_PIN (1<<6) -#define CONFIG_SYS_VCXK_RESET_PORT piob -#define CONFIG_SYS_VCXK_RESET_DDR oer - -#endif /* CONFIG_VIDEO */ - -/* Environment */ - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000) -#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOMMAND "run nfsboot" - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp $(copy_addr) uImage_cpux9k2;" \ - "run bootargsdefaults;" \ - "set bootargs $(bootargs) boot=nfs " \ - ";echo $(bootargs)" \ - ";bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "displaywidth=256\0" \ - "displayheight=512\0" \ - "displaybsteps=1023\0" \ - "ubootaddr=10000000\0" \ - "splashimage=100A0000\0" \ - "kerneladdr=100C0000\0" \ - "kernelsize=00400000\0" \ - "rootfsaddr=10520000\0" \ - "copy_addr=21200000\0" \ - "rootfssize=00AE0000\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "bootargsdefaults=set bootargs " \ - "console=ttyS0,115200 " \ - "video=vcxk_fb:xres:${displaywidth}," \ - "yres:${displayheight}," \ - "bres:${displaybsteps} " \ - "mem=62M " \ - "panic=10 " \ - "uboot=\\\"${ver}\\\" " \ - "\0" \ - "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ - "dhcp $(copy_addr) uImage_cpux9k2;" \ - "erase $(kerneladdr) +$(kernelsize);" \ - "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ - "protect on $(kerneladdr) +$(kernelsize)" \ - "\0" \ - "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ - "dhcp $(copy_addr) rfs;" \ - "erase $(rootfsaddr) +$(rootfssize);" \ - "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ - "\0" \ - "update_uboot=protect off 10000000 1007FFFF;" \ - "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \ - "erase 10000000 1007FFFF;" \ - "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ - "protect on 10000000 1007FFFF;reset\0" \ - "update_splash=protect off $(splashimage) +20000;" \ - "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \ - "erase $(splashimage) +20000;" \ - "cp.b $(fileaddr) $(splashimage) $(filesize);" \ - "protect on $(splashimage) +20000;reset\0" \ - "emergency=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(kerneladdr)\0" \ - "netemergency=run bootargsdefaults;" \ - "dhcp $(copy_addr) uImage_cpux9k2;" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(copy_addr)\0" \ - "norboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=local " \ - ";bootm $(kerneladdr)\0" \ - "nandboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=nand " \ - ";bootm $(kerneladdr)\0" \ - " " - -/*--------------------------------------------------------------------------*/ - -#endif - -/* EOF */ -- cgit v1.3.1 From a6f7f78744320639a6ddb797819f54e930a6ed23 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:04 -0600 Subject: arm: Remove enbw_cmc board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-davinci/Kconfig | 4 - board/enbw/enbw_cmc/Kconfig | 12 - board/enbw/enbw_cmc/MAINTAINERS | 6 - board/enbw/enbw_cmc/Makefile | 10 - board/enbw/enbw_cmc/enbw_cmc.c | 893 ---------------------------------------- configs/enbw_cmc_defconfig | 5 - doc/README.switch_config | 25 -- include/configs/enbw_cmc.h | 440 -------------------- 8 files changed, 1395 deletions(-) delete mode 100644 board/enbw/enbw_cmc/Kconfig delete mode 100644 board/enbw/enbw_cmc/MAINTAINERS delete mode 100644 board/enbw/enbw_cmc/Makefile delete mode 100644 board/enbw/enbw_cmc/enbw_cmc.c delete mode 100644 configs/enbw_cmc_defconfig delete mode 100644 doc/README.switch_config delete mode 100644 include/configs/enbw_cmc.h (limited to 'include') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 4997b2ce54d..8079fabd6f3 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -4,9 +4,6 @@ choice prompt "DaVinci board select" optional -config TARGET_ENBW_CMC - bool "EnBW CMC board" - config TARGET_IPAM390 bool "IPAM390 board" select SUPPORT_SPL @@ -33,7 +30,6 @@ endchoice config SYS_SOC default "davinci" -source "board/enbw/enbw_cmc/Kconfig" source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" source "board/davinci/ea20/Kconfig" diff --git a/board/enbw/enbw_cmc/Kconfig b/board/enbw/enbw_cmc/Kconfig deleted file mode 100644 index 796736d8653..00000000000 --- a/board/enbw/enbw_cmc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ENBW_CMC - -config SYS_BOARD - default "enbw_cmc" - -config SYS_VENDOR - default "enbw" - -config SYS_CONFIG_NAME - default "enbw_cmc" - -endif diff --git a/board/enbw/enbw_cmc/MAINTAINERS b/board/enbw/enbw_cmc/MAINTAINERS deleted file mode 100644 index f7c99207db5..00000000000 --- a/board/enbw/enbw_cmc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ENBW_CMC BOARD -M: Heiko Schocher -S: Maintained -F: board/enbw/enbw_cmc/ -F: include/configs/enbw_cmc.h -F: configs/enbw_cmc_defconfig diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile deleted file mode 100644 index 054d6e7c839..00000000000 --- a/board/enbw/enbw_cmc/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := enbw_cmc.o diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c deleted file mode 100644 index 53b83621473..00000000000 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ /dev/null @@ -1,893 +0,0 @@ -/* - * (C) Copyright 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on da830evm.c. Original Copyrights follow: - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, - { DAVINCI_LPSC_SPI1 }, - { DAVINCI_LPSC_ARM_RAM_ROM }, - { DAVINCI_LPSC_UART0 }, - { DAVINCI_LPSC_EMAC }, - { DAVINCI_LPSC_UART0 }, - { DAVINCI_LPSC_GPIO }, - { DAVINCI_LPSC_DDR_EMIF }, - { DAVINCI_LPSC_UART1 }, - { DAVINCI_LPSC_UART2 }, - { DAVINCI_LPSC_MMC_SD1 }, - { DAVINCI_LPSC_USB20 }, - { DAVINCI_LPSC_USB11 }, -}; - -const int lpsc_size = ARRAY_SIZE(lpsc); - -static const struct pinmux_config enbw_pins[] = { - { pinmux(0), 8, 0 }, - { pinmux(0), 8, 1 }, - { pinmux(0), 8, 2 }, - { pinmux(0), 8, 3 }, - { pinmux(0), 8, 4 }, - { pinmux(0), 8, 5 }, - { pinmux(1), 4, 0 }, - { pinmux(1), 8, 1 }, - { pinmux(1), 8, 2 }, - { pinmux(1), 8, 3 }, - { pinmux(1), 8, 4 }, - { pinmux(1), 8, 5 }, - { pinmux(1), 8, 6 }, - { pinmux(1), 4, 7 }, - { pinmux(2), 8, 0 }, - { pinmux(5), 1, 0 }, - { pinmux(5), 1, 3 }, - { pinmux(5), 1, 7 }, - { pinmux(5), 1, 5 }, - { pinmux(5), 1, 4 }, - { pinmux(5), 1, 3 }, - { pinmux(5), 1, 2 }, - { pinmux(5), 1, 1 }, - { pinmux(5), 1, 0 }, - { pinmux(6), 8, 0 }, - { pinmux(6), 8, 1 }, - { pinmux(6), 8, 2 }, - { pinmux(6), 8, 3 }, - { pinmux(6), 8, 4 }, - { pinmux(6), 8, 5 }, - { pinmux(6), 1, 7 }, - { pinmux(7), 8, 2 }, - { pinmux(7), 1, 3 }, - { pinmux(7), 8, 6 }, - { pinmux(7), 1, 7 }, - { pinmux(13), 8, 2 }, - { pinmux(13), 8, 3 }, - { pinmux(13), 8, 4 }, - { pinmux(13), 8, 5 }, - { pinmux(13), 8, 6 }, - { pinmux(13), 8, 7 }, - { pinmux(14), 8, 0 }, - { pinmux(14), 8, 1 }, - { pinmux(16), 8, 1 }, - { pinmux(16), 8, 2 }, - { pinmux(16), 8, 3 }, - { pinmux(16), 8, 4 }, - { pinmux(16), 8, 5 }, - { pinmux(16), 8, 6 }, - { pinmux(16), 8, 7 }, - { pinmux(17), 1, 0 }, - { pinmux(17), 1, 1 }, - { pinmux(17), 1, 2 }, - { pinmux(17), 8, 3 }, - { pinmux(17), 8, 4 }, - { pinmux(17), 8, 5 }, - { pinmux(17), 8, 6 }, - { pinmux(17), 8, 7 }, - { pinmux(18), 8, 0 }, - { pinmux(18), 8, 1 }, - { pinmux(18), 2, 2 }, - { pinmux(18), 2, 3 }, - { pinmux(18), 2, 4 }, - { pinmux(18), 8, 6 }, - { pinmux(18), 8, 7 }, - { pinmux(19), 8, 0 }, - { pinmux(19), 2, 1 }, - { pinmux(19), 2, 2 }, - { pinmux(19), 2, 3 }, - { pinmux(19), 2, 4 }, - { pinmux(19), 8, 5 }, - { pinmux(19), 8, 6 }, -}; - -const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(emac_pins_mii), - PINMUX_ITEM(emac_pins_mdio), - PINMUX_ITEM(i2c0_pins), - PINMUX_ITEM(emifa_pins_cs2), - PINMUX_ITEM(emifa_pins_cs3), - PINMUX_ITEM(emifa_pins_cs4), - PINMUX_ITEM(emifa_pins_nand), - PINMUX_ITEM(emifa_pins_nor), - PINMUX_ITEM(spi1_pins_base), - PINMUX_ITEM(spi1_pins_scs0), - PINMUX_ITEM(uart1_pins_txrx), - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(uart2_pins_rtscts), - PINMUX_ITEM(enbw_pins), -}; - -const int pinmuxes_size = ARRAY_SIZE(pinmuxes); - -struct gpio_config { - char name[GPIO_NAME_SIZE]; - unsigned char bank; - unsigned char gpio; - unsigned char out; - unsigned char value; -}; - -static const struct gpio_config enbw_gpio_config_hut[] = { - { "RS485 enable", 8, 11, 1, 0 }, - { "RS485 iso", 8, 10, 1, 1 }, - { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, - { "W2HUT RS485 iso", 8, 8, 1, 1 }, -}; - -static const struct gpio_config enbw_gpio_config_w[] = { - { "RS485 enable", 8, 11, 1, 0 }, - { "RS485 iso", 8, 10, 1, 0 }, - { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, - { "W2HUT RS485 iso", 8, 8, 1, 0 }, -}; - -static const struct gpio_config enbw_gpio_config[] = { - { "LAN reset", 7, 15, 1, 1 }, - { "ena 11V PLC", 7, 14, 1, 0 }, - { "ena 1.5V PLC", 7, 13, 1, 0 }, - { "disable VBUS", 7, 12, 1, 1 }, - { "PLC reset", 6, 13, 1, 0 }, - { "LCM RS", 6, 12, 1, 0 }, - { "LCM R/W", 6, 11, 1, 0 }, - { "PLC pairing", 6, 10, 1, 1 }, - { "PLC MDIO CLK", 6, 9, 1, 0 }, - { "HK218", 6, 8, 1, 0 }, - { "HK218 Rx", 6, 1, 1, 1 }, - { "TPM reset", 6, 0, 1, 0 }, - { "Board-Type", 3, 9, 0, 0 }, - { "HW-ID0", 2, 7, 0, 0 }, - { "HW-ID1", 2, 6, 0, 0 }, - { "HW-ID2", 2, 3, 0, 0 }, - { "PV-IF RxD ena", 0, 15, 1, 1 }, - { "LED1", 1, 15, 1, 1 }, - { "LED2", 0, 1, 1, 1 }, - { "LED3", 0, 2, 1, 1 }, - { "LED4", 0, 3, 1, 1 }, - { "LED5", 0, 4, 1, 1 }, - { "LED6", 0, 5, 1, 0 }, - { "LED7", 0, 6, 1, 0 }, - { "LED8", 0, 14, 1, 0 }, - { "USER1", 0, 12, 0, 0 }, - { "USER2", 0, 13, 0, 0 }, -}; - -#define PHY_POWER 0x0800 - -static void enbw_cmc_switch(int port, int on) -{ - const char *devname; - unsigned char phyaddr = 3; - unsigned char reg = 0; - unsigned short data; - - if (port == 1) - phyaddr = 2; - - devname = miiphy_get_current_dev(); - if (!devname) { - printf("Error: no mii device\n"); - return; - } - if (miiphy_read(devname, phyaddr, reg, &data) != 0) { - printf("Error reading from the PHY addr=%02x reg=%02x\n", - phyaddr, reg); - return; - } - - if (on) - data &= ~PHY_POWER; - else - data |= PHY_POWER; - - if (miiphy_write(devname, phyaddr, reg, data) != 0) { - printf("Error writing to the PHY addr=%02x reg=%02x\n", - phyaddr, reg); - return; - } -} - -static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz) -{ - int i, ret; - - for (i = 0; i < sz; i++) { - int gpio = conf[i].bank * 16 + - conf[i].gpio; - - ret = gpio_request(gpio, conf[i].name); - if (ret) { - printf("%s: Could not get %s gpio\n", __func__, - conf[i].name); - return ret; - } - - if (conf[i].out) - gpio_direction_output(gpio, - conf[i].value); - else - gpio_direction_input(gpio); - } - - return 0; -} - -int board_init(void) -{ - int board_type, hw_id; - -#ifndef CONFIG_USE_IRQ - irq_init(); -#endif - /* address of boot parameters, not used as booting with DTT */ - gd->bd->bi_boot_params = 0; - - enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config)); - - /* detect HW version */ - board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE); - hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) + - (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) + - (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2); - printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"), - hw_id); - if (board_type) - enbw_cmc_init_gpio(enbw_gpio_config_w, - ARRAY_SIZE(enbw_gpio_config_w)); - else - enbw_cmc_init_gpio(enbw_gpio_config_hut, - ARRAY_SIZE(enbw_gpio_config_hut)); - - /* setup the SUSPSRC for ARM to control emulation suspend */ - clrbits_le32(&davinci_syscfg_regs->suspsrc, - (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART2)); - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC - -#define KSZ_CMD_READ 0x03 -#define KSZ_CMD_WRITE 0x02 -#define KSZ_ID 0x95 - -static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val) -{ - unsigned long flags = SPI_XFER_BEGIN; - int ret; - int cmd_len; - u8 cmd[2]; - - cmd[0] = KSZ_CMD_READ; - cmd[1] = reg; - cmd_len = 2; - - ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); - if (ret) { - debug("Failed to send command (%zu bytes): %d\n", - cmd_len, ret); - return -EINVAL; - } - flags |= SPI_XFER_END; - *val = 0; - cmd_len = 1; - ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags); - if (ret) { - debug("Failed to read (%zu bytes): %d\n", - cmd_len, ret); - return -EINVAL; - } - - return 0; -} - -static int enbw_cmc_switch_read_ident(struct spi_slave *spi) -{ - int ret; - u8 val; - - ret = enbw_cmc_switch_read(spi, 0, &val); - if (ret) { - debug("Failed to read\n"); - return -EINVAL; - } - - if (val != KSZ_ID) - return -EINVAL; - - return 0; -} - -static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg, - unsigned long val) -{ - unsigned long flags = SPI_XFER_BEGIN; - int ret; - int cmd_len; - u8 cmd[3]; - - cmd[0] = KSZ_CMD_WRITE; - cmd[1] = reg; - cmd[2] = val; - cmd_len = 3; - flags |= SPI_XFER_END; - - ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); - if (ret) { - debug("Failed to send command (%zu bytes): %d\n", - cmd_len, ret); - return -EINVAL; - } - - udelay(1000); - ret = enbw_cmc_switch_read(spi, reg, &cmd[0]); - if (ret) { - debug("Failed to read\n"); - return -EINVAL; - } - if (val != cmd[0]) - debug("warning: reg: %lx va: %x soll: %lx\n", - reg, cmd[0], val); - - return 0; -} - -static int enbw_cmc_eof(unsigned char *ptr) -{ - if (*ptr == 0xff) - return 1; - - return 0; -} - -static char *enbw_cmc_getnewline(char *ptr) -{ - while (*ptr != 0x0a) { - ptr++; - if (enbw_cmc_eof((unsigned char *)ptr)) - return NULL; - } - - ptr++; - return ptr; -} - -static char *enbw_cmc_getvalue(char *ptr, int *value) -{ - int end = 0; - - *value = -EINVAL; - - if (!isxdigit(*ptr)) - end = 1; - - while (end) { - if ((*ptr == '#') || (*ptr == ';')) { - ptr = enbw_cmc_getnewline(ptr); - return ptr; - } - if (ptr != NULL) { - if (isxdigit(*ptr)) { - end = 0; - } else if (*ptr == 0x0a) { - ptr++; - return ptr; - } else { - ptr++; - if (enbw_cmc_eof((unsigned char *)ptr)) - return NULL; - } - } else { - return NULL; - } - } - *value = (int)simple_strtoul((const char *)ptr, &ptr, 16); - ptr++; - return ptr; -} - -static struct spi_slave *enbw_cmc_init_spi(void) -{ - struct spi_slave *spi; - int ret; - - spi = spi_setup_slave(0, 0, 1000000, 0); - if (!spi) { - printf("Failed to set up slave\n"); - return NULL; - } - - ret = spi_claim_bus(spi); - if (ret) { - debug("Failed to claim SPI bus: %d\n", ret); - goto err_claim_bus; - } - - ret = enbw_cmc_switch_read_ident(spi); - if (ret) - goto err_read; - - return spi; -err_read: - spi_release_bus(spi); -err_claim_bus: - spi_free_slave(spi); - return NULL; -} - -static int enbw_cmc_config_switch(unsigned long addr) -{ - struct spi_slave *spi; - char *ptr = (char *)addr; - int value, reg; - int ret = 0; - - debug("configure switch with file on addr: 0x%lx\n", addr); - - spi = enbw_cmc_init_spi(); - if (!spi) - return -EINVAL; - - while (ptr != NULL) { - ptr = enbw_cmc_getvalue(ptr, ®); - if (ptr != NULL) { - ptr = enbw_cmc_getvalue(ptr, &value); - if ((ptr != NULL) && (value >= 0)) - if (enbw_cmc_switch_write(spi, reg, value)) { - /* error writing to switch */ - ptr = NULL; - ret = -EINVAL; - } - } - } - - spi_release_bus(spi); - spi_free_slave(spi); - return ret; -} - -static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned long addr; - - if (argc < 2) - return cmd_usage(cmdtp); - - addr = simple_strtoul(argv[1], NULL, 16); - enbw_cmc_config_switch(addr); - - return 0; -} - -U_BOOT_CMD(switch, 3, 1, do_switch, - "switch addr", - "[addr]" -); - -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - struct spi_slave *spi; - const char *s; - size_t len = 0; - int config = 1; - - davinci_emac_mii_mode_sel(0); - - /* send a config file to the switch */ - s = hwconfig_subarg("switch", "config", &len); - if (len) { - unsigned long addr = simple_strtoul(s, NULL, 16); - - config = enbw_cmc_config_switch(addr); - } - - if (config) { - /* - * no valid config file -> do we have some args in - * hwconfig ? - */ - if ((hwconfig_subarg("switch", "lan", &len)) || - (hwconfig_subarg("switch", "lmn", &len))) { - /* If so start switch */ - spi = enbw_cmc_init_spi(); - if (spi) { - if (enbw_cmc_switch_write(spi, 1, 0)) - config = 0; - udelay(10000); - if (enbw_cmc_switch_write(spi, 1, 1)) - config = 0; - spi_release_bus(spi); - spi_free_slave(spi); - } - } else { - config = 0; - } - } - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - if (config) { - if (hwconfig_subarg_cmp("switch", "lan", "on")) - /* Switch port lan on */ - enbw_cmc_switch(1, 1); - else - enbw_cmc_switch(1, 0); - - if (hwconfig_subarg_cmp("switch", "lmn", "on")) - /* Switch port pwl on */ - enbw_cmc_switch(2, 1); - else - enbw_cmc_switch(2, 0); - } - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#ifdef CONFIG_PREBOOT -static uchar kbd_magic_prefix[] = "key_magic_"; -static uchar kbd_command_prefix[] = "key_cmd_"; - -struct kbd_data_t { - char s1; -}; - -struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data) -{ - /* read SW1 + SW2 */ - kbd_data->s1 = gpio_get_value(12) + - (gpio_get_value(13) << 1); - return kbd_data; -} - -static int compare_magic(const struct kbd_data_t *kbd_data, char *str) -{ - char s1 = str[0]; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (s1 != kbd_data->s1) - return -1; - - return 0; -} - -static char *key_match(const struct kbd_data_t *kbd_data) -{ - char magic[sizeof(kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - kbd_magic_keys = getenv("magic_keys"); - if (kbd_magic_keys == NULL) - kbd_magic_keys = ""; - - /* - * loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); - - if (compare_magic(kbd_data, getenv(magic)) == 0) { - char cmd_name[sizeof(kbd_command_prefix) + 1]; - char *cmd; - - sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv(cmd_name); - - return cmd; - } - } - - return NULL; -} -#endif /* CONFIG_PREBOOT */ - -int misc_init_r(void) -{ - char *s, buf[32]; -#ifdef CONFIG_PREBOOT - struct kbd_data_t kbd_data; - /* Decode keys */ - char *str = strdup(key_match(get_keys(&kbd_data))); - /* Set or delete definition */ - setenv("preboot", str); - free(str); -#endif /* CONFIG_PREBOOT */ - - /* count all restarts, and save this in an environment var */ - s = getenv("restartcount"); - - if (s) - sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1); - else - strcpy(buf, "1"); - - setenv("restartcount", buf); - saveenv(); - -#ifdef CONFIG_HW_WATCHDOG - davinci_hw_watchdog_enable(); -#endif - - return 0; -} - -struct cmc_led { - char name[20]; - unsigned char bank; - unsigned char gpio; -}; - -struct cmc_led led_table[] = { - {"led1", 1, 15}, - {"led2", 0, 1}, - {"led3", 0, 2}, - {"led4", 0, 3}, - {"led5", 0, 4}, - {"led6", 0, 5}, - {"led7", 0, 6}, - {"led8", 0, 14}, -}; - -static int cmc_get_led_state(struct cmc_led *led) -{ - int value; - int gpio = led->bank * 16 + led->gpio; - - value = gpio_get_value(gpio); - - return value; -} - -static int cmc_set_led_state(struct cmc_led *led, int state) -{ - int gpio = led->bank * 16 + led->gpio; - - gpio_set_value(gpio, state); - return 0; -} - -static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - struct cmc_led *led; - int found = 0; - int i = 0; - int only_print = 0; - int len = ARRAY_SIZE(led_table); - - if (argc < 2) - return cmd_usage(cmdtp); - - if (argc < 3) - only_print = 1; - - led = led_table; - while ((!found) && (i < len)) { - if (strcmp(argv[1], led->name) == 0) { - found = 1; - } else { - led++; - i++; - } - } - if (!found) - return cmd_usage(cmdtp); - - if (only_print) { - if (cmc_get_led_state(led)) - printf("on\n"); - else - printf("off\n"); - - return 0; - } - if (strcmp(argv[2], "on") == 0) - cmc_set_led_state(led, 1); - else - cmc_set_led_state(led, 0); - - return 0; -} - -U_BOOT_CMD(led, 3, 1, do_led, - "switch on/off board led", - "[name] [on/off]" -); - -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - davinci_hw_watchdog_reset(); -} -#endif - -#if defined(CONFIG_POST) -void arch_memory_failure_handle(void) -{ - struct davinci_gpio *gpio = davinci_gpio_bank01; - int state = 1; - - /* - * if memor< failure blink with the LED 1,2 and 3 - * as we running from flash, we cannot use the gpio - * api here, so access the gpio pin direct through - * the gpio register. - */ - while (1) { - if (state) { - clrbits_le32(&gpio->out_data, 0x80000006); - state = 0; - } else { - setbits_le32(&gpio->out_data, 0x80000006); - state = 1; - } - udelay(500); - } -} -#endif - -ulong post_word_load(void) -{ - struct davinci_rtc *reg = - (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; - - return in_be32(®->scratch2); -} - -void post_word_store(ulong value) -{ - struct davinci_rtc *reg = - (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; - - /* - * write RTC kick register to enable write - * for RTC Scratch registers. Cratch0 and 1 are - * used for bootcount values. - */ - writel(RTC_KICK0R_WE, ®->kick0r); - writel(RTC_KICK1R_WE, ®->kick1r); - out_be32(®->scratch2, value); -} - -void board_gpio_init(void) -{ - struct davinci_gpio *gpio = davinci_gpio_bank01; - - /* - * set LED (gpio Interface not usable here) - * set LED pins to output and state 0 - */ - clrbits_le32(&gpio->dir, 0x8000407e); - clrbits_le32(&gpio->out_data, 0x8000407e); - /* set LED 1 - 5 to state on */ - setbits_le32(&gpio->out_data, 0x8000001e); - - /* - * set some gpio pins to low, this is needed early, - * so we have no gpio Interface here - * gpios: - * 8[8] Mode PV select low - * 8[9] Debug Rx Enable low - * 8[10] Mode Select PV low - * 8[11] Counter Interface RS485 Rx-Enable low - */ - gpio = davinci_gpio_bank8; - clrbits_le32(&gpio->dir, 0x00000f00); - clrbits_le32(&gpio->out_data, 0x0f00); -} - -int board_late_init(void) -{ - cmc_set_led_state(&led_table[4], 0); - - return 0; -} - -void show_boot_progress(int val) -{ - switch (val) { - case 1: - cmc_set_led_state(&led_table[4], 1); - break; - case 4: - cmc_set_led_state(&led_table[4], 0); - break; - case 15: - cmc_set_led_state(&led_table[4], 1); - break; - } -} - -#ifdef CONFIG_DAVINCI_MMC -static struct davinci_mmc mmc_sd1 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, - .input_clk = 228000000, - .host_caps = MMC_MODE_4BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_2, -}; - -int board_mmc_init(bd_t *bis) -{ - mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID); - /* Add slot-0 to mmc subsystem */ - return davinci_mmc_init(bis, &mmc_sd1); -} -#endif diff --git a/configs/enbw_cmc_defconfig b/configs/enbw_cmc_defconfig deleted file mode 100644 index 90249f37729..00000000000 --- a/configs/enbw_cmc_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_ENBW_CMC=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/doc/README.switch_config b/doc/README.switch_config deleted file mode 100644 index f8903738e1f..00000000000 --- a/doc/README.switch_config +++ /dev/null @@ -1,25 +0,0 @@ -On the enbw_cmc board is a KSZ8864RMN switch which needs -configured through spi before working. This is done on -startup from u-boot through a config file stored at an -address specified in the "hwconfig" environment variable, -subcommand "config". - -For example on the enbw_cmc board: - -hwconfig=switch:lan=on,pwl=off,config=0x60160000 - -The file has the following structure: - -- a comment starts with a '#' or a ';' and ends with a newline -- The switch needs for its config a reg/value pair, so we - have two columns in the file: - reg : contains the register address - value: contains a 8 bit register value - This 2 columns are seperated through space or tab. - -example (minimal configuration on the enbw_cmc board): - -;reg value comment -;----------------------------------------- -0x01 0x00 -0x01 0x01 ; Start Switch with this configuration diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h deleted file mode 100644 index 141489d179d..00000000000 --- a/include/configs/enbw_cmc.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7 -#define CONFIG_USE_NAND - -/* - * SoC Configuration - */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_DA850_LOWLEVEL -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_DA850_PLL_INIT -#define CONFIG_SYS_DA850_DDR_INIT -#define CONFIG_DA8XX_GPIO -#define CONFIG_HOSTNAME enbw_cmc - -#define MACH_TYPE_ENBW_CMC 3585 -#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* - * I2C Configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 -#define CONFIG_CMD_I2C - -#define CONFIG_CMD_DTT -#define CONFIG_DTT_LM75 -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -/* - * SPI Configuration - */ -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) -#define CONFIG_CMD_SPI - -/* - * Flash & Environment - */ -#ifdef CONFIG_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1" -#define MTDPARTS_DEFAULT \ - "mtdparts=" \ - "physmap-flash.0:" \ - "512k(U-Boot)," \ - "64k(env1)," \ - "64k(env2)," \ - "-(rest);" \ - "davinci_nand.1:" \ - "128k(dtb)," \ - "3m(kernel)," \ - "4m(rootfs)," \ - "-(userfs)" - - -#define CONFIG_CMD_MTDPARTS - -#endif - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE (64 << 10) -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#undef CONFIG_ENV_IS_IN_NAND -#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \ - CONFIG_ENV_SECT_SIZE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=c0000000\0" \ - "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize};" \ - "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\ - "netdev=eth0\0" \ - "rootpath=/opt/eldk-arm/arm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "kernel_addr_r=c0700000\0" \ - "fdt_addr_r=c0600000\0" \ - "ramdisk_addr_r=c0b00000\0" \ - "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \ - __stringify(CONFIG_HOSTNAME) ".dtb\0" \ - "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \ - "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \ - "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \ - "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \ - "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \ - "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyS2," \ - "${baudrate}n8\0" \ - "net_nfs=run load_fdt load_kernel; " \ - "run nfsargs addip addcon addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\ - "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ - "bootcmd=run net_nfs\0" \ - "machid=e01\0" \ - "key_cmd_0=echo key: 0\0" \ - "key_cmd_1=echo key: 1\0" \ - "key_cmd_2=echo key: 2\0" \ - "key_cmd_3=echo key: 3\0" \ - "key_magic_0=0\0" \ - "key_magic_1=1\0" \ - "key_magic_2=2\0" \ - "key_magic_3=3\0" \ - "magic_keys=0123\0" \ - "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "logversion=2\0" \ - "\0" - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_BOOTDELAY 3 -#define CONFIG_HWCONFIG -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_BOARD_LATE_INIT - -/* - * U-Boot commands - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_CACHE - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#ifdef CONFIG_USE_NAND -#define CONFIG_CMD_NAND - -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_LZO -#define CONFIG_RBTREE -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#endif - -#if !defined(CONFIG_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV -#endif - -#define CONFIG_SYS_TEXT_BASE 0x60000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) - -#define CONFIG_VERSION_VARIABLE -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMC_RESET_PIN 0x04000000 -#define CONFIG_CMC_RESET_TIMEOUT 3 - -#define CONFIG_HW_WATCHDOG -#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE -#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000 -#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 - -#define CONFIG_CMD_DATE -#define CONFIG_RTC_DAVINCI - -/* SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#define CONFIG_MMC_MBLOCK -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MMC - -/* GPIO */ -#define CONFIG_ENBW_CMC_BOARD_TYPE 57 -#define CONFIG_ENBW_CMC_HW_ID_BIT0 39 -#define CONFIG_ENBW_CMC_HW_ID_BIT1 38 -#define CONFIG_ENBW_CMC_HW_ID_BIT2 35 - -/* FDT support */ -#define CONFIG_OF_LIBFDT - -/* LowLevel Init */ -/* PLL */ -#define CONFIG_SYS_DV_CLKMODE 0 -#define CONFIG_SYS_DA850_PLL0_POSTDIV 0 -#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 -#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */ -#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 -#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 -#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 -#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 - -#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 -#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 -#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 - -#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */ -#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */ - -/* DDR RAM */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ - DV_DDR_PHY_EXT_STRBEN | \ - (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \ - (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \ - (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ - (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \ - (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ - (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \ - (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ - (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ - (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ - (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */ - -/* - * freq = 150MHz -> t = 7ns - */ -#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \ - (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ - (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ - (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ - (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \ - ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT)) - -/* - * freq = 150MHz -> t=7ns - */ -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \ - (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \ - (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ - (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ - (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ - (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ - (2 << DV_DDR_SDTMR2_CKE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2 | \ - DAVINCI_SYSCFG_SUSPSRC_EMAC |\ - DAVINCI_SYSCFG_SUSPSRC_I2C) - -#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \ - DAVINCI_ABCR_WSTROBE(6) | \ - DAVINCI_ABCR_WHOLD(1) | \ - DAVINCI_ABCR_RSETUP(2) | \ - DAVINCI_ABCR_RSTROBE(6) | \ - DAVINCI_ABCR_RHOLD(1) | \ - DAVINCI_ABCR_ASIZE_16BIT) - -#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ - DAVINCI_ABCR_WSTROBE(2) | \ - DAVINCI_ABCR_WHOLD(1) | \ - DAVINCI_ABCR_RSETUP(1) | \ - DAVINCI_ABCR_RSTROBE(6) | \ - DAVINCI_ABCR_RHOLD(1) | \ - DAVINCI_ABCR_ASIZE_8BIT) - -/* - * NOR Bootconfiguration word: - * Method: Direc boot - * EMIFA access mode: 16 Bit - */ -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) - -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS -#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE -#define CONFIG_LOGBUFFER -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -#define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE -#define CONFIG_SYS_BOOTCOUNT_BE - -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 3eb8f58d759fa243c09195acff6ff9d6f4e3636f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:05 -0600 Subject: arm: Remove ima3-mx53 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/esg/ima3-mx53/Kconfig | 15 --- board/esg/ima3-mx53/MAINTAINERS | 6 - board/esg/ima3-mx53/Makefile | 9 -- board/esg/ima3-mx53/ima3-mx53.c | 206 --------------------------------- board/esg/ima3-mx53/imximage.cfg | 104 ----------------- configs/ima3-mx53_defconfig | 6 - include/configs/ima3-mx53.h | 238 --------------------------------------- 8 files changed, 589 deletions(-) delete mode 100644 board/esg/ima3-mx53/Kconfig delete mode 100644 board/esg/ima3-mx53/MAINTAINERS delete mode 100644 board/esg/ima3-mx53/Makefile delete mode 100644 board/esg/ima3-mx53/ima3-mx53.c delete mode 100644 board/esg/ima3-mx53/imximage.cfg delete mode 100644 configs/ima3-mx53_defconfig delete mode 100644 include/configs/ima3-mx53.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 34c20e9eb50..277339f60f8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -485,10 +485,6 @@ config TARGET_M53EVK select CPU_V7 select SUPPORT_SPL -config TARGET_IMA3_MX53 - bool "Support ima3-mx53" - select CPU_V7 - config TARGET_MX51EVK bool "Support mx51evk" select CPU_V7 @@ -808,7 +804,6 @@ source "board/creative/xfi3/Kconfig" source "board/davedenx/qong/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" -source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls2085ardb/Kconfig" diff --git a/board/esg/ima3-mx53/Kconfig b/board/esg/ima3-mx53/Kconfig deleted file mode 100644 index d73238f9a90..00000000000 --- a/board/esg/ima3-mx53/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMA3_MX53 - -config SYS_BOARD - default "ima3-mx53" - -config SYS_VENDOR - default "esg" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "ima3-mx53" - -endif diff --git a/board/esg/ima3-mx53/MAINTAINERS b/board/esg/ima3-mx53/MAINTAINERS deleted file mode 100644 index 96de0815c7e..00000000000 --- a/board/esg/ima3-mx53/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IMA3-MX53 BOARD -#M: - -S: Maintained -F: board/esg/ima3-mx53/ -F: include/configs/ima3-mx53.h -F: configs/ima3-mx53_defconfig diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile deleted file mode 100644 index afb8925c741..00000000000 --- a/board/esg/ima3-mx53/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2012, Stefano Babic -# -# Based on ti/evm/Makefile -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ima3-mx53.o diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c deleted file mode 100644 index df758ee6b87..00000000000 --- a/board/esg/ima3-mx53/ima3-mx53.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * (C) Copyright 2012, Stefano Babic - * - * (C) Copyright 2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* NOR flash configuration */ -#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2)) -#define IMA3_MX53_CS0GCR2 0 -#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15)) -#define IMA3_MX53_CS0RCR2 0 -#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15)) -#define IMA3_MX53_CS0WCR2 0 - -DECLARE_GLOBAL_DATA_PTR; - -static void weim_nor_settings(void) -{ - struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; - - writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1); - writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2); - writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1); - writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2); - writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1); - writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2); - writel(0x0, &weim_regs->wcr); - - set_chipselect_size(CS0_128); -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR }; - -int board_mmc_getcd(struct mmc *mmc) -{ - int ret; - - ret = !gpio_get_value(IMX_GPIO_NR(1, 1)); - - return ret; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) -#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - gpio_direction_input(IMX_GPIO_NR(1, 1)); - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} -#endif - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) - -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL), - /* SSEL 0 */ - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); - gpio_direction_output(IMX_GPIO_NR(5, 29), 1); -} - -int board_early_init_f(void) -{ - /* configure I/O pads */ - setup_iomux_uart(); - setup_iomux_fec(); - - weim_nor_settings(); - - /* configure spi */ - setup_iomux_spi(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - mxc_set_sata_internal_clock(); - - return 0; -} - -#if defined(CONFIG_RESET_PHY_R) -#include - -void reset_phy(void) -{ - unsigned short reg; - - /* reset the phy */ - miiphy_reset("FEC", CONFIG_PHY_ADDR); - - /* set hard link to 100Mbit, full-duplex */ - miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®); - reg &= ~BMCR_ANENABLE; - reg |= (BMCR_SPEED100 | BMCR_FULLDPLX); - miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg); - - miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®); - reg |= (1 << 5); - miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg); -} -#endif - -int checkboard(void) -{ - puts("Board: IMA3_MX53\n"); - - return 0; -} diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg deleted file mode 100644 index 324a90e9028..00000000000 --- a/board/esg/ima3-mx53/imximage.cfg +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2012 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM nor - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -/* IOMUX for RAM only */ -DATA 4 0x53fa8554 0x300020 -DATA 4 0x53fa8560 0x300020 -DATA 4 0x53fa8594 0x300020 -DATA 4 0x53fa8584 0x300020 -DATA 4 0x53fa8558 0x300040 -DATA 4 0x53fa8568 0x300040 -DATA 4 0x53fa8590 0x300040 -DATA 4 0x53fa857c 0x300040 -DATA 4 0x53fa8564 0x300040 -DATA 4 0x53fa8580 0x300040 -DATA 4 0x53fa8570 0x300220 -DATA 4 0x53fa8578 0x300220 -DATA 4 0x53fa872c 0x300000 -DATA 4 0x53fa8728 0x300000 -DATA 4 0x53fa871c 0x300000 -DATA 4 0x53fa8718 0x300000 -DATA 4 0x53fa8574 0x300020 -DATA 4 0x53fa8588 0x300020 -DATA 4 0x53fa855c 0x0 -DATA 4 0x53fa858c 0x0 -DATA 4 0x53fa856c 0x300040 -DATA 4 0x53fa86f0 0x300000 -DATA 4 0x53fa8720 0x300000 -DATA 4 0x53fa86fc 0x0 -DATA 4 0x53fa86f4 0x0 -DATA 4 0x53fa8714 0x0 -DATA 4 0x53fa8724 0x4000000 - -/* DDR RAM */ -DATA 4 0x63fd9088 0x40404040 -DATA 4 0x63fd9090 0x40404040 -DATA 4 0x63fd907C 0x01420143 -DATA 4 0x63fd9080 0x01450146 -DATA 4 0x63fd9018 0x00111740 -DATA 4 0x63fd9000 0x84190000 - -/* esdcfgX */ -DATA 4 0x63fd900C 0x9f5152e3 -DATA 4 0x63fd9010 0xb68e8a63 -DATA 4 0x63fd9014 0x01ff00db - -/* Read/Write command delay */ -DATA 4 0x63fd902c 0x000026d2 - -/* Out of reset delays */ -DATA 4 0x63fd9030 0x00ff0e21 - -/* ESDCTL ODT timing control */ -DATA 4 0x63fd9008 0x12273030 - -/* ESDCTL power down control */ -DATA 4 0x63fd9004 0x0002002d - -/* Set registers in DDR memory chips */ -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x052080b0 -DATA 4 0x63fd901c 0x04008040 - -/* ESDCTL refresh control */ -DATA 4 0x63fd9020 0x00005800 - -/* PHY ZQ HW control */ -DATA 4 0x63fd9040 0x05380003 - -/* PHY ODT control */ -DATA 4 0x63fd9058 0x00022222 - -/* start DDR3 */ -DATA 4 0x63fd901c 0x00000000 diff --git a/configs/ima3-mx53_defconfig b/configs/ima3-mx53_defconfig deleted file mode 100644 index 1f5e3a69116..00000000000 --- a/configs/ima3-mx53_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMA3_MX53=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg" -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y -CONFIG_SYS_PROMPT="IMA3 MX53 U-Boot > " diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h deleted file mode 100644 index 2fa6c3d91ba..00000000000 --- a/include/configs/ima3-mx53.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * (C) Copyright 2012, Stefano Babic - * - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53-EVK Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SOC type must be included before imx-regs.h */ -#define CONFIG_MX53 -#include - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_OF_LIBFDT - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F - -/* Enable GPIOs */ -#define CONFIG_MXC_GPIO - -/* UART */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - -/* MMC */ -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION - -/* Ethernet on FEC */ -#define CONFIG_MII - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x01 -#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR -#define CONFIG_RESET_PHY_R -#define CONFIG_FEC_MXC_NO_ANEG -#define CONFIG_ETHPRIME "FEC0" - -/* SPI */ -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 - -/* SPI FLASH - not used for environment */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_GPIO - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ -#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */ - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nor0=f0000000.flash" - -/* FLASH and environment organization */ - -#define CONFIG_SYS_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ -#define CONFIG_FLASH_CFI_MTD /* with MTD support */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define HOSTNAME ima3-mx53 - -#define CONFIG_HOSTNAME ima3-mx53 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram0 rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${console},${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "console=ttymxc3\0" \ - "loadaddr=70800000\0" \ - "kernel_addr_r=70800000\0" \ - "ramdisk_addr_r=71000000\0" \ - "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ - "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ - "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ - "mmcargs=setenv bootargs root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addip addtty addmtd addmisc mmcload;" \ - "bootm\0" \ - "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \ - "${loadaddr} ${uimage}\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \ - "tftp ${kernel_addr_r} ${bootfile}\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "satargs=setenv bootargs root=/dev/sda1\0" \ - "satafile=boot/uImage\0" \ - "ssdboot=echo Booting from ssd ...; " \ - "run satargs addip addtty addmtd addmisc;" \ - "sata init;ext2load sata 0:1 ${kernel_addr_r} " \ - "${satafile};bootm\0" \ - "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \ - "uimage=uImage\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=0xf0001000\0" \ - "update=protect off 0xf0000000 +60000;" \ - "erase ${uboot_addr} +60000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - - -#define CONFIG_CMD_SATA -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA - #define CONFIG_SYS_SATA_MAX_DEVICE 1 - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR - #define CONFIG_LBA48 - #define CONFIG_LIBATA -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From bc0840bcb73277bb36a8ecd59653d6b0e4287e99 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:06 -0600 Subject: arm: Remove imx27lite, imx27_litekit and magnesium boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 9 -- board/logicpd/imx27lite/Kconfig | 31 ------- board/logicpd/imx27lite/MAINTAINERS | 12 --- board/logicpd/imx27lite/Makefile | 9 -- board/logicpd/imx27lite/imx27lite.c | 77 ---------------- board/logicpd/imx27lite/lowlevel_init.S | 156 -------------------------------- configs/imx27lite_defconfig | 3 - configs/magnesium_defconfig | 3 - include/configs/imx27lite.h | 49 ---------- include/configs/magnesium.h | 58 ------------ 10 files changed, 407 deletions(-) delete mode 100644 board/logicpd/imx27lite/Kconfig delete mode 100644 board/logicpd/imx27lite/MAINTAINERS delete mode 100644 board/logicpd/imx27lite/Makefile delete mode 100644 board/logicpd/imx27lite/imx27lite.c delete mode 100644 board/logicpd/imx27lite/lowlevel_init.S delete mode 100644 configs/imx27lite_defconfig delete mode 100644 configs/magnesium_defconfig delete mode 100644 include/configs/imx27lite.h delete mode 100644 include/configs/magnesium.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 277339f60f8..6daa969dd6d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -152,14 +152,6 @@ config TARGET_APF27 select CPU_ARM926EJS select SUPPORT_SPL -config TARGET_IMX27LITE - bool "Support imx27lite" - select CPU_ARM926EJS - -config TARGET_MAGNESIUM - bool "Support magnesium" - select CPU_ARM926EJS - config TARGET_APX4DEVKIT bool "Support apx4devkit" select CPU_ARM926EJS @@ -831,7 +823,6 @@ source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" -source "board/logicpd/imx27lite/Kconfig" source "board/logicpd/imx31_litekit/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" diff --git a/board/logicpd/imx27lite/Kconfig b/board/logicpd/imx27lite/Kconfig deleted file mode 100644 index c7de2e3814c..00000000000 --- a/board/logicpd/imx27lite/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if TARGET_IMX27LITE - -config SYS_BOARD - default "imx27lite" - -config SYS_VENDOR - default "logicpd" - -config SYS_SOC - default "mx27" - -config SYS_CONFIG_NAME - default "imx27lite" - -endif - -if TARGET_MAGNESIUM - -config SYS_BOARD - default "imx27lite" - -config SYS_VENDOR - default "logicpd" - -config SYS_SOC - default "mx27" - -config SYS_CONFIG_NAME - default "magnesium" - -endif diff --git a/board/logicpd/imx27lite/MAINTAINERS b/board/logicpd/imx27lite/MAINTAINERS deleted file mode 100644 index a7b22ac049d..00000000000 --- a/board/logicpd/imx27lite/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -IMX27LITE BOARD -M: Wolfgang Denk -S: Maintained -F: board/logicpd/imx27lite/ -F: include/configs/imx27lite.h -F: configs/imx27lite_defconfig - -MAGNESIUM BOARD -M: Heiko Schocher -S: Maintained -F: include/configs/magnesium.h -F: configs/magnesium_defconfig diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile deleted file mode 100644 index 50a3da62ed1..00000000000 --- a/board/logicpd/imx27lite/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := imx27lite.o -obj-y += lowlevel_init.o diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c deleted file mode 100644 index 07b07a07f69..00000000000 --- a/board/logicpd/imx27lite/imx27lite.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2008,2009 Eric Jarrige - * Copyright (C) 2009 Ilya Yanok - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ -#if defined(CONFIG_SYS_NAND_LARGEPAGE) - struct system_control_regs *sc_regs = - (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; -#endif - - gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - -#ifdef CONFIG_MXC_UART - mx27_uart1_init_pins(); -#endif -#ifdef CONFIG_FEC_MXC - mx27_fec_init_pins(); - imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31)); - gpio_set_value(GPIO_PORTC | 31, 1); -#endif -#ifdef CONFIG_MXC_MMC -#if defined(CONFIG_MAGNESIUM) - mx27_sd1_init_pins(); -#else - mx27_sd2_init_pins(); -#endif -#endif - -#if defined(CONFIG_SYS_NAND_LARGEPAGE) - /* - * set in FMCR NF_FMS Bit(5) to 1 - * (NAND Flash with 2 Kbyte page size) - */ - writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr); -#endif - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); -#endif -} - -int checkboard(void) -{ - puts("Board: "); - puts(CONFIG_BOARDNAME); - return 0; -} diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S deleted file mode 100644 index 9cb702f30f3..00000000000 --- a/board/logicpd/imx27lite/lowlevel_init.S +++ /dev/null @@ -1,156 +0,0 @@ -/* - * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia - * Applications Processor Reference Manual, Rev. 0.2". - * - * (C) Copyright 2008 Eric Jarrige - * (C) Copyright 2009 Ilya Yanok - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include -#include - -SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE -SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE -SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0) -SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3) -SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \ - ESDCTL_ROW13 | ESDCTL_COL10) -SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \ - ESDCTL_ROW13 | ESDCTL_COL10) -SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \ - ESDCTL_ROW13 | ESDCTL_COL10) -SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL - -.macro init_aipi - /* - * setup AIPI1 and AIPI2 - */ - write32 AIPI1_PSR0, AIPI1_PSR0_VAL - write32 AIPI1_PSR1, AIPI1_PSR1_VAL - write32 AIPI2_PSR0, AIPI2_PSR0_VAL - write32 AIPI2_PSR1, AIPI2_PSR1_VAL - -.endm /* init_aipi */ - -.macro init_clock - ldr r0, =CSCR - /* disable MPLL/SPLL first */ - ldr r1, [r0] - bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) - str r1, [r0] - - write32 MPCTL0, MPCTL0_VAL - write32 SPCTL0, SPCTL0_VAL - - write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART - - /* - * add some delay here - */ - wait_timer 0x1000 - - /* peripheral clock divider */ - write32 PCDR0, PCDR0_VAL - write32 PCDR1, PCDR1_VAL - - /* Configure PCCR0 and PCCR1 */ - write32 PCCR0, PCCR0_VAL - write32 PCCR1, PCCR1_VAL - -.endm /* init_clock */ - -.macro sdram_init - ldr r0, SOC_ESDCTL_BASE_W - mov r2, #PHYS_SDRAM_1 - - /* Do initial reset */ - mov r1, #ESDMISC_MDDR_DL_RST - str r1, [r0, #ESDMISC_ROF] - - /* Hold for more than 200ns */ - wait_timer 0x10000 - - /* Activate LPDDR iface */ - mov r1, #ESDMISC_MDDREN - str r1, [r0, #ESDMISC_ROF] - - /* Check The chip version TO1 or TO2 */ - ldr r1, SOC_SI_ID_REG_W - ldr r1, [r1] - ands r1, r1, #0xF0000000 - /* add Latency on CAS only for TO2 */ - ldreq r1, SDRAM_ESDCFG_T2_W - ldrne r1, SDRAM_ESDCFG_T1_W - str r1, [r0, #ESDCFG0_ROF] - - /* Run initialization sequence */ - ldr r1, SDRAM_PRECHARGE_CMD_W - str r1, [r0, #ESDCTL0_ROF] - ldr r1, [r2, #SDRAM_ALL_VAL] - - ldr r1, SDRAM_AUTOREF_CMD_W - str r1, [r0, #ESDCTL0_ROF] - ldr r1, [r2, #SDRAM_ALL_VAL] - ldr r1, [r2, #SDRAM_ALL_VAL] - - ldr r1, SDRAM_LOADMODE_CMD_W - str r1, [r0, #ESDCTL0_ROF] - ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL] - add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL - ldrb r1, [r3] - - ldr r1, SDRAM_NORMAL_CMD_W - str r1, [r0, #ESDCTL0_ROF] - -#if (CONFIG_NR_DRAM_BANKS > 1) - /* 2nd sdram */ - mov r2, #PHYS_SDRAM_2 - - /* Check The chip version TO1 or TO2 */ - ldr r1, SOC_SI_ID_REG_W - ldr r1, [r1] - ands r1, r1, #0xF0000000 - /* add Latency on CAS only for TO2 */ - ldreq r1, SDRAM_ESDCFG_T2_W - ldrne r1, SDRAM_ESDCFG_T1_W - str r1, [r0, #ESDCFG1_ROF] - - /* Run initialization sequence */ - ldr r1, SDRAM_PRECHARGE_CMD_W - str r1, [r0, #ESDCTL1_ROF] - ldr r1, [r2, #SDRAM_ALL_VAL] - - ldr r1, SDRAM_AUTOREF_CMD_W - str r1, [r0, #ESDCTL1_ROF] - ldr r1, [r2, #SDRAM_ALL_VAL] - ldr r1, [r2, #SDRAM_ALL_VAL] - - ldr r1, SDRAM_LOADMODE_CMD_W - str r1, [r0, #ESDCTL1_ROF] - ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL] - add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL - ldrb r1, [r3] - - ldr r1, SDRAM_NORMAL_CMD_W - str r1, [r0, #ESDCTL1_ROF] -#endif /* CONFIG_NR_DRAM_BANKS > 1 */ - -.endm /* sdram_init */ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - init_aipi - - init_clock - - sdram_init - - mov pc,r10 diff --git a/configs/imx27lite_defconfig b/configs/imx27lite_defconfig deleted file mode 100644 index b02955d6c7d..00000000000 --- a/configs/imx27lite_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX27LITE=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/magnesium_defconfig b/configs/magnesium_defconfig deleted file mode 100644 index 2fa658911dc..00000000000 --- a/configs/magnesium_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MAGNESIUM=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h deleted file mode 100644 index c18c35ef53d..00000000000 --- a/include/configs/imx27lite.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2009 Ilya Yanok - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all imx27lite related boards */ -#include "imx27lite-common.h" -/* - * SoC Configuration - */ -#define CONFIG_IMX27LITE -#define CONFIG_HOSTNAME imx27 -#define CONFIG_BOARDNAME "LogicPD imx27lite\n" - -/* - * Flash & Environment - */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ -#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) -#define PHYS_FLASH_SIZE 0x200000 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ - -/* - * SD/MMC - */ -#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 - -/* - * MTD partitions - */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=" \ - "physmap-flash.0:" \ - "256k(U-Boot)," \ - "1664k(user)," \ - "64k(env1)," \ - "64k(env2);" \ - "mxc_nand.0:" \ - "128k(IPL-SPL)," \ - "4m(kernel)," \ - "22m(rootfs)," \ - "-(userfs)" - -#endif /* __CONFIG_H */ diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h deleted file mode 100644 index 3364bde71fc..00000000000 --- a/include/configs/magnesium.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2010 Heiko Schocher - * - * based on: - * Copyright (C) 2009 Ilya Yanok - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* include common defines/options for all imx27lite related boards */ -#include "imx27lite-common.h" - -/* - * SoC Configuration - */ -#define CONFIG_MAGNESIUM -#define CONFIG_HOSTNAME magnesium -#define CONFIG_BOARDNAME "Projectiondesign magnesium\n" - -/* - * Flash & Environment - */ -#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */ -#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000) -#define PHYS_FLASH_SIZE 0x800000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */ - -/* - * NAND - */ -#define CONFIG_SYS_NAND_LARGEPAGE - -/* - * SD/MMC - */ -#define CONFIG_MXC_MCI_REGS_BASE 0x10013000 - -/* - * MTD partitions - */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" -#define MTDPARTS_DEFAULT \ - "mtdparts=" \ - "physmap-flash.0:" \ - "256k(U-Boot)," \ - "7680k(user)," \ - "128k(env1)," \ - "128k(env2);" \ - "mxc_nand.0:" \ - "128k(IPL-SPL)," \ - "4m(kernel)," \ - "22m(rootfs)," \ - "-(userfs)" - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 36d14178fc4b3c31be7327209c8347ebe4774830 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:07 -0600 Subject: arm: Remove mx31_litekit board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/logicpd/imx31_litekit/Kconfig | 15 --- board/logicpd/imx31_litekit/MAINTAINERS | 6 - board/logicpd/imx31_litekit/Makefile | 9 -- board/logicpd/imx31_litekit/imx31_litekit.c | 91 --------------- board/logicpd/imx31_litekit/lowlevel_init.S | 87 -------------- configs/imx31_litekit_defconfig | 4 - include/configs/imx31_litekit.h | 171 ---------------------------- 8 files changed, 388 deletions(-) delete mode 100644 board/logicpd/imx31_litekit/Kconfig delete mode 100644 board/logicpd/imx31_litekit/MAINTAINERS delete mode 100644 board/logicpd/imx31_litekit/Makefile delete mode 100644 board/logicpd/imx31_litekit/imx31_litekit.c delete mode 100644 board/logicpd/imx31_litekit/lowlevel_init.S delete mode 100644 configs/imx31_litekit_defconfig delete mode 100644 include/configs/imx31_litekit.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6daa969dd6d..f92fa5a9781 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -260,10 +260,6 @@ config TARGET_TT01 bool "Support tt01" select CPU_ARM1136 -config TARGET_IMX31_LITEKIT - bool "Support imx31_litekit" - select CPU_ARM1136 - config TARGET_WOODBURN bool "Support woodburn" select CPU_ARM1136 @@ -823,7 +819,6 @@ source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" -source "board/logicpd/imx31_litekit/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" diff --git a/board/logicpd/imx31_litekit/Kconfig b/board/logicpd/imx31_litekit/Kconfig deleted file mode 100644 index d90f854a18b..00000000000 --- a/board/logicpd/imx31_litekit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMX31_LITEKIT - -config SYS_BOARD - default "imx31_litekit" - -config SYS_VENDOR - default "logicpd" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "imx31_litekit" - -endif diff --git a/board/logicpd/imx31_litekit/MAINTAINERS b/board/logicpd/imx31_litekit/MAINTAINERS deleted file mode 100644 index 8e3608e0af9..00000000000 --- a/board/logicpd/imx31_litekit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IMX31_LITEKIT BOARD -#M: - -S: Maintained -F: board/logicpd/imx31_litekit/ -F: include/configs/imx31_litekit.h -F: configs/imx31_litekit_defconfig diff --git a/board/logicpd/imx31_litekit/Makefile b/board/logicpd/imx31_litekit/Makefile deleted file mode 100644 index 3fd71c8debf..00000000000 --- a/board/logicpd/imx31_litekit/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := imx31_litekit.o -obj-y += lowlevel_init.o diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c deleted file mode 100644 index 386e106324f..00000000000 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - /* CS0: Nor Flash */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) - }; - - /* CS4: Network Controller */ - static const struct mxc_weimcs cs4 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) - }; - - mxc_setup_weimcs(0, &cs0); - mxc_setup_weimcs(4, &cs4); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* SPI2 */ - mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); - - /* start SPI2 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - - return 0; -} - -int checkboard(void) -{ - printf("Board: i.MX31 Litekit\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S deleted file mode 100644 index 7c456bc4a78..00000000000 --- a/board/logicpd/imx31_litekit/lowlevel_init.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -.globl lowlevel_init -lowlevel_init: - - REG IPU_CONF, IPU_CONF_DI_EN - REG CCM_CCMR, 0x074B0BF5 - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - - REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0) - - REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23) - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - - REG 0x43FAC26C, 0 /* SDCLK */ - REG 0x43FAC270, 0 /* CAS */ - REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ - REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - REG 0x43FAC28C, 0 - REG 0x43FAC290, 0 - REG 0x43FAC294, 0 - REG 0x43FAC298, 0 - REG 0x43FAC29C, 0 - REG 0x43FAC2A0, 0 - REG 0x43FAC2A4, 0 - REG 0x43FAC2A8, 0 - REG 0x43FAC2AC, 0 - REG 0x43FAC2B0, 0 - REG 0x43FAC2B4, 0 - REG 0x43FAC2B8, 0 - REG 0x43FAC2BC, 0 - REG 0x43FAC2C0, 0 - REG 0x43FAC2C4, 0 - REG 0x43FAC2C8, 0 - REG 0x43FAC2CC, 0 - REG 0x43FAC2D0, 0 - REG 0x43FAC2D4, 0 - REG 0x43FAC2D8, 0 - REG 0x43FAC2DC, 0 - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr diff --git a/configs/imx31_litekit_defconfig b/configs/imx31_litekit_defconfig deleted file mode 100644 index f10759b8aa1..00000000000 --- a/configs/imx31_litekit_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_LITEKIT=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="uboot> " diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h deleted file mode 100644 index 23e3a6c5fc1..00000000000 --- a/include/configs/imx31_litekit.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff - * Kshitij Gupta - * - * Configuration settings for the LogicPD i.MX31 Litekit board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX31 1 /* This is a mx31 */ -#define CONFIG_MX31_CLK32 32000 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE - -/* Temporarily disabled */ -#if 0 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT 1 -#define CONFIG_FIT_VERBOSE 1 -#endif - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_MXC_GPIO - -#define CONFIG_HARD_SPI 1 -#define CONFIG_MXC_SPI 1 -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NAND - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ - "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0" - - -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000) -#define CONFIG_SMC911X_32_BIT 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ - -#define CONFIG_CMDLINE_EDITING 1 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000) -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SIZE (64 * 1024) - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* - * JFFS2 partitions - */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" - -/* - * NAND flash - */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR -#define CONFIG_MXC_NAND_HWECC - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From df0b116de160218426faa31fe6339f0e6678ae4f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:09 -0600 Subject: arm: Remove jornada board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 -- board/jornada/Kconfig | 9 --- board/jornada/MAINTAINERS | 6 -- board/jornada/Makefile | 11 --- board/jornada/jornada.c | 44 ----------- board/jornada/setup.S | 194 ---------------------------------------------- configs/jornada_defconfig | 9 --- include/configs/jornada.h | 123 ----------------------------- 8 files changed, 401 deletions(-) delete mode 100644 board/jornada/Kconfig delete mode 100644 board/jornada/MAINTAINERS delete mode 100644 board/jornada/Makefile delete mode 100644 board/jornada/jornada.c delete mode 100644 board/jornada/setup.S delete mode 100644 configs/jornada_defconfig delete mode 100644 include/configs/jornada.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f92fa5a9781..8544b4222ef 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -684,10 +684,6 @@ config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA -config TARGET_JORNADA - bool "Support jornada" - select CPU_SA1100 - config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select CPU_V7 @@ -817,7 +813,6 @@ source "board/hisilicon/hikey/Kconfig" source "board/icpdas/lp8x4x/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" -source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" diff --git a/board/jornada/Kconfig b/board/jornada/Kconfig deleted file mode 100644 index 195bc26f9e8..00000000000 --- a/board/jornada/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_JORNADA - -config SYS_BOARD - default "jornada" - -config SYS_CONFIG_NAME - default "jornada" - -endif diff --git a/board/jornada/MAINTAINERS b/board/jornada/MAINTAINERS deleted file mode 100644 index c77d7457203..00000000000 --- a/board/jornada/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -JORNADA BOARD -M: Kristoffer Ericson -S: Maintained -F: board/jornada/ -F: include/configs/jornada.h -F: configs/jornada_defconfig diff --git a/board/jornada/Makefile b/board/jornada/Makefile deleted file mode 100644 index 6a6fbf35513..00000000000 --- a/board/jornada/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# 2004 (c) MontaVista Software, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := jornada.o -obj-y += setup.o diff --git a/board/jornada/jornada.c b/board/jornada/jornada.c deleted file mode 100644 index ff6dbf0ed4e..00000000000 --- a/board/jornada/jornada.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2004 (c) MontaVista Software, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_JORNADA720; - gd->bd->bi_boot_params = 0xc0000100; - - - /* - * Turn on flashing. - * Would be nice to have some protection but - * that would have to be implemented in the - * flash init function, which isnt possible yet. - */ - PPSR |= (1 << 7); - PPDR |= (1 << 7); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return (0); -} diff --git a/board/jornada/setup.S b/board/jornada/setup.S deleted file mode 100644 index da9f00646da..00000000000 --- a/board/jornada/setup.S +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * 2004 (c) MontaVista Software, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include "config.h" -#include "version.h" - - -/*----------------------------------------------------------------------- - * Board defines: - */ - -#define MDCNFG 0x00 -#define MDCAS00 0x04 -#define MDCAS01 0x08 -#define MDCAS02 0x0C -#define MSC0 0x10 -#define MSC1 0x14 -#define MECR 0x18 -#define MDREFR 0x1C -#define MDCAS20 0x20 -#define MDCAS21 0x24 -#define MDCAS22 0x28 -#define MSC2 0x2C -#define SMCNFG 0x30 - -#define GPDR 0x04 -#define GPSR 0x08 -#define GPCR 0x0C -#define GAFR 0x1C - -#define PPDR 0x00 -#define PPSR 0x04 -#define PPAR 0x08 - -#define MDREFR_TRASR(n_) (n_ & (0x0000000f)) -#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4) -#define MDREFR_K0DB2 (1 << 18) -#define MDREFR_K1DB2 (1 << 22) -#define MDREFR_K2DB2 (1 << 26) - -#define MDREFR_K0RUN (1 << 17) -#define MDREFR_K1RUN (1 << 21) -#define MDREFR_K2RUN (1 << 25) - -#define MDREFR_SLFRSH (1 << 31) -#define MDREFR_E1PIN (1 << 20) - -#define PSSR 0x04 -#define PSSR_DH 0x00000008 -#define POSR 0x08 -#define RCSR 0x04 - -/*----------------------------------------------------------------------- - * Setup parameters for the board: - */ -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 -PWR_BASE: .word 0x90020000 -RST_BASE: .long 0x90030000 -PPC_BASE: .long 0x90060000 -GPIO_BASE: .long 0x90040000 -IC_BASE: .word 0x90050000 - -cpuspeed: .word 0xa0 -/* calculated from old blob bootloader */ -mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */ -mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */ -mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */ -mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */ -msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */ -msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */ -mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */ -mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */ -mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */ -mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */ -mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */ -msc2: .long 0x201d2959 /* msc2 0x201d2959 */ -smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */ - -pin_set_out: .long 0x37ff70 -pin_set_dir: .long 0x11480 - -gpdr_set: .long 0x0B3A0900 -gpsr_set: .long 0x02100800 -gpcr_set: .long 0x092A0100 -gafr_set: .long 0x08600000 - -.globl lowlevel_init -lowlevel_init: - - - /* this is required for flashing */ - ldr r0, PPC_BASE - ldr r1, pin_set_out - str r1, [r0, #PPSR] - ldr r1, pin_set_dir - str r1, [r0, #PPDR] - - /* Setting up the memory and stuff */ - /***********************************/ - - ldr r0, MEM_BASE - - ldr r1, mdcnfg - str r1, [r0, #MDCNFG] - ldr r1, mdcas00 - str r1, [r0, #MDCAS00] - ldr r1, mdcas01 - str r1, [r0, #MDCAS01] - ldr r1, mdcas02 - str r1, [r0, #MDCAS02] - ldr r1, mdcas20 - str r1, [r0, #MDCAS20] - ldr r1, mdcas21 - str r1, [r0, #MDCAS21] - ldr r1, mdcas22 - str r1, [r0, #MDCAS22] - - /* clear kxDB2 */ - ldr r2, [r0, #MDREFR] - bic r2, r2, #MDREFR_K0DB2 - bic r2, r2, #MDREFR_K1DB2 - bic r2, r2, #MDREFR_K2DB2 - str r2, [r0, #MDREFR] - - ldr r2, [r0, #MDREFR] - orr r2, r2, #MDREFR_TRASR(7) - - mov r4, #0x2000 - spin: subs r4, r4, #1 - bne spin - - ldr r1, PWR_BASE - mov r2, #PSSR_DH - str r2, [r1, #PSSR] - - ldr r2, [r0, #MDREFR] - bic r2, r2, #MDREFR_K0DB2 - bic r2, r2, #MDREFR_K1DB2 - bic r2, r2, #MDREFR_K2DB2 - str r2, [r0, #MDREFR] - - ldr r2, [r0, #MDREFR] - orr r2, r2, #MDREFR_TRASR(7) - orr r2, r2, #MDREFR_DRI(12) - orr r2, r2, #MDREFR_K0DB2 - orr r2, r2, #MDREFR_K1DB2 - orr r2, r2, #MDREFR_K2DB2 - str r2, [r0, #MDREFR] - - ldr r2, [r0, #MDREFR] - orr r2, r2, #MDREFR_K0RUN - orr r2, r2, #MDREFR_K1RUN - orr r2, r2, #MDREFR_K2RUN - str r2, [r0, #MDREFR] - - ldr r2, [r0, #MDREFR] - bic r2, r2, #MDREFR_SLFRSH - str r2, [r0, #MDREFR] - - ldr r2, [r0, #MDREFR] - orr r2, r2, #MDREFR_E1PIN - str r2, [r0, #MDREFR] - - ldr r2, MEM_START -.rept 8 - ldr r3, [r2] -.endr - - ldr r2, [r0, #MDCNFG] - orr r2, r2, #0x00000003 - orr r2, r2, #0x00030000 - str r2, [r0, #MDCNFG] - - ldr r1, msc0 - str r1, [r0, #MSC0] - ldr r1, msc1 - str r1, [r0, #MSC1] - ldr r1, msc2 - str r1, [r0, #MSC2] - ldr r1, smcnfg - str r1, [r0, #SMCNFG] - ldr r1, mecr - str r1, [r0, #MECR] - - mov pc, lr diff --git a/configs/jornada_defconfig b/configs/jornada_defconfig deleted file mode 100644 index 65cbc2a1071..00000000000 --- a/configs/jornada_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_JORNADA=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_MISC is not set -CONFIG_SYS_PROMPT="HP Jornada# " diff --git a/include/configs/jornada.h b/include/configs/jornada.h deleted file mode 100644 index 30904763405..00000000000 --- a/include/configs/jornada.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright 2010 (C) - * Kristoffer Ericson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA110 CPU */ -#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -#define CONFIG_SYS_TEXT_BASE 0xC1F00000 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* Console setting */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * select serial console configuration - */ -#define CONFIG_SA1100_SERIAL 1 -#define CONFIG_SERIAL3 1 /* we use serial 3 */ -#define CONFIG_BAUDRATE 19200 -#define CONFIG_LOADS_ECHO 1 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_JFFS2 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1" -#define CONFIG_BOOTCOMMAND "run boot_kernel" -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ -#define CONFIG_SYS_LOAD_ADDR 0xc0000000 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* console buffsize */ -#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */ -#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */ -#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_ERASE_TOUT (4096) -#define CONFIG_SYS_FLASH_WRITE_TOUT (4096) -#define CONFIG_SYS_FLASH_INCREMENT 0x02000000 -#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 260 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_FLASH_SHOW_PROGRESS 1 - -/* Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x00040000 -#define CONFIG_ENV_OFFSET 0x00040000 -#define CONFIG_ENV_SIZE 0x00040000 -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - Monitor - 0x00000000 - 0x00040000 (256kb) - Environment - 0x00040000 - 0x00080000 (256kb) - Kernel - 0x00080000 - 0x00380000 (3mb) - Rootfs - 0x00380000 - 0x........ (rest) -*/ - -#define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_INIT_SP_ADDR 0x0 -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=jornada7xx-0" -#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\ - "3m(kernel),-(user);" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "flash_kernel=protect off all; " \ - "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \ - "flash_uboot=protect off all; " \ - "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \ - "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0" -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 9f840b8d56a98abc75d0a97449230e44f60b6e62 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:10 -0600 Subject: arm: Remove lp8x4x board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/icpdas/lp8x4x/Kconfig | 12 -- board/icpdas/lp8x4x/MAINTAINERS | 6 - board/icpdas/lp8x4x/Makefile | 9 -- board/icpdas/lp8x4x/lp8x4x.c | 128 --------------------- configs/lp8x4x_defconfig | 4 - include/configs/lp8x4x.h | 238 ---------------------------------------- 7 files changed, 402 deletions(-) delete mode 100644 board/icpdas/lp8x4x/Kconfig delete mode 100644 board/icpdas/lp8x4x/MAINTAINERS delete mode 100644 board/icpdas/lp8x4x/Makefile delete mode 100644 board/icpdas/lp8x4x/lp8x4x.c delete mode 100644 configs/lp8x4x_defconfig delete mode 100644 include/configs/lp8x4x.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8544b4222ef..6365e8f9004 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -676,10 +676,6 @@ config TARGET_ZIPITZ2 bool "Support zipitz2" select CPU_PXA -config TARGET_LP8X4X - bool "Support lp8x4x" - select CPU_PXA - config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -810,7 +806,6 @@ source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hale/tt01/Kconfig" source "board/hisilicon/hikey/Kconfig" -source "board/icpdas/lp8x4x/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/karo/tx25/Kconfig" diff --git a/board/icpdas/lp8x4x/Kconfig b/board/icpdas/lp8x4x/Kconfig deleted file mode 100644 index 3e87c4016ba..00000000000 --- a/board/icpdas/lp8x4x/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_LP8X4X - -config SYS_BOARD - default "lp8x4x" - -config SYS_VENDOR - default "icpdas" - -config SYS_CONFIG_NAME - default "lp8x4x" - -endif diff --git a/board/icpdas/lp8x4x/MAINTAINERS b/board/icpdas/lp8x4x/MAINTAINERS deleted file mode 100644 index 90a82e3fe44..00000000000 --- a/board/icpdas/lp8x4x/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -LP8X4X BOARD -M: Sergey Yanovich -S: Maintained -F: board/icpdas/lp8x4x/ -F: include/configs/lp8x4x.h -F: configs/lp8x4x_defconfig diff --git a/board/icpdas/lp8x4x/Makefile b/board/icpdas/lp8x4x/Makefile deleted file mode 100644 index 88e0606e1e9..00000000000 --- a/board/icpdas/lp8x4x/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# ICPDAS LP-8x4x Support -# -# Copyright (C) 2013 Sergey Yanovich -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := lp8x4x.o diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c deleted file mode 100644 index a136dc4c37a..00000000000 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * ICP DAS LP-8x4x Support - * - * Copyright (C) 2010 Marek Vasut - * adapted from Voipac PXA270 Support by - * Copyright (C) 2013 Sergey Yanovich - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - if (index !=0 || init != USB_INIT_HOST) - return -1; - - writel(readl(CKEN) | CKEN10_USBHOST, CKEN); - - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (readl(UHCHR) & UHCHR_FSBIR) - continue; /* required by checkpath.pl */ - - writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); - writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA); - writel(readl(UHCRHDA) | 0x800, UHCRHDA); - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); - writel(readl(UHCRHDA) | 0x100, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - - return 0; -} - -int usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - if (index !=0 || init != USB_INIT_HOST) - return -1; - - return usb_board_stop(); -} -#endif - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/configs/lp8x4x_defconfig b/configs/lp8x4x_defconfig deleted file mode 100644 index 63bbccaf7c8..00000000000 --- a/configs/lp8x4x_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LP8X4X=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h deleted file mode 100644 index 10a7b05daf3..00000000000 --- a/include/configs/lp8x4x.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * ICP DAS LP-8x4x configuration file - * - * Copyright (C) 2013 Sergey Yanovich - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */ -#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */ -#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOOTCOMMAND \ - "bootm 80000 - 240000;" - -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ - "init=/sbin/init rootfstype=ext4 rootwait" - -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_LZMA /* LZMA compression support */ -#define CONFIG_OF_LIBFDT - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_USB -#undef CONFIG_LCD -#undef CONFIG_CMD_IDE - -/* - * Networking Configuration - * chip on the ICPDAS LINPAC board - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x0C000000 -#define DM9000_IO 0x0C000000 -#define DM9000_DATA 0x0C004000 -#define DM9000_IO_2 0x0D000000 -#define DM9000_DATA_2 0x0D004000 -#define CONFIG_NET_RETRY_COUNT 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#endif - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa0008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Use first 64kb bank of the internal SRAM */ -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x0808c014 -#define CONFIG_SYS_GPSR1_VAL 0x00cf0002 -#define CONFIG_SYS_GPSR2_VAL 0x0221c000 -#define CONFIG_SYS_GPSR3_VAL 0x00020000 - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x0000ab80 -#define CONFIG_SYS_GPCR2_VAL 0x00100000 -#define CONFIG_SYS_GPCR3_VAL 0x0 - -#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4 -#define CONFIG_SYS_GPDR1_VAL 0xfcffab83 -#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff -#define CONFIG_SYS_GPDR3_VAL 0x00021b81 - -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018 -#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402 -#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c -#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 - -#define CONFIG_SYS_PSSR_VAL 0x32 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x005002c0 -#define CONFIG_SYS_CCCR 0x02000290 -#define CONFIG_SYS_CLKCFG 0x0000000b - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2 -#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc -#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_MDREFR_VAL 0x2093e018 -#define CONFIG_SYS_MDCNFG_VAL 0x890009d1 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x0000c497 -#define CONFIG_SYS_MCMEM1_VAL 0x0000c497 -#define CONFIG_SYS_MCATT0_VAL 0x0000c497 -#define CONFIG_SYS_MCATT1_VAL 0x0000c497 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x00008407 - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x" -#define CONFIG_USB_STORAGE -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 7cd768cf2c398a70d18ce4d4078586957ccf5e20 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:12 -0600 Subject: arm: Remove mv88f6281gtw_ge board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/mv88f6281gtw_ge/Kconfig | 12 -- board/Marvell/mv88f6281gtw_ge/MAINTAINERS | 6 - board/Marvell/mv88f6281gtw_ge/Makefile | 9 -- board/Marvell/mv88f6281gtw_ge/kwbimage.cfg | 149 ------------------------ board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 119 ------------------- board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h | 20 ---- configs/mv88f6281gtw_ge_defconfig | 7 -- include/configs/mv88f6281gtw_ge.h | 88 -------------- 9 files changed, 414 deletions(-) delete mode 100644 board/Marvell/mv88f6281gtw_ge/Kconfig delete mode 100644 board/Marvell/mv88f6281gtw_ge/MAINTAINERS delete mode 100644 board/Marvell/mv88f6281gtw_ge/Makefile delete mode 100644 board/Marvell/mv88f6281gtw_ge/kwbimage.cfg delete mode 100644 board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c delete mode 100644 board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h delete mode 100644 configs/mv88f6281gtw_ge_defconfig delete mode 100644 include/configs/mv88f6281gtw_ge.h (limited to 'include') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 1261885dad7..ed9ea8aec60 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -7,9 +7,6 @@ choice config TARGET_OPENRD bool "Marvell OpenRD Board" -config TARGET_MV88F6281GTW_GE - bool "MV88f6281GTW_GE Board" - config TARGET_RD6281A bool "RD6281A Board" @@ -67,7 +64,6 @@ config SYS_SOC default "kirkwood" source "board/Marvell/openrd/Kconfig" -source "board/Marvell/mv88f6281gtw_ge/Kconfig" source "board/Marvell/rd6281a/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" diff --git a/board/Marvell/mv88f6281gtw_ge/Kconfig b/board/Marvell/mv88f6281gtw_ge/Kconfig deleted file mode 100644 index 00d7d1c5ee4..00000000000 --- a/board/Marvell/mv88f6281gtw_ge/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MV88F6281GTW_GE - -config SYS_BOARD - default "mv88f6281gtw_ge" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "mv88f6281gtw_ge" - -endif diff --git a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS deleted file mode 100644 index 9c26ca7658b..00000000000 --- a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MV88F6281GTW_GE BOARD -M: Prafulla Wadaskar -S: Maintained -F: board/Marvell/mv88f6281gtw_ge/ -F: include/configs/mv88f6281gtw_ge.h -F: configs/mv88f6281gtw_ge_defconfig diff --git a/board/Marvell/mv88f6281gtw_ge/Makefile b/board/Marvell/mv88f6281gtw_ge/Makefile deleted file mode 100644 index e83bbf76e28..00000000000 --- a/board/Marvell/mv88f6281gtw_ge/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mv88f6281gtw_ge.o diff --git a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg deleted file mode 100644 index 9fa87acde0e..00000000000 --- a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg +++ /dev/null @@ -1,149 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000a00 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x38543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x0000002A # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000000D # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000046 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd enabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 1 , D2P Latency enabled -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E811 # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit11-10:1, DQ_ODTSel. ODT select turned on - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c deleted file mode 100644 index ef08ad8928d..00000000000 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Maintainer : Prafulla Wadaskar - * - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "mv88f6281gtw_ge.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, - MV88F6281GTW_GE_OE_VAL_HIGH, - MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_GPIO, - MPP5_GPO, - MPP6_SYSRST_OUTn, - MPP7_SPI_SCn, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, - MPP13_GPIO, - MPP14_GPIO, - MPP15_GPIO, - MPP16_GPIO, - MPP17_GPIO, - MPP18_GPO, - MPP19_GPO, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_MV88E61XX_SWITCH -void reset_phy(void) -{ - /* configure and initialize switch */ - struct mv88e61xx_config swcfg = { - .name = "egiga0", - .vlancfg = MV88E61XX_VLANCFG_ROUTER, - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, - .led_init = MV88E61XX_LED_INIT_EN, - .mdip = MV88E61XX_MDIP_REVERSE, - .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = (1 << 5), - .ports_enabled = 0x3f - }; - - mv88e61xx_switch_initialize(&swcfg); -} -#endif /* CONFIG_MV88E61XX_SWITCH */ diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h deleted file mode 100644 index 447e227c58e..00000000000 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MV88F6281GTW_GE_H -#define __MV88F6281GTW_GE_H - -#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \ - |(1 << 20) | (1 << 21))) /*enable GLED,RLED */ -#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \ - |(1 << 13)|(1 << 16)|(1 << 17))) -#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */ -#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17)) - - -#endif /* __MV88F6281GTW_GE_H */ diff --git a/configs/mv88f6281gtw_ge_defconfig b/configs/mv88f6281gtw_ge_defconfig deleted file mode 100644 index 8988734ef39..00000000000 --- a/configs/mv88f6281gtw_ge_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_MV88F6281GTW_GE=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h deleted file mode 100644 index 45a4a7541cd..00000000000 --- a/include/configs/mv88f6281gtw_ge.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_MV88F6281GTW_GE_H -#define _CONFIG_MV88F6281GTW_GE_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_SF -#define CONFIG_CMD_USB - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Unwanted stuffs from mv-common.h */ -#undef CONFIG_CMD_EXT2 -#undef CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_UBI -#undef CONFIG_CMD_UBIFS -#undef CONFIG_RBTREE - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -#define CONFIG_ENV_SIZE 0x1000 /* 4k */ -#define CONFIG_ENV_ADDR 0x30000 -#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \ - "512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ - "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */ -#endif /* CONFIG_CMD_NET */ - -#endif /* _CONFIG_MV88F6281GTW_GE_H */ -- cgit v1.3.1 From b6073fd2115ec3418cead26ce8acaf5cfb0e2f98 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:13 -0600 Subject: arm: Remove mx51_efikamx, mx51_efikasb boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/genesi/mx51_efikamx/Kconfig | 15 - board/genesi/mx51_efikamx/MAINTAINERS | 7 - board/genesi/mx51_efikamx/Makefile | 13 - board/genesi/mx51_efikamx/efikamx-usb.c | 230 -------------- board/genesi/mx51_efikamx/efikamx.c | 509 ------------------------------ board/genesi/mx51_efikamx/imximage_mx.cfg | 118 ------- board/genesi/mx51_efikamx/imximage_sb.cfg | 101 ------ configs/mx51_efikamx_defconfig | 7 - configs/mx51_efikasb_defconfig | 6 - include/configs/mx51_efikamx.h | 242 -------------- 11 files changed, 1253 deletions(-) delete mode 100644 board/genesi/mx51_efikamx/Kconfig delete mode 100644 board/genesi/mx51_efikamx/MAINTAINERS delete mode 100644 board/genesi/mx51_efikamx/Makefile delete mode 100644 board/genesi/mx51_efikamx/efikamx-usb.c delete mode 100644 board/genesi/mx51_efikamx/efikamx.c delete mode 100644 board/genesi/mx51_efikamx/imximage_mx.cfg delete mode 100644 board/genesi/mx51_efikamx/imximage_sb.cfg delete mode 100644 configs/mx51_efikamx_defconfig delete mode 100644 configs/mx51_efikasb_defconfig delete mode 100644 include/configs/mx51_efikamx.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6365e8f9004..4d85e36a678 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -493,10 +493,6 @@ config TARGET_MX53SMD bool "Support mx53smd" select CPU_V7 -config TARGET_MX51_EFIKAMX - bool "Support mx51_efikamx" - select CPU_V7 - config TARGET_VISION2 bool "Support vision2" select CPU_V7 @@ -801,7 +797,6 @@ source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" source "board/freescale/mx53smd/Kconfig" source "board/freescale/vf610twr/Kconfig" -source "board/genesi/mx51_efikamx/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hale/tt01/Kconfig" diff --git a/board/genesi/mx51_efikamx/Kconfig b/board/genesi/mx51_efikamx/Kconfig deleted file mode 100644 index 355702a4b6d..00000000000 --- a/board/genesi/mx51_efikamx/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX51_EFIKAMX - -config SYS_BOARD - default "mx51_efikamx" - -config SYS_VENDOR - default "genesi" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx51_efikamx" - -endif diff --git a/board/genesi/mx51_efikamx/MAINTAINERS b/board/genesi/mx51_efikamx/MAINTAINERS deleted file mode 100644 index f1398c49269..00000000000 --- a/board/genesi/mx51_efikamx/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX51_EFIKAMX BOARD -#M: - -S: Maintained -F: board/genesi/mx51_efikamx/ -F: include/configs/mx51_efikamx.h -F: configs/mx51_efikamx_defconfig -F: configs/mx51_efikasb_defconfig diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile deleted file mode 100644 index 87f5f9ede18..00000000000 --- a/board/genesi/mx51_efikamx/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (C) 2010, Marek Vasut -# -# BASED ON: imx51evk -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2009 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := efikamx.o efikamx-usb.o diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c deleted file mode 100644 index 9dfd24961af..00000000000 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (C) 2010 Marek Vasut - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../../../drivers/usb/host/ehci.h" - -/* - * Configure the USB H1 and USB H2 IOMUX - */ -void setup_iomux_usb(void) -{ - static const iomux_v3_cfg_t usb_h1_pads[] = { - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - }; - - static const iomux_v3_cfg_t usb_pads[] = { - MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */ - MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */ - NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */ - NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */ - NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */ - }; - - imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads)); - - if (machine_is_efikasb()) { - static const iomux_v3_cfg_t usb_h2_pads[] = { - MX51_PAD_EIM_A24__USBH2_CLK, - MX51_PAD_EIM_A25__USBH2_DIR, - MX51_PAD_EIM_A26__USBH2_STP, - MX51_PAD_EIM_A27__USBH2_NXT, - MX51_PAD_EIM_D16__USBH2_DATA0, - MX51_PAD_EIM_D17__USBH2_DATA1, - MX51_PAD_EIM_D18__USBH2_DATA2, - MX51_PAD_EIM_D19__USBH2_DATA3, - MX51_PAD_EIM_D20__USBH2_DATA4, - MX51_PAD_EIM_D21__USBH2_DATA5, - MX51_PAD_EIM_D22__USBH2_DATA6, - MX51_PAD_EIM_D23__USBH2_DATA7, - }; - - imx_iomux_v3_setup_multiple_pads(usb_h2_pads, - ARRAY_SIZE(usb_h2_pads)); - } - - imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); -} - -/* - * Enable devices connected to USB BUSes - */ -static void efika_usb_enable_devices(void) -{ - /* Enable Bluetooth */ - gpio_direction_output(IMX_GPIO_NR(2, 11), 0); - udelay(10000); - gpio_set_value(IMX_GPIO_NR(2, 11), 1); - - /* Enable WiFi */ - gpio_direction_output(IMX_GPIO_NR(2, 16), 1); - udelay(10000); - - /* Reset the WiFi chip */ - gpio_direction_output(IMX_GPIO_NR(2, 10), 0); - udelay(10000); - gpio_set_value(IMX_GPIO_NR(2, 10), 1); -} - -/* - * Reset USB HUB (or HUBs on EfikaSB) - */ -static void efika_usb_hub_reset(void) -{ - /* HUB reset */ - gpio_direction_output(IMX_GPIO_NR(1, 5), 1); - udelay(1000); - gpio_set_value(IMX_GPIO_NR(1, 5), 0); - udelay(1000); - gpio_set_value(IMX_GPIO_NR(1, 5), 1); -} - -/* - * Reset USB PHY (or PHYs on EfikaSB) - */ -static void efika_usb_phy_reset(void) -{ - /* SMSC 3317 PHY reset */ - gpio_direction_output(IMX_GPIO_NR(2, 9), 0); - udelay(1000); - gpio_set_value(IMX_GPIO_NR(2, 9), 1); -} - -static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, - iomux_v3_cfg_t stp_pad_gpio, - iomux_v3_cfg_t stp_pad_usb) -{ - int ret; - struct ulpi_regs *ulpi = (struct ulpi_regs *)0; - struct ulpi_viewport ulpi_vp; - - imx_iomux_v3_setup_pad(stp_pad_gpio); - gpio_direction_output(stp_gpio, 0); - udelay(1000); - gpio_set_value(stp_gpio, 1); - udelay(1000); - - imx_iomux_v3_setup_pad(stp_pad_usb); - udelay(10000); - - ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; - ulpi_vp.port_num = 0; - - ret = ulpi_init(&ulpi_vp); - if (ret) { - printf("Efika USB ULPI initialization failed\n"); - return; - } - - /* ULPI set flags */ - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, - ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | - ULPI_OTG_EXTVBUSIND); - ulpi_write(&ulpi_vp, &ulpi->function_ctrl, - ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | - ULPI_FC_SUSPENDM); - ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); - - /* Set VBus */ - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - /* - * Set VBusChrg - * - * NOTE: This violates USB specification, but otherwise, USB on Efika - * doesn't work. - */ - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); -} - -int board_ehci_hcd_init(int port) -{ - /* Init iMX51 EHCI */ - efika_usb_phy_reset(); - efika_usb_hub_reset(); - efika_usb_enable_devices(); - - return 0; -} - -/* This overrides a weak function */ -void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, - uint32_t *reg) -{ - uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT); - struct usb_ehci *ehci = (struct usb_ehci *)port; - struct ulpi_regs *ulpi = (struct ulpi_regs *)0; - struct ulpi_viewport ulpi_vp; - - ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; - ulpi_vp.port_num = 0; - - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); - - mdelay(50); - - /* terminate the reset */ - *reg = ehci_readl(status_reg); - *reg |= EHCI_PS_PE; -} - -void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) -{ - uint32_t tmp; - - if (port == 0) { - /* Adjust UTMI PHY frequency to 24MHz */ - tmp = readl(OTG_BASE_ADDR + 0x80c); - tmp = (tmp & ~0x3) | 0x01; - writel(tmp, OTG_BASE_ADDR + 0x80c); - } else if (port == 1) { - efika_ehci_init(ehci, IMX_GPIO_NR(1, 27), - MX51_PAD_USBH1_STP__GPIO1_27, - MX51_PAD_USBH1_STP__USBH1_STP); - } else if ((port == 2) && machine_is_efikasb()) { - efika_ehci_init(ehci, IMX_GPIO_NR(2, 20), - MX51_PAD_EIM_A26__GPIO2_20, - MX51_PAD_EIM_A26__USBH2_STP); - } - - if (port) - mdelay(10); -} - -/* - * Ethernet on the Smarttop is on the USB bus. Rather than give an error about - * "CPU Net Initialization Failed", just pass this test since no other settings - * are required. Smartbook doesn't have built-in Ethernet but we will let it - * pass anyway considering someone may have plugged in a USB stick and all - * they need to do is run "usb start". - */ -int board_eth_init(bd_t *bis) -{ - return 0; -} diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c deleted file mode 100644 index 6ba55cd08a8..00000000000 --- a/board/genesi/mx51_efikamx/efikamx.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Marek Vasut - * Copyright (C) 2009-2012 Genesi USA, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Compile-time error checking - */ -#ifndef CONFIG_MXC_SPI -#error "CONFIG_MXC_SPI not set, this is essential for board's operation!" -#endif - -/* - * Board revisions - * - * Note that we get these revisions here for convenience, but we only set - * up for the production model Smarttop (1.3) and Smartbook (2.0). - * - */ -#define EFIKAMX_BOARD_REV_11 0x1 -#define EFIKAMX_BOARD_REV_12 0x2 -#define EFIKAMX_BOARD_REV_13 0x3 -#define EFIKAMX_BOARD_REV_14 0x4 - -#define EFIKASB_BOARD_REV_13 0x1 -#define EFIKASB_BOARD_REV_20 0x2 - -/* - * Board identification - */ -static u32 get_mx_rev(void) -{ - u32 rev = 0; - /* - * Retrieve board ID: - * - * gpio: 16 17 11 - * ============== - * r1.1: 1+ 1 1 - * r1.2: 1 1 0 - * r1.3: 1 0 1 - * r1.4: 1 0 0 - * - * + note: r1.1 does not strap this pin properly so it needs to - * be hacked or ignored. - */ - - /* set to 1 in order to get correct value on board rev 1.1 */ - gpio_direction_output(IMX_GPIO_NR(3, 16), 1); - gpio_direction_input(IMX_GPIO_NR(3, 11)); - gpio_direction_input(IMX_GPIO_NR(3, 16)); - gpio_direction_input(IMX_GPIO_NR(3, 17)); - - rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0; - rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1; - rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2; - - return (~rev & 0x7) + 1; -} - -static iomux_v3_cfg_t const efikasb_revision_pads[] = { - MX51_PAD_EIM_CS3__GPIO2_28, - MX51_PAD_EIM_CS4__GPIO2_29, -}; - -static inline u32 get_sb_rev(void) -{ - u32 rev = 0; - - imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, - ARRAY_SIZE(efikasb_revision_pads)); - gpio_direction_input(IMX_GPIO_NR(2, 28)); - gpio_direction_input(IMX_GPIO_NR(2, 29)); - - rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0; - rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1; - - return rev; -} - -inline uint32_t get_efikamx_rev(void) -{ - if (machine_is_efikamx()) - return get_mx_rev(); - else if (machine_is_efikasb()) - return get_sb_rev(); -} - -u32 get_board_rev(void) -{ - return get_cpu_rev() | (get_efikamx_rev() << 8); -} - -/* - * DRAM initialization - */ -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -/* - * UART configuration - */ -static iomux_v3_cfg_t const efikamx_uart_pads[] = { - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, -}; - -/* - * SPI configuration - */ -static iomux_v3_cfg_t const efikamx_spi_pads[] = { - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - MX51_PAD_GPIO1_6__GPIO1_6, -}; - -#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24) -#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25) -#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6) - -/* - * PMIC configuration - */ -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 1) ? 121 : -1; -} - -static void power_init(void) -{ - unsigned int val; - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; - struct pmic *p; - int ret; - - ret = pmic_init(CONFIG_FSL_PMIC_BUS); - if (ret) - return; - - p = pmic_get("FSL_PMIC"); - if (!p) - return; - - /* Write needed to Power Gate 2 register */ - pmic_reg_read(p, REG_POWER_MISC, &val); - val &= ~PWGT2SPIEN; - pmic_reg_write(p, REG_POWER_MISC, val); - - /* Externally powered */ - pmic_reg_read(p, REG_CHARGE, &val); - val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; - pmic_reg_write(p, REG_CHARGE, val); - - /* power up the system first */ - pmic_reg_write(p, REG_POWER_MISC, PWUP); - - /* Set core voltage to 1.1V */ - pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; - pmic_reg_write(p, REG_SW_0, val); - - /* Setup VCC (SW2) to 1.25 */ - pmic_reg_read(p, REG_SW_1, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.25 */ - pmic_reg_read(p, REG_SW_2, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_2, val); - udelay(50); - - /* Raise the core frequency to 800MHz */ - writel(0x0, &mxc_ccm->cacrr); - - /* Set switchers in Auto in NORMAL mode & STANDBY mode */ - /* Setup the switcher mode for SW1 & SW2*/ - pmic_reg_read(p, REG_SW_4, &val); - val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | - (SWMODE_MASK << SWMODE2_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(p, REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - pmic_reg_read(p, REG_SW_5, &val); - val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | - (SWMODE_MASK << SWMODE4_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); - pmic_reg_write(p, REG_SW_5, val); - - /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ - pmic_reg_read(p, REG_SETTING_0, &val); - val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; - pmic_reg_write(p, REG_SETTING_0, val); - - /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - pmic_reg_read(p, REG_SETTING_1, &val); - val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; - pmic_reg_write(p, REG_SETTING_1, val); - - /* Enable VGEN1, VGEN2, VDIG, VPLL */ - pmic_reg_read(p, REG_MODE_0, &val); - val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; - pmic_reg_write(p, REG_MODE_0, val); - - /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(p, REG_MODE_1, val); - udelay(200); - - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(p, REG_MODE_1, val); - - pmic_reg_read(p, REG_POWER_CTL2, &val); - val |= WDIRESET; - pmic_reg_write(p, REG_POWER_CTL2, val); - - udelay(2500); -} -#else -static inline void power_init(void) { } -#endif - -/* - * MMC configuration - */ -#ifdef CONFIG_FSL_ESDHC - -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC2_BASE_ADDR}, -}; - -static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = { - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - MX51_PAD_GPIO1_1__SD1_WP, -}; - -#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1) - -static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = { - MX51_PAD_GPIO1_0__SD1_CD, - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL), -}; - -#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0) -#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27) - -static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = { - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - MX51_PAD_GPIO1_7__SD2_WP, - MX51_PAD_GPIO1_8__SD2_CD, -}; - -#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8) -#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7) - -static inline uint32_t efikamx_mmc_getcd(u32 base) -{ - if (base == MMC_SDHC1_BASE_ADDR) - if (machine_is_efikamx()) - return EFIKAMX_SDHC1_CD; - else - return EFIKASB_SDHC1_CD; - else - return EFIKASB_SDHC2_CD; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base); - int ret = !gpio_get_value(cd); - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - - /* - * All Efika MX boards use eSDHC1 with a common write-protect GPIO - */ - imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, - ARRAY_SIZE(efikamx_sdhc1_pads)); - gpio_direction_input(EFIKAMX_SDHC1_WP); - - /* - * Smartbook and Smarttop differ on the location of eSDHC1 - * carrier-detect GPIO - */ - if (machine_is_efikamx()) { - imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]); - gpio_direction_input(EFIKAMX_SDHC1_CD); - } else if (machine_is_efikasb()) { - imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]); - gpio_direction_input(EFIKASB_SDHC1_CD); - } - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - - if (machine_is_efikasb()) { - - imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, - ARRAY_SIZE(efikasb_sdhc2_pads)); - gpio_direction_input(EFIKASB_SDHC2_CD); - gpio_direction_input(EFIKASB_SDHC2_WP); - if (!ret) - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); - } - - return ret; -} -#endif - -/* - * PATA - */ -static iomux_v3_cfg_t const efikamx_pata_pads[] = { - MX51_PAD_NANDF_WE_B__PATA_DIOW, - MX51_PAD_NANDF_RE_B__PATA_DIOR, - MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, - MX51_PAD_NANDF_CLE__PATA_RESET_B, - MX51_PAD_NANDF_WP_B__PATA_DMACK, - MX51_PAD_NANDF_RB0__PATA_DMARQ, - MX51_PAD_NANDF_RB1__PATA_IORDY, - MX51_PAD_GPIO_NAND__PATA_INTRQ, - MX51_PAD_NANDF_CS2__PATA_CS_0, - MX51_PAD_NANDF_CS3__PATA_CS_1, - MX51_PAD_NANDF_CS4__PATA_DA_0, - MX51_PAD_NANDF_CS5__PATA_DA_1, - MX51_PAD_NANDF_CS6__PATA_DA_2, - MX51_PAD_NANDF_D15__PATA_DATA15, - MX51_PAD_NANDF_D14__PATA_DATA14, - MX51_PAD_NANDF_D13__PATA_DATA13, - MX51_PAD_NANDF_D12__PATA_DATA12, - MX51_PAD_NANDF_D11__PATA_DATA11, - MX51_PAD_NANDF_D10__PATA_DATA10, - MX51_PAD_NANDF_D9__PATA_DATA9, - MX51_PAD_NANDF_D8__PATA_DATA8, - MX51_PAD_NANDF_D7__PATA_DATA7, - MX51_PAD_NANDF_D6__PATA_DATA6, - MX51_PAD_NANDF_D5__PATA_DATA5, - MX51_PAD_NANDF_D4__PATA_DATA4, - MX51_PAD_NANDF_D3__PATA_DATA3, - MX51_PAD_NANDF_D2__PATA_DATA2, - MX51_PAD_NANDF_D1__PATA_DATA1, - MX51_PAD_NANDF_D0__PATA_DATA0, -}; - -/* - * EHCI USB - */ -#ifdef CONFIG_CMD_USB -extern void setup_iomux_usb(void); -#else -static inline void setup_iomux_usb(void) { } -#endif - -/* - * LED configuration - * - * Smarttop LED pad config is done in the DCD - * - */ -#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13) -#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14) -#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15) - -static iomux_v3_cfg_t const efikasb_led_pads[] = { - MX51_PAD_GPIO1_3__GPIO1_3, - MX51_PAD_EIM_CS0__GPIO2_25, -}; - -#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25) -#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */ - -/* - * Board initialization - */ -int board_early_init_f(void) -{ - if (machine_is_efikasb()) { - imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, - ARRAY_SIZE(efikasb_led_pads)); - gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0); - gpio_direction_output(EFIKASB_MESSAGE_LED, 1); - } else if (machine_is_efikamx()) { - /* - * Set up GPIO directions for LEDs. - * IOMUX has been done in the DCD already. - * Turn the red LED on for pre-relocation code. - */ - gpio_direction_output(EFIKAMX_LED_BLUE, 0); - gpio_direction_output(EFIKAMX_LED_GREEN, 0); - gpio_direction_output(EFIKAMX_LED_RED, 1); - } - - /* - * Both these pad configurations for UART and SPI are kind of redundant - * since they are the Power-On Defaults for the i.MX51. But, it seems we - * should make absolutely sure that they are set up correctly. - */ - imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, - ARRAY_SIZE(efikamx_uart_pads)); - imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, - ARRAY_SIZE(efikamx_spi_pads)); - - /* not technically required for U-Boot operation but do it anyway. */ - gpio_direction_input(EFIKAMX_PMIC_IRQ); - /* Deselect both CS for now, otherwise NOR doesn't probe properly. */ - gpio_direction_output(EFIKAMX_SPI_SS0, 0); - gpio_direction_output(EFIKAMX_SPI_SS1, 1); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_late_init(void) -{ - if (machine_is_efikamx()) { - /* - * Set up Blue LED for "In U-Boot" status. - * We're all relocated and ready to U-Boot! - */ - gpio_set_value(EFIKAMX_LED_RED, 0); - gpio_set_value(EFIKAMX_LED_GREEN, 0); - gpio_set_value(EFIKAMX_LED_BLUE, 1); - } - - power_init(); - - imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, - ARRAY_SIZE(efikamx_pata_pads)); - setup_iomux_usb(); - - return 0; -} - -int checkboard(void) -{ - u32 rev = get_efikamx_rev(); - - printf("Board: Genesi Efika MX "); - if (machine_is_efikamx()) - printf("Smarttop (1.%i)\n", rev & 0xf); - else if (machine_is_efikasb()) - printf("Smartbook\n"); - - return 0; -} diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg deleted file mode 100644 index e2911eb401a..00000000000 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2009 Pegatron Corporation - * Copyright (C) 2010 Marek Vasut - * Copyright (C) 2009-2012 Genesi USA, Inc. - * - * BASED ON: imx51evk - * - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM spi - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -/* - * Essential GPIO settings to be done as early as possible - * PCBIDn pad settings are all the defaults except #2 which needs HVE off - */ -DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 -DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 -DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 -DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE -DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 -DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 -DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15 - -/* DDR bus IOMUX PAD settings */ -DATA 4 0x73fa850c 0x20c5 # SDODT1 -DATA 4 0x73fa8510 0x20c5 # SDODT0 -DATA 4 0x73fa84ac 0xc5 # SDWE -DATA 4 0x73fa84b0 0xc5 # SDCKE0 -DATA 4 0x73fa84b4 0xc5 # SDCKE1 -DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 -DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 -DATA 4 0x73fa882c 0x2 # DRAM_B4 -DATA 4 0x73fa88a4 0x2 # DRAM_B0 -DATA 4 0x73fa88ac 0x2 # DRAM_B1 -DATA 4 0x73fa88b8 0x2 # DRAM_B2 -DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 -DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 -DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 -DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3 - -/* - * Setting DDR for micron - * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model - * CAS=3 BL=4 - */ -/* ESDCTL_ESDCTL0 */ -DATA 4 0x83fd9000 0x82a20000 -/* ESDCTL_ESDCTL1 */ -DATA 4 0x83fd9008 0x82a20000 -/* ESDCTL_ESDMISC */ -DATA 4 0x83fd9010 0xcaaaf6d0 -/* ESDCTL_ESDCFG0 */ -DATA 4 0x83fd9004 0x3f3574aa -/* ESDCTL_ESDCFG1 */ -DATA 4 0x83fd900c 0x3f3574aa - -/* Init DRAM on CS0 */ -/* ESDCTL_ESDSCR */ -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x0000801a -DATA 4 0x83fd9014 0x0000801b -DATA 4 0x83fd9014 0x00448019 -DATA 4 0x83fd9014 0x07328018 -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x06328018 -DATA 4 0x83fd9014 0x03808019 -DATA 4 0x83fd9014 0x00408019 -DATA 4 0x83fd9014 0x00008000 - -/* Init DRAM on CS1 */ -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x0000801e -DATA 4 0x83fd9014 0x0000801f -DATA 4 0x83fd9014 0x0000801d -DATA 4 0x83fd9014 0x0732801c -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x0632801c -DATA 4 0x83fd9014 0x0380801d -DATA 4 0x83fd9014 0x0040801d -DATA 4 0x83fd9014 0x00008004 - -/* Write to CTL0 */ -DATA 4 0x83fd9000 0xb2a20000 -/* Write to CTL1 */ -DATA 4 0x83fd9008 0xb2a20000 -/* ESDMISC */ -DATA 4 0x83fd9010 0x000ad6d0 -/* ESDCTL_ESDCDLYGD */ -DATA 4 0x83fd9034 0x90000000 -DATA 4 0x83fd9014 0x00000000 diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg deleted file mode 100644 index a67d41b42e9..00000000000 --- a/board/genesi/mx51_efikamx/imximage_sb.cfg +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2009 Pegatron Corporation - * Copyright (C) 2010 Marek Vasut - * Copyright (C) 2009-2012 Genesi USA, Inc. - * - * BASED ON: imx51evk - * - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM spi - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register -*/ -/* DDR bus IOMUX PAD settings */ -DATA 4 0x73fa88a0 0x200 # GRP_INMODE1 -DATA 4 0x73fa850c 0x20c5 # SDODT1 -DATA 4 0x73fa8510 0x20c5 # SDODT0 -DATA 4 0x73fa8848 0x4 # DDR_A1 -DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK -DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0 -DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1 -DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2 -DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3 -DATA 4 0x73fa8820 0x0 # DDRPKS -DATA 4 0x73fa84ac 0xe5 # SDWE -DATA 4 0x73fa84b0 0xe5 # SDCKE0 -DATA 4 0x73fa84b4 0xe5 # SDCKE1 -DATA 4 0x73fa84cc 0xe5 # DRAM_CS0 -DATA 4 0x73fa84d0 0xe4 # DRAM_CS1 - -/* - * Setting DDR for micron - * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model - * CAS=3 BL=4 - */ -/* ESDCTL_ESDCTL0 */ -DATA 4 0x83fd9000 0x82a20000 -/* ESDCTL_ESDCTL1 */ -DATA 4 0x83fd9008 0x82a20000 -/* ESDCTL_ESDMISC */ -DATA 4 0x83fd9010 0xcaaaf6d0 -/* ESDCTL_ESDCFG0 */ -DATA 4 0x83fd9004 0x333574aa -/* ESDCTL_ESDCFG1 */ -DATA 4 0x83fd900c 0x333574aa - -/* Init DRAM on CS0 */ -/* ESDCTL_ESDSCR */ -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x0000801a -DATA 4 0x83fd9014 0x0000801b -DATA 4 0x83fd9014 0x00448019 -DATA 4 0x83fd9014 0x07328018 -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x06328018 -DATA 4 0x83fd9014 0x03808019 -DATA 4 0x83fd9014 0x00408019 -DATA 4 0x83fd9014 0x00008000 - -/* Init DRAM on CS1 */ -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x0000801e -DATA 4 0x83fd9014 0x0000801f -DATA 4 0x83fd9014 0x0000801d -DATA 4 0x83fd9014 0x0732801c -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x0632801c -DATA 4 0x83fd9014 0x0380801d -DATA 4 0x83fd9014 0x0042801d -DATA 4 0x83fd9014 0x00008004 - -/* Write to CTL0 */ -DATA 4 0x83fd9000 0xb2a20000 -/* Write to CTL1 */ -DATA 4 0x83fd9008 0xb2a20000 -/* ESDMISC */ -DATA 4 0x83fd9010 0xcaaaf6d0 -/* ESDCTL_ESDCDLYGD */ -DATA 4 0x83fd9034 0x90000000 -DATA 4 0x83fd9014 0x00000000 diff --git a/configs/mx51_efikamx_defconfig b/configs/mx51_efikamx_defconfig deleted file mode 100644 index a88c2230646..00000000000 --- a/configs/mx51_efikamx_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX51_EFIKAMX=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y -CONFIG_SYS_PROMPT="Efika> " diff --git a/configs/mx51_efikasb_defconfig b/configs/mx51_efikasb_defconfig deleted file mode 100644 index 1bc7c00cb8c..00000000000 --- a/configs/mx51_efikasb_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX51_EFIKAMX=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h deleted file mode 100644 index 373cfcbc792..00000000000 --- a/include/configs/mx51_efikamx.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX51EVK Board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -/* An i.MX51 CPU */ -#define CONFIG_MX51 - -#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) -#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) - -#include - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0x97800000 - -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE - -/* - * Environmental settings - */ - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) -#define CONFIG_ENV_SIZE (4 * 1024) - -/* - * ATAG setup - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -/* - * Hardware drivers - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_MXC_GPIO - -/* - * SPI Interface - */ -#ifdef CONFIG_CMD_SPI - -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* SPI FLASH */ -#ifdef CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SF_DEFAULT_CS 1 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_SPI_MODE (SPI_MODE_0) -#define CONFIG_FSL_ENV_IN_SF -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SYS_NO_FLASH - -#else -#define CONFIG_ENV_IS_NOWHERE -#endif - -/* SPI PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS (0 | 120 << 8) -#define CONFIG_FSL_PMIC_CLK 25000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX -#endif - -/* - * MMC Configs - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 -#endif - -/* - * ATA/IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define CONFIG_MX51_PATA - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0 -#define CONFIG_SYS_ATA_REG_OFFSET 0xa0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8 - -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_IDE_PREINIT -#define CONFIG_MXC_ATA_PIO_MODE 4 -#endif - -/* - * USB - */ -#define CONFIG_CMD_USB -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_MX5 -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_MXC_USB_PORT 1 -#if (CONFIG_MXC_USB_PORT == 0) -#define CONFIG_MXC_USB_PORTSC (1 << 28) -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY -#else -#define CONFIG_MXC_USB_PORTSC (2 << 30) -#define CONFIG_MXC_USB_FLAGS 0 -#endif -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP -#define CONFIG_PREBOOT -/* USB NET */ -#ifdef CONFIG_CMD_NET -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#endif -#endif /* CONFIG_CMD_USB */ - -/* - * Filesystems - */ -#ifdef CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x90800000 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x90010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 -#define CONFIG_SYS_MAIN_PWR_ON - -#endif -- cgit v1.3.1 From 0abdd9d01ac6ca58d8c5765bdaf4283949fdcd76 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:14 -0600 Subject: arm: Remove nhk8815 boards and nomadik arch These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 6 - arch/arm/mach-nomadik/Kconfig | 17 --- arch/arm/mach-nomadik/Makefile | 9 -- arch/arm/mach-nomadik/gpio.c | 83 ------------ arch/arm/mach-nomadik/include/mach/gpio.h | 26 ---- arch/arm/mach-nomadik/include/mach/mtu.h | 50 -------- arch/arm/mach-nomadik/reset.S | 14 -- arch/arm/mach-nomadik/timer.c | 71 ---------- board/st/nhk8815/Kconfig | 12 -- board/st/nhk8815/MAINTAINERS | 8 -- board/st/nhk8815/Makefile | 12 -- board/st/nhk8815/README.nhk8815 | 32 ----- board/st/nhk8815/nhk8815.c | 92 ------------- configs/nhk8815_defconfig | 7 - configs/nhk8815_onenand_defconfig | 7 - drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/nomadik.c | 206 ------------------------------ include/configs/nhk8815.h | 170 ------------------------ include/nomadik.h | 40 ------ 19 files changed, 863 deletions(-) delete mode 100644 arch/arm/mach-nomadik/Kconfig delete mode 100644 arch/arm/mach-nomadik/Makefile delete mode 100644 arch/arm/mach-nomadik/gpio.c delete mode 100644 arch/arm/mach-nomadik/include/mach/gpio.h delete mode 100644 arch/arm/mach-nomadik/include/mach/mtu.h delete mode 100644 arch/arm/mach-nomadik/reset.S delete mode 100644 arch/arm/mach-nomadik/timer.c delete mode 100644 board/st/nhk8815/Kconfig delete mode 100644 board/st/nhk8815/MAINTAINERS delete mode 100644 board/st/nhk8815/Makefile delete mode 100644 board/st/nhk8815/README.nhk8815 delete mode 100644 board/st/nhk8815/nhk8815.c delete mode 100644 configs/nhk8815_defconfig delete mode 100644 configs/nhk8815_onenand_defconfig delete mode 100644 drivers/mtd/nand/nomadik.c delete mode 100644 include/configs/nhk8815.h delete mode 100644 include/nomadik.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4d85e36a678..186e14fa2f5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -197,10 +197,6 @@ config TARGET_SC_SPS_1 select CPU_ARM926EJS select SUPPORT_SPL -config ARCH_NOMADIK - bool "ST-Ericsson Nomadik" - select CPU_ARM926EJS - config ORION5X bool "Marvell Orion" select CPU_ARM926EJS @@ -725,8 +721,6 @@ source "arch/arm/cpu/armv7/mx6/Kconfig" source "arch/arm/cpu/armv7/mx5/Kconfig" -source "arch/arm/mach-nomadik/Kconfig" - source "arch/arm/cpu/armv7/omap3/Kconfig" source "arch/arm/cpu/armv7/omap4/Kconfig" diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig deleted file mode 100644 index ba72a4105d9..00000000000 --- a/arch/arm/mach-nomadik/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if ARCH_NOMADIK - -choice - prompt "Nomadik board select" - optional - -config NOMADIK_NHK8815 - bool "ST 8815 Nomadik Hardware Kit" - -endchoice - -config SYS_SOC - default "nomadik" - -source "board/st/nhk8815/Kconfig" - -endif diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile deleted file mode 100644 index cdf1345d58f..00000000000 --- a/arch/arm/mach-nomadik/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = timer.o gpio.o -obj-y += reset.o diff --git a/arch/arm/mach-nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c deleted file mode 100644 index eff5b2b75e3..00000000000 --- a/arch/arm/mach-nomadik/gpio.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static unsigned long gpio_base[4] = { - NOMADIK_GPIO0_BASE, - NOMADIK_GPIO1_BASE, - NOMADIK_GPIO2_BASE, - NOMADIK_GPIO3_BASE -}; - -enum gpio_registers { - GPIO_DAT = 0x00, /* data register */ - GPIO_DATS = 0x04, /* data set */ - GPIO_DATC = 0x08, /* data clear */ - GPIO_PDIS = 0x0c, /* pull disable */ - GPIO_DIR = 0x10, /* direction */ - GPIO_DIRS = 0x14, /* direction set */ - GPIO_DIRC = 0x18, /* direction clear */ - GPIO_AFSLA = 0x20, /* alternate function select A */ - GPIO_AFSLB = 0x24, /* alternate function select B */ -}; - -static inline unsigned long gpio_to_base(int gpio) -{ - return gpio_base[gpio / 32]; -} - -static inline u32 gpio_to_bit(int gpio) -{ - return 1 << (gpio & 0x1f); -} - -void nmk_gpio_af(int gpio, int alternate_function) -{ - unsigned long base = gpio_to_base(gpio); - u32 bit = gpio_to_bit(gpio); - u32 afunc, bfunc; - - /* alternate function is 0..3, with one bit per register */ - afunc = readl(base + GPIO_AFSLA) & ~bit; - bfunc = readl(base + GPIO_AFSLB) & ~bit; - if (alternate_function & 1) afunc |= bit; - if (alternate_function & 2) bfunc |= bit; - writel(afunc, base + GPIO_AFSLA); - writel(bfunc, base + GPIO_AFSLB); -} - -void nmk_gpio_dir(int gpio, int dir) -{ - unsigned long base = gpio_to_base(gpio); - u32 bit = gpio_to_bit(gpio); - - if (dir) - writel(bit, base + GPIO_DIRS); - else - writel(bit, base + GPIO_DIRC); -} - -void nmk_gpio_set(int gpio, int val) -{ - unsigned long base = gpio_to_base(gpio); - u32 bit = gpio_to_bit(gpio); - - if (val) - writel(bit, base + GPIO_DATS); - else - writel(bit, base + GPIO_DATC); -} - -int nmk_gpio_get(int gpio) -{ - unsigned long base = gpio_to_base(gpio); - u32 bit = gpio_to_bit(gpio); - - return readl(base + GPIO_DAT) & bit; -} diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h deleted file mode 100644 index 311758ae1a4..00000000000 --- a/arch/arm/mach-nomadik/include/mach/gpio.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __NMK_GPIO_H__ -#define __NMK_GPIO_H__ - -/* - * These functions are called from the soft-i2c driver, but - * are also used by board files to set output bits. - */ - -enum nmk_af { /* alternate function settings */ - GPIO_GPIO = 0, - GPIO_ALT_A, - GPIO_ALT_B, - GPIO_ALT_C -}; - -extern void nmk_gpio_af(int gpio, int alternate_function); -extern void nmk_gpio_dir(int gpio, int dir); -extern void nmk_gpio_set(int gpio, int val); -extern int nmk_gpio_get(int gpio); - -#endif /* __NMK_GPIO_H__ */ diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h deleted file mode 100644 index f89f242247d..00000000000 --- a/arch/arm/mach-nomadik/include/mach/mtu.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MTU_H -#define __ASM_ARCH_MTU_H - -/* - * The MTU device hosts four different counters, with 4 set of - * registers. These are register names. - */ - -#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ -#define MTU_RIS 0x04 /* Raw interrupt status */ -#define MTU_MIS 0x08 /* Masked interrupt status */ -#define MTU_ICR 0x0C /* Interrupt clear register */ - -/* per-timer registers take 0..3 as argument */ -#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ -#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ -#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ -#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ - -/* bits for the control register */ -#define MTU_CRn_ENA 0x80 -#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CRn_PRESCALE_MASK 0x0c -#define MTU_CRn_PRESCALE_1 0x00 -#define MTU_CRn_PRESCALE_16 0x04 -#define MTU_CRn_PRESCALE_256 0x08 -#define MTU_CRn_32BITS 0x02 -#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ - -/* Other registers are usual amba/primecell registers, currently not used */ -#define MTU_ITCR 0xff0 -#define MTU_ITOP 0xff4 - -#define MTU_PERIPH_ID0 0xfe0 -#define MTU_PERIPH_ID1 0xfe4 -#define MTU_PERIPH_ID2 0xfe8 -#define MTU_PERIPH_ID3 0xfeC - -#define MTU_PCELL0 0xff0 -#define MTU_PCELL1 0xff4 -#define MTU_PCELL2 0xff8 -#define MTU_PCELL3 0xffC - -#endif /* __ASM_ARCH_MTU_H */ diff --git a/arch/arm/mach-nomadik/reset.S b/arch/arm/mach-nomadik/reset.S deleted file mode 100644 index ec954726aeb..00000000000 --- a/arch/arm/mach-nomadik/reset.S +++ /dev/null @@ -1,14 +0,0 @@ -#include -/* - * Processor reset for Nomadik - */ - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */ - ldr r1, =0x1 - str r1, [r0, #0x18] - -_loop_forever: - b _loop_forever diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c deleted file mode 100644 index 775d0b74884..00000000000 --- a/arch/arm/mach-nomadik/timer.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * The timer is a decrementer, we'll left it free running at 2.4MHz. - * We have 2.4 ticks per microsecond and an overflow in almost 30min - */ -#define TIMER_CLOCK (24 * 100 * 1000) -#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ -#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ -#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) -#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) - -/* macro to read the decrementing 32 bit timer as an increasing count */ -#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) - -/* Configure a free-running, auto-wrap counter with no prescaler */ -int timer_init(void) -{ - ulong val; - - writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, - CONFIG_SYS_TIMERBASE + MTU_CR(0)); - - /* Reset the timer */ - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); - /* - * The load-register isn't really immediate: it changes on clock - * edges, so we must wait for our newly-written value to appear. - * Since we might miss reading 0, wait for any change in value. - */ - val = READ_TIMER(); - while (READ_TIMER() == val) - ; - - return 0; -} - -/* Return how many HZ passed since "base" */ -ulong get_timer(ulong base) -{ - return TICKS_TO_HZ(READ_TIMER()) - base; -} - -/* Delay x useconds */ -void __udelay(unsigned long usec) -{ - ulong ini, end; - - ini = READ_TIMER(); - end = ini + USEC_TO_COUNT(usec); - while ((signed)(end - READ_TIMER()) > 0) - ; -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/board/st/nhk8815/Kconfig b/board/st/nhk8815/Kconfig deleted file mode 100644 index 94547dc118d..00000000000 --- a/board/st/nhk8815/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if NOMADIK_NHK8815 - -config SYS_BOARD - default "nhk8815" - -config SYS_VENDOR - default "st" - -config SYS_CONFIG_NAME - default "nhk8815" - -endif diff --git a/board/st/nhk8815/MAINTAINERS b/board/st/nhk8815/MAINTAINERS deleted file mode 100644 index 72c3a8d9039..00000000000 --- a/board/st/nhk8815/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -NHK8815 BOARD -M: Nomadik Linux Team -M: Alessandro Rubini -S: Maintained -F: board/st/nhk8815/ -F: include/configs/nhk8815.h -F: configs/nhk8815_defconfig -F: configs/nhk8815_onenand_defconfig diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile deleted file mode 100644 index dd56944db16..00000000000 --- a/board/st/nhk8815/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 -# ARM Ltd. -# Philippe Robin, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := nhk8815.o diff --git a/board/st/nhk8815/README.nhk8815 b/board/st/nhk8815/README.nhk8815 deleted file mode 100644 index 9008e393637..00000000000 --- a/board/st/nhk8815/README.nhk8815 +++ /dev/null @@ -1,32 +0,0 @@ - -The Nomadik 8815 CPU has a "secure" boot mode where no external access -(not even JTAG) is allowed. The "remap" bits in the evaluation board -are configured in order to boot from the internal ROM memory (in -secure mode). - -The boot process as defined by the manufacturer executes external code -(loaded from NAND or OneNAND) that that disables such "security" in -order to run u-boot and later the kernel without constraints. Such -code is a proprietary initial boot loader, called "X-Loader" (in case -anyone wonders, it has no relations with other loaders with the same -name and there is no GPL code inside the ST X-Loader). - -SDRAM configuration, PLL setup and initial loading from NAND is -implemented in the X-Loader, so U-Boot is already running in SDRAM -when control is handed over to it. - -The Makefile offers two different configurations to be used if you -boot from Nand or OneNand. - - make nhk8815_config - make nhk8815_onenand_config - -Both support OneNand and Nand. Since U-Boot, running in RAM, can't know -where it was loaded from, the configurations differ in where the filesystem -is looked for by default. - - -On www.st.com/nomadik and on www.stnwireless.com there are documents, -summary data and white papers on Nomadik. The full datasheet for -STn8815 is not currently available on line but under specific request -to the local ST sales offices. diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c deleted file mode 100644 index 94d0f76266e..00000000000 --- a/board/st/nhk8815/nhk8815.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2005 - * STMicrolelctronics, - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress(int progress) -{ - printf("%i\n", progress); -} -#endif - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_NOMADIK; - gd->bd->bi_boot_params = 0x00000100; - writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20); - writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24); - writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); - writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); - - /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ - writel(0x0000305b, REG_FSMC_BCR1); - writel(0x00033f33, REG_FSMC_BTR1); - - /* Set up SMCS0 for OneNand: sram-like once again */ - writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */ - writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */ - - icache_enable(); - return 0; -} - -int board_late_init(void) -{ - /* Set the two I2C gpio lines to be gpio high */ - nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1); - nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1); - nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO); - - /* Reset the I2C port expander, on GPIO77 */ - nmk_gpio_af(77, GPIO_GPIO); - nmk_gpio_dir(77, 1); - nmk_gpio_set(77, 0); - udelay(10); - nmk_gpio_set(77, 1); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/configs/nhk8815_defconfig b/configs/nhk8815_defconfig deleted file mode 100644 index 218d92a6ca5..00000000000 --- a/configs/nhk8815_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_NOMADIK=y -CONFIG_NOMADIK_NHK8815=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="Nomadik> " diff --git a/configs/nhk8815_onenand_defconfig b/configs/nhk8815_onenand_defconfig deleted file mode 100644 index c01559d8cdd..00000000000 --- a/configs/nhk8815_onenand_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_NOMADIK=y -CONFIG_NOMADIK_NHK8815=y -CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 71c1a519e97..b4e53761766 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -60,7 +60,6 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_NDFC) += ndfc.o -obj-$(CONFIG_NAND_NOMADIK) += nomadik.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c deleted file mode 100644 index a7cee5138db..00000000000 --- a/drivers/mtd/nand/nomadik.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * (C) Copyright 2007 STMicroelectronics, - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */ -{ - __asm__ __volatile__( - "eor %0, %0, %0, lsr #4\n\t" - "eor %0, %0, %0, lsr #2\n\t" - "eor %0, %0, %0, lsr #1\n\t" - "ands %0, %0, #1\n\t" - "subne %0, %0, #2\t" - : "=r" (b) : "0" (b)); - return b; -} - -/* - * This is the ECC routine used in hardware, according to the manual. - * HW claims to make the calculation but not the correction; so we must - * recalculate the bytes for a comparison. - */ -static int ecc512(const unsigned char *data, unsigned char *ecc) -{ - int gpar = 0; - int i, val, par; - int pbits = 0; /* P8, P16, ... P2048 */ - int pprime = 0; /* P8', P16', ... P2048' */ - int lowbits; /* P1, P2, P4 and primes */ - - for (i = 0; i < 512; i++) { - par = parity((val = data[i])); - gpar ^= val; - pbits ^= (i & par); - } - /* - * Ok, now gpar is global parity (xor of all bytes) - * pbits are all the parity bits (non-prime ones) - */ - par = parity(gpar); - pprime = pbits ^ par; - /* Put low bits in the right position for ecc[2] (bits 7..2) */ - lowbits = 0 - | (parity(gpar & 0xf0) & 0x80) /* P4 */ - | (parity(gpar & 0x0f) & 0x40) /* P4' */ - | (parity(gpar & 0xcc) & 0x20) /* P2 */ - | (parity(gpar & 0x33) & 0x10) /* P2' */ - | (parity(gpar & 0xaa) & 0x08) /* P1 */ - | (parity(gpar & 0x55) & 0x04); /* P1' */ - - ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8)); - /* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */ - ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1) - | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2) - | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3) - | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4)); - - ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3) - | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2) - | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1) - | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0)); - return 0; -} - -/* This is the method in the chip->ecc field */ -static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) -{ - return ecc512(dat, ecc_code); -} - -static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat, - uint8_t *r_ecc, uint8_t *c_ecc) -{ - struct nand_chip *chip = mtd->priv; - uint32_t r, c, d, diff; /*read, calculated, xor of them */ - - if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes)) - return 0; - - /* Reorder the bytes into ascending-order 24 bits -- see manual */ - r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2; - c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2; - diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */ - - /* If 12 bits are different, one per pair, it's correctable */ - if (((diff | (diff>>1)) & 0x555555) == 0x555555) { - int bit = ((diff & 2) >> 1) - | ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3); - int byte; - - d = diff >> 6; /* remove bit-order info */ - byte = ((d & 2) >> 1) - | ((d & 0x8) >> 2) | ((d & 0x20) >> 3) - | ((d & 0x80) >> 4) | ((d & 0x200) >> 5) - | ((d & 0x800) >> 6) | ((d & 0x2000) >> 7) - | ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9); - /* correct the single bit */ - dat[byte] ^= 1<priv; - u32 pcr0 = readl(REG_FSMC_PCR0); - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); - - if (ctrl & NAND_CLE) - IO_ADDR_W |= MASK_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= MASK_ALE; - - if (ctrl & NAND_NCE) - writel(pcr0 | 0x4, REG_FSMC_PCR0); - else - writel(pcr0 & ~0x4, REG_FSMC_PCR0); - - this->IO_ADDR_W = (void *) IO_ADDR_W; - this->IO_ADDR_R = (void *) IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */ -static int nomadik_nand_ready(struct mtd_info *mtd) -{ - return 1; /* The ready bit is handled in hardware */ -} - -/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */ -static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - u32 *p = (u32 *) buf; - - len >>= 2; - writel(0, REG_FSMC_ECCR0); - for (i = 0; i < len; i++) - p[i] = readl(chip->IO_ADDR_R); -} - -int board_nand_init(struct nand_chip *chip) -{ - /* Set up the FSMC_PCR0 for nand access*/ - writel(0x0000004a, REG_FSMC_PCR0); - /* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */ - writel(0x00020401, REG_FSMC_PMEM0); - writel(0x00020404, REG_FSMC_PATT0); - - chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; - chip->cmd_ctrl = nomadik_nand_hwcontrol; - chip->dev_ready = nomadik_nand_ready; - /* The chip allows 32bit reads, so avoid the default 8bit copy */ - chip->read_buf = nomadik_nand_read_buf; - - /* ECC: follow the hardware-defined rulse, but do it in sw */ - chip->ecc.mode = NAND_ECC_HW; - chip->ecc.bytes = 3; - chip->ecc.size = 512; - chip->ecc.strength = 1; - chip->ecc.layout = &nomadik_ecc_layout; - chip->ecc.calculate = nomadik_ecc_calculate; - chip->ecc.hwctl = nomadik_ecc_hwctl; - chip->ecc.correct = nomadik_ecc_correct; - - return 0; -} diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h deleted file mode 100644 index dd70adcceaf..00000000000 --- a/include/configs/nhk8815.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2005 - * STMicroelectronics. - * Configuration settings for the "Nomadik Hardware Kit" NHK-8815, - * the evaluation board for the Nomadik 8815 System on Chip. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_NOMADIK_8815 /* cpu variant */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ - -/* commands */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_SYS_NO_FLASH -/* There is NAND storage */ -#define CONFIG_NAND_NOMADIK -#define CONFIG_CMD_JFFS2 - -/* user interface */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* boot config */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" -#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \ - " fsload 0x800000 initrd.gz.uimg;" \ - " bootm 0x100000 0x800000" - -/* memory-related information */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) -/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */ -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20)) - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) - -#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */ - -/* timing informazion */ -#define CONFIG_SYS_TIMERBASE 0x101E2000 - -/* serial port (PL011) configuration */ -#define CONFIG_PL011_SERIAL -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_SERIAL0 0x101FD000 -#define CFG_SERIAL1 0x101FB000 - -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } -#define CONFIG_PL011_CLOCK 48000000 - -/* i2c, for the port extenders (uses gpio.c in board directory) */ -#ifndef __ASSEMBLY__ -#include -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT 1 /* I2C bit-banged */ -#define I2C_SOFT_DEFS -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define __SDA 63 -#define __SCL 62 -#define I2C_SDA(x) nmk_gpio_set(__SDA, x) -#define I2C_SCL(x) nmk_gpio_set(__SCL, x) -#define I2C_READ (nmk_gpio_get(__SDA)!=0) -#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1) -#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0) -#define I2C_DELAY (udelay(2)) -#endif /* __ASSEMBLY__ */ - -/* Ethernet */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_IO_VADDR 0xee000000 -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) -#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) - -#define CONFIG_SMC91111 /* Using SMC91c111*/ -#define CONFIG_SMC91111_BASE 0x34000300 -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_IP_DEFRAG /* Allows faster download, TFTP and NFS */ -#define CONFIG_TFTP_BLOCKSIZE 4096 -#define CONFIG_NFS_READ_SIZE 4096 - -/* Storage information: onenand and nand */ -#define CONFIG_CMD_ONENAND -#define CONFIG_MTD_ONENAND_VERIFY_WRITE -#define CONFIG_SYS_ONENAND_BASE 0x30000000 - -#define CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ - -/* - * Filesystem information - * - * Since U-Boot has been loaded to RAM by vendor code, we could use - * either or both OneNand and Nand. However, we need to know where the - * filesystem lives. Comments below report vendor-selected partitions - */ -#ifdef CONFIG_BOOT_ONENAND - /* Partition Size Start - * XloaderTOC + X-Loader 256KB 0x00000000 - * Memory init function 256KB 0x00040000 - * U-Boot + env 2MB 0x00080000 - * Sysimage (kernel + ramdisk) 4MB 0x00280000 - * JFFS2 Root filesystem 22MB 0x00680000 - * JFFS2 User Data 227.5MB 0x01C80000 - */ -# define CONFIG_JFFS2_DEV "onenand0" -# define CONFIG_JFFS2_PART_SIZE 0x01600000 -# define CONFIG_JFFS2_PART_OFFSET 0x00680000 -# define CONFIG_ENV_IS_IN_ONENAND -# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ -# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE) - -#else /* BOOT_NAND */ - /* Partition Size Start - * XloaderTOC + X-Loader 256KB 0x00000000 - * Memory init function 256KB 0x00040000 - * U-Boot + env 2MB 0x00080000 - * Kernel Image 3MB 0x00280000 - * JFFS2 Root filesystem 22MB 0x00580000 - * JFFS2 User Data 100.5MB 0x01b80000 - */ -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ -# define CONFIG_JFFS2_PART_SIZE 0x01600000 -# define CONFIG_JFFS2_PART_OFFSET 0x00580000 -# define CONFIG_ENV_IS_IN_NAND -# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ -# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE) - -#endif /* CONFIG_BOOT_ONENAND */ - -/* this is needed to make hello_world.c and other stuff happy */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#endif /* __CONFIG_H */ diff --git a/include/nomadik.h b/include/nomadik.h deleted file mode 100644 index ea65b2d828c..00000000000 --- a/include/nomadik.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Collection of constants used to access Nomadik registers */ - -#ifndef __NOMADIK_H__ -#define __NOMADIK_H__ - -/* Base addresses of our peripherals */ -#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */ -#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ -#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ -#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ -#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */ -#define NOMADIK_1NAND_BASE 0x30000000 -#define NOMADIK_GPIO0_BASE 0x101E4000 -#define NOMADIK_GPIO1_BASE 0x101E5000 -#define NOMADIK_GPIO2_BASE 0x101E6000 -#define NOMADIK_GPIO3_BASE 0x101E7000 -#define NOMADIK_CPLD_BASE 0x36000000 -#define NOMADIK_UART0_BASE 0x101FD000 -#define NOMADIK_UART1_BASE 0x101FB000 -#define NOMADIK_UART2_BASE 0x101F2000 - -#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */ -#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */ - -#define NOMADIK_RTC_BASE 0x101E8000 -#define NOMADIK_ETH0_BASE 0x36800300 -#define NOMADIK_CPLD_UART_BASE 0x36480000 - -/* Chip select registers ("Flexible Static Memory Controller") */ - -#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00) -#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04) -#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08) -#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c) -#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40) -#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48) -#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c) -#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54) - -#endif /* __NOMADIK_H__ */ -- cgit v1.3.1 From 8dc372f93bd7d8f0ee87561d5c4b126697de85cc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:16 -0600 Subject: arm: Remove omap3_mvblx board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/omap3/Kconfig | 4 - board/matrix_vision/mvblx/Kconfig | 12 - board/matrix_vision/mvblx/MAINTAINERS | 6 - board/matrix_vision/mvblx/Makefile | 11 - board/matrix_vision/mvblx/config.mk | 17 -- board/matrix_vision/mvblx/fpga.c | 214 ----------------- board/matrix_vision/mvblx/fpga.h | 15 -- board/matrix_vision/mvblx/mvblx.c | 159 ------------- board/matrix_vision/mvblx/mvblx.h | 346 ---------------------------- board/matrix_vision/mvblx/sys_eeprom.c | 403 --------------------------------- configs/omap3_mvblx_defconfig | 9 - doc/README.omap3 | 4 - include/configs/omap3_mvblx.h | 277 ---------------------- 13 files changed, 1477 deletions(-) delete mode 100644 board/matrix_vision/mvblx/Kconfig delete mode 100644 board/matrix_vision/mvblx/MAINTAINERS delete mode 100644 board/matrix_vision/mvblx/Makefile delete mode 100644 board/matrix_vision/mvblx/config.mk delete mode 100644 board/matrix_vision/mvblx/fpga.c delete mode 100644 board/matrix_vision/mvblx/fpga.h delete mode 100644 board/matrix_vision/mvblx/mvblx.c delete mode 100644 board/matrix_vision/mvblx/mvblx.h delete mode 100644 board/matrix_vision/mvblx/sys_eeprom.c delete mode 100644 configs/omap3_mvblx_defconfig delete mode 100644 include/configs/omap3_mvblx.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 83cb7fff42a..b9040985529 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -93,9 +93,6 @@ config TARGET_OMAP3_LOGIC select DM_SERIAL select DM_GPIO -config TARGET_OMAP3_MVBLX - bool "OMAP3 MVBLX" - config TARGET_NOKIA_RX51 bool "Nokia RX51" @@ -143,7 +140,6 @@ source "board/8dtech/eco5pk/Kconfig" source "board/corscience/tricorder/Kconfig" source "board/htkw/mcx/Kconfig" source "board/logicpd/omap3som/Kconfig" -source "board/matrix_vision/mvblx/Kconfig" source "board/nokia/rx51/Kconfig" source "board/technexion/tao3530/Kconfig" source "board/technexion/twister/Kconfig" diff --git a/board/matrix_vision/mvblx/Kconfig b/board/matrix_vision/mvblx/Kconfig deleted file mode 100644 index adbc20a934e..00000000000 --- a/board/matrix_vision/mvblx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP3_MVBLX - -config SYS_BOARD - default "mvblx" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "omap3_mvblx" - -endif diff --git a/board/matrix_vision/mvblx/MAINTAINERS b/board/matrix_vision/mvblx/MAINTAINERS deleted file mode 100644 index 2f9a1532cbb..00000000000 --- a/board/matrix_vision/mvblx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBLX BOARD -M: Michael Jones -S: Maintained -F: board/matrix_vision/mvblx/ -F: include/configs/omap3_mvblx.h -F: configs/omap3_mvblx_defconfig diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile deleted file mode 100644 index c056ebaf781..00000000000 --- a/board/matrix_vision/mvblx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mvblx.o fpga.o -obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o - -ccflags-y += -Werror diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk deleted file mode 100644 index de13072dab4..00000000000 --- a/board/matrix_vision/mvblx/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c deleted file mode 100644 index 7f9b2455059..00000000000 --- a/board/matrix_vision/mvblx/fpga.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2011 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "fpga.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, /* Altera_pre_fn */ - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - fast_passive_parallel, - Altera_EP3C5_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -#define GPIO_RESET 43 -#define GPIO_DCLK 65 -#define GPIO_nSTATUS 157 -#define GPIO_CONF_DONE 158 -#define GPIO_nCONFIG 159 -#define GPIO_DATA0 54 -#define GPIO_DATA1 55 -#define GPIO_DATA2 56 -#define GPIO_DATA3 57 -#define GPIO_DATA4 58 -#define GPIO_DATA5 60 -#define GPIO_DATA6 61 -#define GPIO_DATA7 62 - -DECLARE_GLOBAL_DATA_PTR; - -/* return FPGA_SUCCESS on success, else FPGA_FAIL - */ -int mvblx_init_fpga(void) -{ - fpga_debug("Initializing FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - - if (gpio_request(GPIO_DCLK, "dclk") || - gpio_request(GPIO_nSTATUS, "nStatus") || -#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE - gpio_request(GPIO_CONF_DONE, "conf_done") || -#endif - gpio_request(GPIO_nCONFIG, "nConfig") || - gpio_request(GPIO_DATA0, "data0") || - gpio_request(GPIO_DATA1, "data1") || - gpio_request(GPIO_DATA2, "data2") || - gpio_request(GPIO_DATA3, "data3") || - gpio_request(GPIO_DATA4, "data4") || - gpio_request(GPIO_DATA5, "data5") || - gpio_request(GPIO_DATA6, "data6") || - gpio_request(GPIO_DATA7, "data7")) { - printf("%s: error requesting GPIOs.", __func__); - return FPGA_FAIL; - } - - /* set up outputs */ - gpio_direction_output(GPIO_DCLK, 0); - gpio_direction_output(GPIO_nCONFIG, 0); - gpio_direction_output(GPIO_DATA0, 0); - gpio_direction_output(GPIO_DATA1, 0); - gpio_direction_output(GPIO_DATA2, 0); - gpio_direction_output(GPIO_DATA3, 0); - gpio_direction_output(GPIO_DATA4, 0); - gpio_direction_output(GPIO_DATA5, 0); - gpio_direction_output(GPIO_DATA6, 0); - gpio_direction_output(GPIO_DATA7, 0); - - /* NB omap_free_gpio() resets to an input, so we can't - * free ie. nCONFIG, or else the FPGA would reset - * Q: presumably gpio_free() has the same effect? - */ - - /* set up inputs */ - gpio_direction_input(GPIO_nSTATUS); -#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE - gpio_direction_input(GPIO_CONF_DONE); -#endif - - fpga_config_fn(0, 1, 0); - udelay(60); - - return FPGA_SUCCESS; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert); - if (flush) { - gpio_set_value(GPIO_nCONFIG, !assert); - udelay(1); - gpio_set_value(GPIO_nCONFIG, assert); - } - - return assert; -} - -int fpga_done_fn(int cookie) -{ - int result = 0; - - /* since revA of BLX, we will not get this signal. */ - udelay(10); -#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE - fpga_debug("not waiting for CONF_DONE."); - result = 1; -#else - fpga_debug("CONF_DONE check ... "); - if (gpio_get_value(GPIO_CONF_DONE)) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - gpio_free(GPIO_CONF_DONE); -#endif - - return result; -} - -int fpga_status_fn(int cookie) -{ - int result = 0; - fpga_debug("STATUS check ... "); - - result = gpio_get_value(GPIO_nSTATUS); - - if (result < 0) - fpga_debug("error\n"); - else if (result > 0) - fpga_debug("high\n"); - else - fpga_debug("low\n"); - - return result; -} - -static inline int _write_fpga(u8 byte) -{ - gpio_set_value(GPIO_DATA0, byte & 0x01); - gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01); - gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01); - gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01); - gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01); - gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01); - gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01); - gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01); - - /* clock */ - gpio_set_value(GPIO_DCLK, 1); - udelay(1); - gpio_set_value(GPIO_DCLK, 0); - udelay(1); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - int headerlen = len - cyclone2.size; - - if (headerlen < 0) - return FPGA_FAIL; - else if (headerlen == sizeof(uint32_t)) { - const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */ - char fpgavers_str[fpgavers_len]; - snprintf(fpgavers_str, fpgavers_len, "0x%08x", - be32_to_cpup((uint32_t*)data)); - setenv("fpgavers", fpgavers_str); - } - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = headerlen; i < len; i++) - _write_fpga(data[i]); - fpga_debug("-%s\n", __func__); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h deleted file mode 100644 index 411b039c016..00000000000 --- a/board/matrix_vision/mvblx/fpga.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvblx_init_fpga(void); - -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c deleted file mode 100644 index c9d615b79a2..00000000000 --- a/board/matrix_vision/mvblx/mvblx.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * MATRIX VISION GmbH mvBlueLYNX-X - * - * Derived from Beagle and Overo - * - * (C) Copyright 2004-2008 - * Texas Instruments, - * - * Author : - * Sunil Kumar - * Shashi Ranjan - * - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mvblx.h" -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) -static void setup_net_chip(void); -#endif /* CONFIG_CMD_NET */ - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - printf("mvBlueLYNX-X\n"); - if (get_cpu_family() == CPU_OMAP36XX) - setenv("mpurate", "1000"); - else - setenv("mpurate", "600"); - - twl4030_power_init(); - -#if defined(CONFIG_CMD_NET) - setup_net_chip(); -#endif /* CONFIG_CMD_NET */ - - mvblx_init_fpga(); - - mac_read_from_eeprom(); - - dieid_num_r(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_MVBLX(); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - omap_mmc_init(0, 0, 0, -1, -1); - omap_mmc_init(1, 0, 0, -1, -1); - return 0; -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); - twl4030_power_mmc_init(1); -} -#endif - -#if defined(CONFIG_CMD_NET) -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - /* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1); - writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2); - writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3); - writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4); - writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5); - writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6); - writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - /* Make GPIO 139 as output pin */ - writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe); - - /* Now send a pulse on the GPIO pin */ - writel(GPIO11, &gpio5_base->setdataout); - udelay(1); - writel(GPIO11, &gpio5_base->cleardataout); - udelay(1); - writel(GPIO11, &gpio5_base->setdataout); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -int overwrite_console(void) -{ - /* return true if console should be overwritten */ - return 0; -} - -#endif /* CONFIG_CMD_NET */ diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h deleted file mode 100644 index 6c1c752e489..00000000000 --- a/board/matrix_vision/mvblx/mvblx.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * (C) Copyright 2008 - * Dirk Behme - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _MVBLX_H_ -#define _MVBLX_H_ - -#include - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "OMAP3 mvBlueLYNX-X camera", - "no NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_MVBLX() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\ - MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ - /*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ - /*Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - /*Expansion card 1*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ - MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ - MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\ - /*Expansion card 2 */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - /*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\ - MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\ - /*Modem Interface */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\ - MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ - MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ - MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\ - MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\ - MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\ - /* USB EHCI (port 2) not used */\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ - MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ - MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ - MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\ - /* USB EHCI (port 1) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\ - /*Die to Die */\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ - -#endif diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c deleted file mode 100644 index db429870102..00000000000 --- a/board/matrix_vision/mvblx/sys_eeprom.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor - * York Sun (yorksun@freescale.com) - * Haiying Wang (haiying.wang@freescale.com) - * Timur Tabi (timur@freescale.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* #define DEBUG */ - -/* - * static eeprom: EEPROM layout - */ -static struct __attribute__ ((__packed__)) eeprom { - u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */ - u8 sn[10]; /* 0x10 - 0x19 Serial Number */ - u8 date[6]; /* 0x1A - 0x1F Build Date */ - u8 mac[6]; /* 0x20 - 0x25 MAC address */ - u8 reserved[10];/* 0x26 - 0x2f reserved */ - u32 crc; /* x+1 CRC32 checksum */ -} e; - -/* Set to 1 if we've read EEPROM into memory */ -static int has_been_read; - -/** - * show_eeprom - display the contents of the EEPROM - */ -static void show_eeprom(void) -{ - unsigned int crc; - char safe_string[16]; - -#ifdef DEBUG - int i; -#endif - u8 *p; - - /* ID */ - strncpy(safe_string, (char *)e.id, sizeof(e.id)); - safe_string[sizeof(e.id)-1] = 0; - printf("ID: mvBlueLYNX-X%s\n", safe_string); - - /* Serial number */ - strncpy(safe_string, (char *)e.sn, sizeof(e.sn)); - safe_string[sizeof(e.sn)-1] = 0; - printf("SN: %s\n", safe_string); - - /* Build date, BCD date values, as YYMMDDhhmmss */ - printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", - e.date[0], e.date[1], e.date[2], - e.date[3] & 0x7F, e.date[4], e.date[5], - e.date[3] & 0x80 ? "PM" : ""); - - /* Show MAC address */ - p = e.mac; - printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n", - p[0], p[1], p[2], p[3], p[4], p[5]); - - crc = crc32(0, (void *)&e, sizeof(e) - 4); - - if (crc == be32_to_cpu(e.crc)) - printf("CRC: %08x\n", be32_to_cpu(e.crc)); - else - printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc); - -#ifdef DEBUG - printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); - for (i = 0; i < sizeof(e); i++) { - if ((i % 16) == 0) - printf("%02X: ", i); - printf("%02X ", ((u8 *)&e)[i]); - if (((i % 16) == 15) || (i == sizeof(e) - 1)) - printf("\n"); - } -#endif -} - -/** - * read_eeprom - read the EEPROM into memory - */ -static int read_eeprom(void) -{ - int ret; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus; -#endif - - if (has_been_read) - return 0; - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif - - ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - (uchar *)&e, sizeof(e)); - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif - -#ifdef DEBUG - show_eeprom(); -#endif - - has_been_read = (ret == 0) ? 1 : 0; - - return ret; -} - -/** - * update_crc - update the CRC - * - * This function should be called after each update to the EEPROM structure, - * to make sure the CRC is always correct. - */ -static void update_crc(void) -{ - u32 crc; - - crc = crc32(0, (void *)&e, sizeof(e) - 4); - e.crc = cpu_to_be32(crc); -} - -/** - * prog_eeprom - write the EEPROM from memory - */ -static int prog_eeprom(void) -{ - int ret = 0; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus; -#endif - - update_crc(); - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif - - ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - (uchar *)&e, sizeof(e)); - - if (!ret) { - /* Verify the write by reading back the EEPROM and comparing */ - struct eeprom e2; -#ifdef DEBUG - printf("%s verifying...\n", __func__); -#endif - ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - (uchar *)&e2, sizeof(e2)); - - if (!ret && memcmp(&e, &e2, sizeof(e))) - ret = -1; - } - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif - - if (ret) { - printf("Programming failed.\n"); - has_been_read = 0; - return -1; - } - - printf("Programming passed.\n"); - return 0; -} - -/** - * h2i - converts hex character into a number - * - * This function takes a hexadecimal character (e.g. '7' or 'C') and returns - * the integer equivalent. - */ -static inline u8 h2i(char p) -{ - if ((p >= '0') && (p <= '9')) - return p - '0'; - - if ((p >= 'A') && (p <= 'F')) - return (p - 'A') + 10; - - if ((p >= 'a') && (p <= 'f')) - return (p - 'a') + 10; - - return 0; -} - -/** - * set_date - stores the build date into the EEPROM - * - * This function takes a pointer to a string in the format "YYMMDDhhmmss" - * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, - * and stores it in the build date field of the EEPROM local copy. - */ -static void set_date(const char *string) -{ - unsigned int i; - - if (strlen(string) != 12) { - printf("Usage: mac date YYMMDDhhmmss\n"); - return; - } - - for (i = 0; i < 6; i++) - e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); - - update_crc(); -} - -/** - * set_mac_address - stores a MAC address into the EEPROM - * - * This function takes a pointer to MAC address string - * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and - * stores it in the MAC address field in the EEPROM local copy. - */ -static void set_mac_address(const char *string) -{ - char *p = (char *) string; - unsigned int i; - - for (i = 0; *p && (i < 6); i++) { - e.mac[i] = simple_strtoul(p, &p, 16); - if (*p == ':') - p++; - } - - update_crc(); -} - -int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char cmd; - - if (argc == 1) { - show_eeprom(); - return 0; - } - - cmd = argv[1][0]; - - if (cmd == 'r') { -#ifdef DEBUG - printf("%s read\n", __func__); -#endif - read_eeprom(); - return 0; - } - - if (argc == 2) { - switch (cmd) { - case 's': /* save */ -#ifdef DEBUG - printf("%s save\n", __func__); -#endif - prog_eeprom(); - break; - default: - return cmd_usage(cmdtp); - } - - return 0; - } - - /* We know we have at least one parameter */ - - switch (cmd) { - case 'n': /* serial number */ -#ifdef DEBUG - printf("%s serial number\n", __func__); -#endif - memset(e.sn, 0, sizeof(e.sn)); - strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); - update_crc(); - break; - case 'd': /* date BCD format YYMMDDhhmmss */ - set_date(argv[2]); - break; - case 'e': /* errata */ - printf("mac errata not implemented\n"); - break; - case 'i': /* id */ - memset(e.id, 0, sizeof(e.id)); - strncpy((char *)e.id, argv[2], sizeof(e.id) - 1); - update_crc(); - break; - case 'p': /* ports */ - printf("mac ports not implemented (always 1 port)\n"); - break; - case '0' ... '9': - /* we only have "mac 0" but any digit can be used here */ - set_mac_address(argv[2]); - break; - case 'h': /* help */ - default: - return cmd_usage(cmdtp); - } - - return 0; -} - -static inline int is_portrait(void) -{ - int i; - unsigned int orient_index = 0; /* idx of char which determines orientation */ - - for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) { - if (e.id[i] == '-') { - orient_index = i+1; - break; - } - } - - return (orient_index && - (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8')); -} - -int mac_read_from_eeprom(void) -{ - u32 crc, crc_offset = offsetof(struct eeprom, crc); - u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ -#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf" -#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf" - - if (read_eeprom()) { - printf("EEPROM Read failed.\n"); - return -1; - } - - crc = crc32(0, (void *)&e, crc_offset); - crcp = (void *)&e + crc_offset; - if (crc != be32_to_cpu(*crcp)) { - printf("EEPROM CRC mismatch (%08x != %08x)\n", crc, - be32_to_cpu(e.crc)); - return -1; - } - - if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) && - memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { - char ethaddr[18]; - - sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - e.mac[0], - e.mac[1], - e.mac[2], - e.mac[3], - e.mac[4], - e.mac[5]); - /* Only initialize environment variables that are blank - * (i.e. have not yet been set) - */ - if (!getenv("ethaddr")) - setenv("ethaddr", ethaddr); - } - - if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) && - memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) { - char serial_num[12]; - - strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1); - /* Only initialize environment variables that are blank - * (i.e. have not yet been set) - */ - if (!getenv("serial#")) - setenv("serial#", serial_num); - } - - /* decide which fpga file to load depending on orientation */ - if (is_portrait()) - setenv("fpgafilename", FILENAME_PORTRAIT); - else - setenv("fpgafilename", FILENAME_LANDSCAPE); - - /* TODO should I calculate CRC here? */ - return 0; -} - -#ifdef CONFIG_SERIAL_TAG -void get_board_serial(struct tag_serialnr *serialnr) -{ - char *serial = getenv("serial#"); - - if (serial && (strlen(serial) > 3)) { - /* use the numerical part of the serial number LXnnnnnn */ - serialnr->high = 0; - serialnr->low = simple_strtoul(serial + 2, NULL, 10); - } else { - serialnr->high = 0; - serialnr->low = 0; - } -} -#endif diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig deleted file mode 100644 index fb12a70560b..00000000000 --- a/configs/omap3_mvblx_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_OMAP34XX=y -CONFIG_TARGET_OMAP3_MVBLX=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR="S" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="mvblx # " diff --git a/doc/README.omap3 b/doc/README.omap3 index a62c3574054..e09ac032c0f 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -68,10 +68,6 @@ make make cm_t35_config make -* BlueLYNX-X: - -make omap3_mvblx_config -make Custom commands =============== diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h deleted file mode 100644 index 9e2cf7333cf..00000000000 --- a/include/configs/omap3_mvblx.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * MATRIX VISION GmbH mvBlueLYNX-X - * - * Derived from omap3_beagle.h: - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * Configuration settings for the TI OMAP3530 Beagle board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ -#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include /* get chip and board defs */ -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 -#define CONFIG_SERIAL_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SERIAL1 1 /* UART1 */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* silent console by default */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_SILENT_CONSOLE 1 - -/* USB */ -#define CONFIG_USB_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 -#define CONFIG_USBD_VENDORID 0x164c -#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201 -#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201 -#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH" -#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X" - -/* no FLASH available */ -#define CONFIG_SYS_NO_FLASH - -/* commands to include */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_FPGA_LOADMK - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -/* Environment information */ -#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */ -#define CONFIG_BOOTDELAY 0 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "silent=true\0" \ - "loadaddr=0x82000000\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO0,115200n8\0" \ - "mpurate=600\0" \ - "vram=12M\0" \ - "dvimode=1024x768-24@60\0" \ - "defaultdisplay=dvi\0" \ - "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\ - "/lib/firmware/mvblx/${fpgafilename}; then " \ - "fpga load 0 ${loadaddr} ${filesize}; " \ - "fi;\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "mvfw.fpgavers=${fpgavers} " \ - "${cmdline_suffix}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmcbootcmd= " \ - "echo Trying mmc${mmcdev}; " \ - "mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loading boot environment from mmc${mmcdev}; " \ - "run importbootenv; " \ - "fi;" \ - "run loadfpga; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi;" \ - "fi\0" - -#define CONFIG_BOOTCOMMAND \ - "setenv mmcdev 1;" \ - "run mmcbootcmd || " \ - "setenv mmcdev 0;" \ - "run mmcbootcmd" - - -#define CONFIG_AUTO_COMPLETE 1 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */ -#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -#define CONFIG_ENV_IS_NOWHERE 1 - -/*---------------------------------------------------------------------------- - * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family) - *---------------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NET) - #define CONFIG_SMC911X 1 - #define CONFIG_SMC911X_32_BIT - #define CONFIG_SMC911X_BASE 0x2C000000 -#endif /* (CONFIG_CMD_NET) */ - -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_EEPROM_BUS_NUM 2 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_OMAP3_SPI - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 93b25c08139d08c4236bd16bb1cd6508b7df4b0b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:17 -0600 Subject: arm: Remove omap3_sdp3430 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/omap3/Kconfig | 4 - board/ti/sdp3430/Kconfig | 12 -- board/ti/sdp3430/MAINTAINERS | 6 - board/ti/sdp3430/Makefile | 8 - board/ti/sdp3430/config.mk | 17 -- board/ti/sdp3430/sdp.c | 203 -------------------- board/ti/sdp3430/sdp.h | 401 --------------------------------------- configs/omap3_sdp3430_defconfig | 7 - include/configs/omap3_sdp3430.h | 318 ------------------------------- 9 files changed, 976 deletions(-) delete mode 100644 board/ti/sdp3430/Kconfig delete mode 100644 board/ti/sdp3430/MAINTAINERS delete mode 100644 board/ti/sdp3430/Makefile delete mode 100644 board/ti/sdp3430/config.mk delete mode 100644 board/ti/sdp3430/sdp.c delete mode 100644 board/ti/sdp3430/sdp.h delete mode 100644 configs/omap3_sdp3430_defconfig delete mode 100644 include/configs/omap3_sdp3430.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index b9040985529..4fa72f7835b 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -12,9 +12,6 @@ config TARGET_MT_VENTOUX bool "TeeJet Mt.Ventoux" select SUPPORT_SPL -config TARGET_OMAP3_SDP3430 - bool "TI OMAP3430 SDP" - config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" select SUPPORT_SPL @@ -125,7 +122,6 @@ config SYS_SOC source "board/logicpd/am3517evm/Kconfig" source "board/teejet/mt_ventoux/Kconfig" -source "board/ti/sdp3430/Kconfig" source "board/ti/beagle/Kconfig" source "board/compulab/cm_t35/Kconfig" source "board/compulab/cm_t3517/Kconfig" diff --git a/board/ti/sdp3430/Kconfig b/board/ti/sdp3430/Kconfig deleted file mode 100644 index 7e73d99aba1..00000000000 --- a/board/ti/sdp3430/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP3_SDP3430 - -config SYS_BOARD - default "sdp3430" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "omap3_sdp3430" - -endif diff --git a/board/ti/sdp3430/MAINTAINERS b/board/ti/sdp3430/MAINTAINERS deleted file mode 100644 index 943c196d9f9..00000000000 --- a/board/ti/sdp3430/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SDP3430 BOARD -M: Nishanth Menon -S: Maintained -F: board/ti/sdp3430/ -F: include/configs/omap3_sdp3430.h -F: configs/omap3_sdp3430_defconfig diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile deleted file mode 100644 index 753f09979cc..00000000000 --- a/board/ti/sdp3430/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := sdp.o diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk deleted file mode 100644 index e4d9be13e39..00000000000 --- a/board/ti/sdp3430/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments Incorporated, -# -# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c deleted file mode 100644 index 7171363e764..00000000000 --- a/board/ti/sdp3430/sdp.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated, - * Richard Woodruff - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sdp.h" - -DECLARE_GLOBAL_DATA_PTR; - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "OMAP3 SDP3430 board", -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "OneNAND", -#elif defined(CONFIG_ENV_IS_IN_NAND) - "NAND", -#else - "NOR", -#endif -}; - -/* Timing definitions for GPMC controller for Sibley NOR */ -static const u32 gpmc_sdp_nor[] = { - SDP3430_NOR_GPMC_CONF1, - SDP3430_NOR_GPMC_CONF2, - SDP3430_NOR_GPMC_CONF3, - SDP3430_NOR_GPMC_CONF4, - SDP3430_NOR_GPMC_CONF5, - SDP3430_NOR_GPMC_CONF6, - /*CONF7- computed as params */ -}; - -/* - * Timing definitions for GPMC controller for Debug Board - * Debug board contains access to ethernet and DIP Switch setting - * information etc. - */ -static const u32 gpmc_sdp_debug[] = { - SDP3430_DEBUG_GPMC_CONF1, - SDP3430_DEBUG_GPMC_CONF2, - SDP3430_DEBUG_GPMC_CONF3, - SDP3430_DEBUG_GPMC_CONF4, - SDP3430_DEBUG_GPMC_CONF5, - SDP3430_DEBUG_GPMC_CONF6, - /*CONF7- computed as params */ -}; - -/* Timing defintions for GPMC OneNAND */ -static const u32 gpmc_sdp_onenand[] = { - SDP3430_ONENAND_GPMC_CONF1, - SDP3430_ONENAND_GPMC_CONF2, - SDP3430_ONENAND_GPMC_CONF3, - SDP3430_ONENAND_GPMC_CONF4, - SDP3430_ONENAND_GPMC_CONF5, - SDP3430_ONENAND_GPMC_CONF6, - /*CONF7- computed as params */ -}; - -/* GPMC definitions for GPMC NAND */ -static const u32 gpmc_sdp_nand[] = { - SDP3430_NAND_GPMC_CONF1, - SDP3430_NAND_GPMC_CONF2, - SDP3430_NAND_GPMC_CONF3, - SDP3430_NAND_GPMC_CONF4, - SDP3430_NAND_GPMC_CONF5, - SDP3430_NAND_GPMC_CONF6, - /*CONF7- computed as params */ -}; - -/* gpmc_cfg is initialized by gpmc_init and we use it here */ -extern struct gpmc *gpmc_cfg; - -/** - * @brief board_init - gpmc and basic setup as phase1 of boot sequence - * - * @return 0 - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* TODO: Dynamically pop out CS mapping and program accordingly */ - /* Configure devices for default ON ON ON settings */ - enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0], - CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M); - enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000, - GPMC_SIZE_16M); - enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000, - GPMC_SIZE_16M); - enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE, - GPMC_SIZE_16M); - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c) -#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b) - -/** - * @brief board_eth_init Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - */ -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - int cnt = 20; - - writew(0x0, LAN_RESET_REGISTER); - do { - writew(0x1, LAN_RESET_REGISTER); - udelay(100); - if (cnt == 0) - goto reset_err_out; - --cnt; - } while (readw(LAN_RESET_REGISTER) != 0x1); - - cnt = 20; - - do { - writew(0x0, LAN_RESET_REGISTER); - udelay(100); - if (cnt == 0) - goto reset_err_out; - --cnt; - } while (readw(LAN_RESET_REGISTER) != 0x0000); - udelay(1000); - - writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG); - udelay(1000); - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -reset_err_out: - -#endif - return rc; -} - -/** - * @brief misc_init_r - Configure SDP board specific configurations - * such as power configurations, ethernet initialization as phase2 of - * boot sequence - * - * @return 0 - */ -int misc_init_r(void) -{ - /* Partial setup: - * VAUX3 - 2.8V for DVI - * VPLL1 - 1.8V - * VDAC - 1.8V - * and turns on LEDA/LEDB (not needed ... NOP?) - */ - twl4030_power_init(); - - /* FIXME finish setup: - * VAUX1 - 2.8V for mainboard I/O - * VAUX2 - 2.8V for camera - * VAUX4 - 1.8V for OMAP3 CSI - * VMMC1 - 3.15V (init, variable) for MMC1 - * VMMC2 - 1.85V for MMC2 - * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM - * VPLL2 - 1.8V - */ - - return 0; -} - -/** - * @brief set_muxconf_regs Setting up the configuration Mux registers - * specific to the hardware. Many pins need to be moved from protect - * to primary mode. - */ -void set_muxconf_regs(void) -{ - /* platform specific muxes */ - MUX_SDP3430(); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h deleted file mode 100644 index 0e631897e38..00000000000 --- a/board/ti/sdp3430/sdp.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _BOARD_SDP_H_ -#define _BOARD_SDP_H_ - -#define OFF_IN_PD 0 -#define OFF_OUT_PD 0 - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_SDP3430()\ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\ - MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\ - MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\ - MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\ - MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\ - MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - /*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\ - MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\ - MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\ - MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - /*Audio InterfACe */\ - MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - /*Expansion Card */\ - MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\ - /*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\ - MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\ - MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\ - MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\ - /*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - /*Modem Interface */\ - MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ - MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\ - MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\ - MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\ - MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\ - MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\ - MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ - MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\ - MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\ - MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\ - MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\ - MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\ - MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\ - MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\ - MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\ - MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ - MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\ - MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\ - MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\ - MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\ - MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - /*Die to Die */\ - MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ - MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\ - MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/ - -/* - * GPMC Timing definitions for SDP3430 - * at L3 = 166Mhz - */ - -/* Timing definitions for GPMC controller for Sibley NOR */ -#define SDP3430_NOR_GPMC_CONF1 0x00001200 -#define SDP3430_NOR_GPMC_CONF2 0x001F1F00 -#define SDP3430_NOR_GPMC_CONF3 0x00080802 -#define SDP3430_NOR_GPMC_CONF4 0x1C091C09 -#define SDP3430_NOR_GPMC_CONF5 0x01131F1F -#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2 - -/* - * Timing definitions for GPMC controller for Debug Board - * Debug board contains access to ethernet and DIP Switch setting - * information etc. - */ -#define SDP3430_DEBUG_GPMC_CONF1 0x00611200 -#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01 -#define SDP3430_DEBUG_GPMC_CONF3 0x00080803 -#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09 -#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F -#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4 - -/* Timing defintions for GPMC OneNAND */ -#define SDP3430_ONENAND_GPMC_CONF1 0x00001200 -#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01 -#define SDP3430_ONENAND_GPMC_CONF3 0x00030301 -#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04 -#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010 -#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000 - -/* GPMC definitions for GPMC NAND */ -#define SDP3430_NAND_GPMC_CONF1 0x00000800 -#define SDP3430_NAND_GPMC_CONF2 0x00141400 -#define SDP3430_NAND_GPMC_CONF3 0x00141400 -#define SDP3430_NAND_GPMC_CONF4 0x0F010F01 -#define SDP3430_NAND_GPMC_CONF5 0x010C1414 -#define SDP3430_NAND_GPMC_CONF6 0x1F040A80 - -#endif /* _BOARD_SDP_H_ */ diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig deleted file mode 100644 index 2e46091986a..00000000000 --- a/configs/omap3_sdp3430_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_OMAP34XX=y -CONFIG_TARGET_OMAP3_SDP3430=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="OMAP34XX SDP # " diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h deleted file mode 100644 index f43e477ad25..00000000000 --- a/include/configs/omap3_sdp3430.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments Incorporated. - * Richard Woodruff - * Syed Mohammed Khasim - * Nishanth Menon - * - * Configuration settings for the 3430 TI SDP3430 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* TODO: REMOVE THE FOLLOWING - * Retained the following till size.h is removed in u-boot - */ -#include -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include /* get chip and board defs */ -#include - -/* - * NOTE: these #defines presume standard SDP jumper settings. - * In particular: - * - 26 MHz clock (not 19.2 or 38.4 MHz) - * - Boot from 128MB NOR, not NAND or OneNAND - * - * At this writing, OMAP3 U-Boot support doesn't permit concurrent - * support for all the flash types the board supports. - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - * Total Size Environment - 256k - * Malloc - add 256k - */ -#define CONFIG_ENV_SIZE (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) - -/*--------------------------------------------------------------------------*/ - -/* - * Hardware drivers - */ - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -/* - * serial port - NS16550 compatible - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be - * swapped with UART2 via jumpering. Downsides of using J8: it doesn't - * support UART boot (that's only for UART3); it prevents sharing a Linux - * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards. - * - * UART boot uses UART3 on J9, and the SDP user's guide says to use - * that for console. Downsides of using J9: you can't use IRDA too; - * since UART3 isn't in the CORE power domain, it may be a bit less - * usable in certain PM-sensitive debug scenarios. - */ -#undef CONSOLE_J9 /* else J8/UART1 (innermost) */ - -#ifdef CONSOLE_J9 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 */ -#else -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SERIAL1 1 /* UART1 */ -#endif - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * I2C for power management setup - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* OMITTED: single 1 Gbit MT29F1G NAND flash */ - -/* - * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash - */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH 2 -#define PHYS_FLASH_SIZE (128 << 20) -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */ - -/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10) -#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE) -/*--------------------------------------------------------------------------*/ - -/* Enabled commands */ -#define CONFIG_CMD_DHCP /* DHCP Support */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_MMC /* MMC support */ - -/*--------------------------------------------------------------------------*/ -/* - * MMC boot support - */ - -#if defined(CONFIG_CMD_MMC) -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 -#endif - -/*---------------------------------------------------------------------------- - * SMSC9115 Ethernet from SMSC9118 family - *---------------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NET) - -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE DEBUG_BASE -#define CONFIG_LAN91C96_EXT_PHY - -#define CONFIG_BOOTP_SEND_HOSTNAME -/* - * BOOTP fields - */ -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 -#endif /* (CONFIG_CMD_NET) */ - -/* - * Environment setup - * - * Default boot order: mmc bootscript, MMC uImage, NOR image. - * Network booting environment must be configured at site. - */ - -/* allow overwriting serial config and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS0,115200n8\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "norargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock3 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from MMC/SD ...; " \ - "autoscr ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from MMC/SD ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "norboot=echo Booting from NOR ...; " \ - "run norargs; " \ - "bootm 0x80000\0" \ - -#define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run norboot; " \ - "fi; " \ - "fi; " \ - "else run norboot; fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/*--------------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg - - * a basic sanity check ONLY - * IF you would like to increase coverage, increase the end address - * or run the test with custom options - */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/*--------------------------------------------------------------------------*/ - -/* - * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * SDRAM Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*--------------------------------------------------------------------------*/ - -/* - * NOR FLASH usage ... default nCS0: - * - one 256KB sector for U-Boot - * - one 256KB sector for its parameters (not all used) - * - eight sectors (2 MB) for kernel - * - rest for JFFS2 - */ - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * NAND FLASH usage ... default nCS1: - * - four 128KB sectors for X-Loader - * - four 128KB sectors for U-Boot - * - two 128KB sector for its parameters - * - 32 sectors (4 MB) for kernel - * - rest for filesystem - */ - -/* - * OneNAND FLASH usage ... default nCS2: - * - four 128KB sectors for X-Loader - * - two 128KB sectors for U-Boot - * - one 128KB sector for its parameters - * - sixteen sectors (2 MB) for kernel - * - rest for filesystem - */ - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 7a2c1b13d70f38c38c4a4fe153265a861ebd5cd2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:18 -0600 Subject: arm: Remove openrd boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/openrd/Kconfig | 12 --- board/Marvell/openrd/MAINTAINERS | 12 --- board/Marvell/openrd/Makefile | 14 ---- board/Marvell/openrd/kwbimage.cfg | 152 ----------------------------------- board/Marvell/openrd/openrd.c | 161 -------------------------------------- board/Marvell/openrd/openrd.h | 30 ------- configs/openrd_base_defconfig | 7 -- configs/openrd_client_defconfig | 7 -- configs/openrd_ultimate_defconfig | 7 -- include/configs/openrd.h | 137 -------------------------------- 11 files changed, 543 deletions(-) delete mode 100644 board/Marvell/openrd/Kconfig delete mode 100644 board/Marvell/openrd/MAINTAINERS delete mode 100644 board/Marvell/openrd/Makefile delete mode 100644 board/Marvell/openrd/kwbimage.cfg delete mode 100644 board/Marvell/openrd/openrd.c delete mode 100644 board/Marvell/openrd/openrd.h delete mode 100644 configs/openrd_base_defconfig delete mode 100644 configs/openrd_client_defconfig delete mode 100644 configs/openrd_ultimate_defconfig delete mode 100644 include/configs/openrd.h (limited to 'include') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ed9ea8aec60..6228f5bc117 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -4,9 +4,6 @@ choice prompt "Marvell Kirkwood board select" optional -config TARGET_OPENRD - bool "Marvell OpenRD Board" - config TARGET_RD6281A bool "RD6281A Board" @@ -63,7 +60,6 @@ endchoice config SYS_SOC default "kirkwood" -source "board/Marvell/openrd/Kconfig" source "board/Marvell/rd6281a/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig deleted file mode 100644 index 124b66da0f1..00000000000 --- a/board/Marvell/openrd/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OPENRD - -config SYS_BOARD - default "openrd" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "openrd" - -endif diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS deleted file mode 100644 index 7a189ab6d52..00000000000 --- a/board/Marvell/openrd/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -OPENRD BOARD -M: Prafulla Wadaskar -S: Maintained -F: board/Marvell/openrd/ -F: include/configs/openrd.h -F: configs/openrd_base_defconfig - -OPENRD_CLIENT BOARD -#M: - -S: Maintained -F: configs/openrd_client_defconfig -F: configs/openrd_ultimate_defconfig diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile deleted file mode 100644 index 8f95b7922e3..00000000000 --- a/board/Marvell/openrd/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2009 -# Net Insight -# Written-by: Simon Kagstrom -# -# Based on sheevaplug: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := openrd.o diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg deleted file mode 100644 index 8e5993715ed..00000000000 --- a/board/Marvell/openrd/kwbimage.cfg +++ /dev/null @@ -1,152 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strength reduced -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) - -DATA 0xFFD0149C 0x0000E40f # CPU ODT Control -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm -# bit14: 1, M_STARTBURST_IN ODT: Enabled -# bit15: 1, DDR IO ODT Unit: Use ODT block -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c deleted file mode 100644 index 55cf525cf8a..00000000000 --- a/board/Marvell/openrd/openrd.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.c: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "openrd.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, /* Alt UART1_TXD */ - MPP14_SD_D0, /* Alt UART1_RXD */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_TSMP9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, /* UART1 / SD sel */ - MPP35_TDM_CH0_TX_QL, - MPP36_TDM_SPI_CS1, - MPP37_TDM_CH2_TX_QL, - MPP38_TDM_CH2_RX_QL, - MPP39_AUDIO_I2SBCLK, - MPP40_AUDIO_I2SDO, - MPP41_AUDIO_I2SLRC, - MPP42_AUDIO_I2SMCLK, - MPP43_AUDIO_I2SDI, - MPP44_AUDIO_EXTCLK, - MPP45_TDM_PCLK, - MPP46_TDM_FS, - MPP47_TDM_DRX, - MPP48_TDM_DTX, - MPP49_TDM_CH0_RX_QL, - 0 - }; - - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ -#if defined(CONFIG_BOARD_IS_OPENRD_BASE) - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; -#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; -#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116/88E1121 PHY */ -void mv_phy_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf(PHY_NO" Initialized on %s\n", name); -} - -void reset_phy(void) -{ - mv_phy_init("egiga0"); - -#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT - /* Kirkwood ethernet driver is written with the assumption that in case - * of multiple PHYs, their addresses are consecutive. But unfortunately - * in case of OpenRD-Client, PHY addresses are not consecutive.*/ - miiphy_write("egiga1", 0xEE, 0xEE, 24); -#endif - -#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ - defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) - /* configure and initialize both PHY's */ - mv_phy_init("egiga1"); -#endif -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h deleted file mode 100644 index 56dfeea1a8e..00000000000 --- a/board/Marvell/openrd/openrd.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __OPENRD_BASE_H -#define __OPENRD_BASE_H - -#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ -#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ -#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __OPENRD_BASE_H */ diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig deleted file mode 100644 index 16861397c3a..00000000000 --- a/configs/openrd_base_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_OPENRD=y -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig deleted file mode 100644 index c34231560c6..00000000000 --- a/configs/openrd_client_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_OPENRD=y -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig deleted file mode 100644 index 530ba4d10cf..00000000000 --- a/configs/openrd_ultimate_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_OPENRD=y -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/openrd.h b/include/configs/openrd.h deleted file mode 100644 index 72113144b3c..00000000000 --- a/include/configs/openrd.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_OPENRD_H -#define _CONFIG_OPENRD_H - -/* - * Version number information - */ -#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" -#else -# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT -# define CONFIG_IDENT_STRING "\nOpenRD-Client" -# else -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_IDENT_STRING "\nOpenRD-Base" -# else -# error Unknown OpenRD board specified -# endif -# endif -#endif - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_OPENRD_BASE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_SYS_MVFS -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_IDE - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define MTDIDS_DEFAULT "nand0=nand_mtd" -#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ - "0x400000@0x100000(uImage),"\ - "0x1fb00000@0x500000(rootfs)" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ - "mtdids="MTDIDS_DEFAULT"\0" \ - "mtdparts="MTDPARTS_DEFAULT"\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -# else -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -# endif -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_PHY_BASE_ADR 0x0 -# define PHY_NO "88E1121" -# else -# define CONFIG_PHY_BASE_ADR 0x8 -# define PHY_NO "88E1116" -# endif -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -#endif /* _CONFIG_OPENRD_BASE_H */ -- cgit v1.3.1 From 819216ddfab1e81430086fd0c8e7f187c38dd81a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:19 -0600 Subject: arm: Remove otc570 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-at91/Kconfig | 5 - board/esd/otc570/Kconfig | 12 -- board/esd/otc570/MAINTAINERS | 7 - board/esd/otc570/Makefile | 13 -- board/esd/otc570/otc570.c | 372 ------------------------------------- board/esd/otc570/partition.c | 23 --- configs/otc570_dataflash_defconfig | 8 - configs/otc570_defconfig | 8 - include/configs/otc570.h | 252 ------------------------- 9 files changed, 700 deletions(-) delete mode 100644 board/esd/otc570/Kconfig delete mode 100644 board/esd/otc570/MAINTAINERS delete mode 100644 board/esd/otc570/Makefile delete mode 100644 board/esd/otc570/otc570.c delete mode 100644 board/esd/otc570/partition.c delete mode 100644 configs/otc570_dataflash_defconfig delete mode 100644 configs/otc570_defconfig delete mode 100644 include/configs/otc570.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index de06416da51..cb2994c2817 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -103,10 +103,6 @@ config TARGET_MEESC bool "Support meesc" select CPU_ARM926EJS -config TARGET_OTC570 - bool "Support otc570" - select CPU_ARM926EJS - config TARGET_CORVUS bool "Support corvus" select CPU_ARM926EJS @@ -144,7 +140,6 @@ source "board/BuS/vl_ma2sc/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" -source "board/esd/otc570/Kconfig" source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" diff --git a/board/esd/otc570/Kconfig b/board/esd/otc570/Kconfig deleted file mode 100644 index 4966f5f755b..00000000000 --- a/board/esd/otc570/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OTC570 - -config SYS_BOARD - default "otc570" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "otc570" - -endif diff --git a/board/esd/otc570/MAINTAINERS b/board/esd/otc570/MAINTAINERS deleted file mode 100644 index a7e165d8bad..00000000000 --- a/board/esd/otc570/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -OTC570 BOARD -M: Daniel Gorsulowski -S: Maintained -F: board/esd/otc570/ -F: include/configs/otc570.h -F: configs/otc570_defconfig -F: configs/otc570_dataflash_defconfig diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile deleted file mode 100644 index 740bb0a2826..00000000000 --- a/board/esd/otc570/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop -# Lead Tech Design -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += otc570.o -obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c deleted file mode 100644 index 4751d0a9e99..00000000000 --- a/board/esd/otc570/otc570.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * (C) Copyright 2010-2011 - * Daniel Gorsulowski - * esd electronic system design gmbh - * - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_LCD -# include -# include -# ifdef CONFIG_LCD_INFO -# include -# include -# endif -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -static int hw_rev = -1; /* hardware revision */ - -int get_hw_rev(void) -{ - if (hw_rev >= 0) - return hw_rev; - - hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); - hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; - hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; - hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; - - if (hw_rev == 15) - hw_rev = 0; - - return hw_rev; -} - -#ifdef CONFIG_CMD_NAND -static void otc570_nand_hw_init(void) -{ - unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; - at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; - - /* Enable CS3 */ - csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; - writel(csa, &matrix->csa[0]); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), - &smc->cs[3].setup); - - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - - writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(12), - &smc->cs[3].mode); - - /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); - - /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif /* CONFIG_CMD_NAND */ - -#ifdef CONFIG_MACB -static void otc570_macb_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); - at91_macb_hw_init(); -} -#endif - -/* - * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT - * controller debugging - * The ET1100 is located at physical address 0x70000000 - * Its process memory is located at physical address 0x70001000 - */ -static void otc570_ethercat_hw_init(void) -{ - at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; - - /* Configure SMC EBI1_CS0 for EtherCAT */ - writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), - &smc1->cs[0].setup); - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | - AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), - &smc1->cs[0].pulse); - writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), - &smc1->cs[0].cycle); - /* - * Configure behavior at external wait signal, byte-select mode, 16 bit - * data bus width, none data float wait states and TDF optimization - */ - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | - AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | - AT91_SMC_MODE_TDF, &smc1->cs[0].mode); - - /* Configure RDY/BSY */ - at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ -} - -#ifdef CONFIG_LCD -/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */ -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_clk = 25175000, - .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - - .vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */ - .vl_tft = 1, /* 0 = passive, 1 = TFT */ - .vl_vsync_len = 1, /* Length of vertical sync in NOL */ - .vl_upper_margin = 35, /* Idle lines at the frame start */ - .vl_lower_margin = 5, /* Idle lines at the end of the frame */ - .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */ - .vl_left_margin = 112, /* Idle cycles at the line beginning */ - .vl_right_margin = 1, /* Idle cycles at the end of the line */ - - .mmio = ATMEL_BASE_LCDC, -}; - -void lcd_enable(void) -{ - at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */ -} - -void lcd_disable(void) -{ - at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */ -} - -static void otc570_lcd_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ - at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ - at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ - at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */ - - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); -} - -#ifdef CONFIG_LCD_INFO -void lcd_show_board_info(void) -{ - ulong dram_size, nand_size; - int i; - char temp[32]; - - dram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; - nand_size = 0; - for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; - - lcd_printf("\n%s\n", U_BOOT_VERSION); - lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate())); - lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", - dram_size >> 20, - nand_size >> 20 ); - lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n"); - lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev()); - lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number); -} -#endif /* CONFIG_LCD_INFO */ -#endif /* CONFIG_LCD */ - -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); -#endif - return rc; -} - -int checkboard(void) -{ - char str[32]; - - puts("Board : esd ARM9 HMI Panel - OTC570"); - if (getenv_f("serial#", str, sizeof(str)) > 0) { - puts(", serial# "); - puts(str); - } - printf("\n"); - printf("Hardware-revision: 1.%d\n", get_hw_rev()); - printf("Mach-type : %lu\n", gd->bd->bi_arch_number); - return 0; -} - -#ifdef CONFIG_SERIAL_TAG -void get_board_serial(struct tag_serialnr *serialnr) -{ - char *str; - - char *serial = getenv("serial#"); - if (serial) { - str = strchr(serial, '_'); - if (str && (strlen(str) >= 4)) { - serialnr->high = (*(str + 1) << 8) | *(str + 2); - serialnr->low = simple_strtoul(str + 3, NULL, 16); - } - } else { - serialnr->high = 0; - serialnr->low = 0; - } -} -#endif - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - return hw_rev | 0x100; -} -#endif - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - char str[64]; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_pio_output(AT91_PIO_PORTA, 29, 1); - at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); - /* Set USART_MODE = 1 (RS485) */ - writel(1, 0xFFF8C004); - - printf("USART0: "); - - if (getenv_f("usart0", str, sizeof(str)) == -1) { - printf("No entry - assuming 1-wire\n"); - /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */ - at91_set_pio_output(AT91_PIO_PORTA, 29, 0); - } else { - if (strcmp(str, "1-wire") == 0) { - printf("%s\n", str); - at91_set_pio_output(AT91_PIO_PORTA, 29, 0); - } else if (strcmp(str, "rs485") == 0) { - printf("%s\n", str); - at91_set_pio_output(AT91_PIO_PORTA, 29, 1); - } else { - printf("Wrong entry - assuming 1-wire "); - printf("(valid values are '1-wire' or 'rs485')\n"); - at91_set_pio_output(AT91_PIO_PORTA, 29, 0); - } - } -#ifdef CONFIG_LCD - printf("Display memory address: 0x%08lX\n", gd->fb_base); -#endif - - return 0; -} -#endif /* CONFIG_MISC_INIT_R */ - -int board_early_init_f(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* enable all clocks */ - writel((1 << ATMEL_ID_PIOA) | - (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOCDE) | - (1 << ATMEL_ID_TWI) | - (1 << ATMEL_ID_SPI0) | -#ifdef CONFIG_LCD - (1 << ATMEL_ID_LCDC) | -#endif - (1 << ATMEL_ID_UHP), - &pmc->pcer); - - at91_seriald_hw_init(); - - /* arch number of OTC570-Board */ - gd->bd->bi_arch_number = MACH_TYPE_OTC570; - - return 0; -} - -int board_init(void) -{ - /* initialize ET1100 Controller */ - otc570_ethercat_hw_init(); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_CMD_NAND - otc570_nand_hw_init(); -#endif -#ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); -#endif -#ifdef CONFIG_MACB - otc570_macb_hw_init(); -#endif -#ifdef CONFIG_AT91_CAN - at91_can_hw_init(); -#endif -#ifdef CONFIG_USB_OHCI_NEW - at91_uhp_hw_init(); -#endif -#ifdef CONFIG_LCD - otc570_lcd_hw_init(); -#endif - return 0; -} diff --git a/board/esd/otc570/partition.c b/board/esd/otc570/partition.c deleted file mode 100644 index b6afafc2399..00000000000 --- a/board/esd/otc570/partition.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2008 - * Ulf Samuelsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ -}; - -/* define the area offsets */ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, -}; diff --git a/configs/otc570_dataflash_defconfig b/configs/otc570_dataflash_defconfig deleted file mode 100644 index c5ff59a5a23..00000000000 --- a/configs/otc570_dataflash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_OTC570=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/otc570_defconfig b/configs/otc570_defconfig deleted file mode 100644 index 8cc55eea8cf..00000000000 --- a/configs/otc570_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_OTC570=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/otc570.h b/include/configs/otc570.h deleted file mode 100644 index 0cada63ef79..00000000000 --- a/include/configs/otc570.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2010-2011 - * Daniel Gorsulowski - * esd electronic system design gmbh - * - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the esd OTC570 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - * Since the linker has to swallow that define, we must use a pure - * hex number here! - */ -#define CONFIG_SYS_TEXT_BASE 0x20002000 - -/* - * since a number of boards are not being listed in linux - * arch/arm/tools/mach-types any more, the mach-types have to be - * defined here - */ -#define MACH_TYPE_OTC570 2166 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ - -/* Misc CPU related */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_MISC_INIT_R /* Call misc_init_r */ - -#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */ -#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ -#define CONFIG_PREBOOT /* enable preboot variable */ - -/* - * Hardware drivers - */ - -/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - -/* general purpose I/O */ -#define CONFIG_AT91_GPIO - -/* Console output */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* LCD */ -#define CONFIG_LCD -#undef CONFIG_SPLASH_SCREEN - -#ifdef CONFIG_LCD -# define LCD_BPP LCD_COLOR8 - -# ifndef CONFIG_SPLASH_SCREEN -# define CONFIG_LCD_LOGO -# define CONFIG_LCD_INFO -# undef CONFIG_LCD_INFO_BELOW_LOGO -# endif /* CONFIG_SPLASH_SCREEN */ - -# undef LCD_TEST_PATTERN -# define CONFIG_SYS_WHITE_ON_BLACK -# define CONFIG_ATMEL_LCD -# define CONFIG_SYS_CONSOLE_IS_IN_ENV -# define CONFIG_OTC570_LCD_BASE (CONFIG_SYS_SDRAM_BASE + 0x03fa5000) -# define CONFIG_CMD_BMP -#endif /* CONFIG_LCD */ - -/* RTC and I2C stuff */ -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -/* Configure data and clock pins for pio */ -# define I2C_INIT { \ - at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ - at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \ -} -# define I2C_SOFT_DECLARATIONS -/* Configure data pin as output */ -# define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) -/* Configure data pin as input */ -# define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0) -/* Read data pin */ -# define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4) -/* Set data pin */ -# define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit) -/* Set clock pin */ -# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit) -# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE - -/* LED */ -#define CONFIG_AT91_LED - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE) - -/* DataFlash */ -#ifdef CONFIG_SYS_USE_DATAFLASH -# define CONFIG_ATMEL_DATAFLASH_SPI -# define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -# define AT91_SPI_CLK 15000000 -# define DATAFLASH_TCSS (0x1a << 16) -# define DATAFLASH_TCHS (0x1 << 24) -#endif - -/* NOR flash is not populated, disable it */ -#define CONFIG_SYS_NO_FLASH - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -# define CONFIG_NAND_ATMEL -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ -# define CONFIG_SYS_NAND_DBW_8 -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_FIT -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_RESET_PHY_R - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT - -/* CAN */ -#define CONFIG_AT91_CAN - -/* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */ - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env in dataflash on CS0 */ -# define CONFIG_ENV_IS_IN_DATAFLASH -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ - 0x8400) -# define CONFIG_ENV_OFFSET 0x4200 -# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ - CONFIG_ENV_OFFSET) -# define CONFIG_ENV_SIZE 0x4200 - -#elif CONFIG_SYS_USE_NANDFLASH - -/* bootstrap + u-boot + env + linux in nandflash */ -# define CONFIG_ENV_IS_IN_NAND 1 -# define CONFIG_ENV_OFFSET 0xC0000 -# define CONFIG_ENV_SIZE 0x20000 - -#endif - -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128*1024, 0x1000) - -#endif -- cgit v1.3.1 From 35782e9cca145603d58aa73c7ab1c1548e409367 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:20 -0600 Subject: arm: Remove palmld board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/palmld/Kconfig | 9 -- board/palmld/MAINTAINERS | 6 -- board/palmld/Makefile | 9 -- board/palmld/palmld.c | 61 ------------ configs/palmld_defconfig | 7 -- include/configs/palmld.h | 245 ----------------------------------------------- 7 files changed, 342 deletions(-) delete mode 100644 board/palmld/Kconfig delete mode 100644 board/palmld/MAINTAINERS delete mode 100644 board/palmld/Makefile delete mode 100644 board/palmld/palmld.c delete mode 100644 configs/palmld_defconfig delete mode 100644 include/configs/palmld.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 186e14fa2f5..cf0c2a759cc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -634,10 +634,6 @@ config TARGET_H2200 bool "Support h2200" select CPU_PXA -config TARGET_PALMLD - bool "Support palmld" - select CPU_PXA - config TARGET_PALMTC bool "Support palmtc" select CPU_PXA @@ -801,7 +797,6 @@ source "board/karo/tx25/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" -source "board/palmld/Kconfig" source "board/palmtc/Kconfig" source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" diff --git a/board/palmld/Kconfig b/board/palmld/Kconfig deleted file mode 100644 index 31112957192..00000000000 --- a/board/palmld/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PALMLD - -config SYS_BOARD - default "palmld" - -config SYS_CONFIG_NAME - default "palmld" - -endif diff --git a/board/palmld/MAINTAINERS b/board/palmld/MAINTAINERS deleted file mode 100644 index 7d21b7b3ebc..00000000000 --- a/board/palmld/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PALMLD BOARD -M: Marek Vasut -S: Maintained -F: board/palmld/ -F: include/configs/palmld.h -F: configs/palmld_defconfig diff --git a/board/palmld/Makefile b/board/palmld/Makefile deleted file mode 100644 index ea93ca88e23..00000000000 --- a/board/palmld/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Palm LifeDrive Support -# -# Copyright (C) 2010 Marek Vasut -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := palmld.o diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c deleted file mode 100644 index fee4dcd7b36..00000000000 --- a/board/palmld/palmld.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Palm LifeDrive Support - * - * Copyright (C) 2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of PalmLD */ - gd->bd->bi_arch_number = MACH_TYPE_PALMLD; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Set PWM for LCD */ - writel(0x7, PWM_CTRL0); - writel(0x16c, PWM_PERVAL0); - writel(0x11a, PWM_PWDUTY0); - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; -} diff --git a/configs/palmld_defconfig b/configs/palmld_defconfig deleted file mode 100644 index 354071ac6f1..00000000000 --- a/configs/palmld_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_PALMLD=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="$ " diff --git a/include/configs/palmld.h b/include/configs/palmld.h deleted file mode 100644 index ec48c14acae..00000000000 --- a/include/configs/palmld.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Palm LifeDrive configuration file - * - * Copyright (C) 2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_PALMLD 1 /* Palm LifeDrive board */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_BOOTCOMMAND \ - "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x0x60000; " \ - "fi; " -#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 9600 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_IDE -#define CONFIG_LCD -#define CONFIG_PXA_LCD - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_LQ038J7DH53 -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x4000 - -/* - * IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x10 -#define CONFIG_SYS_ATA_REG_OFFSET 0x10 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x10 - -#define CONFIG_SYS_ATA_STRIDE 1 -#endif - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012 -#define CONFIG_SYS_GAFR1_L_VAL 0x69988056 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa -#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x01040001 -#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c -#define CONFIG_SYS_GAFR3_U_VAL 0x00000009 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0xc26b0000 -#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93 -#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff -#define CONFIG_SYS_GPDR3_VAL 0x006ff38d -#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee -#define CONFIG_SYS_GPSR1_VAL 0x03affdae -#define CONFIG_SYS_GPSR2_VAL 0x07554000 -#define CONFIG_SYS_GPSR3_VAL 0x01bc0785 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x01ffffff -#define CONFIG_SYS_CCCR 0x02000210 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 -#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 -#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 -#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd -#define CONFIG_SYS_MDREFR_VAL 0x201fa031 -#define CONFIG_SYS_MDMRS_VAL 0x00320032 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000003 -#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 -#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 -#define CONFIG_SYS_MCATT0_VAL 0x0001c391 -#define CONFIG_SYS_MCATT1_VAL 0x0001c391 -#define CONFIG_SYS_MCIO0_VAL 0x00014611 -#define CONFIG_SYS_MCIO1_VAL 0x0001c391 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 8896325d733ce4ac9ae5fab1594f3ef7ebba49d6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:21 -0600 Subject: arm: Remove palmtc board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 -- board/palmtc/Kconfig | 9 -- board/palmtc/MAINTAINERS | 6 -- board/palmtc/Makefile | 9 -- board/palmtc/palmtc.c | 61 ------------- configs/palmtc_defconfig | 6 -- include/configs/palmtc.h | 219 ----------------------------------------------- 7 files changed, 315 deletions(-) delete mode 100644 board/palmtc/Kconfig delete mode 100644 board/palmtc/MAINTAINERS delete mode 100644 board/palmtc/Makefile delete mode 100644 board/palmtc/palmtc.c delete mode 100644 configs/palmtc_defconfig delete mode 100644 include/configs/palmtc.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf0c2a759cc..ad41ba3a21e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -634,10 +634,6 @@ config TARGET_H2200 bool "Support h2200" select CPU_PXA -config TARGET_PALMTC - bool "Support palmtc" - select CPU_PXA - config TARGET_PALMTREO680 bool "Support palmtreo680" select CPU_PXA @@ -797,7 +793,6 @@ source "board/karo/tx25/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" -source "board/palmtc/Kconfig" source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" diff --git a/board/palmtc/Kconfig b/board/palmtc/Kconfig deleted file mode 100644 index 3eb71988376..00000000000 --- a/board/palmtc/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PALMTC - -config SYS_BOARD - default "palmtc" - -config SYS_CONFIG_NAME - default "palmtc" - -endif diff --git a/board/palmtc/MAINTAINERS b/board/palmtc/MAINTAINERS deleted file mode 100644 index 57b6a22e49b..00000000000 --- a/board/palmtc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PALMTC BOARD -M: Marek Vasut -S: Maintained -F: board/palmtc/ -F: include/configs/palmtc.h -F: configs/palmtc_defconfig diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile deleted file mode 100644 index b4a682d24d9..00000000000 --- a/board/palmtc/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Palm Tungsten|C Support -# -# Copyright (C) 2009-2010 Marek Vasut -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := palmtc.o diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c deleted file mode 100644 index a6207b44e78..00000000000 --- a/board/palmtc/palmtc.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Palm Tungsten|C Support - * - * Copyright (C) 2009-2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* Arch number of Palm Tungsten|C */ - gd->bd->bi_arch_number = MACH_TYPE_PALMTC; - - /* Adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Set PWM for LCD */ - writel(0x5f, PWM_CTRL1); - writel(0x3ff, PWM_PERVAL1); - writel(892, PWM_PWDUTY1); - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} diff --git a/configs/palmtc_defconfig b/configs/palmtc_defconfig deleted file mode 100644 index de617e1804e..00000000000 --- a/configs/palmtc_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_PALMTC=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="$ " diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h deleted file mode 100644 index 81c3f028ff3..00000000000 --- a/include/configs/palmtc.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Palm Tungsten|C configuration file - * - * Copyright (C) 2009-2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */ -#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x80000; " \ - "fi; " -#define CONFIG_BOOTARGS \ - "console=tty0 console=ttyS0,115200" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - * STUART - the lower serial port on Colibri board - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_LCD -#define CONFIG_PXA_LCD - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_ACX517AKN -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 64 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_ADDR 0x40000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x00011004 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008 -#define CONFIG_SYS_GAFR1_L_VAL 0x60888050 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa -#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 -#define CONFIG_SYS_GPCR0_VAL 0x0 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPDR0_VAL 0xcfff8140 -#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3 -#define CONFIG_SYS_GPDR2_VAL 0x0001ffff -#define CONFIG_SYS_GPSR0_VAL 0x00010f8f -#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5 -#define CONFIG_SYS_GPSR2_VAL 0x03fe0800 - -#define CONFIG_SYS_PSSR_VAL PSSR_RDH - -/* Clock setup: - * CKEN[1] - PWM1 ; CKEN[6] - FFUART - * CKEN[12] - MMC ; CKEN[16] - LCD - */ -#define CONFIG_SYS_CKEN 0x00011042 -#define CONFIG_SYS_CCCR 0x00000161 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x800092c2 -#define CONFIG_SYS_MSC1_VAL 0x80008000 -#define CONFIG_SYS_MSC2_VAL 0x80008000 -#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9 -#define CONFIG_SYS_MDREFR_VAL 0x00118018 -#define CONFIG_SYS_MDMRS_VAL 0x00220032 -#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00010e04 -#define CONFIG_SYS_MCIO1_VAL 0x00010e04 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From f6eac00aba2047dad50fb3c95a962d386b326673 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:22 -0600 Subject: arm: Remove polaris and trizepsiv boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass Acked-by: Stefano Babic --- arch/arm/Kconfig | 5 - board/trizepsiv/Kconfig | 9 -- board/trizepsiv/MAINTAINERS | 7 - board/trizepsiv/Makefile | 8 -- board/trizepsiv/conxs.c | 148 --------------------- board/trizepsiv/eeprom.c | 62 --------- configs/polaris_defconfig | 4 - configs/trizepsiv_defconfig | 3 - include/configs/trizepsiv.h | 309 -------------------------------------------- 9 files changed, 555 deletions(-) delete mode 100644 board/trizepsiv/Kconfig delete mode 100644 board/trizepsiv/MAINTAINERS delete mode 100644 board/trizepsiv/Makefile delete mode 100644 board/trizepsiv/conxs.c delete mode 100644 board/trizepsiv/eeprom.c delete mode 100644 configs/polaris_defconfig delete mode 100644 configs/trizepsiv_defconfig delete mode 100644 include/configs/trizepsiv.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ad41ba3a21e..a3a6c6e6b17 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -643,10 +643,6 @@ config TARGET_PXA255_IDP bool "Support pxa255_idp" select CPU_PXA -config TARGET_TRIZEPSIV - bool "Support trizepsiv" - select CPU_PXA - config TARGET_VPAC270 bool "Support vpac270" select CPU_PXA @@ -822,7 +818,6 @@ source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" -source "board/trizepsiv/Kconfig" source "board/technologic/ts4800/Kconfig" source "board/ttcontrol/vision2/Kconfig" source "board/vpac270/Kconfig" diff --git a/board/trizepsiv/Kconfig b/board/trizepsiv/Kconfig deleted file mode 100644 index 56b255709a2..00000000000 --- a/board/trizepsiv/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_TRIZEPSIV - -config SYS_BOARD - default "trizepsiv" - -config SYS_CONFIG_NAME - default "trizepsiv" - -endif diff --git a/board/trizepsiv/MAINTAINERS b/board/trizepsiv/MAINTAINERS deleted file mode 100644 index ba48c2e2e0d..00000000000 --- a/board/trizepsiv/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -TRIZEPSIV BOARD -M: Stefano Babic -S: Maintained -F: board/trizepsiv/ -F: include/configs/trizepsiv.h -F: configs/polaris_defconfig -F: configs/trizepsiv_defconfig diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile deleted file mode 100644 index c49686fc608..00000000000 --- a/board/trizepsiv/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := conxs.o eeprom.o diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c deleted file mode 100644 index 1ddf05dcdd4..00000000000 --- a/board/trizepsiv/conxs.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefano Babic, DENX Gmbh, sbabic@denx.de - * - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ - -extern struct serial_device serial_ffuart_device; -extern struct serial_device serial_btuart_device; -extern struct serial_device serial_stuart_device; - -#if CONFIG_MK_POLARIS -#define BOOT_CONSOLE "serial_stuart" -#else -#define BOOT_CONSOLE "serial_ffuart" -#endif -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_usb_init(int index, enum usb_init_type init) -{ - writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (readl(UHCHR) & UHCHR_FSBIR) - ; - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA); - writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - - return; -} - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of ConXS Board */ - gd->bd->bi_arch_number = 776; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa000003c; - - return 0; -} - -int board_late_init(void) -{ - char *console=getenv("boot_console"); - - if ((console == NULL) || (strcmp(console,"serial_btuart") && - strcmp(console,"serial_stuart") && - strcmp(console,"serial_ffuart"))) { - console = BOOT_CONSOLE; - } - setenv("stdout",console); - setenv("stdin", console); - setenv("stderr",console); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c deleted file mode 100644 index 1318edc5d63..00000000000 --- a/board/trizepsiv/eeprom.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int i; - u8 data[2]; - - for (i=0; i < 0x40; i++) { - if (!(i % 0x10)) - printf("\n%08x:", i); - dm9000_read_srom_word(i, data); - printf(" %02x%02x", data[1], data[0]); - } - printf ("\n"); - return (0); -} - -static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int offset,value; - - if (argc < 4) - return cmd_usage(cmdtp); - - offset=simple_strtoul(argv[2],NULL,16); - value=simple_strtoul(argv[3],NULL,16); - if (offset > 0x40) { - printf("Wrong offset : 0x%x\n",offset); - return cmd_usage(cmdtp); - } - dm9000_write_srom_word(offset, value); - return (0); -} - -int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - if (argc < 2) - return cmd_usage(cmdtp); - - if (strcmp (argv[1],"read") == 0) - return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); - else if (strcmp (argv[1],"write") == 0) - return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); - else - return cmd_usage(cmdtp); -} - -U_BOOT_CMD( - dm9000ee,4,1,do_dm9000_eeprom, - "Read/Write eeprom connected to Ethernet Controller", - "\ndm9000ee write \n" - "\tdm9000ee read \n" - "\tword:\t\t00-02 : MAC Address\n" - "\t\t\t03-07 : DM9000 Configuration\n" - "\t\t\t08-63 : User data" -); diff --git a/configs/polaris_defconfig b/configs/polaris_defconfig deleted file mode 100644 index e2095669eab..00000000000 --- a/configs/polaris_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TRIZEPSIV=y -CONFIG_SYS_EXTRA_OPTIONS="POLARIS" -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/trizepsiv_defconfig b/configs/trizepsiv_defconfig deleted file mode 100644 index 18879837fba..00000000000 --- a/configs/trizepsiv_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TRIZEPSIV=y -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h deleted file mode 100644 index 40c8d718d83..00000000000 --- a/include/configs/trizepsiv.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefano Babic, DENX Gmbh, sbabic@denx.de - * - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the LUBBOCK board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */ - -#define CONFIG_MMC 1 -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -#define RTC - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ -#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ -#define CONFIG_STUART 1 /* we use STUART on Conxs */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_DOS_PARTITION 1 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_SERVERIP 192.168.1.99 -#define CONFIG_BOOTCOMMAND "run boot_flash" -#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ - " rw root=/dev/ram initrd=0xa0800000,5m" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "program_boot_mmc=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_mmc=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_mmc=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa0030000 uzImage && " \ - "fatload mmc 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "boot_flash=" \ - "cp.b 0x1c0000 0xa0800000 0x500000; " \ - "bootm 0x40000\0" \ - -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -/* #define CONFIG_INITRD_TAG 1 */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00018000 -#define CONFIG_SYS_GPSR1_VAL 0x00000000 -#define CONFIG_SYS_GPSR2_VAL 0x400dc000 -#define CONFIG_SYS_GPSR3_VAL 0x00000000 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x00018000 -#define CONFIG_SYS_GPDR1_VAL 0x00028801 -#define CONFIG_SYS_GPDR2_VAL 0x520dc000 -#define CONFIG_SYS_GPDR3_VAL 0x0001E000 -#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00000013 -#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A -#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000003 -#define CONFIG_SYS_GAFR3_U_VAL 0x00002401 -#define CONFIG_SYS_GRER0_VAL 0x00000000 -#define CONFIG_SYS_GRER1_VAL 0x00000000 -#define CONFIG_SYS_GRER2_VAL 0x00000000 -#define CONFIG_SYS_GRER3_VAL 0x00000000 - -#define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER3_VAL 0x00000020 - -#if CONFIG_POLARIS -#define CONFIG_SYS_GFER0_VAL 0x00000001 -#define CONFIG_SYS_GFER2_VAL 0x00200000 -#else -#define CONFIG_SYS_GFER0_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 -#endif - -#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */ -#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */ - -/* - * Memory settings - */ - -#define CONFIG_SYS_MSC0_VAL 0x4df84df0 -#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4 -#if CONFIG_POLARIS -#define CONFIG_SYS_MSC2_VAL 0xa2697ff8 -#else -#define CONFIG_SYS_MSC2_VAL 0xa26936d4 -#endif -#define CONFIG_SYS_MDCNFG_VAL 0x880009C9 -#define CONFIG_SYS_MDREFR_VAL 0x20ca201e -#define CONFIG_SYS_MDMRS_VAL 0x00220022 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00004204 -#define CONFIG_SYS_MCMEM1_VAL 0x00010204 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x0000c108 - -#define CONFIG_DRIVER_DM9000 1 - -#if CONFIG_POLARIS -#define CONFIG_DM9000_BASE 0x0C800000 -#else -#define CONFIG_DM9000_BASE 0x08000000 -#endif - -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) - -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv" -#define CONFIG_USB_STORAGE 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 - -/* - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* write flash less slowly */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* Unlock to be used with Intel chips */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/* Flash environment locations */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 79d19734a9e2dbd3fc414512227a24f60cd3572a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:23 -0600 Subject: arm: Remove portuxg20, stamp9g20 boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/mach-at91/Kconfig | 5 - board/taskit/stamp9g20/Kconfig | 12 -- board/taskit/stamp9g20/MAINTAINERS | 7 -- board/taskit/stamp9g20/Makefile | 17 --- board/taskit/stamp9g20/led.c | 122 ------------------- board/taskit/stamp9g20/stamp9g20.c | 159 ------------------------ configs/portuxg20_defconfig | 10 -- configs/stamp9g20_defconfig | 11 -- include/configs/stamp9g20.h | 244 ------------------------------------- 9 files changed, 587 deletions(-) delete mode 100644 board/taskit/stamp9g20/Kconfig delete mode 100644 board/taskit/stamp9g20/MAINTAINERS delete mode 100644 board/taskit/stamp9g20/Makefile delete mode 100644 board/taskit/stamp9g20/led.c delete mode 100644 board/taskit/stamp9g20/stamp9g20.c delete mode 100644 configs/portuxg20_defconfig delete mode 100644 configs/stamp9g20_defconfig delete mode 100644 include/configs/stamp9g20.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index cb2994c2817..26ba5ace03a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -43,10 +43,6 @@ config TARGET_PM9263 bool "Ronetix pm9263 board" select CPU_ARM926EJS -config TARGET_STAMP9G20 - bool "Support stamp9g20" - select CPU_ARM926EJS - config TARGET_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK board" select CPU_ARM926EJS @@ -147,6 +143,5 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -source "board/taskit/stamp9g20/Kconfig" endif diff --git a/board/taskit/stamp9g20/Kconfig b/board/taskit/stamp9g20/Kconfig deleted file mode 100644 index 1121dacfc70..00000000000 --- a/board/taskit/stamp9g20/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_STAMP9G20 - -config SYS_BOARD - default "stamp9g20" - -config SYS_VENDOR - default "taskit" - -config SYS_CONFIG_NAME - default "stamp9g20" - -endif diff --git a/board/taskit/stamp9g20/MAINTAINERS b/board/taskit/stamp9g20/MAINTAINERS deleted file mode 100644 index a91c1960cb5..00000000000 --- a/board/taskit/stamp9g20/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -STAMP9G20 BOARD -M: Markus Hubig -S: Maintained -F: board/taskit/stamp9g20/ -F: include/configs/stamp9g20.h -F: configs/portuxg20_defconfig -F: configs/stamp9g20_defconfig diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile deleted file mode 100644 index d015e0f7401..00000000000 --- a/board/taskit/stamp9g20/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop -# Lead Tech Design -# -# (C) Copyright 2012 -# Markus Hubig -# IMKO GmbH -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += stamp9g20.o -obj-y += led.o diff --git a/board/taskit/stamp9g20/led.c b/board/taskit/stamp9g20/led.c deleted file mode 100644 index c5831258bdf..00000000000 --- a/board/taskit/stamp9g20/led.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * (C) Copyright 2009 - * Eric Benard - * - * (C) Copyright 2012 - * Markus Hubig - * IMKO GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -static unsigned int saved_state[3] = {STATUS_LED_OFF, - STATUS_LED_OFF, STATUS_LED_OFF}; - -void coloured_LED_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable the clock */ - writel(ATMEL_ID_PIOC, &pmc->pcer); - - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); - - at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_YELLOW_LED, 0); -} - -void red_led_on(void) -{ - at91_set_gpio_value(CONFIG_RED_LED, 1); - saved_state[STATUS_LED_RED] = STATUS_LED_ON; -} - -void red_led_off(void) -{ - at91_set_gpio_value(CONFIG_RED_LED, 0); - saved_state[STATUS_LED_RED] = STATUS_LED_OFF; -} - -void green_led_on(void) -{ - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - saved_state[STATUS_LED_GREEN] = STATUS_LED_ON; -} - -void green_led_off(void) -{ - at91_set_gpio_value(CONFIG_GREEN_LED, 0); - saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF; -} - -void yellow_led_on(void) -{ - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); - saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON; -} - -void yellow_led_off(void) -{ - at91_set_gpio_value(CONFIG_YELLOW_LED, 0); - saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF; -} - -void __led_init(led_id_t mask, int state) -{ - __led_set(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) - red_led_off(); - else - red_led_on(); - - } else if (STATUS_LED_GREEN == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN]) - green_led_off(); - else - green_led_on(); - - } else if (STATUS_LED_YELLOW == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW]) - yellow_led_off(); - else - yellow_led_on(); - } -} - -void __led_set(led_id_t mask, int state) -{ - if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == state) - red_led_on(); - else - red_led_off(); - - } else if (STATUS_LED_GREEN == mask) { - if (STATUS_LED_ON == state) - green_led_on(); - else - green_led_off(); - - } else if (STATUS_LED_YELLOW == mask) { - if (STATUS_LED_ON == state) - yellow_led_on(); - else - yellow_led_off(); - } -} diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c deleted file mode 100644 index 27cdf77f012..00000000000 --- a/board/taskit/stamp9g20/stamp9g20.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Achim Ehrlich - * taskit GmbH - * - * (C) Copyright 2012- - * Markus Hubig - * IMKO GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MACB -# include -# include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static void stamp9G20_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - /* Assign CS3 to NAND/SmartMedia Interface */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} - -#ifdef CONFIG_MACB -static void stamp9G20_macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ - at91_set_gpio_output(AT91_PIN_PA26, 0); - - /* - * Disable pull-up on: - * RXDV (PA17) => PHY normal mode (not Test mode) - * ERX0 (PA14) => PHY ADDR0 - * ERX1 (PA15) => PHY ADDR1 - * ERX2 (PA25) => PHY ADDR2 - * ERX3 (PA26) => PHY ADDR3 - * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA18) | - pin_to_mask(AT91_PIN_PA28), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA18) | - pin_to_mask(AT91_PIN_PA28), - &pioa->puer); - - /* Initialize EMAC=MACB hardware */ - at91_macb_hw_init(); -} -#endif /* CONFIG_MACB */ - -int board_early_init_f(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), &pmc->pcer); - - return 0; -} - -int board_postclk_init(void) -{ - /* - * Initialize the serial interface here, because be need a running - * timer to set PC9 to high and wait for some time to enable the - * level converter of the RS232 interface on the PortuxG20 board. - */ - -#ifdef CONFIG_PORTUXG20 - at91_set_gpio_output(AT91_PIN_PC9, 1); - mdelay(1); -#endif - at91_seriald_hw_init(); - - return 0; -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - stamp9G20_nand_hw_init(); -#ifdef CONFIG_MACB - stamp9G20_macb_hw_init(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#ifdef CONFIG_MACB -int board_eth_init(bd_t *bis) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); -} -#endif /* CONFIG_MACB */ diff --git a/configs/portuxg20_defconfig b/configs/portuxg20_defconfig deleted file mode 100644 index 1e8344f00a4..00000000000 --- a/configs/portuxg20_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_STAMP9G20=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20" -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/stamp9g20_defconfig b/configs/stamp9g20_defconfig deleted file mode 100644 index 40d6232b91e..00000000000 --- a/configs/stamp9g20_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_STAMP9G20=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot> " diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h deleted file mode 100644 index 87df70bdacf..00000000000 --- a/include/configs/stamp9g20.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2010 - * Achim Ehrlich - * taskit GmbH - * - * (C) Copyright 2012 - * Markus Hubig - * IMKO GmbH - * - * Configuation settings for the stamp9g20 CPU module. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot - * program. Since the linker has to swallow that define, we must use a pure - * hex number here! - */ -#define CONFIG_SYS_TEXT_BASE 0x23f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ - -/* misc settings */ -#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ -#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ -#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */ -#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */ -#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ - -/* setting board specific options */ -#ifdef CONFIG_PORTUXG20 -# define CONFIG_MACH_TYPE MACH_TYPE_PORTUXG20 -# define CONFIG_MACB -#else -# define CONFIG_MACH_TYPE MACH_TYPE_STAMP9G20 -#endif - -/* - * SDRAM: 1 bank, 64 MB, base address 0x20000000 - * Already initialized before u-boot gets started. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 << 20) - -/* - * Perform a SDRAM Memtest from the start of SDRAM - * till the beginning of the U-Boot position in RAM. - */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000) - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above that - * address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash settings */ -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO /* enable the GPIO features */ -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -/* LED configuration */ -#define CONFIG_STATUS_LED -#define CONFIG_BOARD_SPECIFIC_LED - -/* The LED PINs */ -#define CONFIG_RED_LED AT91_PIN_PC5 -#define CONFIG_GREEN_LED AT91_PIN_PC4 -#define CONFIG_YELLOW_LED AT91_PIN_PC10 - -#define STATUS_LED_RED 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_YELLOW 2 - -/* Red LED */ -#define STATUS_LED_BIT STATUS_LED_RED -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) - -/* Green LED */ -#define STATUS_LED_BIT1 STATUS_LED_GREEN -#define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) - -/* Yellow LED */ -#define STATUS_LED_BIT2 STATUS_LED_YELLOW -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) - -/* Boot status LED */ -#define STATUS_LED_BOOT STATUS_LED_GREEN - -/* - * Ethernet configuration - * - * PortuxG20 has always ethernet but for Stamp9G20 you - * can enable it here if your baseboard features ethernet. - */ - -#define CONFIG_MACB -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 - -#ifdef CONFIG_MACB -# define CONFIG_RMII /* use reduced MII inteface */ -# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* BOOTP and DHCP options */ -# define CONFIG_BOOTP_BOOTFILESIZE -# define CONFIG_BOOTP_BOOTPATH -# define CONFIG_BOOTP_GATEWAY -# define CONFIG_BOOTP_HOSTNAME -# define CONFIG_NFSBOOTCOMMAND \ - "setenv autoload yes; setenv autoboot yes; " \ - "setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ - "dhcp" -#endif /* CONFIG_MACB */ - -/* Enable the watchdog */ -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_HW_WATCHDOG - -/* USB configuration */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* General Boot Parameter */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -/* - * RAM Memory address where to put the - * Linux Kernel befor starting. - */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -/* - * The NAND Flash partitions: - * ========================================== - * 0x0000000-0x001ffff -> 128k, bootstrap - * 0x0020000-0x005ffff -> 256k, u-boot - * 0x0060000-0x007ffff -> 128k, env1 - * 0x0080000-0x009ffff -> 128k, env2 (backup) - * 0x0100000-0x06fffff -> 6M, kernel - * 0x0700000-0x8000000 -> 121M, RootFS - */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET ((128 + 256) << 10) -#define CONFIG_ENV_OFFSET_REDUND ((128 + 256 + 128) << 10) -#define CONFIG_ENV_SIZE (128 << 10) - -/* - * Predefined environment variables. - * Usefull to define some easy to use boot commands. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - \ - "basicargs=console=ttyS0,115200\0" \ - \ - "mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro," \ - "256k(uboot)ro,128k(env1)ro," \ - "128k(env2)ro,6M(linux),-(root)rw\0" \ - \ - "flashboot=setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/mtdblock5 rootfstype=jffs2; " \ - "nand read 0x22000000 0x100000 0x600000; " \ - "bootm 22000000\0" \ - \ - "sdboot=setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/mmcblk0p1 rootwait; " \ - "nand read 0x22000000 0x100000 0x600000; " \ - "bootm 22000000" - -/* Command line & features configuration */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_LED - -#ifdef CONFIG_MACB -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -#endif /* CONFIG_MACB */ - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 49d8899ba9c26335e4a12e01c18028fc5e40c796 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:24 -0600 Subject: arm: Remove pxa255_idp, zipitz2 boards These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 10 -- board/pxa255_idp/Kconfig | 9 - board/pxa255_idp/MAINTAINERS | 6 - board/pxa255_idp/Makefile | 8 - board/pxa255_idp/README | 11 -- board/pxa255_idp/idp_notes.txt | 46 ----- board/pxa255_idp/pxa_idp.c | 140 ---------------- board/pxa255_idp/pxa_reg_calcs.out | 119 ------------- board/pxa255_idp/pxa_reg_calcs.py | 298 --------------------------------- board/zipitz2/Kconfig | 9 - board/zipitz2/MAINTAINERS | 6 - board/zipitz2/Makefile | 10 -- board/zipitz2/zipitz2.c | 202 ---------------------- configs/pxa255_idp_defconfig | 3 - configs/zipitz2_defconfig | 7 - include/configs/pxa255_idp.h | 335 ------------------------------------- include/configs/zipitz2.h | 238 -------------------------- 17 files changed, 1457 deletions(-) delete mode 100644 board/pxa255_idp/Kconfig delete mode 100644 board/pxa255_idp/MAINTAINERS delete mode 100644 board/pxa255_idp/Makefile delete mode 100644 board/pxa255_idp/README delete mode 100644 board/pxa255_idp/idp_notes.txt delete mode 100644 board/pxa255_idp/pxa_idp.c delete mode 100644 board/pxa255_idp/pxa_reg_calcs.out delete mode 100644 board/pxa255_idp/pxa_reg_calcs.py delete mode 100644 board/zipitz2/Kconfig delete mode 100644 board/zipitz2/MAINTAINERS delete mode 100644 board/zipitz2/Makefile delete mode 100644 board/zipitz2/zipitz2.c delete mode 100644 configs/pxa255_idp_defconfig delete mode 100644 configs/zipitz2_defconfig delete mode 100644 include/configs/pxa255_idp.h delete mode 100644 include/configs/zipitz2.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a3a6c6e6b17..e96e902ffd1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -639,10 +639,6 @@ config TARGET_PALMTREO680 select CPU_PXA select SUPPORT_SPL -config TARGET_PXA255_IDP - bool "Support pxa255_idp" - select CPU_PXA - config TARGET_VPAC270 bool "Support vpac270" select CPU_PXA @@ -652,10 +648,6 @@ config TARGET_XAENIAX bool "Support xaeniax" select CPU_PXA -config TARGET_ZIPITZ2 - bool "Support zipitz2" - select CPU_PXA - config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -792,7 +784,6 @@ source "board/olimex/mx23_olinuxino/Kconfig" source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" -source "board/pxa255_idp/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" @@ -825,7 +816,6 @@ source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" -source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/board/pxa255_idp/Kconfig b/board/pxa255_idp/Kconfig deleted file mode 100644 index 544831199d4..00000000000 --- a/board/pxa255_idp/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PXA255_IDP - -config SYS_BOARD - default "pxa255_idp" - -config SYS_CONFIG_NAME - default "pxa255_idp" - -endif diff --git a/board/pxa255_idp/MAINTAINERS b/board/pxa255_idp/MAINTAINERS deleted file mode 100644 index 24d723602c9..00000000000 --- a/board/pxa255_idp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PXA255_IDP BOARD -M: Cliff Brake -S: Maintained -F: board/pxa255_idp/ -F: include/configs/pxa255_idp.h -F: configs/pxa255_idp_defconfig diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile deleted file mode 100644 index 59d696741da..00000000000 --- a/board/pxa255_idp/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pxa_idp.o diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README deleted file mode 100644 index 0cc2f2ae33e..00000000000 --- a/board/pxa255_idp/README +++ /dev/null @@ -1,11 +0,0 @@ -Tested: - -- MMC -- Ethernet -- BL console (on serial port connector J5) -- flash support - -Todo: - -- display support -- PCMCIA support diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt deleted file mode 100644 index 47467485fe8..00000000000 --- a/board/pxa255_idp/idp_notes.txt +++ /dev/null @@ -1,46 +0,0 @@ -Notes on the Vibren PXA255 IDP. - -Chip select usage: - -CS0 - flash -CS1 - alt flash (Mdoc or main flash) -CS2 - high speed expansion bus -CS3 - Media Q, low speed exp bus -CS4 - low speed exp bus -CS5 - low speed exp bus - - IDE: offset 0x03000000 (abs: 0x17000000) - - Eth: offset 0x03400000 (abs: 0x17400000) - - core voltage latch: offset 0x03800000 (abs: 0x17800000) - - CPLD: offset 0x03C00000 (abs: 0x17C00000) - -PCMCIA Power control - -MAX1602EE w/ code pulled high (Cirrus code) -vx = 5v -vy = 3v - - Bit pattern - PWR 3,2,1,0 -vcc vpp A1VCC A0VCC A1VPP A0VPP -===================================================== -0 0 0 0 0 0 0x0 -3 (vy) 0 1 0 1 1 0xB -3 (vy) 3 (vy) 1 0 0 1 0x9 -3 (vy) 12(12in) 1 0 1 0 0xA -5 (vx) 0 0 1 1 1 0x7 -5 (vx) 5 (vx) 0 1 0 1 0x5 -5 (vx 12(12in) 0 1 1 0 0x6 - -Display power sequencing: - -- VDD applied -- within 1sec, activate scanning signals -- wait at least 50mS - scanning signals must be active before activating DISP - -Signal mapping: -Schematic LV8V31 signal name -========================================= -LCD_ENAVLCD DISP -LCD_PWR Applies VDD to board - -Both of the above signals are controlled by the CPLD diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c deleted file mode 100644 index 197ff3ef31d..00000000000 --- a/board/pxa255_idp/pxa_idp.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2004 - * BEC Systems - * Cliff Brake - * Support for Accelent/Vibren PXA255 IDP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* turn on serial ports */ - *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13; - - /* set PWM for LCD */ - /* a value that works is 60Hz, 77% duty cycle */ - writel(readl(CKEN) | CKEN0_PWM0, CKEN); - writel(0x3f, PWM_CTRL0); - writel(0x3ff, PWM_PERVAL0); - writel(792, PWM_PWDUTY0); - - /* clear reset to AC97 codec */ - writel(readl(CKEN) | CKEN2_AC97, CKEN); - writel(GCR_COLD_RST, GCR); - - /* enable LCD backlight */ - /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */ - - /* test display */ - /* lcd_puts("This is a test\nTest #2\n"); */ - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef DEBUG_BLINKC_ENABLE - -void delay_c(void) -{ - /* reset OSCR to 0 */ - writel(0, OSCR); - while (readl(OSCR) > 0x10000) - ; - - while (readl(OSCR) < 0xd4000) - ; -} - -void blink_c(void) -{ - int led_bit = (1<<10); - - writel(led_bit, GPDR0); - writel(led_bit, GPCR0); - delay_c(); - writel(led_bit, GPSR0); - delay_c(); - writel(led_bit, GPCR0); -} - -int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("IDPCMD started\n"); - return 0; -} - -U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd, - "custom IDP command", - "no args at this time" -); - -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out deleted file mode 100644 index 39295fb6796..00000000000 --- a/board/pxa255_idp/pxa_reg_calcs.out +++ /dev/null @@ -1,119 +0,0 @@ -gafr0_l: 0x80001005 -gafr0_u: 0xa5128012 -gafr1_l: 0x699a9558 -gafr1_u: 0xaaa5aa6a -gafr2_l: 0xaaaaaaaa -gafr2_u: 0x2 -gpcr0: 0x1800400 -gpcr1: 0x0 -gpcr2: 0x0 -gpdr0: 0xc1818440 -gpdr1: 0xfcffab82 -gpdr2: 0x1ffff -gpsr0: 0x8000 -gpsr1: 0x3f0002 -gpsr2: 0x1c000 - - -#define CONFIG_SYS_GAFR0_L_VAL 0x80001005 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 -#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x2 -#define CONFIG_SYS_GPCR0_VAL 0x1800400 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPDR0_VAL 0xc1818440 -#define CONFIG_SYS_GPDR1_VAL 0xfcffab82 -#define CONFIG_SYS_GPDR2_VAL 0x1ffff -#define CONFIG_SYS_GPSR0_VAL 0x8000 -#define CONFIG_SYS_GPSR1_VAL 0x3f0002 -#define CONFIG_SYS_GPSR2_VAL 0x1c000 - - -GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET# -GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET# -GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA -GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ# -GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH -GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH# -GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK -GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD# -GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD# -GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD# -GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED -GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK -GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK -GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT -GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ -GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1# -GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0 -GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB -GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY -GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O# -GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0 -GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI -GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O# -GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK -GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM -GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD -GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD -GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK -GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK -GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0 -GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT -GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC -GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1 -GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5# -GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD -GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS -GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD -GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR -GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI -GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD -GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR -GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS -GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD -GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD -GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS -GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS -GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD -GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD -GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE# -GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE# -GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR# -GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW# -GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1# -GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2# -GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL -GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG# -GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT# -GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16# -GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0 -GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1 -GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2 -GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3 -GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4 -GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5 -GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6 -GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7 -GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8 -GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9 -GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10 -GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11 -GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12 -GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13 -GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14 -GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15 -GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK -GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK -GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK -GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS -GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2# -GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3# -GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4# -GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc= -GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc= -GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc= -GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc= diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py deleted file mode 100644 index 4a721d1b046..00000000000 --- a/board/pxa255_idp/pxa_reg_calcs.py +++ /dev/null @@ -1,298 +0,0 @@ -#!/usr/bin/python - -# (C) Copyright 2004 -# BEC Systems -# Cliff Brake - -# SPDX-License-Identifier: GPL-2.0+ - -# calculations for PXA255 registers - -class gpio: - dir = '0' - set = '0' - clr = '0' - alt = '0' - desc = '' - - def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): - self.dir = dir - self.set = set - self.clr = clr - self.alt = alt - self.desc = desc - - -# the following is a dictionary of all GPIOs in the system -# the key is the GPIO number - - -pxa255_alt_func = { - 0: ['gpio', 'none', 'none', 'none'], - 1: ['gpio', 'gpio reset', 'none', 'none'], - 2: ['gpio', 'none', 'none', 'none'], - 3: ['gpio', 'none', 'none', 'none'], - 4: ['gpio', 'none', 'none', 'none'], - 5: ['gpio', 'none', 'none', 'none'], - 6: ['gpio', 'MMC clk', 'none', 'none'], - 7: ['gpio', '48MHz clock', 'none', 'none'], - 8: ['gpio', 'MMC CS0', 'none', 'none'], - 9: ['gpio', 'MMC CS1', 'none', 'none'], - 10: ['gpio', 'RTC Clock', 'none', 'none'], - 11: ['gpio', '3.6MHz', 'none', 'none'], - 12: ['gpio', '32KHz', 'none', 'none'], - 13: ['gpio', 'none', 'MBGNT', 'none'], - 14: ['gpio', 'MBREQ', 'none', 'none'], - 15: ['gpio', 'none', 'nCS_1', 'none'], - 16: ['gpio', 'none', 'PWM0', 'none'], - 17: ['gpio', 'none', 'PWM1', 'none'], - 18: ['gpio', 'RDY', 'none', 'none'], - 19: ['gpio', 'DREQ[1]', 'none', 'none'], - 20: ['gpio', 'DREQ[0]', 'none', 'none'], - 21: ['gpio', 'none', 'none', 'none'], - 22: ['gpio', 'none', 'none', 'none'], - 23: ['gpio', 'none', 'SSP SCLK', 'none'], - 24: ['gpio', 'none', 'SSP SFRM', 'none'], - 25: ['gpio', 'none', 'SSP TXD', 'none'], - 26: ['gpio', 'SSP RXD', 'none', 'none'], - 27: ['gpio', 'SSP EXTCLK', 'none', 'none'], - 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'], - 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'], - 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'], - 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'], - 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'], - 33: ['gpio', 'none', 'nCS_5', 'none'], - 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'], - 35: ['gpio', 'FF CTS', 'none', 'none'], - 36: ['gpio', 'FF DCD', 'none', 'none'], - 37: ['gpio', 'FF DSR', 'none', 'none'], - 38: ['gpio', 'FF RI', 'none', 'none'], - 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'], - 40: ['gpio', 'none', 'FF DTR', 'none'], - 41: ['gpio', 'none', 'FF RTS', 'none'], - 42: ['gpio', 'BT RXD', 'none', 'HW RXD'], - 43: ['gpio', 'none', 'BT TXD', 'HW TXD'], - 44: ['gpio', 'BT CTS', 'none', 'HW CTS'], - 45: ['gpio', 'none', 'BT RTS', 'HW RTS'], - 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'], - 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'], - 48: ['gpio', 'HW TXD', 'nPOE', 'none'], - 49: ['gpio', 'HW RXD', 'nPWE', 'none'], - 50: ['gpio', 'HW CTS', 'nPIOR', 'none'], - 51: ['gpio', 'nPIOW', 'HW RTS', 'none'], - 52: ['gpio', 'none', 'nPCE[1]', 'none'], - 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'], - 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'], - 55: ['gpio', 'none', 'nPREG', 'none'], - 56: ['gpio', 'nPWAIT', 'none', 'none'], - 57: ['gpio', 'nIOIS16', 'none', 'none'], - 58: ['gpio', 'none', 'LDD[0]', 'none'], - 59: ['gpio', 'none', 'LDD[1]', 'none'], - 60: ['gpio', 'none', 'LDD[2]', 'none'], - 61: ['gpio', 'none', 'LDD[3]', 'none'], - 62: ['gpio', 'none', 'LDD[4]', 'none'], - 63: ['gpio', 'none', 'LDD[5]', 'none'], - 64: ['gpio', 'none', 'LDD[6]', 'none'], - 65: ['gpio', 'none', 'LDD[7]', 'none'], - 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'], - 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'], - 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'], - 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'], - 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'], - 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'], - 72: ['gpio', '32 KHz', 'LDD[14]', 'none'], - 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'], - 74: ['gpio', 'none', 'LCD_FCLK', 'none'], - 75: ['gpio', 'none', 'LCD_LCLK', 'none'], - 76: ['gpio', 'none', 'LCD_PCLK', 'none'], - 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'], - 78: ['gpio', 'none', 'nCS_2', 'none'], - 79: ['gpio', 'none', 'nCS_3', 'none'], - 80: ['gpio', 'none', 'nCS_4', 'none'], - 81: ['gpio', 'NSSPSCLK', 'none', 'none'], - 82: ['gpio', 'NSSPSFRM', 'none', 'none'], - 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], - 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], -} - - -#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): - -gpio_list = [] - -for i in range(0,85): - gpio_list.append(gpio()) - -#chip select GPIOs -gpio_list[18] = gpio(0, 0, 0, 1, 'RDY') -gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#') -gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#') -gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#') -gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#') -gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#') -gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#') -gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI') -gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#') -gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') -gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') -gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB') -gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0') - -# PCMCIA stuff -gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#') -gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#') -gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#') -gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL') -gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#') -gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#') -gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#') -gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#') -gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#') -gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#') - -# SSP port -gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD') -gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD') -gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM') -gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK') -gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK') - -# audio codec -gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1') -gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC') -gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT') -gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0') -gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK') - -# serial ports -gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD') -gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD') -gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS') -gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS') -gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR') -gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR') -gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI') -gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD') - -gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD') -gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD') -gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS') -gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS') - -gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD') -gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD') - -# misc GPIO signals -gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ') -gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT') -gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK') -gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK') -gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED') -gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#') -gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#') -gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#') -gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK') -gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#') -gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH') -gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#') -gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA') -gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#') -gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#') - -# LCD GPIOs -gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0') -gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1') -gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2') -gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3') -gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4') -gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5') -gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6') -gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7') -gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8') -gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9') -gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10') -gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11') -gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12') -gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13') -gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14') -gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15') -gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK') -gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK') -gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK') -gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS') - -# calculate registers -pxa_regs = { - 'gpdr0':0, 'gpdr1':0, 'gpdr2':0, - 'gpsr0':0, 'gpsr1':0, 'gpsr2':0, - 'gpcr0':0, 'gpcr1':0, 'gpcr2':0, - 'gafr0_l':0, 'gafr0_u':0, - 'gafr1_l':0, 'gafr1_u':0, - 'gafr2_l':0, 'gafr2_u':0, -} - -# U-boot define names -uboot_reg_names = { - 'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL', - 'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL', - 'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL', - 'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL', - 'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL', - 'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL', -} - -# bit mappings - -bit_mappings = [ - -{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} }, -{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} }, -{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} }, -{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} }, -{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} }, -{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} }, -{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} }, -{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} }, -{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} }, - -] - -def stuff_bits(bit_mapping, gpio_list): - gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1]) - - for gpio in gpios: - for reg in bit_mapping['regs'].keys(): - value = eval( 'gpio_list[gpio].%s' % (reg) ) - if ( value ): - # we have a high bit - bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift'] - bit = value << (bit_shift) - pxa_regs[bit_mapping['regs'][reg]] |= bit - -for i in bit_mappings: - stuff_bits(i, gpio_list) - -# now print out all regs -registers = pxa_regs.keys() -registers.sort() -for reg in registers: - print '%s: 0x%x' % (reg, pxa_regs[reg]) - -# print define to past right into U-Boot source code - -print -print - -for reg in registers: - print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg]) - -# print all GPIOS -print -print - -for i in range(len(gpio_list)): - gpio_i = gpio_list[i] - alt_func_desc = pxa255_alt_func[i][gpio_i.alt] - print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc) - - diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig deleted file mode 100644 index c6635040a37..00000000000 --- a/board/zipitz2/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_ZIPITZ2 - -config SYS_BOARD - default "zipitz2" - -config SYS_CONFIG_NAME - default "zipitz2" - -endif diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS deleted file mode 100644 index 55b0f6406cd..00000000000 --- a/board/zipitz2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZIPITZ2 BOARD -M: Marek Vasut -S: Maintained -F: board/zipitz2/ -F: include/configs/zipitz2.h -F: configs/zipitz2_defconfig diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile deleted file mode 100644 index 855f6bcda86..00000000000 --- a/board/zipitz2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (C) 2009 -# Marek Vasut -# -# Heavily based on pxa255_idp platform -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := zipitz2.o diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c deleted file mode 100644 index 90bba6a5fc1..00000000000 --- a/board/zipitz2/zipitz2.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2009 - * Marek Vasut - * - * Heavily based on pxa255_idp platform - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_SPI -void lcd_start(void); -#else -inline void lcd_start(void) {}; -#endif - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Z2 */ - gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Enable LCD */ - lcd_start(); - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -#ifdef CONFIG_CMD_SPI - -struct { - unsigned char reg; - unsigned short data; - unsigned char mdelay; -} lcd_data[] = { - { 0x07, 0x0000, 0 }, - { 0x13, 0x0000, 10 }, - { 0x11, 0x3004, 0 }, - { 0x14, 0x200F, 0 }, - { 0x10, 0x1a20, 0 }, - { 0x13, 0x0040, 50 }, - { 0x13, 0x0060, 0 }, - { 0x13, 0x0070, 200 }, - { 0x01, 0x0127, 0 }, - { 0x02, 0x0700, 0 }, - { 0x03, 0x1030, 0 }, - { 0x08, 0x0208, 0 }, - { 0x0B, 0x0620, 0 }, - { 0x0C, 0x0110, 0 }, - { 0x30, 0x0120, 0 }, - { 0x31, 0x0127, 0 }, - { 0x32, 0x0000, 0 }, - { 0x33, 0x0503, 0 }, - { 0x34, 0x0727, 0 }, - { 0x35, 0x0124, 0 }, - { 0x36, 0x0706, 0 }, - { 0x37, 0x0701, 0 }, - { 0x38, 0x0F00, 0 }, - { 0x39, 0x0F00, 0 }, - { 0x40, 0x0000, 0 }, - { 0x41, 0x0000, 0 }, - { 0x42, 0x013f, 0 }, - { 0x43, 0x0000, 0 }, - { 0x44, 0x013f, 0 }, - { 0x45, 0x0000, 0 }, - { 0x46, 0xef00, 0 }, - { 0x47, 0x013f, 0 }, - { 0x48, 0x0000, 0 }, - { 0x07, 0x0015, 30 }, - { 0x07, 0x0017, 0 }, - { 0x20, 0x0000, 0 }, - { 0x21, 0x0000, 0 }, - { 0x22, 0x0000, 0 }, -}; - -void zipitz2_spi_sda(int set) -{ - /* GPIO 13 */ - if (set) - writel((1 << 13), GPSR0); - else - writel((1 << 13), GPCR0); -} - -void zipitz2_spi_scl(int set) -{ - /* GPIO 22 */ - if (set) - writel((1 << 22), GPCR0); - else - writel((1 << 22), GPSR0); -} - -unsigned char zipitz2_spi_read(void) -{ - /* GPIO 40 */ - return !!(readl(GPLR1) & (1 << 8)); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Always valid */ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* GPIO 88 low */ - writel((1 << 24), GPCR2); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* GPIO 88 high */ - writel((1 << 24), GPSR2); - -} - -void lcd_start(void) -{ - int i; - unsigned char reg[3] = { 0x74, 0x00, 0 }; - unsigned char data[3] = { 0x76, 0, 0 }; - unsigned char dummy[3] = { 0, 0, 0 }; - - /* PWM2 AF */ - writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); - /* Enable clock to all PWM */ - writel(readl(CKEN) | 0x3, CKEN); - /* Configure PWM2 */ - writel(0x4f, PWM_CTRL2); - writel(0x2ff, PWM_PWDUTY2); - writel(792, PWM_PERVAL2); - - /* Toggle the reset pin to reset the LCD */ - writel((1 << 19), GPSR0); - udelay(100000); - writel((1 << 19), GPCR0); - udelay(20000); - writel((1 << 19), GPSR0); - udelay(20000); - - /* Program the LCD init sequence */ - for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { - reg[0] = 0x74; - reg[1] = 0x0; - reg[2] = lcd_data[i].reg; - spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); - - data[0] = 0x76; - data[1] = lcd_data[i].data >> 8; - data[2] = lcd_data[i].data & 0xff; - spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); - - if (lcd_data[i].mdelay) - udelay(lcd_data[i].mdelay * 1000); - } - - writel((1 << 11), GPSR0); -} -#endif diff --git a/configs/pxa255_idp_defconfig b/configs/pxa255_idp_defconfig deleted file mode 100644 index c7be4e9b337..00000000000 --- a/configs/pxa255_idp_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_PXA255_IDP=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig deleted file mode 100644 index 2977ccc8dde..00000000000 --- a/configs/zipitz2_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_ZIPITZ2=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_PROMPT="$ " diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h deleted file mode 100644 index 332d79f89f5..00000000000 --- a/include/configs/pxa255_idp.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Copied from lubbock.h - * - * (C) Copyright 2004 - * BEC Systems - * Cliff Brake - * Configuation settings for the Accelent/Vibren PXA255 IDP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * If we are developing, we might want to start U-Boot from RAM - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* - * define the following to enable debug blinks. A debug blink function - * must be defined in memsetup.S - */ -#undef DEBUG_BLINK_ENABLE -#undef DEBUG_BLINKC_ENABLE - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ - -#undef CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_SHARP_LM8V31 -#endif - -#define CONFIG_MMC 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_BOARD_LATE_INIT - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * PXA250 IDP memory map information - */ - -#define IDP_CS5_ETH_OFFSET 0x03400000 - - -/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) -#define CONFIG_SMC_USE_32_BIT 1 -/* #define CONFIG_SMC_USE_IOFUNCS */ - -/* the following has to be set high -- suspect something is wrong with - * with the tftp timeout routines. FIXME!!! - */ -#define CONFIG_NET_RETRY_COUNT 100 - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_DHCP - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -/* #define CONFIG_INITRD_TAG 1 */ - -/* - * Current memory map for Vibren supplied Linux images: - * - * Flash: - * 0 - 0x3ffff (size = 0x40000): bootloader - * 0x40000 - 0x13ffff (size = 0x100000): kernel - * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs - * - * RAM: - * 0xa0008000 - kernel is loaded - * 0xa3000000 - Uboot runs (48MB into RAM) - * - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "prog_boot_mmc=" \ - "mw.b 0xa0000000 0xff 0x40000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset;" \ - "fi\0" \ - "prog_uzImage_mmc=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_mmc=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa1000000 uzImage && " \ - "then " \ - "bootm 0xa1000000; " \ - "fi\0" \ - "prog_boot_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset; " \ - "fi\0" \ - "prog_uzImage_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_net=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if bootp 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" - - -/* "erase_env=" */ -/* "protect off" */ - - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#define RTC 1 /* enable 32KHz osc */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -/* - * GPIO settings - */ - -#define CONFIG_SYS_GAFR0_L_VAL 0x80001005 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 -#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x2 -#define CONFIG_SYS_GPCR0_VAL 0x1800400 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPDR0_VAL 0xc1818440 -#define CONFIG_SYS_GPDR1_VAL 0xfcffab82 -#define CONFIG_SYS_GPDR2_VAL 0x1ffff -#define CONFIG_SYS_GPSR0_VAL 0x8000 -#define CONFIG_SYS_GPSR1_VAL 0x3f0002 -#define CONFIG_SYS_GPSR2_VAL 0x1c000 - -#define CONFIG_SYS_PSSR_VAL 0x20 - -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 -#define CONFIG_SYS_CKEN 0x0 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2 -#define CONFIG_SYS_MSC1_VAL 0x43AC494C -#define CONFIG_SYS_MSC2_VAL 0x39D449D4 -#define CONFIG_SYS_MDCNFG_VAL 0x090009C9 -#define CONFIG_SYS_MDREFR_VAL 0x0085C017 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000003 -#define CONFIG_SYS_MCMEM0_VAL 0x00014405 -#define CONFIG_SYS_MCMEM1_VAL 0x00014405 -#define CONFIG_SYS_MCATT0_VAL 0x00014405 -#define CONFIG_SYS_MCATT1_VAL 0x00014405 -#define CONFIG_SYS_MCIO0_VAL 0x00014405 -#define CONFIG_SYS_MCIO1_VAL 0x00014405 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* put cfg at end of flash for now */ -#define CONFIG_ENV_IS_IN_FLASH 1 - /* Addr of Environment Sector */ -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) -#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16) - -#endif /* __CONFIG_H */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h deleted file mode 100644 index 0199190eb87..00000000000 --- a/include/configs/zipitz2.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Aeronix Zipit Z2 configuration file - * - * Copyright (C) 2009-2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -#undef CONFIG_BOARD_LATE_INIT -#undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_PREBOOT - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x20000 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ - "then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x60000; " \ - "fi; " -#define CONFIG_BOOTARGS \ - "console=tty0 console=ttyS2,115200 fbcon=rotate:3" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_LZMA /* LZMA compression support */ - -/* - * Serial Console Configuration - * STUART - the lower serial port on Colibri board - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_STUART 1 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_SPI - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * SPI and LCD - */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_LMS283GF05 -#define CONFIG_VIDEO_LOGO -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -#define SPI_DELAY udelay(10) -#define SPI_SDA(val) zipitz2_spi_sda(val) -#define SPI_SCL(val) zipitz2_spi_scl(val) -#define SPI_READ zipitz2_spi_read() -#ifndef __ASSEMBLY__ -void zipitz2_spi_sda(int); -void zipitz2_spi_scl(int); -unsigned char zipitz2_spi_read(void); -#endif -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ - -/* - * SRAM Map - */ -#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ -#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) - -/* - * NOR FLASH - */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 -#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 -#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 -#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 -#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000020 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 -#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff -#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a -#define CONFIG_SYS_GPSR0_VAL 0x06080400 -#define CONFIG_SYS_GPSR1_VAL 0x007f0000 -#define CONFIG_SYS_GPSR2_VAL 0x032a0000 -#define CONFIG_SYS_GPSR3_VAL 0x00000180 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00511220 -#define CONFIG_SYS_CCCR 0x00000190 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 -#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 -#define CONFIG_SYS_MSC2_VAL 0x0000b884 -#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 -#define CONFIG_SYS_MDREFR_VAL 0x2011a01e -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From daf770864d341324536411e4286610091bf04341 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:25 -0600 Subject: arm: Remove qong board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/davedenx/qong/Kconfig | 15 -- board/davedenx/qong/MAINTAINERS | 6 - board/davedenx/qong/Makefile | 11 -- board/davedenx/qong/fpga.c | 77 ---------- board/davedenx/qong/lowlevel_init.S | 223 ---------------------------- board/davedenx/qong/qong.c | 259 --------------------------------- board/davedenx/qong/qong_fpga.h | 23 --- configs/qong_defconfig | 2 - include/configs/qong.h | 283 ------------------------------------ 10 files changed, 904 deletions(-) delete mode 100644 board/davedenx/qong/Kconfig delete mode 100644 board/davedenx/qong/MAINTAINERS delete mode 100644 board/davedenx/qong/Makefile delete mode 100644 board/davedenx/qong/fpga.c delete mode 100644 board/davedenx/qong/lowlevel_init.S delete mode 100644 board/davedenx/qong/qong.c delete mode 100644 board/davedenx/qong/qong_fpga.h delete mode 100644 configs/qong_defconfig delete mode 100644 include/configs/qong.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e96e902ffd1..e46764f0a5a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -239,10 +239,6 @@ config TARGET_IMX31_PHYCORE bool "Support imx31_phycore" select CPU_ARM1136 -config TARGET_QONG - bool "Support qong" - select CPU_ARM1136 - config TARGET_MX31ADS bool "Support mx31ads" select CPU_ARM1136 @@ -751,7 +747,6 @@ source "board/cirrus/edb93xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/creative/xfi3/Kconfig" -source "board/davedenx/qong/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" source "board/freescale/ls2085a/Kconfig" diff --git a/board/davedenx/qong/Kconfig b/board/davedenx/qong/Kconfig deleted file mode 100644 index 76cf343dede..00000000000 --- a/board/davedenx/qong/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_QONG - -config SYS_BOARD - default "qong" - -config SYS_VENDOR - default "davedenx" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "qong" - -endif diff --git a/board/davedenx/qong/MAINTAINERS b/board/davedenx/qong/MAINTAINERS deleted file mode 100644 index a275b5bce48..00000000000 --- a/board/davedenx/qong/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -QONG BOARD -M: Wolfgang Denk -S: Maintained -F: board/davedenx/qong/ -F: include/configs/qong.h -F: configs/qong_defconfig diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile deleted file mode 100644 index 48c443d7605..00000000000 --- a/board/davedenx/qong/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2009 -# Ilya Yanok, Emcraft Systems Ltd, -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := qong.o fpga.o -obj-y += lowlevel_init.o diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c deleted file mode 100644 index 2eaad1e976f..00000000000 --- a/board/davedenx/qong/fpga.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "qong_fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -static void qong_jtag_init(void) -{ - return; -} - -static void qong_fpga_jtag_set_tdi(int value) -{ - gpio_set_value(QONG_FPGA_TDI_PIN, value); -} - -static void qong_fpga_jtag_set_tms(int value) -{ - gpio_set_value(QONG_FPGA_TMS_PIN, value); -} - -static void qong_fpga_jtag_set_tck(int value) -{ - gpio_set_value(QONG_FPGA_TCK_PIN, value); -} - -static int qong_fpga_jtag_get_tdo(void) -{ - return gpio_get_value(QONG_FPGA_TDO_PIN); -} - -lattice_board_specific_func qong_fpga_fns = { - qong_jtag_init, - qong_fpga_jtag_set_tdi, - qong_fpga_jtag_set_tms, - qong_fpga_jtag_set_tck, - qong_fpga_jtag_get_tdo -}; - -Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = { - { - Lattice_XP2, - lattice_jtag_mode, - 356519, - (void *) &qong_fpga_fns, - NULL, - 0, - "lfxp2_5e_ftbga256" - }, -}; - -int qong_fpga_init(void) -{ - int i; - - fpga_init(); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - fpga_add(fpga_lattice, &qong_fpga[i]); - } - return 0; -} - -#endif diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S deleted file mode 100644 index 8887023f8c8..00000000000 --- a/board/davedenx/qong/lowlevel_init.S +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2009, Emcraft Systems, Ilya Yanok - * - * Based on board/freescale/mx31ads/lowlevel_init.S - * by Guennadi Liakhovetski. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -.macro SETUP_RAM cfg, ctl - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - ldr r3, =\cfg - ldr r2, =WEIM_ESDCFG0 - str r3, [r2] - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - ldr r3, =\ctl - ldr r2, =WEIM_ESDCTL0 - str r3, [r2] - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - -.endm -/* RedBoot: To support 133MHz DDR */ -.macro init_drive_strength - /* - * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits - * in SW_PAD_CTL registers - */ - - /* SDCLK */ - ldr r1, =IOMUXC_SW_PAD_CTL(0x2b) - ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) - str r0, [r1, #0x6C] - - /* CAS */ - ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x70] - - /* RAS */ - ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) - str r0, [r1, #0x74] - - /* CS2 (CSD0) */ - ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x7C] - - /* DQM3 */ - ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x84] - - /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ -pad_loop: - ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) - str r0, [r1, #0x88] - add r1, r1, #4 - subs r2, r2, #0x1 - bne pad_loop -.endm /* init_drive_strength */ - -.globl lowlevel_init -lowlevel_init: - - init_drive_strength - - /* Image Processing Unit: */ - /* Too early to switch display on? */ - /* Switch on Display Interface */ - REG IPU_CONF, IPU_CONF_DI_EN - /* Clock Control Module: */ - REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ - /* Switch to MCU PLL */ - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - - /* 399-133-66.5 */ - ldr r0, =CCM_BASE - ldr r1, =0xFF871650 - /* PDR0 */ - str r1, [r0, #0x4] - ldr r1, MPCTL_PARAM_399 - /* MPCTL */ - str r1, [r0, #0x10] - - /* Set UPLL=240MHz, USB=60MHz */ - ldr r1, =0x49FCFE7F - /* PDR1 */ - str r1, [r0, #0x8] - ldr r1, UPCTL_PARAM_240 - /* UPCTL */ - str r1, [r0, #0x14] - /* default CLKO to 1/8 of the ARM core */ - mov r1, #0x00000208 - /* COSR */ - str r1, [r0, #0x1c] - - /* Default: 1, 4, 12, 1 */ - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - -check_ddr_module: -/* Set stackpointer in internal RAM to call get_ram_size */ - ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16) - stmfd sp!, {r0-r11, ip, lr} - mov ip, lr /* save link reg across call */ - - ldr r0,=0x08000000 - SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB - ldr r0,=0x80000000 - ldr r1,=0x10000000 - bl get_ram_size - ldr r1,=0x10000000 - cmp r0,r1 - beq restore_regs - SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB - ldr r0,=0x80000000 - ldr r1,=0x08000000 - bl get_ram_size - ldr r1,=0x08000000 - cmp r0,r1 - beq restore_regs - -restore_regs: - ldmfd sp!, {r0-r11, ip, lr} - mov lr, ip /* restore link reg */ - - mov pc, lr - - -MPCTL_PARAM_399: - .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0)) -UPCTL_PARAM_240: - .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0)) - - .equ ESDCFG0_128MB, \ - (0 << 21) + /* tXP */ \ - (1 << 20) + /* tWTR */ \ - (2 << 18) + /* tRP */ \ - (1 << 16) + /* tMRD */ \ - (0 << 15) + /* tWR */ \ - (5 << 12) + /* tRAS */ \ - (1 << 10) + /* tRRD */ \ - (3 << 8) + /* tCAS */ \ - (2 << 4) + /* tRCD */ \ - (0x0F << 0) /* tRC */ - - .equ ESDCTL0_128MB, \ - (1 << 31) + /* enable */ \ - (0 << 28) + /* mode */ \ - (0 << 27) + /* supervisor protect */ \ - (2 << 24) + /* 13 rows */ \ - (2 << 20) + /* 10 cols */ \ - (2 << 16) + /* 32 bit */ \ - (3 << 13) + /* 7.81us (64ms/8192) */ \ - (0 << 10) + /* power down timer */ \ - (0 << 8) + /* full page */ \ - (1 << 7) + /* burst length */ \ - (0 << 0) /* precharge timer */ - - .equ ESDCFG0_256MB, \ - (3 << 21) + /* tXP */ \ - (0 << 20) + /* tWTR */ \ - (2 << 18) + /* tRP */ \ - (1 << 16) + /* tMRD */ \ - (0 << 15) + /* tWR */ \ - (5 << 12) + /* tRAS */ \ - (1 << 10) + /* tRRD */ \ - (3 << 8) + /* tCAS */ \ - (2 << 4) + /* tRCD */ \ - (7 << 0) /* tRC */ - - .equ ESDCTL0_256MB, \ - (1 << 31) + \ - (0 << 28) + \ - (0 << 27) + \ - (3 << 24) + /* 14 rows */ \ - (2 << 20) + /* 10 cols */ \ - (2 << 16) + \ - (4 << 13) + /* 3.91us (64ms/16384) */ \ - (0 << 10) + \ - (0 << 8) + \ - (1 << 7) + \ - (0 << 0) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c deleted file mode 100644 index ad1694b79fb..00000000000 --- a/board/davedenx/qong/qong.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * - * (c) 2009 Emcraft Systems, Ilya Yanok - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qong_fpga.h" -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -static void qong_fpga_reset(void) -{ - gpio_set_value(QONG_FPGA_RST_PIN, 0); - udelay(30); - gpio_set_value(QONG_FPGA_RST_PIN, 1); - - udelay(300); -} - -int board_early_init_f(void) -{ -#ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ - static const struct mxc_weimcs cs1 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(1, &cs1); - - /* setup pins for FPGA */ - mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); - - /* FPGA reset Pin */ - /* rstn = 0 */ - gpio_direction_output(QONG_FPGA_RST_PIN, 0); - - /* set interrupt pin as input */ - gpio_direction_input(QONG_FPGA_IRQ_PIN); - - /* FPGA JTAG Interface */ - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO)); - gpio_direction_output(QONG_FPGA_TCK_PIN, 0); - gpio_direction_output(QONG_FPGA_TMS_PIN, 0); - gpio_direction_output(QONG_FPGA_TDI_PIN, 0); - gpio_direction_input(QONG_FPGA_TDO_PIN); -#endif - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* setup pins for SPI (pmic) */ - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - - /* Setup pins for USB2 Host */ - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - - mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); - mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); - mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); - mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); - mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - mx31_set_gpr(MUX_PGP_UH2, 1); - - return 0; - -} - -int board_init(void) -{ - /* Chip selects */ - /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ - /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - - /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_QONG; - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - - qong_fpga_init(); - - return 0; -} - -int board_late_init(void) -{ - u32 val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - /* Enable RTC battery */ - pmic_reg_read(p, REG_POWER_CTL0, &val); - pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); - pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); - -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - - return 0; -} - -int checkboard(void) -{ - printf("Board: DAVE/DENX Qong\n"); - return 0; -} - -int misc_init_r(void) -{ -#ifdef CONFIG_QONG_FPGA - u32 tmp; - - tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION; - printf("FPGA: "); - printf("version register = %u.%u.%u\n", - (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF); -#endif - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET) - return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1); -#else - return 0; -#endif -} - -#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) -static void board_nand_setup(void) -{ - /* CS3: NAND 8-bit */ - static const struct mxc_weimcs cs3 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(3, &cs3); - - mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1); - - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO)); - - /* Make sure to reset the fpga else you cannot access NAND */ - qong_fpga_reset(); - - /* Enable NAND flash */ - gpio_set_value(15, 1); - gpio_set_value(14, 1); - gpio_direction_output(15, 0); - gpio_direction_input(16); - gpio_direction_input(14); - -} - -int qong_nand_rdy(void *chip) -{ - udelay(1); - return gpio_get_value(16); -} - -void qong_nand_select_chip(struct mtd_info *mtd, int chip) -{ - if (chip >= 0) - gpio_set_value(15, 0); - else - gpio_set_value(15, 1); - -} - -void qong_nand_plat_init(void *chip) -{ - struct nand_chip *nand = (struct nand_chip *)chip; - nand->chip_delay = 20; - nand->select_chip = qong_nand_select_chip; - nand->options &= ~NAND_BUSWIDTH_16; - board_nand_setup(); -} - -#endif diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h deleted file mode 100644 index 2a619f7377b..00000000000 --- a/board/davedenx/qong/qong_fpga.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * - * (c) 2009 Emcraft Systems, Ilya Yanok - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef QONG_FPGA_H -#define QONG_FPGA_H - -#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE -#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000) -#define QONG_FPGA_PERIPH_SIZE (1 << 24) - -#define QONG_FPGA_TCK_PIN 26 -#define QONG_FPGA_TMS_PIN 25 -#define QONG_FPGA_TDI_PIN 8 -#define QONG_FPGA_TDO_PIN 7 -#define QONG_FPGA_RST_PIN 48 -#define QONG_FPGA_IRQ_PIN 40 - -int qong_fpga_init(void); -#endif /* QONG_FPGA_H */ diff --git a/configs/qong_defconfig b/configs/qong_defconfig deleted file mode 100644 index fddd8363188..00000000000 --- a/configs/qong_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_QONG=y diff --git a/include/configs/qong.h b/include/configs/qong.h deleted file mode 100644 index f34a54f7540..00000000000 --- a/include/configs/qong.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, - * - * Configuration settings for the Dave/DENX QongEVB-LITE board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_QONG - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_MXC_GPIO -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG - -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_RTC_MC13XXX - -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 - -/* FPGA */ -#define CONFIG_FPGA -#define CONFIG_QONG_FPGA -#define CONFIG_FPGA_BASE (CS1_BASE) -#define CONFIG_FPGA_LATTICE -#define CONFIG_FPGA_COUNT 1 - -#ifdef CONFIG_QONG_FPGA -/* Ethernet */ -#define CONFIG_DNET -#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE) - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MX3 -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) - -/* USB */ -#define CONFIG_CMD_USB -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_MXC -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORT 2 -#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT) -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#endif /* CONFIG_CMD_USB */ - -/* - * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the - * initial TFTP transfer, should the user wish one, significantly. - */ -#define CONFIG_ARP_TIMEOUT 200UL - -#endif /* CONFIG_QONG_FPGA */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_SPI -#define CONFIG_CMD_UNZIP - -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "uboot_addr=A0000000\0" \ - "kernel_addr=A00C0000\0" \ - "ramdisk_addr=A0300000\0" \ - "u-boot=qong/u-boot.bin\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=qong\0" \ - "bootfile=qong/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/armVFP\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run flash_self\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \ - "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \ - "vmode:0\0" \ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* memtest works on first 255MB of RAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -#define CONFIG_MISC_INIT_R - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ - -/* - * NAND driver - */ - -#ifndef __ASSEMBLY__ -extern void qong_nand_plat_init(void *chip); -extern int qong_nand_rdy(void *chip); -#endif -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CS3_BASE -#define NAND_PLAT_INIT() qong_nand_plat_init(nand) - -#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) -#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) -#define QONG_NAND_WRITE(addr, cmd) \ - do { \ - __REG8(addr) = cmd; \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip)) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* Flash memory is CFI compliant */ -#define CONFIG_SYS_FLASH_CFI -/* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_CFI_DRIVER -/* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -/* Use hardware sector protection */ -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * Filesystem - */ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_RBTREE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_LZO -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ - "nand0=gen_nand" -#define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:" \ - "512k(U-Boot),128k(env1),128k(env2)," \ - "2304k(kernel),13m(ramdisk),-(user);" \ - "gen_nand:" \ - "128m(nand)" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) - -#define CONFIG_BOARD_EARLY_INIT_F - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 47b87d2eedcdf7be821247e570128664709844d4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:26 -0600 Subject: arm: Remove rd6281a board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/rd6281a/Kconfig | 12 --- board/Marvell/rd6281a/MAINTAINERS | 6 -- board/Marvell/rd6281a/Makefile | 9 --- board/Marvell/rd6281a/kwbimage.cfg | 151 ----------------------------------- board/Marvell/rd6281a/rd6281a.c | 157 ------------------------------------- board/Marvell/rd6281a/rd6281a.h | 25 ------ configs/rd6281a_defconfig | 6 -- include/configs/rd6281a.h | 96 ----------------------- 9 files changed, 466 deletions(-) delete mode 100644 board/Marvell/rd6281a/Kconfig delete mode 100644 board/Marvell/rd6281a/MAINTAINERS delete mode 100644 board/Marvell/rd6281a/Makefile delete mode 100644 board/Marvell/rd6281a/kwbimage.cfg delete mode 100644 board/Marvell/rd6281a/rd6281a.c delete mode 100644 board/Marvell/rd6281a/rd6281a.h delete mode 100644 configs/rd6281a_defconfig delete mode 100644 include/configs/rd6281a.h (limited to 'include') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 6228f5bc117..3002c04098b 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -4,9 +4,6 @@ choice prompt "Marvell Kirkwood board select" optional -config TARGET_RD6281A - bool "RD6281A Board" - config TARGET_DREAMPLUG bool "DreamPlug Board" @@ -60,7 +57,6 @@ endchoice config SYS_SOC default "kirkwood" -source "board/Marvell/rd6281a/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" diff --git a/board/Marvell/rd6281a/Kconfig b/board/Marvell/rd6281a/Kconfig deleted file mode 100644 index 025ee26dc6b..00000000000 --- a/board/Marvell/rd6281a/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RD6281A - -config SYS_BOARD - default "rd6281a" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "rd6281a" - -endif diff --git a/board/Marvell/rd6281a/MAINTAINERS b/board/Marvell/rd6281a/MAINTAINERS deleted file mode 100644 index d4ad592a9ef..00000000000 --- a/board/Marvell/rd6281a/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RD6281A BOARD -M: Prafulla Wadaskar -S: Maintained -F: board/Marvell/rd6281a/ -F: include/configs/rd6281a.h -F: configs/rd6281a_defconfig diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile deleted file mode 100644 index cb773705e8a..00000000000 --- a/board/Marvell/rd6281a/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := rd6281a.o diff --git a/board/Marvell/rd6281a/kwbimage.cfg b/board/Marvell/rd6281a/kwbimage.cfg deleted file mode 100644 index f969d92ed74..00000000000 --- a/board/Marvell/rd6281a/kwbimage.cfg +++ /dev/null @@ -1,151 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x00000099 # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 1, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 0, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 -# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 -# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c deleted file mode 100644 index b0020c95a5b..00000000000 --- a/board/Marvell/rd6281a/rd6281a.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "rd6281a.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(RD6281A_OE_VAL_LOW, - RD6281A_OE_VAL_HIGH, - RD6281A_OE_LOW, RD6281A_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GE1_14, - MPP35_GPIO, - MPP36_AUDIO_SPDIFI, - MPP37_AUDIO_SPDIFO, - MPP38_GPIO, - MPP39_TDM_SPI_CS0, - MPP40_TDM_SPI_SCK, - MPP41_TDM_SPI_MISO, - MPP42_TDM_SPI_MOSI, - MPP43_TDM_CODEC_INTn, - MPP44_GPIO, - MPP45_TDM_PCLK, - MPP46_TDM_FS, - MPP47_TDM_DRX, - MPP48_TDM_DTX, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_RD88F6281; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -void mv_phy_88e1116_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __FUNCTION__); - return; - } - if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __FUNCTION__); - return; - } - - printf("88E1116 Initialized on %s\n", name); -} - -/* Configure and enable Switch and PHY */ -void reset_phy(void) -{ - /* configure and initialize switch */ - struct mv88e61xx_config swcfg = { - .name = "egiga0", - .vlancfg = MV88E61XX_VLANCFG_ROUTER, - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, - .led_init = MV88E61XX_LED_INIT_EN, - .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = (1 << 5), - .ports_enabled = 0x3f, - }; - - mv88e61xx_switch_initialize(&swcfg); - - /* configure and initialize PHY */ - mv_phy_88e1116_init("egiga1"); -} diff --git a/board/Marvell/rd6281a/rd6281a.h b/board/Marvell/rd6281a/rd6281a.h deleted file mode 100644 index 5e1f6a83fe9..00000000000 --- a/board/Marvell/rd6281a/rd6281a.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __RD6281A_H -#define __RD6281A_H - -#define RD6281A_OE_LOW (~(1 << 7)) -#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12)) -#define RD6281A_OE_VAL_LOW (0) -#define RD6281A_OE_VAL_HIGH (1 << 12) - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __RD6281A_H */ diff --git a/configs/rd6281a_defconfig b/configs/rd6281a_defconfig deleted file mode 100644 index 8fe8594da1d..00000000000 --- a/configs/rd6281a_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_RD6281A=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h deleted file mode 100644 index a0120b06fdb..00000000000 --- a/include/configs/rd6281a.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_RD6281A_H -#define _CONFIG_RD6281A_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-RD6281A" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_RD6281A /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_IDE - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ - "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE -#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ -#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ -#define CONFIG_PHY_BASE_ADR 0x0A -#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_RD6281A_H */ -- cgit v1.3.1 From 7650beb7ca905729891984e117443544157448d0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:27 -0600 Subject: arm: Remove scb9328 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/scb9328/Kconfig | 12 -- board/scb9328/MAINTAINERS | 6 - board/scb9328/Makefile | 9 -- board/scb9328/flash.c | 310 ----------------------------------------- board/scb9328/intel.h | 78 ----------- board/scb9328/lowlevel_init.S | 188 ------------------------- board/scb9328/scb9328.c | 54 -------- configs/scb9328_defconfig | 7 - include/configs/scb9328.h | 312 ------------------------------------------ 10 files changed, 981 deletions(-) delete mode 100644 board/scb9328/Kconfig delete mode 100644 board/scb9328/MAINTAINERS delete mode 100644 board/scb9328/Makefile delete mode 100644 board/scb9328/flash.c delete mode 100644 board/scb9328/intel.h delete mode 100644 board/scb9328/lowlevel_init.S delete mode 100644 board/scb9328/scb9328.c delete mode 100644 configs/scb9328_defconfig delete mode 100644 include/configs/scb9328.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e46764f0a5a..ad3f554ccc5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -79,10 +79,6 @@ config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T -config TARGET_SCB9328 - bool "Support scb9328" - select CPU_ARM920T - config TARGET_VCMA9 bool "Support VCMA9" select CPU_ARM920T @@ -781,7 +777,6 @@ source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" -source "board/scb9328/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" diff --git a/board/scb9328/Kconfig b/board/scb9328/Kconfig deleted file mode 100644 index 68e99ea2e33..00000000000 --- a/board/scb9328/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SCB9328 - -config SYS_BOARD - default "scb9328" - -config SYS_SOC - default "imx" - -config SYS_CONFIG_NAME - default "scb9328" - -endif diff --git a/board/scb9328/MAINTAINERS b/board/scb9328/MAINTAINERS deleted file mode 100644 index 0917266afd0..00000000000 --- a/board/scb9328/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SCB9328 BOARD -M: Torsten Koschorrek -S: Maintained -F: board/scb9328/ -F: include/configs/scb9328.h -F: configs/scb9328_defconfig diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile deleted file mode 100644 index 0b08f1a8713..00000000000 --- a/board/scb9328/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := scb9328.o flash.o -obj-y += lowlevel_init.o diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c deleted file mode 100644 index 73bfa00eed6..00000000000 --- a/board/scb9328/flash.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This code was inspired by Marius Groeger and Kyle Harris code - * available in other board ports for U-Boot - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Written by Peter Figuli , 2003. - */ - -#include -#include "intel.h" - - -/* - * This code should handle CFI FLASH memory device. This code is very - * minimalistic approach without many essential error handling code as well. - * Because U-Boot actually is missing smart handling of FLASH device, - * we just set flash_id to anything else to FLASH_UNKNOW, so common code - * can call us without any restrictions. - * TODO: Add CFI Query, to be able to determine FLASH device. - * TODO: Add error handling code - * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but - * hopefully may work with other configurations. - */ - -#if ( SCB9328_FLASH_BUS_WIDTH == 1 ) -# define FLASH_BUS vu_char -# define FLASH_BUS_RET u_char -# if ( SCB9328_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# else -# error "With 8bit bus only one chip is allowed" -# endif - - -#elif ( SCB9328_FLASH_BUS_WIDTH == 2 ) -# define FLASH_BUS vu_short -# define FLASH_BUS_RET u_short -# if ( SCB9328_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# elif ( SCB9328_FLASH_INTERLEAVE == 2 ) -# define FLASH_CMD( x ) (( x << 8 )| x ) -# else -# error "With 16bit bus only 1 or 2 chip(s) are allowed" -# endif - - -#elif ( SCB9328_FLASH_BUS_WIDTH == 4 ) -# define FLASH_BUS vu_long -# define FLASH_BUS_RET u_long -# if ( SCB9328_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# elif ( SCB9328_FLASH_INTERLEAVE == 2 ) -# define FLASH_CMD( x ) (( x << 16 )| x ) -# elif ( SCB9328_FLASH_INTERLEAVE == 4 ) -# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) -# else -# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" -# endif - -#else -# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" -#endif - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static FLASH_BUS_RET flash_status_reg (void) -{ - - FLASH_BUS *addr = (FLASH_BUS *) 0; - - /* cppcheck-suppress nullPointer */ - *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); - - /* cppcheck-suppress nullPointer */ - return *addr; -} - -static int flash_ready (ulong timeout) -{ - int ok = 1; - ulong start; - - start = get_timer(0); - while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != - FLASH_CMD (CFI_INTEL_SR_READY)) { - if (get_timer(start) > timeout && timeout != 0) { - ok = 0; - break; - } - } - return ok; -} - -#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 ) -# error "SCB9328 platform has only one flash bank!" -#endif - - -ulong flash_init (void) -{ - int i; - unsigned long address = SCB9328_FLASH_BASE; - - flash_info[0].size = SCB9328_FLASH_BANK_SIZE; - flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - flash_info[0].flash_id = INTEL_MANUFACT; - memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) { - flash_info[0].start[i] = address; -#ifdef SCB9328_FLASH_UNLOCK - /* Some devices are hw locked after start. */ - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); - flash_ready (0); - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); -#endif - address += SCB9328_FLASH_SECT_SIZE; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return SCB9328_FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - - printf (" Intel vendor\n"); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if (!(i % 5)) { - printf ("\n"); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, non_protected = 0, sector; - int rc = ERR_OK; - - FLASH_BUS *address; - - for (sector = s_first; sector <= s_last; sector++) { - if (!info->protect[sector]) { - non_protected++; - } - } - - if (!non_protected) { - return ERR_PROTECTED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - - /* Start erase on unprotected sectors */ - for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { - if (info->protect[sector]) { - printf ("Protected sector %2d skipping...\n", sector); - continue; - } else { - printf ("Erasing sector %2d ... ", sector); - } - - address = (FLASH_BUS *) (info->start[sector]); - - *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); - *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); - if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) { - *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); - printf ("ok.\n"); - } else { - *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); - rc = ERR_TIMOUT; - printf ("timeout! Aborting...\n"); - break; - } - *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - if (flag) { - enable_interrupts (); - } - - return rc; -} - -static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) -{ - FLASH_BUS *address = (FLASH_BUS *) dest; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*address & data) != data) { - return ERR_NOT_ERASED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts (); - - *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); - *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); - *address = data; - - if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) { - *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); - rc = ERR_TIMOUT; - printf ("timeout! Aborting...\n"); - } - - *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); - if (flag) { - enable_interrupts (); - } - - return rc; -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong read_addr, write_addr; - FLASH_BUS data; - int i, result = ERR_OK; - - - read_addr = addr & ~(sizeof (FLASH_BUS) - 1); - write_addr = read_addr; - if (read_addr != addr) { - data = 0; - for (i = 0; i < sizeof (FLASH_BUS); i++) { - if (read_addr < addr || cnt == 0) { - data |= *((uchar *) read_addr) << i * 8; - } else { - data |= (*src++) << i * 8; - cnt--; - } - read_addr++; - } - if ((result = write_data (info, write_addr, data)) != ERR_OK) { - return result; - } - write_addr += sizeof (FLASH_BUS); - } - for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { - if ((result = write_data (info, write_addr, - *((FLASH_BUS *) src))) != ERR_OK) { - return result; - } - write_addr += sizeof (FLASH_BUS); - src += sizeof (FLASH_BUS); - } - if (cnt > 0) { - read_addr = write_addr; - data = 0; - for (i = 0; i < sizeof (FLASH_BUS); i++) { - if (cnt > 0) { - data |= (*src++) << i * 8; - cnt--; - } else { - data |= *((uchar *) read_addr) << i * 8; - } - read_addr++; - } - if ((result = write_data (info, write_addr, data)) != 0) { - return result; - } - } - return ERR_OK; -} diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h deleted file mode 100644 index 5596d271330..00000000000 --- a/board/scb9328/intel.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2002 ETC s.r.o. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Written by Marcel Telka , 2002. - * - * Documentation: - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - */ - -#ifndef FLASH_INTEL_H -#define FLASH_INTEL_H - -#include - -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ - -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ - -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ - -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ - -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ - -#define CFI_CHIP_INTEL_28F320J3A 0x0016 -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" -#define CFI_CHIP_INTEL_28F640J3A 0x0017 -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" -#define CFI_CHIP_INTEL_28F128J3A 0x0018 -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" - -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ - -#define CFI_CHIP_INTEL_28F640K3 0x8801 -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" -#define CFI_CHIP_INTEL_28F128K3 0x8802 -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" -#define CFI_CHIP_INTEL_28F256K3 0x8803 -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" -#define CFI_CHIP_INTEL_28F640K18 0x8805 -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" -#define CFI_CHIP_INTEL_28F128K18 0x8806 -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" -#define CFI_CHIP_INTEL_28F256K18 0x8807 -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" - -#endif /* FLASH_INTEL_H */ diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S deleted file mode 100644 index d5727248db5..00000000000 --- a/board/scb9328/lowlevel_init.S +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* Change PERCLK1DIV to 14 ie 14+1 */ - ldr r0, =PCDR - ldr r1, =CONFIG_SYS_PCDR_VAL - str r1, [r0] - -/* set MCU PLL Control Register 0 */ - - ldr r0, =MPCTL0 - ldr r1, =CONFIG_SYS_MPCTL0_VAL - str r1, [r0] - -/* set mpll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<21) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - -/* set System PLL Control Register 0 */ - - ldr r0, =SPCTL0 - ldr r1, =CONFIG_SYS_SPCTL0_VAL - str r1, [r0] - -/* set spll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<22) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - - ldr r0, =CSCR - ldr r1, =CONFIG_SYS_CSCR_VAL - str r1, [r0] - -/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon - *this..... - * - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 - * register 1, this stops it using the output of the PLL and thus runs at the - * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never - * use the value set in the CM_OSC registers...regardless of what you set it - * too! Thus, although i thought i was running at 140MHz, i'm actually running - * at 40!.. - - * Slapping this into my bootloader does the trick... - - * MRC p15,0,r0,c1,c0,0 ; read core configuration register - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration - * register - */ - MRC p15,0,r0,c1,c0,0 - ORR r0,r0,#0xC0000000 - MCR p15,0,r0,c1,c0,0 - - ldr r0, =GPR(0) - ldr r1, =CONFIG_SYS_GPR_A_VAL - str r1, [r0] - - ldr r0, =GIUS(0) - ldr r1, =CONFIG_SYS_GIUS_A_VAL - str r1, [r0] - -/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ - - ldr r0, =FMCR - ldr r1, =CONFIG_SYS_FMCR_VAL - str r1, [r0] - - ldr r0, =CS0U - ldr r1, =CONFIG_SYS_CS0U_VAL - str r1, [r0] - - ldr r0, =CS0L - ldr r1, =CONFIG_SYS_CS0L_VAL - str r1, [r0] - - ldr r0, =CS1U - ldr r1, =CONFIG_SYS_CS1U_VAL - str r1, [r0] - - ldr r0, =CS1L - ldr r1, =CONFIG_SYS_CS1L_VAL - str r1, [r0] - - ldr r0, =CS2U - ldr r1, =CONFIG_SYS_CS2U_VAL - str r1, [r0] - - ldr r0, =CS2L - ldr r1, =CONFIG_SYS_CS2L_VAL - str r1, [r0] - - ldr r0, =CS3U - ldr r1, =CONFIG_SYS_CS3U_VAL - str r1, [r0] - - ldr r0, =CS3L - ldr r1, =CONFIG_SYS_CS3L_VAL - str r1, [r0] - - ldr r0, =CS4U - ldr r1, =CONFIG_SYS_CS4U_VAL - str r1, [r0] - - ldr r0, =CS4L - ldr r1, =CONFIG_SYS_CS4L_VAL - str r1, [r0] - - ldr r0, =CS5U - ldr r1, =CONFIG_SYS_CS5U_VAL - str r1, [r0] - - ldr r0, =CS5L - ldr r1, =CONFIG_SYS_CS5L_VAL - str r1, [r0] - -/* SDRAM Setup */ - - ldr r0, =SDCTL0 - ldr r1, =PRECHARGE_CMD - str r1, [r0] - - ldr r0, =0x08200000 - ldr r1, =0x0 /* Issue Precharge all Command */ - str r1, [r0] - - ldr r0, =SDCTL0 - ldr r1, =AUTOREFRESH_CMD - str r1, [r0] - - ldr r0, =0x08000000 - ldr r1, =0x0 /* Issue AutoRefresh Command */ - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - - ldr r0, =SDCTL0 - ldr r1, =0xb10a8300 - str r1, [r0] - - ldr r0, =0x08223000 /* CAS Latency 2 */ - ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */ - str r1, [r0] - - ldr r0, =SDCTL0 - ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */ - str r1, [r0] - - mov pc,r10 diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c deleted file mode 100644 index 3463f52693a..00000000000 --- a/board/scb9328/scb9328.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init (void) -{ - gd->bd->bi_arch_number = MACH_TYPE_SCB9328; - gd->bd->bi_boot_params = 0x08000100; - - return 0; -} - -int dram_init (void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1, - SCB9328_SDRAM_1_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; - gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; -} - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - return; -} - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/configs/scb9328_defconfig b/configs/scb9328_defconfig deleted file mode 100644 index c9c50348083..00000000000 --- a/configs/scb9328_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_SCB9328=y -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="scb9328> " diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h deleted file mode 100644 index d4ffb467bd8..00000000000 --- a/include/configs/scb9328.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * SPDX-License-Identifier: GPL-2.0+ - * Written by Peter Figuli , 2003. - * - * 2003/13/06 Initial MP10 Support copied from wepep250 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */ -#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ - -#define CONFIG_IMX_SERIAL -#define CONFIG_IMX_SERIAL1 -/* - * Select serial console configuration - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -/* - * Boot options. Setting delay to -1 stops autostart count down. - * NOTE: Sending parameters to kernel depends on kernel version and - * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept - * parameters at all! Do not get confused by them so. - */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" -#define CONFIG_BOOTCOMMAND "bootm 10040000" -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.10.10.9 -#define CONFIG_SERVERIP 10.10.10.10 - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CONFIG_SYS_LONGHELP /* undef saves memory */ -#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ - -#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ -#define CONFIG_SYS_MEMTEST_END 0x08F00000 - -#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ - -#define CONFIG_BAUDRATE 115200 -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG 1 /* send initrd params */ - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) - -/* SDRAM Setup Values -0x910a8300 Precharge Command CAS 3 -0x910a8200 Precharge Command CAS 2 - -0xa10a8300 AutoRefresh Command CAS 3 -0xa10a8200 Set AutoRefresh Command CAS 2 */ - -#define PRECHARGE_CMD 0x910a8200 -#define AUTOREFRESH_CMD 0xa10a8200 - -/* - * SDRAM Memory Map - */ -/* SH FIXME */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ -#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define CONFIG_SYS_TEXT_BASE 0x10000000 - -#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) - -/* - * Configuration for FLASH memory for the Synertronixx board - */ - -/* #define SCB9328_FLASH_32M */ - -/* 32MB */ -#ifdef SCB9328_FLASH_32M -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#else - -/* 16MB */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#endif /* SCB9328_FLASH_32M */ - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CONFIG_SYS_FLASH_CFI - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */ - -#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -/* Setup for PA23 which is Reset Default PA23 but has to become - CS5 */ - -#define CONFIG_SYS_GPR_A_VAL 0x00800000 -#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe - -#define CONFIG_SYS_MONITOR_BASE 0x10000000 -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ - -/* - * CSxU_VAL: - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | - * - * CSxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| - */ - -#define CONFIG_SYS_CS0U_VAL 0x000F2000 -#define CONFIG_SYS_CS0L_VAL 0x11110d01 -#define CONFIG_SYS_CS1U_VAL 0x000F0a00 -#define CONFIG_SYS_CS1L_VAL 0x11110601 -#define CONFIG_SYS_CS2U_VAL 0x0 -#define CONFIG_SYS_CS2L_VAL 0x0 - -#define CONFIG_SYS_CS3U_VAL 0x000FFFFF -#define CONFIG_SYS_CS3L_VAL 0x00000303 - -#define CONFIG_SYS_CS4U_VAL 0x000F0a00 -#define CONFIG_SYS_CS4L_VAL 0x11110301 - -/* CNC == 3 too long - #define CONFIG_SYS_CS5U_VAL 0x0000C210 */ - -/* #define CONFIG_SYS_CS5U_VAL 0x00008400 - mal laenger mahcen, ob der bei 150MHz laenger haelt dann und - kaum langsamer ist */ -/* #define CONFIG_SYS_CS5U_VAL 0x00009400 - #define CONFIG_SYS_CS5L_VAL 0x11010D03 */ - -#define CONFIG_SYS_CS5U_VAL 0x00008400 -#define CONFIG_SYS_CS5L_VAL 0x00000D03 - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x16000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) - -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz - - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz - - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz - - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ - -#define CPU200 - -#ifdef CPU200 -#define CONFIG_SYS_MPCTL0_VAL 0x00321431 -#else -#define CONFIG_SYS_MPCTL0_VAL 0x040e200e -#endif - -/* #define BUS64 */ -#define BUS72 - -#ifdef BUS72 -#define CONFIG_SYS_SPCTL0_VAL 0x04002400 -#endif - -#ifdef BUS96 -#define CONFIG_SYS_SPCTL0_VAL 0x04001800 -#endif - -#ifdef BUS64 -#define CONFIG_SYS_SPCTL0_VAL 0x08001800 -#endif - -/* Das ist der BCLK Divider, der aus der System PLL - BCLK und HCLK erzeugt: - 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 - 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 - 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 - 0x2f001003 : 192MHz/5=38,4MHz - 0x2f000003 : 64MHz/1 - Bit 22: SPLL Restart - Bit 21: MPLL Restart */ - -#ifdef BUS64 -#define CONFIG_SYS_CSCR_VAL 0x2f030003 -#endif - -#ifdef BUS72 -#define CONFIG_SYS_CSCR_VAL 0x2f030403 -#endif - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CONFIG_SYS_LOAD_ADDR 0x08400000 - -#define MHZ16QUARZINUSE - -#ifdef MHZ16QUARZINUSE -#define CONFIG_SYSPLL_CLK_FREQ 16000000 -#else -#define CONFIG_SYSPLL_CLK_FREQ 16780000 -#endif - -#define CONFIG_SYS_CLK_FREQ 16780000 - -/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ -#define CONFIG_SYS_FMCR_VAL 0x00000001 - -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef BUS96 -#define CONFIG_SYS_PCDR_VAL 0x000b00b5 -#endif - -#ifdef BUS64 -#define CONFIG_SYS_PCDR_VAL 0x000b00b3 -#endif - -#ifdef BUS72 -#define CONFIG_SYS_PCDR_VAL 0x000b00b8 -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From f73db66d6205438e499c725416c222642167c6d9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:28 -0600 Subject: arm: Remove tk71 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-kirkwood/Kconfig | 4 -- board/karo/tk71/Kconfig | 12 ---- board/karo/tk71/MAINTAINERS | 6 -- board/karo/tk71/Makefile | 9 --- board/karo/tk71/kwbimage.cfg | 158 ----------------------------------------- board/karo/tk71/tk71.c | 150 -------------------------------------- configs/tk71_defconfig | 6 -- include/configs/tk71.h | 112 ----------------------------- 8 files changed, 457 deletions(-) delete mode 100644 board/karo/tk71/Kconfig delete mode 100644 board/karo/tk71/MAINTAINERS delete mode 100644 board/karo/tk71/Makefile delete mode 100644 board/karo/tk71/kwbimage.cfg delete mode 100644 board/karo/tk71/tk71.c delete mode 100644 configs/tk71_defconfig delete mode 100644 include/configs/tk71.h (limited to 'include') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3002c04098b..c053602a509 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -25,9 +25,6 @@ config TARGET_DNS325 config TARGET_ICONNECT bool "iconnect Board" -config TARGET_TK71 - bool "TK71 Board" - config TARGET_KM_KIRKWOOD bool "KM_KIRKWOOD Board" @@ -64,7 +61,6 @@ source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" source "board/iomega/iconnect/Kconfig" -source "board/karo/tk71/Kconfig" source "board/keymile/km_arm/Kconfig" source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig" diff --git a/board/karo/tk71/Kconfig b/board/karo/tk71/Kconfig deleted file mode 100644 index 7b3d5486671..00000000000 --- a/board/karo/tk71/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TK71 - -config SYS_BOARD - default "tk71" - -config SYS_VENDOR - default "karo" - -config SYS_CONFIG_NAME - default "tk71" - -endif diff --git a/board/karo/tk71/MAINTAINERS b/board/karo/tk71/MAINTAINERS deleted file mode 100644 index ac85d6b44c5..00000000000 --- a/board/karo/tk71/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TK71 BOARD -#M: - -S: Maintained -F: board/karo/tk71/ -F: include/configs/tk71.h -F: configs/tk71_defconfig diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile deleted file mode 100644 index 0e0df770f7a..00000000000 --- a/board/karo/tk71/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2012 Marek Vasut -# on behalf of DENX Software Engineering GmbH -# -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := tk71.o diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg deleted file mode 100644 index a32e27c6a09..00000000000 --- a/board/karo/tk71/kwbimage.cfg +++ /dev/null @@ -1,158 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# adopted to TK71 by -# Nils Faerber -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000034 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x00000000 # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 10, Cs0size=512Mb -# bit5-4: 01, Cs1width=x16 -# bit7-6: 10, Cs1size=512Mb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000F80F # CPU ODT Control -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm -# bit14: 1, M_STARTBURST_IN ODT: Enabled -# bit15: 1, DDR IO ODT Unit: Use ODT block -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c deleted file mode 100644 index 35546d24e87..00000000000 --- a/board/karo/tk71/tk71.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define TK71_OE_LOW (~0) -#define TK71_OE_HIGH (~0) -#define TK71_OE_VAL_LOW (0) -#define TK71_OE_VAL_HIGH (0) - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(TK71_OE_VAL_LOW, - TK71_OE_VAL_HIGH, - TK71_OE_LOW, TK71_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_NET - -#define MV88E1116_MAC_CTRL2_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -static void mv_phy_88e1118_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1118 Initialized on %s\n", name); -} - -/* Configure and enable Switch and PHY */ -void reset_phy(void) -{ - /* configure and initialize PHY */ - mv_phy_88e1118_init("egiga0"); - -} -#endif diff --git a/configs/tk71_defconfig b/configs/tk71_defconfig deleted file mode 100644 index 5e2a0b84c92..00000000000 --- a/configs/tk71_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_TK71=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/tk71.h b/include/configs/tk71.h deleted file mode 100644 index 46e8c90b455..00000000000 --- a/include/configs/tk71.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_TK71_H__ -#define __CONFIG_TK71_H__ - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKa-Ro TK71" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define MACH_TYPE_TK71 2399 -#define CONFIG_MACH_TYPE MACH_TYPE_TK71 - -/* - * Commands configuration - */ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * NAND flash - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_JFFS2_NAND -#define CONFIG_JFFS2_DEV "nand0,3" -#endif - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} -#define CONFIG_PHY_BASE_ADR 0x08 -#endif - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_KIRKWOOD -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#endif - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_NOWHERE -#endif - -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_ADDR 0x80000 -#define CONFIG_ENV_OFFSET 0x80000 - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;" -#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \ - "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \ - "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \ - "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \ - "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0" -#define MTDIDS_DEFAULT "nand0=orion_nand" -#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS - -#define PHYS_SDRAM_1 0x00000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ - -#endif /* __CONFIG_TK71_H__ */ -- cgit v1.3.1 From 0c81f37d9a22b38368296ffd9ea008add8657f7d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:29 -0600 Subject: arm: Remove tt01 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/hale/tt01/Kconfig | 15 --- board/hale/tt01/MAINTAINERS | 6 - board/hale/tt01/Makefile | 10 -- board/hale/tt01/lowlevel_init.S | 16 --- board/hale/tt01/tt01.c | 243 ------------------------------------ configs/tt01_defconfig | 4 - include/configs/tt01.h | 266 ---------------------------------------- 8 files changed, 565 deletions(-) delete mode 100644 board/hale/tt01/Kconfig delete mode 100644 board/hale/tt01/MAINTAINERS delete mode 100644 board/hale/tt01/Makefile delete mode 100644 board/hale/tt01/lowlevel_init.S delete mode 100644 board/hale/tt01/tt01.c delete mode 100644 configs/tt01_defconfig delete mode 100644 include/configs/tt01.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ad3f554ccc5..4b684eb07ee 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -244,10 +244,6 @@ config TARGET_MX31PDK select CPU_ARM1136 select SUPPORT_SPL -config TARGET_TT01 - bool "Support tt01" - select CPU_ARM1136 - config TARGET_WOODBURN bool "Support woodburn" select CPU_ARM1136 @@ -764,7 +760,6 @@ source "board/freescale/mx53smd/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" -source "board/hale/tt01/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" diff --git a/board/hale/tt01/Kconfig b/board/hale/tt01/Kconfig deleted file mode 100644 index af9828a4bf0..00000000000 --- a/board/hale/tt01/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TT01 - -config SYS_BOARD - default "tt01" - -config SYS_VENDOR - default "hale" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "tt01" - -endif diff --git a/board/hale/tt01/MAINTAINERS b/board/hale/tt01/MAINTAINERS deleted file mode 100644 index 2f582be8f3a..00000000000 --- a/board/hale/tt01/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TT01 BOARD -M: Helmut Raiger -S: Maintained -F: board/hale/tt01/ -F: include/configs/tt01.h -F: configs/tt01_defconfig diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile deleted file mode 100644 index e06a040422b..00000000000 --- a/board/hale/tt01/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2009 HALE electronic -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := tt01.o -obj-y += lowlevel_init.o diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S deleted file mode 100644 index 54132a18fb4..00000000000 --- a/board/hale/tt01/lowlevel_init.S +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2009 Magnus Lilja - * (C) Copyright 2011 Helmut Raiger - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - mov pc, lr diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c deleted file mode 100644 index 011aed08417..00000000000 --- a/board/hale/tt01/tt01.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2011 HALE electronic - * (C) Copyright 2009 Magnus Lilja - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define BOARD_STRING "Board: HALE TT-01" - -/* Clock configuration */ -#define CCM_CCMR_SETUP 0x074B0BF5 - -static void board_setup_clocks(void) -{ - struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE; - volatile int wait = 0x10000; - - writel(CCM_CCMR_SETUP, &ccm->ccmr); - while (wait--) - ; - - writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr); - writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); - - /* Set up clock to 532MHz */ - writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | - PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | - PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | - PDR0_MCU_PODF(0), &ccm->pdr0); - writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12), - &ccm->mpctl); - writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1), - &ccm->spctl); -} - -/* DRAM configuration */ - -#define ESDMISC_MDDR_SETUP 0x00000004 -#define ESDMISC_MDDR_RESET_DL 0x0000000c -/* - * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: - * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 - * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 - * tRCD = 011, tRC = 010 - * note: all but tWTR (1), tRC (111) are reset defaults, - * the same values work in the jtag configuration - * - * Bluetechnix setup has 0x75e73a (for 128MB) = - * 0b 0111 0101 1110 0111 0011 1010 - * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 - * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 - * tRCD = 011, tRC = 010 - */ -#define ESDCFG0_MDDR_SETUP 0x006ac73a -#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) -#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ(2) | ESDCTL_BL(1)) -#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) -#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) -#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) -#define ESDCTL_RW ESDCTL_SETTINGS - -static void board_setup_sdram(void) -{ - u32 *pad; - struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; - - /* - * setup pad control for the controller pins - * no loopback, no pull, no keeper, no open drain, - * standard input, standard drive, slow slew rate - */ - for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B; - pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++) - *pad = 0; - - /* set up MX31 DDR Memory Controller */ - writel(ESDMISC_MDDR_SETUP, &esdc->misc); - writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0); - - /* perform DDR init sequence for CSD0 */ - writel(ESDCTL_PRECHARGE, &esdc->ctl0); - writel(0x12344321, CSD0_BASE+0x0f00); - writel(ESDCTL_AUTOREFRESH, &esdc->ctl0); - writel(0x12344321, CSD0_BASE); - writel(0x12344321, CSD0_BASE); - writel(ESDCTL_LOADMODEREG, &esdc->ctl0); - writeb(0xda, CSD0_BASE+0x33); - writeb(0xff, CSD0_BASE+0x1000000); - writel(ESDCTL_RW, &esdc->ctl0); - writel(0xDEADBEEF, CSD0_BASE); - writel(ESDMISC_MDDR_RESET_DL, &esdc->misc); -} - -static void tt01_spi3_hw_init(void) -{ - /* CSPI3 */ - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); - /* CSPI3, SS0 = Atlas */ - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); - - /* start CSPI3 clock (3 = always on except if PLL off) */ - setbits_le32(CCM_CGR0, 3 << 16); -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - /* CS4: FPGA incl. network controller */ - struct mxc_weimcs cs4 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) - }; - - /* this seems essential, won't start without, but why? */ - writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF); - - board_setup_clocks(); - board_setup_sdram(); - mxc_setup_weimcs(4, &cs4); - - /* Setup UART2 and SPI3 pins */ - mx31_uart2_hw_init(); - tt01_spi3_hw_init(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts(BOARD_STRING "\n"); - return 0; -} - -#ifdef CONFIG_MXC_MMC -int board_mmc_init(bd_t *bis) -{ - u32 val; - struct pmic *p; - int ret; - - /* - * this is the first driver to use the pmic, so call - * pmic_init() here. board_late_init() is too late for - * the MMC driver. - */ - - ret = pmic_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - /* configure pins for SDHC1 only */ - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC)); - - /* turn on power V_MMC1 */ - if (pmic_reg_read(p, REG_MODE_1, &val) < 0) - pmic_reg_write(p, REG_MODE_1, val | VMMC1EN); - - return mxc_mmc_init(bis); -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -void video_get_info_str(int line_number, char *info) -{ - u32 srev = get_cpu_rev(); - - switch (line_number) { - case 2: - sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz", - (srev & 0xF0) >> 4, (srev & 0x0F), - ((srev & 0x8000) ? " unknown" : ""), - mxc_get_clock(MXC_ARM_CLK) / 1000000); - break; - case 3: - strcpy(info, " " BOARD_STRING); - break; - default: - info[0] = 0; - } -} -#endif diff --git a/configs/tt01_defconfig b/configs/tt01_defconfig deleted file mode 100644 index 08f9f7bdca6..00000000000 --- a/configs/tt01_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TT01=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="TT01> " diff --git a/include/configs/tt01.h b/include/configs/tt01.h deleted file mode 100644 index ca1e2e25fb5..00000000000 --- a/include/configs/tt01.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * (C) Copyright 2011 HALE electronic - * (C) Copyright 2008 Magnus Lilja - * - * Configuration settings for the HALE TT-01 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_MX31 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */ -#define CONFIG_SYS_TEXT_BASE 0xA0000000 - - -/* - * Physical Memory Map: - * CS settings are defined by i.MX31: - * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 - * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 - * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. - * - * HALE set-up of the bluetechnix board for now is: - * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface - * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 - * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) - * the flash chip is a mirrorbit S29WS256N ! - * - the PSRAM is hooked to CS5 (0xB6000000) - * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 - * - 64Mbit = 8MByte (will go away in the production set-up) - * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: - * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks - * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface - * - * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM - * is not used right now. We should be able to reduce the SOM to NAND flash - * only and boot from there. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) - -/* default load address, 1MB up the road */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) - -/* Size of malloc() pool, make sure possible frame buffer fits */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) - -/* memtest works on all but the last 1MB (u-boot) and malloc area */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END \ - (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) - -/* CFI FLASH driver setup */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_SPANSION_S29WS_N -/* - * TODO: Bluetechnix (the supplier of the SOM) did define these values - * in their original version of u-boot (1.2 or so). This should be - * reviewed. - * - * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - * #define CONFIG_SYS_FLASH_PROTECTION - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ - -/* - * FLASH and environment organization, only the Spansion chip is supported: - * - it has 254 * 128kB + 8 * 32kB blocks - * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF - * and 2 sectors with 128k as environment = - * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF - * - this could be less, but this is only for developer versions of the board - * and no-one is going to use the NOR flash anyway. - * - * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is - * way to large, but it avoids ENV overwrite (when updating u-boot) in case - * size breaks the next boundary (as it has with 128k). - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* Hardware drivers */ - -/* - * on TT-01 UART1 pins are used by Audio, so we use UART2 - * TT-01 implements a hardware that turns off components depending on - * the power level. In PL=1 the RS232 transceiver is usually off, - * make sure that the transceiver is enabled during PL=1 for testing! - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_MXC_SPI -#define CONFIG_MXC_GPIO - -/* MC13783 connected to CSPI3 and SS0 */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL - -#define CONFIG_FSL_PMIC_BUS 2 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 - -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -/* console is UART2 on TT-01 */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* ethernet setup for the onboard smc9118 */ -#define CONFIG_MII -#define CONFIG_SMC911X -/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ -#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) -#define CONFIG_SMC911X_16_BIT - -/* mmc driver */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MXC_MMC -#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR - -/* video support */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MX3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -/* splash image won't work with NAND boot, use preboot script */ -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */ -#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */ - -/* allow stdin, stdout and stderr variables to redirect output */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */ -#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */ -#define CONFIG_PREBOOT - -/* allow decompressing max. 4MB */ -#define CONFIG_VIDEO_BMP_GZIP -/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */ -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024) - -/* - * Command definition - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND -/* - * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support - * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports - * a software locking scheme. - */ -#define CONFIG_CMD_BMP - -#define CONFIG_BOOTDELAY 3 - -/* - * currently a default setting for booting via script is implemented - * set user to login name and serverip to tftp host, define your - * boot behaviour in bootscript.loginname - * - * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c) - * - * This set-up is for the L5F30947T04 by Epson, which is - * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync - * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -"videomode=epson\0" \ -"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \ - "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \ -"bootcmd=dhcp bootscript.${user}; source\0" - -#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ -#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_CMDLINE_EDITING - -/* MMC boot support */ -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -#define CONFIG_NAND_MXC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * actually this is nothing someone wants to configure! - * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() - * is not used by the driver. - */ -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR -#define CONFIG_MXC_NAND_HWECC - -/* the current u-boot driver does not use the nand flash setup! */ -#define CONFIG_SYS_NAND_LARGEPAGE -/* - * it's not 16 bit: - * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT - * the current u-boot mxc_nand.c tries to auto-detect, but this only - * reads the boot settings during reset (which might be wrong) - */ - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From b928e658f4f342d0834356ec7e37aef1b3e30829 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:30 -0600 Subject: arm: Remove versatileab board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 8 +- arch/arm/Makefile | 1 - arch/arm/mach-versatile/Kconfig | 15 --- board/armltd/versatile/MAINTAINERS | 8 -- board/armltd/versatile/Makefile | 9 -- board/armltd/versatile/lowlevel_init.S | 17 --- board/armltd/versatile/versatile.c | 99 --------------- configs/versatileab_defconfig | 18 --- configs/versatilepb_defconfig | 18 --- configs/versatileqemu_defconfig | 18 --- include/configs/versatile.h | 214 --------------------------------- 11 files changed, 1 insertion(+), 424 deletions(-) delete mode 100644 arch/arm/mach-versatile/Kconfig delete mode 100644 board/armltd/versatile/MAINTAINERS delete mode 100644 board/armltd/versatile/Makefile delete mode 100644 board/armltd/versatile/lowlevel_init.S delete mode 100644 board/armltd/versatile/versatile.c delete mode 100644 configs/versatileab_defconfig delete mode 100644 configs/versatilepb_defconfig delete mode 100644 configs/versatileqemu_defconfig delete mode 100644 include/configs/versatile.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4b684eb07ee..3e650beb5b8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -70,7 +70,7 @@ config SYS_L2CACHE_OFF choice prompt "Target select" - default ARCH_VERSATILE + default TARGET_HIKEY config ARCH_AT91 bool "Atmel AT91" @@ -227,10 +227,6 @@ config TARGET_X600 select CPU_ARM926EJS select SUPPORT_SPL -config ARCH_VERSATILE - bool "ARM Ltd. Versatile family" - select CPU_ARM926EJS - config TARGET_IMX31_PHYCORE bool "Support imx31_phycore" select CPU_ARM1136 @@ -709,8 +705,6 @@ source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-uniphier/Kconfig" -source "arch/arm/mach-versatile/Kconfig" - source "arch/arm/mach-zynq/Kconfig" source "arch/arm/cpu/armv7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1eca815c08b..13a2780a0e7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -58,7 +58,6 @@ machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier -machine-$(CONFIG_ARCH_VERSATILE) += versatile machine-$(CONFIG_ARCH_ZYNQ) += zynq machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig deleted file mode 100644 index d2e76f4afc6..00000000000 --- a/arch/arm/mach-versatile/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if ARCH_VERSATILE - -config SYS_BOARD - default "versatile" - -config SYS_VENDOR - default "armltd" - -config SYS_SOC - default "versatile" - -config SYS_CONFIG_NAME - default "versatile" - -endif diff --git a/board/armltd/versatile/MAINTAINERS b/board/armltd/versatile/MAINTAINERS deleted file mode 100644 index a56dd99bb33..00000000000 --- a/board/armltd/versatile/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -VERSATILE BOARD -#M: - -S: Maintained -F: board/armltd/versatile/ -F: include/configs/versatile.h -F: configs/versatileab_defconfig -F: configs/versatilepb_defconfig -F: configs/versatileqemu_defconfig diff --git a/board/armltd/versatile/Makefile b/board/armltd/versatile/Makefile deleted file mode 100644 index a09a0ae550e..00000000000 --- a/board/armltd/versatile/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := versatile.o -obj-y += lowlevel_init.o diff --git a/board/armltd/versatile/lowlevel_init.S b/board/armltd/versatile/lowlevel_init.S deleted file mode 100644 index 539ba41e668..00000000000 --- a/board/armltd/versatile/lowlevel_init.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003, ARM Ltd. - * Philippe Robin, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - - /* All done by Versatile's boot monitor! */ - mov pc, lr diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c deleted file mode 100644 index 4e2d3421d8b..00000000000 --- a/board/armltd/versatile/versatile.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_early_init_f (void) -{ - /* - * set clock frequency: - * VERSATILE_REFCLK is 32KHz - * VERSATILE_TIMCLK is 1MHz - */ - *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= - ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); - - return 0; -} - -int board_init (void) -{ - /* arch number of Versatile Board */ -#ifdef CONFIG_ARCH_VERSATILE_AB - gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; -#else - gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - gd->flags = 0; - - icache_enable (); - - return 0; -} - - -int misc_init_r (void) -{ - setenv("verify", "n"); - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/configs/versatileab_defconfig b/configs/versatileab_defconfig deleted file mode 100644 index 3dc7d19660b..00000000000 --- a/configs/versatileab_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB" -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_MISC is not set diff --git a/configs/versatilepb_defconfig b/configs/versatilepb_defconfig deleted file mode 100644 index 9fe83b97c30..00000000000 --- a/configs/versatilepb_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB" -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_MISC is not set diff --git a/configs/versatileqemu_defconfig b/configs/versatileqemu_defconfig deleted file mode 100644 index 9ddef4d9bdd..00000000000 --- a/configs/versatileqemu_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB" -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_MISC is not set diff --git a/include/configs/versatile.h b/include/configs/versatile.h deleted file mode 100644 index 636ca436d9f..00000000000 --- a/include/configs/versatile.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * Configuration for Versatile PB. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */ -#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ - -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 - -#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ -#define CONFIG_SYS_TIMER_RATE (1000000 / 256) -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN - -/* - * control registers - */ -#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ - -/* - * System controller bit assignment - */ -#define VERSATILE_REFCLK 0 -#define VERSATILE_TIMCLK 1 - -#define VERSATILE_TIMER1_EnSel 15 -#define VERSATILE_TIMER2_EnSel 17 -#define VERSATILE_TIMER3_EnSel 19 -#define VERSATILE_TIMER4_EnSel 21 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE 8192 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0x10010000 -#undef CONFIG_SMC91111_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS \ - {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1 } -#define CONFIG_CONS_INDEX 0 - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_SYS_SERIAL0 0x101F1000 -#define CONFIG_SYS_SERIAL1 0x101F2000 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ - "console=ttyAMA0,38400n1" - -/* - * Static configuration when assigning fixed address - */ -#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Monitor Command Prompt */ -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_ARCH_VERSATILE_AB -# define CONFIG_SYS_PROMPT "VersatileAB # " -#else -# define CONFIG_SYS_PROMPT "VersatilePB # " -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -#define CONFIG_BOARD_EARLY_INIT_F - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_ARCH_VERSATILE_QEMU -#define CONFIG_SYS_TEXT_BASE 0x10000 -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#else -#define CONFIG_SYS_TEXT_BASE 0x01000000 -/* - * Use the CFI flash driver for ease of use - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_ENV_IS_IN_FLASH 1 -/* - * System control register - */ -#define VERSATILE_SYS_BASE 0x10000000 -#define VERSATILE_SYS_FLASH_OFFSET 0x4C -#define VERSATILE_FLASHCTRL \ - (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) -/* Enable writing to flash */ -#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ - -/* - * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block - * i.e. - * the bottom "sector" (bottom boot), or top "sector" - * (top boot), is a seperate erase region divided into - * 4 (equal) smaller sectors. This, notionally, allows - * quicker erase/rewrire of the most frequently changed - * area...... - * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4 - */ - -#ifdef CONFIG_ARCH_VERSATILE_AB -#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */ -#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE) -#define CONFIG_SYS_MAX_FLASH_SECT (520) -#endif - -#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ -#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ -#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT (260) -#endif - -#define CONFIG_SYS_FLASH_BASE 0x34000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE) - -/* The ARM Boot Monitor is shipped in the lowest sector of flash */ - -#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE) -#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From bee2b99d06014e8c461c2656984b11f97430d6c3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:31 -0600 Subject: arm: Remove vision2 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass Acked-by: Stefano Babic --- arch/arm/Kconfig | 5 - board/ttcontrol/vision2/Kconfig | 15 - board/ttcontrol/vision2/MAINTAINERS | 6 - board/ttcontrol/vision2/Makefile | 9 - board/ttcontrol/vision2/imximage_hynix.cfg | 212 ----------- board/ttcontrol/vision2/vision2.c | 572 ----------------------------- configs/vision2_defconfig | 7 - doc/README.watchdog | 1 + include/configs/vision2.h | 199 ---------- 9 files changed, 1 insertion(+), 1025 deletions(-) delete mode 100644 board/ttcontrol/vision2/Kconfig delete mode 100644 board/ttcontrol/vision2/MAINTAINERS delete mode 100644 board/ttcontrol/vision2/Makefile delete mode 100644 board/ttcontrol/vision2/imximage_hynix.cfg delete mode 100644 board/ttcontrol/vision2/vision2.c delete mode 100644 configs/vision2_defconfig delete mode 100644 include/configs/vision2.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3e650beb5b8..e892c54559e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -473,10 +473,6 @@ config TARGET_MX53SMD bool "Support mx53smd" select CPU_V7 -config TARGET_VISION2 - bool "Support vision2" - select CPU_V7 - config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 @@ -789,7 +785,6 @@ source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" source "board/technologic/ts4800/Kconfig" -source "board/ttcontrol/vision2/Kconfig" source "board/vpac270/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" diff --git a/board/ttcontrol/vision2/Kconfig b/board/ttcontrol/vision2/Kconfig deleted file mode 100644 index cacd2c5dfe2..00000000000 --- a/board/ttcontrol/vision2/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_VISION2 - -config SYS_BOARD - default "vision2" - -config SYS_VENDOR - default "ttcontrol" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "vision2" - -endif diff --git a/board/ttcontrol/vision2/MAINTAINERS b/board/ttcontrol/vision2/MAINTAINERS deleted file mode 100644 index cfc9903c712..00000000000 --- a/board/ttcontrol/vision2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -VISION2 BOARD -M: Stefano Babic -S: Maintained -F: board/ttcontrol/vision2/ -F: include/configs/vision2.h -F: configs/vision2_defconfig diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile deleted file mode 100644 index c3e1e87f3de..00000000000 --- a/board/ttcontrol/vision2/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2009 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := vision2.o diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg deleted file mode 100644 index c74973edec1..00000000000 --- a/board/ttcontrol/vision2/imximage_hynix.cfg +++ /dev/null @@ -1,212 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * (C) Copyright 2010 - * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* - * Boot Device : one of - * spi, nand, onenand, sd - */ -BOOT_FROM spi - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * ####################### - * ### Disable WDOG ### - * ####################### - */ -DATA 2 0x73f98000 0x30 - -/* - * ####################### - * ### SET DDR Clk ### - * ####################### - */ -/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */ -DATA 4 0x73FD4018 0x000024C0 - -/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */ -DATA 4 0x73FD4038 0x2010241 - -/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */ -DATA 4 0x73fa8600 0x00000107 -/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */ -DATA 4 0x73fa8604 0x00000107 -/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ -DATA 4 0x73fa8608 0x00000187 -/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */ -DATA 4 0x73fa860c 0x00000187 -/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */ -DATA 4 0x73fa8614 0x00000107 -/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */ -DATA 4 0x73fa86a8 0x00000187 - -/* - * ####################### - * ### Settings IOMUXC ### - * ####################### - */ -/* - * DDR IOMUX configuration - * Control, Data, Address pads are in their default state: HIGH DS, FAST SR. - * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS - */ -DATA 4 0x73fa84b8 0x000000e7 -/* PVTC MAX (at GPC, PGR reg) */ -/* DATA 4 0x73FD8004 0x1fc00000 */ - -/* DQM0 DS high slew rate slow */ -DATA 4 0x73fa84d4 0x000000e4 -/* DQM1 DS high slew rate slow */ -DATA 4 0x73fa84d8 0x000000e4 -/* DQM2 DS high slew rate slow */ -DATA 4 0x73fa84dc 0x000000e4 -/* DQM3 DS high slew rate slow */ -DATA 4 0x73fa84e0 0x000000e4 - -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */ -DATA 4 0x73fa84bc 0x000000c4 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */ -DATA 4 0x73fa84c0 0x000000c4 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */ -DATA 4 0x73fa84c4 0x000000c4 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */ -DATA 4 0x73fa84c8 0x000000c4 - -/* DRAM_DATA B0 */ -DATA 4 0x73fa88a4 0x00000004 -/* DRAM_DATA B1 */ -DATA 4 0x73fa88ac 0x00000004 -/* DRAM_DATA B2 */ -DATA 4 0x73fa88b8 0x00000004 -/* DRAM_DATA B3 */ -DATA 4 0x73fa882c 0x00000004 - -/* DRAM_DATA B0 slew rate */ -DATA 4 0x73fa8878 0x00000000 -/* DRAM_DATA B1 slew rate */ -DATA 4 0x73fa8880 0x00000000 -/* DRAM_DATA B2 slew rate */ -DATA 4 0x73fa888c 0x00000000 -/* DRAM_DATA B3 slew rate */ -DATA 4 0x73fa889c 0x00000000 - -/* - * ####################### - * ### Configure SDRAM ### - * ####################### - */ - -/* Configure CS0 */ -/* ####################### */ - -/* ESDCTL0: Enable controller */ -DATA 4 0x83fd9000 0x83220000 - -/* Init DRAM on CS0 */ -/* ESDSCR: Precharge command */ -DATA 4 0x83fd9014 0x04008008 -/* ESDSCR: Refresh command */ -DATA 4 0x83fd9014 0x00008010 -/* ESDSCR: Refresh command */ -DATA 4 0x83fd9014 0x00008010 -/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ -DATA 4 0x83fd9014 0x00338018 -/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ -DATA 4 0x83fd9014 0x0020801a -/* ESDSCR */ -DATA 4 0x83fd9014 0x00008000 - -/* ESDSCR: EMR with full Drive strength */ -/* DATA 4 0x83fd9014 0x0000801a */ - -/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */ -DATA 4 0x83fd9000 0xC3220000 - -/* - * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks - * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks - * DATA 4 0x83fd9004 0xC33574AA - */ -/* - * micron mDDR - * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks - * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks - * DATA 4 0x83FD9004 0x101564a8 - */ -/* - * hynix mDDR - * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks - * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks - */ -DATA 4 0x83FD9004 0x704564a8 - -/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */ -DATA 4 0x83fd9010 0x000a1700 - -/* Configure CS1 */ -/* ####################### */ - -/* ESDCTL1: Enable controller */ -DATA 4 0x83fd9008 0x83220000 - -/* Init DRAM on CS1 */ -/* ESDSCR: Precharge command */ -DATA 4 0x83fd9014 0x0400800c -/* ESDSCR: Refresh command */ -DATA 4 0x83fd9014 0x00008014 -/* ESDSCR: Refresh command */ -DATA 4 0x83fd9014 0x00008014 -/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */ -DATA 4 0x83fd9014 0x0033801c -/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */ -DATA 4 0x83fd9014 0x0020801e -/* ESDSCR */ -DATA 4 0x83fd9014 0x00008004 - -/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */ -DATA 4 0x83fd9008 0xC3220000 -/* - * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks - * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks - * DATA 4 0x83fd900c 0xC33574AA - */ -/* - * micron mDDR - * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks - * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks - * DATA 4 0x83FD900C 0x101564a8 - */ -/* - * hynix mDDR - * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks - * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks - */ -DATA 4 0x83FD900C 0x704564a8 - -/* ESDSCR (mDRAM configuration finished) */ -DATA 4 0x83FD9014 0x00000004 - -/* ESDSCR - clear "configuration request" bit */ -DATA 4 0x83fd9014 0x00000000 diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c deleted file mode 100644 index 247991d5888..00000000000 --- a/board/ttcontrol/vision2/vision2.c +++ /dev/null @@ -1,572 +0,0 @@ -/* - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -static struct fb_videomode const nec_nl6448bc26_09c = { - "NEC_NL6448BC26-09C", - 60, /* Refresh */ - 640, /* xres */ - 480, /* yres */ - 37650, /* pixclock = 26.56Mhz */ - 48, /* left margin */ - 16, /* right margin */ - 31, /* upper margin */ - 12, /* lower margin */ - 96, /* hsync-len */ - 2, /* vsync-len */ - 0, /* sync */ - FB_VMODE_NONINTERLACED, /* vmode */ - 0, /* flag */ -}; - -#ifdef CONFIG_HW_WATCHDOG -#include -void hw_watchdog_reset(void) -{ - int val; - - /* toggle watchdog trigger pin */ - val = gpio_get_value(IMX_GPIO_NR(3, 2)); - val = val ? 0 : 1; - gpio_set_value(IMX_GPIO_NR(3, 2), val); -} -#endif - -static void init_drive_strength(void) -{ - static const iomux_v3_cfg_t ddr_pads[] = { - NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0), - NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE), - NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0), - NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS, - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS, - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE), - NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0), - NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0), - NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0), - NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0), - NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0), - NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX51_GRP_INMODE1, 0), - NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED), - NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED), - NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED), - NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED), - - NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3, - MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -static void setup_weim(void) -{ - struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; - - pweim->cs0gcr1 = 0x004100b9; - pweim->cs0gcr2 = 0x00000001; - pweim->cs0rcr1 = 0x0a018000; - pweim->cs0rcr2 = 0; - pweim->cs0wcr1 = 0x0704a240; -} - -static void setup_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - MX51_PAD_EIM_D25__UART3_RXD, /* console RX */ - MX51_PAD_EIM_D26__UART3_TXD, /* console TX */ - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 1) ? 121 : -1; -} - -void spi_io_init(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS | - PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS | - PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS | - PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} - -static void reset_peripherals(int reset) -{ -#ifdef CONFIG_VISION2_HW_1_0 - static const iomux_v3_cfg_t fec_cfg_pads[] = { - /* RXD1 */ - NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL), - /* RXD2 */ - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL), - /* RXD3 */ - NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL), - /* RXER */ - NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL), - /* COL */ - NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL), - /* RCLK */ - NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL), - /* RXD0 */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL), - }; - - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_D9__FEC_RDATA0, - NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), - MX51_PAD_EIM_CS4__FEC_RX_ER, - NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), - }; -#endif - - if (reset) { - - /* reset_n is on NANDF_D15 */ - gpio_direction_output(IMX_GPIO_NR(3, 25), 0); - -#ifdef CONFIG_VISION2_HW_1_0 - /* - * set FEC Configuration lines - * set levels of FEC config lines - */ - gpio_direction_output(IMX_GPIO_NR(3, 11), 0); - gpio_direction_output(IMX_GPIO_NR(3, 10), 1); - gpio_direction_output(IMX_GPIO_NR(3, 31), 1); - - /* set direction of FEC config lines */ - gpio_direction_output(IMX_GPIO_NR(2, 27), 0); - gpio_direction_output(IMX_GPIO_NR(2, 28), 0); - gpio_direction_output(IMX_GPIO_NR(2, 29), 0); - gpio_direction_output(IMX_GPIO_NR(2, 23), 1); - - imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, - ARRAY_SIZE(fec_cfg_pads)); -#endif - - /* activate reset_n pin */ - imx_iomux_v3_setup_pad( - NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25, - PAD_CTL_DSE_MAX)); - } else { - /* set FEC Control lines */ - gpio_direction_input(IMX_GPIO_NR(3, 25)); - udelay(500); - -#ifdef CONFIG_VISION2_HW_1_0 - imx_iomux_v3_setup_multiple_pads(fec_pads, - ARRAY_SIZE(fec_pads)); -#endif - } -} - -static void power_init_mx51(void) -{ - unsigned int val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_PMIC); - if (ret) - return; - - p = pmic_get("FSL_PMIC"); - if (!p) - return; - - /* Write needed to Power Gate 2 register */ - pmic_reg_read(p, REG_POWER_MISC, &val); - - /* enable VCAM with 2.775V to enable read from PMIC */ - val = VCAMCONFIG | VCAMEN; - pmic_reg_write(p, REG_MODE_1, val); - - /* - * Set switchers in Auto in NORMAL mode & STANDBY mode - * Setup the switcher mode for SW1 & SW2 - */ - pmic_reg_read(p, REG_SW_4, &val); - val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | - (SWMODE_MASK << SWMODE2_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(p, REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - pmic_reg_read(p, REG_SW_5, &val); - val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | - (SWMODE_MASK << SWMODE3_SHIFT)); - val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); - pmic_reg_write(p, REG_SW_5, val); - - - /* Set VGEN3 to 1.8V, VCAM to 3.0V */ - pmic_reg_read(p, REG_SETTING_0, &val); - val &= ~(VCAM_MASK | VGEN3_MASK); - val |= VCAM_3_0; - pmic_reg_write(p, REG_SETTING_0, val); - - /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ - pmic_reg_read(p, REG_SETTING_1, &val); - val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; - pmic_reg_write(p, REG_SETTING_1, val); - - /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(p, REG_MODE_1, val); - udelay(200); - - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(p, REG_MODE_1, val); - - pmic_reg_read(p, REG_POWER_CTL2, &val); - val |= WDIRESET; - pmic_reg_write(p, REG_POWER_CTL2, val); - - udelay(2500); - -} -#endif - -static void setup_gpios(void) -{ - static const iomux_v3_cfg_t gpio_pads_1[] = { - NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* CAM_SUP_DISn */ - NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* DAB Display EN */ - NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* WDOG_TRIGGER */ - }; - - static const iomux_v3_cfg_t gpio_pads_2[] = { - NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* Display2 TxEN */ - NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* DAB Light EN */ - NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* AUDIO_MUTE */ - NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* SPARE_OUT */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* BEEPER_EN */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* POWER_OFF */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* FRAM_WE */ - NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE | - PAD_CTL_DSE_MED), /* EXPANSION_EN */ - MX51_PAD_GPIO1_2__PWM1_PWMO, - }; - - unsigned int i; - - imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1)); - - /* Now we need to trigger the watchdog */ - WATCHDOG_RESET(); - - imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2)); - - /* - * Set GPIO1_4 to high and output; it is used to reset - * the system on reboot - */ - gpio_direction_output(IMX_GPIO_NR(1, 4), 1); - - gpio_direction_output(IMX_GPIO_NR(1, 7), 0); - for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++) - gpio_direction_output(i, 0); - - gpio_direction_output(IMX_GPIO_NR(3, 30), 0); - - /* Set POWER_OFF high */ - gpio_direction_output(IMX_GPIO_NR(3, 27), 1); - - gpio_direction_output(IMX_GPIO_NR(3, 26), 0); - - gpio_direction_output(IMX_GPIO_NR(4, 26), 0); - - gpio_direction_output(IMX_GPIO_NR(4, 25), 1); - - WATCHDOG_RESET(); -} - -static void setup_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - MX51_PAD_NANDF_CS3__FEC_MDC, - NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_D9__FEC_RDATA0, - MX51_PAD_NANDF_CS6__FEC_TDATA3, - MX51_PAD_NANDF_CS5__FEC_TDATA2, - MX51_PAD_NANDF_CS4__FEC_TDATA1, - MX51_PAD_NANDF_D8__FEC_TDATA0, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), - NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_EIM_CS4__FEC_RX_ER, - NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {MMC_SDHC1_BASE_ADDR}, -}; - -int get_mmc_getcd(u8 *cd, struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = gpio_get_value(IMX_GPIO_NR(1, 0)); - else - *cd = 0; - - return 0; -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | - PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), - NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), - }; - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -void lcd_enable(void) -{ - static const iomux_v3_cfg_t lcd_pads[] = { - MX51_PAD_DI1_PIN2__DI1_PIN2, - MX51_PAD_DI1_PIN3__DI1_PIN3, - }; - - int ret; - - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - - gpio_set_value(IMX_GPIO_NR(1, 2), 1); - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2, - NO_PAD_CTRL)); - - ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666); - if (ret) - puts("LCD cannot be configured\n"); -} - -int board_early_init_f(void) -{ - - - init_drive_strength(); - - /* Setup debug led */ - gpio_direction_output(IMX_GPIO_NR(1, 6), 0); - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST)); - - /* wait a little while to give the pll time to settle */ - sdelay(100000); - - setup_weim(); - setup_uart(); - setup_fec(); - setup_gpios(); - - spi_io_init(); - - return 0; -} - -static void backlight(int on) -{ - if (on) { - gpio_set_value(IMX_GPIO_NR(3, 1), 1); - udelay(10000); - gpio_set_value(IMX_GPIO_NR(3, 4), 1); - } else { - gpio_set_value(IMX_GPIO_NR(3, 1), 0); - gpio_set_value(IMX_GPIO_NR(3, 4), 0); - } -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - lcd_enable(); - - backlight(1); - - return 0; -} - -int board_late_init(void) -{ - power_init_mx51(); - - reset_peripherals(1); - udelay(2000); - reset_peripherals(0); - udelay(2000); - - /* Early revisions require a second reset */ -#ifdef CONFIG_VISION2_HW_1_0 - reset_peripherals(1); - udelay(2000); - reset_peripherals(0); - udelay(2000); -#endif - - return 0; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int checkboard(void) -{ - puts("Board: TTControl Vision II CPU V\n"); - - return 0; -} - -int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int on; - - if (argc < 2) - return cmd_usage(cmdtp); - - on = (strcmp(argv[1], "on") == 0); - backlight(on); - - return 0; -} - -U_BOOT_CMD( - lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd, - "Vision2 Backlight", - "lcdbl [on|off]\n" -); diff --git a/configs/vision2_defconfig b/configs/vision2_defconfig deleted file mode 100644 index 962dc5b2a0b..00000000000 --- a/configs/vision2_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VISION2=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y -CONFIG_SYS_PROMPT="Vision II U-boot > " diff --git a/doc/README.watchdog b/doc/README.watchdog index 59f306b8511..b66fd6cb8ac 100644 --- a/doc/README.watchdog +++ b/doc/README.watchdog @@ -27,6 +27,7 @@ CONFIG_IMX_WATCHDOG Available for i.mx31/35/5x/6x to service the watchdog. This is not automatically set because some boards (vision2) still need to define their own hw_watchdog_reset routine. + TODO: vision2 is removed now, so perhaps this can be changed. CONFIG_XILINX_TB_WATCHDOG Available for Xilinx Axi platforms to service timebase watchdog timer. diff --git a/include/configs/vision2.h b/include/configs/vision2.h deleted file mode 100644 index b43373f1344..00000000000 --- a/include/configs/vision2.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX51-3Stack Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -#define CONFIG_MX51 /* in a mx51 */ -#define CONFIG_SYS_TEXT_BASE 0x97800000 - -#include - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_BOARD_LATE_INIT - -#ifndef MACH_TYPE_TTC_VISION2 -#define MACH_TYPE_TTC_VISION2 2775 -#endif -#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART3_BASE -#define CONFIG_MXC_GPIO -#define CONFIG_MXC_SPI -#define CONFIG_HW_WATCHDOG - - /* - * SPI Configs - * */ -#define CONFIG_FSL_SF -#define CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH_STMICRO - -/* - * Use gpio 4 pin 25 as chip select for SPI flash - * This corresponds to gpio 121 - */ -#define CONFIG_SF_DEFAULT_CS 1 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) -#define CONFIG_ENV_SIZE (4 * 1024) - -#define CONFIG_FSL_ENV_IN_SF -#define CONFIG_ENV_IS_IN_SPI_FLASH - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* - * MMC Configs - */ -#define CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_MMC - -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -#define CONFIG_CMD_DATE - -/* - * Eth Configs - */ -#define CONFIG_HAS_ETH1 -#define CONFIG_MII - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#define CONFIG_CMD_SPI - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=0x90800000\0" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HUSH_PARSER - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_BOARD_EARLY_INIT_F - -/* 166 MHz DDR RAM */ -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 -#define CONFIG_SYS_MAIN_PWR_ON - -#define CONFIG_SYS_NO_FLASH - -/* - * Framebuffer and LCD - */ -#define CONFIG_PREBOOT -#define CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#define CONFIG_BMP_16BPP -#define CONFIG_IPUV3_CLK 133000000 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 6e830dfc1aaa3780422e22c599c77dbcb0575759 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:32 -0600 Subject: arm: Remove vl_ma2sc board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-at91/Kconfig | 5 - board/BuS/vl_ma2sc/Kconfig | 12 - board/BuS/vl_ma2sc/MAINTAINERS | 7 - board/BuS/vl_ma2sc/Makefile | 12 - board/BuS/vl_ma2sc/vl_ma2sc.c | 519 ----------------------------------------- configs/vl_ma2sc_defconfig | 9 - configs/vl_ma2sc_ram_defconfig | 9 - include/configs/vl_ma2sc.h | 429 ---------------------------------- 8 files changed, 1002 deletions(-) delete mode 100644 board/BuS/vl_ma2sc/Kconfig delete mode 100644 board/BuS/vl_ma2sc/MAINTAINERS delete mode 100644 board/BuS/vl_ma2sc/Makefile delete mode 100644 board/BuS/vl_ma2sc/vl_ma2sc.c delete mode 100644 configs/vl_ma2sc_defconfig delete mode 100644 configs/vl_ma2sc_ram_defconfig delete mode 100644 include/configs/vl_ma2sc.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 26ba5ace03a..fdaf3287220 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -91,10 +91,6 @@ config TARGET_SAMA5D4EK select CPU_V7 select SUPPORT_SPL -config TARGET_VL_MA2SC - bool "Support vl_ma2sc" - select CPU_ARM926EJS - config TARGET_MEESC bool "Support meesc" select CPU_ARM926EJS @@ -132,7 +128,6 @@ source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/bluewater/snapper9260/Kconfig" -source "board/BuS/vl_ma2sc/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig deleted file mode 100644 index 848177f4c4e..00000000000 --- a/board/BuS/vl_ma2sc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_VL_MA2SC - -config SYS_BOARD - default "vl_ma2sc" - -config SYS_VENDOR - default "BuS" - -config SYS_CONFIG_NAME - default "vl_ma2sc" - -endif diff --git a/board/BuS/vl_ma2sc/MAINTAINERS b/board/BuS/vl_ma2sc/MAINTAINERS deleted file mode 100644 index b70104d52e5..00000000000 --- a/board/BuS/vl_ma2sc/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -VL_MA2SC BOARD -M: Jens Scharsig -S: Maintained -F: board/BuS/vl_ma2sc/ -F: include/configs/vl_ma2sc.h -F: configs/vl_ma2sc_defconfig -F: configs/vl_ma2sc_ram_defconfig diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile deleted file mode 100644 index d4b24ac8c2f..00000000000 --- a/board/BuS/vl_ma2sc/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2009-2012 -# Jens Scharsig -# BuS Elektronik GmbH & Co. KG -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += vl_ma2sc.o diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c deleted file mode 100644 index e4e1a8572f1..00000000000 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ /dev/null @@ -1,519 +0,0 @@ -/* - * (C) Copyright 2009-2012 - * Jens Scharsig - * BuS Elektronik GmbH & Co. KG - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_NAND -static void vl_ma2sc_nand_hw_init(void) -{ - unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; - at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ - at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ - at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ - - /* Enable CS3 */ - csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; - writel(csa, &matrix->csa[0]); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), - &pmc->pcer); - - /* Configure RDY/BSY */ -#ifdef CONFIG_SYS_NAND_READY_PIN - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); -#endif - /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -#ifdef CONFIG_MACB -static void vl_ma2sc_macb_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); - - at91_phy_reset(); - - at91_macb_hw_init(); -} -#endif - -#ifdef CONFIG_LCD -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 240, - .vl_clk = 6500000, - .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED | - ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVVD_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5), - .vl_tft = 1, - .vl_hsync_len = 5, /* Horiz Sync Pulse Width */ - .vl_left_margin = 68, /* horiz back porch */ - .vl_right_margin = 20, /* horiz front porch */ - .vl_vsync_len = 2, /* vert Sync Pulse Width */ - .vl_upper_margin = 18, /* vert back porch */ - .vl_lower_margin = 4, /* vert front porch */ - .mmio = ATMEL_BASE_LCDC, -}; - -void lcd_enable(void) -{ -} - -void lcd_disable(void) -{ -} - -static void vl_ma2sc_lcd_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ - at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ - - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ - at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ - at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - - at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ - - at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ - at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ - at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ - at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ - at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ - at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ - - at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ - - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); - gd->fb_base = ATMEL_BASE_SRAM0; -} -#endif /* Config LCD */ - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOCDE), - &pmc->pcer); - - at91_seriald_hw_init(); - - return 0; -} -#endif - -int board_init(void) -{ - at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - u32 pin; - - pin = 0x1F000001; - writel(pin, &pio->pioa.idr); - writel(pin, &pio->pioa.pudr); - writel(pin, &pio->pioa.per); - writel(pin, &pio->pioa.oer); - writel(pin, &pio->pioa.sodr); - writel((1 << 25), &pio->pioa.codr); - - pin = 0x1F000100; - writel(pin, &pio->piob.idr); - writel(pin, &pio->piob.pudr); - writel(pin, &pio->piob.per); - writel(pin, &pio->piob.oer); - writel(pin, &pio->piob.codr); - writel((1 << 24), &pio->piob.sodr); - - pin = 0x40000000; /* Pullup DRxD enbable */ - writel(pin, &pio->pioc.puer); - - pin = 0x0000000F; /* HWversion als Input */ - writel(pin, &pio->piod.idr); - writel(pin, &pio->piod.puer); - writel(pin, &pio->piod.per); - writel(pin, &pio->piod.odr); - writel(pin, &pio->piod.owdr); - - gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); - writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); - writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); - writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); - -#ifdef CONFIG_CMD_NAND - vl_ma2sc_nand_hw_init(); -#endif -#ifdef CONFIG_MACB - vl_ma2sc_macb_hw_init(); -#endif -#ifdef CONFIG_USB_OHCI_NEW - at91_uhp_hw_init(); -#endif -#ifdef CONFIG_LCD - vl_ma2sc_lcd_hw_init(); -#endif - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - uchar buffer[8]; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - u32 pin; - - buffer[0] = 0x04; - buffer[1] = 0x00; - if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) - puts("error reseting rtc clock\n\0"); - - /* read hardware version */ - - pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; - printf("Board: revision %c\n", pin); - buffer[0] = pin; - buffer[1] = 0; - setenv("revision", (char *) buffer); - - pin = 0x40000000; /* Pullup DRxD enbable */ - writel(pin, &pio->pioc.puer); - return 0; -} -#endif - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(); -#endif -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); -#endif - return rc; -} - -#ifdef CONFIG_SYS_I2C_SOFT -void i2c_init_board(void) -{ - u32 pin; - - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - u8 sda = (1<<4); - u8 scl = (1<<5); - - writel(1 << ATMEL_ID_PIOB, &pmc->pcer); - pin = sda | scl; - writel(pin, &pio->piob.idr); /* Disable Interupt */ - writel(pin, &pio->piob.pudr); - writel(pin, &pio->piob.per); - writel(pin, &pio->piob.oer); - writel(pin, &pio->piob.sodr); -} -#endif - -void watchdog_reset(void) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - u32 pin = 0x1; /* PA0 */ - - if ((readl(&pio->pioa.odsr) & pin) > 0) - writel(pin, &pio->pioa.codr); - else - writel(pin, &pio->pioa.sodr); -} - -void enable_caches(void) -{ -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - -/*---------------------------------------------------------------------------*/ - -int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = 1; - int row; - int col; - u32 pinz; - u32 pins; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ - - pins = 0x1F000000; - writel(pins, &pio->pioa.idr); - writel(pins, &pio->pioa.pudr); - writel(pins, &pio->pioa.per); - writel(pins, &pio->pioa.oer); - writel(pins, &pio->pioa.sodr); - - pinz = 0x1F000000; - writel(pinz, &pio->piob.idr); - writel(pinz, &pio->piob.pudr); - writel(pinz, &pio->piob.per); - writel(pinz, &pio->piob.oer); - writel(pinz, &pio->piob.sodr); - - for (row = 0; row < 5; row++) { - for (col = 0; col < 5; col++) { - writel((0x01000000 << col), &pio->piob.sodr); - writel((0x01000000 << row), &pio->pioa.codr); - printf("LED Test %d x %d\n", row, col); - udelay(1000000); - writel(pinz, &pio->piob.codr); - writel(pins, &pio->pioa.sodr); - } - } - return rcode; -} - -void poweroff(void) -{ - watchdog_reset(); - at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ - udelay(100); - at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ - udelay(100); - at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ - udelay(100); - while (1) - watchdog_reset(); -} - -int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = 1; - poweroff(); - return rcode; -} - -int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - u32 freq; - u32 durate; - int rcode = 1; - - freq = 1000; - durate = 2; - switch (argc) { - case 3: - durate = simple_strtoul(argv[2], NULL, 10); - case 2: - freq = simple_strtoul(argv[1], NULL, 10); - case 1: - break; - default: - cmd_usage(cmdtp); - rcode = 1; - break; - } - durate = durate * freq; - freq = 500000 / freq; - for (i = 0; i < durate; i++) { - at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ - udelay(freq); - at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ - udelay(freq); - } - at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ - return rcode; -} - -int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = 1; - int row; - u32 col; - u32 pinz; - u32 pins; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - writel((1 << ATMEL_ID_PIOA), &pmc->pcer); - - pins = 0x001F0000; - writel(pins, &pio->pioa.idr); - writel(pins, &pio->pioa.pudr); - writel(pins, &pio->pioa.per); - writel(pins, &pio->pioa.odr); - - pinz = 0x000F0000; - writel(pinz, &pio->piob.idr); - writel(pinz, &pio->piob.pudr); - writel(pinz, &pio->piob.per); - writel(pinz, &pio->piob.oer); - writel(pinz, &pio->piob.codr); - - while (1) { - col = 0; - for (row = 0; row < 4; row++) { - writel((0x00010000 << row), &pio->piob.sodr); - udelay(10000); - col <<= 4; - col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; - writel(pinz, &pio->piob.codr); - } - printf("Matix: "); - for (row = 0; row < 16; row++) { - printf("%1.1d", col & 1); - col >>= 1; - } - printf(" SP %d\r ", - 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); - if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { - /* SHUTDOWN */ - row = 0; - while (row < 1000) { - if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) - row++; - udelay(100); - } - udelay(100000); - row = 0; - while (row < 1000) { - if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { - row++; - udelay(1000); - } - } - poweroff(); - while (1) - ; - } - } - return rcode; -} - -/*****************************************************************************/ - -U_BOOT_CMD( - ledtest, 1, 0, do_ledtest, - "test ledmatrix", - "\n" - ); - -U_BOOT_CMD( - keytest, 1, 0, do_keytest, - "test keymatix and special keys, poweroff on pressing ON key", - "\n" - ); - -U_BOOT_CMD( - poweroff, 1, 0, do_poweroff, - "power off", - "\n" - ); - -U_BOOT_CMD( - beep, 3, 0, do_beep, - "[freq [duration]]", - "freq frequence of beep\nduration duration of beep\n" - ); - -/*****************************************************************************/ diff --git a/configs/vl_ma2sc_defconfig b/configs/vl_ma2sc_defconfig deleted file mode 100644 index c908c6e7fd1..00000000000 --- a/configs/vl_ma2sc_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_VL_MA2SC=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/vl_ma2sc_ram_defconfig b/configs/vl_ma2sc_ram_defconfig deleted file mode 100644 index 43a576f3b2a..00000000000 --- a/configs/vl_ma2sc_ram_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_VL_MA2SC=y -CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h deleted file mode 100644 index 3facd7f257c..00000000000 --- a/include/configs/vl_ma2sc.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2009-2012 - * Jens Scharsig - * BuS Elektronik GmbH & Co. KG - * - * Configuation settings for the VL_MA2SC board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*--------------------------------------------------------------------------*/ - -#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ -#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_MISC_INIT_R - -#include - -#define MACH_TYPE_VL_MA2SC 2412 -#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC - -#define CONFIG_SYS_DCACHE_OFF - -#ifdef CONFIG_RAMLOAD -#define CONFIG_SYS_TEXT_BASE 0x21000000 -#else -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_IDENT_STRING " on MiS Activ 2" -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AT91_GPIO - -#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) -#define CONFIG_SYS_USE_NORFLASH -#define CONFIG_SYS_USE_BOOT_NORFLASH -#endif - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Hardware drivers - */ - -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_WATCHDOG - -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LCD */ -#define CONFIG_LCD -#define CONFIG_ATMEL_LCD -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_BLACK_ON_WHITE -#define LCD_BPP LCD_COLOR8 -#define CONFIG_ATMEL_LCD_BGR555 - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_MD5SUM -#define CONFIG_CMD_SHA1SUM -/* -#define CONFIG_CMD_SPI -*/ -#define CONFIG_CMD_FAT -#define CONFIG_CMD_USB - -#define CONFIG_SYS_LONGHELP -#define CONFIG_MD5 -#define CONFIG_SHA1 - -/*---------------------------------------------------------------------------- - * Hardware confuguration - *---------------------------------------------------------------------------*/ - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_AT91C_PQFP_UHPBUG - -/* I2C-Bus */ - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ - -#ifndef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE - -/* Software I2C driver configuration */ -#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) - -#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ -#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ - -#define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); -#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); -#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - writel(AT91_PIN_SDA, &pio->piob.sodr); \ - else \ - writel(AT91_PIN_SDA, &pio->piob.codr); \ - } while (0); -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - writel(AT91_PIN_SCL, &pio->piob.sodr); \ - else \ - writel(AT91_PIN_SCL, &pio->piob.codr); \ - } while (0); -#endif - -/* I2C-RTC */ - -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/* EEPROM */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 - -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ - AT91_MATRIX_CSA_EBI_CS1A) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_MR_URSTEN | \ - AT91_RSTC_MR_ERSTL(15)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xFFF) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xFFF)) - -/* clocks */ - -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define MHZ180 -#if defined(MHZ199) -/* 199,8994 MHZ */ -#define MASTER_PLL_MUL 911 -#define MASTER_PLL_DIV 56 -#define MASTER_PLL_OUT 2 -#elif defined(MHZ180) -/* 180 MHZ */ -#define MASTER_PLL_MUL 1875 -#define MASTER_PLL_DIV 128 -#define MASTER_PLL_OUT 2 -#elif defined(MHZTEST) -/* Test MHZ */ -#define CONFIG_DISPLAY_CPUINFO -#define MASTER_PLL_MUL 8 -#define MASTER_PLL_DIV 1 -#define MASTER_PLL_OUT 2 -#else -/* 176.9472 MHZ */ -#define MASTER_PLL_MUL 72 -#define MASTER_PLL_DIV 5 -#define MASTER_PLL_OUT 2 -#endif - -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) - -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLAR_29 | \ - AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ - AT91_PMC_PLLXR_PLLCOUNT(63) | \ - AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ - AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ - -#define CONFIG_SYS_SDRC_MR_VAL1 0 -#define CONFIG_SYS_SDRC_TR_VAL1 700 -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (8 << 28)) /* Exit Self Refresh to Active Delay */ - -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* NOR flash */ - -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ - AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ - AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 5 -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x21e00000 - -/* Address and size of Primary Environment Sector */ -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ - 38400, 57600, 9600 } - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#ifndef CONFIG_RAMLOAD -#define CONFIG_BOOTCOMMAND "run nfsboot" -#endif -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_BOOT_RETRY_MIN 15 - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp $(copy_addr) $(kernelname);" \ - "run bootargsdefaults;" \ - "set bootargs $(bootargs) boot=nfs " \ - ";echo $(bootargs)" \ - ";bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubootaddr=10000000\0" \ - "splashimage=10080000\0" \ - "kerneladdr=100A0000\0" \ - "kernelsize=00800000\0" \ - "minifsaddr=108A0000\0" \ - "minifssize=00060000\0" \ - "rootfsaddr=10900000\0" \ - "copy_addr=20200000\0" \ - "rootfssize=01700000\0" \ - "kernelname=uImage_vl_ma2sc\0" \ - "bootargsdefaults=set bootargs " \ - "console=ttyS0,115200 " \ - "video=atmel_lcdfb " \ - "mem=62M " \ - "panic=10 " \ - "boardrevison=\\\"${revision}\\\" " \ - "uboot=\\\"${ver}\\\" " \ - "\0" \ - "update_all=run update_kernel;run update_root;" \ - "run update_splash; run update_uboot\0" \ - "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ - "dhcp $(copy_addr) $(kernelname);" \ - "erase $(kerneladdr) +$(kernelsize);" \ - "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ - "protect on $(kerneladdr) +$(kernelsize)" \ - "\0" \ - "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ - "dhcp $(copy_addr) vl_ma2sc.root;" \ - "erase $(rootfsaddr) +$(rootfssize);" \ - "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ - "\0" \ - "update_splash=protect off $(splashimage) +20000;" \ - "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ - "erase $(splashimage) +20000;" \ - "cp.b $(fileaddr) 10080000 $(filesize);" \ - "protect on $(splashimage) +20000\0" \ - "update_uboot=protect off 10000000 1005FFFF;" \ - "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ - "erase 10000000 1005FFFF;" \ - "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ - "protect on 10000000 1005FFFF;reset\0" \ - "emergency=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(kerneladdr)\0" \ - "netemergency=run bootargsdefaults;" \ - "dhcp $(copy_addr) $(kernelname);" \ - "set bootargs $(bootargs) root=initramfs boot=emergency " \ - ";bootm $(copy_addr)\0" \ - "norboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=local quiet " \ - ";bootm $(kerneladdr)\0" \ - "nandboot=run bootargsdefaults;" \ - "set bootargs $(bootargs) root=initramfs boot=nand " \ - ";bootm $(kerneladdr)\0" \ - "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ - "clearenv=protect off 10060000 1007FFFF;" \ - "erase 10060000 1007FFFF;reset\0" \ - " " - -#endif -- cgit v1.3.1 From 452ef8304608849ebf9120202dd4015c0ebcb5cb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:33 -0600 Subject: arm: Remove vpac270_nor_128 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 6 - board/vpac270/Kconfig | 9 -- board/vpac270/MAINTAINERS | 8 - board/vpac270/Makefile | 13 -- board/vpac270/onenand.c | 46 ------ board/vpac270/u-boot-spl.lds | 81 ---------- board/vpac270/vpac270.c | 126 --------------- configs/vpac270_nor_128_defconfig | 6 - configs/vpac270_nor_256_defconfig | 6 - configs/vpac270_ond_256_defconfig | 8 - include/configs/vpac270.h | 325 -------------------------------------- 11 files changed, 634 deletions(-) delete mode 100644 board/vpac270/Kconfig delete mode 100644 board/vpac270/MAINTAINERS delete mode 100644 board/vpac270/Makefile delete mode 100644 board/vpac270/onenand.c delete mode 100644 board/vpac270/u-boot-spl.lds delete mode 100644 board/vpac270/vpac270.c delete mode 100644 configs/vpac270_nor_128_defconfig delete mode 100644 configs/vpac270_nor_256_defconfig delete mode 100644 configs/vpac270_ond_256_defconfig delete mode 100644 include/configs/vpac270.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e892c54559e..4065001d76e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -619,11 +619,6 @@ config TARGET_PALMTREO680 select CPU_PXA select SUPPORT_SPL -config TARGET_VPAC270 - bool "Support vpac270" - select CPU_PXA - select SUPPORT_SPL - config TARGET_XAENIAX bool "Support xaeniax" select CPU_PXA @@ -785,7 +780,6 @@ source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" source "board/technologic/ts4800/Kconfig" -source "board/vpac270/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" diff --git a/board/vpac270/Kconfig b/board/vpac270/Kconfig deleted file mode 100644 index 1701b35d12a..00000000000 --- a/board/vpac270/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_VPAC270 - -config SYS_BOARD - default "vpac270" - -config SYS_CONFIG_NAME - default "vpac270" - -endif diff --git a/board/vpac270/MAINTAINERS b/board/vpac270/MAINTAINERS deleted file mode 100644 index 1c627657ba1..00000000000 --- a/board/vpac270/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -VPAC270 BOARD -M: Marek Vasut -S: Maintained -F: board/vpac270/ -F: include/configs/vpac270.h -F: configs/vpac270_nor_128_defconfig -F: configs/vpac270_nor_256_defconfig -F: configs/vpac270_ond_256_defconfig diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile deleted file mode 100644 index ad7f7d8d66d..00000000000 --- a/board/vpac270/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Voipac PXA270 Support -# -# Copyright (C) 2010 Marek Vasut -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifndef CONFIG_SPL_BUILD -obj-y := vpac270.o -else -obj-y := onenand.o -endif diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c deleted file mode 100644 index a749b310c5e..00000000000 --- a/board/vpac270/onenand.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Voipac PXA270 OneNAND SPL - * - * Copyright (C) 2011 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -void board_init_f(unsigned long unused) -{ - extern uint32_t _end; - uint32_t tmp; - - asm volatile("mov %0, pc" : "=r"(tmp)); - tmp >>= 24; - - /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */ - if (tmp == 0) { - tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE; - onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE); - asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE)); - } - - /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */ - arch_cpu_init(); - pxa2xx_dram_init(); - onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR, - CONFIG_SPL_ONENAND_LOAD_SIZE, - (void *)CONFIG_SYS_TEXT_BASE); - asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE)); - - for (;;) - ; -} - -void __attribute__((noreturn)) hang(void) -{ - for (;;) - ; -} diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds deleted file mode 100644 index 954afb9f8b7..00000000000 --- a/board/vpac270/u-boot-spl.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - * - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = CONFIG_SPL_TEXT_BASE; - .text.0 : - { - *(.vectors) - arch/arm/cpu/pxa/start.o (.text*) - arch/arm/lib/built-in.o (.text*) - board/vpac270/built-in.o (.text*) - drivers/built-in.o (.text*) - } - - - /* Start of the rest of the SPL */ - . = CONFIG_SPL_TEXT_BASE + 0x800; - - .text.1 : - { - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - __image_copy_end = .; - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - . = ALIGN(0x800); - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c deleted file mode 100644 index 8d777df8464..00000000000 --- a/board/vpac270/vpac270.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Voipac PXA270 Support - * - * Copyright (C) 2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* Arch number of vpac270 */ - gd->bd->bi_arch_number = MACH_TYPE_VPAC270; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int dram_init(void) -{ -#ifndef CONFIG_ONENAND - pxa2xx_dram_init(); -#endif - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - -#ifdef CONFIG_RAM_256M - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (readl(UHCHR) & UHCHR_FSBIR) - ; - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); - writel(readl(UHCRHDA) | 0x100, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - - return; -} -#endif - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(bd_t *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/configs/vpac270_nor_128_defconfig b/configs/vpac270_nor_128_defconfig deleted file mode 100644 index 1d116533abc..00000000000 --- a/configs/vpac270_nor_128_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VPAC270=y -CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="$ " diff --git a/configs/vpac270_nor_256_defconfig b/configs/vpac270_nor_256_defconfig deleted file mode 100644 index bcd10065b4f..00000000000 --- a/configs/vpac270_nor_256_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VPAC270=y -CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="$ " diff --git a/configs/vpac270_ond_256_defconfig b/configs/vpac270_ond_256_defconfig deleted file mode 100644 index d98981916ac..00000000000 --- a/configs/vpac270_ond_256_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VPAC270=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="$ " diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h deleted file mode 100644 index 976ba5db742..00000000000 --- a/include/configs/vpac270.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Voipac PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_VPAC270 1 /* Voipac PXA270 board */ -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#ifdef CONFIG_ONENAND -#define CONFIG_SPL_ONENAND_SUPPORT -#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 -#define CONFIG_SPL_ONENAND_LOAD_SIZE \ - (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) -#define CONFIG_SPL_TEXT_BASE 0x5c000000 -#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds" -#endif - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ - "bootm 0xa4000000; " \ - "fi; " \ - "bootm 0x60000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_onenand=" \ - "onenand erase 0x0 0x80000 ; " \ - "onenand write 0xa0000000 0x0 0x80000" - -#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_LZMA /* LZMA compression support */ -#define CONFIG_OF_LIBFDT - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_USB -#undef CONFIG_LCD -#define CONFIG_CMD_IDE - -#ifdef CONFIG_ONENAND -#define CONFIG_CMD_ONENAND -#else -#undef CONFIG_CMD_ONENAND -#endif - -/* - * Networking Configuration - * chip on the Voipac PXA270 board - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_NET_RETRY_COUNT 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#endif - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP -#ifdef CONFIG_SYS_HUSH_PARSER -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ - - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -#ifdef CONFIG_RAM_256M -#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#endif - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#ifdef CONFIG_RAM_256M -#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ -#else -#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -#if defined(CONFIG_CMD_FLASH) /* NOR */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#ifdef CONFIG_RAM_256M -#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ -#endif - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#ifdef CONFIG_RAM_256M -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } -#else -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#endif - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ONENAND_BASE 0x00000000 - -#define CONFIG_ENV_IS_IN_ONENAND 1 - -#else /* No flash */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#endif - -/* - * IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 -#define CONFIG_SYS_ATA_REG_OFFSET 0x120 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 - -#define CONFIG_SYS_ATA_STRIDE 2 -#endif - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x01308800 -#define CONFIG_SYS_GPSR1_VAL 0x00cf0000 -#define CONFIG_SYS_GPSR2_VAL 0x922ac000 -#define CONFIG_SYS_GPSR3_VAL 0x0161e800 - -#define CONFIG_SYS_GPCR0_VAL 0x00010000 -#define CONFIG_SYS_GPCR1_VAL 0x0 -#define CONFIG_SYS_GPCR2_VAL 0x0 -#define CONFIG_SYS_GPCR3_VAL 0x0 - -#define CONFIG_SYS_GPDR0_VAL 0xcbb18800 -#define CONFIG_SYS_GPDR1_VAL 0xfccfa981 -#define CONFIG_SYS_GPDR2_VAL 0x922affff -#define CONFIG_SYS_GPDR3_VAL 0x0161e904 - -#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 -#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 -#define CONFIG_SYS_GAFR3_L_VAL 0x54010310 -#define CONFIG_SYS_GAFR3_U_VAL 0x00025401 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00500240 -#define CONFIG_SYS_CCCR 0x02000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9 -#define CONFIG_SYS_MSC1_VAL 0x02ccf974 -#define CONFIG_SYS_MSC2_VAL 0x00000000 -#ifdef CONFIG_RAM_256M -#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 -#else -#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 -#endif -#define CONFIG_SYS_MDREFR_VAL 0x201fe01e -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" -#define CONFIG_USB_STORAGE -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 1c87dd76c490041fce01e3dbfe29d993eadd693b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:34 -0600 Subject: arm: Remove xaeniax board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 5 - board/xaeniax/Kconfig | 9 - board/xaeniax/MAINTAINERS | 6 - board/xaeniax/Makefile | 8 - board/xaeniax/flash.c | 412 ----------------------------------- board/xaeniax/xaeniax.c | 69 ------ configs/xaeniax_defconfig | 3 - drivers/net/smc91111.c | 51 +---- drivers/net/smc91111.h | 22 -- include/configs/xaeniax.h | 539 ---------------------------------------------- 10 files changed, 1 insertion(+), 1123 deletions(-) delete mode 100644 board/xaeniax/Kconfig delete mode 100644 board/xaeniax/MAINTAINERS delete mode 100644 board/xaeniax/Makefile delete mode 100644 board/xaeniax/flash.c delete mode 100644 board/xaeniax/xaeniax.c delete mode 100644 configs/xaeniax_defconfig delete mode 100644 include/configs/xaeniax.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4065001d76e..89fe420c4de 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -619,10 +619,6 @@ config TARGET_PALMTREO680 select CPU_PXA select SUPPORT_SPL -config TARGET_XAENIAX - bool "Support xaeniax" - select CPU_PXA - config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -783,7 +779,6 @@ source "board/technologic/ts4800/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" -source "board/xaeniax/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/board/xaeniax/Kconfig b/board/xaeniax/Kconfig deleted file mode 100644 index 519e21fb9a8..00000000000 --- a/board/xaeniax/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_XAENIAX - -config SYS_BOARD - default "xaeniax" - -config SYS_CONFIG_NAME - default "xaeniax" - -endif diff --git a/board/xaeniax/MAINTAINERS b/board/xaeniax/MAINTAINERS deleted file mode 100644 index 44bb5883f20..00000000000 --- a/board/xaeniax/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -XAENIAX BOARD -#M: - -S: Maintained -F: board/xaeniax/ -F: include/configs/xaeniax.h -F: configs/xaeniax_defconfig diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile deleted file mode 100644 index e5f116debbd..00000000000 --- a/board/xaeniax/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := xaeniax.o flash.o diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c deleted file mode 100644 index 6ad62166a9f..00000000000 --- a/board/xaeniax/flash.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c deleted file mode 100644 index 995c262b6c7..00000000000 --- a/board/xaeniax/xaeniax.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2004 - * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of xaeniax */ - gd->bd->bi_arch_number = 585; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/configs/xaeniax_defconfig b/configs/xaeniax_defconfig deleted file mode 100644 index 8634cc7b60e..00000000000 --- a/configs/xaeniax_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_XAENIAX=y -# CONFIG_CMD_SETEXPR is not set diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index ade14cd4757..f31216ffa6c 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -499,15 +499,8 @@ again: } /* we have a packet address, so tell the card to use it */ -#ifndef CONFIG_XAENIAX SMC_outb (dev, packet_no, PN_REG); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl (dev, packet_no << 16, 0); -#endif + /* do not write new ptr value if Write data fifo not empty */ while ( saved_ptr & PTR_NOTEMPTY ) printf ("Write data fifo not empty!\n"); @@ -542,39 +535,19 @@ again: */ #ifdef USE_32_BIT SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); -#ifndef CONFIG_XAENIAX if (length & 0x2) SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG); -#else - /* On XANEIAX, we can only use 32-bit writes, so we need to handle - * unaligned tail part specially. The standard code doesn't work. - */ - if ((length & 3) == 3) { - u16 * ptr = (u16*) &buf[length-3]; - SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), - SMC91111_DATA_REG); - } else if ((length & 2) == 2) { - u16 * ptr = (u16*) &buf[length-2]; - SMC_outl(dev, *ptr, SMC91111_DATA_REG); - } else if (length & 1) { - SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); - } else { - SMC_outl(dev, 0, SMC91111_DATA_REG); - } -#endif #else SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); #endif /* USE_32_BIT */ -#ifndef CONFIG_XAENIAX /* Send the last byte, if there is one. */ if ((length & 1) == 0) { SMC_outw (dev, 0, SMC91111_DATA_REG); } else { SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); } -#endif /* and let the chipset deal with it */ SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); @@ -588,9 +561,6 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX - SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); -#endif /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { @@ -610,9 +580,6 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX - SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); -#endif /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { @@ -625,15 +592,7 @@ again: } /* restore previously saved registers */ -#ifndef CONFIG_XAENIAX SMC_outb( dev, saved_pnr, PN_REG ); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl(dev, saved_pnr << 16, 0); -#endif SMC_outw( dev, saved_ptr, PTR_REG ); return length; @@ -802,15 +761,7 @@ static int smc_rcv(struct eth_device *dev) udelay(1); /* Wait until not busy */ /* restore saved registers */ -#ifndef CONFIG_XAENIAX SMC_outb( dev, saved_pnr, PN_REG ); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl( dev, saved_pnr << 16, 0); -#endif SMC_outw( dev, saved_ptr, PTR_REG ); if (!is_error) { diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index e19c491cbce..5197f36039f 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -77,19 +77,6 @@ struct smc91111_priv{ if (__p & 2) __v >>= 8; \ else __v &= 0xff; \ __v; }) -#elif defined(CONFIG_XAENIAX) -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) -#define SMC_inw(a,z) ({ \ - unsigned int __p = (unsigned int)((a)->iobase + (z)); \ - unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ - if (__p & 3) __v >>= 16; \ - else __v &= 0xffff; \ - __v; }) -#define SMC_inb(a,p) ({ \ - unsigned int ___v = SMC_inw((a),(p) & ~1); \ - if ((p) & 1) ___v >>= 8; \ - else ___v &= 0xff; \ - ___v; }) #else #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) @@ -104,15 +91,6 @@ struct smc91111_priv{ #ifdef CONFIG_XSENGINE #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) -#elif defined (CONFIG_XAENIAX) -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) -#define SMC_outw(a,d,p) ({ \ - dword __dwo = SMC_inl((a),(p) & ~3); \ - dword __dwn = (word)(d); \ - __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ - __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ - SMC_outl((a), __dwo, (p) & ~3); \ -}) #else #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h deleted file mode 100644 index 8d19bffa025..00000000000 --- a/include/configs/xaeniax.h +++ /dev/null @@ -1,539 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2004 - * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the xaeniax board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */ -#define CONFIG_XAENIAX 1 /* on a xaeniax board */ -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_BOARD_LATE_INIT - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ -#define CONFIG_CONS_INDEX 4 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_DTT - - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.68.201 -#define CONFIG_SERVERIP 192.168.68.62 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 0x00100000" -#define CONFIG_BOOTARGS "console=ttyS1,115200" -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* FIXME */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* - * SMSC91C111 Network Card - */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ -#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * GPIO settings - */ - -/* - * GP05 == nUSBReset is 1 - * GP10 == CFReset is 1 - * GP13 == nCFDataEnable is 1 - * GP14 == nCFAddrEnable is 1 - * GP15 == nCS1 is 1 - * GP21 == ComBrdReset is 1 - * GP24 == SFRM is 1 - * GP25 == TXD is 1 - * GP31 == SYNC is 1 - * GP33 == nCS5 is 1 - * GP39 == FFTXD is 1 - * GP41 == RTS is 1 - * GP43 == BTTXD is 1 - * GP45 == BTRTS is 1 - * GP47 == TXD is 1 - * GP48 == nPOE is 1 - * GP49 == nPWE is 1 - * GP50 == nPIOR is 1 - * GP51 == nPIOW is 1 - * GP52 == nPCE[1] is 1 - * GP53 == nPCE[2] is 1 - * GP54 == nPSKTSEL is 1 - * GP55 == nPREG is 1 - * GP78 == nCS2 is 1 - * GP79 == nCS3 is 1 - * GP80 == nCS4 is 1 - * GP82 == NSSPSFRM is 1 - * GP83 == NSSPTXD is 1 - */ -#define CONFIG_SYS_GPSR0_VAL 0x8320E420 -#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82 -#define CONFIG_SYS_GPSR2_VAL 0x000DC000 - -/* - * GP03 == LANReset is 0 - * GP06 == USBWakeUp is 0 - * GP11 == USBControl is 0 - * GP12 == Buzzer is 0 - * GP16 == PWM0 is 0 - * GP17 == PWM1 is 0 - * GP23 == SCLK is 0 - * GP30 == SDATA_OUT is 0 - * GP81 == NSSPCLK is 0 - */ -#define CONFIG_SYS_GPCR0_VAL 0x40C31848 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00020000 - -/* - * GP00 == CPUWakeUpUSB is input - * GP01 == GP reset is input - * GP02 == LANInterrupt is input - * GP03 == LANReset is output - * GP04 == USBInterrupt is input - * GP05 == nUSBReset is output - * GP06 == USBWakeUp is output - * GP07 == CFReady/nBusy is input - * GP08 == nCFCardDetect1 is input - * GP09 == nCFCardDetect2 is input - * GP10 == nCFReset is output - * GP11 == USBControl is output - * GP12 == Buzzer is output - * GP13 == CFDataEnable is output - * GP14 == CFAddressEnable is output - * GP15 == nCS1 is output - * GP16 == PWM0 is output - * GP17 == PWM1 is output - * GP18 == RDY is input - * GP19 == ReaderReady is input - * GP20 == ReaderReset is input - * GP21 == ComBrdReset is output - * GP23 == SCLK is output - * GP24 == SFRM is output - * GP25 == TXD is output - * GP26 == RXD is input - * GP27 == EXTCLK is input - * GP28 == BITCLK is output - * GP29 == SDATA_IN0 is input - * GP30 == SDATA_OUT is output - * GP31 == SYNC is output - * GP32 == SYSSCLK is output - * GP33 == nCS5 is output - * GP34 == FFRXD is input - * GP35 == CTS is input - * GP36 == DCD is input - * GP37 == DSR is input - * GP38 == RI is input - * GP39 == FFTXD is output - * GP40 == DTR is output - * GP41 == RTS is output - * GP42 == BTRXD is input - * GP43 == BTTXD is output - * GP44 == BTCTS is input - * GP45 == BTRTS is output - * GP46 == RXD is input - * GP47 == TXD is output - * GP48 == nPOE is output - * GP49 == nPWE is output - * GP50 == nPIOR is output - * GP51 == nPIOW is output - * GP52 == nPCE[1] is output - * GP53 == nPCE[2] is output - * GP54 == nPSKTSEL is output - * GP55 == nPREG is output - * GP56 == nPWAIT is input - * GP57 == nPIOS16 is input - * GP58 == LDD[0] is output - * GP59 == LDD[1] is output - * GP60 == LDD[2] is output - * GP61 == LDD[3] is output - * GP62 == LDD[4] is output - * GP63 == LDD[5] is output - * GP64 == LDD[6] is output - * GP65 == LDD[7] is output - * GP66 == LDD[8] is output - * GP67 == LDD[9] is output - * GP68 == LDD[10] is output - * GP69 == LDD[11] is output - * GP70 == LDD[12] is output - * GP71 == LDD[13] is output - * GP72 == LDD[14] is output - * GP73 == LDD[15] is output - * GP74 == LCD_FCLK is output - * GP75 == LCD_LCLK is output - * GP76 == LCD_PCLK is output - * GP77 == LCD_ACBIAS is output - * GP78 == nCS2 is output - * GP79 == nCS3 is output - * GP80 == nCS4 is output - * GP81 == NSSPCLK is output - * GP82 == NSSPSFRM is output - * GP83 == NSSPTXD is output - * GP84 == NSSPRXD is input - */ -#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68 -#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83 -#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF - -/* - * GP01 == GP reset is AF01 - * GP15 == nCS1 is AF10 - * GP16 == PWM0 is AF10 - * GP17 == PWM1 is AF10 - * GP18 == RDY is AF01 - * GP23 == SCLK is AF10 - * GP24 == SFRM is AF10 - * GP25 == TXD is AF10 - * GP26 == RXD is AF01 - * GP27 == EXTCLK is AF01 - * GP28 == BITCLK is AF01 - * GP29 == SDATA_IN0 is AF10 - * GP30 == SDATA_OUT is AF01 - * GP31 == SYNC is AF01 - * GP32 == SYSCLK is AF01 - * GP33 == nCS5 is AF10 - * GP34 == FFRXD is AF01 - * GP35 == CTS is AF01 - * GP36 == DCD is AF01 - * GP37 == DSR is AF01 - * GP38 == RI is AF01 - * GP39 == FFTXD is AF10 - * GP40 == DTR is AF10 - * GP41 == RTS is AF10 - * GP42 == BTRXD is AF01 - * GP43 == BTTXD is AF10 - * GP44 == BTCTS is AF01 - * GP45 == BTRTS is AF10 - * GP46 == RXD is AF10 - * GP47 == TXD is AF01 - * GP48 == nPOE is AF10 - * GP49 == nPWE is AF10 - * GP50 == nPIOR is AF10 - * GP51 == nPIOW is AF10 - * GP52 == nPCE[1] is AF10 - * GP53 == nPCE[2] is AF10 - * GP54 == nPSKTSEL is AF10 - * GP55 == nPREG is AF10 - * GP56 == nPWAIT is AF01 - * GP57 == nPIOS16 is AF01 - * GP58 == LDD[0] is AF10 - * GP59 == LDD[1] is AF10 - * GP60 == LDD[2] is AF10 - * GP61 == LDD[3] is AF10 - * GP62 == LDD[4] is AF10 - * GP63 == LDD[5] is AF10 - * GP64 == LDD[6] is AF10 - * GP65 == LDD[7] is AF10 - * GP66 == LDD[8] is AF10 - * GP67 == LDD[9] is AF10 - * GP68 == LDD[10] is AF10 - * GP69 == LDD[11] is AF10 - * GP70 == LDD[12] is AF10 - * GP71 == LDD[13] is AF10 - * GP72 == LDD[14] is AF10 - * GP73 == LDD[15] is AF10 - * GP74 == LCD_FCLK is AF10 - * GP75 == LCD_LCLK is AF10 - * GP76 == LCD_PCLK is AF10 - * GP77 == LCD_ACBIAS is AF10 - * GP78 == nCS2 is AF10 - * GP79 == nCS3 is AF10 - * GP80 == nCS4 is AF10 - * GP81 == NSSPCLK is AF01 - * GP82 == NSSPSFRM is AF01 - * GP83 == NSSPTXD is AF01 - * GP84 == NSSPRXD is AF10 - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x80000004 -#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A -#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559 -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA -#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA -#define CONFIG_SYS_GAFR2_U_VAL 0x00000256 - -/* - * clock settings - */ -/* RDH = 1 - * PH = 0 - * VFS = 0 - * BFS = 0 - * SSS = 0 - */ -#define CONFIG_SYS_PSSR_VAL 0x00000030 - -#define CONFIG_SYS_CKEN 0x00000080 /* */ -#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 - - -/* - * Memory settings - * - * This is the configuration for nCS0/1 -> flash banks - * configuration for nCS1 : - * [31] 0 - - * [30:28] 000 - - * [27:24] 0000 - - * [23:20] 0000 - - * [19] 0 - - * [18:16] 000 - - * configuration for nCS0: - * [15] 0 - Slower Device - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns - * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) - * [03] 0 - 32 Bit bus width - * [02:00] 010 - burst OF 4 ROM or FLASH -*/ -#define CONFIG_SYS_MSC0_VAL 0x000023D2 - -/* This is the configuration for nCS2/3 -> USB controller, LAN - * configuration for nCS3: LAN - * [31] 0 - Slower Device - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: USB - * [15] 1 - Faster Device - * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_SYS_MSC1_VAL 0x1224A26C - -/* This is the configuration for nCS4/5 -> LAN - * configuration for nCS5: - * [31] 0 - - * [30:28] 000 - - * [27:24] 0000 - - * [23:20] 0000 - - * [19] 0 - - * [18:16] 000 - - * configuration for nCS4: LAN - * [15] 1 - Faster Device - * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 0 - 32 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_SYS_MSC2_VAL 0x00001224 - -/* MDCNFG: SDRAM Configuration Register - * - * [31:29] 000 - reserved - * [28] 0 - no SA1111 compatiblity mode - * [27] 0 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 00 - timings - * [23] 0 - internal banks in lower partition 2/3 (not used) - * [22:21] 00 - row address bits for partition 2/3 (not used) - * [20:19] 00 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15:13] 000 - reserved - * [12] 0 - no SA1111 compatiblity mode - * [11] 1 - latch return data with return clock - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ -/* use the configuration above but disable partition 0 */ -#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9 - -/* MDREFR: SDRAM Refresh Control Register - * - * [32:26] 0 - reserved - * [25] 0 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 0 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 1 - APD: auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 0 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 0 - E0PIN: disable SDCKE0 - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CONFIG_SYS_MDMRS_VAL 0x00320032 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From ad4f54ea86bd8a1836bd270566374927fe9c5b08 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:36 -0600 Subject: arm: Remove palmtreo680 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 6 - board/palmtreo680/Kconfig | 9 - board/palmtreo680/MAINTAINERS | 6 - board/palmtreo680/Makefile | 9 - board/palmtreo680/README | 563 ---------------------------------------- board/palmtreo680/palmtreo680.c | 148 ----------- configs/palmtreo680_defconfig | 12 - include/configs/palmtreo680.h | 270 ------------------- 8 files changed, 1023 deletions(-) delete mode 100644 board/palmtreo680/Kconfig delete mode 100644 board/palmtreo680/MAINTAINERS delete mode 100644 board/palmtreo680/Makefile delete mode 100644 board/palmtreo680/README delete mode 100644 board/palmtreo680/palmtreo680.c delete mode 100644 configs/palmtreo680_defconfig delete mode 100644 include/configs/palmtreo680.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89fe420c4de..e9cd91a5c85 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -614,11 +614,6 @@ config TARGET_H2200 bool "Support h2200" select CPU_PXA -config TARGET_PALMTREO680 - bool "Support palmtreo680" - select CPU_PXA - select SUPPORT_SPL - config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -748,7 +743,6 @@ source "board/karo/tx25/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" -source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/samsung/smdk2410/Kconfig" diff --git a/board/palmtreo680/Kconfig b/board/palmtreo680/Kconfig deleted file mode 100644 index b5fdb9a361a..00000000000 --- a/board/palmtreo680/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PALMTREO680 - -config SYS_BOARD - default "palmtreo680" - -config SYS_CONFIG_NAME - default "palmtreo680" - -endif diff --git a/board/palmtreo680/MAINTAINERS b/board/palmtreo680/MAINTAINERS deleted file mode 100644 index b0ff9d02836..00000000000 --- a/board/palmtreo680/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PALMTREO680 BOARD -#M: Mike Dunn -S: Orphan (since 2014-06) -F: board/palmtreo680/ -F: include/configs/palmtreo680.h -F: configs/palmtreo680_defconfig diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile deleted file mode 100644 index 4f79e4bf11a..00000000000 --- a/board/palmtreo680/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Palm Treo680 Support -# -# Copyright (C) 2013 Mike Dunn -# -# This file is released under the terms of GPL v2 and any later version. -# See the file COPYING in the root directory of the source tree for details. - -obj-y := palmtreo680.o diff --git a/board/palmtreo680/README b/board/palmtreo680/README deleted file mode 100644 index c8799c6ab1a..00000000000 --- a/board/palmtreo680/README +++ /dev/null @@ -1,563 +0,0 @@ - -README for the Palm Treo 680. - -Copyright (C) 2013 Mike Dunn - -You may reproduce the contents of this file entirely or in part, but please -credit me by name if you do. Thanks. - - -Intro -===== - -Yes, you can program u-boot onto the flash of your Palm Treo 680 so that u-boot -(then Linux, Android, ...) runs at power-up. This document describes how, and -gives some implementation details on this port of u-boot and describes how the -Treo 680 boots from reset. - -But first, I probably don't need to tell you that after doing this, your phone -will no longer run PalmOS. You *may* be able to later restore your phone to its -original state by creating a backup image of the flash before writing u-boot -(details below), but this is not heavily tested and should not be relied upon. -There is also the possibility that something may go wrong during the process of -programming u-boot, leaving you with a bricked phone. If you follow these -instructions carefully this chance will be minimized, but I do not recommend -that you program u-boot onto a phone that you can not afford to lose, and -certainly not one that contains important data that is not backed up elsewhere. -I AM NOT RESPONSIBLE FOR THE LOSS OF YOUR PHONE. DO THIS AT YOUR OWN RISK. -Having said that, feel free to send me a note cursing me out if something does -go wrong, but please tell me what happened exactly. For that matter, I'd love -to hear from you if you succeed. - - -Details on the SPL -================== - -The docg4 features a 2k region at the start of its address space that interfaces -to the system bus like a NOR flash. This allows the docg4 to function as a boot -ROM. The Treo 680 uses this feature. The contents of this 2k region are -write-protected and can not be reprogrammed. Fortunately, the code it contains -does what we need to do, at least partially. After some essential hardware -initialization (like the SDRAM controller), it runs an IPL (initial program -loader) that copies 128K (no more, no less) from flash to a fixed address in -SDRAM (0xa1700000) and jumps to it. 128K is too small for u-boot, so we use it -to load a u-boot secondary program loader (SPL). But since our SPL only -occupies a little over 1k, we can economize on flash usage by having the IPL -load a portion of u-boot proper as well. We let the IPL load the first 128k of -a concatenated spl + u-boot image, and because the SPL is placed before u-boot -proper, the IPL jumps to the SPL, which copies the portion of u-boot that the -IPL has already loaded to its correct SDRAM address, and then loads the -remainder of u-boot and jumps to it. - - -The docg4's "reliable mode" -=========================== - -This is a special mode of operation of the docg4's integrated controller whereby -consecutive pairs of 2k regions are used in parallel (in some fashion) to store -2k of data. In other words, the normal capacity is halved, but the data -integrity is improved. In this mode, the data is read or written from pages in -even-numbered 2k regions (regions starting at 0x000, 0x1000, 0x2000, ...). The -odd-numbered 2k regions (regions starting at 0x800, 0x1800, 0x2800, ...) are -transparently used in parallel. In reliable mode, the odd-numbered 2k regions -are not meant to be read or written directly. - -Reliable mode is used by the IPL because there is not enough space in its 2k -footprint to implement the BCH ecc algorithm. Data that is read while reliable -mode is enabled must have been written in reliable mode, or the read fails. -However, data written in reliable mode can also be read in normal mode (just not -as reliably), but only from the even-numbered 2k regions; the odd-numbered 2k -regions appear to contain junk, and will generate ecc errors. When the IPL and -SPL read from flash, the odd-numbered 2k regions are explicitly skipped. The -same is true for the flash_u-boot utility when it writes the u-boot image in -reliable mode. - -The docg4 Linux driver supports writing in reliable mode (it is enabled by the -module parameter), but not reading. However, the u-boot docg4_spl driver does -read in reliable mode, in the same fashion as the IPL. - - -Details on the IPL and its data format -====================================== - -Starting from block 5 and counting upward, the IPL will search for and load the -first two blocks it finds that contain a magic number in the oob of the first -page of the block. The contents are loaded to SDRAM starting at address -0xa1700000. After two blocks have been loaded, it jumps to 0xa1700000. The -number of blocks loaded and the load address in SDRAM are hard-coded; only the -flash offset of the blocks can vary at run-time (based on the presence of the -magic number). - -In addition to using the docg4's reliable mode, the IPL expects each 512 byte -page to be written redundantly in the subsequent page. The hardware is capable -of detecting bit errors (but not correcting them), and if a bit error is -detected when a page is read, the page contents are discarded and the subsequent -page is read. - -Reliable mode reduces the capacity of a block by half, and the redundant pages -reduce it by half again. As a result, the normal 256k capacity of a block is -reduced to 64k for the purposes of the IPL/SPL. - -For the sake of simplicity and uniformity, the u-boot SPL mimics the operation -of the IPL, and expects the image to be stored in the same format. - - -Instructions on Programming u-boot to flash -=========================================== - -To program u-boot to your flash, you will need to boot the Linux kernel on your -phone using a PalmOS bootloader such as cocoboot. The details of building and -running Linux on your Treo (cross-compiling, creating a root filesystem, -configuring the kernel, etc) are beyond the scope of this document. The -remainder of this document describes in detail how to program u-boot to the -flash using Linux running on the Treo. - - -Hardware Prerequisites -====================== - -A Palm Treo 680: - (dugh) - -A Palm usb cable: - You'll need this to establish a usbtty console connection to u-boot from a - desktop PC. Currently there is no support in u-boot for the pxa27x keypad - (coming soon), so a serial link must be used for the console. - These cables are still widely available if you don't already have one. - -A Linux desktop PC. - You may be able to use Windows for the u-boot console if you have a usb driver - that is compatible with the Linux usbserial driver, but for programming u-boot - to flash, you'll really want to use a Linux PC. - - -Treo-side Software Prerequisites -================================ - -Linux bootloader for PalmOS: - - Cocoboot is the only one I'm aware of. If you don't already have this, you - can download it from - https://download.enlightenment.org/misc/Illume/Treo-650/2008-11-13/sdcard-base.tar.gz - which is a compressed tar archive of the contents of an sd card containing - cocoboot. Use mkdosfs to create a fat16 filesystem on the first primary - partition of the card, mount the partition, and extract the tar file to it. - You will probably need to edit the cocoboot.conf file to customize the - parameters passed to the kernel. - - -Linux kernel: - - The kernel on the Treo 680 is still a little rough around the edges, and the - official kernel frequently breaks on the Treo :( A development kernel - specifically for the Treo 680 can be found on github: - http://github.com/mike-dunn/linux-treo680 - The master branch of this tree has been tested on the Treo, and I recommend - using this kernel for programming u-boot. As of this writing, there may be a - bug in the docg4 nand flash driver that sometimes causes block erasures to - fail. This has been fixed in the above tree. - - If you choose to use the official kernel, it must contain the docg4 driver that - includes the reliable_mode module parameter. This was a later enhancement to - the driver, and was merged to the kernel as of v3.8. Do not try to use an - earlier kernel that contains the docg4 driver without support for writing in - reliable mode. If you try to program u-boot to flash with the docg4 driver - loaded without the reliable_mode parameter enabled, you *will* brick your - phone! - - For the purpose of programming u-boot to flash, the following options must be - enabled in the Treo kernel's .config: - - CONFIG_MTD=y - CONFIG_MTD_CMDLINE_PARTS=y - CONFIG_MTD_CHAR=y - CONFIG_MTD_NAND_DOCG4=m - - Note that the docg4 nand driver is configured as a module, because we will - want to load and unload it with reliable_mode enabled or disabled as needed. - - You will also need to specify mtd partitions on the kernel command line. In - the instructions that follow, we will assume that the flash blocks to which - u-boot will be programmed are defined by the second partition on the device. - The u-boot config file (include/configs/palmtreo680.h) places the u-boot image - at the start of block 6 (offset 0x180000), which is the first writable - (non-protected) block on the flash (this is also where the PalmOS SPL starts). - The u-boot image occupies four blocks, so to create the u-boot partition, pass - this command line to the kernel: - mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) - This will create three partitions: - protected_part: the first six blocks, which are read-only - bootloader_part: the next four blocks, for the u-boot image - filesys_part: the remainder of the device - The mtdchar kernel device driver will use device nodes /dev/mtd0, /dev/mtd1, - and /dev/mtd2 for these partitions, respectively. Ensure that your root file - system at least has /dev/mtd1 if you are not running udev or mdev. - -Userspace Utilities: - - In addition to everything necessary to provide a useful userspace environment - (busybox is indispensable, of course), you will need the mtd-utils package on - your root filesystem. I use version 1.5.0 of mtd-utils, and I suggest you use - this version as well, or at leat a version very close to this one, as - mtd-utils has tended to be fluid. - - Note that busybox includes a version of mtd-utils. These are deficient and - should not be used. When you run one of these utilities (nanddump, etc), - ensure you are invoking the separate executable from mtd-utils, and not the - one built into busybox. I recommend that you configure busybox with its - mtd-utils disabled to avoid any possibility of confusion. - - You will also need to cross-compile the userspace Linux utility in - tools/palmtreo680/flash_u-boot.c, which we will run on the Treo to perform the - actual write of the u-boot image to flash. This utility links against libmtd - from the mtd-utils package. - - -Desktop PC-side Software Prerequisites -====================================== - -Terminal emulator application: - minicom, kermit, etc. - -Linux kernel: - Compiled with CONFIG_USB_SERIAL enabled. Build this as a module. - - -Recommended (Not directly related to u-boot) -============================================ - -Working directly on the Treo's tiny screen and keypad is difficult and -error-prone. I recommend that you log into the Linux kernel running on your -Treo from your desktop PC using ethernet over usb. The desktop's kernel must be -configured with CONFIG_USB_USBNET, CONFIG_USB_NET_CDCETHER, and -CONFIG_USB_NET_CDC_SUBSET. The Treo's kernel will need CONFIG_USB_ETH, and its -init script will need to start an ssh daemon like dropbear. Note that the usb0 -network interface will not appear on the desktop PC until the Treo kernel's usb -ethernet gadget driver has initialized. You must wait for this to occur (watch -the PC's kernel log) before you can assign usb0 an ip address and log in to the -Treo. If you also build the Treo's kernel with CONFIG_IP_PNP enabled, you can -pass its ip address on the kernel command line, and obviate the need to -initialize the network interface in your init script. - -Having the Palm usb cable connected to the host has the added benefit of keeping -power supplied to your Treo, reducing the drain on the battery. If something -goes wrong while you're programming u-boot to the flash, you will have lots of -time to correct it before the battery dies. - -I have encountered a situation where the kernel is sometimes unable to mount a -root filesystem on the mmc card due to the mmc controller not initializing in -time, (and CONFIG_MMC_UNSAFE_RESUME doesn't seem to help) so I recommend that -you build a minimal root filesystem into the kernel using the kernel's initramfs -feature (CONFIG_BLK_DEV_INITRD). If you want your root filesystem on the mmc -card, your init script can mount and switch_root to the mmc card after a short -sleep. But keep in mind that in this case you won't be able to use an mmc card -to transfer files between your desktop and the Treo once Linux is running. -Another option for transfering files is to mount an nfs filesystem exported by -the desktop PC. For greatest convenience, you can export the root filesystem -itself from your desktop PC and switch_root to it in your init script. This -will work if your initramfs init script contains a loop that waits for you to -initialize the usb0 network interface on the desktop PC; e.g., loop while a ping -to the desktop PC returns an error. After the loop exits, do the nfs mount and -call switch_root. (You can not use the kernel nfsroot feature because the -network will not be up when the kernel expects it to be; i.e., not until you -configure the usb0 interface on the desktop.) Use the nfs 'nolock' option when -mounting to avoid the need to run a portmapper like rpcbind. - - -Preliminaries -============= - -Once Linux is running on your Treo, you may want to perform a few sanity checks -before programming u-boot. These checks will verify my assumptions regarding -all the Treo 680s out there, and also ensure that the flash and mtd-utils are -working correctly. If you are impatient and reckless, you may skip this -section, but see disclaimer at the top of this file! - -Load the docg4 driver: - - $ modprobe docg4 ignore_badblocks=1 reliable_mode=1 - -We tell the driver to use the docg4's "reliable mode" when writing because this -is the format required by the IPL, which runs from power-up and loads the first -portion of u-boot. We must ignore bad blocks because linux mtd uses out-of-band -(oob) bytes to mark bad blocks, which will cause the blocks written by PalmOS to -be misidentified as "bad" by libmtd. - -Check the kernel log to ensure that all's well: - - $ dmesg | tail - <... snip ...> - docg4 docg4: NAND device: 128MiB Diskonchip G4 detected - 3 cmdlinepart partitions found on MTD device Msys_Diskonchip_G4 - Creating 3 MTD partitions on "Msys_Diskonchip_G4": - 0x000000000000-0x000000180000 : "protected_part" - 0x000000180000-0x000000280000 : "bootloader_part" - 0x000000280000-0x000008000000 : "filesys_part" - -Ensure that the partition boundaries are as shown. (If no partitions are shown, -did you remember to pass them to the kernel on the command line?) We will write -u-boot to bootloader_part, which starts at offset 0x180000 (block 6) and spans 4 -256k blocks. This partition is accessed through the device node /dev/mtd1. - -The docg4 contains a read-only table that identifies blocks that were marked as -bad at the factory. This table is in the page at offset 0x2000, which is within -the partition protected_part (/dev/mtd0). There is a slight chance that one or -more of the four blocks that we will use for u-boot is listed in the table, so -use nanddump to inspect the table to see if this is the case: - - $ nanddump -p -l 512 -s 0x2000 -o /dev/mtd0 - ECC failed: 0 - ECC corrected: 0 - Number of bad blocks: 0 - Number of bbt blocks: 0 - Block size 262144, page size 512, OOB size 16 - Dumping data starting at 0x00002000 and ending at 0x00002200... - 0x00002000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff - <... snip ...> - -The format of the table is simple: one bit per block, with block numbers -increasing from left to right, starting with block 0 as the most significant bit -of the first byte. A bit will be clear if the corresponding block is bad. We -want to use blocks 6 throgh 9, so both of the two least significant bits of the -first byte must be set, as must the two most significant bits of the second -byte. If this is not true in your case (you are very unlucky), you should use -the first contiguous set of four good blocks after block 6, and adjust the -partition boundaries accordingly. You will also have to change the value of -CONFIG_SYS_NAND_U_BOOT_OFFS in include/configs/palmtreo680.h and recompile -u-boot. Because the two blocks loaded by the IPL do not have to be contiguous, -but our SPL expects them to be, you will need to erase any good blocks that are -at an offset prior to CONFIG_SYS_NAND_U_BOOT_OFFS, so that the IPL does not find -the magic number in oob and load it. Once you have done all this, the -instructions in this file still apply, except that the instructions below for -restoring the original PalmOS block contents may need to be modified. - -Next, use nanddump to verify that the PalmOS SPL is where we expect it to be. -The SPL can be identified by a magic number in the oob bytes of the first page -of each of the two blocks containing the SPL image. Pages are 512 bytes in -size, so to dump the first page, plus the oob: - - $ nanddump -p -l 512 -s 0 -o /dev/mtd1 - ECC failed: 0 - ECC corrected: 0 - Number of bad blocks: 0 - Number of bbt blocks: 0 - Block size 262144, page size 512, OOB size 16 - Dumping data starting at 0x00000000 and ending at 0x00000200... - 0x00000000: 0a 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00 - <... snip ...> - 0x000001f0: 13 4c 21 60 13 4d 2a 69 13 4b 29 69 89 1a 99 42 - OOB Data: 42 49 50 4f 30 30 30 10 3a e2 00 92 be a0 11 ff - -Verify that the first seven bytes of oob data match those in the above line. -(This is ASCII "BIPO000".) - -Do the same for the next block: - $ nanddump -p -l 512 -s 0x40000 -o /dev/mtd1 - -The first seven oob bytes in last line should read: - - OOB Data: 42 49 50 4f 30 30 31 81 db 8e 8f 46 07 9b 59 ff - -(This is ASCII "BIPO001".) - -For additional assurance, verify that the next block does *not* contain SPL -data. - - $ nanddump -p -l 512 -s 0x80000 -o /dev/mtd1 - -It doesn't matter what the oob contains, as long as the first four bytes are -*not* ASCII "BIPO". PalmOS should only be using two blocks for the SPL -(although we will need four for u-boot). - -If you want, you can back up the contents of bootloader_part to a file. You may -be able to restore it later, if desired (see "Restoring PalmOS" below). - - $ nanddump -l 0x100000 -s 0 -o -f bootloader_part.orig /dev/mtd1 - -nanddump will spew voluminous warnings about uncorrectable ecc errors. This is -a consequence of reading pages that were written in reliable mode, and is -expected (these should all occur on pages in odd-numbered 2k regions; i.e., -0x800, 0xa00, 0xc00, 0xe00, 0x1800, 0x1a00, ...). The size of the file -bootloader_part.orig should be 1081344, which is 2048 pages, each of size 512 -plus 16 oob bytes. If you are using initramfs for the root filesystem, don't -forget to copy the file to permanent storage, such as an mmc card. - -If all of the above went well, you can now program u-boot. - - -Programming u-boot -================== - -Our u-boot includes a small SPL that must be prepended to u-boot proper. From -the base u-boot source directory on your desktop PC: - - $ cat spl/u-boot-spl.bin u-boot.bin > u-boot-concat.bin - -cd to the tools/palmtreo680/ directory, and cross-compile flash_u-boot.c for the -Treo: - - $(CC) -o flash_u-boot $(CFLAGS) $(INCLUDEPATH) $(LIBPATH) flash_u-boot.c -lmtd - -Substitute variable values from your cross-compilation environment as -appropriate. Note that it links to libmtd from mtd-utils, and this must be -included in $(LIBPATH) and $(INCLUDEPATH). - -Transfer u-boot-concat.bin and the compiled flash_u-boot utility to the Treo's -root filesystem. On the Treo, cd to the directory where these files were -placed. - -Load the docg4 driver if you have not already done so. - - $ modprobe docg4 ignore_badblocks=1 reliable_mode=1 - -Erase the blocks to which we will write u-boot: - - $ flash_erase /dev/mtd1 0x00 4 - -If no errors are reported, write u-boot to the flash: - - $ ./flash_u-boot u-boot-concat.bin /dev/mtd1 - -You can use nanddump (see above) to verify that the data was written. This -time, "BIPO" should be seen in the first four oob bytes of the first page of all -four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000. - -Shutdown linux, remove and re-insert the battery, hold your breath... - - -Enjoying u-boot -=============== - -After you insert the battery, the u-boot splash screen should appear on the lcd -after a few seconds. With the usb cable connecting the Treo to your PC, in the -kernel log of your PC you should see - - <6>usb 3-1: New USB device found, idVendor=0525, idProduct=a4a6 - <6>usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - <6>usb 3-1: Product: U-Boot 2013.01-00167-gd62ef56-dirty - <6>usb 3-1: Manufacturer: Das U-Boot - -Load the usbserial module on your desktop PC: - - $ modprobe usbserial vendor=0x0525 product=0xa4a6 - -and run your favorite terminal emulation utility (minicom, kermit, etc) with the -serial device set to /dev/ttyUSB0 (assuming this is your only usb serial -device). You should be at the u-boot console (type 'help'). - -There is not much that is unique about using u-boot on the palm treo 680. -Kernels can be loaded from mmc, flash, and from the desktop PC via kermit. You -can expand the size of the second partition on the flash to contain a kernel, or -else put the kernel(s) in their own partition. - -Nand commands work as expected, with the excepton that blocks not written by the -linux mtd subsystem may be misidentified by the u-boot docg4 driver as "bad" if -they contain data in the oob bytes. This will be the case for the blocks -containing the u-boot image, for example. To work around this, use 'nand scrub' -instead of 'nand erase' to erase these blocks, and 'nand read.raw' to read them -to memory. (It would be useful if u-boot's nand commands provided a way to -explicitly ignore "bad" blocks, because read.raw does not perform ecc.) The -'nand dump' command will read these "bad" blocks, however. - -Currently u-boot itself can only be programmed to flash from Linux; there is no -support for reliable mode in u-boot's docg4 flash driver. This should be -corrected soon. - - -Customizing -=========== - -If you change u-boot's configuration significantly (adding or removing -features), you may have to adjust the value of CONFIG_SYS_NAND_U_BOOT_SIZE. -This is the size of the concatenated spl + u-boot image, and tells the SPL how -many flash blocks it needs to load. It will be rounded up to the next 64k -boundary (the spl flash block capacity), so it does not have to be exact, but -you must ensure that it is not less than the actual image size. If it is larger -than the image, blocks may be needlessly loaded, but if too small, u-boot may -only be partially loaded, resulting in a boot failure (bricked phone), so better -to be too large. The flash_u-boot utility will work with any size image and -write the required number of blocks, provided that the partition is large -enough. - -As the first writable block on the device, block 6 seems to make the most sense -as the flash offset for writing u-boot (and this is where PalmOS places its -SPL). But you can place it elsewhere if you like. If you do, you need to -adjust CONFIG_SYS_NAND_U_BOOT_OFFS accordingly, and you must ensure that blocks -preceeding the ones containing u-boot do *not* have the magic number in oob (the -IPL looks for this). In other words, make sure that any blocks that previously -contained the u-boot image or PalmOS SPL are erased (and optionally written with -something else) so that the IPL does not load it. Also make sure that the new -u-boot starting offset is at the start of a flash partition (check the kernel -log after loading the docg4 driver), and pass the corresponding mtd device file -to the flash_u-boot utility. - -The u-boot built-in default environment is used because a writable environment -in flash did not seem worth the cost of a 256k flash block. But adding this -should be straightforward. - - -Restoring PalmOS -================ - -If you backed up the contents of bootloader_part flash partition earlier, you -should be able to restore it with the shell script shown below. The first two -blocks of data contain the PalmOS SPL and were written in reliable mode, whereas -the next two blocks were written in normal mode, so the script has to load and -unload the docg4 driver. Make sure that the mtd-utils nandwrite and flash_erase -are in your path (and are not those from busybox). Also double-check that the -backup image file bootloader_part.orig is exactly 1081344 bytes in length. If -not, it was not backed up correctly. Run the script as: - - ./restore_bootpart bootloader_part.orig /dev/mtd1 - -The script will take a minute or so to run. When it finishes, you may want to -verify with nanddump that the data looks correct before you cycle power, because -if the backup or restore failed, your phone will be bricked. Note that as a -consequence of reliable mode, the odd-numbered 2k regions in the first two -blocks will not exactly match the contents of the backup file, (so unfortunately -we can't simply dump the flash contents to a file and do a binary diff with the -original back-up image to verify that it was restored correctly). Also, -nanddump will report uncorrectable ecc errors when it reads those regions. - -#!/bin/sh - -if [ $# -ne 2 ]; then - echo "usage: $0: " - exit 1 -fi - -# reliable mode used for the first two blocks -modprobe -r docg4 -modprobe docg4 ignore_badblocks=1 reliable_mode=1 || exit 1 - -# erase all four blocks -flash_erase $2 0 4 - -# Program the first two blocks in reliable mode. -# 2k (4 pages) is written at a time, skipping alternate 2k regions -# Note that "2k" is 2112 bytes, including 64 oob bytes -file_ofs=0 -flash_ofs=0 -page=0 -while [ $page -ne 1024 ]; do - dd if=$1 bs=2112 skip=$file_ofs count=1 | nandwrite -o -n -s $flash_ofs $2 - || exit 1 - file_ofs=$((file_ofs+2)) - flash_ofs=$((flash_ofs+0x1000)) - page=$((page+8)) -done; - -# normal mode used for the next two blocks -modprobe -r docg4 -modprobe docg4 ignore_badblocks=1 || exit 1 -dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1 -modprobe -r docg4 - -TODO -==== - - - Keypad support. - - Interactive boot menu using keypad and lcd. - - Add reliable mode support to the u-boot docg4 driver. - - U-boot command that will write a new image to the bootloader partition in - flash. - - Linux FTD support. diff --git a/board/palmtreo680/palmtreo680.c b/board/palmtreo680/palmtreo680.c deleted file mode 100644 index f4f6e1f5b95..00000000000 --- a/board/palmtreo680/palmtreo680.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Palm Treo 680 Support - * - * Copyright (C) 2013 Mike Dunn - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static struct nand_chip docg4_nand_chip; - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100; - - return 0; -} - -int dram_init(void) -{ - /* IPL initializes SDRAM (we're already running from it) */ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_LCD -void lcd_enable(void) -{ - /* - * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd - * driver code. We need it as an output gpio. - */ - writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L); - - /* power-up and enable the lcd */ - writel(0x00400000, GPSR(86)); /* enable; drive high */ - writel(0x00002000, GPSR(77)); /* power; drive high */ - writel(0x02000000, GPCR(25)); /* enable_n; drive low */ - - /* turn on LCD backlight and configure PWM for reasonable brightness */ - writel(0x00, PWM_CTRL0); - writel(0x1b1, PWM_PERVAL0); - writel(0xfd, PWM_PWDUTY0); - writel(0x00000040, GPSR(38)); /* backlight power on */ -} -#endif - -#ifdef CONFIG_MMC -int board_mmc_init(bd_t *bis) -{ - writel(1 << 10, GPSR(42)); /* power on */ - return pxa_mmc_register(0); -} -#endif - -void board_nand_init(void) -{ - /* we have one 128M diskonchip G4 */ - - struct mtd_info *mtd = &nand_info[0]; - struct nand_chip *nand = &docg4_nand_chip; - if (docg4_nand_init(mtd, nand, 0)) - hang(); -} - -#ifdef CONFIG_SPL_BUILD -void nand_boot(void) -{ - __attribute__((noreturn)) void (*uboot)(void); - - extern const void *_start, *_end; /* boundaries of spl in memory */ - - /* size of spl; ipl loads this, and then a portion of u-boot */ - const size_t spl_image_size = ((size_t)&_end - (size_t)&_start); - - /* the flash offset of the blocks that are loaded by the spl */ - const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS + - DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE; - - /* total number of bytes loaded by IPL */ - const size_t ipl_load_size = - DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL; - - /* number of bytes of u-boot proper that was loaded by the IPL */ - const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size; - - /* number of remaining bytes of u-boot that the SPL must load */ - const size_t spl_load_size = - CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size; - - /* memory address where we resume loading u-boot */ - void *const load_addr = - (void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size); - - /* - * Copy the portion of u-boot already read from flash by the IPL to its - * correct load address. - */ - memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size); - - /* - * Resume loading u-boot where the IPL left off. - */ - nand_spl_load_image(spl_load_offset, spl_load_size, load_addr); - -#ifdef CONFIG_NAND_ENV_DST - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (void *)CONFIG_NAND_ENV_DST); - -#ifdef CONFIG_ENV_OFFSET_REDUND - nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); -#endif -#endif - /* - * Jump to U-Boot image - */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - (*uboot)(); -} - -void board_init_f(ulong bootflag) -{ - nand_boot(); -} - -#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/palmtreo680_defconfig b/configs/palmtreo680_defconfig deleted file mode 100644 index b56191d8764..00000000000 --- a/configs/palmtreo680_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_PALMTREO680=y -CONFIG_SPL=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h deleted file mode 100644 index 5ffed829559..00000000000 --- a/include/configs/palmtreo680.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Palm Treo 680 configuration file - * - * Copyright (C) 2013 Mike Dunn - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X -#define CONFIG_PALMTREO680 -#define CONFIG_MACH_TYPE MACH_TYPE_TREO680 - -#define CONFIG_SYS_MALLOC_LEN (4096*1024) - -#define CONFIG_LZMA - -/* - * Serial Console Configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_CONS_INDEX 3 - -/* we have nand (although technically nand *is* flash...) */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_LCD -/* #define CONFIG_KEYBOARD */ /* TODO */ - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_ACX544AKN -#define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR16 -#define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */ -#define CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */ -#define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */ -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -#endif - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#endif - -/* - * HUSH Shell Configuration - */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_SYS_LONGHELP -#undef CONFIG_SYS_PROMPT -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " -#else -#endif -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * DRAM Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x0E000000 -#define CONFIG_SYS_GAFR0_U_VAL 0xA500001A -#define CONFIG_SYS_GAFR1_L_VAL 0x60000002 -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959 -#define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA -#define CONFIG_SYS_GAFR2_U_VAL 0x41440F08 -#define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF -#define CONFIG_SYS_GAFR3_U_VAL 0x00001401 -#define CONFIG_SYS_GPCR0_VAL 0x1FF80400 -#define CONFIG_SYS_GPCR1_VAL 0x03003FC1 -#define CONFIG_SYS_GPCR2_VAL 0x01C1E000 -#define CONFIG_SYS_GPCR3_VAL 0x01C1E000 -#define CONFIG_SYS_GPDR0_VAL 0xCFF90400 -#define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1 -#define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF -#define CONFIG_SYS_GPDR3_VAL 0x0069FF81 -#define CONFIG_SYS_GPSR0_VAL 0x02000018 -#define CONFIG_SYS_GPSR1_VAL 0x00000000 -#define CONFIG_SYS_GPSR2_VAL 0x000C0000 -#define CONFIG_SYS_GPSR3_VAL 0x00080000 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x01ffffff -#define CONFIG_SYS_CCCR 0x02000210 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 -#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 -#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 -#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd -#define CONFIG_SYS_MDREFR_VAL 0x201fa031 -#define CONFIG_SYS_MDMRS_VAL 0x00320032 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 -#define CONFIG_SYS_MECR_VAL 0x00000003 -#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 -#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 -#define CONFIG_SYS_MCATT0_VAL 0x0001c391 -#define CONFIG_SYS_MCATT1_VAL 0x0001c391 -#define CONFIG_SYS_MCIO0_VAL 0x00014611 -#define CONFIG_SYS_MCIO1_VAL 0x0001c391 - -/* - * USB - */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY -#define CONFIG_USB_DEV_PULLUP_GPIO 114 - -/* - * SPL - */ -#define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */ -#define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */ -#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */ -#define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */ - -/* - * NAND - */ -#define CONFIG_NAND_DOCG4 -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */ -#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */ -#define CONFIG_SYS_NAND_PAGE_SIZE 0x200 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 -#define CONFIG_BITREVERSE /* needed by docg4 driver */ -#define CONFIG_BCH /* needed by docg4 driver */ - -/* - * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It - * will be rounded up to the next 64k boundary (the spl flash block size), so it - * does not have to be exact, but you must ensure that it is not less than the - * actual image size, or it may fail to boot (bricked phone)! - * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.) -*/ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */ - -/* - * This is the byte offset into the flash at which the concatenated spl + u-boot - * image is placed. It must be at the start of a block (256k boundary). Blocks - * 0 - 5 are write-protected, so we start at block 6. - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */ - -/* DRAM address to which u-boot proper is loaded (before it relocates itself) */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST - -/* passed to linker by Makefile as arg to -Ttext option */ -#define CONFIG_SYS_TEXT_BASE 0xa0000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */ - -/* - * environment - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_BUILD_ENVCRC -#define CONFIG_ENV_SIZE 0x200 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=usbtty\0" \ - "stdout=usbtty\0" \ - "stderr=usbtty" -#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \ -ip=192.168.11.102:::255.255.255.0:treo:usb0" -#define CONFIG_BOOTDELAY 3 - -#if 0 /* example: try 2nd mmc partition, then nand */ -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \ - "bootm 0xa1000000; " \ - "elif nand read 0xa1000000 0x280000 0x240000; then " \ - "bootm 0xa1000000; " \ - "fi; " -#endif - -/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */ -#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000 - -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_ICACHE_OFF - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From b9599dd857b3f6ed9c7c7e7438dffb84ee5ce1a0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:39 -0600 Subject: arm: Remove tx25 board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 6 -- board/karo/tx25/Kconfig | 15 --- board/karo/tx25/MAINTAINERS | 6 -- board/karo/tx25/Makefile | 11 --- board/karo/tx25/lowlevel_init.S | 98 ------------------- board/karo/tx25/tx25.c | 210 ---------------------------------------- configs/tx25_defconfig | 6 -- include/configs/tx25.h | 172 -------------------------------- 8 files changed, 524 deletions(-) delete mode 100644 board/karo/tx25/Kconfig delete mode 100644 board/karo/tx25/MAINTAINERS delete mode 100644 board/karo/tx25/Makefile delete mode 100644 board/karo/tx25/lowlevel_init.S delete mode 100644 board/karo/tx25/tx25.c delete mode 100644 configs/tx25_defconfig delete mode 100644 include/configs/tx25.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e9cd91a5c85..9fd248f25a4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -134,11 +134,6 @@ config TARGET_MX25PDK bool "Support mx25pdk" select CPU_ARM926EJS -config TARGET_TX25 - bool "Support tx25" - select CPU_ARM926EJS - select SUPPORT_SPL - config TARGET_ZMX25 bool "Support zmx25" select CPU_ARM926EJS @@ -739,7 +734,6 @@ source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" -source "board/karo/tx25/Kconfig" source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" diff --git a/board/karo/tx25/Kconfig b/board/karo/tx25/Kconfig deleted file mode 100644 index 42746c1c0f6..00000000000 --- a/board/karo/tx25/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TX25 - -config SYS_BOARD - default "tx25" - -config SYS_VENDOR - default "karo" - -config SYS_SOC - default "mx25" - -config SYS_CONFIG_NAME - default "tx25" - -endif diff --git a/board/karo/tx25/MAINTAINERS b/board/karo/tx25/MAINTAINERS deleted file mode 100644 index 2defe342fff..00000000000 --- a/board/karo/tx25/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TX25 BOARD -M: John Rigby -S: Maintained -F: board/karo/tx25/ -F: include/configs/tx25.h -F: configs/tx25_defconfig diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile deleted file mode 100644 index add5dd36692..00000000000 --- a/board/karo/tx25/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2009 DENX Software Engineering -# Author: John Rigby -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += lowlevel_init.o -endif -obj-y += tx25.o diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S deleted file mode 100644 index 11b80b42a3c..00000000000 --- a/board/karo/tx25/lowlevel_init.S +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * Based on U-Boot and RedBoot sources for several different i.mx - * platforms. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -.macro init_clocks - /* - * clocks - * - * first enable CLKO debug output - * 0x40000000 enables the debug CLKO signal - * 0x05000000 sets CLKO divider to 6 - * 0x00600000 makes CLKO parent clk the USB clk - */ - write32 0x53f80064, 0x45600000 - - /* CCTL: ARM = 399 MHz, AHB = 133 MHz */ - write32 0x53f80008, 0x20034000 - - /* - * PCDR2: NFC = 33.25 MHz - * This is required for the NAND Flash of this board, which is a Samsung - * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with - * the NFC driver in symmetric (i.e. one-cycle) mode. - */ - write32 0x53f80020, 0x01010103 - - /* - * enable all implemented clocks in all three - * clock control registers - */ - write32 0x53f8000c, 0x1fffffff - write32 0x53f80010, 0xffffffff - write32 0x53f80014, 0xfdfff -.endm - -.macro init_ddrtype - /* - * ddr_type is 3.3v SDRAM - */ - write32 0x43fac454, 0x800 -.endm - -/* - * sdram controller init - */ -.macro init_sdram_bank bankaddr, ctl, cfg - ldr r0, =0xb8001000 - ldr r2, =\bankaddr - /* - * reset SDRAM controller - * then wait for initialization to complete - */ - ldr r1, =(1 << 1) - str r1, [r0, #0x10] -1: ldr r3, [r0, #0x10] - tst r3, #(1 << 31) - beq 1b - - ldr r1, =0x95728 - str r1, [r0, #\cfg] /* config */ - - ldr r1, =0x92116480 /* control | precharge */ - str r1, [r0, #\ctl] /* write command to controller */ - str r1, [r2, #0x400] /* command encoded in address */ - - ldr r1, =0xa2116480 /* auto refresh */ - str r1, [r0, #\ctl] - ldrb r3, [r2] /* read dram twice to auto refresh */ - ldrb r3, [r2] - - ldr r1, =0xb2116480 /* control | load mode */ - str r1, [r0, #\ctl] /* write command to controller */ - strb r1, [r2, #0x33] /* command encoded in address */ - - ldr r1, =0x82116480 /* control | normal (0)*/ - str r1, [r0, #\ctl] /* write command to controller */ -.endm - -.globl lowlevel_init -lowlevel_init: - init_aips - init_max - init_m3if - init_clocks - - init_sdram_bank 0x80000000, 0x0, 0x4 - - init_sdram_bank 0x90000000, 0x8, 0xc - mov pc, lr diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c deleted file mode 100644 index 4d1a0ec7257..00000000000 --- a/board/karo/tx25/tx25.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * Based on imx27lite.c: - * Copyright (C) 2008,2009 Eric Jarrige - * Copyright (C) 2009 Ilya Yanok - * And: - * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong bootflag) -{ - /* - * copy ourselves from where we are running to where we were - * linked at. Use ulong pointers as all addresses involved - * are 4-byte-aligned. - */ - ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; - asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); - asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); - asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); - asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); - for (dst = start_ptr; dst < end_ptr; dst++) - *dst = *(dst+(run_ptr-link_ptr)); - /* - * branch to nand_boot's link-time address. - */ - asm volatile("ldr pc, =nand_boot"); -} -#endif - -#ifdef CONFIG_FEC_MXC -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define FEC_OUT_PAD_CTRL 0 - -#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) -#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) - -void tx25_fec_init(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), - - NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */ - NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */ - }; - - static const iomux_v3_cfg_t fec_cfg_pads[] = { - MX25_PAD_FEC_RDATA0__GPIO_3_10, - MX25_PAD_FEC_RDATA1__GPIO_3_11, - MX25_PAD_FEC_RX_DV__GPIO_3_12, - }; - - debug("tx25_fec_init\n"); - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* drop PHY power and assert reset (low) */ - gpio_direction_output(GPIO_FEC_RESET_B, 0); - gpio_direction_output(GPIO_FEC_ENABLE_B, 0); - - mdelay(5); - - debug("resetting phy\n"); - - /* turn on PHY power leaving reset asserted */ - gpio_set_value(GPIO_FEC_ENABLE_B, 1); - - mdelay(10); - - /* - * Setup some strapping pins that are latched by the PHY - * as reset goes high. - * - * Set PHY mode to 111 - * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 - * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 - * mode2 is tied high so nothing to do - * - * Turn on RMII mode - * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode - */ - /* - * set each mux mode to gpio mode - */ - imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, - ARRAY_SIZE(fec_cfg_pads)); - - /* - * set each to 1 and make each an output - */ - gpio_direction_output(IMX_GPIO_NR(3, 10), 1); - gpio_direction_output(IMX_GPIO_NR(3, 11), 1); - gpio_direction_output(IMX_GPIO_NR(3, 12), 1); - - mdelay(22); /* this value came from RedBoot */ - - /* - * deassert PHY reset - */ - gpio_set_value(GPIO_FEC_RESET_B, 1); - - mdelay(5); - - /* - * set FEC pins back - */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} -#else -#define tx25_fec_init() -#endif - -#ifdef CONFIG_MXC_UART -/* - * Set up input pins with hysteresis and 100-k pull-ups - */ -#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define UART1_OUT_PAD_CTRL 0 - -static void tx25_uart1_init(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} -#else -#define tx25_uart1_init() -#endif - -int board_init() -{ - tx25_uart1_init(); - - /* board id for linux */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - return 0; -} - -int board_late_init(void) -{ - tx25_fec_init(); - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); -#else - -#endif -} - -int checkboard(void) -{ - printf("KARO TX25\n"); - return 0; -} diff --git a/configs/tx25_defconfig b/configs/tx25_defconfig deleted file mode 100644 index b7524141026..00000000000 --- a/configs/tx25_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TX25=y -CONFIG_SPL=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/tx25.h b/include/configs/tx25.h deleted file mode 100644 index 834b6169f6f..00000000000 --- a/include/configs/tx25.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * KARO TX25 board - SoC Configuration - */ -#define CONFIG_MX25 -#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */ -#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ - -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SPL_MAX_SIZE 2048 -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#define CONFIG_SPL_TEXT_BASE 0x810c0000 -#define CONFIG_SYS_TEXT_BASE 0x81200000 - -#ifndef MACH_TYPE_TX25 -#define MACH_TYPE_TX25 2177 -#endif - -#define CONFIG_MACH_TYPE MACH_TYPE_TX25 - -#ifdef CONFIG_SPL_BUILD -/* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 - -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST - -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#else -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Memory Info - */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -/* - * Board has 2 32MB banks of DRAM but there is a bug when using - * both so only the first is configured - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#if (CONFIG_NR_DRAM_BANKS == 2) -#define PHYS_SDRAM_2 0x90000000 -#define PHYS_SDRAM_2_SIZE 0x02000000 -#endif -/* 8MB DRAM test */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000) - -/* - * Serial Info - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -#define CONFIG_MXC_GPIO - -/* - * Flash & Environment - */ -/* No NOR flash present */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN -#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - -/* NAND */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (0xBB000000) -#define CONFIG_JFFS2_NAND -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer sz */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP - -/* U-Boot commands */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_CACHE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_MII -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=tx25/u-boot.bin\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "hostname=tx25\0" \ - "bootfile=tx25/uImage\0" \ - "rootpath=/opt/eldk/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ - "upd=run load update\0" \ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 0ddc5a2dee424be8522fa1d68685dd2eb91f9887 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 2 Sep 2015 11:10:59 +0200 Subject: arm: spear: Add BCH4 SW support to SPEAr600 x600 board This board is equipped with a Micron NAND chip (MT29F1G08ABADAH4) that needs 4-bit ECC. But the SPEAr600 only supports 1-bit HW ECC internally. This patch enables the SW 4-bit BCH support for this board. Signed-off-by: Stefan Roese Cc: Viresh Kumar --- include/configs/x600.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/x600.h b/include/configs/x600.h index 6a5738863ad..f672485d69d 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -67,6 +67,8 @@ #define CONFIG_MTD_ECC_SOFT #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_ECC_BCH +#define CONFIG_BCH /* UBI/UBI config options */ #define CONFIG_MTD_DEVICE -- cgit v1.3.1 From 9b6aa00dbc7e946171c2c8ddae531ed83fc8e9e7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 2 Sep 2015 11:11:00 +0200 Subject: arm: spear: Enable THUMB mode on x600 board To reduce the size of the U-Boot image on the x600 board, lets enable the THUMB mode. This reduces the overall size to less than 0x6000 bytes. Fitting it again in the onboard NOR flash. Signed-off-by: Stefan Roese Cc: Viresh Kumar --- include/configs/x600.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/x600.h b/include/configs/x600.h index f672485d69d..73ba67c3e91 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -17,6 +17,7 @@ #define CONFIG_SPEAR600 /* SPEAr600 SoC */ #define CONFIG_X600 /* on X600 board */ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_THUMB_BUILD #include -- cgit v1.3.1 From 6e295186c7fc8bf5be22a05f6ca9602f2bb507f2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 2 Sep 2015 17:24:57 -0600 Subject: Move malloc_cache_aligned() to its own header At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to a new header so that this can be avoided. The header would perhaps be better named as alignmem.h but it needs to be included after common.h and people might be confused by this. With the name memalign.h it fits nicely after malloc() in most cases. Signed-off-by: Simon Glass Acked-by: Marcel Ziswiler --- common/cmd_ubi.c | 2 +- drivers/mtd/nand/nand_util.c | 1 + fs/ubifs/super.c | 3 +++ fs/ubifs/ubifs.c | 2 ++ include/common.h | 9 --------- include/memalign.h | 25 +++++++++++++++++++++++++ lib/gzip.c | 1 + lib/zlib/zutil.c | 4 +++- 8 files changed, 36 insertions(+), 11 deletions(-) create mode 100644 include/memalign.h (limited to 'include') diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 10eea655701..0460b4cc56f 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -14,7 +14,7 @@ #include #include #include - +#include #include #include #include diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 21b4a618ce5..71285b66694 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 0bf52db0cef..41763a18979 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -28,6 +28,9 @@ #include #else +#include +#include +#include #include #include #include diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 4daa7fad53d..f7a084747e6 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -23,6 +23,8 @@ * Adrian Hunter */ +#include +#include #include "ubifs.h" #include diff --git a/include/common.h b/include/common.h index c12f402f773..c48e5bc11bf 100644 --- a/include/common.h +++ b/include/common.h @@ -1060,15 +1060,6 @@ int cpu_release(int nr, int argc, char * const argv[]); #define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) -#ifndef __ASSEMBLY__ -#include - -static inline void *malloc_cache_aligned(size_t size) -{ - return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); -} -#endif - /* * check_member() - Check the offset of a structure member * diff --git a/include/memalign.h b/include/memalign.h new file mode 100644 index 00000000000..f78b9dd9dc7 --- /dev/null +++ b/include/memalign.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ALIGNMEM_H +#define __ALIGNMEM_H + +/* + * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It + * is used to align DMA buffers. + */ +#ifndef __ASSEMBLY__ +#include + +#include + +static inline void *malloc_cache_aligned(size_t size) +{ + return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); +} +#endif + +#endif /* __ALIGNMEM_H */ diff --git a/lib/gzip.c b/lib/gzip.c index cd8e9fea43d..2c49e4e9ffa 100644 --- a/lib/gzip.c +++ b/lib/gzip.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "zlib/zutil.h" diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index 173a81d1ea4..227343e48d3 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c @@ -43,7 +43,9 @@ void z_error (m) */ #ifndef MY_ZCALLOC /* Any system without a special alloc function */ -#ifndef __UBOOT__ +#ifdef __UBOOT__ +#include +#else #ifndef STDC extern voidp malloc OF((uInt size)); extern voidp calloc OF((uInt items, uInt size)); -- cgit v1.3.1 From cf92e05c0135bc2b1a1b25a3218e31e6d79bad59 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 2 Sep 2015 17:24:58 -0600 Subject: Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass --- board/raspberrypi/rpi/rpi.c | 1 + board/samsung/common/misc.c | 1 + common/cmd_usb.c | 1 + common/env_fat.c | 1 + common/env_mmc.c | 1 + common/env_nand.c | 1 + common/env_ubi.c | 1 + common/usb.c | 1 + common/usb_hub.c | 1 + common/usb_kbd.c | 1 + common/usb_storage.c | 1 + disk/part_dos.c | 1 + disk/part_efi.c | 1 + disk/part_mac.c | 1 + drivers/block/ahci.c | 1 + drivers/mmc/dw_mmc.c | 1 + drivers/mmc/mmc.c | 1 + drivers/mmc/rpmb.c | 1 + drivers/mtd/nand/tegra_nand.c | 1 + drivers/net/e1000.c | 1 + drivers/net/fec_mxc.c | 1 + drivers/net/rtl8169.c | 1 + drivers/spi/mxs_spi.c | 1 + drivers/usb/eth/asix.c | 1 + drivers/usb/eth/asix88179.c | 1 + drivers/usb/eth/mcs7830.c | 1 + drivers/usb/eth/smsc95xx.c | 1 + drivers/usb/gadget/ether.c | 1 + drivers/usb/gadget/f_thor.c | 1 + drivers/usb/host/dwc2.c | 1 + drivers/usb/host/ehci-hcd.c | 1 + drivers/usb/host/ohci-hcd.c | 1 + drivers/usb/host/usb-uclass.c | 1 + drivers/video/bcm2835.c | 1 + fs/ext4/dev.c | 1 + fs/ext4/ext4_common.c | 1 + fs/ext4/ext4_write.c | 1 + fs/fat/fat.c | 1 + include/common.h | 87 ---------------------------------------- include/memalign.h | 93 ++++++++++++++++++++++++++++++++++++++++++- 40 files changed, 130 insertions(+), 88 deletions(-) (limited to 'include') diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index d21750e2a04..6d7be11518e 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index f0d69d4a48f..e0e2c48632c 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 6874af75471..6bdbbc5c052 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/common/env_fat.c b/common/env_fat.c index e4c848935ad..d79d864a0c1 100644 --- a/common/env_fat.c +++ b/common/env_fat.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/common/env_mmc.c b/common/env_mmc.c index 51e7707cb0f..96398224cc8 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/common/env_nand.c b/common/env_nand.c index 92e0e053dfe..b32eeac9d76 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/common/env_ubi.c b/common/env_ubi.c index 77bbfa6ef43..e0dc5af8513 100644 --- a/common/env_ubi.c +++ b/common/env_ubi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #undef crc32 diff --git a/common/usb.c b/common/usb.c index fbaf8ecbe23..700bfc315b6 100644 --- a/common/usb.c +++ b/common/usb.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/common/usb_hub.c b/common/usb_hub.c index 652a104361f..415b45c1f13 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 02270244417..95912f99c76 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/common/usb_storage.c b/common/usb_storage.c index b9784304086..b390310ee35 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include diff --git a/disk/part_dos.c b/disk/part_dos.c index cf1a36ebb82..89263d38aaa 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "part_dos.h" #ifdef HAVE_BLOCK_DEVICE diff --git a/disk/part_efi.c b/disk/part_efi.c index 5856f932111..15627f29e8b 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include diff --git a/disk/part_mac.c b/disk/part_mac.c index cbcb995c48c..099e0a0035b 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -15,6 +15,7 @@ #include #include +#include #include #include "part_mac.h" diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 0d19dd25a34..82c68439f86 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 1117fedefeb..a84c1e16d8b 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 371c1ec2123..2a58702848b 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "mmc_private.h" diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index 9d0b8bc0c8f..1c6888fc48f 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include "mmc_private.h" diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index debad4f791f..a77db7b65df 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 7b830ff8c05..2ba03ed73e4 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -32,6 +32,7 @@ tested on both gig copper and gig fiber boards #include #include #include +#include #include #include "e1000.h" diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bff5fd11197..79f6737e8e9 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 7b6e20f30fb..ebd46b27e5f 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #ifndef CONFIG_DM_ETH #include diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 2b9f395a978..627644b56bd 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 8a43e7c27d6..ad083cf8ae4 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "usb_ether.h" diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 94dfe85eff3..cf4085d7657 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -12,6 +12,7 @@ #include #include "usb_ether.h" #include +#include #include /* ASIX AX88179 based USB 3.0 Ethernet Devices */ diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index c1b708600e8..bbdad8b79ae 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "usb_ether.h" diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 1dcd088b8df..dc8fa8891be 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 53f4672291f..c5e35ee3507 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "gadget_chips.h" diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 06139ee04d2..ff1481ba372 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 85236aeb2a4..541c0f96870 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 88b670b7f8a..135ef726227 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 0ffd838db29..9bde2b252c0 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -41,6 +41,7 @@ #endif #include +#include #include #include "ohci.h" diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index b17a7d762e0..c66ebb6678d 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 61d054dd892..7867fe3895d 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -6,6 +6,7 @@ #include #include +#include #include #include diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c index c77c02cdfce..20f52566f09 100644 --- a/fs/ext4/dev.c +++ b/fs/ext4/dev.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include "ext4_common.h" diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index cab5465b9d4..c77e22d477a 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index fbc4c4b1cc1..d346c065cd8 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -23,6 +23,7 @@ #include +#include #include #include #include "ext4_common.h" diff --git a/fs/fat/fat.c b/fs/fat/fat.c index a863644d648..06dcbb70057 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include diff --git a/include/common.h b/include/common.h index c48e5bc11bf..68b24d0778d 100644 --- a/include/common.h +++ b/include/common.h @@ -973,93 +973,6 @@ int cpu_release(int nr, int argc, char * const argv[]); #define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) -/* - * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It - * is used to align DMA buffers. - */ -#ifndef __ASSEMBLY__ -#include -#endif - -/* - * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the - * stack that meets the minimum architecture alignment requirements for DMA. - * Such a buffer is useful for DMA operations where flushing and invalidating - * the cache before and after a read and/or write operation is required for - * correct operations. - * - * When called the macro creates an array on the stack that is sized such - * that: - * - * 1) The beginning of the array can be advanced enough to be aligned. - * - * 2) The size of the aligned portion of the array is a multiple of the minimum - * architecture alignment required for DMA. - * - * 3) The aligned portion contains enough space for the original number of - * elements requested. - * - * The macro then creates a pointer to the aligned portion of this array and - * assigns to the pointer the address of the first element in the aligned - * portion of the array. - * - * Calling the macro as: - * - * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024); - * - * Will result in something similar to saying: - * - * uint32_t buffer[1024]; - * - * The following differences exist: - * - * 1) The resulting buffer is guaranteed to be aligned to the value of - * ARCH_DMA_MINALIGN. - * - * 2) The buffer variable created by the macro is a pointer to the specified - * type, and NOT an array of the specified type. This can be very important - * if you want the address of the buffer, which you probably do, to pass it - * to the DMA hardware. The value of &buffer is different in the two cases. - * In the macro case it will be the address of the pointer, not the address - * of the space reserved for the buffer. However, in the second case it - * would be the address of the buffer. So if you are replacing hard coded - * stack buffers with this macro you need to make sure you remove the & from - * the locations where you are taking the address of the buffer. - * - * Note that the size parameter is the number of array elements to allocate, - * not the number of bytes. - * - * This macro can not be used outside of function scope, or for the creation - * of a function scoped static buffer. It can not be used to create a cache - * line aligned global buffer. - */ -#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) -#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) -#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ - char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ - + (align - 1)]; \ - \ - type *name = (type *) ALIGN((uintptr_t)__##name, align) -#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ - ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) -#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ - ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) -#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ - ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) - -/* - * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's - * purpose is to allow allocating aligned buffers outside of function scope. - * Usage of this macro shall be avoided or used with extreme care! - */ -#define DEFINE_ALIGN_BUFFER(type, name, size, align) \ - static char __##name[ALIGN(size * sizeof(type), align)] \ - __aligned(align); \ - \ - static type *name = (type *)__##name -#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ - DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) - /* * check_member() - Check the offset of a structure member * diff --git a/include/memalign.h b/include/memalign.h index f78b9dd9dc7..a9600390839 100644 --- a/include/memalign.h +++ b/include/memalign.h @@ -13,9 +13,100 @@ */ #ifndef __ASSEMBLY__ #include - #include +/* + * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the + * stack that meets the minimum architecture alignment requirements for DMA. + * Such a buffer is useful for DMA operations where flushing and invalidating + * the cache before and after a read and/or write operation is required for + * correct operations. + * + * When called the macro creates an array on the stack that is sized such + * that: + * + * 1) The beginning of the array can be advanced enough to be aligned. + * + * 2) The size of the aligned portion of the array is a multiple of the minimum + * architecture alignment required for DMA. + * + * 3) The aligned portion contains enough space for the original number of + * elements requested. + * + * The macro then creates a pointer to the aligned portion of this array and + * assigns to the pointer the address of the first element in the aligned + * portion of the array. + * + * Calling the macro as: + * + * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024); + * + * Will result in something similar to saying: + * + * uint32_t buffer[1024]; + * + * The following differences exist: + * + * 1) The resulting buffer is guaranteed to be aligned to the value of + * ARCH_DMA_MINALIGN. + * + * 2) The buffer variable created by the macro is a pointer to the specified + * type, and NOT an array of the specified type. This can be very important + * if you want the address of the buffer, which you probably do, to pass it + * to the DMA hardware. The value of &buffer is different in the two cases. + * In the macro case it will be the address of the pointer, not the address + * of the space reserved for the buffer. However, in the second case it + * would be the address of the buffer. So if you are replacing hard coded + * stack buffers with this macro you need to make sure you remove the & from + * the locations where you are taking the address of the buffer. + * + * Note that the size parameter is the number of array elements to allocate, + * not the number of bytes. + * + * This macro can not be used outside of function scope, or for the creation + * of a function scoped static buffer. It can not be used to create a cache + * line aligned global buffer. + */ +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) +#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) +#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + + (align - 1)]; \ + \ + type *name = (type *)ALIGN((uintptr_t)__##name, align) +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) +#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/* + * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's + * purpose is to allow allocating aligned buffers outside of function scope. + * Usage of this macro shall be avoided or used with extreme care! + */ +#define DEFINE_ALIGN_BUFFER(type, name, size, align) \ + static char __##name[ALIGN(size * sizeof(type), align)] \ + __aligned(align); \ + \ + static type *name = (type *)__##name +#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ + DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/** + * malloc_cache_aligned() - allocate a memory region aligned to cache line size + * + * This allocates memory at a cache-line boundary. The amount allocated may + * be larger than requested as it is rounded up to the nearest multiple of the + * cache-line size. This ensured that subsequent cache operations on this + * memory (flush, invalidate) will not affect subsequently allocated regions. + * + * @size: Minimum number of bytes to allocate + * + * @return pointer to new memory region, or NULL if there is no more memory + * available. + */ static inline void *malloc_cache_aligned(size_t size) { return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); -- cgit v1.3.1 From bcd62e72b2a0185f455ac5bac84416b59b294097 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Sep 2015 15:27:52 +0530 Subject: include: configs: Enable DWC3 and DFU in OMAP5 uEVM Enable dwc3, dwc3-omap and PHY to get DWC3 functional in OMAP5 uEVM. Also enable support for DFU. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Tom Rini --- include/configs/omap5_uevm.h | 62 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'include') diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 86479213fc8..18a2924fd47 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -19,6 +19,47 @@ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" #endif +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" + +#define DFU_ALT_INFO_EMMC \ + "dfu_alt_info_emmc=" \ + "rawemmc raw 0 3751936;" \ + "boot part 1 1;" \ + "rootfs part 1 2;" \ + "MLO fat 1 1;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ + "spl-os-args fat 1 1;" \ + "spl-os-image fat 1 1;" \ + "u-boot.img fat 1 1;" \ + "uEnv.txt fat 1 1\0" + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram 0x80200000 0x4000000;" \ + "fdt ram 0x80f80000 0x80000;" \ + "ramdisk ram 0x81000000 0x4000000\0" + +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM + #include #define CONFIG_CONS_INDEX 3 @@ -58,6 +99,27 @@ #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 +/* USB GADGET */ +#define CONFIG_USB_DWC3_PHY_OMAP +#define CONFIG_USB_DWC3_OMAP +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_USB_GADGET_DUALSPEED + +/* USB Device Firmware Update support */ +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_RAM +#define CONFIG_CMD_DFU + +#define CONFIG_DFU_MMC + /* Enabled commands */ #define CONFIG_CMD_DHCP /* DHCP Support */ -- cgit v1.3.1 From 99d969612f6e46192b4a963a7e5f8466a884f920 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:48 -0600 Subject: ARM: tegra: fix malloc region sizing Commit 52a7c98a1772 "tegra-common: increase malloc pool len by dfu mmc file buffer size" updated the definition of CONFIG_SYS_MALLOC_LEN for Tegra to take account of the DFU buffer size. However, this change had no effect, since typical Tegra board config headers don't set the DFU- related defines until after tegra-common.h is included. Fix this by moving the affected conditional code to tegra-common-post.h, which is included last. Also move the definition of SYS_NONCACHED_MEMORY since it's a related and adjacent definition. Fix the condition to test for the DFU feature, rather than specifically MMC DFU support, so it applies in all cases. Signed-off-by: Stephen Warren --- include/configs/tegra-common-post.h | 14 ++++++++++++++ include/configs/tegra-common.h | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index e67ff7b9571..594fa456d17 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -8,6 +8,20 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H +/* + * Size of malloc() pool + */ +#ifdef CONFIG_USB_FUNCTION_DFU +#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ + CONFIG_SYS_DFU_DATA_BUF_SIZE) +#else +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#endif + +#ifndef CONFIG_ARM64 +#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ +#endif + #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 6fe5f2ce654..b886c645076 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -36,20 +36,6 @@ #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ -/* - * Size of malloc() pool - */ -#ifdef CONFIG_DFU_MMC -#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ - CONFIG_SYS_DFU_DATA_BUF_SIZE) -#else -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#endif - -#ifndef CONFIG_ARM64 -#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#endif - /* * NS16550 Configuration */ -- cgit v1.3.1 From f69d72ee2a147b93f6d7664daf62af997e28f5b0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:49 -0600 Subject: ARM: tegra: tweak DFU buffer sizes CONFIG_SYS_DFU_DATA_BUF_SIZE defines the size of chunks transferred across USB. This doesn't need to be particularly large, since it doesn't limit the overall transfer size. CONFIG_SYS_DFU_MAX_FILE_SIZE is used to buffer an entire file before writing it to a filesystem. This define limits the maximum file size that may be transferred. Bump this up to 32MiB in order to support large uncompressed kernel images. Both of these buffers are dynamically allocated, and so the size of both needs to be taken into account when calculating the required malloc region size. Signed-off-by: Stephen Warren --- include/configs/tegra-common-post.h | 5 +++-- include/configs/tegra-common-usb-gadget.h | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 594fa456d17..651c4c49353 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -12,8 +12,9 @@ * Size of malloc() pool */ #ifdef CONFIG_USB_FUNCTION_DFU -#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ - CONFIG_SYS_DFU_DATA_BUF_SIZE) +#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ + CONFIG_SYS_DFU_DATA_BUF_SIZE + \ + CONFIG_SYS_DFU_MAX_FILE_SIZE) #else #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h index e51da3f4057..b1a14cbe73b 100644 --- a/include/configs/tegra-common-usb-gadget.h +++ b/include/configs/tegra-common-usb-gadget.h @@ -30,7 +30,8 @@ #define CONFIG_CMD_USB_MASS_STORAGE /* DFU protocol */ #define CONFIG_USB_FUNCTION_DFU -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M +#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M #define CONFIG_CMD_DFU #ifdef CONFIG_MMC #define CONFIG_DFU_MMC -- cgit v1.3.1 From 68295a48bf9d1939f91fe0b26c5afe8dd0f3dfa0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:50 -0600 Subject: ARM: tegra: enable filesystem writing Writing to files is a useful feature in general, so enable it everywhere. The primary purpose is to make DFU useful on filesystems in addition to raw devices. Signed-off-by: Stephen Warren --- include/configs/tegra-common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index b886c645076..1c469d092e8 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -140,6 +140,8 @@ #ifndef CONFIG_SPL_BUILD #include +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_FAT_WRITE #endif #endif /* _TEGRA_COMMON_H_ */ -- cgit v1.3.1 From aa46b408a5b3c9042e8383917f962e1c3a0ae2f2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:51 -0600 Subject: ARM: tegra: enable DFU for RAM This allows transferring data directly to/from RAM. For example, one could create a boot script that starts DFU on a RAM region, then once DFU exits (which is under the control of the attached USB host, via a USB bus reset), uses the code/data that was received over DFU. Signed-off-by: Stephen Warren --- include/configs/tegra-common-usb-gadget.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h index b1a14cbe73b..f6e1d5c4db2 100644 --- a/include/configs/tegra-common-usb-gadget.h +++ b/include/configs/tegra-common-usb-gadget.h @@ -39,6 +39,7 @@ #ifdef CONFIG_SPI_FLASH #define CONFIG_DFU_SF #endif +#define CONFIG_DFU_RAM #endif #endif /* _TEGRA_COMMON_USB_GADGET_H_ */ -- cgit v1.3.1 From 9d1b2987996907359548fb0e850f49cc37b768f1 Mon Sep 17 00:00:00 2001 From: Enric Balletbò i Serra Date: Mon, 7 Sep 2015 07:43:20 +0200 Subject: board: Add Toby-Churchill SL50 board support. Add support for Lightwriter SL50 series board, a small, robust and portable Voice Output Communication Aids (VOCA) designed to meet the particular and changing needs of people with speech loss resulting from a wide range of acquired, progressive and congenital conditions. Signed-off-by: Enric Balletbo i Serra --- arch/arm/Kconfig | 8 + board/tcl/sl50/Kconfig | 31 ++++ board/tcl/sl50/MAINTAINERS | 6 + board/tcl/sl50/Makefile | 13 ++ board/tcl/sl50/board.c | 386 ++++++++++++++++++++++++++++++++++++++++++ board/tcl/sl50/board.h | 22 +++ board/tcl/sl50/mux.c | 154 +++++++++++++++++ configs/am335x_sl50_defconfig | 10 ++ include/configs/am335x_sl50.h | 138 +++++++++++++++ 9 files changed, 768 insertions(+) create mode 100644 board/tcl/sl50/Kconfig create mode 100644 board/tcl/sl50/MAINTAINERS create mode 100644 board/tcl/sl50/Makefile create mode 100644 board/tcl/sl50/board.c create mode 100644 board/tcl/sl50/board.h create mode 100644 board/tcl/sl50/mux.c create mode 100644 configs/am335x_sl50_defconfig create mode 100644 include/configs/am335x_sl50.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9fd248f25a4..57c48d5bb76 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -363,6 +363,13 @@ config TARGET_AM335X_EVM select DM_SERIAL select DM_GPIO +config TARGET_AM335X_SL50 + bool "Support am335x_sl50" + select CPU_V7 + select SUPPORT_SPL + select DM + select DM_SERIAL + config TARGET_AM43XX_EVM bool "Support am43xx_evm" select CPU_V7 @@ -755,6 +762,7 @@ source "board/st/stm32f429-discovery/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/zmx25/Kconfig" +source "board/tcl/sl50/Kconfig" source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/birdland/bav335x/Kconfig" diff --git a/board/tcl/sl50/Kconfig b/board/tcl/sl50/Kconfig new file mode 100644 index 00000000000..390a47631ec --- /dev/null +++ b/board/tcl/sl50/Kconfig @@ -0,0 +1,31 @@ +if TARGET_AM335X_SL50 + +config SYS_BOARD + default "sl50" + +config SYS_VENDOR + default "tcl" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_sl50" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0 as for example the IDK + uses UART3 so enter 4 here. + +config DM_GPIO + default y + +config DM_SERIAL + default y + +endif diff --git a/board/tcl/sl50/MAINTAINERS b/board/tcl/sl50/MAINTAINERS new file mode 100644 index 00000000000..29f1e3d0508 --- /dev/null +++ b/board/tcl/sl50/MAINTAINERS @@ -0,0 +1,6 @@ +SL50 BOARD +M: Enric Balletbo i Serra +S: Maintained +F: board/tcl/sl50/ +F: include/configs/am335x_sl50.h +F: configs/am335x_sl50_defconfig diff --git a/board/tcl/sl50/Makefile b/board/tcl/sl50/Makefile new file mode 100644 index 00000000000..d4a548cd81e --- /dev/null +++ b/board/tcl/sl50/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c new file mode 100644 index 00000000000..e89ee35d306 --- /dev/null +++ b/board/tcl/sl50/board.c @@ -0,0 +1,386 @@ +/* + * board.c + * + * Board functions for TCL SL50 board + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +static const struct ddr_data ddr3_sl50_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_sl50_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_sl50_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr_sl50 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* BeagleBone PMIC Code */ + int usb_cur_lim; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* + * Set LDO3 to 1.8V and LDO4 to 3.3V + */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + return &dpll_ddr_sl50; +} + +void set_uart_mux_conf(void) +{ +#if CONFIG_CONS_INDEX == 1 + enable_uart0_pin_mux(); +#elif CONFIG_CONS_INDEX == 2 + enable_uart1_pin_mux(); +#elif CONFIG_CONS_INDEX == 3 + enable_uart2_pin_mux(); +#elif CONFIG_CONS_INDEX == 4 + enable_uart3_pin_mux(); +#elif CONFIG_CONS_INDEX == 5 + enable_uart4_pin_mux(); +#elif CONFIG_CONS_INDEX == 6 + enable_uart5_pin_mux(); +#endif +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_evm15 = { + .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(400, &ioregs_bonelt, + &ddr3_sl50_data, + &ddr3_sl50_cmd_ctrl_data, + &ddr3_sl50_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_MII; + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the first instance. + */ +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + +#endif +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("usbnet_devaddr", mac_addr); + + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); + else + n += rv; +#endif + return n; +} +#endif diff --git a/board/tcl/sl50/board.h b/board/tcl/sl50/board.h new file mode 100644 index 00000000000..ae2ef6bfd9f --- /dev/null +++ b/board/tcl/sl50/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * TCL SL50 boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c new file mode 100644 index 00000000000..e0d76ef695d --- /dev/null +++ b/board/tcl/sl50/mux.c @@ -0,0 +1,154 @@ +/* + * mux.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); +} diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig new file mode 100644 index 00000000000..0ddccc8a7d8 --- /dev/null +++ b/configs/am335x_sl50_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SL50=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" +CONFIG_CONS_INDEX=1 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h new file mode 100644 index 00000000000..f655e69f90f --- /dev/null +++ b/include/configs/am335x_sl50.h @@ -0,0 +1,138 @@ +/* + * am335x_sl50.h + * + * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM335X_EVM_H +#define __CONFIG_AM335X_EVM_H + +#include +#undef CONFIG_BOOTDELAY + +#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_FIT +# define CONFIG_FIT +#endif +# define CONFIG_TIMESTAMP +# define CONFIG_LZO +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD + +#include + +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#define AM335XX_BOARD_FDTFILE \ + "fdtfile=am335x-sl50.dtb\0" \ + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + AM335XX_BOARD_FDTFILE \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* Bootcount using the RTC block */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX +#define CONFIG_SYS_BOOTCOUNT_BE + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* Remove other SPL modes. */ +#undef CONFIG_SPL_YMODEM_SUPPORT +#undef CONFIG_SPL_NAND_SUPPORT +#undef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_NAND +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +#endif + +#if defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +#endif /* ! __CONFIG_AM335X_SL50_H */ -- cgit v1.3.1 From 40372244f206fcf94eadfcd1d063185373d5d25d Mon Sep 17 00:00:00 2001 From: Enric Balletbò i Serra Date: Mon, 7 Sep 2015 08:28:09 +0200 Subject: igep00x0: Switch to use the generic distro configuration and environment. This patch changes a little bit the environment, current environment was broken for a long time, and board don't as expected sometimes, on production systems this is fixed adding boot script. I think it's time to change this to make a system conformant environment and use generic distro configurations and environment instead. We can use a boot script for the old way boot mode. Signed-off-by: Enric Balletbo i Serra --- board/isee/igep00x0/igep00x0.c | 4 +- include/configs/omap3_igep00x0.h | 95 ++++++++++++---------------------------- 2 files changed, 30 insertions(+), 69 deletions(-) (limited to 'include') diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 693fce741a0..6eb191c5e03 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -153,10 +153,10 @@ void set_fdt(void) { switch (gd->bd->bi_arch_number) { case MACH_TYPE_IGEP0020: - setenv("dtbfile", "omap3-igep0020.dtb"); + setenv("fdtfile", "omap3-igep0020.dtb"); break; case MACH_TYPE_IGEP0030: - setenv("dtbfile", "omap3-igep0030.dtb"); + setenv("fdtfile", "omap3-igep0030.dtb"); break; } } diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 04433edcc54..4409103f491 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -19,6 +19,8 @@ #include #include +#undef CONFIG_BOOTDELAY + /* * Display CPU and Board information */ @@ -81,74 +83,33 @@ /*#undef CONFIG_ENV_IS_NOWHERE*/ +#ifndef CONFIG_SPL_BUILD + +#include + +/* Environment */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define MEM_LAYOUT_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "scriptaddr=0x87E00000\0" \ + "pxefile_addr_r=0x87F00000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include + + #define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ - "dtbaddr=0x81600000\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=auto\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=jffs2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr}\0" \ - "mmcbootfdt=echo Booting with DT from mmc ...; " \ - "bootz ${loadaddr} - ${dtbaddr}\0" \ - "nandboot=echo Booting from onenand ...; " \ - "run nandargs; " \ - "onenand read ${loadaddr} 280000 400000; " \ - "bootz ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadzimage; then " \ - "if test -n $dtbfile; then " \ - "if run loadfdt; then " \ - "run mmcbootfdt;" \ - "fi;" \ - "fi;" \ - "run mmcboot;" \ - "fi;" \ - "fi;" \ - "run nandboot;" \ + ENV_DEVICE_SETTINGS \ + MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* * FLASH and environment organization -- cgit v1.3.1 From 92a3188d7d836779915e3a6f9251fa07b9c753e4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 7 Sep 2015 13:43:52 +0200 Subject: bitops: introduce BIT() definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann Acked-by: Stefan Roese Acked-by: Anatolij Gustschin --- arch/arm/include/asm/arch-am33xx/cpu.h | 1 - arch/arm/include/asm/arch-hi6220/gpio.h | 2 -- arch/arm/include/asm/arch-omap5/cpu.h | 2 -- arch/arm/include/asm/arch-tegra/dc.h | 2 -- arch/arm/mach-davinci/cpu.c | 2 -- arch/arm/mach-keystone/include/mach/clock_defs.h | 2 -- arch/arm/mach-keystone/include/mach/hardware.h | 2 -- arch/arm/mach-mvebu/include/mach/soc.h | 2 -- arch/arm/mach-zynq/include/mach/gpio.h | 2 -- drivers/ddr/marvell/a38x/ddr3_init.h | 2 -- drivers/mtd/nand/jz4740_nand.c | 1 - drivers/spi/davinci_spi.c | 2 -- drivers/spi/ep93xx_spi.c | 2 -- drivers/video/anx9804.c | 2 -- include/fsl-mc/fsl_mc.h | 1 - include/linux/bitops.h | 2 ++ 16 files changed, 2 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 13a9cad2388..112ac5eacd9 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -17,7 +17,6 @@ #include -#define BIT(x) (1 << x) #define CL_BIT(x) (0 << x) /* Timer register bits */ diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h index 98122a2f707..4fafaef5d55 100644 --- a/arch/arm/include/asm/arch-hi6220/gpio.h +++ b/arch/arm/include/asm/arch-hi6220/gpio.h @@ -11,8 +11,6 @@ #define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \ 0xf7020000 - 0x4000) + (0x1000 * bank)) -#define BIT(x) (1 << (x)) - #define HI6220_GPIO_PER_BANK 8 #define HI6220_GPIO_DIR 0x400 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 6109b92777c..b1513e9aaf4 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -56,8 +56,6 @@ struct watchdog { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ -#define BIT(x) (1 << (x)) - #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 6ffb4683959..3a87f0b9566 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -364,8 +364,6 @@ struct dc_ctlr { struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ }; -#define BIT(pos) (1U << pos) - /* DC_CMD_DISPLAY_COMMAND 0x032 */ #define CTRL_MODE_SHIFT 5 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index ff611477572..74c3d5d936c 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV9 0x174 -#define BIT(x) (1 << (x)) - /* SOC-specific pll info */ #ifdef CONFIG_SOC_DM355 #define ARM_PLLDIV PLLC_PLLDIV1 diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h index 8ad371f43d2..f8d61d6ef1f 100644 --- a/arch/arm/mach-keystone/include/mach/clock_defs.h +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h @@ -11,8 +11,6 @@ #include -#define BIT(x) (1 << (x)) - /* PLL Control Registers */ struct pllctl_regs { u32 ctl; /* 00 */ diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 53f28ec8daf..f98a24eb573 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -24,8 +24,6 @@ typedef volatile unsigned int *dv_reg_p; #endif -#define BIT(x) (1 << (x)) - #define KS2_DDRPHY_PIR_OFFSET 0x04 #define KS2_DDRPHY_PGCR0_OFFSET 0x08 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index a8a6b27d802..02c21bcdedd 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -11,8 +11,6 @@ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H -#define BIT(x) (1 << (x)) - #define SOC_MV78460_ID 0x7846 #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h index 9e1e7da2037..0789c497368 100644 --- a/arch/arm/mach-zynq/include/mach/gpio.h +++ b/arch/arm/mach-zynq/include/mach/gpio.h @@ -71,6 +71,4 @@ /* GPIO upper 16 bit mask */ #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 -#define BIT(x) (1< #include -#define BIT(x) (1 << (x)) - /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 #define SPIGCR0_SPIRST_MASK 0x0 diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c index 235557ea3c5..cb682ddda48 100644 --- a/drivers/spi/ep93xx_spi.c +++ b/drivers/spi/ep93xx_spi.c @@ -16,8 +16,6 @@ #include - -#define BIT(x) (1<<(x)) #define SSPBASE SPI_BASE #define SSPCR0 0x0000 diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index 83d60d672dd..37ad69a039c 100755 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -14,8 +14,6 @@ #include #include "anx9804.h" -#define BIT(x) (1 << (x)) - /* Registers at i2c address 0x38 */ #define ANX9804_HDCP_CONTROL_0_REG 0x01 diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 9106f25f683..9517a4a7b5d 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -12,7 +12,6 @@ #define MC_CCSR_BASE_ADDR \ ((struct mc_ccsr_registers __iomem *)0x8340000) -#define BIT(x) (1 << (x)) #define GCR1_P1_STOP BIT(31) #define GCR1_P2_STOP BIT(30) #define GCR1_P1_DE_RST BIT(23) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index e7243102986..7d30ace41fc 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -3,6 +3,8 @@ #include +#define BIT(nr) (1UL << (nr)) + /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore -- cgit v1.3.1 From e093d0b2e874784b10f31196b74b3e7a99563d59 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Tue, 8 Sep 2015 09:50:00 +0300 Subject: omap3: cm-t3517: enable 'netretry' and setup timeout SBC-T3517 evaluation board has two Eth interfaces. Enable network retry of another interface if the default if failed or disconnected. Add 'netretry=yes' in the default env. Setup relevant timeout values in the board config file. Signed-off-by: Dmitry Lifshitz Acked-by: Igor Grinberg --- include/configs/cm_t3517.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 33b22a72b98..4c3dcfe495b 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -170,6 +170,7 @@ "loadaddr=0x82000000\0" \ "baudrate=115200\0" \ "console=ttyO2,115200n8\0" \ + "netretry=yes\0" \ "mpurate=auto\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ @@ -274,6 +275,8 @@ #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) +#define CONFIG_ARP_TIMEOUT 200UL +#define CONFIG_NET_RETRY_COUNT 5 #endif /* CONFIG_CMD_NET */ /* additions for new relocation code, must be added to all boards */ -- cgit v1.3.1 From 2f6e4bf8922146812041d1622d9caf962825996f Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 9 Sep 2015 11:25:39 +0300 Subject: omap3: cm-t3517: change environment size Mainline CM-T3517 U-Boot environment size differs from that one shipped with CM-T3517 boards. Update environment size, to avoid backward compatibility issues. Signed-off-by: Dmitry Lifshitz Acked-by: Igor Grinberg --- include/configs/cm_t3517.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 4c3dcfe495b..6bcba93956b 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -66,7 +66,7 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* -- cgit v1.3.1 From f3b44e8b2735a542cd962c74e8bc2dd50a87ab67 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 9 Sep 2015 11:27:17 +0300 Subject: omap3: cm-t3517: define CONFIG_MACH_TYPE Define CONFIG_MACH_TYPE to allow non DT Linux boot. Signed-off-by: Dmitry Lifshitz Acked-by: Igor Grinberg --- include/configs/cm_t3517.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 6bcba93956b..69332b647da 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -36,6 +36,8 @@ #include /* get chip and board defs */ #include +#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 + /* * Display CPU and Board information */ -- cgit v1.3.1 From 1368f99346b1a6c566095bcb1df662cdbdb129b3 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:13 -0500 Subject: thermal: imx_thermal: rework driver to be reused Rework imx_thermal driver to be used across i.MX processor that support thermal sensor Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx6/soc.c | 2 +- arch/arm/imx-common/cpu.c | 10 ++++------ drivers/thermal/Makefile | 2 +- drivers/thermal/imx_thermal.c | 18 +++++++++++------- include/configs/cgtqmx6eval.h | 4 ++-- include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/tbs2910.h | 2 +- 13 files changed, 27 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8ad8da84650..51101127663 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -38,7 +38,7 @@ struct scu_regs { u32 fpga_rev; }; -#if defined(CONFIG_IMX6_THERMAL) +#if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx6_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, .fuse_bank = 1, diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index e27546c906d..38cd0c82807 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -154,14 +154,12 @@ int print_cpuinfo(void) u32 cpurev; __maybe_unused u32 max_freq; -#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) + cpurev = get_cpu_rev(); + +#if defined(CONFIG_IMX_THERMAL) struct udevice *thermal_dev; int cpu_tmp, minc, maxc, ret; -#endif - cpurev = get_cpu_rev(); - -#if defined(CONFIG_MX6) printf("CPU: Freescale i.MX%s rev%d.%d", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, @@ -181,7 +179,7 @@ int print_cpuinfo(void) mxc_get_clock(MXC_ARM_CLK) / 1000000); #endif -#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) +#if defined(CONFIG_IMX_THERMAL) puts("CPU: "); switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_AUTOMOTIVE: diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 6d4cacdcf7f..d768f5ef808 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -6,4 +6,4 @@ # obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o -obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o +obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 3c6c9679f97..d90874e5ec7 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -41,7 +41,7 @@ struct thermal_data { int maxc; }; -static int read_cpu_temperature(struct udevice *dev) +static int read_cpu_temperature_mx6(struct udevice *dev) { int temperature; unsigned int reg, n_meas; @@ -129,13 +129,15 @@ int imx_thermal_get_temp(struct udevice *dev, int *temp) struct thermal_data *priv = dev_get_priv(dev); int cpu_tmp = 0; - cpu_tmp = read_cpu_temperature(dev); + if (is_soc_type(MXC_SOC_MX6)) + cpu_tmp = read_cpu_temperature_mx6(dev); while (cpu_tmp >= priv->critical) { printf("CPU Temperature (%dC) too close to max (%dC)", cpu_tmp, priv->maxc); puts(" waiting...\n"); udelay(5000000); - cpu_tmp = read_cpu_temperature(dev); + if (is_soc_type(MXC_SOC_MX6)) + cpu_tmp = read_cpu_temperature_mx6(dev); } *temp = cpu_tmp; @@ -157,10 +159,12 @@ static int imx_thermal_probe(struct udevice *dev) /* Read Temperature calibration data fuse */ fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse); - /* Check for valid fuse */ - if (fuse == 0 || fuse == ~0) { - printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); - return -EPERM; + if (is_soc_type(MXC_SOC_MX6)) { + /* Check for valid fuse */ + if (fuse == 0 || fuse == ~0) { + printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); + return -EPERM; + } } /* set critical cooling temp */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 92930c8f725..55a06643dc4 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -33,10 +33,10 @@ #define CONFIG_CMD_BMODE /* Thermal support */ -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_CMD_FUSE -#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX_THERMAL) #define CONFIG_MXC_OCOTP #endif diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 12744a61432..58cee96ac31 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -19,7 +19,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 8b9d9228769..231bea7855c 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -57,7 +57,7 @@ #define CONFIG_CMD_GPIO /* Thermal */ -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Serial */ #define CONFIG_MXC_UART diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 634a09f3492..6e89dd1455f 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,7 +14,7 @@ #define CONFIG_SPL_MMC_SUPPORT #include "imx6_spl.h" -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6a57841f5fe..98eb0427aa5 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -11,7 +11,7 @@ #include "mx6_common.h" -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 04d53a7f08e..0a641c2daa5 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -197,6 +197,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 74d04a088f3..f30c1482ec3 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -177,7 +177,7 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #define CONFIG_CMD_TIME diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 4a2280bc184..d8a4f161223 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -241,6 +241,6 @@ #define CONFIG_FEC_DMA_MINALIGN 64 #endif -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 66cb274f68a..70b440340ff 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -20,7 +20,7 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_IMX6_THERMAL +#define CONFIG_IMX_THERMAL /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -- cgit v1.3.1 From 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Thu, 3 Sep 2015 11:49:28 -0500 Subject: imx: mx7dsabresd: Add support for MX7D SABRESD board * Add i.MX7D SABRESD target board support with enabled modules: UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX. Build target: mx7dsabresd_config Signed-off-by: Peng Fan Signed-off-by: Fugang Duan Signed-off-by: Ye.Li Signed-off-by: Adrian Alonso --- arch/arm/Kconfig | 6 + arch/arm/cpu/armv7/mx7/Kconfig | 27 ++ arch/arm/include/asm/arch-mx7/sys_proto.h | 2 + board/freescale/mx7dsabresd/Kconfig | 15 + board/freescale/mx7dsabresd/MAINTAINERS | 6 + board/freescale/mx7dsabresd/Makefile | 6 + board/freescale/mx7dsabresd/imximage.cfg | 94 +++++ board/freescale/mx7dsabresd/mx7dsabresd.c | 555 ++++++++++++++++++++++++++++++ configs/mx7dsabresd_defconfig | 14 + include/configs/mx7_common.h | 95 +++++ include/configs/mx7dsabresd.h | 194 +++++++++++ 11 files changed, 1014 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx7/Kconfig create mode 100644 board/freescale/mx7dsabresd/Kconfig create mode 100644 board/freescale/mx7dsabresd/MAINTAINERS create mode 100644 board/freescale/mx7dsabresd/Makefile create mode 100644 board/freescale/mx7dsabresd/imximage.cfg create mode 100644 board/freescale/mx7dsabresd/mx7dsabresd.c create mode 100644 configs/mx7dsabresd_defconfig create mode 100644 include/configs/mx7_common.h create mode 100644 include/configs/mx7dsabresd.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 57c48d5bb76..c4371c71733 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -442,6 +442,10 @@ config ARCH_KEYSTONE select CPU_V7 select SUPPORT_SPL +config ARCH_MX7 + bool "Freescale MX7" + select CPU_V7 + config ARCH_MX6 bool "Freescale MX6" select CPU_V7 @@ -665,6 +669,8 @@ source "arch/arm/mach-keystone/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/cpu/armv7/mx7/Kconfig" + source "arch/arm/cpu/armv7/mx6/Kconfig" source "arch/arm/cpu/armv7/mx5/Kconfig" diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig new file mode 100644 index 00000000000..892ffae3095 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -0,0 +1,27 @@ +if ARCH_MX7 + +config MX7 + bool + default y + +config MX7D + bool + +choice + prompt "MX7 board select" + optional + +config TARGET_MX7DSABRESD + bool "mx7dsabresd" + select CPU_V7 + select DM + select DM_THERMAL + +endchoice + +config SYS_SOC + default "mx7" + +source "board/freescale/mx7dsabresd/Kconfig" + +endif diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h index f19684b0248..ca7608bd56b 100644 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -5,3 +5,5 @@ */ #include + +void set_wdog_reset(struct wdog_regs *wdog); diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig new file mode 100644 index 00000000000..d7c6ae41fd0 --- /dev/null +++ b/board/freescale/mx7dsabresd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX7DSABRESD + +config SYS_BOARD + default "mx7dsabresd" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "mx7dsabresd" + +endif diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS new file mode 100644 index 00000000000..3910ee45248 --- /dev/null +++ b/board/freescale/mx7dsabresd/MAINTAINERS @@ -0,0 +1,6 @@ +MX7DSABRESD BOARD +M: Adrian Alonso +S: Maintained +F: board/freescale/mx7dsabresd +F: include/configs/mx7dsabresd.h +F: configs/mx7dsabresd_defconfig diff --git a/board/freescale/mx7dsabresd/Makefile b/board/freescale/mx7dsabresd/Makefile new file mode 100644 index 00000000000..14336ab8546 --- /dev/null +++ b/board/freescale/mx7dsabresd/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7dsabresd.o diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg new file mode 100644 index 00000000000..91b70ee4c81 --- /dev/null +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : sd + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00171717 +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000d6e +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c new file mode 100644 index 00000000000..d163bee20f7 --- /dev/null +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -0,0 +1,555 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, + .gp = IMX_GPIO_NR(4, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, + .gp = IMX_GPIO_NR(4, 9), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define IOX_SDI IMX_GPIO_NR(1, 9) +#define IOX_STCP IMX_GPIO_NR(1, 12) +#define IOX_SHCP IMX_GPIO_NR(1, 13) + +static iomux_v3_cfg_t const iox_pads[] = { + /* IOX_SDI */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_STCP */ + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_SHCP */ + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * PCIE_DIS_B --> Q0 + * PCIE_RST_B --> Q1 + * HDMI_RST_B --> Q2 + * PERI_RST_B --> Q3 + * SENSOR_RST_B --> Q4 + * ENET_RST_B --> Q5 + * PERI_3V3_EN --> Q6 + * LCD_PWR_EN --> Q7 + */ +enum qn { + PCIE_DIS_B, + PCIE_RST_B, + HDMI_RST_B, + PERI_RST_B, + SENSOR_RST_B, + ENET_RST_B, + PERI_3V3_EN, + LCD_PWR_EN, +}; + +enum qn_func { + qn_reset, + qn_enable, + qn_disable, +}; + +enum qn_level { + qn_low = 0, + qn_high = 1, +}; + +static enum qn_level seq[3][2] = { + {0, 1}, {1, 1}, {0, 0} +}; + +static enum qn_func qn_output[8] = { + qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, + qn_enable +}; + +void iox74lv_init(void) +{ + int i; + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); +}; + +void iox74lv_set(int index) +{ + int i; + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + + if (i == index) + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + else + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +static int mmc_get_env_devno(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + u8 boot_type = (*p)->boot_dev_type; + u8 dev_no = (*p)->boot_dev_instance; + + /* If not boot from sd/mmc, use default value */ + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) + return CONFIG_SYS_MMC_ENV_DEV; + + if (dev_no == 2) + dev_no--; + + return dev_no; +} + +static int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 1) + dev_no++; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc2 USDHC3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); + gpio_direction_output(USDHC3_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + return set_clk_enet(ENET_125MHz); +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); + + iox74lv_init(); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: i.MX7D SABRESD\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX7 +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} +#endif diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig new file mode 100644 index 00000000000..bb954244829 --- /dev/null +++ b/configs/mx7dsabresd_defconfig @@ -0,0 +1,14 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D" +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h new file mode 100644 index 00000000000..ea2be496e05 --- /dev/null +++ b/include/configs/mx7_common.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7_COMMON_H +#define __MX7_COMMON_H + +#include +#include +#include + +#ifndef CONFIG_MX7 +#define CONFIG_MX7 +#endif + +/* Timer settings */ +#define CONFIG_MXC_GPT_HCLK +#define CONFIG_SYSCOUNTER_TIMER +#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ + +/* Enable iomux-lpsr support */ +#define CONFIG_IOMUX_LPSR +#define CONFIG_IMX_FIXED_IVT_OFFSET + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_ROM_UNIFIED_SECTIONS +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#ifndef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 3 +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Filesystems and image support */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT + +/* Miscellaneous configurable options */ +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* GPIO */ +#define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +#endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h new file mode 100644 index 00000000000..ec6e0a6d6bf --- /dev/null +++ b/include/configs/mx7dsabresd.h @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D SABRESD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_SABRESD_CONFIG_H +#define __MX7D_SABRESD_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_DBG_MONITOR +#define PHYS_SDRAM_SIZE SZ_1G + +/* Network */ +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_BROADCOM +#define CONFIG_FEC_DMA_MINALIGN 64 +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +/* I2C configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7d-sdb.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define CONFIG_CMD_BMODE + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX7 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From bd8366763c25c94dbf9429a3b5c88ce0ea78b4fa Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 1 Sep 2015 11:03:15 +0800 Subject: imx: discard duplicated MXC_OCOTP and CMD_FUSE We have CONFIG_MXC_OCOTP and CONFIG_CMD_FUSE in mx6_common.h, discard duplicated macro definitions in board header files. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Peter Robinson Cc: Otavio Salvador --- include/configs/mx6ul_14x14_evk.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index d8a4f161223..670b1c26a9b 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -34,11 +34,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CMD_FUSE -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -- cgit v1.3.1 From d9cbb264e8c277af0ae8c55bac01b8564dfc3f9c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 6 Sep 2015 15:02:34 +0800 Subject: imx: mx6ul: support mx6ul 9x9 evk board This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk, the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are: 1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC. 2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk supports 512MB DDR3 3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package. This patch add the following: 1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size() 2. Introduce a macro is_mx6ul_9x9_evk using CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work, so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with mx6ul_14x14_evk. And we have no way to dymaically checking this chip is 9x9 or 14x14. 3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations. POWER related configurations also effect for mx6ul_14x14_evk. But power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk. 4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM configurations. 5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file according to board_rev and board_name. 6. Add TARGET_MX6UL_9X9_EVK Kconfig entry Boot Log: U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53) reading u-boot.img reading u-boot.img U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 41C Reset cause: POR Board: MX6UL 9x9 EVK I2C: ready DRAM: 256 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: FEC1 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/Kconfig | 8 + board/freescale/mx6ul_14x14_evk/Kconfig | 2 +- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 183 ++++++++++++++++++---- configs/mx6ul_9x9_evk_defconfig | 8 + include/configs/mx6ul_14x14_evk.h | 26 ++- 5 files changed, 190 insertions(+), 37 deletions(-) create mode 100644 configs/mx6ul_9x9_evk_defconfig (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 8b0120fea50..b3f7eaf4f6c 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -104,6 +104,14 @@ config TARGET_MX6SXSABRESD select DM select DM_THERMAL +config TARGET_MX6UL_9X9_EVK + bool "mx6ul_9x9_evk" + select MX6UL + select CPU_V7 + select DM + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6UL_14X14_EVK bool "mx6ul_14x14_evk" select MX6UL diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig index 393aca629bc..eda02c9f78f 100644 --- a/board/freescale/mx6ul_14x14_evk/Kconfig +++ b/board/freescale/mx6ul_14x14_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6UL_14X14_EVK +if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK config SYS_BOARD default "mx6ul_14x14_evk" diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index c09d84e5405..612fb788340 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -23,6 +23,9 @@ #include #include #include +#include +#include +#include "../common/pfuze.h" #include #include @@ -210,11 +213,56 @@ struct i2c_pads_info i2c_pad_info1 = { .gp = IMX_GPIO_NR(1, 29), }, }; + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + if (is_mx6ul_9x9_evk()) { + struct pmic *pfuze; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", + reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); + + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); + + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); + } + + return 0; +} +#endif #endif int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + gd->ram_size = imx_ddr_size(); return 0; } @@ -614,6 +662,15 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "EVK"); + + if (is_mx6ul_9x9_evk()) + setenv("board_rev", "9X9"); + else + setenv("board_rev", "14X14"); +#endif + return 0; } @@ -624,7 +681,10 @@ u32 get_board_rev(void) int checkboard(void) { - puts("Board: MX6UL 14x14 EVK\n"); + if (is_mx6ul_9x9_evk()) + puts("Board: MX6UL 9x9 EVK\n"); + else + puts("Board: MX6UL 14x14 EVK\n"); return 0; } @@ -634,7 +694,76 @@ int checkboard(void) #include #include -const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK + .grp_ddr_type = 0x00080000, +#else + .grp_ddr_type = 0x000c0000, +#endif +}; + +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000000, + .dram_odt1 = 0x00000000, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00003030, + .dram_sdqs1 = 0x00003030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x20000000, + .p0_mprddlctl = 0x4040484f, + .p0_mpwrdlctl = 0x40405247, + .mpzqlp2ctl = 0x1b4700c7, +}; + +static struct mx6_lpddr2_cfg mem_ddr = { + .mem_speed = 800, + .density = 2, + .width = 16, + .banks = 4, + .rowaddr = 14, + .coladdr = 10, + .trcd_lp = 1500, + .trppb_lp = 1500, + .trpab_lp = 2000, + .trasmin = 4250, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 18, + .ncs = 1, + .cs1_mirror = 0, + .walat = 0, + .ralat = 5, + .mif3_mode = 3, + .bi_on = 1, + .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ + .rtt_nom = 0, + .sde_to_rst = 0, /* LPDDR2 does not need this field */ + .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ + .ddr_type = DDR_TYPE_LPDDR2, +}; + +#else +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { .dram_dqm0 = 0x00000030, .dram_dqm1 = 0x00000030, .dram_ras = 0x00000030, @@ -648,24 +777,29 @@ const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { .dram_reset = 0x00000030, }; -const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { +static struct mx6_mmdc_calibration mx6_mmcd_calib = { .p0_mpwldectrl0 = 0x00070007, .p0_mpdgctrl0 = 0x41490145, .p0_mprddlctl = 0x40404546, .p0_mpwrdlctl = 0x4040524D, }; +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + static struct mx6_ddr3_cfg mem_ddr = { .mem_speed = 800, .density = 4, @@ -678,6 +812,7 @@ static struct mx6_ddr3_cfg mem_ddr = { .trcmin = 4875, .trasmin = 3500, }; +#endif static void ccgr_init(void) { @@ -695,24 +830,8 @@ static void ccgr_init(void) static void spl_dram_init(void) { - struct mx6_ddr_sysinfo sysinfo = { - .dsize = 0, - .cs_density = 20, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - }; - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); } void board_init_f(ulong dummy) diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig new file mode 100644 index 00000000000..e54609d83af --- /dev/null +++ b/configs/mx6ul_9x9_evk_defconfig @@ -0,0 +1,8 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_SPL=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 670b1c26a9b..a5c13f78362 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -14,12 +14,16 @@ #include "mx6_common.h" #include +#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) + /* SPL options */ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_ROM_UNIFIED_SECTIONS #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO @@ -61,9 +65,13 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 -#endif -#define PHYS_SDRAM_SIZE SZ_512M +/* PMIC only for 9X9 EVK */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif #undef CONFIG_CMD_IMLS @@ -75,7 +83,7 @@ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6ul-14x14-evk.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -129,9 +137,19 @@ "fi; " \ "else " \ "bootz; " \ - "fi;\0" + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ -- cgit v1.3.1 From 4189947de4a8ed50772981c860b7d43b4e04ea97 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 Sep 2015 14:43:11 -0300 Subject: mx6ul_14x14_evk: Remove CONFIG_SPL_FAT_SUPPORT If the SD card does not contain the u-boot.img then we get the following error: U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29) ** Partition 1 not valid on device 0 ** spl_register_fat_device: fat register err - -1 spl_load_image_fat: error reading image u-boot.img, err - -1 Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the job. Signed-off-by: Fabio Estevam --- include/configs/mx6ul_14x14_evk.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index a5c13f78362..b4369807009 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -19,7 +19,6 @@ /* SPL options */ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -- cgit v1.3.1 From 016a5bb7c78720e1bf1defd5fd72c44f4335064a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 Sep 2015 14:50:23 -0300 Subject: mx6slevk: Remove CONFIG_SPL_FAT_SUPPORT If the SD card does not contain the u-boot.img then we get the following error: U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29) ** Partition 1 not valid on device 0 ** spl_register_fat_device: fat register err - -1 spl_load_image_fat: error reading image u-boot.img, err - -1 Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the job. Signed-off-by: Fabio Estevam --- include/configs/mx6slevk.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 0a641c2daa5..51b297a1a35 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -14,7 +14,6 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif -- cgit v1.3.1 From bfa593f307eceeaa8ed67f119538d288dc47f68b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 Sep 2015 14:50:24 -0300 Subject: mx6sxsabresd: Remove CONFIG_SPL_FAT_SUPPORT If the SD card does not contain the u-boot.img then we get the following error: U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29) ** Partition 1 not valid on device 0 ** spl_register_fat_device: fat register err - -1 spl_load_image_fat: error reading image u-boot.img, err - -1 Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the job. Signed-off-by: Fabio Estevam --- include/configs/mx6sxsabresd.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index f30c1482ec3..381eaa24d53 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -15,7 +15,6 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif -- cgit v1.3.1 From 2181d331bf548c57fe5c0dfbb32ef8913aa217f6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 9 Sep 2015 11:16:39 -0300 Subject: cgtqmx6eval: Remove CONFIG_CMD_FUSE option CONFIG_CMD_FUSE and CONFIG_MXC_OCOTP are selected by mx6_common.h, so there is no need to define them locally. Signed-off-by: Fabio Estevam --- include/configs/cgtqmx6eval.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 55a06643dc4..c7d54ee2492 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -35,11 +35,6 @@ /* Thermal support */ #define CONFIG_IMX_THERMAL -#define CONFIG_CMD_FUSE -#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX_THERMAL) -#define CONFIG_MXC_OCOTP -#endif - /* I2C Configs */ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C -- cgit v1.3.1 From b1ee2d25227d383a52cb2134165f3033c5f1ce12 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 9 Sep 2015 11:16:40 -0300 Subject: mx6ul_14x14_evk: Remove CONFIG_SYS_GENERIC_BOARD CONFIG_SYS_GENERIC_BOARD is selected by mx6_common.h, so there is no need to define it locally. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- include/configs/mx6ul_14x14_evk.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index b4369807009..34ce9bf1ed6 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -24,7 +24,6 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_ROM_UNIFIED_SECTIONS -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.3.1 From b398ed58df92728f6b2e33082af0493877b2b350 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 9 Sep 2015 11:16:41 -0300 Subject: mx6ul_14x14_evk: Remove unused config option CONFIG_ROM_UNIFIED_SECTIONS is not used anywhere, so let's remove it. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- include/configs/mx6ul_14x14_evk.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 34ce9bf1ed6..49cdc289a3e 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -23,7 +23,6 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_ROM_UNIFIED_SECTIONS #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.3.1 From ba35a4fd121b5c591626f26bdbf41ea515713aff Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 9 Sep 2015 11:16:42 -0300 Subject: mx6ul_14x14_evk: Do not undef config options There is no need to undef the config options. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- include/configs/mx6ul_14x14_evk.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 49cdc289a3e..467dc8a8f88 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -49,13 +49,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #endif -#undef CONFIG_BOOTM_NETBSD -#undef CONFIG_BOOTM_PLAN9 -#undef CONFIG_BOOTM_RTEMS - -#undef CONFIG_CMD_EXPORTENV -#undef CONFIG_CMD_IMPORTENV - /* I2C configs */ #define CONFIG_CMD_I2C #ifdef CONFIG_CMD_I2C @@ -70,8 +63,6 @@ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #endif -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.3.1 From a29539c261a6afc7ff956c8626bea545f3b0f2a0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 9 Sep 2015 11:16:43 -0300 Subject: mx6ul_14x14_evk: Remove CONFIG_FEC_DMA_MINALIGN CONFIG_FEC_DMA_MINALIGN is not used anywhere, so let's remove it. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- include/configs/mx6ul_14x14_evk.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 467dc8a8f88..39cacf8541c 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -239,7 +239,6 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL -#define CONFIG_FEC_DMA_MINALIGN 64 #endif #define CONFIG_IMX_THERMAL -- cgit v1.3.1 From 10b347fc34aa8c5382f49126c3ce5c4e7f064d2e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 9 Sep 2015 11:16:44 -0300 Subject: mx6ul_14x14_evk: Use the default CONFIG_SYS_PBSIZE Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Fabio Estevam --- include/configs/mx6ul_14x14_evk.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 39cacf8541c..465ddee8817 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -151,9 +151,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) -- cgit v1.3.1 From 6083aec1db1ac29f486641eee3d162a337cc4a01 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 1 Sep 2015 19:01:02 +0200 Subject: ARM: Kirkwood: enable generic board support for LaCie boards This patch enables generic board support for the following Kirkwood-based LaCie boards: - Network Space v2 (Mini, Lite and Max). - Internet Space v2. - D2 Network v2. - 2Big Network v2. Signed-off-by: Simon Guinot Reviewed-by: Simon Glass Tested-by: Simon Glass --- include/configs/lacie_kw.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 30810d37529..7f63ae0d222 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -7,6 +7,11 @@ #ifndef _CONFIG_LACIE_KW_H #define _CONFIG_LACIE_KW_H +/* + * Generic board support + */ +#define CONFIG_SYS_GENERIC_BOARD + /* * Machine number definition */ -- cgit v1.3.1 From 278bd4e7d71e4e54677b36106615c02b87b69bd6 Mon Sep 17 00:00:00 2001 From: Sergey Kostanbaev Date: Thu, 10 Sep 2015 01:40:01 +0300 Subject: arm: move edb93xx to generic board architecture Use CONFIG_SYS_GENERIC_BOARD in EDB93XX board family --- include/configs/edb93xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index efe2a9daa7c..e3e32aa0814 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -25,6 +25,8 @@ #error "no board defined" #endif +#define CONFIG_SYS_GENERIC_BOARD + /* Initial environment and monitor configuration options. */ #define CONFIG_BOOTDELAY 2 #define CONFIG_CMDLINE_TAG 1 -- cgit v1.3.1 From 4c669e2d3b0d65aeb5593c04b719284a41013c87 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Thu, 3 Sep 2015 11:12:20 +0200 Subject: ARM: Kirkwood: fix IDE configuration on LaCie boards On the LaCie boards netspace_max_v2 and net2big_v2, two internal hard drives are available. Additionally on the d2net_v2 board, an extra hard drive can be plugged via eSATA. This patch updates CONFIG_SYS_IDE_MAXBUS and CONFIG_SYS_IDE_MAXDEVICE accordingly for this boards. Signed-off-by: Simon Guinot --- include/configs/lacie_kw.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 7f63ae0d222..7f878b713af 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -101,8 +101,6 @@ #undef CONFIG_SYS_IDE_MAXDEVICE #undef CONFIG_SYS_PROMPT #define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 #if defined(CONFIG_D2NET_V2) #define CONFIG_SYS_PROMPT "d2v2> " #elif defined(CONFIG_NET2BIG_V2) @@ -132,6 +130,11 @@ #if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#else +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 #endif #endif /* CONFIG_MVSATA_IDE */ -- cgit v1.3.1 From 02464e386bb5f0a022c121f95ae75cf583759d95 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 6 Aug 2015 15:31:02 -0600 Subject: fdt: add new fdt address parsing functions fdtdec_get_addr_size() hard-codes the number of cells used to represent an address or size in DT. This is incorrect in many cases depending on the DT binding for a particular node or property (e.g. it is incorrect for the "reg" property). In most cases, DT parsing code must use the properties #address-cells and #size-cells to parse addres properties. This change splits up the implementation of fdtdec_get_addr_size() so that the core logic can be used for both hard-coded and non-hard-coded cases. Various wrapper functions are implemented that support cases where hard-coded cell counts should or should not be used, and where the client does and doesn't know the parent node ID that contains the properties #address-cells and #size-cells. dev_get_addr() is updated to use the new functions. Core functionality in fdtdec_get_addr_size_fixed() is widely tested via fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and dev_get_addr() by manually modifying the Tegra I2C driver to invoke them. Much of the core implementation of fdtdec_get_addr_size_fixed(), fdtdec_get_addr_size_auto_parent(), and fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit". Based-on-work-by: Thierry Reding Cc: Thierry Reding Cc: Simon Glass Cc: Michal Suchanek Signed-off-by: Stephen Warren Acked-by: Simon Glass Dropped #define DEBUG at the top of fdtdec.c: Signed-off-by: Simon Glass --- drivers/core/device.c | 5 ++- include/fdtdec.h | 111 ++++++++++++++++++++++++++++++++++++++++++++---- lib/fdtdec.c | 114 ++++++++++++++++++++++++++++++++++++++++---------- 3 files changed, 200 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/drivers/core/device.c b/drivers/core/device.c index 0ccd443f252..0bc04d4876d 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -581,7 +581,10 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr; - addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + dev->parent->of_offset, + dev->of_offset, "reg", + 0, NULL); if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) addr = simple_bus_translate(dev->parent, addr); diff --git a/include/fdtdec.h b/include/fdtdec.h index a422ecedb84..2de6dda04c5 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -295,10 +295,90 @@ int fdtdec_next_compatible(const void *blob, int node, int fdtdec_next_compatible_subnode(const void *blob, int node, enum fdt_compat_id id, int *depthp); -/** - * Look up an address property in a node and return it as an address. - * The property must hold either one address with no trailing data or - * one address with a length. This is only tested on 32-bit machines. +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant assumes a known and fixed number of cells are used to + * represent the address and size. + * + * You probably don't want to use this function directly except to parse + * non-standard properties, and never to parse the "reg" property. Instead, + * use one of the "auto" variants below, which automatically honor the + * #address-cells and #size-cells properties in the parent node. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param na the number of cells used to represent an address + * @param ns the number of cells used to represent a size + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, + const char *prop_name, int index, int na, int ns, + fdt_size_t *sizep); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant automatically determines the number of cells used to represent + * the address and size by parsing the provided parent node's #address-cells + * and #size-cells properties. + * + * @param blob FDT blob + * @param parent parent node of @node + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, + int node, const char *prop_name, int index, fdt_size_t *sizep); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant automatically determines the number of cells used to represent + * the address and size by parsing the parent node's #address-cells + * and #size-cells properties. The parent node is automatically found. + * + * The automatic parent lookup implemented by this function is slow. + * Consequently, fdtdec_get_addr_size_auto_parent() should be used where + * possible. + * + * @param blob FDT blob + * @param parent parent node of @node + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, + const char *prop_name, int index, fdt_size_t *sizep); + +/* + * Look up an address property in a node and return the parsed address. + * + * This variant hard-codes the number of cells used to represent the address + * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also + * always returns the first address value in the property (index 0). + * + * Use of this function is not recommended due to the hard-coding of cell + * counts. There is no programmatic validation that these hard-coded values + * actually match the device tree content in any way at all. This assumption + * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately + * set in the U-Boot build and exercising strict control over DT content to + * ensure use of matching #address-cells/#size-cells properties. However, this + * approach is error-prone; those familiar with DT will not expect the + * assumption to exist, and could easily invalidate it. If the assumption is + * invalidated, this function will not report the issue, and debugging will + * be required. Instead, use fdtdec_get_addr_size_auto_parent(). * * @param blob FDT blob * @param node node to examine @@ -308,14 +388,29 @@ int fdtdec_next_compatible_subnode(const void *blob, int node, fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name); -/** - * Look up an address property in a node and return it as an address. - * The property must hold one address with a length. This is only tested - * on 32-bit machines. +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant hard-codes the number of cells used to represent the address + * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also + * always returns the first address value in the property (index 0). + * + * Use of this function is not recommended due to the hard-coding of cell + * counts. There is no programmatic validation that these hard-coded values + * actually match the device tree content in any way at all. This assumption + * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately + * set in the U-Boot build and exercising strict control over DT content to + * ensure use of matching #address-cells/#size-cells properties. However, this + * approach is error-prone; those familiar with DT will not expect the + * assumption to exist, and could easily invalidate it. If the assumption is + * invalidated, this function will not report the issue, and debugging will + * be required. Instead, use fdtdec_get_addr_size_auto_parent(). * * @param blob FDT blob * @param node node to examine * @param prop_name name of property to find + * @param sizep a pointer to store the size into. Use NULL if not required * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5770094fbfa..9f0b65de383 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -86,32 +86,104 @@ const char *fdtdec_get_compatible(enum fdt_compat_id id) return compat_names[id]; } -fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, - const char *prop_name, fdt_size_t *sizep) +fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, + const char *prop_name, int index, int na, int ns, + fdt_size_t *sizep) { - const fdt_addr_t *cell; + const fdt32_t *prop, *prop_end; + const fdt32_t *prop_addr, *prop_size, *prop_after_size; int len; + fdt_addr_t addr; debug("%s: %s: ", __func__, prop_name); - cell = fdt_getprop(blob, node, prop_name, &len); - if (cell && ((!sizep && len == sizeof(fdt_addr_t)) || - len == sizeof(fdt_addr_t) * 2)) { - fdt_addr_t addr = fdt_addr_to_cpu(*cell); - if (sizep) { - const fdt_size_t *size; - - size = (fdt_size_t *)((char *)cell + - sizeof(fdt_addr_t)); - *sizep = fdt_size_to_cpu(*size); - debug("addr=%08lx, size=%llx\n", - (ulong)addr, (u64)*sizep); - } else { - debug("%08lx\n", (ulong)addr); - } - return addr; + + if (na > (sizeof(fdt_addr_t) / sizeof(fdt32_t))) { + debug("(na too large for fdt_addr_t type)\n"); + return FDT_ADDR_T_NONE; } - debug("(not found)\n"); - return FDT_ADDR_T_NONE; + + if (ns > (sizeof(fdt_size_t) / sizeof(fdt32_t))) { + debug("(ns too large for fdt_size_t type)\n"); + return FDT_ADDR_T_NONE; + } + + prop = fdt_getprop(blob, node, prop_name, &len); + if (!prop) { + debug("(not found)\n"); + return FDT_ADDR_T_NONE; + } + prop_end = prop + (len / sizeof(*prop)); + + prop_addr = prop + (index * (na + ns)); + prop_size = prop_addr + na; + prop_after_size = prop_size + ns; + if (prop_after_size > prop_end) { + debug("(not enough data: expected >= %d cells, got %d cells)\n", + (u32)(prop_after_size - prop), ((u32)(prop_end - prop))); + return FDT_ADDR_T_NONE; + } + + addr = fdtdec_get_number(prop_addr, na); + + if (sizep) { + *sizep = fdtdec_get_number(prop_size, ns); + debug("addr=%08llx, size=%llx\n", (u64)addr, (u64)*sizep); + } else { + debug("addr=%08llx\n", (u64)addr); + } + + return addr; +} + +fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, + int node, const char *prop_name, int index, fdt_size_t *sizep) +{ + int na, ns; + + debug("%s: ", __func__); + + na = fdt_address_cells(blob, parent); + if (na < 1) { + debug("(bad #address-cells)\n"); + return FDT_ADDR_T_NONE; + } + + ns = fdt_size_cells(blob, parent); + if (ns < 1) { + debug("(bad #size-cells)\n"); + return FDT_ADDR_T_NONE; + } + + debug("na=%d, ns=%d, ", na, ns); + + return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na, + ns, sizep); +} + +fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, + const char *prop_name, int index, fdt_size_t *sizep) +{ + int parent; + + debug("%s: ", __func__); + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("(no parent found)\n"); + return FDT_ADDR_T_NONE; + } + + return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name, + index, sizep); +} + +fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, + const char *prop_name, fdt_size_t *sizep) +{ + return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0, + sizeof(fdt_addr_t) / sizeof(fdt32_t), + sizeof(fdt_size_t) / sizeof(fdt32_t), + sizep); } fdt_addr_t fdtdec_get_addr(const void *blob, int node, -- cgit v1.3.1 From 46e950a786238ecc08d803f2040a84a2d2361b76 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Sep 2015 14:54:02 -0400 Subject: omap3_evm_common.h: Switch to SYS_GENERIC_BOARD Tested on my OMAP3 uEVM. Signed-off-by: Tom Rini Reviewed-by: Simon Glass Tested-by: Simon Glass --- include/configs/omap3_evm_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7e7f6f2e9f4..0ebe5c118bc 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -15,6 +15,7 @@ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 -- cgit v1.3.1 From aeca15dcb32511fa7754a829501e87c671673722 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Sep 2015 14:54:03 -0400 Subject: ti814x_evm: Switch to SYS_GENERIC_BOARD Take over maintainership as well. Not tested as PG2.0 (which I have) needs additional work over PG1.0 (which Matt has). Cc: Matt Porter Signed-off-by: Tom Rini Reviewed-by: Simon Glass Tested-by: Simon Glass --- board/ti/ti814x/MAINTAINERS | 2 +- include/configs/ti814x_evm.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/ti/ti814x/MAINTAINERS b/board/ti/ti814x/MAINTAINERS index e39b253d256..b2ee39e8a33 100644 --- a/board/ti/ti814x/MAINTAINERS +++ b/board/ti/ti814x/MAINTAINERS @@ -1,5 +1,5 @@ TI814X BOARD -M: Matt Porter +M: Tom Rini S: Maintained F: board/ti/ti814x/ F: include/configs/ti814x_evm.h diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 7fa35a15425..ceeb7fe46bd 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #include -- cgit v1.3.1 From f458c8dac463d0a6037d4ecdbe59f07c4df34ad4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Sep 2015 14:54:04 -0400 Subject: ti816x: Switch to SYS_GENERIC_BOARD Tested on my TI186x rev E. (PG2.0) and take over maintainership. Signed-off-by: Tom Rini Reviewed-by: Simon Glass Tested-by: Simon Glass --- board/ti/ti816x/MAINTAINERS | 2 +- include/configs/ti816x_evm.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS index d3de144bc21..fd9a98fc762 100644 --- a/board/ti/ti816x/MAINTAINERS +++ b/board/ti/ti816x/MAINTAINERS @@ -1,5 +1,5 @@ TI816X BOARD -#M: - +M: Tom Rini S: Maintained F: board/ti/ti816x/ F: include/configs/ti816x_evm.h diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 01d82337415..4c192896ad6 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_CPU_INIT -- cgit v1.3.1 From 2573428140b3b0e5a6580066f413ef90d20441a2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 13 Aug 2015 22:34:22 -0600 Subject: ARM: tegra: Add p2371-2180 board P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and two GPIO expansion headers. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-2180.dts | 60 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 9 + board/nvidia/p2371-2180/Kconfig | 12 + board/nvidia/p2371-2180/MAINTAINERS | 6 + board/nvidia/p2371-2180/Makefile | 8 + board/nvidia/p2371-2180/p2371-2180.c | 51 ++++ board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 265 +++++++++++++++++++++ configs/p2371-2180_defconfig | 17 ++ include/configs/p2371-2180.h | 65 +++++ 10 files changed, 494 insertions(+) create mode 100644 arch/arm/dts/tegra210-p2371-2180.dts create mode 100644 board/nvidia/p2371-2180/Kconfig create mode 100644 board/nvidia/p2371-2180/MAINTAINERS create mode 100644 board/nvidia/p2371-2180/Makefile create mode 100644 board/nvidia/p2371-2180/p2371-2180.c create mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h create mode 100644 configs/p2371-2180_defconfig create mode 100644 include/configs/p2371-2180.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0a8c88de9e3..5afe8a91fd6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-venice2.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ + tegra210-p2371-2180.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts new file mode 100644 index 00000000000..5d9adcff31c --- /dev/null +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -0,0 +1,60 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA P2371-2180"; + compatible = "nvidia,p2371-2180", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index bd34db71173..b07363a4c38 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -18,6 +18,14 @@ config TARGET_P2371_0000 HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. +config TARGET_P2371_2180 + bool "NVIDIA Tegra210 P2371-2180 board" + help + P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The + combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB + micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and + two GPIO expansion headers. + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -30,6 +38,7 @@ config SYS_SOC source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2371-0000/Kconfig" +source "board/nvidia/p2371-2180/Kconfig" source "board/nvidia/p2571/Kconfig" endif diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig new file mode 100644 index 00000000000..8622bdaa16b --- /dev/null +++ b/board/nvidia/p2371-2180/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2371_2180 + +config SYS_BOARD + default "p2371-2180" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2371-2180" + +endif diff --git a/board/nvidia/p2371-2180/MAINTAINERS b/board/nvidia/p2371-2180/MAINTAINERS new file mode 100644 index 00000000000..815377490c7 --- /dev/null +++ b/board/nvidia/p2371-2180/MAINTAINERS @@ -0,0 +1,6 @@ +P2371-2180 BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/p2371-2180/ +F: include/configs/p2371-2180.h +F: configs/p2371-2180_defconfig diff --git a/board/nvidia/p2371-2180/Makefile b/board/nvidia/p2371-2180/Makefile new file mode 100644 index 00000000000..10aefb071e6 --- /dev/null +++ b/board/nvidia/p2371-2180/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p2371-2180.o diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c new file mode 100644 index 00000000000..cf2dd0b14f0 --- /dev/null +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "../p2571/max77620_init.h" +#include "pinmux-config-p2371-2180.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(p2371_2180_gpio_inits, + ARRAY_SIZE(p2371_2180_gpio_inits)); + + pinmux_config_pingrp_table(p2371_2180_pingrps, + ARRAY_SIZE(p2371_2180_pingrps)); + + pinmux_config_drvgrp_table(p2371_2180_drvgrps, + ARRAY_SIZE(p2371_2180_drvgrps)); +} diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h new file mode 100644 index 00000000000..ff89b9ee4b0 --- /dev/null +++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py p2371-2180". + */ + +#ifndef _PINMUX_CONFIG_P2371_2180_H_ +#define _PINMUX_CONFIG_P2371_2180_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(E6, IN), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H1, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, IN), + GPIO_INIT(L1, IN), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V3, IN), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y0, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z2, IN), + GPIO_INIT(Z3, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(CC1, IN), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config p2371_2180_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, DMIC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_P2371_2180_H */ diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig new file mode 100644 index 00000000000..83fde57a0c4 --- /dev/null +++ b/configs/p2371-2180_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_P2371_2180=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h new file mode 100644 index 00000000000..378d5a905e9 --- /dev/null +++ b/include/configs/p2371-2180.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P2371_2180_H +#define _P2371_2180_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (P2371-2180) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _P2371_2180_H */ -- cgit v1.3.1 From bfac08472371d4d6d4fa56972b0e1166f780633a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 19 Aug 2015 15:15:41 -0600 Subject: ARM: tegra: fix COUNTER_FREQUENCY for T210 While T210 boards all have 38.4MHz crystals, per the TRM, the only supported configuration is to divide the crystal frequency by 2 to generate clk_m, which is what feeds the ARM generic timers amongst other things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2. When I queried the 19.2 value in Tom's original T210 patches, I wasn't aware of this extra divide-by-2, and didn't notice any effect from the incorrect value, since its only used if U-Boot is booted in EL3, whereas I'm booting it in EL2. Reported-by: Thierry Reding Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/e2220-1170.h | 3 ++- include/configs/p2371-0000.h | 3 ++- include/configs/p2371-2180.h | 3 ++- include/configs/p2571.h | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index dff3f2a3573..3bc60637edc 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -60,6 +60,7 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #endif /* _E2220_1170_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 9d7b650d98c..397a0ef8ae7 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -60,6 +60,7 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 378d5a905e9..f311ae9e7d0 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -60,6 +60,7 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 356c941a773..3bf98884723 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -61,7 +61,8 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #define CONFIG_OF_BOARD_SETUP #endif /* _P2571_H */ -- cgit v1.3.1 From b9f269f60f71241500c3a28ca7a39b680eeae786 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 20 Aug 2015 17:38:42 -0600 Subject: ARM: tegra: replace V_PROMPT define with kconfig Commit 181bd9dc61d2 "kconfig: add config option for shell prompt" replaced define V_PROMPT with Kconfig option SYS_PROMPT. This crossed with patches adding Tegra T210 boards. Migrate the boards to the new scheme. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- configs/e2220-1170_defconfig | 1 + configs/p2371-0000_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + include/configs/e2220-1170.h | 1 - include/configs/p2371-0000.h | 1 - include/configs/p2371-2180.h | 1 - include/configs/p2571.h | 1 - 8 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 72e5ab39e4c..03eed5d55ac 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -15,3 +15,4 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # " diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 71a9a75bca4..f8ca4d33fe9 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -15,3 +15,4 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # " diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 83fde57a0c4..98448eed82d 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 877a905b44e..1d0b022b432 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -15,3 +15,4 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_PROMPT="Tegra210 (P2571) # " diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 3bc60637edc..32ebb82f48d 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (E2220-1170) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" /* Board-specific serial config */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 397a0ef8ae7..ac089472e65 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (P2371-0000) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" /* Board-specific serial config */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index f311ae9e7d0..3bdf1961a31 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (P2371-2180) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" /* Board-specific serial config */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 3bf98884723..51653bb17b1 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -13,7 +13,6 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra210 (P2571) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" /* Board-specific serial config */ -- cgit v1.3.1 From 95bdf6469d651076fde0e63a78024e1786a7485d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:42:21 +0200 Subject: e2220-1170: Remove hard-coded counter frequency The counter frequency is derived from clk_m on Tegra, but that clock can be configured by the primary bootloader to run at the same frequency as the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most typically 19.2 MHz). Remove the hard-coded frequency and allow the timer setup code to query the correct value at runtime. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- include/configs/e2220-1170.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 32ebb82f48d..998a69aba10 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -59,7 +59,4 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -/* Crystal is 38.4MHz. clk_m runs at half that rate */ -#define COUNTER_FREQUENCY 19200000 - #endif /* _E2220_1170_H */ -- cgit v1.3.1 From ca2d6dc25e9bbe623e3cf1467fa0b3ce4a7b70a8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:42:22 +0200 Subject: p2371: Remove hard-coded counter frequency The counter frequency is derived from clk_m on Tegra, but that clock can be configured by the primary bootloader to run at the same frequency as the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most typically 19.2 MHz). Remove the hard-coded frequency and allow the timer setup code to query the correct value at runtime. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- include/configs/p2371-0000.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index ac089472e65..f2a713d0bee 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -59,7 +59,4 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -/* Crystal is 38.4MHz. clk_m runs at half that rate */ -#define COUNTER_FREQUENCY 19200000 - #endif /* _P2371_0000_H */ -- cgit v1.3.1 From f8007235a0a50cd3538b47d1fd02e96e1f64a285 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:42:23 +0200 Subject: p2571: Remove hard-coded counter frequency The counter frequency is derived from clk_m on Tegra, but that clock can be configured by the primary bootloader to run at the same frequency as the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most typically 19.2 MHz). Remove the hard-coded frequency and allow the timer setup code to query the correct value at runtime. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- include/configs/p2571.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 51653bb17b1..c65d3e5fcbc 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -60,8 +60,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -/* Crystal is 38.4MHz. clk_m runs at half that rate */ -#define COUNTER_FREQUENCY 19200000 #define CONFIG_OF_BOARD_SETUP #endif /* _P2571_H */ -- cgit v1.3.1 From 1e0f226362ffd2bd8c1a238af1d1b21ea86d3111 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 11 Sep 2015 03:24:34 -0700 Subject: dm: pci: Add an inline API to test if a device is on a PCI bus Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/pci/pci-uclass.c | 4 ++-- include/dm/device.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index ea70853da21..0756bbe8f13 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -238,7 +238,7 @@ int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, { struct udevice *bus; - for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) + for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size); } @@ -303,7 +303,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, { struct udevice *bus; - for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) + for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep, size); diff --git a/include/dm/device.h b/include/dm/device.h index a239be64691..85196124b4d 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -485,6 +485,17 @@ bool device_is_last_sibling(struct udevice *dev); */ int device_set_name(struct udevice *dev, const char *name); +/** + * device_is_on_pci_bus - Test if a device is on a PCI bus + * + * @dev: device to test + * @return: true if it is on a PCI bus, false otherwise + */ +static inline bool device_is_on_pci_bus(struct udevice *dev) +{ + return device_get_uclass_id(dev->parent) == UCLASS_PCI; +} + /* device resource management */ typedef void (*dr_release_t)(struct udevice *dev, void *res); typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data); -- cgit v1.3.1 From 2afb62305e2a20c7a98b2c19d4902671c45f153c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 11 Sep 2015 03:24:37 -0700 Subject: x86: quark: Add PCIe/USB static register programming after memory init This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/quark/quark.c | 64 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 22 ++++++++++++ include/configs/galileo.h | 1 + 3 files changed, 87 insertions(+) (limited to 'include') diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index caa3875cc4f..934250b44bc 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -223,6 +223,53 @@ void reset_cpu(ulong addr) x86_full_reset(); } +static void quark_pcie_init(void) +{ + u32 val; + + /* PCIe upstream non-posted & posted request size */ + qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, + CCFG_UPRS | CCFG_UNRS); + qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, + CCFG_UPRS | CCFG_UNRS); + + /* PCIe packet fast transmit mode (IPF) */ + qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); + qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); + + /* PCIe message bus idle counter (SBIC) */ + qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); + val |= MBC_SBIC; + qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); + qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); + val |= MBC_SBIC; + qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); +} + +static void quark_usb_init(void) +{ + u32 bar; + + /* Change USB EHCI packet buffer OUT/IN threshold */ + qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); + writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); + + /* Disable USB device interrupts */ + qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); + writel(0x7f, bar + USBD_INT_MASK); + writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); + writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); +} + +int arch_early_init_r(void) +{ + quark_pcie_init(); + + quark_usb_init(); + + return 0; +} + int cpu_mmc_init(bd_t *bis) { return pci_mmc_init("Quark SDHCI", mmc_supported, @@ -256,3 +303,20 @@ int arch_misc_init(void) { return pirq_init(); } + +void board_final_cleanup(void) +{ + struct quark_rcba *rcba; + u32 base, val; + + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); + base &= ~MEM_BAR_EN; + rcba = (struct quark_rcba *)base; + + /* Initialize 'Component ID' to zero */ + val = readl(&rcba->esd); + val &= ~0xff0000; + writel(val, &rcba->esd); + + return; +} diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index 5d81976998d..eb3afbff1d5 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -88,6 +88,20 @@ /* 64KiB of RMU binary in flash */ #define RMU_BINARY_SIZE 0x10000 +/* PCIe Root Port Configuration Registers */ + +#define PCIE_RP_CCFG 0xd0 +#define CCFG_UPRS (1 << 14) +#define CCFG_UNRS (1 << 15) +#define CCFG_UNSD (1 << 23) +#define CCFG_UPSD (1 << 24) + +#define PCIE_RP_MPC2 0xd4 +#define MPC2_IPF (1 << 11) + +#define PCIE_RP_MBC 0xf4 +#define MBC_SBIC (3 << 16) + /* Legacy Bridge PCI Configuration Registers */ #define LB_GBA 0x44 #define LB_PM1BLK 0x48 @@ -100,6 +114,14 @@ #define LB_BC 0xd8 #define LB_RCBA 0xf0 +/* USB EHCI memory-mapped registers */ +#define EHCI_INSNREG01 0x94 + +/* USB device memory-mapped registers */ +#define USBD_INT_MASK 0x410 +#define USBD_EP_INT_STS 0x414 +#define USBD_EP_INT_MASK 0x418 + #ifndef __ASSEMBLY__ /* Root Complex Register Block */ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index b7ec2792bbe..ba6c8f172bd 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_ARCH_MISC_INIT /* ns16550 UART is memory-mapped in Quark SoC */ -- cgit v1.3.1 From 559964e7d4fe3405a5a074837c1904cc276c84f9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 10 Sep 2015 16:03:38 -0300 Subject: mx6sabre_common: Add Fastboot support Tested basic fastboot commands, such as: On the mx6qsabresd U-boot prompt: => fastboot 0 On the host PC: $ fastboot getvar bootloader-version -i 0x0525 bootloader-version: U-Boot 2015.10-rc2-23960-g2462cce-dirty finished. total time: 0.000s $ fastboot reboot -i 0x0525 --> board reboots fine. Signed-off-by: Fabio Estevam --- include/configs/mx6sabre_common.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 98eb0427aa5..2970b831098 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -238,6 +238,12 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 #endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ -- cgit v1.3.1 From a6e3159e5a5eb3fca03da792aa069df6df881f40 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Sep 2015 13:06:46 -0300 Subject: mx7dsabresd: Remove unused config option CONFIG_FEC_DMA_MINALIGN is not used anywhere, so let's remove it. Signed-off-by: Fabio Estevam --- include/configs/mx7dsabresd.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index ec6e0a6d6bf..2a736c458c9 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -24,7 +24,6 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_BROADCOM -#define CONFIG_FEC_DMA_MINALIGN 64 /* ENET1 */ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR -- cgit v1.3.1 From 3e08e1b7274bcde611928f7fdb7c78cd5f259532 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 17 Sep 2015 15:13:20 -0300 Subject: cgtqmx6eval: Add USB Mass Storage support => ums 0 mmc 0 (Mounts the micro SD) => ums 0 mmc 1 (Mounts the eMMC) => ums 0 mmc 2 (Mounts the big SD) Signed-off-by: Otavio Salvador --- include/configs/cgtqmx6eval.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index c7d54ee2492..7158ab0f2b8 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -63,6 +63,20 @@ #define CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Congatec" + /* Framebuffer */ #define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 -- cgit v1.3.1 From c4390486a6f198f82a5944eb1e123d9673331cf5 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:52:44 +0300 Subject: drivers/net/vsc9953: Remove 'CONFIG_' from macros' name Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 38 +++++++++++++++++++------------------- include/vsc9953.h | 46 +++++++++++++++++++++++----------------------- 2 files changed, 42 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index fed7358448f..068ab8695bc 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -202,26 +202,26 @@ void vsc9953_init(bd_t *bis) VSC9953_DEVCPU_GCB); out_le32(&l2dev_gcb->chip_regs.soft_rst, - CONFIG_VSC9953_SOFT_SWC_RST_ENA); + VSC9953_SOFT_SWC_RST_ENA); timeout = 50000; while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) & - CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout) + VSC9953_SOFT_SWC_RST_ENA) && --timeout) udelay(1); /* busy wait for vsc9953 soft reset */ if (timeout == 0) debug("Timeout waiting for VSC9953 to reset\n"); - out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE | - CONFIG_VSC9953_MEM_INIT); + out_le32(&l2sys_reg->sys.reset_cfg, VSC9953_MEM_ENABLE | + VSC9953_MEM_INIT); timeout = 50000; while ((in_le32(&l2sys_reg->sys.reset_cfg) & - CONFIG_VSC9953_MEM_INIT) && --timeout) + VSC9953_MEM_INIT) && --timeout) udelay(1); /* busy wait for vsc9953 memory init */ if (timeout == 0) debug("Timeout waiting for VSC9953 memory to initialize\n"); out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg) - | CONFIG_VSC9953_CORE_ENABLE)); + | VSC9953_CORE_ENABLE)); /* VSC9953 Setting to be done once only */ out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00); @@ -233,34 +233,34 @@ void vsc9953_init(bd_t *bis) /* Enable VSC9953 GMII Ports Port ID 0 - 7 */ if (VSC9953_INTERNAL_PORT_CHECK(i)) { out_le32(&l2ana_reg->pfc[i].pfc_cfg, - CONFIG_VSC9953_PFC_FC_QSGMII); + VSC9953_PFC_FC_QSGMII); out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], - CONFIG_VSC9953_MAC_FC_CFG_QSGMII); + VSC9953_MAC_FC_CFG_QSGMII); } else { out_le32(&l2ana_reg->pfc[i].pfc_cfg, - CONFIG_VSC9953_PFC_FC); + VSC9953_PFC_FC); out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], - CONFIG_VSC9953_MAC_FC_CFG); + VSC9953_MAC_FC_CFG); } out_le32(&l2dev_gmii_reg->port_mode.clock_cfg, - CONFIG_VSC9953_CLOCK_CFG); + VSC9953_CLOCK_CFG); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg, - CONFIG_VSC9953_MAC_ENA_CFG); + VSC9953_MAC_ENA_CFG); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg, - CONFIG_VSC9953_MAC_MODE_CFG); + VSC9953_MAC_MODE_CFG); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg, - CONFIG_VSC9953_MAC_IFG_CFG); + VSC9953_MAC_IFG_CFG); /* mac_hdx_cfg varies with port id*/ - hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16)); + hdx_cfg = VSC9953_MAC_HDX_CFG | (i << 16); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); out_le32(&l2sys_reg->sys.front_port_mode[i], - CONFIG_VSC9953_FRONT_PORT_MODE); + VSC9953_FRONT_PORT_MODE); out_le32(&l2qsys_reg->sys.switch_port_mode[i], - CONFIG_VSC9953_PORT_ENA); + VSC9953_PORT_ENA); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, - CONFIG_VSC9953_MAC_MAX_LEN); + VSC9953_MAC_MAX_LEN); out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], - CONFIG_VSC9953_PAUSE_CFG); + VSC9953_PAUSE_CFG); /* WAIT FOR 2 us*/ udelay(2); diff --git a/include/vsc9953.h b/include/vsc9953.h index 3d11b87a1f5..3f14dad3136 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -33,29 +33,29 @@ #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 #define VSC9953_PHY_REGS_OFFST 0x0000AC -#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001 -#define CONFIG_VSC9953_CORE_ENABLE 0x80 -#define CONFIG_VSC9953_MEM_ENABLE 0x40 -#define CONFIG_VSC9953_MEM_INIT 0x20 - -#define CONFIG_VSC9953_PORT_ENA 0x00003a00 -#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011 -#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011 -#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515 -#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043 -#define CONFIG_VSC9953_CLOCK_CFG 0x00000001 -#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001 -#define CONFIG_VSC9953_PFC_FC 0x00000001 -#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000 -#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000 -#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000 -#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe -#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff -#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000 -#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee - -#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff -#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004 +#define VSC9953_SOFT_SWC_RST_ENA 0x00000001 +#define VSC9953_CORE_ENABLE 0x80 +#define VSC9953_MEM_ENABLE 0x40 +#define VSC9953_MEM_INIT 0x20 + +#define VSC9953_PORT_ENA 0x00003a00 +#define VSC9953_MAC_ENA_CFG 0x00000011 +#define VSC9953_MAC_MODE_CFG 0x00000011 +#define VSC9953_MAC_IFG_CFG 0x00000515 +#define VSC9953_MAC_HDX_CFG 0x00001043 +#define VSC9953_CLOCK_CFG 0x00000001 +#define VSC9953_CLOCK_CFG_1000M 0x00000001 +#define VSC9953_PFC_FC 0x00000001 +#define VSC9953_PFC_FC_QSGMII 0x00000000 +#define VSC9953_MAC_FC_CFG 0x04700000 +#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 +#define VSC9953_PAUSE_CFG 0x001ffffe +#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff +#define VSC9953_FRONT_PORT_MODE 0x00000000 +#define VSC9953_MAC_MAX_LEN 0x000005ee + +#define VSC9953_VCAP_MV_CFG 0x0000ffff +#define VSC9953_VCAP_UPDATE_CTRL 0x01000004 #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) -- cgit v1.3.1 From 3cc8cfffb21b618a51a51e746aac709a12540b79 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:52:45 +0300 Subject: drivers/net/vsc9953: Cleanup patch This patch groups some macros defined for registers and replaces some magic numbers from vsc9953 with macros. Also, "port" and "port_nr" words are replaced with "port_no", puts each variable declaration on a line and removes unnecessary tabs. Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 144 +++++++++++++++++++++++++------------------------- include/vsc9953.h | 121 ++++++++++++++++++++++++++---------------- 2 files changed, 147 insertions(+), 118 deletions(-) (limited to 'include') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 068ab8695bc..524b979d525 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include static struct vsc9953_info vsc9953_l2sw = { @@ -25,50 +27,50 @@ static struct vsc9953_info vsc9953_l2sw = { .port[9] = VSC9953_PORT_INFO_INITIALIZER(9), }; -void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus) +void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].bus = bus; + vsc9953_l2sw.port[port_no].bus = bus; } -void vsc9953_port_info_set_phy_address(int port, int address) +void vsc9953_port_info_set_phy_address(int port_no, int address) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].phyaddr = address; + vsc9953_l2sw.port[port_no].phyaddr = address; } -void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int) +void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].enet_if = phy_int; + vsc9953_l2sw.port[port_no].enet_if = phy_int; } -void vsc9953_port_enable(int port) +void vsc9953_port_enable(int port_no) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].enabled = 1; + vsc9953_l2sw.port[port_no].enabled = 1; } -void vsc9953_port_disable(int port) +void vsc9953_port_disable(int port_no) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].enabled = 0; + vsc9953_l2sw.port[port_no].enabled = 0; } static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, int regnum, int value) { - int timeout = 50000; + int timeout = 50000; out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | @@ -85,8 +87,8 @@ static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, int regnum) { - int value = 0xFFFF; - int timeout = 50000; + int value = 0xFFFF; + int timeout = 50000; while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout) udelay(1); @@ -120,8 +122,8 @@ static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, static int init_phy(struct eth_device *dev) { - struct vsc9953_port_info *l2sw_port = dev->priv; - struct phy_device *phydev = NULL; + struct vsc9953_port_info *l2sw_port = dev->priv; + struct phy_device *phydev = NULL; #ifdef CONFIG_PHYLIB if (!l2sw_port->bus) @@ -148,21 +150,21 @@ static int init_phy(struct eth_device *dev) return 0; } -static int vsc9953_port_init(int port) +static int vsc9953_port_init(int port_no) { - struct eth_device *dev; + struct eth_device *dev; /* Internal ports never have a PHY */ - if (VSC9953_INTERNAL_PORT_CHECK(port)) + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) return 0; /* alloc eth device */ dev = (struct eth_device *)calloc(1, sizeof(struct eth_device)); if (!dev) - return 1; + return -ENOMEM; - sprintf(dev->name, "SW@PORT%d", port); - dev->priv = &vsc9953_l2sw.port[port]; + sprintf(dev->name, "SW@PORT%d", port_no); + dev->priv = &vsc9953_l2sw.port[port_no]; dev->init = NULL; dev->halt = NULL; dev->send = NULL; @@ -170,7 +172,7 @@ static int vsc9953_port_init(int port) if (init_phy(dev)) { free(dev); - return 1; + return -ENODEV; } return 0; @@ -178,13 +180,15 @@ static int vsc9953_port_init(int port) void vsc9953_init(bd_t *bis) { - u32 i, hdx_cfg = 0, phy_addr = 0; - int timeout; - struct vsc9953_system_reg *l2sys_reg; - struct vsc9953_qsys_reg *l2qsys_reg; - struct vsc9953_dev_gmii *l2dev_gmii_reg; - struct vsc9953_analyzer *l2ana_reg; - struct vsc9953_devcpu_gcb *l2dev_gcb; + u32 i; + u32 hdx_cfg = 0; + u32 phy_addr = 0; + int timeout; + struct vsc9953_system_reg *l2sys_reg; + struct vsc9953_qsys_reg *l2qsys_reg; + struct vsc9953_dev_gmii *l2dev_gmii_reg; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_devcpu_gcb *l2dev_gcb; l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET + VSC9953_DEV_GMII_OFFSET); @@ -312,83 +316,81 @@ void vsc9953_init(bd_t *bis) #ifdef CONFIG_VSC9953_CMD /* Enable/disable status of a VSC9953 port */ -static void vsc9953_port_status_set(int port_nr, u8 enabled) +static void vsc9953_port_status_set(int port_no, u8 enabled) { - u32 val; - struct vsc9953_qsys_reg *l2qsys_reg; + struct vsc9953_qsys_reg *l2qsys_reg; /* Administrative down */ - if (vsc9953_l2sw.port[port_nr].enabled == 0) + if (!vsc9953_l2sw.port[port_no].enabled) return; l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + VSC9953_QSYS_OFFSET); - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]); - if (enabled == 1) - val |= (1 << 13); + if (enabled) + setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); else - val &= ~(1 << 13); - - out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val); + clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); } /* Set all VSC9953 ports' status */ static void vsc9953_port_all_status_set(u8 enabled) { - int i; + int i; for (i = 0; i < VSC9953_MAX_PORTS; i++) vsc9953_port_status_set(i, enabled); } /* Start autonegotiation for a VSC9953 PHY */ -static void vsc9953_phy_autoneg(int port_nr) +static void vsc9953_phy_autoneg(int port_no) { - if (!vsc9953_l2sw.port[port_nr].phydev) + if (!vsc9953_l2sw.port[port_no].phydev) return; - if (vsc9953_l2sw.port[port_nr].phydev->drv->startup( - vsc9953_l2sw.port[port_nr].phydev)) - printf("Failed to start PHY for port %d\n", port_nr); + if (vsc9953_l2sw.port[port_no].phydev->drv->startup( + vsc9953_l2sw.port[port_no].phydev)) + printf("Failed to start PHY for port %d\n", port_no); } /* Start autonegotiation for all VSC9953 PHYs */ static void vsc9953_phy_all_autoneg(void) { - int i; + int i; for (i = 0; i < VSC9953_MAX_PORTS; i++) vsc9953_phy_autoneg(i); } /* Print a VSC9953 port's configuration */ -static void vsc9953_port_config_show(int port) +static void vsc9953_port_config_show(int port_no) { - int speed; - int duplex; - int link; - u8 enabled; - u32 val; + int speed; + int duplex; + int link; + u8 enabled; + u32 val; struct vsc9953_qsys_reg *l2qsys_reg; l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + VSC9953_QSYS_OFFSET); - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]); - enabled = vsc9953_l2sw.port[port].enabled & - ((val & 0x00002000) >> 13); + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); + enabled = vsc9953_l2sw.port[port_no].enabled && + (val & VSC9953_PORT_ENA); /* internal ports (8 and 9) are fixed */ - if (VSC9953_INTERNAL_PORT_CHECK(port)) { + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { link = 1; speed = SPEED_2500; duplex = DUPLEX_FULL; } else { - if (vsc9953_l2sw.port[port].phydev) { - link = vsc9953_l2sw.port[port].phydev->link; - speed = vsc9953_l2sw.port[port].phydev->speed; - duplex = vsc9953_l2sw.port[port].phydev->duplex; + if (vsc9953_l2sw.port[port_no].phydev) { + link = vsc9953_l2sw.port[port_no].phydev->link; + speed = vsc9953_l2sw.port[port_no].phydev->speed; + duplex = vsc9953_l2sw.port[port_no].phydev->duplex; } else { link = -1; speed = -1; @@ -396,7 +398,7 @@ static void vsc9953_port_config_show(int port) } } - printf("%8d ", port); + printf("%8d ", port_no); printf("%8s ", enabled == 1 ? "enabled" : "disabled"); printf("%8s ", link == 1 ? "up" : "down"); @@ -426,7 +428,7 @@ static void vsc9953_port_config_show(int port) /* Print VSC9953 ports' configuration */ static void vsc9953_port_all_config_show(void) { - int i; + int i; for (i = 0; i < VSC9953_MAX_PORTS; i++) vsc9953_port_config_show(i); @@ -487,11 +489,11 @@ static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(ethsw, 5, 0, do_ethsw, "vsc9953 l2 switch commands", - "port enable|disable\n" + "port enable|disable\n" " - enable/disable an l2 switch port\n" - " port_nr=0..9; use \"all\" for all ports\n" - "ethsw port show\n" + " port_no=0..9; use \"all\" for all ports\n" + "ethsw port show\n" " - show an l2 switch port's configuration\n" - " port_nr=0..9; use \"all\" for all ports\n" + " port_no=0..9; use \"all\" for all ports\n" ); #endif /* CONFIG_VSC9953_CMD */ diff --git a/include/vsc9953.h b/include/vsc9953.h index 3f14dad3136..6ebe141d68d 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -17,7 +17,6 @@ #include #include #include -#include #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) @@ -33,29 +32,57 @@ #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 #define VSC9953_PHY_REGS_OFFST 0x0000AC +/* Macros for vsc9953_chip_regs.soft_rst register */ #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 + +/* Macros for vsc9953_sys_sys.reset_cfg register */ #define VSC9953_CORE_ENABLE 0x80 #define VSC9953_MEM_ENABLE 0x40 #define VSC9953_MEM_INIT 0x20 -#define VSC9953_PORT_ENA 0x00003a00 +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ #define VSC9953_MAC_ENA_CFG 0x00000011 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ #define VSC9953_MAC_MODE_CFG 0x00000011 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ #define VSC9953_MAC_IFG_CFG 0x00000515 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ #define VSC9953_MAC_HDX_CFG 0x00001043 + +/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ +#define VSC9953_MAC_MAX_LEN 0x000005ee + +/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ #define VSC9953_CLOCK_CFG 0x00000001 #define VSC9953_CLOCK_CFG_1000M 0x00000001 + +/* Macros for vsc9953_sys_sys.front_port_mode register */ +#define VSC9953_FRONT_PORT_MODE 0x00000000 + +/* Macros for vsc9953_ana_pfc.pfc_cfg register */ #define VSC9953_PFC_FC 0x00000001 #define VSC9953_PFC_FC_QSGMII 0x00000000 + +/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ #define VSC9953_MAC_FC_CFG 0x04700000 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 + +/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ #define VSC9953_PAUSE_CFG 0x001ffffe + +/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff -#define VSC9953_FRONT_PORT_MODE 0x00000000 -#define VSC9953_MAC_MAX_LEN 0x000005ee +/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ #define VSC9953_VCAP_MV_CFG 0x0000ffff #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 + +/* Macros for vsc9953_qsys_sys.switch_port_mode register */ +#define VSC9953_PORT_ENA 0x00003a00 + #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) @@ -74,9 +101,9 @@ struct vsc9953_mdio_info { char *name; }; -/* VSC9953 ANA structure for T1040 U-boot*/ +/* VSC9953 ANA structure */ -struct vsc9953_ana_port { +struct vsc9953_ana_port { u32 vlan_cfg; u32 drop_cfg; u32 qos_cfg; @@ -138,7 +165,7 @@ struct vsc9953_ana_pgid { u32 port_grp_id[91]; }; -struct vsc9953_ana_pfc { +struct vsc9953_ana_pfc { u32 pfc_cfg; u32 reserved1[15]; }; @@ -149,7 +176,7 @@ struct vsc9953_ana_pol_misc { u32 pol_hyst; }; -struct vsc9953_ana_common { +struct vsc9953_ana_common { u32 aggr_cfg; u32 cpuq_cfg; u32 cpuq_8021_cfg; @@ -176,18 +203,18 @@ struct vsc9953_analyzer { u32 reserved5[196]; struct vsc9953_ana_common common; }; -/* END VSC9953 ANA structure for T1040 U-boot*/ +/* END VSC9953 ANA structure t*/ -/* VSC9953 DEV_GMII structure for T1040 U-boot*/ +/* VSC9953 DEV_GMII structure */ -struct vsc9953_dev_gmii_port_mode { +struct vsc9953_dev_gmii_port_mode { u32 clock_cfg; u32 port_misc; u32 reserved1; u32 eee_cfg; }; -struct vsc9953_dev_gmii_mac_cfg_status { +struct vsc9953_dev_gmii_mac_cfg_status { u32 mac_ena_cfg; u32 mac_mode_cfg; u32 mac_maxlen_cfg; @@ -205,11 +232,11 @@ struct vsc9953_dev_gmii { struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; }; -/* END VSC9953 DEV_GMII structure for T1040 U-boot*/ +/* END VSC9953 DEV_GMII structure */ -/* VSC9953 QSYS structure for T1040 U-boot*/ +/* VSC9953 QSYS structure */ -struct vsc9953_qsys_hsch { +struct vsc9953_qsys_hsch { u32 cir_cfg; u32 reserved1; u32 se_cfg; @@ -218,7 +245,7 @@ struct vsc9953_qsys_hsch { u32 reserved2[20]; }; -struct vsc9953_qsys_sys { +struct vsc9953_qsys_sys { u32 port_mode[12]; u32 switch_port_mode[11]; u32 stat_cnt_cfg; @@ -232,32 +259,32 @@ struct vsc9953_qsys_sys { u32 reserved1[23]; }; -struct vsc9953_qsys_qos_cfg { +struct vsc9953_qsys_qos_cfg { u32 red_profile[16]; u32 res_qos_mode; }; -struct vsc9953_qsys_drop_cfg { +struct vsc9953_qsys_drop_cfg { u32 egr_drop_mode; }; -struct vsc9953_qsys_mmgt { +struct vsc9953_qsys_mmgt { u32 eq_cntrl; u32 reserved1; }; -struct vsc9953_qsys_hsch_misc { +struct vsc9953_qsys_hsch_misc { u32 hsch_misc_cfg; u32 reserved1[546]; }; -struct vsc9953_qsys_res_ctrl { +struct vsc9953_qsys_res_ctrl { u32 res_cfg; u32 res_stat; }; -struct vsc9953_qsys_reg { +struct vsc9953_qsys_reg { struct vsc9953_qsys_hsch hsch[108]; struct vsc9953_qsys_sys sys; struct vsc9953_qsys_qos_cfg qos_cfg; @@ -267,18 +294,18 @@ struct vsc9953_qsys_reg { struct vsc9953_qsys_res_ctrl res_ctrl[1024]; }; -/* END VSC9953 QSYS structure for T1040 U-boot*/ +/* END VSC9953 QSYS structure */ -/* VSC9953 SYS structure for T1040 U-boot*/ +/* VSC9953 SYS structure */ -struct vsc9953_sys_stat { +struct vsc9953_sys_stat { u32 rx_cntrs[64]; u32 tx_cntrs[64]; u32 drop_cntrs[64]; u32 reserved1[6]; }; -struct vsc9953_sys_sys { +struct vsc9953_sys_sys { u32 reset_cfg; u32 reserved1; u32 vlan_etype_cfg; @@ -289,7 +316,7 @@ struct vsc9953_sys_sys { u32 reserved2[50]; }; -struct vsc9953_sys_pause_cfg { +struct vsc9953_sys_pause_cfg { u32 pause_cfg[11]; u32 pause_tot_cfg; u32 tail_drop_level[11]; @@ -297,29 +324,29 @@ struct vsc9953_sys_pause_cfg { u32 mac_fc_cfg[10]; }; -struct vsc9953_sys_mmgt { +struct vsc9953_sys_mmgt { u16 free_cnt; }; -struct vsc9953_system_reg { +struct vsc9953_system_reg { struct vsc9953_sys_stat stat; struct vsc9953_sys_sys sys; struct vsc9953_sys_pause_cfg pause_cfg; struct vsc9953_sys_mmgt mmgt; }; -/* END VSC9953 SYS structure for T1040 U-boot*/ +/* END VSC9953 SYS structure */ -/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ +/* VSC9953 DEVCPU_GCB structure */ -struct vsc9953_chip_regs { +struct vsc9953_chip_regs { u32 chipd_id; u32 gpr; u32 soft_rst; }; -struct vsc9953_gpio { +struct vsc9953_gpio { u32 gpio_out_set[10]; u32 gpio_out_clr[10]; u32 gpio_out[10]; @@ -338,31 +365,31 @@ struct vsc9953_mii_mng { u32 miiscan_lst_rslts_valid; }; -struct vsc9953_mii_read_scan { +struct vsc9953_mii_read_scan { u32 mii_scan_results_sticky[2]; }; -struct vsc9953_devcpu_gcb { +struct vsc9953_devcpu_gcb { struct vsc9953_chip_regs chip_regs; struct vsc9953_gpio gpio; struct vsc9953_mii_mng mii_mng[2]; struct vsc9953_mii_read_scan mii_read_scan; }; -/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ +/* END VSC9953 DEVCPU_GCB structure */ -/* VSC9953 IS* structure for T1040 U-boot*/ +/* VSC9953 IS* structure */ -struct vsc9953_vcap_core_cfg { +struct vsc9953_vcap_core_cfg { u32 vcap_update_ctrl; u32 vcap_mv_cfg; }; -struct vsc9953_vcap { -struct vsc9953_vcap_core_cfg vcap_core_cfg; +struct vsc9953_vcap { + struct vsc9953_vcap_core_cfg vcap_core_cfg; }; -/* END VSC9953 IS* structure for T1040 U-boot*/ +/* END VSC9953 IS* structure */ #define VSC9953_PORT_INFO_INITIALIZER(idx) \ { \ @@ -388,15 +415,15 @@ struct vsc9953_port_info { /* Structure to describe a VSC9953 switch */ struct vsc9953_info { - struct vsc9953_port_info port[VSC9953_MAX_PORTS]; + struct vsc9953_port_info port[VSC9953_MAX_PORTS]; }; void vsc9953_init(bd_t *bis); -void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus); -void vsc9953_port_info_set_phy_address(int port, int address); -void vsc9953_port_enable(int port); -void vsc9953_port_disable(int port); -void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int); +void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); +void vsc9953_port_info_set_phy_address(int port_no, int address); +void vsc9953_port_enable(int port_no); +void vsc9953_port_disable(int port_no); +void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); #endif /* _VSC9953_H_ */ -- cgit v1.3.1 From fe91095b799d21428bd39392650ca0b06789776e Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:52:46 +0300 Subject: drivers/net/vsc9953: Fix bug when enabling a port When a port is enabled at init time, the initializing function touches more bits than necessary to enable a port (also touches reserved bits and default bit values). This patch fixes this issue by changing the value of the define used to enable the port and assures that no other bits are changes by replacing out_le32() with setbits_le32(). Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 4 ++-- include/vsc9953.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 524b979d525..2e8eec41f8e 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -259,8 +259,8 @@ void vsc9953_init(bd_t *bis) out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); out_le32(&l2sys_reg->sys.front_port_mode[i], VSC9953_FRONT_PORT_MODE); - out_le32(&l2qsys_reg->sys.switch_port_mode[i], - VSC9953_PORT_ENA); + setbits_le32(&l2qsys_reg->sys.switch_port_mode[i], + VSC9953_PORT_ENA); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, VSC9953_MAC_MAX_LEN); out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], diff --git a/include/vsc9953.h b/include/vsc9953.h index 6ebe141d68d..6ae5fec1cba 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -81,7 +81,7 @@ #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ -#define VSC9953_PORT_ENA 0x00003a00 +#define VSC9953_PORT_ENA 0x00002000 #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ -- cgit v1.3.1 From 440873dfc44eec4f92c482068c8be4c9f900032f Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:24 +0300 Subject: drivers/net/vsc9953: Fix missing reserved register The VSC9953 DS reserves a register between vlan_mask and anag_efil registers. Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- include/vsc9953.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/vsc9953.h b/include/vsc9953.h index 6ae5fec1cba..8ff02c15aa7 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -143,6 +143,7 @@ struct vsc9953_ana_ana_tables { struct vsc9953_ana_ana { u32 adv_learn; u32 vlan_mask; + u32 reserved; u32 anag_efil; u32 an_events; u32 storm_limit_burst; -- cgit v1.3.1 From 8756de2824e7c282afca59db3706aa5d473a7067 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:25 +0300 Subject: include/bitfield: Add new bitfield operations These new operations allow manipulation of bitfields within a word by using a mask instead of width and shift values to extract/replace the bitfields. Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- include/bitfield.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'include') diff --git a/include/bitfield.h b/include/bitfield.h index b884c746001..a59f3c279aa 100644 --- a/include/bitfield.h +++ b/include/bitfield.h @@ -27,6 +27,12 @@ * old = bitfield_extract(old_reg_val, 10, 5); * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new); * + * or + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract_by_mask(old_reg_val, mask); + * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new); + * * The numbers 10 and 5 could for example come from data * tables which describe all bitfields in all registers. */ @@ -56,3 +62,29 @@ static inline uint bitfield_replace(uint reg_val, uint shift, uint width, return (reg_val & ~mask) | ((bitfield_val << shift) & mask); } + +/* Produces a shift of the bitfield given a mask */ +static inline uint bitfield_shift(uint mask) +{ + return mask ? ffs(mask) - 1 : 0; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) +{ + uint shift = bitfield_shift(mask); + + return (reg_val & mask) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, + uint bitfield_val) +{ + uint shift = bitfield_shift(mask); + + return (reg_val & ~mask) | ((bitfield_val << shift) & mask); +} -- cgit v1.3.1 From 9de059871f8364dd898faf0b6057b8fa69fa2728 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:26 +0300 Subject: drivers/net/vsc9953: Add default configuration for VSC9953 L2 Switch At startup, the default configuration should be: - enable HW learning on all ports (HW default); - all ports are VLAN aware; - all ports are members of VLAN 1; - all ports have Port-based VLAN 1; - on all ports, the switch is allowed to remove maximum one VLAN tag, - on egress, the switch should add a VLAN tag if the frame is classified to a different VLAN than the port's Port-based VLAN; Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 253 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/vsc9953.h | 56 +++++++++++ 2 files changed, 309 insertions(+) (limited to 'include') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 2e8eec41f8e..59e0fabbd97 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -178,6 +179,256 @@ static int vsc9953_port_init(int port_no) return 0; } +static int vsc9953_vlan_table_poll_idle(void) +{ + struct vsc9953_analyzer *l2ana_reg; + int timeout; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + timeout = 50000; + while (((in_le32(&l2ana_reg->ana_tables.vlan_access) & + VSC9953_VLAN_CMD_MASK) != VSC9953_VLAN_CMD_IDLE) && --timeout) + udelay(1); + + return timeout ? 0 : -EBUSY; +} + +/* vlan table set/clear all membership of vid */ +static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + /* read current vlan configuration */ + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, + bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, + bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_PORT_MASK | VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE | + (set_member ? VSC9953_VLAN_PORT_MASK : 0)); +} + +/* Set PVID for a VSC9953 port */ +static void vsc9953_port_vlan_pvid_set(int port_no, int pvid) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + /* Set PVID on ingress */ + val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_VID_MASK, pvid); + out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); + + /* Set PVID on egress */ + val = in_le32(&l2rew_reg->port[port_no].port_vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_PORT_VLAN_CFG_VID_MASK, + pvid); + out_le32(&l2rew_reg->port[port_no].port_vlan_cfg, val); +} + +static void vsc9953_port_all_vlan_pvid_set(int pvid) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_pvid_set(i, pvid); +} + +/* Enable/disable vlan aware of a VSC9953 port */ +static void vsc9953_port_vlan_aware_set(int port_no, int enabled) +{ + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enabled) + setbits_le32(&l2ana_reg->port[port_no].vlan_cfg, + VSC9953_VLAN_CFG_AWARE_ENA); + else + clrbits_le32(&l2ana_reg->port[port_no].vlan_cfg, + VSC9953_VLAN_CFG_AWARE_ENA); +} + +/* Set all VSC9953 ports' vlan aware */ +static void vsc9953_port_all_vlan_aware_set(int enabled) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_aware_set(i, enabled); +} + +/* Enable/disable vlan pop count of a VSC9953 port */ +static void vsc9953_port_vlan_popcnt_set(int port_no, int popcnt) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + if (popcnt > 3 || popcnt < 0) { + printf("Invalid pop count value: %d\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_POP_CNT_MASK, + popcnt); + out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); +} + +/* Set all VSC9953 ports' pop count */ +static void vsc9953_port_all_vlan_poncnt_set(int popcnt) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_popcnt_set(i, popcnt); +} + +/* Enable/disable learning for frames dropped due to ingress filtering */ +static void vsc9953_vlan_ingr_fltr_learn_drop(int enable) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enable) + setbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); + else + clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); +} + +/* Egress untag modes of a VSC9953 port */ +enum egress_untag_mode { + EGRESS_UNTAG_ALL = 0, + EGRESS_UNTAG_PVID_AND_ZERO, + EGRESS_UNTAG_ZERO, + EGRESS_UNTAG_NONE, +}; + +static void vsc9953_port_vlan_egr_untag_set(int port_no, + enum egress_untag_mode mode) +{ + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + switch (mode) { + case EGRESS_UNTAG_ALL: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_NONE); + break; + case EGRESS_UNTAG_PVID_AND_ZERO: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, + VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO); + break; + case EGRESS_UNTAG_ZERO: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, + VSC9953_TAG_CFG_ALL_BUT_ZERO); + break; + case EGRESS_UNTAG_NONE: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_ALL); + break; + default: + printf("Unknown untag mode for port %d\n", port_no); + } +} + +static void vsc9953_port_all_vlan_egress_untagged_set( + enum egress_untag_mode mode) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_set(i, mode); +} + +/***************************************************************************** +At startup, the default configuration would be: + - HW learning enabled on all ports; (HW default) + - All ports are in VLAN 1; + - All ports are VLAN aware; + - All ports have POP_COUNT 1; + - All ports have PVID 1; + - All ports have TPID 0x8100; (HW default) + - All ports tag frames classified to all VLANs that are not PVID; +*****************************************************************************/ +void vsc9953_default_configuration(void) +{ + int i; + + for (i = 0; i < VSC9953_MAX_VLAN; i++) + vsc9953_vlan_table_membership_all_set(i, 0); + vsc9953_port_all_vlan_aware_set(1); + vsc9953_port_all_vlan_pvid_set(1); + vsc9953_port_all_vlan_poncnt_set(1); + vsc9953_vlan_table_membership_all_set(1, 1); + vsc9953_vlan_ingr_fltr_learn_drop(1); + vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO); +} + void vsc9953_init(bd_t *bis) { u32 i; @@ -310,6 +561,8 @@ void vsc9953_init(bd_t *bis) } } + vsc9953_default_configuration(); + printf("VSC9953 L2 switch initialized\n"); return; } diff --git a/include/vsc9953.h b/include/vsc9953.h index 8ff02c15aa7..bb9e22df2f1 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -21,6 +21,7 @@ #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) #define VSC9953_SYS_OFFSET 0x010000 +#define VSC9953_REW_OFFSET 0x030000 #define VSC9953_DEV_GMII_OFFSET 0x100000 #define VSC9953_QSYS_OFFSET 0x200000 #define VSC9953_ANA_OFFSET 0x280000 @@ -80,9 +81,38 @@ #define VSC9953_VCAP_MV_CFG 0x0000ffff #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 +/* Macros for vsc9953_ana_port.vlan_cfg register */ +#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 +#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 +#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff + +/* Macros for vsc9953_rew_port.port_vlan_cfg register */ +#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff + +/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ +#define VSC9953_ANA_TBL_VID_MASK 0x00000fff + +/* Macros for vsc9953_ana_ana_tables.vlan_access register */ +#define VSC9953_VLAN_PORT_MASK 0x00001ffc +#define VSC9953_VLAN_CMD_MASK 0x00000003 +#define VSC9953_VLAN_CMD_IDLE 0x00000000 +#define VSC9953_VLAN_CMD_READ 0x00000001 +#define VSC9953_VLAN_CMD_WRITE 0x00000002 +#define VSC9953_VLAN_CMD_INIT 0x00000003 + /* Macros for vsc9953_qsys_sys.switch_port_mode register */ #define VSC9953_PORT_ENA 0x00002000 +/* Macros for vsc9953_ana_ana.adv_learn register */ +#define VSC9953_VLAN_CHK 0x00000400 + +/* Macros for vsc9953_rew_port.port_tag_cfg register */ +#define VSC9953_TAG_CFG_MASK 0x00000180 +#define VSC9953_TAG_CFG_NONE 0x00000000 +#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 +#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 +#define VSC9953_TAG_CFG_ALL 0x00000180 + #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) @@ -91,6 +121,9 @@ (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ ) ? 0 : 1 \ ) +#define VSC9953_MAX_VLAN 4096 +#define VSC9953_VLAN_CHECK(vid) \ + (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" @@ -338,6 +371,29 @@ struct vsc9953_system_reg { /* END VSC9953 SYS structure */ +/* VSC9953 REW structure */ + +struct vsc9953_rew_port { + u32 port_vlan_cfg; + u32 port_tag_cfg; + u32 port_port_cfg; + u32 port_dscp_cfg; + u32 port_pcp_dei_qos_map_cfg[16]; + u32 reserved[12]; +}; + +struct vsc9953_rew_common { + u32 reserve[4]; + u32 dscp_remap_dp1_cfg[64]; + u32 dscp_remap_cfg[64]; +}; + +struct vsc9953_rew_reg { + struct vsc9953_rew_port port[12]; + struct vsc9953_rew_common common; +}; + +/* END VSC9953 REW structure */ /* VSC9953 DEVCPU_GCB structure */ -- cgit v1.3.1 From 4ea54e3f2394cfca9ffaa14c181d2ae8a11677a8 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:27 +0300 Subject: common/cmd_ethsw: Add generic commands for Ethernet Switches This patch creates a flexible parser for Ethernet Switch configurations that should support complex commands. The parser searches for predefined keywords in the command and calls the proper function when a match is found. Also, the parser allows for optional keywords, such as "port", to apply the command on a port or on all ports. For now, the defined commands are: ethsw [port ] { enable | disable | show } Signed-off-by: Codrin Ciubotariu Reviewed-by: York Sun --- common/Makefile | 1 + common/cmd_ethsw.c | 347 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 48 ++++++++ 3 files changed, 396 insertions(+) create mode 100644 common/cmd_ethsw.c create mode 100644 include/ethsw.h (limited to 'include') diff --git a/common/Makefile b/common/Makefile index 556fb075929..491c56552f4 100644 --- a/common/Makefile +++ b/common/Makefile @@ -214,6 +214,7 @@ obj-$(CONFIG_DFU_TFTP) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o obj-$(CONFIG_CMD_DFU) += cmd_dfu.o obj-$(CONFIG_CMD_GPT) += cmd_gpt.o +obj-$(CONFIG_CMD_ETHSW) += cmd_ethsw.o # Power obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c new file mode 100644 index 00000000000..9a7ae74f87b --- /dev/null +++ b/common/cmd_ethsw.c @@ -0,0 +1,347 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Ethernet Switch commands + */ + +#include +#include +#include +#include + +static const char *ethsw_name; + +static struct keywords_to_function { + enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; + int cmd_func_offset; + int (*keyword_function)(struct ethsw_command_def *parsed_cmd); +} ethsw_cmd_def[] = { + { + .cmd_keyword = { + ethsw_id_enable, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_enable), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_disable, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_disable), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_show), + .keyword_function = NULL, + }, +}; + +struct keywords_optional { + int cmd_keyword[ETHSW_MAX_CMD_PARAMS]; +} cmd_opt_def[] = { + { + .cmd_keyword = { + ethsw_id_port, + ethsw_id_port_no, + ethsw_id_key_end, + }, + }, +}; + +static int keyword_match_gen(enum ethsw_keyword_id key_id, int argc, char + *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd); +static int keyword_match_port(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd); + +/* + * Define properties for each keyword; + * keep the order synced with enum ethsw_keyword_id + */ +struct keyword_def { + const char *keyword_name; + int (*match)(enum ethsw_keyword_id key_id, int argc, char *const argv[], + int *argc_nr, struct ethsw_command_def *parsed_cmd); +} keyword[] = { + { + .keyword_name = "help", + .match = &keyword_match_gen, + }, { + .keyword_name = "show", + .match = &keyword_match_gen, + }, { + .keyword_name = "port", + .match = &keyword_match_port + }, { + .keyword_name = "enable", + .match = &keyword_match_gen, + }, { + .keyword_name = "disable", + .match = &keyword_match_gen, + }, +}; + +/* + * Function used by an Ethernet Switch driver to set the functions + * that must be called by the parser when an ethsw command is given + */ +int ethsw_define_functions(const struct ethsw_command_func *cmd_func) +{ + int i; + void **aux_p; + int (*cmd_func_aux)(struct ethsw_command_def *); + + if (!cmd_func->ethsw_name) + return -EINVAL; + + ethsw_name = cmd_func->ethsw_name; + + for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) { + /* + * get the pointer to the function send by the Ethernet Switch + * driver that corresponds to the proper ethsw command + */ + if (ethsw_cmd_def[i].keyword_function) + continue; + + aux_p = (void *)cmd_func + ethsw_cmd_def[i].cmd_func_offset; + + cmd_func_aux = (int (*)(struct ethsw_command_def *)) *aux_p; + ethsw_cmd_def[i].keyword_function = cmd_func_aux; + } + + return 0; +} + +/* Generic function used to match a keyword only by a string */ +static int keyword_match_gen(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd) +{ + if (strcmp(argv[*argc_nr], keyword[key_id].keyword_name) == 0) { + parsed_cmd->cmd_to_keywords[*argc_nr] = key_id; + + return 1; + } + return 0; +} + +/* Function used to match the command's port */ +static int keyword_match_port(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd) +{ + unsigned long val; + + if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd)) + return 0; + + if (*argc_nr + 1 >= argc) + return 0; + + if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) { + parsed_cmd->port = val; + (*argc_nr)++; + parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_port_no; + return 1; + } + + return 0; +} + +/* Finds optional keywords and modifies *argc_va to skip them */ +static void cmd_keywords_opt_check(const struct ethsw_command_def *parsed_cmd, + int *argc_val) +{ + int i; + int keyw_opt_matched; + int argc_val_max; + int const *cmd_keyw_p; + int const *cmd_keyw_opt_p; + + /* remember the best match */ + argc_val_max = *argc_val; + + /* + * check if our command's optional keywords match the optional + * keywords of an available command + */ + for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) { + keyw_opt_matched = 0; + cmd_keyw_p = &parsed_cmd->cmd_to_keywords[keyw_opt_matched]; + cmd_keyw_opt_p = &cmd_opt_def[i].cmd_keyword[keyw_opt_matched]; + + /* + * increase the number of keywords that + * matched with a command + */ + while (keyw_opt_matched + *argc_val < + parsed_cmd->cmd_keywords_nr && + *cmd_keyw_opt_p != ethsw_id_key_end && + *(cmd_keyw_p + *argc_val) == *cmd_keyw_opt_p) { + keyw_opt_matched++; + cmd_keyw_p++; + cmd_keyw_opt_p++; + } + + /* + * if all our optional command's keywords perfectly match an + * optional pattern, then we can move to the next defined + * keywords in our command; remember the one that matched the + * greatest number of keywords + */ + if (keyw_opt_matched + *argc_val <= + parsed_cmd->cmd_keywords_nr && + *cmd_keyw_opt_p == ethsw_id_key_end && + *argc_val + keyw_opt_matched > argc_val_max) + argc_val_max = *argc_val + keyw_opt_matched; + } + + *argc_val = argc_val_max; +} + +/* + * Finds the function to call based on keywords and + * modifies *argc_va to skip them + */ +static void cmd_keywords_check(struct ethsw_command_def *parsed_cmd, + int *argc_val) +{ + int i; + int keyw_matched; + int *cmd_keyw_p; + int *cmd_keyw_def_p; + + /* + * check if our command's keywords match the + * keywords of an available command + */ + for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) { + keyw_matched = 0; + cmd_keyw_p = &parsed_cmd->cmd_to_keywords[keyw_matched]; + cmd_keyw_def_p = ðsw_cmd_def[i].cmd_keyword[keyw_matched]; + + /* + * increase the number of keywords that + * matched with a command + */ + while (keyw_matched + *argc_val < parsed_cmd->cmd_keywords_nr && + *cmd_keyw_def_p != ethsw_id_key_end && + *(cmd_keyw_p + *argc_val) == *cmd_keyw_def_p) { + keyw_matched++; + cmd_keyw_p++; + cmd_keyw_def_p++; + } + + /* + * if all our command's keywords perfectly match an + * available command, then we get the function we need to call + * to configure the Ethernet Switch + */ + if (keyw_matched && keyw_matched + *argc_val == + parsed_cmd->cmd_keywords_nr && + *cmd_keyw_def_p == ethsw_id_key_end) { + *argc_val += keyw_matched; + parsed_cmd->cmd_function = + ethsw_cmd_def[i].keyword_function; + return; + } + } +} + +/* find all the keywords in the command */ +static int keywords_find(int argc, char * const argv[], + struct ethsw_command_def *parsed_cmd) +{ + int i; + int j; + int argc_val; + int rc = CMD_RET_SUCCESS; + + for (i = 1; i < argc; i++) { + for (j = 0; j < ethsw_id_count; j++) { + if (keyword[j].match(j, argc, argv, &i, parsed_cmd)) + break; + } + } + + /* if there is no keyword match for a word, the command is invalid */ + for (i = 1; i < argc; i++) + if (parsed_cmd->cmd_to_keywords[i] == ethsw_id_key_end) + rc = CMD_RET_USAGE; + + parsed_cmd->cmd_keywords_nr = argc; + argc_val = 1; + + /* get optional parameters first */ + cmd_keywords_opt_check(parsed_cmd, &argc_val); + + if (argc_val == parsed_cmd->cmd_keywords_nr) + return CMD_RET_USAGE; + + /* + * check the keywords and if a match is found, + * get the function to call + */ + cmd_keywords_check(parsed_cmd, &argc_val); + + /* error if not all commands' parameters were matched */ + if (argc_val == parsed_cmd->cmd_keywords_nr) { + if (!parsed_cmd->cmd_function) { + printf("Command not available for: %s\n", ethsw_name); + rc = CMD_RET_FAILURE; + } + } else { + rc = CMD_RET_USAGE; + } + + return rc; +} + +static void command_def_init(struct ethsw_command_def *parsed_cmd) +{ + int i; + + for (i = 0; i < ETHSW_MAX_CMD_PARAMS; i++) + parsed_cmd->cmd_to_keywords[i] = ethsw_id_key_end; + + parsed_cmd->port = ETHSW_CMD_PORT_ALL; + parsed_cmd->cmd_function = NULL; +} + +/* function to interpret commands starting with "ethsw " */ +static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct ethsw_command_def parsed_cmd; + int rc = CMD_RET_SUCCESS; + + if (argc == 1 || argc >= ETHSW_MAX_CMD_PARAMS) + return CMD_RET_USAGE; + + command_def_init(&parsed_cmd); + + rc = keywords_find(argc, argv, &parsed_cmd); + + if (rc == CMD_RET_SUCCESS) + rc = parsed_cmd.cmd_function(&parsed_cmd); + + return rc; +} + +#define ETHSW_PORT_CONF_HELP "[port ] { enable | disable | show } " \ +"- enable/disable a port; show shows a port's configuration" + +U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, + "Ethernet l2 switch commands", + ETHSW_PORT_CONF_HELP"\n" +); diff --git a/include/ethsw.h b/include/ethsw.h new file mode 100644 index 00000000000..9e80095dd75 --- /dev/null +++ b/include/ethsw.h @@ -0,0 +1,48 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Ethernet Switch commands + */ + +#ifndef _CMD_ETHSW_H_ +#define _CMD_ETHSW_H_ + +#define ETHSW_MAX_CMD_PARAMS 20 +#define ETHSW_CMD_PORT_ALL -1 + +/* IDs used to track keywords in a command */ +enum ethsw_keyword_id { + ethsw_id_key_end = -1, + ethsw_id_help, + ethsw_id_show, + ethsw_id_port, + ethsw_id_enable, + ethsw_id_disable, + ethsw_id_count, /* keep last */ +}; + +enum ethsw_keyword_opt_id { + ethsw_id_port_no = ethsw_id_count + 1, + ethsw_id_count_all, /* keep last */ +}; + +struct ethsw_command_def { + int cmd_to_keywords[ETHSW_MAX_CMD_PARAMS]; + int cmd_keywords_nr; + int port; + int (*cmd_function)(struct ethsw_command_def *parsed_cmd); +}; + +/* Structure to be created and initialized by an Ethernet Switch driver */ +struct ethsw_command_func { + const char *ethsw_name; + int (*port_enable)(struct ethsw_command_def *parsed_cmd); + int (*port_disable)(struct ethsw_command_def *parsed_cmd); + int (*port_show)(struct ethsw_command_def *parsed_cmd); +}; + +int ethsw_define_functions(const struct ethsw_command_func *cmd_func); + +#endif /* _CMD_ETHSW_H_ */ -- cgit v1.3.1 From 24a23deb90eea0acf049e226a70d8507394833c5 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:28 +0300 Subject: drivers/net/vsc9953: Use the generic Ethernet Switch parser This patch replaces the parser used by VSC9953 L2 Switch driver with the generic one. Also, the config macro that enables the VSC9953 commands has been replaced in all the platforms that use this driver with the config macro that corresponds to the generic parser. Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 349 +++++++++++++++++++++------------------------ include/configs/T104xRDB.h | 2 +- 2 files changed, 166 insertions(+), 185 deletions(-) (limited to 'include') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 59e0fabbd97..bf53535fb44 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -14,6 +14,7 @@ #include #include #include +#include static struct vsc9953_info vsc9953_l2sw = { .port[0] = VSC9953_PORT_INFO_INITIALIZER(0), @@ -405,6 +406,165 @@ static void vsc9953_port_all_vlan_egress_untagged_set( vsc9953_port_vlan_egr_untag_set(i, mode); } +#ifdef CONFIG_CMD_ETHSW + +/* Enable/disable status of a VSC9953 port */ +static void vsc9953_port_status_set(int port_no, u8 enabled) +{ + struct vsc9953_qsys_reg *l2qsys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) + return; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + if (enabled) + setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); + else + clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); +} + +/* Start autonegotiation for a VSC9953 PHY */ +static void vsc9953_phy_autoneg(int port_no) +{ + if (!vsc9953_l2sw.port[port_no].phydev) + return; + + if (vsc9953_l2sw.port[port_no].phydev->drv->startup( + vsc9953_l2sw.port[port_no].phydev)) + printf("Failed to start PHY for port %d\n", port_no); +} + +/* Print a VSC9953 port's configuration */ +static void vsc9953_port_config_show(int port_no) +{ + int speed; + int duplex; + int link; + u8 enabled; + u32 val; + struct vsc9953_qsys_reg *l2qsys_reg; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); + enabled = vsc9953_l2sw.port[port_no].enabled && + (val & VSC9953_PORT_ENA); + + /* internal ports (8 and 9) are fixed */ + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { + link = 1; + speed = SPEED_2500; + duplex = DUPLEX_FULL; + } else { + if (vsc9953_l2sw.port[port_no].phydev) { + link = vsc9953_l2sw.port[port_no].phydev->link; + speed = vsc9953_l2sw.port[port_no].phydev->speed; + duplex = vsc9953_l2sw.port[port_no].phydev->duplex; + } else { + link = -1; + speed = -1; + duplex = -1; + } + } + + printf("%8d ", port_no); + printf("%8s ", enabled == 1 ? "enabled" : "disabled"); + printf("%8s ", link == 1 ? "up" : "down"); + + switch (speed) { + case SPEED_10: + printf("%8d ", 10); + break; + case SPEED_100: + printf("%8d ", 100); + break; + case SPEED_1000: + printf("%8d ", 1000); + break; + case SPEED_2500: + printf("%8d ", 2500); + break; + case SPEED_10000: + printf("%8d ", 10000); + break; + default: + printf("%8s ", "-"); + } + + printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); +} + +static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + u8 enabled; + + /* Last keyword should tell us if we should enable/disable the port */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_enable) + enabled = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + enabled = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_status_set(parsed_cmd->port, enabled); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_status_set(i, enabled); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_phy_autoneg(parsed_cmd->port); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", + "Duplex"); + vsc9953_port_config_show(parsed_cmd->port); + + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_phy_autoneg(i); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", "Duplex"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_config_show(i); + } + + return CMD_RET_SUCCESS; +} + +static struct ethsw_command_func vsc9953_cmd_func = { + .ethsw_name = "L2 Switch VSC9953", + .port_enable = &vsc9953_port_status_key_func, + .port_disable = &vsc9953_port_status_key_func, + .port_show = &vsc9953_port_config_key_func, +}; + +#endif /* CONFIG_CMD_ETHSW */ + /***************************************************************************** At startup, the default configuration would be: - HW learning enabled on all ports; (HW default) @@ -563,190 +723,11 @@ void vsc9953_init(bd_t *bis) vsc9953_default_configuration(); +#ifdef CONFIG_CMD_ETHSW + if (ethsw_define_functions(&vsc9953_cmd_func) < 0) + debug("Unable to use \"ethsw\" commands\n"); +#endif + printf("VSC9953 L2 switch initialized\n"); return; } - -#ifdef CONFIG_VSC9953_CMD -/* Enable/disable status of a VSC9953 port */ -static void vsc9953_port_status_set(int port_no, u8 enabled) -{ - struct vsc9953_qsys_reg *l2qsys_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) - return; - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - if (enabled) - setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], - VSC9953_PORT_ENA); - else - clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], - VSC9953_PORT_ENA); -} - -/* Set all VSC9953 ports' status */ -static void vsc9953_port_all_status_set(u8 enabled) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_status_set(i, enabled); -} - -/* Start autonegotiation for a VSC9953 PHY */ -static void vsc9953_phy_autoneg(int port_no) -{ - if (!vsc9953_l2sw.port[port_no].phydev) - return; - - if (vsc9953_l2sw.port[port_no].phydev->drv->startup( - vsc9953_l2sw.port[port_no].phydev)) - printf("Failed to start PHY for port %d\n", port_no); -} - -/* Start autonegotiation for all VSC9953 PHYs */ -static void vsc9953_phy_all_autoneg(void) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_phy_autoneg(i); -} - -/* Print a VSC9953 port's configuration */ -static void vsc9953_port_config_show(int port_no) -{ - int speed; - int duplex; - int link; - u8 enabled; - u32 val; - struct vsc9953_qsys_reg *l2qsys_reg; - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); - enabled = vsc9953_l2sw.port[port_no].enabled && - (val & VSC9953_PORT_ENA); - - /* internal ports (8 and 9) are fixed */ - if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { - link = 1; - speed = SPEED_2500; - duplex = DUPLEX_FULL; - } else { - if (vsc9953_l2sw.port[port_no].phydev) { - link = vsc9953_l2sw.port[port_no].phydev->link; - speed = vsc9953_l2sw.port[port_no].phydev->speed; - duplex = vsc9953_l2sw.port[port_no].phydev->duplex; - } else { - link = -1; - speed = -1; - duplex = -1; - } - } - - printf("%8d ", port_no); - printf("%8s ", enabled == 1 ? "enabled" : "disabled"); - printf("%8s ", link == 1 ? "up" : "down"); - - switch (speed) { - case SPEED_10: - printf("%8d ", 10); - break; - case SPEED_100: - printf("%8d ", 100); - break; - case SPEED_1000: - printf("%8d ", 1000); - break; - case SPEED_2500: - printf("%8d ", 2500); - break; - case SPEED_10000: - printf("%8d ", 10000); - break; - default: - printf("%8s ", "-"); - } - - printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); -} - -/* Print VSC9953 ports' configuration */ -static void vsc9953_port_all_config_show(void) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_config_show(i); -} - -/* function to interpret commands starting with "ethsw " */ -static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u8 enable; - u32 port; - - if (argc < 4) - return -1; - - if (strcmp(argv[1], "port")) - return -1; - - if (!strcmp(argv[3], "show")) { - if (!strcmp(argv[2], "all")) { - vsc9953_phy_all_autoneg(); - printf("%8s %8s %8s %8s %8s\n", - "Port", "Status", "Link", "Speed", - "Duplex"); - vsc9953_port_all_config_show(); - return 0; - } else { - port = simple_strtoul(argv[2], NULL, 10); - if (!VSC9953_PORT_CHECK(port)) - return -1; - vsc9953_phy_autoneg(port); - printf("%8s %8s %8s %8s %8s\n", - "Port", "Status", "Link", "Speed", - "Duplex"); - vsc9953_port_config_show(port); - return 0; - } - } else if (!strcmp(argv[3], "enable")) { - enable = 1; - } else if (!strcmp(argv[3], "disable")) { - enable = 0; - } else { - return -1; - } - - if (!strcmp(argv[2], "all")) { - vsc9953_port_all_status_set(enable); - return 0; - } else { - port = simple_strtoul(argv[2], NULL, 10); - if (!VSC9953_PORT_CHECK(port)) - return -1; - vsc9953_port_status_set(port, enable); - return 0; - } - - return -1; -} - -U_BOOT_CMD(ethsw, 5, 0, do_ethsw, - "vsc9953 l2 switch commands", - "port enable|disable\n" - " - enable/disable an l2 switch port\n" - " port_no=0..9; use \"all\" for all ports\n" - "ethsw port show\n" - " - show an l2 switch port's configuration\n" - " port_no=0..9; use \"all\" for all ports\n" -); -#endif /* CONFIG_VSC9953_CMD */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index cd5b3e2adaf..5b61b56a4e7 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -759,7 +759,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) #define CONFIG_VSC9953 -#define CONFIG_VSC9953_CMD +#define CONFIG_CMD_ETHSW #ifdef CONFIG_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 -- cgit v1.3.1 From 86719f0cd55bc13186798217b08fa6a048eda27c Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:29 +0300 Subject: drivers/net/vsc9953: Add command to show/clear port counters The new added command: ethsw [port ] statistics { [help] | [clear] } will print counters like the number of Rx/Tx frames, number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc. This patch also adds this commnd in the genereric ethsw parser from cmd_ethsw.c Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/cmd_ethsw.c | 42 +++++++++ drivers/net/vsc9953.c | 256 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 4 + include/vsc9953.h | 116 ++++++++++++++++++++++- 4 files changed, 415 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c index 9a7ae74f87b..8c54a3d7e46 100644 --- a/common/cmd_ethsw.c +++ b/common/cmd_ethsw.c @@ -13,6 +13,16 @@ static const char *ethsw_name; +#define ETHSW_PORT_STATS_HELP "ethsw [port ] statistics " \ +"{ [help] | [clear] } - show an l2 switch port's statistics" + +static int ethsw_port_stats_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_PORT_STATS_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -42,6 +52,31 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, port_show), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_statistics, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_port_stats_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_statistics, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_stats), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_statistics, + ethsw_id_clear, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_stats_clear), + .keyword_function = NULL, }, }; @@ -88,6 +123,12 @@ struct keyword_def { }, { .keyword_name = "disable", .match = &keyword_match_gen, + }, { + .keyword_name = "statistics", + .match = &keyword_match_gen, + }, { + .keyword_name = "clear", + .match = &keyword_match_gen, }, }; @@ -344,4 +385,5 @@ static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, "Ethernet l2 switch commands", ETHSW_PORT_CONF_HELP"\n" + ETHSW_PORT_STATS_HELP"\n" ); diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index bf53535fb44..1dddb44c8bf 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -500,6 +500,223 @@ static void vsc9953_port_config_show(int port_no) printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); } +/* Show VSC9953 ports' statistics */ +static void vsc9953_port_statistics_show(int port_no) +{ + u32 rx_val; + u32 tx_val; + struct vsc9953_system_reg *l2sys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + printf("Statistics for L2 Switch port %d:\n", port_no); + + /* Set counter view for our port */ + out_le32(&l2sys_reg->sys.stat_cfg, port_no); + +#define VSC9953_STATS_PRINTF "%-15s %10u" + + /* Get number of Rx and Tx frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx frames:", rx_val, "Tx frames:", tx_val); + + /* Get number of Rx and Tx bytes */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_oct); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_oct); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx bytes:", rx_val, "Tx bytes:", tx_val); + + /* Get number of Rx frames received ok and Tx frames sent ok */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_0) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_1) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_2) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_3) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_4) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_5) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_6) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_7) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_0) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_1) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_2) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_3) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_4) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_5) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_6) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_7); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx frames ok:", rx_val, "Tx frames ok:", tx_val); + + /* Get number of Rx and Tx unicast frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_uc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_uc); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx unicast:", rx_val, "Tx unicast:", tx_val); + + /* Get number of Rx and Tx broadcast frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_bc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_bc); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx broadcast:", rx_val, "Tx broadcast:", tx_val); + + /* Get number of Rx and Tx frames of 64B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 64B:", rx_val, "Tx 64B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 65B and 127B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 65B-127B:", rx_val, "Tx 65B-127B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 128B and 255B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 128B-255B:", rx_val, "Tx 128B-255B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 256B and 511B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 256B-511B:", rx_val, "Tx 256B-511B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 512B and 1023B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 512B-1023B:", rx_val, "Tx 512B-1023B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 1024B and 1526B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 1024B-1526B:", rx_val, "Tx 1024B-1526B:", tx_val); + + /* Get number of Rx and Tx jumbo frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx jumbo:", rx_val, "Tx jumbo:", tx_val); + + /* Get number of Rx and Tx dropped frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_tail) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_0) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_1) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_2) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_3) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_4) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_5) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_6) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_7) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_0) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_1) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_2) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_3) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_4) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_5) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_6) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_7); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_drop) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx drops:", rx_val, "Tx drops:", tx_val); + + /* + * Get number of Rx frames with CRC or alignment errors + * and number of detected Tx collisions + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_crc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_col); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx CRC&align:", rx_val, "Tx coll:", tx_val); + + /* + * Get number of Rx undersized frames and + * number of Tx aged frames + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx undersize:", rx_val, "Tx aged:", tx_val); + + /* Get number of Rx oversized frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long); + printf(VSC9953_STATS_PRINTF"\n", "Rx oversized:", rx_val); + + /* Get number of Rx fragmented frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag); + printf(VSC9953_STATS_PRINTF"\n", "Rx fragments:", rx_val); + + /* Get number of Rx jabber errors */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber); + printf(VSC9953_STATS_PRINTF"\n", "Rx jabbers:", rx_val); + + /* + * Get number of Rx frames filtered due to classification rules or + * no destination ports + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_local); + printf(VSC9953_STATS_PRINTF"\n", "Rx filtered:", rx_val); + + printf("\n"); +} + +/* Clear statistics for a VSC9953 port */ +static void vsc9953_port_statistics_clear(int port_no) +{ + struct vsc9953_system_reg *l2sys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + /* Clear all counter groups for our ports */ + out_le32(&l2sys_reg->sys.stat_cfg, port_no | + VSC9953_STAT_CLEAR_RX | VSC9953_STAT_CLEAR_TX | + VSC9953_STAT_CLEAR_DR); +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -556,11 +773,50 @@ static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_port_stats_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_statistics_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_statistics_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def + *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_statistics_clear(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_statistics_clear(i); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, .port_disable = &vsc9953_port_status_key_func, .port_show = &vsc9953_port_config_key_func, + .port_stats = &vsc9953_port_stats_key_func, + .port_stats_clear = &vsc9953_port_stats_clear_key_func, }; #endif /* CONFIG_CMD_ETHSW */ diff --git a/include/ethsw.h b/include/ethsw.h index 9e80095dd75..8f1c4145a18 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -20,6 +20,8 @@ enum ethsw_keyword_id { ethsw_id_port, ethsw_id_enable, ethsw_id_disable, + ethsw_id_statistics, + ethsw_id_clear, ethsw_id_count, /* keep last */ }; @@ -41,6 +43,8 @@ struct ethsw_command_func { int (*port_enable)(struct ethsw_command_def *parsed_cmd); int (*port_disable)(struct ethsw_command_def *parsed_cmd); int (*port_show)(struct ethsw_command_def *parsed_cmd); + int (*port_stats)(struct ethsw_command_def *parsed_cmd); + int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/vsc9953.h b/include/vsc9953.h index bb9e22df2f1..83c4c89d62f 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -77,6 +77,11 @@ /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff +/* Macros for vsc9953_sys_sys.stat_cfg register */ +#define VSC9953_STAT_CLEAR_RX 0x00000400 +#define VSC9953_STAT_CLEAR_TX 0x00000800 +#define VSC9953_STAT_CLEAR_DR 0x00001000 + /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ #define VSC9953_VCAP_MV_CFG 0x0000ffff #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 @@ -332,10 +337,115 @@ struct vsc9953_qsys_reg { /* VSC9953 SYS structure */ +struct vsc9953_rx_cntrs { + u32 c_rx_oct; + u32 c_rx_uc; + u32 c_rx_mc; + u32 c_rx_bc; + u32 c_rx_short; + u32 c_rx_frag; + u32 c_rx_jabber; + u32 c_rx_crc; + u32 c_rx_symbol_err; + u32 c_rx_sz_64; + u32 c_rx_sz_65_127; + u32 c_rx_sz_128_255; + u32 c_rx_sz_256_511; + u32 c_rx_sz_512_1023; + u32 c_rx_sz_1024_1526; + u32 c_rx_sz_jumbo; + u32 c_rx_pause; + u32 c_rx_control; + u32 c_rx_long; + u32 c_rx_cat_drop; + u32 c_rx_red_prio_0; + u32 c_rx_red_prio_1; + u32 c_rx_red_prio_2; + u32 c_rx_red_prio_3; + u32 c_rx_red_prio_4; + u32 c_rx_red_prio_5; + u32 c_rx_red_prio_6; + u32 c_rx_red_prio_7; + u32 c_rx_yellow_prio_0; + u32 c_rx_yellow_prio_1; + u32 c_rx_yellow_prio_2; + u32 c_rx_yellow_prio_3; + u32 c_rx_yellow_prio_4; + u32 c_rx_yellow_prio_5; + u32 c_rx_yellow_prio_6; + u32 c_rx_yellow_prio_7; + u32 c_rx_green_prio_0; + u32 c_rx_green_prio_1; + u32 c_rx_green_prio_2; + u32 c_rx_green_prio_3; + u32 c_rx_green_prio_4; + u32 c_rx_green_prio_5; + u32 c_rx_green_prio_6; + u32 c_rx_green_prio_7; + u32 reserved[20]; +}; + +struct vsc9953_tx_cntrs { + u32 c_tx_oct; + u32 c_tx_uc; + u32 c_tx_mc; + u32 c_tx_bc; + u32 c_tx_col; + u32 c_tx_drop; + u32 c_tx_pause; + u32 c_tx_sz_64; + u32 c_tx_sz_65_127; + u32 c_tx_sz_128_255; + u32 c_tx_sz_256_511; + u32 c_tx_sz_512_1023; + u32 c_tx_sz_1024_1526; + u32 c_tx_sz_jumbo; + u32 c_tx_yellow_prio_0; + u32 c_tx_yellow_prio_1; + u32 c_tx_yellow_prio_2; + u32 c_tx_yellow_prio_3; + u32 c_tx_yellow_prio_4; + u32 c_tx_yellow_prio_5; + u32 c_tx_yellow_prio_6; + u32 c_tx_yellow_prio_7; + u32 c_tx_green_prio_0; + u32 c_tx_green_prio_1; + u32 c_tx_green_prio_2; + u32 c_tx_green_prio_3; + u32 c_tx_green_prio_4; + u32 c_tx_green_prio_5; + u32 c_tx_green_prio_6; + u32 c_tx_green_prio_7; + u32 c_tx_aged; + u32 reserved[33]; +}; + +struct vsc9953_drop_cntrs { + u32 c_dr_local; + u32 c_dr_tail; + u32 c_dr_yellow_prio_0; + u32 c_dr_yellow_prio_1; + u32 c_dr_yellow_prio_2; + u32 c_dr_yellow_prio_3; + u32 c_dr_yellow_prio_4; + u32 c_dr_yellow_prio_5; + u32 c_dr_yellow_prio_6; + u32 c_dr_yellow_prio_7; + u32 c_dr_green_prio_0; + u32 c_dr_green_prio_1; + u32 c_dr_green_prio_2; + u32 c_dr_green_prio_3; + u32 c_dr_green_prio_4; + u32 c_dr_green_prio_5; + u32 c_dr_green_prio_6; + u32 c_dr_green_prio_7; + u32 reserved[46]; +}; + struct vsc9953_sys_stat { - u32 rx_cntrs[64]; - u32 tx_cntrs[64]; - u32 drop_cntrs[64]; + struct vsc9953_rx_cntrs rx_cntrs; + struct vsc9953_tx_cntrs tx_cntrs; + struct vsc9953_drop_cntrs drop_cntrs; u32 reserved1[6]; }; -- cgit v1.3.1 From 68c929da6bf754ace639b2159e2d5b9e22323aaa Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:30 +0300 Subject: drivers/net/vsc9953: Add commands to enable/disable HW learning The command: ethsw [port ] learning { [help] | show | auto | disable } can be used to enable/disable HW learning on a port. This patch also adds this command to the generic ethsw parser from cmd_ethsw. Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/cmd_ethsw.c | 60 +++++++++++++++++++++ drivers/net/vsc9953.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 4 ++ include/vsc9953.h | 6 +++ 4 files changed, 211 insertions(+) (limited to 'include') diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c index 8c54a3d7e46..c1c33d10482 100644 --- a/common/cmd_ethsw.c +++ b/common/cmd_ethsw.c @@ -23,6 +23,17 @@ static int ethsw_port_stats_help_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +#define ETHSW_LEARN_HELP "ethsw [port ] learning " \ +"{ [help] | show | auto | disable } " \ +"- enable/disable/show learning configuration on a port" + +static int ethsw_learn_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_LEARN_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -77,6 +88,48 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, port_stats_clear), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_learning, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_learn_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_learning, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_learn_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_learning, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_learn_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_learning, + ethsw_id_auto, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_learn), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_learning, + ethsw_id_disable, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_learn), + .keyword_function = NULL, }, }; @@ -129,6 +182,12 @@ struct keyword_def { }, { .keyword_name = "clear", .match = &keyword_match_gen, + }, { + .keyword_name = "learning", + .match = &keyword_match_gen, + }, { + .keyword_name = "auto", + .match = &keyword_match_gen, }, }; @@ -386,4 +445,5 @@ U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, "Ethernet l2 switch commands", ETHSW_PORT_CONF_HELP"\n" ETHSW_PORT_STATS_HELP"\n" + ETHSW_LEARN_HELP"\n" ); diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 1dddb44c8bf..21b14e6a190 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -717,6 +717,72 @@ static void vsc9953_port_statistics_clear(int port_no) VSC9953_STAT_CLEAR_DR); } +enum port_learn_mode { + PORT_LEARN_NONE, + PORT_LEARN_AUTO +}; + +/* Set learning configuration for a VSC9953 port */ +static void vsc9953_port_learn_mode_set(int port_no, enum port_learn_mode mode) +{ + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (mode) { + case PORT_LEARN_NONE: + clrbits_le32(&l2ana_reg->port[port_no].port_cfg, + VSC9953_PORT_CFG_LEARN_DROP | + VSC9953_PORT_CFG_LEARN_CPU | + VSC9953_PORT_CFG_LEARN_AUTO | + VSC9953_PORT_CFG_LEARN_ENA); + break; + case PORT_LEARN_AUTO: + clrsetbits_le32(&l2ana_reg->port[port_no].port_cfg, + VSC9953_PORT_CFG_LEARN_DROP | + VSC9953_PORT_CFG_LEARN_CPU, + VSC9953_PORT_CFG_LEARN_ENA | + VSC9953_PORT_CFG_LEARN_AUTO); + break; + default: + printf("Unknown learn mode for port %d\n", port_no); + } +} + +/* Get learning configuration for a VSC9953 port */ +static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return -1; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* For now we only support HW learning (auto) and no learning */ + val = in_le32(&l2ana_reg->port[port_no].port_cfg); + if ((val & (VSC9953_PORT_CFG_LEARN_ENA | + VSC9953_PORT_CFG_LEARN_AUTO)) == + (VSC9953_PORT_CFG_LEARN_ENA | VSC9953_PORT_CFG_LEARN_AUTO)) + *mode = PORT_LEARN_AUTO; + else + *mode = PORT_LEARN_NONE; + + return 0; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -810,6 +876,79 @@ static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def return CMD_RET_SUCCESS; } +static int vsc9953_learn_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum port_learn_mode mode; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + if (vsc9953_port_learn_mode_get(parsed_cmd->port, &mode)) + return CMD_RET_FAILURE; + printf("%7s %11s\n", "Port", "Learn mode"); + switch (mode) { + case PORT_LEARN_NONE: + printf("%7d %11s\n", parsed_cmd->port, "disable"); + break; + case PORT_LEARN_AUTO: + printf("%7d %11s\n", parsed_cmd->port, "auto"); + break; + default: + printf("%7d %11s\n", parsed_cmd->port, "-"); + } + } else { + printf("%7s %11s\n", "Port", "Learn mode"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_learn_mode_get(i, &mode)) + continue; + switch (mode) { + case PORT_LEARN_NONE: + printf("%7d %11s\n", i, "disable"); + break; + case PORT_LEARN_AUTO: + printf("%7d %11s\n", i, "auto"); + break; + default: + printf("%7d %11s\n", i, "-"); + } + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum port_learn_mode mode; + + /* Last keyword should tell us the learn mode */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_auto) + mode = PORT_LEARN_AUTO; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + mode = PORT_LEARN_NONE; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_learn_mode_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_learn_mode_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -817,6 +956,8 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_show = &vsc9953_port_config_key_func, .port_stats = &vsc9953_port_stats_key_func, .port_stats_clear = &vsc9953_port_stats_clear_key_func, + .port_learn = &vsc9953_learn_set_key_func, + .port_learn_show = &vsc9953_learn_show_key_func, }; #endif /* CONFIG_CMD_ETHSW */ diff --git a/include/ethsw.h b/include/ethsw.h index 8f1c4145a18..6d2f0de61ec 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -22,6 +22,8 @@ enum ethsw_keyword_id { ethsw_id_disable, ethsw_id_statistics, ethsw_id_clear, + ethsw_id_learning, + ethsw_id_auto, ethsw_id_count, /* keep last */ }; @@ -45,6 +47,8 @@ struct ethsw_command_func { int (*port_show)(struct ethsw_command_def *parsed_cmd); int (*port_stats)(struct ethsw_command_def *parsed_cmd); int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd); + int (*port_learn)(struct ethsw_command_def *parsed_cmd); + int (*port_learn_show)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/vsc9953.h b/include/vsc9953.h index 83c4c89d62f..49215e6cc18 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -105,6 +105,12 @@ #define VSC9953_VLAN_CMD_WRITE 0x00000002 #define VSC9953_VLAN_CMD_INIT 0x00000003 +/* Macros for vsc9953_ana_port.port_cfg register */ +#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 +#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 +#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 +#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 + /* Macros for vsc9953_qsys_sys.switch_port_mode register */ #define VSC9953_PORT_ENA 0x00002000 -- cgit v1.3.1 From 0118e83ba4e1811515dc944a826758cad8a394b7 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 9 Sep 2015 18:00:51 +0300 Subject: common/env_flags.c: Add function to validate a MAC address The code that checks if a string has the format of a MAC address has been moved to a separate function called eth_validate_ethaddr_str(). This has been done to allow other components (such as vsc9953 driver) to validate a MAC address. Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/env_flags.c | 40 +++++++++++++++++++++++++++------------- include/env_flags.h | 7 +++++++ 2 files changed, 34 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/common/env_flags.c b/common/env_flags.c index 5189f5b2ddd..e682d851789 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -187,6 +187,31 @@ static void skip_num(int hex, const char *value, const char **end, *end = value; } +#ifdef CONFIG_CMD_NET +int eth_validate_ethaddr_str(const char *addr) +{ + const char *end; + const char *cur; + int i; + + cur = addr; + for (i = 0; i < 6; i++) { + skip_num(1, cur, &end, 2); + if (cur == end) + return -1; + if (cur + 2 == end && is_hex_prefix(cur)) + return -1; + if (i != 5 && *end != ':') + return -1; + if (i == 5 && *end != '\0') + return -1; + cur = end + 1; + } + + return 0; +} +#endif + /* * Based on the declared type enum, validate that the value string complies * with that format @@ -239,19 +264,8 @@ static int _env_flags_validate_type(const char *value, } break; case env_flags_vartype_macaddr: - cur = value; - for (i = 0; i < 6; i++) { - skip_num(1, cur, &end, 2); - if (cur == end) - return -1; - if (cur + 2 == end && is_hex_prefix(cur)) - return -1; - if (i != 5 && *end != ':') - return -1; - if (i == 5 && *end != '\0') - return -1; - cur = end + 1; - } + if (eth_validate_ethaddr_str(value)) + return -1; break; #endif case env_flags_vartype_end: diff --git a/include/env_flags.h b/include/env_flags.h index 2d2de88fc04..8823fb9602e 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -109,6 +109,13 @@ enum env_flags_varaccess env_flags_parse_varaccess(const char *flags); */ enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags); +#ifdef CONFIG_CMD_NET +/* + * Check if a string has the format of an Ethernet MAC address + */ +int eth_validate_ethaddr_str(const char *addr); +#endif + #ifdef USE_HOSTCC /* * Look up the type of a variable directly from the .flags var. -- cgit v1.3.1 From 22449858f8eae3f03399f76b4a982dd2f0d4df00 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 9 Sep 2015 18:00:52 +0300 Subject: drivers/net/vsc9953: Add commands to manipulate the FDB for VSC9953 The new command: ethsw [port ] [vlan ] fdb { [help] | show | flush | { add | del } } Can be used to add and delete FDB entries. Also, the command can be used to show entries from the FDB tables. When used with [port ] and [vlan ], only the matching the FDB entries can be seen or flushed. The command has also been added to the generic ethsw parser from cmd_ethsw.c. Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/cmd_ethsw.c | 178 +++++++++++++++++++ drivers/net/vsc9953.c | 472 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 15 ++ include/vsc9953.h | 28 +++ 4 files changed, 693 insertions(+) (limited to 'include') diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c index c1c33d10482..9ba680a9b90 100644 --- a/common/cmd_ethsw.c +++ b/common/cmd_ethsw.c @@ -9,6 +9,7 @@ #include #include #include +#include #include static const char *ethsw_name; @@ -34,6 +35,18 @@ static int ethsw_learn_help_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +#define ETHSW_FDB_HELP "ethsw [port ] [vlan ] fdb " \ +"{ [help] | show | flush | { add | del } } " \ +"- Add/delete a mac entry in FDB; use show to see FDB entries; " \ +"if vlan is missing, VID 1 will be used" + +static int ethsw_fdb_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_FDB_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -130,6 +143,59 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, port_learn), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_fdb, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_fdb_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_fdb, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_fdb_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_fdb, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + fdb_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_fdb, + ethsw_id_flush, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + fdb_flush), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_fdb, + ethsw_id_add, + ethsw_id_add_del_mac, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + fdb_entry_add), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_fdb, + ethsw_id_del, + ethsw_id_add_del_mac, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + fdb_entry_del), + .keyword_function = NULL, }, }; @@ -142,6 +208,20 @@ struct keywords_optional { ethsw_id_port_no, ethsw_id_key_end, }, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_vlan_no, + ethsw_id_key_end, + }, + }, { + .cmd_keyword = { + ethsw_id_port, + ethsw_id_port_no, + ethsw_id_vlan, + ethsw_id_vlan_no, + ethsw_id_key_end, + }, }, }; @@ -151,6 +231,12 @@ static int keyword_match_gen(enum ethsw_keyword_id key_id, int argc, char static int keyword_match_port(enum ethsw_keyword_id key_id, int argc, char *const argv[], int *argc_nr, struct ethsw_command_def *parsed_cmd); +static int keyword_match_vlan(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd); +static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd); /* * Define properties for each keyword; @@ -188,6 +274,21 @@ struct keyword_def { }, { .keyword_name = "auto", .match = &keyword_match_gen, + }, { + .keyword_name = "vlan", + .match = &keyword_match_vlan, + }, { + .keyword_name = "fdb", + .match = &keyword_match_gen, + }, { + .keyword_name = "add", + .match = &keyword_match_mac_addr, + }, { + .keyword_name = "del", + .match = &keyword_match_mac_addr, + }, { + .keyword_name = "flush", + .match = &keyword_match_gen, }, }; @@ -259,6 +360,78 @@ static int keyword_match_port(enum ethsw_keyword_id key_id, int argc, return 0; } +/* Function used to match the command's vlan */ +static int keyword_match_vlan(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd) +{ + unsigned long val; + int aux; + + if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd)) + return 0; + + if (*argc_nr + 1 >= argc) + return 0; + + if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) { + parsed_cmd->vid = val; + (*argc_nr)++; + parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_vlan_no; + return 1; + } + + aux = *argc_nr + 1; + + if (keyword_match_gen(ethsw_id_add, argc, argv, &aux, parsed_cmd)) + parsed_cmd->cmd_to_keywords[*argc_nr + 1] = ethsw_id_add; + else if (keyword_match_gen(ethsw_id_del, argc, argv, &aux, parsed_cmd)) + parsed_cmd->cmd_to_keywords[*argc_nr + 1] = ethsw_id_del; + else + return 0; + + if (*argc_nr + 2 >= argc) + return 0; + + if (strict_strtoul(argv[*argc_nr + 2], 10, &val) != -EINVAL) { + parsed_cmd->vid = val; + (*argc_nr) += 2; + parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_add_del_no; + return 1; + } + + return 0; +} + +/* Function used to match the command's MAC address */ +static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd) +{ + if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd)) + return 0; + + if ((*argc_nr + 1 >= argc) || + !is_broadcast_ethaddr(parsed_cmd->ethaddr)) + return 1; + + if (eth_validate_ethaddr_str(argv[*argc_nr + 1])) { + printf("Invalid MAC address: %s\n", argv[*argc_nr + 1]); + return 0; + } + + eth_parse_enetaddr(argv[*argc_nr + 1], parsed_cmd->ethaddr); + + if (is_broadcast_ethaddr(parsed_cmd->ethaddr)) { + memset(parsed_cmd->ethaddr, 0xFF, sizeof(parsed_cmd->ethaddr)); + return 0; + } + + parsed_cmd->cmd_to_keywords[*argc_nr + 1] = ethsw_id_add_del_mac; + + return 1; +} + /* Finds optional keywords and modifies *argc_va to skip them */ static void cmd_keywords_opt_check(const struct ethsw_command_def *parsed_cmd, int *argc_val) @@ -416,7 +589,11 @@ static void command_def_init(struct ethsw_command_def *parsed_cmd) parsed_cmd->cmd_to_keywords[i] = ethsw_id_key_end; parsed_cmd->port = ETHSW_CMD_PORT_ALL; + parsed_cmd->vid = ETHSW_CMD_VLAN_ALL; parsed_cmd->cmd_function = NULL; + + /* We initialize the MAC address with the Broadcast address */ + memset(parsed_cmd->ethaddr, 0xff, sizeof(parsed_cmd->ethaddr)); } /* function to interpret commands starting with "ethsw " */ @@ -446,4 +623,5 @@ U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, ETHSW_PORT_CONF_HELP"\n" ETHSW_PORT_STATS_HELP"\n" ETHSW_LEARN_HELP"\n" + ETHSW_FDB_HELP"\n" ); diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 21b14e6a190..071906c1fbe 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -783,6 +783,389 @@ static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode) return 0; } +/* wait for FDB to become available */ +static int vsc9953_mac_table_poll_idle(void) +{ + struct vsc9953_analyzer *l2ana_reg; + u32 timeout; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + timeout = 50000; + while (((in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_MASK) != + VSC9953_MAC_CMD_IDLE) && --timeout) + udelay(1); + + return timeout ? 0 : -EBUSY; +} + +/* enum describing available commands for the MAC table */ +enum mac_table_cmd { + MAC_TABLE_READ, + MAC_TABLE_LOOKUP, + MAC_TABLE_WRITE, + MAC_TABLE_LEARN, + MAC_TABLE_FORGET, + MAC_TABLE_GET_NEXT, + MAC_TABLE_AGE, +}; + +/* Issues a command to the FDB table */ +static int vsc9953_mac_table_cmd(enum mac_table_cmd cmd) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (cmd) { + case MAC_TABLE_READ: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | VSC9953_MAC_CMD_VALID, + VSC9953_MAC_CMD_READ); + break; + case MAC_TABLE_LOOKUP: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK, VSC9953_MAC_CMD_READ | + VSC9953_MAC_CMD_VALID); + break; + case MAC_TABLE_WRITE: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_WRITE | + VSC9953_MAC_ENTRYTYPE_LOCKED); + break; + case MAC_TABLE_LEARN: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_LEARN | + VSC9953_MAC_ENTRYTYPE_LOCKED | + VSC9953_MAC_CMD_VALID); + break; + case MAC_TABLE_FORGET: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_FORGET); + break; + case MAC_TABLE_GET_NEXT: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_NEXT); + break; + case MAC_TABLE_AGE: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_AGE); + break; + default: + printf("Unknown MAC table command\n"); + } + + if (vsc9953_mac_table_poll_idle() < 0) { + debug("MAC table timeout\n"); + return -1; + } + + return 0; +} + +/* show the FDB entries that correspond to a port and a VLAN */ +static void vsc9953_mac_table_show(int port_no, int vid) +{ + int rc[VSC9953_MAX_PORTS]; + enum port_learn_mode mode[VSC9953_MAX_PORTS]; + int i; + u32 val; + u32 vlan; + u32 mach; + u32 macl; + u32 dest_indx; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* disable auto learning */ + if (port_no == ETHSW_CMD_PORT_ALL) { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); + } + } else { + rc[port_no] = vsc9953_port_learn_mode_get(port_no, + &mode[port_no]); + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); + } + + /* write port and vid to get selected FDB entries */ + val = in_le32(&l2ana_reg->ana.anag_efil); + if (port_no != ETHSW_CMD_PORT_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, + port_no) | VSC9953_AGE_PORT_EN; + } + if (vid != ETHSW_CMD_VLAN_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, + vid) | VSC9953_AGE_VID_EN; + } + out_le32(&l2ana_reg->ana.anag_efil, val); + + /* set MAC and VLAN to 0 to look from beginning */ + clrbits_le32(&l2ana_reg->ana_tables.mach_data, + VSC9953_MAC_VID_MASK | VSC9953_MAC_MACH_MASK); + out_le32(&l2ana_reg->ana_tables.macl_data, 0); + + /* get entries */ + printf("%10s %17s %5s %4s\n", "EntryType", "MAC", "PORT", "VID"); + do { + if (vsc9953_mac_table_cmd(MAC_TABLE_GET_NEXT) < 0) { + debug("GET NEXT MAC table command failed\n"); + break; + } + + val = in_le32(&l2ana_reg->ana_tables.mac_access); + + /* get out when an invalid entry is found */ + if (!(val & VSC9953_MAC_CMD_VALID)) + break; + + switch (val & VSC9953_MAC_ENTRYTYPE_MASK) { + case VSC9953_MAC_ENTRYTYPE_NORMAL: + printf("%10s ", "Dynamic"); + break; + case VSC9953_MAC_ENTRYTYPE_LOCKED: + printf("%10s ", "Static"); + break; + case VSC9953_MAC_ENTRYTYPE_IPV4MCAST: + printf("%10s ", "IPv4 Mcast"); + break; + case VSC9953_MAC_ENTRYTYPE_IPV6MCAST: + printf("%10s ", "IPv6 Mcast"); + break; + default: + printf("%10s ", "Unknown"); + } + + dest_indx = bitfield_extract_by_mask(val, + VSC9953_MAC_DESTIDX_MASK); + + val = in_le32(&l2ana_reg->ana_tables.mach_data); + vlan = bitfield_extract_by_mask(val, VSC9953_MAC_VID_MASK); + mach = bitfield_extract_by_mask(val, VSC9953_MAC_MACH_MASK); + macl = in_le32(&l2ana_reg->ana_tables.macl_data); + + printf("%02x:%02x:%02x:%02x:%02x:%02x ", (mach >> 8) & 0xff, + mach & 0xff, (macl >> 24) & 0xff, (macl >> 16) & 0xff, + (macl >> 8) & 0xff, macl & 0xff); + printf("%5d ", dest_indx); + printf("%4d\n", vlan); + } while (1); + + /* set learning mode to previous value */ + if (port_no == ETHSW_CMD_PORT_ALL) { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, mode[i]); + } + } else { + /* If administrative down, skip */ + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, mode[port_no]); + } + + /* reset FDB port and VLAN FDB selection */ + clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | + VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | + VSC9953_AGE_VID_MASK); +} + +/* Add a static FDB entry */ +static int vsc9953_mac_table_add(u8 port_no, uchar mac[6], int vid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + /* set on which port is the MAC address added */ + val = in_le32(&l2ana_reg->ana_tables.mac_access); + val = bitfield_replace_by_mask(val, VSC9953_MAC_DESTIDX_MASK, port_no); + out_le32(&l2ana_reg->ana_tables.mac_access, val); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LEARN) < 0) + return -1; + + /* check if the MAC address was indeed added */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_READ) < 0) + return -1; + + val = in_le32(&l2ana_reg->ana_tables.mac_access); + + if ((port_no != bitfield_extract_by_mask(val, + VSC9953_MAC_DESTIDX_MASK))) { + printf("Failed to add MAC address\n"); + return -1; + } + return 0; +} + +/* Delete a FDB entry */ +static int vsc9953_mac_table_del(uchar mac[6], u16 vid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* check first if MAC entry is present */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { + debug("Lookup in the MAC table failed\n"); + return -1; + } + + if (!(in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_VALID)) { + printf("The MAC address: %02x:%02x:%02x:%02x:%02x:%02x ", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + printf("VLAN: %d does not exist.\n", vid); + return -1; + } + + /* FDB entry found, proceed to delete */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | + (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_FORGET) < 0) + return -1; + + /* check if the MAC entry is still in FDB */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | + (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { + debug("Lookup in the MAC table failed\n"); + return -1; + } + if (in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_VALID) { + printf("Failed to delete MAC address\n"); + return -1; + } + + return 0; +} + +/* age the unlocked entries in FDB */ +static void vsc9953_mac_table_age(int port_no, int vid) +{ + int rc[VSC9953_MAX_PORTS]; + enum port_learn_mode mode[VSC9953_MAX_PORTS]; + u32 val; + int i; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* set port and VID for selective aging */ + val = in_le32(&l2ana_reg->ana.anag_efil); + if (port_no != ETHSW_CMD_PORT_ALL) { + /* disable auto learning */ + rc[port_no] = vsc9953_port_learn_mode_get(port_no, + &mode[port_no]); + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); + + val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, + port_no) | VSC9953_AGE_PORT_EN; + } else { + /* disable auto learning on all ports */ + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); + } + } + + if (vid != ETHSW_CMD_VLAN_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, vid) | + VSC9953_AGE_VID_EN; + } + out_le32(&l2ana_reg->ana.anag_efil, val); + + /* age the dynamic FDB entries */ + vsc9953_mac_table_cmd(MAC_TABLE_AGE); + + /* clear previously set port and VID */ + clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | + VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | + VSC9953_AGE_VID_MASK); + + if (port_no != ETHSW_CMD_PORT_ALL) { + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, mode[port_no]); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, mode[i]); + } + } +} + +/* Delete all the dynamic FDB entries */ +static void vsc9953_mac_table_flush(int port, int vid) +{ + vsc9953_mac_table_age(port, vid); + vsc9953_mac_table_age(port, vid); +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -949,6 +1332,91 @@ static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_fdb_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && + !VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && + !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + vsc9953_mac_table_show(parsed_cmd->port, parsed_cmd->vid); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_flush_key_func(struct ethsw_command_def *parsed_cmd) +{ + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && + !VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && + !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + vsc9953_mac_table_flush(parsed_cmd->port, parsed_cmd->vid); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_entry_add_key_func(struct ethsw_command_def *parsed_cmd) +{ + int vid; + + /* a port number must be present */ + if (parsed_cmd->port == ETHSW_CMD_PORT_ALL) { + printf("Please specify a port\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + /* Use VLAN 1 if VID is not set */ + vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); + + if (!VSC9953_VLAN_CHECK(vid)) { + printf("Invalid VID number: %d\n", vid); + return CMD_RET_FAILURE; + } + + if (vsc9953_mac_table_add(parsed_cmd->port, parsed_cmd->ethaddr, vid)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd) +{ + int vid; + + /* Use VLAN 1 if VID is not set */ + vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); + + if (!VSC9953_VLAN_CHECK(vid)) { + printf("Invalid VID number: %d\n", vid); + return CMD_RET_FAILURE; + } + + if (vsc9953_mac_table_del(parsed_cmd->ethaddr, vid)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -958,6 +1426,10 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_stats_clear = &vsc9953_port_stats_clear_key_func, .port_learn = &vsc9953_learn_set_key_func, .port_learn_show = &vsc9953_learn_show_key_func, + .fdb_show = &vsc9953_fdb_show_key_func, + .fdb_flush = &vsc9953_fdb_flush_key_func, + .fdb_entry_add = &vsc9953_fdb_entry_add_key_func, + .fdb_entry_del = &vsc9953_fdb_entry_del_key_func, }; #endif /* CONFIG_CMD_ETHSW */ diff --git a/include/ethsw.h b/include/ethsw.h index 6d2f0de61ec..515903164b8 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -11,6 +11,7 @@ #define ETHSW_MAX_CMD_PARAMS 20 #define ETHSW_CMD_PORT_ALL -1 +#define ETHSW_CMD_VLAN_ALL -1 /* IDs used to track keywords in a command */ enum ethsw_keyword_id { @@ -24,11 +25,19 @@ enum ethsw_keyword_id { ethsw_id_clear, ethsw_id_learning, ethsw_id_auto, + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_add, + ethsw_id_del, + ethsw_id_flush, ethsw_id_count, /* keep last */ }; enum ethsw_keyword_opt_id { ethsw_id_port_no = ethsw_id_count + 1, + ethsw_id_vlan_no, + ethsw_id_add_del_no, + ethsw_id_add_del_mac, ethsw_id_count_all, /* keep last */ }; @@ -36,6 +45,8 @@ struct ethsw_command_def { int cmd_to_keywords[ETHSW_MAX_CMD_PARAMS]; int cmd_keywords_nr; int port; + int vid; + uchar ethaddr[6]; int (*cmd_function)(struct ethsw_command_def *parsed_cmd); }; @@ -49,6 +60,10 @@ struct ethsw_command_func { int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd); int (*port_learn)(struct ethsw_command_def *parsed_cmd); int (*port_learn_show)(struct ethsw_command_def *parsed_cmd); + int (*fdb_show)(struct ethsw_command_def *parsed_cmd); + int (*fdb_flush)(struct ethsw_command_def *parsed_cmd); + int (*fdb_entry_add)(struct ethsw_command_def *parsed_cmd); + int (*fdb_entry_del)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/vsc9953.h b/include/vsc9953.h index 49215e6cc18..df1c709523d 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -86,6 +86,25 @@ #define VSC9953_VCAP_MV_CFG 0x0000ffff #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 +/* Macros for register vsc9953_ana_ana_tables.mac_access register */ +#define VSC9953_MAC_CMD_IDLE 0x00000000 +#define VSC9953_MAC_CMD_LEARN 0x00000001 +#define VSC9953_MAC_CMD_FORGET 0x00000002 +#define VSC9953_MAC_CMD_AGE 0x00000003 +#define VSC9953_MAC_CMD_NEXT 0x00000004 +#define VSC9953_MAC_CMD_READ 0x00000006 +#define VSC9953_MAC_CMD_WRITE 0x00000007 +#define VSC9953_MAC_CMD_MASK 0x00000007 +#define VSC9953_MAC_CMD_VALID 0x00000800 +#define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 +#define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 +#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 +#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 +#define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 +#define VSC9953_MAC_DESTIDX_MASK 0x000001f8 +#define VSC9953_MAC_VID_MASK 0x1fff0000 +#define VSC9953_MAC_MACH_MASK 0x0000ffff + /* Macros for vsc9953_ana_port.vlan_cfg register */ #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 @@ -124,6 +143,15 @@ #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 #define VSC9953_TAG_CFG_ALL 0x00000180 +/* Macros for vsc9953_ana_ana.anag_efil register */ +#define VSC9953_AGE_PORT_EN 0x00080000 +#define VSC9953_AGE_PORT_MASK 0x0007c000 +#define VSC9953_AGE_VID_EN 0x00002000 +#define VSC9953_AGE_VID_MASK 0x00001fff + +/* Macros for vsc9953_ana_ana_tables.mach_data register */ +#define VSC9953_MACHDATA_VID_MASK 0x1fff0000 + #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) -- cgit v1.3.1 From a2477924cd302cfae730ebefb431814eb99ad861 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:33 +0300 Subject: drivers/net/vsc9953: Add VLAN commands for VSC9953 The new added commands can be used to configure VLANs for a port on both ingress and egress. The new commands are: ethsw [port ] pvid { [help] | show | } - set/show PVID (ingress and egress VLAN tagging) for a port; ethsw [port ] vlan { [help] | show | add | del } - add a VLAN to a port (VLAN members); ethsw [port ] untagged { [help] | show | all | none | pvid } - set egress tagging mod for a port" ethsw [port ] egress tag { [help] | show | pvid | classified } - Configure VID source for egress tag. Tag's VID could be the frame's classified VID or the PVID of the port These commands have also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/cmd_ethsw.c | 270 ++++++++++++++++++++++++++++ drivers/net/vsc9953.c | 478 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 16 ++ include/vsc9953.h | 3 + 4 files changed, 767 insertions(+) (limited to 'include') diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c index 9ba680a9b90..1fa93effdbc 100644 --- a/common/cmd_ethsw.c +++ b/common/cmd_ethsw.c @@ -47,6 +47,51 @@ static int ethsw_fdb_help_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +#define ETHSW_PVID_HELP "ethsw [port ] " \ +"pvid { [help] | show | } " \ +"- set/show PVID (ingress and egress VLAN tagging) for a port" + +static int ethsw_pvid_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_PVID_HELP"\n"); + + return CMD_RET_SUCCESS; +} + +#define ETHSW_VLAN_HELP "ethsw [port ] vlan " \ +"{ [help] | show | add | del } " \ +"- add a VLAN to a port (VLAN members)" + +static int ethsw_vlan_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_VLAN_HELP"\n"); + + return CMD_RET_SUCCESS; +} + +#define ETHSW_PORT_UNTAG_HELP "ethsw [port ] untagged " \ +"{ [help] | show | all | none | pvid } " \ +" - set egress tagging mod for a port" + +static int ethsw_port_untag_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_PORT_UNTAG_HELP"\n"); + + return CMD_RET_SUCCESS; +} + +#define ETHSW_EGR_VLAN_TAG_HELP "ethsw [port ] egress tag " \ +"{ [help] | show | pvid | classified } " \ +"- Configure VID source for egress tag. " \ +"Tag's VID could be the frame's classified VID or the PVID of the port" + +static int ethsw_egr_tag_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_EGR_VLAN_TAG_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -196,6 +241,181 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, fdb_entry_del), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_pvid, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_pvid_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_pvid, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_pvid_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_pvid, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + pvid_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_pvid, + ethsw_id_pvid_no, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + pvid_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_vlan_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_vlan_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + vlan_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_add, + ethsw_id_add_del_no, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + vlan_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_del, + ethsw_id_add_del_no, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + vlan_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_untagged, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_port_untag_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_untagged, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_port_untag_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_untagged, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_untag_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_untagged, + ethsw_id_all, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_untag_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_untagged, + ethsw_id_none, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_untag_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_untagged, + ethsw_id_pvid, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_untag_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_egr_tag_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_egr_tag_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_egr_vlan_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_pvid, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_egr_vlan_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_classified, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_egr_vlan_set), + .keyword_function = NULL, }, }; @@ -234,6 +454,9 @@ static int keyword_match_port(enum ethsw_keyword_id key_id, int argc, static int keyword_match_vlan(enum ethsw_keyword_id key_id, int argc, char *const argv[], int *argc_nr, struct ethsw_command_def *parsed_cmd); +static int keyword_match_pvid(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd); static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc, char *const argv[], int *argc_nr, struct ethsw_command_def *parsed_cmd); @@ -289,6 +512,27 @@ struct keyword_def { }, { .keyword_name = "flush", .match = &keyword_match_gen, + }, { + .keyword_name = "pvid", + .match = &keyword_match_pvid, + }, { + .keyword_name = "untagged", + .match = &keyword_match_gen, + }, { + .keyword_name = "all", + .match = &keyword_match_gen, + }, { + .keyword_name = "none", + .match = &keyword_match_gen, + }, { + .keyword_name = "egress", + .match = &keyword_match_gen, + }, { + .keyword_name = "tag", + .match = &keyword_match_gen, + }, { + .keyword_name = "classified", + .match = &keyword_match_gen, }, }; @@ -403,6 +647,28 @@ static int keyword_match_vlan(enum ethsw_keyword_id key_id, int argc, return 0; } +/* Function used to match the command's pvid */ +static int keyword_match_pvid(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd) +{ + unsigned long val; + + if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd)) + return 0; + + if (*argc_nr + 1 >= argc) + return 1; + + if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) { + parsed_cmd->vid = val; + (*argc_nr)++; + parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_pvid_no; + } + + return 1; +} + /* Function used to match the command's MAC address */ static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc, char *const argv[], int *argc_nr, @@ -624,4 +890,8 @@ U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, ETHSW_PORT_STATS_HELP"\n" ETHSW_LEARN_HELP"\n" ETHSW_FDB_HELP"\n" + ETHSW_PVID_HELP"\n" + ETHSW_VLAN_HELP"\n" + ETHSW_PORT_UNTAG_HELP"\n" + ETHSW_EGR_VLAN_TAG_HELP"\n" ); diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 071906c1fbe..c5c0e5c60fe 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -196,6 +196,100 @@ static int vsc9953_vlan_table_poll_idle(void) return timeout ? 0 : -EBUSY; } +#ifdef CONFIG_CMD_ETHSW +/* Add/remove a port to/from a VLAN */ +static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + val = in_le32(&l2ana_reg->ana_tables.vlan_access); + if (!add) { + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE) & + ~(bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, + (1 << port_no))); + ; + } else { + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE) | + bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, + (1 << port_no)); + } + out_le32(&l2ana_reg->ana_tables.vlan_access, val); + + /* wait for VLAN table command to flush */ + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } +} + +/* show VLAN membership for a port */ +static void vsc9953_vlan_membership_show(int port_no) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + u32 vid; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + printf("Port %d VLAN membership: ", port_no); + + for (vid = 0; vid < VSC9953_MAX_VLAN; vid++) { + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, + vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_access); + + if (bitfield_extract_by_mask(val, VSC9953_VLAN_PORT_MASK) & + (1 << port_no)) + printf("%d ", vid); + } + printf("\n"); +} +#endif + /* vlan table set/clear all membership of vid */ static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) { @@ -233,6 +327,30 @@ static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) (set_member ? VSC9953_VLAN_PORT_MASK : 0)); } +#ifdef CONFIG_CMD_ETHSW +/* Get PVID of a VSC9953 port */ +static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (vsc9953_l2sw.port[port_nr].enabled) { + printf("Port %d is administrative down\n", port_nr); + return -1; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* Get ingress PVID */ + val = in_le32(&l2ana_reg->port[port_nr].vlan_cfg); + *pvid = bitfield_extract_by_mask(val, VSC9953_VLAN_CFG_VID_MASK); + + return 0; +} +#endif + /* Set PVID for a VSC9953 port */ static void vsc9953_port_vlan_pvid_set(int port_no, int pvid) { @@ -359,6 +477,75 @@ enum egress_untag_mode { EGRESS_UNTAG_NONE, }; +#ifdef CONFIG_CMD_ETHSW +/* Get egress tagging configuration for a VSC9953 port */ +static int vsc9953_port_vlan_egr_untag_get(int port_no, + enum egress_untag_mode *mode) +{ + u32 val; + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return -1; + } + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); + + switch (val & VSC9953_TAG_CFG_MASK) { + case VSC9953_TAG_CFG_NONE: + *mode = EGRESS_UNTAG_ALL; + return 0; + case VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO: + *mode = EGRESS_UNTAG_PVID_AND_ZERO; + return 0; + case VSC9953_TAG_CFG_ALL_BUT_ZERO: + *mode = EGRESS_UNTAG_ZERO; + return 0; + case VSC9953_TAG_CFG_ALL: + *mode = EGRESS_UNTAG_NONE; + return 0; + default: + printf("Unknown egress tagging configuration for port %d\n", + port_no); + return -1; + } +} + +/* Show egress tagging configuration for a VSC9953 port */ +static void vsc9953_port_vlan_egr_untag_show(int port_no) +{ + enum egress_untag_mode mode; + + if (vsc9953_port_vlan_egr_untag_get(port_no, &mode)) { + printf("%7d\t%17s\n", port_no, "-"); + return; + } + + printf("%7d\t", port_no); + switch (mode) { + case EGRESS_UNTAG_ALL: + printf("%17s\n", "all"); + break; + case EGRESS_UNTAG_NONE: + printf("%17s\n", "none"); + break; + case EGRESS_UNTAG_PVID_AND_ZERO: + printf("%17s\n", "PVID and 0"); + break; + case EGRESS_UNTAG_ZERO: + printf("%17s\n", "0"); + break; + default: + printf("%17s\n", "-"); + } +} +#endif + static void vsc9953_port_vlan_egr_untag_set(int port_no, enum egress_untag_mode mode) { @@ -1166,6 +1353,51 @@ static void vsc9953_mac_table_flush(int port, int vid) vsc9953_mac_table_age(port, vid); } +enum egress_vlan_tag { + EGR_TAG_CLASS = 0, + EGR_TAG_PVID, +}; + +/* Set egress tag mode for a VSC9953 port */ +static void vsc9953_port_vlan_egress_tag_set(int port_no, + enum egress_vlan_tag mode) +{ + struct vsc9953_rew_reg *l2rew_reg; + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + switch (mode) { + case EGR_TAG_CLASS: + clrbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_VID_PVID); + break; + case EGR_TAG_PVID: + setbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_VID_PVID); + break; + default: + printf("Unknown egress VLAN tag mode for port %d\n", port_no); + } +} + +/* Get egress tag mode for a VSC9953 port */ +static void vsc9953_port_vlan_egress_tag_get(int port_no, + enum egress_vlan_tag *mode) +{ + u32 val; + struct vsc9953_rew_reg *l2rew_reg; + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); + if (val & VSC9953_TAG_VID_PVID) + *mode = EGR_TAG_PVID; + else + *mode = EGR_TAG_CLASS; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -1417,6 +1649,244 @@ static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_pvid_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int pvid; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (vsc9953_port_vlan_pvid_get(parsed_cmd->port, &pvid)) + return CMD_RET_FAILURE; + printf("%7s %7s\n", "Port", "PVID"); + printf("%7d %7d\n", parsed_cmd->port, pvid); + } else { + printf("%7s %7s\n", "Port", "PVID"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_vlan_pvid_get(i, &pvid)) + continue; + printf("%7d %7d\n", i, pvid); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_pvid_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + /* PVID number should be set in parsed_cmd->vid */ + if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { + printf("Please set a pvid value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_pvid_set(parsed_cmd->port, parsed_cmd->vid); + } else { + vsc9953_port_all_vlan_pvid_set(parsed_cmd->vid); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_vlan_membership_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_vlan_membership_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int add; + + /* VLAN should be set in parsed_cmd->vid */ + if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { + printf("Please set a vlan value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + /* keywords add/delete should be the last but one in array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == + ethsw_id_add) + add = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == + ethsw_id_del) + add = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_vlan_table_membership_set(parsed_cmd->vid, + parsed_cmd->port, add); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_vlan_table_membership_set(parsed_cmd->vid, i, + add); + } + + return CMD_RET_SUCCESS; +} +static int vsc9953_port_untag_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + + printf("%7s\t%17s\n", "Port", "Untag"); + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egr_untag_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_untag_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_untag_mode mode; + + /* keywords for the untagged mode are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_all) + mode = EGRESS_UNTAG_ALL; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_none) + mode = EGRESS_UNTAG_NONE; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_pvid) + mode = EGRESS_UNTAG_PVID_AND_ZERO; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egr_untag_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_egr_vlan_tag_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_vlan_tag mode; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egress_tag_get(parsed_cmd->port, &mode); + printf("%7s\t%12s\n", "Port", "Egress VID"); + printf("%7d\t", parsed_cmd->port); + switch (mode) { + case EGR_TAG_CLASS: + printf("%12s\n", "classified"); + break; + case EGR_TAG_PVID: + printf("%12s\n", "pvid"); + break; + default: + printf("%12s\n", "-"); + } + } else { + printf("%7s\t%12s\n", "Port", "Egress VID"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + vsc9953_port_vlan_egress_tag_get(i, &mode); + switch (mode) { + case EGR_TAG_CLASS: + printf("%7d\t%12s\n", i, "classified"); + break; + case EGR_TAG_PVID: + printf("%7d\t%12s\n", i, "pvid"); + break; + default: + printf("%7d\t%12s\n", i, "-"); + } + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_egr_vlan_tag_set_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_vlan_tag mode; + + /* keywords for the egress vlan tag mode are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_pvid) + mode = EGR_TAG_PVID; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_classified) + mode = EGR_TAG_CLASS; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egress_tag_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egress_tag_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -1430,6 +1900,14 @@ static struct ethsw_command_func vsc9953_cmd_func = { .fdb_flush = &vsc9953_fdb_flush_key_func, .fdb_entry_add = &vsc9953_fdb_entry_add_key_func, .fdb_entry_del = &vsc9953_fdb_entry_del_key_func, + .pvid_show = &vsc9953_pvid_show_key_func, + .pvid_set = &vsc9953_pvid_set_key_func, + .vlan_show = &vsc9953_vlan_show_key_func, + .vlan_set = &vsc9953_vlan_set_key_func, + .port_untag_show = &vsc9953_port_untag_show_key_func, + .port_untag_set = &vsc9953_port_untag_set_key_func, + .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func, + .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, }; #endif /* CONFIG_CMD_ETHSW */ diff --git a/include/ethsw.h b/include/ethsw.h index 515903164b8..cc9708e9ac4 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -30,12 +30,20 @@ enum ethsw_keyword_id { ethsw_id_add, ethsw_id_del, ethsw_id_flush, + ethsw_id_pvid, + ethsw_id_untagged, + ethsw_id_all, + ethsw_id_none, + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_classified, ethsw_id_count, /* keep last */ }; enum ethsw_keyword_opt_id { ethsw_id_port_no = ethsw_id_count + 1, ethsw_id_vlan_no, + ethsw_id_pvid_no, ethsw_id_add_del_no, ethsw_id_add_del_mac, ethsw_id_count_all, /* keep last */ @@ -64,6 +72,14 @@ struct ethsw_command_func { int (*fdb_flush)(struct ethsw_command_def *parsed_cmd); int (*fdb_entry_add)(struct ethsw_command_def *parsed_cmd); int (*fdb_entry_del)(struct ethsw_command_def *parsed_cmd); + int (*pvid_show)(struct ethsw_command_def *parsed_cmd); + int (*pvid_set)(struct ethsw_command_def *parsed_cmd); + int (*vlan_show)(struct ethsw_command_def *parsed_cmd); + int (*vlan_set)(struct ethsw_command_def *parsed_cmd); + int (*port_untag_show)(struct ethsw_command_def *parsed_cmd); + int (*port_untag_set)(struct ethsw_command_def *parsed_cmd); + int (*port_egr_vlan_show)(struct ethsw_command_def *parsed_cmd); + int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/vsc9953.h b/include/vsc9953.h index df1c709523d..12b7acecad1 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -108,6 +108,8 @@ /* Macros for vsc9953_ana_port.vlan_cfg register */ #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 +#define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 +#define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff /* Macros for vsc9953_rew_port.port_vlan_cfg register */ @@ -142,6 +144,7 @@ #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 #define VSC9953_TAG_CFG_ALL 0x00000180 +#define VSC9953_TAG_VID_PVID 0x00000010 /* Macros for vsc9953_ana_ana.anag_efil register */ #define VSC9953_AGE_PORT_EN 0x00080000 -- cgit v1.3.1 From 21d214fcd0a12c75ebb9c675f0f07b8e69f6cb44 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:34 +0300 Subject: drivers/net/vsc9953: Add command for shared/private VLAN learning The command: ethsw vlan fdb { [help] | show | shared | private } - make VLAN learning shared or private" configures the FDB to share the FDB entries learned on multiple VLANs or to keep them separated. By default, the FBD uses private VLAN learning. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/cmd_ethsw.c | 65 +++++++++++++++++++++++++++++++++++ drivers/net/vsc9953.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 4 +++ include/vsc9953.h | 3 ++ 4 files changed, 167 insertions(+) (limited to 'include') diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c index 1fa93effdbc..8cc2a19fe17 100644 --- a/common/cmd_ethsw.c +++ b/common/cmd_ethsw.c @@ -92,6 +92,17 @@ static int ethsw_egr_tag_help_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +#define ETHSW_VLAN_FDB_HELP "ethsw vlan fdb " \ +"{ [help] | show | shared | private } " \ +"- make VLAN learning shared or private" + +static int ethsw_vlan_learn_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_VLAN_FDB_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -416,6 +427,53 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, port_egr_vlan_set), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_vlan_learn_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_vlan_learn_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + vlan_learn_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_shared, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + vlan_learn_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_private, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + vlan_learn_set), + .keyword_function = NULL, }, }; @@ -533,6 +591,12 @@ struct keyword_def { }, { .keyword_name = "classified", .match = &keyword_match_gen, + }, { + .keyword_name = "shared", + .match = &keyword_match_gen, + }, { + .keyword_name = "private", + .match = &keyword_match_gen, }, }; @@ -894,4 +958,5 @@ U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, ETHSW_VLAN_HELP"\n" ETHSW_PORT_UNTAG_HELP"\n" ETHSW_EGR_VLAN_TAG_HELP"\n" + ETHSW_VLAN_FDB_HELP"\n" ); diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index c5c0e5c60fe..f8f52334b9a 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -1398,6 +1398,55 @@ static void vsc9953_port_vlan_egress_tag_get(int port_no, *mode = EGR_TAG_CLASS; } +/* VSC9953 VLAN learning modes */ +enum vlan_learning_mode { + SHARED_VLAN_LEARNING, + PRIVATE_VLAN_LEARNING, +}; + +/* Set VLAN learning mode for VSC9953 */ +static void vsc9953_vlan_learning_set(enum vlan_learning_mode lrn_mode) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (lrn_mode) { + case SHARED_VLAN_LEARNING: + setbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); + break; + case PRIVATE_VLAN_LEARNING: + clrbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); + break; + default: + printf("Unknown VLAN learn mode\n"); + } +} + +/* Get VLAN learning mode for VSC9953 */ +static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana.agen_ctrl); + + if (!(val & VSC9953_FID_MASK_ALL)) { + *lrn_mode = PRIVATE_VLAN_LEARNING; + } else if ((val & VSC9953_FID_MASK_ALL) == VSC9953_FID_MASK_ALL) { + *lrn_mode = SHARED_VLAN_LEARNING; + } else { + printf("Unknown VLAN learning mode\n"); + return -EINVAL; + } + + return 0; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -1887,6 +1936,50 @@ static int vsc9953_egr_vlan_tag_set_key_func( return CMD_RET_SUCCESS; } +static int vsc9953_vlan_learn_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int rc; + enum vlan_learning_mode mode; + + rc = vsc9953_vlan_learning_get(&mode); + if (rc) + return CMD_RET_FAILURE; + + switch (mode) { + case SHARED_VLAN_LEARNING: + printf("VLAN learning mode: shared\n"); + break; + case PRIVATE_VLAN_LEARNING: + printf("VLAN learning mode: private\n"); + break; + default: + printf("Unknown VLAN learning mode\n"); + rc = CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + enum vlan_learning_mode mode; + + /* keywords for shared/private are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_shared) + mode = SHARED_VLAN_LEARNING; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_private) + mode = PRIVATE_VLAN_LEARNING; + else + return CMD_RET_USAGE; + + vsc9953_vlan_learning_set(mode); + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -1908,6 +2001,8 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_untag_set = &vsc9953_port_untag_set_key_func, .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func, .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, + .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, + .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, }; #endif /* CONFIG_CMD_ETHSW */ diff --git a/include/ethsw.h b/include/ethsw.h index cc9708e9ac4..18d2b26b4bd 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -37,6 +37,8 @@ enum ethsw_keyword_id { ethsw_id_egress, ethsw_id_tag, ethsw_id_classified, + ethsw_id_shared, + ethsw_id_private, ethsw_id_count, /* keep last */ }; @@ -80,6 +82,8 @@ struct ethsw_command_func { int (*port_untag_set)(struct ethsw_command_def *parsed_cmd); int (*port_egr_vlan_show)(struct ethsw_command_def *parsed_cmd); int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd); + int (*vlan_learn_show)(struct ethsw_command_def *parsed_cmd); + int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/vsc9953.h b/include/vsc9953.h index 12b7acecad1..24a22a39258 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -135,6 +135,9 @@ /* Macros for vsc9953_qsys_sys.switch_port_mode register */ #define VSC9953_PORT_ENA 0x00002000 +/* Macros for vsc9953_ana_ana.agen_ctrl register */ +#define VSC9953_FID_MASK_ALL 0x00fff000 + /* Macros for vsc9953_ana_ana.adv_learn register */ #define VSC9953_VLAN_CHK 0x00000400 -- cgit v1.3.1 From 5ed1bacd3402a3153c8306766ad099b2261ebe36 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:35 +0300 Subject: drivers/net/vsc9953: Add commands for VLAN ingress filtering The command: ethsw [port ] ingress filtering { [help] | show | enable | disable } - enable/disable VLAN ingress filtering on port can be used to enable/disable/show VLAN ingress filtering on a port. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- common/cmd_ethsw.c | 65 ++++++++++++++++++++++++++++++++++++++ drivers/net/vsc9953.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/ethsw.h | 4 +++ 3 files changed, 155 insertions(+) (limited to 'include') diff --git a/common/cmd_ethsw.c b/common/cmd_ethsw.c index 8cc2a19fe17..8e452e95be7 100644 --- a/common/cmd_ethsw.c +++ b/common/cmd_ethsw.c @@ -103,6 +103,17 @@ static int ethsw_vlan_learn_help_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +#define ETHSW_PORT_INGR_FLTR_HELP "ethsw [port ] ingress filtering" \ +" { [help] | show | enable | disable } " \ +"- enable/disable VLAN ingress filtering on port" + +static int ethsw_ingr_fltr_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_PORT_INGR_FLTR_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -474,6 +485,53 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, vlan_learn_set), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_ingr_fltr_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_ingr_fltr_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_ingr_filt_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_enable, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_ingr_filt_set), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_disable, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_ingr_filt_set), + .keyword_function = NULL, }, }; @@ -597,6 +655,12 @@ struct keyword_def { }, { .keyword_name = "private", .match = &keyword_match_gen, + }, { + .keyword_name = "ingress", + .match = &keyword_match_gen, + }, { + .keyword_name = "filtering", + .match = &keyword_match_gen, }, }; @@ -959,4 +1023,5 @@ U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, ETHSW_PORT_UNTAG_HELP"\n" ETHSW_EGR_VLAN_TAG_HELP"\n" ETHSW_VLAN_FDB_HELP"\n" + ETHSW_PORT_INGR_FLTR_HELP"\n" ); diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index f8f52334b9a..8be87a15b29 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -1447,6 +1447,33 @@ static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode) return 0; } +/* Enable/disable VLAN ingress filtering on a VSC9953 port */ +static void vsc9953_port_ingress_filtering_set(int port_no, int enabled) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enabled) + setbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); + else + clrbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); +} + +/* Return VLAN ingress filtering on a VSC9953 port */ +static int vsc9953_port_ingress_filtering_get(int port_no) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana.vlan_mask); + return !!(val & (1 << port_no)); +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -1980,6 +2007,63 @@ static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_ingr_fltr_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int enabled; + + printf("%7s\t%18s\n", "Port", "Ingress filtering"); + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + enabled = vsc9953_port_ingress_filtering_get(parsed_cmd->port); + printf("%7d\t%18s\n", parsed_cmd->port, enabled ? "enable" : + "disable"); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + enabled = vsc9953_port_ingress_filtering_get(i); + printf("%7d\t%18s\n", parsed_cmd->port, enabled ? + "enable" : + "disable"); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int enable; + + /* keywords for enabling/disabling ingress filtering + * are the last in the array + */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_enable) + enable = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + enable = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_ingress_filtering_set(parsed_cmd->port, enable); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_ingress_filtering_set(i, enable); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -2003,6 +2087,8 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, + .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func, + .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func }; #endif /* CONFIG_CMD_ETHSW */ diff --git a/include/ethsw.h b/include/ethsw.h index 18d2b26b4bd..2d3c12a39e6 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -39,6 +39,8 @@ enum ethsw_keyword_id { ethsw_id_classified, ethsw_id_shared, ethsw_id_private, + ethsw_id_ingress, + ethsw_id_filtering, ethsw_id_count, /* keep last */ }; @@ -84,6 +86,8 @@ struct ethsw_command_func { int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd); int (*vlan_learn_show)(struct ethsw_command_def *parsed_cmd); int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd); + int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd); + int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); -- cgit v1.3.1 From a857d5f835c53f7b66de61b19120ea1188e94999 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:36 +0300 Subject: drivers/net/vsc9953: Add GPL-2.0+ SPDX-License-Identifier Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 2 +- include/vsc9953.h | 11 +++-------- 2 files changed, 4 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 8be87a15b29..7595db1acbd 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * diff --git a/include/vsc9953.h b/include/vsc9953.h index 24a22a39258..cd5cfc76b07 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -1,14 +1,9 @@ /* - * vsc9953.h + * Copyright 2013, 2015 Freescale Semiconductor, Inc. * - * Driver for the Vitesse VSC9953 L2 Switch - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2013 Freescale Semiconductor, Inc. + * SPDX-License-Identifier: GPL-2.0+ * + * Driver for the Vitesse VSC9953 L2 Switch */ #ifndef _VSC9953_H_ -- cgit v1.3.1 From e1df080b0d8b1bf9ed3e6a01a647192b2c90c72a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 17 Sep 2015 17:30:29 +0200 Subject: arm: socfpga: Fix cache configuration By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache policy is selected. This leads to much better performance on the SoCFPGA. A quick network test shows this: Without this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 2.5 MiB/s With this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 7.6 MiB/s A performance improvement of factor ~3. Signed-off-by: Stefan Roese Cc: Dinh Nguyen Cc: Chin Liang See Cc: Pavel Machek Cc: Marek Vasut --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 38ae763653b..a2811bacd2c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -73,7 +73,6 @@ /* * Cache */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -- cgit v1.3.1 From 3cbc7b878ba6352bb0ae21213394844f3a9b3e9d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 22 Sep 2015 17:01:32 -0500 Subject: arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/Kconfig | 4 +- include/configs/socfpga_arria5.h | 97 -------------------------------- include/configs/socfpga_arria5_socdk.h | 97 ++++++++++++++++++++++++++++++++ include/configs/socfpga_cyclone5.h | 97 -------------------------------- include/configs/socfpga_cyclone5_socdk.h | 97 ++++++++++++++++++++++++++++++++ 5 files changed, 196 insertions(+), 196 deletions(-) delete mode 100644 include/configs/socfpga_arria5.h create mode 100644 include/configs/socfpga_arria5_socdk.h delete mode 100644 include/configs/socfpga_cyclone5.h create mode 100644 include/configs/socfpga_cyclone5_socdk.h (limited to 'include') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 089280a91d3..a413ea4d1b4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -50,8 +50,8 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h deleted file mode 100644 index 3193684798c..00000000000 --- a/include/configs/socfpga_arria5.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ -#define __CONFIG_SOCFPGA_ARRIA5_H__ - -#include - -/* U-Boot Commands */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION -#define CONFIG_FAT_WRITE -#define CONFIG_HW_WATCHDOG - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DFU -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_USB_MASS_STORAGE - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) - -/* PHY */ -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Altera" - -/* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_arria5 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h new file mode 100644 index 00000000000..3193684798c --- /dev/null +++ b/include/configs/socfpga_arria5_socdk.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ +#define __CONFIG_SOCFPGA_ARRIA5_H__ + +#include + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_arria5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h deleted file mode 100644 index 9e733e5c487..00000000000 --- a/include/configs/socfpga_cyclone5.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_H__ - -#include - -/* U-Boot Commands */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION -#define CONFIG_FAT_WRITE -#define CONFIG_HW_WATCHDOG - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DFU -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_USB_MASS_STORAGE - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) - -/* PHY */ -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Altera" - -/* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_cyclone5 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h new file mode 100644 index 00000000000..9e733e5c487 --- /dev/null +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_H__ + +#include + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_cyclone5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ -- cgit v1.3.1 From 68a3e32b722261d07cf7325ea86275bf4e3b8917 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 23 Sep 2015 15:38:01 -0500 Subject: arm: socfpga: Enable saveenv for SD/MMC Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen --- include/configs/socfpga_arria5_socdk.h | 4 ++++ include/configs/socfpga_common.h | 1 - include/configs/socfpga_cyclone5_socdk.h | 4 ++++ include/configs/socfpga_de0_nano_soc.h | 4 ++++ include/configs/socfpga_mcvevk.h | 2 ++ include/configs/socfpga_sockit.h | 4 ++++ 6 files changed, 18 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 3193684798c..b75b0a27fa9 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a2811bacd2c..cece0950e29 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -281,7 +281,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 4096 /* diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 9e733e5c487..fa67b25a792 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 2508d037e33..191e1f7a43f 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -55,6 +55,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index c5b4b4ca9d3..ed9b5cce6ac 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,6 +43,8 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_ENV_IS_NOWHERE + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 747e988ac9f..6c71ef4e23f 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -- cgit v1.3.1 From aad604aef36e90bd42b4ce1969960f3427be4a7a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 24 Sep 2015 09:06:06 +0200 Subject: arm: socfpga: Enable env support on MCV Enable support for env in eMMC on MCV SoM. Signed-off-by: Marek Vasut --- include/configs/socfpga_mcvevk.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index ed9b5cce6ac..65816a05cfc 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,7 +43,11 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_ENV_IS_NOWHERE +/* Environment is in MMC */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ #ifdef CONFIG_CMD_USB -- cgit v1.3.1 From 60dba18801a5a7792c8469f42aef1d189a7d863d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 15 Sep 2015 14:05:07 +0800 Subject: imx: mx7dsabresd: drop code for CONFIG_CMD_BMODE We use outer pmic reset and drop internal reset signal, bmode will not work as expected, so drop boot mode code for 7dsabresd board. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Adrian Alonso --- board/freescale/mx7dsabresd/mx7dsabresd.c | 14 -------------- include/configs/mx7dsabresd.h | 2 -- 2 files changed, 16 deletions(-) (limited to 'include') diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index bb823f5342b..ee9890b5990 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -421,15 +420,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, - {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - #ifdef CONFIG_POWER #define I2C_PMIC 0 int power_init_board(void) @@ -464,10 +454,6 @@ int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - #ifdef CONFIG_ENV_IS_IN_MMC mmc_late_init(); #endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 2a736c458c9..ada5de8acaa 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -174,8 +174,6 @@ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_CMD_BMODE - /* USB Configs */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI -- cgit v1.3.1 From 9879842c6fdb64d95085ac66647ed77d7abfd439 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:45 +0900 Subject: ARM: uniphier: drop DCC micro support card support Historically (for compatibility with very old platforms), two different types of micro support cards have been used with the UniPhier SoC development boards. It has been painful to maintain both. Having one of them is enough. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- arch/arm/mach-uniphier/Kconfig | 23 ++----- arch/arm/mach-uniphier/Makefile | 3 +- arch/arm/mach-uniphier/include/mach/board.h | 6 +- arch/arm/mach-uniphier/ph1-ld4/Makefile | 3 +- arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c | 49 --------------- arch/arm/mach-uniphier/ph1-pro4/Makefile | 3 +- arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c | 42 ------------- arch/arm/mach-uniphier/ph1-sld3/Makefile | 3 +- arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c | 37 ----------- arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c | 57 ----------------- arch/arm/mach-uniphier/support_card.c | 87 +++----------------------- configs/ph1_ld4_defconfig | 2 +- configs/ph1_pro4_defconfig | 2 +- configs/ph1_sld3_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- include/configs/uniphier.h | 19 ++---- 16 files changed, 29 insertions(+), 311 deletions(-) delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c (limited to 'include') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 7b49ad3b490..28d574fbb80 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -26,29 +26,14 @@ config MACH_PH1_SLD8 endchoice -choice - prompt "UniPhier Support Card select" - optional - -config PFC_MICRO_SUPPORT_CARD - bool "Support card with PFC CPLD" - help - This option provides support for the expansion board with PFC - original address mapping. - - Say Y to use the on-board UART, Ether, LED devices. - -config DCC_MICRO_SUPPORT_CARD - bool "Support card with DCC CPLD" +config MICRO_SUPPORT_CARD + bool "Use Micro Support Card" help - This option provides support for the expansion board with DCC- - arranged address mapping that is compatible with legacy UniPhier - reference boards. + This option provides support for the expansion board, available + on some UniPhier reference boards. Say Y to use the on-board UART, Ether, LED devices. -endchoice - config CMD_PINMON bool "Enable boot mode pins monitor command" default y diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 103db6d7dc6..5f175575e86 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -29,8 +29,7 @@ endif obj-y += timer.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += support_card.o obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/ obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ diff --git a/arch/arm/mach-uniphier/include/mach/board.h b/arch/arm/mach-uniphier/include/mach/board.h index e3cba5befe2..c039d807f4d 100644 --- a/arch/arm/mach-uniphier/include/mach/board.h +++ b/arch/arm/mach-uniphier/include/mach/board.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2012-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,8 +7,7 @@ #ifndef ARCH_BOARD_H #define ARCH_BOARD_H -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \ - defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +#if defined(CONFIG_MICRO_SUPPORT_CARD) void support_card_reset(void); void support_card_init(void); void support_card_late_init(void); diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile index 0c198c65e77..4a2c944aeef 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += bcu_init.o pll_init.o early_clkrst_init.o \ pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o endif diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c deleted file mode 100644 index 5b5958be053..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - u32 tmp; - - /* system bus output enable */ - tmp = readl(PC0CTRL); - tmp &= 0xfffffcff; - writel(tmp, PC0CTRL); - - /* XECS1: sub/boot memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); - - /* XECS0: boot/sub memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); - - /* XECS3: peripherals */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); - - /* base address regsiters */ - writel(0x0000bc01, SBBASE0); - writel(0x0400bc01, SBBASE1); - writel(0x0800bf01, SBBASE3); - - /* enable access to sub memory when boot swap is on */ - if (boot_is_swapped()) - sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ - - sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile index afd9235e9b3..a52b5aa5565 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += pll_init.o early_clkrst_init.o \ pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o endif diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c deleted file mode 100644 index 877ba79f68d..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - /* XECS0: boot/sub memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); - - /* XECS1: sub/boot memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); - - /* XECS3: peripherals */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); - - writel(0x0000bc01, SBBASE0); /* boot memory */ - writel(0x0400bc01, SBBASE1); /* sub memory */ - writel(0x0800bf01, SBBASE3); /* peripherals */ - - /* enable access to sub memory when boot swap is on */ - if (boot_is_swapped()) - sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ - - sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ - writel(0x00000001, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/Makefile b/arch/arm/mach-uniphier/ph1-sld3/Makefile index aff5d640d6f..e3cb39fa50d 100644 --- a/arch/arm/mach-uniphier/ph1-sld3/Makefile +++ b/arch/arm/mach-uniphier/ph1-sld3/Makefile @@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \ early_pinctrl.o pll_spectrum.o umc_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o endif diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c deleted file mode 100644 index f5e24467ced..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - /* only address/data multiplex mode is supported */ - - /* XECS0 : boot/sub memory (boot swap = off/on) */ - writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00); - writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01); - writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02); - - /* XECS1 : sub/boot memory (boot swap = off/on) */ - writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); - - /* XECS2 : peripherals */ - writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20); - writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21); - writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22); - - /* base address regsiters */ - writel(0x0000bc01, SBBASE0); - writel(0x0400bc01, SBBASE1); - writel(0x0800bf01, SBBASE2); - - sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c deleted file mode 100644 index c2267c73eeb..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - u32 tmp; - - /* system bus output enable */ - tmp = readl(PC0CTRL); - tmp &= 0xfffffcff; - writel(tmp, PC0CTRL); - - /* - * SBCTRL0* does not need settings because PH1-sLD8 has no support for - * XECS0. The boot swap must be enabled to boot from the support card. - */ - - if (boot_is_swapped()) { - /* XECS1 : boot memory if boot swap is on */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); - } - - /* XECS4 : sub memory */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); - - /* XECS5 : peripherals */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); - - /* base address regsiters */ - writel(0x0000bc01, SBBASE0); /* boot memory */ - writel(0x0900bfff, SBBASE1); /* dummy */ - writel(0x0400bc01, SBBASE4); /* sub memory */ - writel(0x0800bf01, SBBASE5); /* peripherals */ - - sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ - sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ - - /* dummy read to assure write process */ - readl(SG_PINCTRL(0)); -} diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index ea85b20e979..4ca6ffea2dc 100644 --- a/arch/arm/mach-uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -8,11 +8,9 @@ #include #include -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) - -#define PFC_MICRO_SUPPORT_CARD_RESET \ +#define MICRO_SUPPORT_CARD_RESET \ ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034) -#define PFC_MICRO_SUPPORT_CARD_REVISION \ +#define MICRO_SUPPORT_CARD_REVISION \ ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0) /* * 0: reset deassert, 1: reset @@ -22,65 +20,22 @@ */ void support_card_reset_deassert(void) { - writel(0, PFC_MICRO_SUPPORT_CARD_RESET); + writel(0, MICRO_SUPPORT_CARD_RESET); } void support_card_reset(void) { - writel(3, PFC_MICRO_SUPPORT_CARD_RESET); + writel(3, MICRO_SUPPORT_CARD_RESET); } static int support_card_show_revision(void) { u32 revision; - revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION); - printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf); + revision = readl(MICRO_SUPPORT_CARD_REVISION); + printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf); return 0; } -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) - -#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300) -#define DCC_MICRO_SUPPORT_CARD_RESET_UART \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304) -#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308) -#define DCC_MICRO_SUPPORT_CARD_REVISION \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0) - -void support_card_reset_deassert(void) -{ - writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ - writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ - writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ -} - -void support_card_reset(void) -{ - writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ - writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ - writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ -} - -static int support_card_show_revision(void) -{ - u32 revision; - - revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION); - - if (revision >= 0x67) { - printf("(DCC CPLD version 3.%d.%d)\n", - revision >> 4, revision & 0xf); - return 0; - } else { - printf("(DCC CPLD unknown version)\n"); - return -1; - } -} -#endif int check_support_card(void) { @@ -146,28 +101,11 @@ static int mem_is_flash(const struct memory_bank *mem) return ret; } -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) - /* {address, size} */ -static const struct memory_bank memory_banks_boot_swap_off[] = { +/* {address, size} */ +static const struct memory_bank memory_banks[] = { {0x02000000, 0x01f00000}, }; -static const struct memory_bank memory_banks_boot_swap_on[] = { - {0x00000000, 0x01f00000}, -}; -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -static const struct memory_bank memory_banks_boot_swap_off[] = { - {0x04000000, 0x02000000}, -}; - -static const struct memory_bank memory_banks_boot_swap_on[] = { - {0x00000000, 0x02000000}, - {0x04000000, 0x02000000}, -}; -#endif - static const struct memory_bank *flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; @@ -187,13 +125,8 @@ static void detect_num_flash_banks(void) cfi_flash_num_flash_banks = 0; - if (boot_is_swapped()) { - memory_bank = memory_banks_boot_swap_on; - end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on); - } else { - memory_bank = memory_banks_boot_swap_off; - end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off); - } + memory_bank = memory_banks; + end = memory_bank + ARRAY_SIZE(memory_banks); for (; memory_bank < end; memory_bank++) { if (cfi_flash_num_flash_banks >= diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 13b124b661e..e9744a3483b 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_MACH_PH1_LD4=y -CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" CONFIG_HUSH_PARSER=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 0982d9141a3..1b3092dbe74 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" CONFIG_HUSH_PARSER=y diff --git a/configs/ph1_sld3_defconfig b/configs/ph1_sld3_defconfig index d49513251e3..df908e260b5 100644 --- a/configs/ph1_sld3_defconfig +++ b/configs/ph1_sld3_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_MACH_PH1_SLD3=y -CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref" CONFIG_HUSH_PARSER=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 584c41ab9f6..81515628578 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_MACH_PH1_SLD8=y -CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" CONFIG_HUSH_PARSER=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index d59564bafd0..7316046952e 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -62,19 +62,10 @@ /* * Support card address map */ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x03f00000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x08000000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) -#endif +#define CONFIG_SUPPORT_CARD_BASE 0x03f00000 +#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) +#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) +#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) #ifdef CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550 @@ -140,7 +131,7 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 /* serial console configuration */ #define CONFIG_BAUDRATE 115200 -- cgit v1.3.1 From d5ed8c5727f6985505ceb6e8640528e7e08e9670 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:47 +0900 Subject: ARM: uniphier: change the external bus address mapping In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces 0x00000000 - 0x0fffffff 0x40000000 - 0x4fffffff are both mapped to the external bus (also called system bus), so either was OK. In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is assigned for the serial NOR interface. Going forward, use the latter for the external bus. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | 12 ++++++------ arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 12 ++++++------ arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 12 ++++++------ arch/arm/mach-uniphier/support_card.c | 2 +- include/configs/uniphier.h | 7 ++++++- 5 files changed, 25 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c index 8e25792b501..4435a47e73c 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c @@ -30,18 +30,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c index 533739c364d..685f9c736c9 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c @@ -23,18 +23,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c index d66f89ea51f..bafab4b0e66 100644 --- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c @@ -24,18 +24,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index 4ca6ffea2dc..ef4576de432 100644 --- a/arch/arm/mach-uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -103,7 +103,7 @@ static int mem_is_flash(const struct memory_bank *mem) /* {address, size} */ static const struct memory_bank memory_banks[] = { - {0x02000000, 0x01f00000}, + {0x42000000, 0x01f00000}, }; static const struct memory_bank diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 7316046952e..45b39c075e5 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -62,7 +62,7 @@ /* * Support card address map */ -#define CONFIG_SUPPORT_CARD_BASE 0x03f00000 +#define CONFIG_SUPPORT_CARD_BASE 0x43f00000 #define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) #define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) #define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) @@ -240,6 +240,7 @@ "fit_addr_r=0x84100000\0" \ "fit_size=0x00f00000\0" \ "norboot=run add_default_bootargs &&" \ + "setexpr fit_addr $nor_base + $fit_addr &&" \ "bootm $fit_addr\0" \ "nandboot=run add_default_bootargs &&" \ "nand read $fit_addr_r $fit_addr $fit_size &&" \ @@ -262,6 +263,9 @@ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "norboot=run add_default_bootargs &&" \ + "setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ + "setexpr fdt_addr $nor_base + $fdt_addr &&" \ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ "nandboot=run add_default_bootargs &&" \ "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ @@ -278,6 +282,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "verify=n\0" \ + "norbase=0x42000000\0" \ "nandupdate=nand erase 0 0x00100000 &&" \ "tftpboot u-boot-spl-dtb.bin &&" \ "nand write $loadaddr 0 0x00010000 &&" \ -- cgit v1.3.1 From cf88affab6c46bc728d47fe2590c465734d78efb Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:49 +0900 Subject: ARM: uniphier: parse device tree to determine DRAM base and size Device tree specifies the available memory ranges in its "/memory" node. Use it to simplify the CONFIG defines. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_common.c | 12 --------- arch/arm/mach-uniphier/dram_init.c | 51 ++++++++++++++++++++++++++++++++--- include/configs/uniphier.h | 11 +------- 3 files changed, 48 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c index 5f2d5f6f5b9..967fa6c0865 100644 --- a/arch/arm/mach-uniphier/board_common.c +++ b/arch/arm/mach-uniphier/board_common.c @@ -18,15 +18,3 @@ int board_init(void) return 0; } - -#if CONFIG_NR_DRAM_BANKS >= 2 -void dram_init_banksize(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE; - gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE; - gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE; -} -#endif diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 4b8c938b5ea..32cc448aeb5 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -1,16 +1,59 @@ /* - * Copyright (C) 2012-2015 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2012-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const void *get_memory_reg_prop(const void *fdt, int *lenp) +{ + int offset; + + offset = fdt_path_offset(fdt, "/memory"); + if (offset < 0) + return NULL; + + return fdt_getprop(fdt, offset, "reg", lenp); +} int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + const fdt32_t *val; + int len; + + val = get_memory_reg_prop(gd->fdt_blob, &len); + if (len < sizeof(*val)) + return -EINVAL; + + gd->ram_size = fdt32_to_cpu(*(val + 1)); + + debug("DRAM size = %08lx\n", gd->ram_size); return 0; } + +void dram_init_banksize(void) +{ + const fdt32_t *val; + int len, i; + + val = get_memory_reg_prop(gd->fdt_blob, &len); + if (len < 0) + return; + + len /= sizeof(*val); + len /= 2; + + for (i = 0; i < len; i++) { + gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++); + gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++); + + debug("DRAM bank %d: start = %08lx, size = %08lx\n", + i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + } +} diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 45b39c075e5..a15838b1725 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -295,17 +295,8 @@ /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT -/* Memory Size & Mapping */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE - -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE -/* Thre is no memory hole */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) -#else +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) -#endif #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ defined(CONFIG_MACH_PH1_SLD8) -- cgit v1.3.1 From d7728aa408b478f83ec7f39ad80abf1046d71e39 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:32 +0900 Subject: ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally. Move them to a C file as local macros. Also, rename the C file. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Makefile | 2 +- arch/arm/mach-uniphier/micro-support-card.c | 231 ++++++++++++++++++++++++++++ arch/arm/mach-uniphier/support_card.c | 228 --------------------------- include/configs/uniphier.h | 11 +- 4 files changed, 234 insertions(+), 238 deletions(-) create mode 100644 arch/arm/mach-uniphier/micro-support-card.c delete mode 100644 arch/arm/mach-uniphier/support_card.c (limited to 'include') diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5f175575e86..df6a569b9a4 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -29,7 +29,7 @@ endif obj-y += timer.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/ obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c new file mode 100644 index 00000000000..4c34748c25c --- /dev/null +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2012-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define MICRO_SUPPORT_CARD_BASE 0x43f00000 +#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000) +#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000) +#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000) +#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034) +#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0) + +/* + * 0: reset deassert, 1: reset + * + * bit[0]: LAN, I2C, LED + * bit[1]: UART + */ +void support_card_reset_deassert(void) +{ + writel(0, MICRO_SUPPORT_CARD_RESET); +} + +void support_card_reset(void) +{ + writel(3, MICRO_SUPPORT_CARD_RESET); +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(MICRO_SUPPORT_CARD_REVISION); + printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf); + return 0; +} + +int check_support_card(void) +{ + printf("SC: Micro Support Card "); + return support_card_show_revision(); +} + +void support_card_init(void) +{ + /* + * After power on, we need to keep the LAN controller in reset state + * for a while. (200 usec) + * Fortunately, enough wait time is already inserted in pll_init() + * function. So we do not have to wait here. + */ + support_card_reset_deassert(); +} + +#if defined(CONFIG_SMC911X) +#include + +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, SMC911X_BASE); +} +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + +#include +#include + +struct memory_bank { + phys_addr_t base; + unsigned long size; +}; + +static int mem_is_flash(const struct memory_bank *mem) +{ + const int loop = 128; + u32 *scratch_addr; + u32 saved_value; + int ret = 1; + int i; + + /* just in case, use the tail of the memory bank */ + scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, + sizeof(u32) * loop, MAP_NOCACHE); + + for (i = 0; i < loop; i++, scratch_addr++) { + saved_value = readl(scratch_addr); + writel(~saved_value, scratch_addr); + if (readl(scratch_addr) != saved_value) { + /* We assume no memory or SRAM here. */ + writel(saved_value, scratch_addr); + ret = 0; + break; + } + } + + unmap_physmem(scratch_addr, MAP_NOCACHE); + + return ret; +} + +/* {address, size} */ +static const struct memory_bank memory_banks[] = { + {0x42000000, 0x01f00000}, +}; + +static const struct memory_bank +*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; + +phys_addr_t cfi_flash_bank_addr(int i) +{ + return flash_banks_list[i]->base; +} + +unsigned long cfi_flash_bank_size(int i) +{ + return flash_banks_list[i]->size; +} + +static void detect_num_flash_banks(void) +{ + const struct memory_bank *memory_bank, *end; + + cfi_flash_num_flash_banks = 0; + + memory_bank = memory_banks; + end = memory_bank + ARRAY_SIZE(memory_banks); + + for (; memory_bank < end; memory_bank++) { + if (cfi_flash_num_flash_banks >= + CONFIG_SYS_MAX_FLASH_BANKS_DETECT) + break; + + if (mem_is_flash(memory_bank)) { + flash_banks_list[cfi_flash_num_flash_banks] = + memory_bank; + + debug("flash bank found: base = 0x%lx, size = 0x%lx\n", + memory_bank->base, memory_bank->size); + cfi_flash_num_flash_banks++; + } + } + + debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); +} +#else /* CONFIG_SYS_NO_FLASH */ +void detect_num_flash_banks(void) +{ +}; +#endif /* CONFIG_SYS_NO_FLASH */ + +void support_card_late_init(void) +{ + detect_num_flash_banks(); +} + +static const u8 ledval_num[] = { + 0x7e, /* 0 */ + 0x0c, /* 1 */ + 0xb6, /* 2 */ + 0x9e, /* 3 */ + 0xcc, /* 4 */ + 0xda, /* 5 */ + 0xfa, /* 6 */ + 0x4e, /* 7 */ + 0xfe, /* 8 */ + 0xde, /* 9 */ +}; + +static const u8 ledval_alpha[] = { + 0xee, /* A */ + 0xf8, /* B */ + 0x72, /* C */ + 0xbc, /* D */ + 0xf2, /* E */ + 0xe2, /* F */ + 0x7a, /* G */ + 0xe8, /* H */ + 0x08, /* I */ + 0x3c, /* J */ + 0xea, /* K */ + 0x70, /* L */ + 0x6e, /* M */ + 0xa8, /* N */ + 0xb8, /* O */ + 0xe6, /* P */ + 0xce, /* Q */ + 0xa0, /* R */ + 0xc8, /* S */ + 0x8c, /* T */ + 0x7c, /* U */ + 0x54, /* V */ + 0xfc, /* W */ + 0xec, /* X */ + 0xdc, /* Y */ + 0xa4, /* Z */ +}; + +static u8 char2ledval(char c) +{ + if (isdigit(c)) + return ledval_num[c - '0']; + else if (isalpha(c)) + return ledval_alpha[toupper(c) - 'A']; + + return 0; +} + +void led_puts(const char *s) +{ + int i; + u32 val = 0; + + if (!s) + return; + + for (i = 0; i < 4; i++) { + val <<= 8; + val |= char2ledval(*s); + if (*s != '\0') + s++; + } + + writel(~val, LED_BASE); +} diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c deleted file mode 100644 index f8333060301..00000000000 --- a/arch/arm/mach-uniphier/support_card.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (C) 2012-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define MICRO_SUPPORT_CARD_RESET \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034) -#define MICRO_SUPPORT_CARD_REVISION \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0) -/* - * 0: reset deassert, 1: reset - * - * bit[0]: LAN, I2C, LED - * bit[1]: UART - */ -void support_card_reset_deassert(void) -{ - writel(0, MICRO_SUPPORT_CARD_RESET); -} - -void support_card_reset(void) -{ - writel(3, MICRO_SUPPORT_CARD_RESET); -} - -static int support_card_show_revision(void) -{ - u32 revision; - - revision = readl(MICRO_SUPPORT_CARD_REVISION); - printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf); - return 0; -} - -int check_support_card(void) -{ - printf("SC: Micro Support Card "); - return support_card_show_revision(); -} - -void support_card_init(void) -{ - /* - * After power on, we need to keep the LAN controller in reset state - * for a while. (200 usec) - * Fortunately, enough wait time is already inserted in pll_init() - * function. So we do not have to wait here. - */ - support_card_reset_deassert(); -} - -#if defined(CONFIG_SMC911X) -#include - -int board_eth_init(bd_t *bis) -{ - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -} -#endif - -#if !defined(CONFIG_SYS_NO_FLASH) - -#include -#include - -struct memory_bank { - phys_addr_t base; - unsigned long size; -}; - -static int mem_is_flash(const struct memory_bank *mem) -{ - const int loop = 128; - u32 *scratch_addr; - u32 saved_value; - int ret = 1; - int i; - - /* just in case, use the tail of the memory bank */ - scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, - sizeof(u32) * loop, MAP_NOCACHE); - - for (i = 0; i < loop; i++, scratch_addr++) { - saved_value = readl(scratch_addr); - writel(~saved_value, scratch_addr); - if (readl(scratch_addr) != saved_value) { - /* We assume no memory or SRAM here. */ - writel(saved_value, scratch_addr); - ret = 0; - break; - } - } - - unmap_physmem(scratch_addr, MAP_NOCACHE); - - return ret; -} - -/* {address, size} */ -static const struct memory_bank memory_banks[] = { - {0x42000000, 0x01f00000}, -}; - -static const struct memory_bank -*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; - -phys_addr_t cfi_flash_bank_addr(int i) -{ - return flash_banks_list[i]->base; -} - -unsigned long cfi_flash_bank_size(int i) -{ - return flash_banks_list[i]->size; -} - -static void detect_num_flash_banks(void) -{ - const struct memory_bank *memory_bank, *end; - - cfi_flash_num_flash_banks = 0; - - memory_bank = memory_banks; - end = memory_bank + ARRAY_SIZE(memory_banks); - - for (; memory_bank < end; memory_bank++) { - if (cfi_flash_num_flash_banks >= - CONFIG_SYS_MAX_FLASH_BANKS_DETECT) - break; - - if (mem_is_flash(memory_bank)) { - flash_banks_list[cfi_flash_num_flash_banks] = - memory_bank; - - debug("flash bank found: base = 0x%lx, size = 0x%lx\n", - memory_bank->base, memory_bank->size); - cfi_flash_num_flash_banks++; - } - } - - debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); -} -#else /* CONFIG_SYS_NO_FLASH */ -void detect_num_flash_banks(void) -{ -}; -#endif /* CONFIG_SYS_NO_FLASH */ - -void support_card_late_init(void) -{ - detect_num_flash_banks(); -} - -static const u8 ledval_num[] = { - 0x7e, /* 0 */ - 0x0c, /* 1 */ - 0xb6, /* 2 */ - 0x9e, /* 3 */ - 0xcc, /* 4 */ - 0xda, /* 5 */ - 0xfa, /* 6 */ - 0x4e, /* 7 */ - 0xfe, /* 8 */ - 0xde, /* 9 */ -}; - -static const u8 ledval_alpha[] = { - 0xee, /* A */ - 0xf8, /* B */ - 0x72, /* C */ - 0xbc, /* D */ - 0xf2, /* E */ - 0xe2, /* F */ - 0x7a, /* G */ - 0xe8, /* H */ - 0x08, /* I */ - 0x3c, /* J */ - 0xea, /* K */ - 0x70, /* L */ - 0x6e, /* M */ - 0xa8, /* N */ - 0xb8, /* O */ - 0xe6, /* P */ - 0xce, /* Q */ - 0xa0, /* R */ - 0xc8, /* S */ - 0x8c, /* T */ - 0x7c, /* U */ - 0x54, /* V */ - 0xfc, /* W */ - 0xec, /* X */ - 0xdc, /* Y */ - 0xa4, /* Z */ -}; - -static u8 char2ledval(char c) -{ - if (isdigit(c)) - return ledval_num[c - '0']; - else if (isalpha(c)) - return ledval_alpha[toupper(c) - 'A']; - - return 0; -} - -void led_puts(const char *s) -{ - int i; - u32 val = 0; - - if (!s) - return; - - for (i = 0; i < 4; i++) { - val <<= 8; - val |= char2ledval(*s); - if (*s != '\0') - s++; - } - - writel(~val, CONFIG_SUPPORT_CARD_LED_BASE); -} diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index a15838b1725..64059612f32 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -59,14 +59,6 @@ #define CONFIG_I2C_EEPROM #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -/* - * Support card address map - */ -#define CONFIG_SUPPORT_CARD_BASE 0x43f00000 -#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) -#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) - #ifdef CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE @@ -81,7 +73,8 @@ #define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE +/* dummy: referenced by examples/standalone/smc911x_eeprom.c */ +#define CONFIG_SMC911X_BASE 0 #define CONFIG_SMC911X_32_BIT /*----------------------------------------------------------------------- -- cgit v1.3.1 From 8497ccc4c23beae38130489d85c97ae38058f20b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:34 +0900 Subject: ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_* I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Kconfig | 14 +++++++------- arch/arm/mach-uniphier/Makefile | 8 ++++---- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 3 ++- arch/arm/mach-uniphier/include/mach/sc-regs.h | 2 +- arch/arm/mach-uniphier/ph1-pro4/pll_init.c | 2 -- configs/ph1_ld4_defconfig | 2 +- configs/ph1_sld3_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- drivers/pinctrl/uniphier/Kconfig | 12 ++++++------ include/configs/uniphier.h | 17 +++++++++-------- 10 files changed, 32 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 28d574fbb80..d7a19c6772c 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -8,20 +8,20 @@ config UNIPHIER_SMP choice prompt "UniPhier SoC select" - default MACH_PH1_PRO4 + default ARCH_UNIPHIER_PH1_PRO4 -config MACH_PH1_SLD3 +config ARCH_UNIPHIER_PH1_SLD3 bool "PH1-sLD3" select UNIPHIER_SMP -config MACH_PH1_LD4 +config ARCH_UNIPHIER_PH1_LD4 bool "PH1-LD4" -config MACH_PH1_PRO4 +config ARCH_UNIPHIER_PH1_PRO4 bool "PH1-Pro4" select UNIPHIER_SMP -config MACH_PH1_SLD8 +config ARCH_UNIPHIER_PH1_SLD8 bool "PH1-sLD8" endchoice @@ -53,11 +53,11 @@ choice config DDR_FREQ_1600 bool "DDR3 1600" - depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4 + depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 config DDR_FREQ_1333 bool "DDR3 1333" - depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8 + depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_SLD8 endchoice diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index df6a569b9a4..d30cc27009b 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -31,7 +31,7 @@ obj-y += timer.o obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o -obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/ -obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ -obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/ -obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += ph1-sld3/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index fce0c01246b..01f5c52c9c4 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -156,7 +156,8 @@ struct ddrphy { /* SoC-specific parameters */ #define NR_DATX8_PER_DDRPHY 2 -#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define NR_DDRPHY_PER_CH 1 #else #define NR_DDRPHY_PER_CH 2 diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index df502940779..9d697b16ee6 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -9,7 +9,7 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#if defined(CONFIG_MACH_PH1_SLD3) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) #define SC_BASE_ADDR 0xf1840000 #else #define SC_BASE_ADDR 0x61840000 diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c index d693368816c..8ae8ed65b87 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c @@ -54,12 +54,10 @@ static void vpll_init(void) tmp = readl(SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; -#if defined(CONFIG_MACH_PH1_PRO4) /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) return; -#endif /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ tmp = readl(SC_VPLL27ACTRL); diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 899a7238f38..e1665c090c8 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_MACH_PH1_LD4=y +CONFIG_ARCH_UNIPHIER_PH1_LD4=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" diff --git a/configs/ph1_sld3_defconfig b/configs/ph1_sld3_defconfig index 79ce0e28cde..4b871d0ebd5 100644 --- a/configs/ph1_sld3_defconfig +++ b/configs/ph1_sld3_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y -CONFIG_MACH_PH1_SLD3=y +CONFIG_ARCH_UNIPHIER_PH1_SLD3=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref" diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 216d49be124..00917fbc515 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_MACH_PH1_SLD8=y +CONFIG_ARCH_UNIPHIER_PH1_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 757edce178f..2ff616e9463 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -5,37 +5,37 @@ config PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD4 bool "UniPhier PH1-LD4 SoC pinctrl driver" - depends on MACH_PH1_LD4 + depends on ARCH_UNIPHIER_PH1_LD4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC pinctrl driver" - depends on MACH_PH1_PRO4 + depends on ARCH_UNIPHIER_PH1_PRO4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_SLD8 bool "UniPhier PH1-sLD8 SoC pinctrl driver" - depends on MACH_PH1_SLD8 + depends on ARCH_UNIPHIER_PH1_SLD8 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC pinctrl driver" - depends on MACH_PH1_PRO5 + depends on ARCH_UNIPHIER_PH1_PRO5 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC pinctrl driver" - depends on MACH_PROXSTREAM2 + depends on ARCH_UNIPHIER_PROXSTREAM2 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC pinctrl driver" - depends on MACH_PH1_LD6B + depends on ARCH_UNIPHIER_PH1_LD6B default y select PINCTRL_UNIPHIER_CORE diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 64059612f32..bd0769e6d92 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_MACH_PH1_SLD3) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) #define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH1 1 #define CONFIG_DDR_NUM_CH2 1 @@ -23,7 +23,7 @@ #define CONFIG_SDRAM2_SIZE 0x10000000 #endif -#if defined(CONFIG_MACH_PH1_LD4) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 @@ -34,7 +34,7 @@ #define CONFIG_SDRAM1_SIZE 0x10000000 #endif -#if defined(CONFIG_MACH_PH1_PRO4) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) #define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH1 2 @@ -45,7 +45,7 @@ #define CONFIG_SDRAM1_SIZE 0x20000000 #endif -#if defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 @@ -175,7 +175,7 @@ #define CONFIG_NAND_DENALI_ECC_SIZE 1024 -#ifdef CONFIG_MACH_PH1_SLD3 +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 #else @@ -291,11 +291,12 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 -#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ - defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 #endif -#if defined(CONFIG_MACH_PH1_PRO4) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -- cgit v1.3.1 From 5451b777de392043c03626f6cbbc3940c49c3417 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:38 +0900 Subject: ARM: uniphier: remove kernel parameter settings from environment Currently, console=ttyS0 is hard-coded in CONFIG_EXTRA_ENV_SETTINGS and it replaces the bootargs in the chosen node of the device tree passed to the kernel. This is not preferable because I am going to add some boards whose console is not ttyS0. Drop bootargs settings from U-Boot's environment and use the one in device tree by default. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index bd0769e6d92..f44c58bf9d0 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -224,22 +224,17 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ "tftpboot; bootm;" -#define CONFIG_BOOTARGS " earlyprintk loglevel=8" - #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "fitImage" #define LINUXBOOT_ENV_SETTINGS \ "fit_addr=0x00100000\0" \ "fit_addr_r=0x84100000\0" \ "fit_size=0x00f00000\0" \ - "norboot=run add_default_bootargs &&" \ - "setexpr fit_addr $nor_base + $fit_addr &&" \ + "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ "bootm $fit_addr\0" \ - "nandboot=run add_default_bootargs &&" \ - "nand read $fit_addr_r $fit_addr $fit_size &&" \ + "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ "bootm $fit_addr_r\0" \ - "tftpboot=run add_default_bootargs &&" \ - "tftpboot $fit_addr_r $bootfile &&" \ + "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ "bootm $fit_addr_r\0" #else #define CONFIG_BOOTFILE "uImage" @@ -255,18 +250,15 @@ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ - "norboot=run add_default_bootargs &&" \ - "setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr $nor_base + $fdt_addr &&" \ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "nandboot=run add_default_bootargs &&" \ - "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ + "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ - "tftpboot=run add_default_bootargs &&" \ - "tftpboot $kernel_addr_r $bootfile &&" \ + "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" @@ -281,8 +273,6 @@ "nand write $loadaddr 0 0x00010000 &&" \ "tftpboot u-boot-dtb.img &&" \ "nand write $loadaddr 0x00010000 0x000f0000\0" \ - "add_default_bootargs=setenv bootargs $bootargs" \ - " console=ttyS0,$baudrate\0" \ LINUXBOOT_ENV_SETTINGS /* Open Firmware flat tree */ -- cgit v1.3.1 From 323d1f9d5bebfe55e97e23c8094055685665afef Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:39 +0900 Subject: ARM: uniphier: allow to enable multiple SoCs Before this commit, the Kconfig menu in mach-uniphier only allowed us to choose one SoC to be compiled. Each SoC has its own defconfig file for the build-test coverage. Consequently, some defconfig files are duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and CONFIG_{SOC_NAME}=y. Now, most of board-specific parameters have been moved to device trees, so it makes sense to include init code of multiple SoCs into a single image as long as the SoCs have similar architecture. In fact, some SoCs of UniPhier family are very similar: - PH1-LD4 and PH1-sLD8 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit) This commit will be helpful to merge some defconfig files for better maintainability. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Kconfig | 45 ++--- arch/arm/mach-uniphier/Makefile | 16 +- arch/arm/mach-uniphier/bcu/Makefile | 3 + arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 34 ++++ arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c | 38 ++++ arch/arm/mach-uniphier/board_early_init_f.c | 42 ++++- arch/arm/mach-uniphier/boards.c | 93 ++++++++++ arch/arm/mach-uniphier/boot-mode/Makefile | 6 + .../mach-uniphier/boot-mode/boot-mode-ph1-ld4.c | 74 ++++++++ .../mach-uniphier/boot-mode/boot-mode-ph1-sld3.c | 106 +++++++++++ arch/arm/mach-uniphier/boot-mode/boot-mode.c | 35 ++++ arch/arm/mach-uniphier/clk/Makefile | 4 + arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 42 +++++ arch/arm/mach-uniphier/clk/clk-ph1-pro4.c | 57 ++++++ arch/arm/mach-uniphier/cmd_pinmon.c | 31 ++-- arch/arm/mach-uniphier/ddrphy/Makefile | 3 + arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c | 72 ++++++++ arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c | 72 ++++++++ arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c | 77 ++++++++ arch/arm/mach-uniphier/ddrphy/ddrphy-training.c | 139 ++++++++++++++ arch/arm/mach-uniphier/ddrphy_training.c | 139 -------------- arch/arm/mach-uniphier/early-clk/Makefile | 4 + .../mach-uniphier/early-clk/early-clk-ph1-ld4.c | 33 ++++ arch/arm/mach-uniphier/early-pinctrl/Makefile | 1 + .../early-pinctrl/early-pinctrl-ph1-sld3.c | 26 +++ arch/arm/mach-uniphier/include/mach/boot-device.h | 11 +- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 4 +- arch/arm/mach-uniphier/include/mach/init.h | 83 +++++++++ arch/arm/mach-uniphier/include/mach/sg-regs.h | 6 + arch/arm/mach-uniphier/include/mach/soc_info.h | 63 +++++++ arch/arm/mach-uniphier/init/Makefile | 6 + arch/arm/mach-uniphier/init/init-ph1-ld4.c | 60 ++++++ arch/arm/mach-uniphier/init/init-ph1-pro4.c | 58 ++++++ arch/arm/mach-uniphier/init/init-ph1-sld3.c | 53 ++++++ arch/arm/mach-uniphier/init/init-ph1-sld8.c | 60 ++++++ arch/arm/mach-uniphier/init/init.c | 46 +++++ arch/arm/mach-uniphier/memconf.c | 103 ----------- arch/arm/mach-uniphier/memconf/Makefile | 2 + arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c | 59 ++++++ arch/arm/mach-uniphier/memconf/memconf.c | 104 +++++++++++ arch/arm/mach-uniphier/ph1-ld4/Makefile | 13 -- arch/arm/mach-uniphier/ph1-ld4/bcu_init.c | 32 ---- arch/arm/mach-uniphier/ph1-ld4/boot-mode.c | 1 - arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c | 41 ----- arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c | 70 ------- arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-ld4/pinctrl.c | 48 ----- arch/arm/mach-uniphier/ph1-ld4/pll_init.c | 189 ------------------- arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c | 1 - arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | 49 ----- arch/arm/mach-uniphier/ph1-ld4/umc_init.c | 171 ----------------- arch/arm/mach-uniphier/ph1-pro4/Makefile | 13 -- arch/arm/mach-uniphier/ph1-pro4/boot-mode.c | 65 ------- arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c | 56 ------ arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c | 70 ------- .../arm/mach-uniphier/ph1-pro4/early_clkrst_init.c | 30 --- arch/arm/mach-uniphier/ph1-pro4/pinctrl.c | 49 ----- arch/arm/mach-uniphier/ph1-pro4/pll_init.c | 149 --------------- arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c | 18 -- arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 42 ----- arch/arm/mach-uniphier/ph1-pro4/umc_init.c | 157 ---------------- arch/arm/mach-uniphier/ph1-sld3/Makefile | 13 -- arch/arm/mach-uniphier/ph1-sld3/bcu_init.c | 36 ---- arch/arm/mach-uniphier/ph1-sld3/boot-mode.c | 97 ---------- arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c | 1 - .../arm/mach-uniphier/ph1-sld3/early_clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c | 23 --- arch/arm/mach-uniphier/ph1-sld3/memconf.c | 52 ------ arch/arm/mach-uniphier/ph1-sld3/pinctrl.c | 24 --- arch/arm/mach-uniphier/ph1-sld3/pll_init.c | 10 - arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c | 18 -- arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 45 ----- arch/arm/mach-uniphier/ph1-sld3/sg_init.c | 9 - arch/arm/mach-uniphier/ph1-sld3/umc_init.c | 15 -- arch/arm/mach-uniphier/ph1-sld8/Makefile | 1 - arch/arm/mach-uniphier/ph1-sld8/bcu_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/boot-mode.c | 1 - arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c | 75 -------- .../arm/mach-uniphier/ph1-sld8/early_clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/pinctrl.c | 42 ----- arch/arm/mach-uniphier/ph1-sld8/pll_init.c | 201 -------------------- arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c | 1 - arch/arm/mach-uniphier/ph1-sld8/sbc_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/umc_init.c | 151 --------------- arch/arm/mach-uniphier/pinctrl/Makefile | 4 + arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 49 +++++ arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 50 +++++ arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 25 +++ arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 43 +++++ arch/arm/mach-uniphier/pll/Makefile | 8 + arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c | 203 ++++++++++++++++++++ arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c | 163 ++++++++++++++++ arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c | 13 ++ arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c | 204 +++++++++++++++++++++ arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c | 20 ++ arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c | 21 +++ arch/arm/mach-uniphier/sbc/Makefile | 4 + arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c | 52 ++++++ arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c | 45 +++++ arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c | 48 +++++ arch/arm/mach-uniphier/soc_info.c | 61 ++++++ arch/arm/mach-uniphier/spl.c | 87 --------- arch/arm/mach-uniphier/umc/Makefile | 3 + arch/arm/mach-uniphier/umc/umc-ph1-ld4.c | 175 ++++++++++++++++++ arch/arm/mach-uniphier/umc/umc-ph1-pro4.c | 161 ++++++++++++++++ arch/arm/mach-uniphier/umc/umc-ph1-sld8.c | 155 ++++++++++++++++ configs/ph1_pro4_defconfig | 1 + include/configs/uniphier.h | 50 +---- 109 files changed, 3116 insertions(+), 2524 deletions(-) create mode 100644 arch/arm/mach-uniphier/bcu/Makefile create mode 100644 arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/boards.c create mode 100644 arch/arm/mach-uniphier/boot-mode/Makefile create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode.c create mode 100644 arch/arm/mach-uniphier/clk/Makefile create mode 100644 arch/arm/mach-uniphier/clk/clk-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/clk/clk-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/ddrphy/Makefile create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-training.c delete mode 100644 arch/arm/mach-uniphier/ddrphy_training.c create mode 100644 arch/arm/mach-uniphier/early-clk/Makefile create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/early-pinctrl/Makefile create mode 100644 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/include/mach/init.h create mode 100644 arch/arm/mach-uniphier/include/mach/soc_info.h create mode 100644 arch/arm/mach-uniphier/init/Makefile create mode 100644 arch/arm/mach-uniphier/init/init-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/init/init-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/init/init-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/init/init-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/init/init.c delete mode 100644 arch/arm/mach-uniphier/memconf.c create mode 100644 arch/arm/mach-uniphier/memconf/Makefile create mode 100644 arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/memconf/memconf.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/bcu_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/umc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/umc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/memconf.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sg_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/umc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/bcu_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/umc_init.c create mode 100644 arch/arm/mach-uniphier/pinctrl/Makefile create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/pll/Makefile create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/sbc/Makefile create mode 100644 arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/soc_info.c delete mode 100644 arch/arm/mach-uniphier/spl.c create mode 100644 arch/arm/mach-uniphier/umc/Makefile create mode 100644 arch/arm/mach-uniphier/umc/umc-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/umc/umc-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/umc/umc-ph1-sld8.c (limited to 'include') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index d7a19c6772c..2cc5dac0700 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -6,25 +6,32 @@ config SYS_CONFIG_NAME config UNIPHIER_SMP bool -choice - prompt "UniPhier SoC select" - default ARCH_UNIPHIER_PH1_PRO4 - config ARCH_UNIPHIER_PH1_SLD3 - bool "PH1-sLD3" + bool "UniPhier PH1-sLD3 SoC" select UNIPHIER_SMP + help + This enables support for UniPhier PH1-sLD3 SoC. config ARCH_UNIPHIER_PH1_LD4 - bool "PH1-LD4" + bool "UniPhier PH1-LD4 SoC" + depends on !ARCH_UNIPHIER_PH1_SLD3 + help + This enables support for UniPhier PH1-LD4 SoC. config ARCH_UNIPHIER_PH1_PRO4 - bool "PH1-Pro4" + bool "UniPhier PH1-Pro4 SoC" select UNIPHIER_SMP + depends on !ARCH_UNIPHIER_PH1_SLD3 && \ + !ARCH_UNIPHIER_PH1_LD4 && \ + !ARCH_UNIPHIER_PH1_SLD8 + help + This enables support for UniPhier PH1-Pro4 SoC. config ARCH_UNIPHIER_PH1_SLD8 - bool "PH1-sLD8" - -endchoice + bool "UniPhier PH1-sLD8 SoC" + depends on !ARCH_UNIPHIER_PH1_SLD3 + help + This enables support for UniPhier PH1-sLD8 SoC. config MICRO_SUPPORT_CARD bool "Use Micro Support Card" @@ -48,22 +55,4 @@ config CMD_DDRPHY_DUMP The command "ddrphy" shows the resulting parameters of DDR PHY training; it is useful for the evaluation of DDR PHY training. -choice - prompt "DDR3 Frequency select" - -config DDR_FREQ_1600 - bool "DDR3 1600" - depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 - -config DDR_FREQ_1333 - bool "DDR3 1333" - depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_SLD8 - -endchoice - -config DDR_FREQ - int - default 1333 if DDR_FREQ_1333 - default 1600 if DDR_FREQ_1600 - endif diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5c2ccbd7a88..b597a1352c2 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -6,9 +6,10 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o obj-y += init_page_table.o -obj-y += spl.o -obj-y += memconf.o -obj-y += ddrphy_training.o +obj-y += boards.o + +obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/ +obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ obj-$(CONFIG_DEBUG_LL) += debug_ll.o @@ -27,13 +28,12 @@ obj-y += cache_uniphier.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o +obj-y += pinctrl/ clk/ + endif obj-y += timer.o +obj-y += soc_info.o +obj-y += boot-mode/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o - -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += ph1-sld3/ -obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ph1-ld4/ -obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ph1-pro4/ -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile new file mode 100644 index 00000000000..5b95bdad957 --- /dev/null +++ b/arch/arm/mach-uniphier/bcu/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c new file mode 100644 index 00000000000..e9d3761fde9 --- /dev/null +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +int ph1_ld4_bcu_init(const struct uniphier_board_data *bd) +{ + int shift; + + writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + + /* Specify DDR channel */ + shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c new file mode 100644 index 00000000000..cb6f8627211 --- /dev/null +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +int ph1_sld3_bcu_init(const struct uniphier_board_data *bd) +{ + int shift; + + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + /* + * 0xe0000000-0xefffffff: Ex-bus + * 0xf0000000-0xfbffffff: ASM bus + * 0xfc000000-0xffffffff: OCM bus + */ + writel(0x24440000, BCSCR5); + + /* Specify DDR channel */ + shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 45f5cea4334..cd516c3121a 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -4,20 +4,46 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include - -void pin_init(void); -void clkrst_init(void); +#include int board_early_init_f(void) { led_puts("U0"); - pin_init(); - - led_puts("U1"); - - clkrst_init(); + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + ph1_sld3_pin_init(); + led_puts("U1"); + ph1_ld4_clk_init(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + case SOC_UNIPHIER_PH1_LD4: + ph1_ld4_pin_init(); + led_puts("U1"); + ph1_ld4_clk_init(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + case SOC_UNIPHIER_PH1_PRO4: + ph1_pro4_pin_init(); + led_puts("U1"); + ph1_pro4_clk_init(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_SLD8: + ph1_sld8_pin_init(); + led_puts("U1"); + ph1_ld4_clk_init(); + break; +#endif + default: + break; + } led_puts("U2"); diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c new file mode 100644 index 00000000000..6a5ea2e585f --- /dev/null +++ b/arch/arm/mach-uniphier/boards.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) +static const struct uniphier_board_data ph1_sld3_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x20000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xc0000000, + .dram_ch1_size = 0x20000000, + .dram_ch1_width = 16, + .dram_ch2_base = 0xc0000000, + .dram_ch2_size = 0x10000000, + .dram_ch2_width = 16, + .dram_freq = 1600, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) +static const struct uniphier_board_data ph1_ld4_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x10000000, + .dram_ch0_width = 16, + .dram_ch1_base = 0x90000000, + .dram_ch1_size = 0x10000000, + .dram_ch1_width = 16, + .dram_freq = 1600, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) +static const struct uniphier_board_data ph1_pro4_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x20000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xa0000000, + .dram_ch1_size = 0x20000000, + .dram_ch1_width = 32, + .dram_freq = 1600, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) +static const struct uniphier_board_data ph1_sld8_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x10000000, + .dram_ch0_width = 16, + .dram_ch1_base = 0x90000000, + .dram_ch1_size = 0x10000000, + .dram_ch1_width = 16, + .dram_freq = 1333, +}; +#endif + +struct uniphier_board_id { + const char *compatible; + const struct uniphier_board_data *param; +}; + +static const struct uniphier_board_id uniphier_boards[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + { "socionext,ph1-sld3", &ph1_sld3_data, }, +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + { "socionext,ph1-ld4", &ph1_ld4_data, }, +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + { "socionext,ph1-pro4", &ph1_pro4_data, }, +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + { "socionext,ph1-sld8", &ph1_sld8_data, }, +#endif +}; + +const struct uniphier_board_data *uniphier_get_board_param(const void *fdt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) { + if (!fdt_node_check_compatible(fdt, 0, + uniphier_boards[i].compatible)) + return uniphier_boards[i].param; + } + + return NULL; +} diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile new file mode 100644 index 00000000000..bd6d0a3d7c9 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -0,0 +1,6 @@ +obj-y += boot-mode.o + +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c new file mode 100644 index 00000000000..f974d9f08d1 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, +}; + +static int get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 ph1_ld4_boot_device(void) +{ + int boot_mode; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} + +void ph1_ld4_boot_mode_show(void) +{ + int mode_sel, i; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); +} diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c new file mode 100644 index 00000000000..c943e12db15 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "External Master"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, +}; + +static int get_boot_mode_sel(void) +{ + return readl(SG_PINMON0) & 0x3f; +} + +u32 ph1_sld3_boot_device(void) +{ + int boot_mode; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} + +void ph1_sld3_boot_mode_show(void) +{ + int mode_sel, i; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); +} diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c new file mode 100644 index 00000000000..71abdef1f4d --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + if (boot_is_swapped()) + return BOOT_DEVICE_NOR; + + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + return ph1_sld3_boot_device(); +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_LD4: + case SOC_UNIPHIER_PH1_PRO4: + case SOC_UNIPHIER_PH1_SLD8: + return ph1_ld4_boot_device(); +#endif + default: + return BOOT_DEVICE_NONE; + } +} diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile new file mode 100644 index 00000000000..e6931d6461b --- /dev/null +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c new file mode 100644 index 00000000000..8b95fbb008a --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_ld4_clk_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c new file mode 100644 index 00000000000..2e1b20a423c --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_pro4_clk_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + SC_CLKCTRL_CEN_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c index 8be2ed4fe63..a61d40e6c5a 100644 --- a/arch/arm/mach-uniphier/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/cmd_pinmon.c @@ -1,6 +1,5 @@ /* - * Copyright (C) 2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2014-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,20 +7,30 @@ #include #include #include +#include static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int mode_sel, i; - printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); - mode_sel = get_boot_mode_sel(); - - puts("Boot Mode Pin:\n"); - - for (i = 0; boot_device_table[i].info; i++) - printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, - boot_device_table[i].info); + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + ph1_sld3_boot_mode_show(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_LD4: + case SOC_UNIPHIER_PH1_PRO4: + case SOC_UNIPHIER_PH1_SLD8: + ph1_ld4_boot_mode_show(); + break; +#endif + default: + break; + } return 0; } diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile new file mode 100644 index 00000000000..e2d109df57a --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c new file mode 100644 index 00000000000..991d9294fd0 --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8253c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a82dbc0, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000800, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c new file mode 100644 index 00000000000..bc47ba3280d --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000000, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c new file mode 100644 index 00000000000..39024a09d5e --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, &phy->mr3); +#else + writel(0x00000800, &phy->mr3); +#endif + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c new file mode 100644 index 00000000000..a98b814df07 --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) +{ + int dx; + u32 __iomem tmp, *p; + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + p = &phy->dx[dx].gcr; + + tmp = readl(p); + /* Specify the rank that should be write leveled */ + tmp &= ~DXGCR_WLRKEN_MASK; + tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; + writel(tmp, p); + } + + p = &phy->dtcr; + + tmp = readl(p); + /* Specify the rank used during data bit deskew and eye centering */ + tmp &= ~DTCR_DTRANK_MASK; + tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; + /* Use Multi-Purpose Register for DQS gate training */ + tmp |= DTCR_DTMPR; + /* Specify the rank enabled for data-training */ + tmp &= ~DTCR_RNKEN_MASK; + tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + writel(tmp, p); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static struct ddrphy_init_sequence init_sequence[] = { + { + "DRAM Initialization", + PIR_DRAMRST | PIR_DRAMINIT, + PGSR0_DIDONE, + PGSR0_DIERR + }, + { + "Write Leveling", + PIR_WL, + PGSR0_WLDONE, + PGSR0_WLERR + }, + { + "Read DQS Gate Training", + PIR_QSGATE, + PGSR0_QSGDONE, + PGSR0_QSGERR + }, + { + "Write Leveling Adjustment", + PIR_WLADJ, + PGSR0_WLADONE, + PGSR0_WLAERR + }, + { + "Read Bit Deskew", + PIR_RDDSKW, + PGSR0_RDDONE, + PGSR0_RDERR + }, + { + "Write Bit Deskew", + PIR_WRDSKW, + PGSR0_WDDONE, + PGSR0_WDERR + }, + { + "Read Eye Training", + PIR_RDEYE, + PGSR0_REDONE, + PGSR0_REERR + }, + { + "Write Eye Training", + PIR_WREYE, + PGSR0_WEDONE, + PGSR0_WEERR + } +}; + +int ddrphy_training(struct ddrphy __iomem *phy) +{ + int i; + u32 pgsr0; + u32 init_flag = PIR_INIT; + u32 done_flag = PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + init_flag |= init_sequence[i].init_flag; + done_flag |= init_sequence[i].done_flag; + } + + writel(init_flag, &phy->pir); + + do { + if (--timeout < 0) { + printf("%s: error: timeout during DDR training\n", + __func__); + return -1; + } + udelay(1); + pgsr0 = readl(&phy->pgsr[0]); + } while ((pgsr0 & done_flag) != done_flag); + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + if (pgsr0 & init_sequence[i].err_flag) { + printf("%s: error: %s failed\n", __func__, + init_sequence[i].description); + return -1; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy_training.c b/arch/arm/mach-uniphier/ddrphy_training.c deleted file mode 100644 index a98b814df07..00000000000 --- a/arch/arm/mach-uniphier/ddrphy_training.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) -{ - int dx; - u32 __iomem tmp, *p; - - for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { - p = &phy->dx[dx].gcr; - - tmp = readl(p); - /* Specify the rank that should be write leveled */ - tmp &= ~DXGCR_WLRKEN_MASK; - tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; - writel(tmp, p); - } - - p = &phy->dtcr; - - tmp = readl(p); - /* Specify the rank used during data bit deskew and eye centering */ - tmp &= ~DTCR_DTRANK_MASK; - tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; - /* Use Multi-Purpose Register for DQS gate training */ - tmp |= DTCR_DTMPR; - /* Specify the rank enabled for data-training */ - tmp &= ~DTCR_RNKEN_MASK; - tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; - writel(tmp, p); -} - -struct ddrphy_init_sequence { - char *description; - u32 init_flag; - u32 done_flag; - u32 err_flag; -}; - -static struct ddrphy_init_sequence init_sequence[] = { - { - "DRAM Initialization", - PIR_DRAMRST | PIR_DRAMINIT, - PGSR0_DIDONE, - PGSR0_DIERR - }, - { - "Write Leveling", - PIR_WL, - PGSR0_WLDONE, - PGSR0_WLERR - }, - { - "Read DQS Gate Training", - PIR_QSGATE, - PGSR0_QSGDONE, - PGSR0_QSGERR - }, - { - "Write Leveling Adjustment", - PIR_WLADJ, - PGSR0_WLADONE, - PGSR0_WLAERR - }, - { - "Read Bit Deskew", - PIR_RDDSKW, - PGSR0_RDDONE, - PGSR0_RDERR - }, - { - "Write Bit Deskew", - PIR_WRDSKW, - PGSR0_WDDONE, - PGSR0_WDERR - }, - { - "Read Eye Training", - PIR_RDEYE, - PGSR0_REDONE, - PGSR0_REERR - }, - { - "Write Eye Training", - PIR_WREYE, - PGSR0_WEDONE, - PGSR0_WEERR - } -}; - -int ddrphy_training(struct ddrphy __iomem *phy) -{ - int i; - u32 pgsr0; - u32 init_flag = PIR_INIT; - u32 done_flag = PGSR0_IDONE; - int timeout = 50000; /* 50 msec is long enough */ -#ifdef DISPLAY_ELAPSED_TIME - ulong start = get_timer(0); -#endif - - for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { - init_flag |= init_sequence[i].init_flag; - done_flag |= init_sequence[i].done_flag; - } - - writel(init_flag, &phy->pir); - - do { - if (--timeout < 0) { - printf("%s: error: timeout during DDR training\n", - __func__); - return -1; - } - udelay(1); - pgsr0 = readl(&phy->pgsr[0]); - } while ((pgsr0 & done_flag) != done_flag); - - for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { - if (pgsr0 & init_sequence[i].err_flag) { - printf("%s: error: %s failed\n", __func__, - init_sequence[i].description); - return -1; - } - } - -#ifdef DISPLAY_ELAPSED_TIME - printf("%s: info: elapsed time %ld msec\n", get_timer(start)); -#endif - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile new file mode 100644 index 00000000000..58af1add582 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c new file mode 100644 index 00000000000..f646c9b7df9 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; + if (spl_boot_device() != BOOT_DEVICE_NAND) + tmp &= ~SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile new file mode 100644 index 00000000000..e497d28f792 --- /dev/null +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c new file mode 100644 index 00000000000..1bb9375016d --- /dev/null +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(63, 0, 4, 4); /* RXD0 */ + sg_set_pinsel(64, 1, 4, 4); /* TXD0 */ + + sg_set_pinsel(65, 0, 4, 4); /* RXD1 */ + sg_set_pinsel(66, 1, 4, 4); /* TXD1 */ + + sg_set_pinsel(96, 2, 4, 4); /* RXD2 */ + sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ +#endif + + return 0; +} diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h index 7a10f1c5b2c..eddb25ffa45 100644 --- a/arch/arm/mach-uniphier/include/mach/boot-device.h +++ b/arch/arm/mach-uniphier/include/mach/boot-device.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2011-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,13 +7,15 @@ #ifndef _ASM_BOOT_DEVICE_H_ #define _ASM_BOOT_DEVICE_H_ -int get_boot_mode_sel(void); - struct boot_device_info { u32 type; char *info; }; -extern struct boot_device_info boot_device_table[]; +u32 ph1_sld3_boot_device(void); +u32 ph1_ld4_boot_device(void); + +void ph1_sld3_boot_mode_show(void); +void ph1_ld4_boot_mode_show(void); #endif /* _ASM_BOOT_DEVICE_H_ */ diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index 01f5c52c9c4..adcc972877e 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -168,7 +168,9 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) #ifndef __ASSEMBLY__ -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h new file mode 100644 index 00000000000..228cbb1a195 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/init.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_INIT_H +#define __MACH_INIT_H + +struct uniphier_board_data { + unsigned long dram_ch0_base; + unsigned long dram_ch0_size; + unsigned long dram_ch0_width; + unsigned long dram_ch1_base; + unsigned long dram_ch1_size; + unsigned long dram_ch1_width; + unsigned long dram_ch2_base; + unsigned long dram_ch2_size; + unsigned long dram_ch2_width; + unsigned int dram_freq; +}; + +const struct uniphier_board_data *uniphier_get_board_param(const void *fdt); + +int ph1_sld3_init(const struct uniphier_board_data *bd); +int ph1_ld4_init(const struct uniphier_board_data *bd); +int ph1_pro4_init(const struct uniphier_board_data *bd); +int ph1_sld8_init(const struct uniphier_board_data *bd); + +#if defined(CONFIG_MICRO_SUPPORT_CARD) +int ph1_sld3_sbc_init(const struct uniphier_board_data *bd); +int ph1_ld4_sbc_init(const struct uniphier_board_data *bd); +int ph1_pro4_sbc_init(const struct uniphier_board_data *bd); +#else +static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd) +{ + return 0; +} + +static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd) +{ + return 0; +} + +static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) +{ + return 0; +} +#endif + +int ph1_sld3_bcu_init(const struct uniphier_board_data *bd); +int ph1_ld4_bcu_init(const struct uniphier_board_data *bd); + +int memconf_init(const struct uniphier_board_data *bd); +int ph1_sld3_memconf_init(const struct uniphier_board_data *bd); + +int ph1_sld3_pll_init(const struct uniphier_board_data *bd); +int ph1_ld4_pll_init(const struct uniphier_board_data *bd); +int ph1_pro4_pll_init(const struct uniphier_board_data *bd); +int ph1_sld8_pll_init(const struct uniphier_board_data *bd); + +int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd); +int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); + +int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd); + +int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd); + +int ph1_ld4_umc_init(const struct uniphier_board_data *bd); +int ph1_pro4_umc_init(const struct uniphier_board_data *bd); +int ph1_sld8_umc_init(const struct uniphier_board_data *bd); + +void ph1_sld3_pin_init(void); +void ph1_ld4_pin_init(void); +void ph1_pro4_pin_init(void); +void ph1_sld8_pin_init(void); + +void ph1_ld4_clk_init(void); +void ph1_pro4_clk_init(void); + +#define pr_err(fmt, args...) printf(fmt, ##args) + +#endif /* __MACH_INIT_H */ diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h index c886e1c6555..d8239f28bc5 100644 --- a/arch/arm/mach-uniphier/include/mach/sg-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h @@ -25,26 +25,32 @@ /* Memory Configuration */ #define SG_MEMCONF (SG_CTRL_BASE | 0x0400) +#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8) #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) +#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2)) #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9) #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) +#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16)) #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24) #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/include/mach/soc_info.h new file mode 100644 index 00000000000..623e7ef20ee --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/soc_info.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_SOC_INFO_H__ +#define __MACH_SOC_INFO_H__ + +enum uniphier_soc_id { + SOC_UNIPHIER_PH1_SLD3, + SOC_UNIPHIER_PH1_LD4, + SOC_UNIPHIER_PH1_PRO4, + SOC_UNIPHIER_PH1_SLD8, + SOC_UNIPHIER_PH1_PRO5, + SOC_UNIPHIER_PROXSTREAM2, + SOC_UNIPHIER_PH1_LD6B, + SOC_UNIPHIER_UNKNOWN, +}; + +#define UNIPHIER_NR_ENABLED_SOCS \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + +#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1) + +#if UNIPHIER_MULTI_SOC +enum uniphier_soc_id uniphier_get_soc_type(void); +#else +static inline enum uniphier_soc_id uniphier_get_soc_type(void) +{ +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + return SOC_UNIPHIER_PH1_SLD3; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + return SOC_UNIPHIER_PH1_LD4; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + return SOC_UNIPHIER_PH1_PRO4; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + return SOC_UNIPHIER_PH1_SLD8; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + return SOC_UNIPHIER_PH1_PRO5; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + return SOC_UNIPHIER_PROXSTREAM2; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + return SOC_UNIPHIER_PH1_LD6B; +#endif + + return SOC_UNIPHIER_UNKNOWN; +} +#endif + +#endif /* __MACH_SOC_INFO_H__ */ diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile new file mode 100644 index 00000000000..dd9804d33b5 --- /dev/null +++ b/arch/arm/mach-uniphier/init/Makefile @@ -0,0 +1,6 @@ +obj-y += init.o + +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/init/init-ph1-ld4.c b/arch/arm/mach-uniphier/init/init-ph1-ld4.c new file mode 100644 index 00000000000..8d0ef0389e1 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-ld4.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_ld4_init(const struct uniphier_board_data *bd) +{ + ph1_ld4_bcu_init(bd); + + ph1_ld4_sbc_init(bd); + + support_card_reset(); + + ph1_ld4_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = ph1_ld4_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + ph1_ld4_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro4.c b/arch/arm/mach-uniphier/init/init-ph1-pro4.c new file mode 100644 index 00000000000..b9ce08d88f9 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-pro4.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_pro4_init(const struct uniphier_board_data *bd) +{ + ph1_pro4_sbc_init(bd); + + support_card_reset(); + + ph1_pro4_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = ph1_pro4_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + ph1_ld4_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld3.c b/arch/arm/mach-uniphier/init/init-ph1-sld3.c new file mode 100644 index 00000000000..1146fdab977 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-sld3.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_sld3_init(const struct uniphier_board_data *bd) +{ + ph1_sld3_bcu_init(bd); + + ph1_sld3_sbc_init(bd); + + support_card_reset(); + + ph1_sld3_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + ph1_sld3_memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + ph1_sld3_early_pin_init(bd); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + led_puts("L5"); + + ph1_sld3_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld8.c b/arch/arm/mach-uniphier/init/init-ph1-sld8.c new file mode 100644 index 00000000000..741e88c212f --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-sld8.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_sld8_init(const struct uniphier_board_data *bd) +{ + ph1_ld4_bcu_init(bd); + + ph1_ld4_sbc_init(bd); + + support_card_reset(); + + ph1_sld8_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = ph1_sld8_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + ph1_ld4_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c new file mode 100644 index 00000000000..316be029ae6 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + const struct uniphier_board_data *param; + + param = uniphier_get_board_param(gd->fdt_blob); + if (!param) + hang(); + + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + ph1_sld3_init(param); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + case SOC_UNIPHIER_PH1_LD4: + ph1_ld4_init(param); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + case SOC_UNIPHIER_PH1_PRO4: + ph1_pro4_init(param); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_SLD8: + ph1_sld8_init(param); + break; +#endif + default: + break; + } +} diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c deleted file mode 100644 index 59ed0b5dd8f..00000000000 --- a/arch/arm/mach-uniphier/memconf.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static inline u32 sg_memconf_val_ch0(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH0_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH0_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH0_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH0_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH0_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH0_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH0_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -static inline u32 sg_memconf_val_ch1(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH1_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH1_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH1_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH1_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH1_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH1_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH1_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -void memconf_init(void) -{ - u32 tmp; - - /* Set DDR size */ - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE - tmp |= SG_MEMCONF_SPARSEMEM; -#endif - writel(tmp, SG_MEMCONF); -} diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile new file mode 100644 index 00000000000..1a718f31fae --- /dev/null +++ b/arch/arm/mach-uniphier/memconf/Makefile @@ -0,0 +1,2 @@ +obj-y += memconf.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c new file mode 100644 index 00000000000..e13f56d1dcb --- /dev/null +++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int ph1_sld3_memconf_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + unsigned long size_per_word; + + tmp = readl(SG_MEMCONF); + + tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK); + + switch (bd->dram_ch2_width) { + case 16: + tmp |= SG_MEMCONF_CH2_NUM_1; + size_per_word = bd->dram_ch2_size; + break; + case 32: + tmp |= SG_MEMCONF_CH2_NUM_2; + size_per_word = bd->dram_ch2_size >> 1; + break; + default: + pr_err("error: unsupported DRAM Ch2 width\n"); + return -EINVAL; + } + + /* Set DDR size */ + switch (size_per_word) { + case SZ_64M: + tmp |= SG_MEMCONF_CH2_SZ_64M; + break; + case SZ_128M: + tmp |= SG_MEMCONF_CH2_SZ_128M; + break; + case SZ_256M: + tmp |= SG_MEMCONF_CH2_SZ_256M; + break; + case SZ_512M: + tmp |= SG_MEMCONF_CH2_SZ_512M; + break; + default: + pr_err("error: unsupported DRAM Ch2 size\n"); + return -EINVAL; + } + + writel(tmp, SG_MEMCONF); + + return 0; +} diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c new file mode 100644 index 00000000000..d490736fa43 --- /dev/null +++ b/arch/arm/mach-uniphier/memconf/memconf.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int memconf_init(const struct uniphier_board_data *bd) +{ + u32 tmp = 0; + unsigned long size_per_word; + + tmp = readl(SG_MEMCONF); + + tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK); + + switch (bd->dram_ch0_width) { + case 16: + tmp |= SG_MEMCONF_CH0_NUM_1; + size_per_word = bd->dram_ch0_size; + break; + case 32: + tmp |= SG_MEMCONF_CH0_NUM_2; + size_per_word = bd->dram_ch0_size >> 1; + break; + default: + pr_err("error: unsupported DRAM Ch0 width\n"); + return -EINVAL; + } + + /* Set DDR size */ + switch (size_per_word) { + case SZ_64M: + tmp |= SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + tmp |= SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + tmp |= SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + tmp |= SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + tmp |= SG_MEMCONF_CH0_SZ_1G; + break; + default: + pr_err("error: unsupported DRAM Ch0 size\n"); + return -EINVAL; + } + + tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK); + + switch (bd->dram_ch1_width) { + case 16: + tmp |= SG_MEMCONF_CH1_NUM_1; + size_per_word = bd->dram_ch1_size; + break; + case 32: + tmp |= SG_MEMCONF_CH1_NUM_2; + size_per_word = bd->dram_ch1_size >> 1; + break; + default: + pr_err("error: unsupported DRAM Ch1 width\n"); + return -EINVAL; + } + + switch (size_per_word) { + case SZ_64M: + tmp |= SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + tmp |= SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + tmp |= SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + tmp |= SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + tmp |= SG_MEMCONF_CH1_SZ_1G; + break; + default: + pr_err("error: unsupported DRAM Ch1 size\n"); + return -EINVAL; + } + + if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base) + tmp |= SG_MEMCONF_SPARSEMEM; + else + tmp &= ~SG_MEMCONF_SPARSEMEM; + + writel(tmp, SG_MEMCONF); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile deleted file mode 100644 index 4b9fe91fb03..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += bcu_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -endif - -obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c b/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c deleted file mode 100644 index a7bc15e7e06..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) - -void bcu_init(void) -{ - int shift; - - writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ - - /* Specify DDR channel */ - shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c deleted file mode 100644 index d359b562919..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c deleted file mode 100644 index 2de81f0a560..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_RSTCTRL_NRST_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_CLKCTRL_CEN_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c deleted file mode 100644 index 2add8fa691f..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8253c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a82dbc0, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(0x00000800, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c deleted file mode 100644 index d7ef16b10a1..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c deleted file mode 100644 index 293a6ab4234..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void pin_init(void) -{ - u32 tmp; - - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ - sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ - sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ - sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ - sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ - sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ - sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ -#endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */ - /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */ - /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */ -#endif - - tmp = readl(SG_IECTRL); - tmp |= 0x41; - writel(tmp, SG_IECTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c b/arch/arm/mach-uniphier/ph1-ld4/pll_init.c deleted file mode 100644 index f8ec2b61fb4..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#undef DPLL_SSC_RATE_1PER - -static void dpll_init(void) -{ - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT (DPLLCTRL.bit[29:20]) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x000f0000; -#if CONFIG_DDR_FREQ == 1600 - tmp |= 0x000c0000; -#elif CONFIG_DDR_FREQ == 1333 - tmp |= 0x000d0000; -#else -# error "Unknown frequency" -#endif - -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~SC_DPLLCTRL_SSC_RATE; -#else - tmp |= SC_DPLLCTRL_SSC_RATE; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); -} - -static void upll_init(void) -{ - u32 tmp, clk_mode_upll, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); - tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); - - if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x0228f5c0; - } else { - /* AXO: default 24.576MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x02328000; - } - } - - writel(tmp, SC_UPLLCTRL); - - /* set 1 to K_LD(UPLLCTRL.bit[27]) */ - tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); - - /* wait 10 usec */ - udelay(10); - - /* set 1 to SNRT(UPLLCTRL.bit[28]) */ - tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* wait 10 usec */ - udelay(10); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -void pll_init(void) -{ - dpll_init(); - upll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 10 usec in upll_init() and vpll_init() - * so 20 usec can be saved here. - */ - udelay(480); -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c deleted file mode 100644 index 837b2a891b7..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/pll_spectrum.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c deleted file mode 100644 index 4435a47e73c..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - u32 tmp; - - /* system bus output enable */ - tmp = readl(PC0CTRL); - tmp &= 0xfffffcff; - writel(tmp, PC0CTRL); - - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c b/arch/arm/mach-uniphier/ph1-ld4/umc_init.c deleted file mode 100644 index a7a4157e793..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void umc_start_ssif(void __iomem *ssif_base) -{ - writel(0x00000000, ssif_base + 0x0000b004); - writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x000fffcf, ssif_base + 0x0000c008); - writel(0x00000001, ssif_base + 0x0000b000); - writel(0x00000001, ssif_base + 0x0000c000); - writel(0x03010101, ssif_base + UMC_MDMCHSEL); - writel(0x03010100, ssif_base + UMC_DMDCHSEL); - - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); - - writel(0x00000001, ssif_base + UMC_CPURST); - writel(0x00000001, ssif_base + UMC_IDSRST); - writel(0x00000001, ssif_base + UMC_IXMRST); - writel(0x00000001, ssif_base + UMC_MDMRST); - writel(0x00000001, ssif_base + UMC_MDDRST); - writel(0x00000001, ssif_base + UMC_SIORST); - writel(0x00000001, ssif_base + UMC_VIORST); - writel(0x00000001, ssif_base + UMC_FRCRST); - writel(0x00000001, ssif_base + UMC_RGLRST); - writel(0x00000001, ssif_base + UMC_AIORST); - writel(0x00000001, ssif_base + UMC_DMDRST); -} - -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) -{ - if (freq == 1333) { - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x000FF0FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - } else if (freq == 1600) { - writel(0x36BB0F17, dramcont + UMC_CMDCTLA); - writel(0x18C6AA24, dramcont + UMC_CMDCTLB); - writel(0x5101387F, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x2F030D3F, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x43030D3F, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - } - - writel(0x00000006, dramcont + UMC_DRMMR1); - - if (freq == 1333) - writel(0x00000290, dramcont + UMC_DRMMR2); - else if (freq == 1600) - writel(0x00000298, dramcont + UMC_DRMMR2); - - writel(0x00000800, dramcont + UMC_DRMMR3); - - if (freq == 1333) { - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - } else if (freq == 1600) { - if (size == 1) - writel(0x002B0617, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x003F0617, dramcont + UMC_SPCCTLA); - - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); - } - - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); - writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); -} - -static int umc_init_sub(int freq, int size_ch0, int size_ch1) -{ - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_0, freq, size_ch0); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; -} - -int umc_init(void) -{ - return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, - CONFIG_SDRAM1_SIZE / 0x08000000); -} - -#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ - (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ - CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 -/* OK */ -#else -#error Unsupported DDR configuration. -#endif diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile deleted file mode 100644 index e8b2c9e8ac2..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -endif - -obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c b/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c deleted file mode 100644 index 54a2510b97f..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -struct boot_device_info boot_device_table[] = { - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - { /* sentinel */ } -}; - -int get_boot_mode_sel(void) -{ - return (readl(SG_PINMON0) >> 1) & 0x1f; -} - -u32 spl_boot_device(void) -{ - int boot_mode; - - if (boot_is_swapped()) - return BOOT_DEVICE_NOR; - - boot_mode = get_boot_mode_sel(); - - return boot_device_table[boot_mode].type; -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c deleted file mode 100644 index 46cace77e54..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | - SC_RSTCTRL_NRST_GIO; -#endif -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_RSTCTRL_NRST_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp = readl(SC_RSTCTRL2); - tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ -#endif - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | - SC_CLKCTRL_CEN_GIO; -#endif -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_CLKCTRL_CEN_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c deleted file mode 100644 index 61ddcf4ec63..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(0x00000000, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c deleted file mode 100644 index 60204b53ba5..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void early_clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); - - tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; - if (spl_boot_device() != BOOT_DEVICE_NAND) - tmp &= ~SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c deleted file mode 100644 index bfaff4fea9a..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ - sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ - sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ - sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ - sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ - sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ - sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ - sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ - sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ - sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ - sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ - sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ - sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ - sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ - /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ - /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ - sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ -#endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */ - sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */ -#endif - - writel(1, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c deleted file mode 100644 index 8ae8ed65b87..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#undef DPLL_SSC_RATE_1PER - -static void dpll_init(void) -{ - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT ( DPLLCTRL.bit[29:20] ) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~(0x000f0000); -#if CONFIG_DDR_FREQ == 1600 - tmp |= 0x000c0000; -#elif CONFIG_DDR_FREQ == 1333 - tmp |= 0x000d0000; -#else -# error "Unsupported frequency" -#endif - - /* - * Set Moduration rate - * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) - */ -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~0x00008000; -#else - tmp |= 0x00008000; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - /* Set VPLL27A & VPLL27B */ - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) - return; - - /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Unset VPLA_K_LD and VPLB_K_LD bit */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set VPLA_M and VPLB_M to 0x20 */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { - /* Set VPLA_K and VPLB_K for AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066666; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066666; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* wait 1 usec */ - udelay(1); - - /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Unset VPLA_SNRST and VPLB_SNRST bit */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -void pll_init(void) -{ - dpll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 1 usec in vpll_init() so 1 usec can be saved here. - */ - udelay(499); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c deleted file mode 100644 index fcf2ad282a7..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void enable_dpll_ssc(void) -{ - u32 tmp; - - tmp = readl(SC_DPLLCTRL); - tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c deleted file mode 100644 index 685f9c736c9..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c b/arch/arm/mach-uniphier/ph1-pro4/umc_init.c deleted file mode 100644 index bd8b9d83b2b..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void umc_start_ssif(void __iomem *ssif_base) -{ - writel(0x00000001, ssif_base + 0x0000b004); - writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x07ffffff, ssif_base + 0x0000c008); - writel(0x00000001, ssif_base + 0x0000b000); - writel(0x00000001, ssif_base + 0x0000c000); - - writel(0x03010100, ssif_base + UMC_HDMCHSEL); - writel(0x03010101, ssif_base + UMC_MDMCHSEL); - writel(0x03010100, ssif_base + UMC_DVCCHSEL); - writel(0x03010100, ssif_base + UMC_DMDCHSEL); - - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); - writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ - - writel(0x00000001, ssif_base + UMC_CPURST); - writel(0x00000001, ssif_base + UMC_IDSRST); - writel(0x00000001, ssif_base + UMC_IXMRST); - writel(0x00000001, ssif_base + UMC_HDMRST); - writel(0x00000001, ssif_base + UMC_MDMRST); - writel(0x00000001, ssif_base + UMC_HDDRST); - writel(0x00000001, ssif_base + UMC_MDDRST); - writel(0x00000001, ssif_base + UMC_SIORST); - writel(0x00000001, ssif_base + UMC_GIORST); - writel(0x00000001, ssif_base + UMC_HD2RST); - writel(0x00000001, ssif_base + UMC_VIORST); - writel(0x00000001, ssif_base + UMC_DVCRST); - writel(0x00000001, ssif_base + UMC_RGLRST); - writel(0x00000001, ssif_base + UMC_VPERST); - writel(0x00000001, ssif_base + UMC_AIORST); - writel(0x00000001, ssif_base + UMC_DMDRST); -} - -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) -{ - writel(0x66bb0f17, dramcont + UMC_CMDCTLA); - writel(0x18c6aa44, dramcont + UMC_CMDCTLB); - writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(0x43030d3f, dramcont + UMC_INITCTLB); - writel(0x00ff00ff, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000298, dramcont + UMC_DRMMR2); - writel(0x00000000, dramcont + UMC_DRMMR3); - writel(0x003f0617, dramcont + UMC_SPCCTLA); - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); - writel(0x04060802, dramcont + UMC_WDATACTL_D0); - writel(0x04060802, dramcont + UMC_WDATACTL_D1); - writel(0x04a02000, dramcont + UMC_DATASET); - writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x0000000f, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x00000000, dramcont + 0x0060); - writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00010000, dramcont + UMC_SPCSETD); - writel(0x80000020, dramcont + UMC_DFICUPDCTLA); -} - -static int umc_init_sub(int freq, int size_ch0, int size_ch1) -{ - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_0, freq, size_ch0); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); - - writel(0x00000103, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_1, freq, size_ch0); - - ddrphy_prepare_training(phy0_1, 1); - ddrphy_training(phy0_1); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 0); - ddrphy_training(phy1_0); - - writel(0x00000103, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_1, freq, size_ch1); - - ddrphy_prepare_training(phy1_1, 1); - ddrphy_training(phy1_1); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; -} - -int umc_init(void) -{ - return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, - CONFIG_SDRAM1_SIZE / 0x08000000); -} - -#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ - (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ - ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ - (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1)) -/* OK */ -#else - #error Unsupported DDR configuration. -#endif diff --git a/arch/arm/mach-uniphier/ph1-sld3/Makefile b/arch/arm/mach-uniphier/ph1-sld3/Makefile deleted file mode 100644 index 48a3756c1d0..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \ - early_pinctrl.o pll_spectrum.o umc_init.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -endif - -obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c deleted file mode 100644 index ccc6897d0ad..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) - -void bcu_init(void) -{ - int shift; - - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - /* - * 0xe0000000-0xefffffff: Ex-bus - * 0xf0000000-0xfbffffff: ASM bus - * 0xfc000000-0xffffffff: OCM bus - */ - writel(0x24440000, BCSCR5); - - /* Specify DDR channel */ - shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c deleted file mode 100644 index 40000afe741..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -struct boot_device_info boot_device_table[] = { - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "External Master"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - { /* sentinel */ } -}; - -int get_boot_mode_sel(void) -{ - return readl(SG_PINMON0) & 0x3f; -} - -u32 spl_boot_device(void) -{ - int boot_mode; - - if (boot_is_swapped()) - return BOOT_DEVICE_NOR; - - boot_mode = get_boot_mode_sel(); - - return boot_device_table[boot_mode].type; -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c deleted file mode 100644 index 3a3dab7a153..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c deleted file mode 100644 index d7ef16b10a1..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c deleted file mode 100644 index f6ceef5f1c0..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -void early_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(63, 0, 4, 4); /* RXD0 */ - sg_set_pinsel(64, 1, 4, 4); /* TXD0 */ - - sg_set_pinsel(65, 0, 4, 4); /* RXD1 */ - sg_set_pinsel(66, 1, 4, 4); /* TXD1 */ - - sg_set_pinsel(96, 2, 4, 4); /* RXD2 */ - sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ -#endif -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/memconf.c b/arch/arm/mach-uniphier/ph1-sld3/memconf.c deleted file mode 100644 index 553a9e33844..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/memconf.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static inline u32 sg_memconf_val_ch2(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH2_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH2_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH2_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH2_SZ_512M; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH2_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH2_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -u32 memconf_additional_val(void) -{ - return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2); -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c deleted file mode 100644 index dea938ed2fa..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -void pin_init(void) -{ -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ - sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ - - sg_set_pinsel(15, 0, 4, 4); /* USB1OC */ - sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */ - - sg_set_pinsel(17, 0, 4, 4); /* USB2OC */ - sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */ - - sg_set_pinsel(19, 0, 4, 4); /* USB3OC */ - sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */ -#endif -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c b/arch/arm/mach-uniphier/ph1-sld3/pll_init.c deleted file mode 100644 index ebd1c310b7a..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void pll_init(void) -{ - /* add pll init code here */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c deleted file mode 100644 index fcf2ad282a7..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void enable_dpll_ssc(void) -{ - u32 tmp; - - tmp = readl(SC_DPLLCTRL); - tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c deleted file mode 100644 index 3e62121ba95..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - /* only address/data multiplex mode is supported */ - - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } - - sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c b/arch/arm/mach-uniphier/ph1-sld3/sg_init.c deleted file mode 100644 index ca3cb9c6b8e..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void sg_init(void) -{ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c b/arch/arm/mach-uniphier/ph1-sld3/umc_init.c deleted file mode 100644 index 91ee3de2827..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -int umc_init(void) -{ - /* add UMC init code here */ - printf("Implement memory init code\n"); - - return 0; -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile deleted file mode 100644 index 8eb575e1d38..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/Makefile +++ /dev/null @@ -1 +0,0 @@ -include $(src)/../ph1-ld4/Makefile diff --git a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c deleted file mode 100644 index 69b172e4e7b..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/bcu_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c deleted file mode 100644 index d359b562919..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c deleted file mode 100644 index 8d3435d6321..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c deleted file mode 100644 index 21efe62da6b..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, &phy->mr3); -#else - writel(0x00000800, &phy->mr3); -#endif - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c deleted file mode 100644 index dd236b7e500..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c deleted file mode 100644 index 1b64414553b..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ - sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ - sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ - sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ - sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ - sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ - sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ -#endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */ - /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ - /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */ -#endif -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c deleted file mode 100644 index 109cb5fee08..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void dpll_init(void) -{ - u32 tmp; - /* - * Set DPLL SSC parameters for DPLLCTRL3 - * [23] DIVN_TEST 0x1 - * [22:16] DIVN 0x50 - * [10] FREFSEL_TEST 0x1 - * [9:8] FREFSEL 0x2 - * [4] ICPD_TEST 0x1 - * [3:0] ICPD 0xb - */ - tmp = readl(SC_DPLLCTRL3); - tmp &= ~0x00ff0717; - tmp |= 0x00d0061b; - writel(tmp, SC_DPLLCTRL3); - - /* - * Set DPLL SSC parameters for DPLLCTRL - * <-1%> <-2%> - * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) - * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x3ff07fff; -#ifdef CONFIG_DPLL_SSC_RATE_1PER - tmp |= 0x084018bf; -#else - tmp |= 0x084031a6; -#endif - writel(tmp, SC_DPLLCTRL); - - /* - * Set DPLL SSC parameters for DPLLCTRL2 - * [31:29] SSC_STEP 0 - * [27] SSC_REG_REF 1 - * [26:20] SSC_M 79 (0x4f) - * [19:0] SSC_K 964689 (0xeb851) - */ - tmp = readl(SC_DPLLCTRL2); - tmp &= ~0xefffffff; - tmp |= 0x0cfeb851; - writel(tmp, SC_DPLLCTRL2); -} - -static void upll_init(void) -{ - u32 tmp, clk_mode_upll, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); - tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); - - if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x0228f5c0; - } else { - /* AXO: default 24.576MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x02328000; - } - } - - writel(tmp, SC_UPLLCTRL); - - /* set 1 to K_LD(UPLLCTRL.bit[27]) */ - tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); - - /* wait 10 usec */ - udelay(10); - - /* set 1 to SNRT(UPLLCTRL.bit[28]) */ - tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* wait 10 usec */ - udelay(10); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -void pll_init(void) -{ - dpll_init(); - upll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 10 usec in upll_init() and vpll_init() - * so 20 usec can be saved here. - */ - udelay(480); -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c deleted file mode 100644 index 9b8c4855e58..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/pll_spectrum.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c deleted file mode 100644 index 225c0d24de3..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/sbc_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c deleted file mode 100644 index 7baea7e8528..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void umc_start_ssif(void __iomem *ssif_base) -{ - writel(0x00000000, ssif_base + 0x0000b004); - writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x000fffcf, ssif_base + 0x0000c008); - writel(0x00000001, ssif_base + 0x0000b000); - writel(0x00000001, ssif_base + 0x0000c000); - writel(0x03010101, ssif_base + UMC_MDMCHSEL); - writel(0x03010100, ssif_base + UMC_DMDCHSEL); - - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); - - writel(0x00000001, ssif_base + UMC_CPURST); - writel(0x00000001, ssif_base + UMC_IDSRST); - writel(0x00000001, ssif_base + UMC_IXMRST); - writel(0x00000001, ssif_base + UMC_MDMRST); - writel(0x00000001, ssif_base + UMC_MDDRST); - writel(0x00000001, ssif_base + UMC_SIORST); - writel(0x00000001, ssif_base + UMC_VIORST); - writel(0x00000001, ssif_base + UMC_FRCRST); - writel(0x00000001, ssif_base + UMC_RGLRST); - writel(0x00000001, ssif_base + UMC_AIORST); - writel(0x00000001, ssif_base + UMC_DMDRST); -} - -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) -{ -#ifdef CONFIG_DDR_STANDARD - writel(0x55990b11, dramcont + UMC_CMDCTLA); - writel(0x16958944, dramcont + UMC_CMDCTLB); -#else - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); -#endif - - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000290, dramcont + UMC_DRMMR2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, dramcont + UMC_DRMMR3); -#else - writel(0x00000800, dramcont + UMC_DRMMR3); -#endif - - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); - writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000004f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000077, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); -} - -static int umc_init_sub(int freq, int size_ch0, int size_ch1) -{ - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_0, freq, size_ch0); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; -} - -int umc_init(void) -{ - return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, - CONFIG_SDRAM1_SIZE / 0x08000000); -} - -#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ - (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ - CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 -/* OK */ -#else -#error Unsupported DDR configuration. -#endif diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile new file mode 100644 index 00000000000..542c670f978 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c new file mode 100644 index 00000000000..160d3ef2991 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_ld4_pin_init(void) +{ + u32 tmp; + + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ + sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ + sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ + sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ + sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ + sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ + sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ + sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ + sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ + sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ + sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ + sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ + sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ + sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ + sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */ + sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */ + /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */ +#endif + + tmp = readl(SG_IECTRL); + tmp |= 0x41; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c new file mode 100644 index 00000000000..f50644c52bb --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_pro4_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ + sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ + sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ + sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ + sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ + sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ + sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ + sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ + sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ + sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ + sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ + sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ + sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ + sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ + /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ + /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ +#endif + +#ifdef CONFIG_USB_XHCI_UNIPHIER + sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ + sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c new file mode 100644 index 00000000000..f1b2bbbb4a2 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void ph1_sld3_pin_init(void) +{ +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ + sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ + + sg_set_pinsel(15, 0, 4, 4); /* USB1OC */ + sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */ + + sg_set_pinsel(17, 0, 4, 4); /* USB2OC */ + sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */ + + sg_set_pinsel(19, 0, 4, 4); /* USB3OC */ + sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */ +#endif +} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c new file mode 100644 index 00000000000..f936a53d1f1 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_sld8_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ + sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ + sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ + sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ + sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ + sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ + sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ + sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ + sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ + sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ + sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ + sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ + sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ + sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ + sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */ + sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ + /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */ +#endif +} diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile new file mode 100644 index 00000000000..d33f99e4461 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \ + pll-spectrum-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \ + pll-spectrum-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pll-init-ph1-pro4.o \ + pll-spectrum-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pll-init-ph1-sld8.o \ + pll-spectrum-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c new file mode 100644 index 00000000000..a272a900e11 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +static int dpll_init(unsigned int dram_freq) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + return 0; +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +int ph1_ld4_pll_init(const struct uniphier_board_data *bd) +{ + int ret; + + ret = dpll_init(bd->dram_freq); + if (ret) + return ret; + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c new file mode 100644 index 00000000000..906c22f6c58 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +static int dpll_init(unsigned int dram_freq) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + return 0; +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + /* Set VPLL27A & VPLL27B */ + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) + return; + + /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Unset VPLA_K_LD and VPLB_K_LD bit */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set VPLA_M and VPLB_M to 0x20 */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { + /* Set VPLA_K and VPLB_K for AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* wait 1 usec */ + udelay(1); + + /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Unset VPLA_SNRST and VPLB_SNRST bit */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +int ph1_pro4_pll_init(const struct uniphier_board_data *bd) +{ + int ret; + + ret = dpll_init(bd->dram_freq); + if (ret) + return ret; + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 1 usec in vpll_init() so 1 usec can be saved here. + */ + udelay(499); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c new file mode 100644 index 00000000000..6294a452c29 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +int ph1_sld3_pll_init(const struct uniphier_board_data *bd) +{ + /* add pll init code here */ + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c new file mode 100644 index 00000000000..f249abeeda3 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static void dpll_init(void) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef CONFIG_DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +int ph1_sld8_pll_init(const struct uniphier_board_data *bd) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c new file mode 100644 index 00000000000..cad0ed8cdd4 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c new file mode 100644 index 00000000000..43dc9736549 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); + + return 0; +} diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile new file mode 100644 index 00000000000..68ffd1c626b --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += sbc-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c new file mode 100644 index 00000000000..929f50a883a --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_ld4_sbc_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c new file mode 100644 index 00000000000..1032c54e644 --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) +{ + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c new file mode 100644 index 00000000000..fb707be83a2 --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_sld3_sbc_init(const struct uniphier_board_data *bd) +{ + /* only address/data multiplex mode is supported */ + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c new file mode 100644 index 00000000000..3e8e7f4ef33 --- /dev/null +++ b/arch/arm/mach-uniphier/soc_info.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#if UNIPHIER_MULTI_SOC +enum uniphier_soc_id uniphier_get_soc_type(void) +{ + u32 revision = readl(SG_REVISION); + enum uniphier_soc_id ret; + + switch ((revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT) { +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 + case 0x25: + ret = SOC_UNIPHIER_PH1_SLD3; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD4 + case 0x26: + ret = SOC_UNIPHIER_PH1_LD4; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO4 + case 0x28: + ret = SOC_UNIPHIER_PH1_PRO4; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD8 + case 0x29: + ret = SOC_UNIPHIER_PH1_SLD8; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO5 + case 0x2A: + ret = SOC_UNIPHIER_PH1_PRO5; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PROXSTREAM2 + case 0x2E: + ret = SOC_UNIPHIER_PROXSTREAM2; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD6B + case 0x2F: + ret = SOC_UNIPHIER_PH1_LD6B; + break; +#endif + default: + ret = SOC_UNIPHIER_UNKNOWN; + break; + } + + return ret; +} +#endif diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c deleted file mode 100644 index 4c3cad3b88b..00000000000 --- a/arch/arm/mach-uniphier/spl.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2013-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void __weak bcu_init(void) -{ -}; - -void __weak sbc_init(void) -{ -}; - -void __weak sg_init(void) -{ -}; - -void __weak early_pin_init(void) -{ -}; - -void sbc_init(void); -void sg_init(void); -void pll_init(void); -void pin_init(void); -void memconf_init(void); -void early_clkrst_init(void); -void early_pin_init(void); -int umc_init(void); -void enable_dpll_ssc(void); - -void spl_board_init(void) -{ - bcu_init(); - - sbc_init(); - - sg_init(); - - support_card_reset(); - - pll_init(); - - support_card_init(); - - led_puts("L0"); - - memconf_init(); - - led_puts("L1"); - - early_clkrst_init(); - - led_puts("L2"); - - early_pin_init(); - - led_puts("L3"); - -#ifdef CONFIG_SPL_SERIAL_SUPPORT - preloader_console_init(); -#endif - - led_puts("L4"); - - { - int res; - - res = umc_init(); - if (res < 0) { - while (1) - ; - } - } - - led_puts("L5"); - - enable_dpll_ssc(); - - led_puts("L6"); -} diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile new file mode 100644 index 00000000000..dd35e77dab4 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c b/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c new file mode 100644 index 00000000000..81246850b38 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + if (freq == 1333) { + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x000FF0FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + } else if (freq == 1600) { + writel(0x36BB0F17, dramcont + UMC_CMDCTLA); + writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + writel(0x5101387F, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x2F030D3F, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x43030D3F, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + } + + writel(0x00000006, dramcont + UMC_DRMMR1); + + if (freq == 1333) + writel(0x00000290, dramcont + UMC_DRMMR2); + else if (freq == 1600) + writel(0x00000298, dramcont + UMC_DRMMR2); + + writel(0x00000800, dramcont + UMC_DRMMR3); + + if (freq == 1333) { + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + } else if (freq == 1600) { + if (size == 1) + writel(0x002B0617, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x003F0617, dramcont + UMC_SPCCTLA); + + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + } + + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int ph1_ld4_umc_init(const struct uniphier_board_data *bd) +{ + if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && + (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && + (bd->dram_freq == 1333 || bd->dram_freq == 1600) && + bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { + return umc_init_sub(bd->dram_freq, + bd->dram_ch0_size / SZ_128M, + bd->dram_ch1_size / SZ_128M); + } else { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } +} diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c b/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c new file mode 100644 index 00000000000..8c9f0579fc7 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000001, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + + writel(0x03010100, ssif_base + UMC_HDMCHSEL); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DVCCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_HDMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_HDDRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_GIORST); + writel(0x00000001, ssif_base + UMC_HD2RST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_DVCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_VPERST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); + writel(0x18c6aa44, dramcont + UMC_CMDCTLB); + writel(0x5101387f, dramcont + UMC_INITCTLA); + writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(0x00ff00ff, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000298, dramcont + UMC_DRMMR2); + writel(0x00000000, dramcont + UMC_DRMMR3); + writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); + writel(0x04060802, dramcont + UMC_WDATACTL_D0); + writel(0x04060802, dramcont + UMC_WDATACTL_D1); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x0000000f, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00000000, dramcont + 0x0060); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00010000, dramcont + UMC_SPCSETD); + writel(0x80000020, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0); + + ddrphy_prepare_training(phy0_1, 1); + ddrphy_training(phy0_1); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 0); + ddrphy_training(phy1_0); + + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1); + + ddrphy_prepare_training(phy1_1, 1); + ddrphy_training(phy1_1); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int ph1_pro4_umc_init(const struct uniphier_board_data *bd) +{ + if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) || + (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) && + ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) || + (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) && + bd->dram_freq == 1600) { + return umc_init_sub(bd->dram_freq, + bd->dram_ch0_size / SZ_128M, + bd->dram_ch1_size / SZ_128M); + } else { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } +} diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c b/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c new file mode 100644 index 00000000000..bc60a3472e1 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ +#ifdef CONFIG_DDR_STANDARD + writel(0x55990b11, dramcont + UMC_CMDCTLA); + writel(0x16958944, dramcont + UMC_CMDCTLB); +#else + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); +#endif + + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000290, dramcont + UMC_DRMMR2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, dramcont + UMC_DRMMR3); +#else + writel(0x00000800, dramcont + UMC_DRMMR3); +#endif + + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000004f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000077, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int ph1_sld8_umc_init(const struct uniphier_board_data *bd) +{ + if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && + (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && + bd->dram_freq == 1333 && + bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { + return umc_init_sub(bd->dram_freq, + bd->dram_ch0_size / SZ_128M, + bd->dram_ch1_size / SZ_128M); + } else { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } +} diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 139767a6ee3..aaf1f460388 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_PH1_PRO4=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index f44c58bf9d0..9109b7f8d9d 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -9,53 +9,6 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_NUM_CH2 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xc0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#define CONFIG_SDRAM2_BASE 0xc0000000 -#define CONFIG_SDRAM2_SIZE 0x10000000 -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 2 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xa0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - #define CONFIG_I2C_EEPROM #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 @@ -285,8 +238,7 @@ defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 -#endif -#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) +#else #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -- cgit v1.3.1 From e0bed6b67dcd0273b4c98df52835fda14f88904a Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 26 Aug 2015 17:54:44 +0300 Subject: configs: remove remnants of CONFIG_SYS_NAND_QUIET_TEST The config option has been removed by one of the syncs with the Linux mainline MTD subsystem: ff94bc40af (mtd, ubi, ubifs: resync with Linux-3.14) It has been left inside the config files. Currently does not look to serve any purpose, so remove it now from all the configs. Signed-off-by: Igor Grinberg Cc: Matthias Fuchs Cc: Stefan Roese Cc: "Albert ARIBAUD (3ADEV)" Cc: Peter Barada Cc: Steve Sakoman Cc: Peter Tyser Cc: Joe Hershberger Cc: Simon Glass Acked-by: Stefan Roese --- include/configs/PMC440.h | 1 - include/configs/cm_t35.h | 1 - include/configs/cm_t3517.h | 1 - include/configs/omap3_beagle.h | 1 - include/configs/omap3_cairo.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omap3_overo.h | 1 - include/configs/spear-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/xpedite517x.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - 12 files changed, 12 deletions(-) (limited to 'include') diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 9ed6c61ab74..17bd18031dc 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -406,7 +406,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 281d614de18..e5fb474afce 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -147,7 +147,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 69332b647da..f3d1f4352e4 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -154,7 +154,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index f309b2e83b7..bf986f86cb6 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -121,7 +121,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 713df3cf80d..3f777b6aebc 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -70,7 +70,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 8bd36340e7b..ecd56158597 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -105,7 +105,6 @@ * Board NAND Info. */ #define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 53ff61d10c1..3b1e5d7ff8e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -88,7 +88,6 @@ #endif /* CONFIG_NAND */ /* Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ /* Environment information */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index fb1bf66d024..edae831f22f 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -97,7 +97,6 @@ #define CONFIG_NAND_FSMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_QUIET_TEST /* * Command support defines diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 408895f3329..bd1c07c3ebb 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -126,7 +126,6 @@ /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 669aa53c913..b5d1126d597 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -138,7 +138,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ #define CONFIG_SYS_NAND_ACTL_DELAY 25 -#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_JFFS2_NAND /* diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 58ace2cf487..0d2423499d9 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -131,7 +131,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ #define CONFIG_NAND_FSL_ELBC /* diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 765aaadf105..f30d1996c01 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -122,7 +122,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ #define CONFIG_NAND_FSL_ELBC /* -- cgit v1.3.1 From d9da26ecc6641d8f257bd32e9108c40805b4cbc3 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 28 Sep 2015 15:58:15 +0530 Subject: am437x_evm: increase phy autoneg timeout When AM437x EVM is connected to Gigabit switch, it takes more time to finish auto-negotiation than on a 10/100 switch. The default 4 second limit times-out more often than not. This is observed when testing with a D-Link DGS-1008A desktop switch. Increase the auto-negotiation time-out for AM437x EVM to handle this case. Signed-off-by: Sekhar Nori --- include/configs/am43xx_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d868442acb5..67d5c48ddeb 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -329,6 +329,7 @@ #define CONFIG_DRIVER_TI_CPSW #define CONFIG_PHYLIB +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL" -- cgit v1.3.1 From c9a67d2489d68abac2f3be151abf1f09126b91a2 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 10 Sep 2015 21:55:13 +0100 Subject: ARM: hikey: Use linux/sizes.h for malloc size Use the #defines in linux/sizes for malloc size as it is more readable. Signed-off-by: Peter Griffin Reviewed-by: Simon Glass --- include/configs/hikey.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 8ff9077c371..7666bf98c5c 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -12,6 +12,8 @@ #ifndef __HIKEY_H #define __HIKEY_H +#include + /* We use generic board for hikey */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_POWER @@ -55,7 +57,7 @@ #define GICC_BASE 0xf6802000 /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) /* PL011 Serial Configuration */ #define CONFIG_PL011_SERIAL -- cgit v1.3.1 From efd7b60a81fe7a8ecffa585691d835456d5d551a Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 10 Sep 2015 21:55:16 +0100 Subject: ARM: hikey: Select DM, DM_GPIO from Kconfig Most platforms enable these options from Kconfig rather than the configs header file. Signed-off-by: Peter Griffin Reviewed-by: Simon Glass --- arch/arm/Kconfig | 2 ++ include/configs/hikey.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c4371c71733..5a8d4b2052d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -602,6 +602,8 @@ config TARGET_LS2085ARDB config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 + select DM + select DM_GPIO help Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 7666bf98c5c..ae8187ad1cc 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -83,9 +83,7 @@ #endif #define CONFIG_HIKEY_GPIO -#define CONFIG_DM_GPIO #define CONFIG_CMD_GPIO -#define CONFIG_DM /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC -- cgit v1.3.1 From 9c71bcdc81b5d5a7acafb4e2b860e3ce68db6108 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 10 Sep 2015 21:55:17 +0100 Subject: ARM: hikey: hi6220: Migrate over to DM_SERIAL and use UART3 by default. Use DM for the pl01x serial driver on hikey. Also allow UART0 or UART3 to be chosen via Kconfig. By default we now output to UART3 as the latest version of ATF outputs to this UART. Also UART3 comes out on the LS connector, as opposed to UART0 which goes to a unpopulated header. As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and call the pinmux configuration code for the UART. Before we were relying on ATF having already configured the pin configuration. NB: Upstream Linux kernel doesn't yet support UART3, so serial console will still be output on UART0 when booting a upstream kernel. Signed-off-by: Peter Griffin Reviewed-by: Simon Glass --- arch/arm/Kconfig | 2 +- board/hisilicon/hikey/Kconfig | 7 +++++++ board/hisilicon/hikey/hikey.c | 43 +++++++++++++++++++++++++++++++++++++++++++ configs/hikey_defconfig | 1 + include/configs/hikey.h | 11 ++++------- 5 files changed, 56 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5a8d4b2052d..0b07e08db6c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -604,6 +604,7 @@ config TARGET_HIKEY select ARM64 select DM select DM_GPIO + select DM_SERIAL help Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. @@ -612,7 +613,6 @@ config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 select SUPPORT_SPL - config TARGET_LS1021ATWR bool "Support ls1021atwr" select CPU_V7 diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig index f7f1055e179..9171502a198 100644 --- a/board/hisilicon/hikey/Kconfig +++ b/board/hisilicon/hikey/Kconfig @@ -12,4 +12,11 @@ config SYS_SOC config SYS_CONFIG_NAME default "hikey" +config CONS_INDEX + int "UART used for console" + range 1 4 + default 4 + help + The hi6220 SoC has 5 UARTs. For example to use UART0 enter 1 here. + endif diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 99487472179..c4ae40bfb4e 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -69,6 +70,48 @@ U_BOOT_DEVICES(hi6220_gpios) = { DECLARE_GLOBAL_DATA_PTR; +static const struct pl01x_serial_platdata serial_platdata = { +#if CONFIG_CONS_INDEX == 1 + .base = HI6220_UART0_BASE, +#elif CONFIG_CONS_INDEX == 4 + .base = HI6220_UART3_BASE, +#else +#error "Unsuported console index value." +#endif + .type = TYPE_PL011, + .clock = 19200000 +}; + +U_BOOT_DEVICE(hikey_seriala) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_uart_init(void) +{ + switch (CONFIG_CONS_INDEX) { + case 1: + hi6220_pinmux_config(PERIPH_ID_UART0); + break; + case 4: + hi6220_pinmux_config(PERIPH_ID_UART3); + break; + default: + debug("%s: Unsupported UART selected\n", __func__); + return -1; + } + + return 0; +} + +int board_early_init_f(void) +{ + board_uart_init(); + return 0; +} +#endif + struct peri_sc_periph_regs *peri_sc = (struct peri_sc_periph_regs *)HI6220_PERI_BASE; diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 64a5929e9eb..70aa7085fd5 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -1,2 +1,3 @@ CONFIG_ARM=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 # CONFIG_CMD_IMLS is not set diff --git a/include/configs/hikey.h b/include/configs/hikey.h index ae8187ad1cc..b7c22e8c48a 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -31,6 +31,8 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT +#define CONFIG_BOARD_EARLY_INIT_F + /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -59,13 +61,8 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) -/* PL011 Serial Configuration */ -#define CONFIG_PL011_SERIAL - -#define CONFIG_PL011_CLOCK 19200000 -#define CONFIG_PL01x_PORTS {(void *)0xF8015000} -#define CONFIG_CONS_INDEX 0 - +/* Serial port PL010/PL011 through the device model */ +#define CONFIG_PL01X_SERIAL #define CONFIG_BAUDRATE 115200 #define CONFIG_CMD_USB -- cgit v1.3.1 From 05e682d46799de7be0ed3200ae2543d47a35fe7b Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 10 Sep 2015 21:55:18 +0100 Subject: ARM: hikey: Adjust SDRAM_1_SIZE to 0x3EFFFFFF DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE. Touching 0x3f000000 memory location from unsecure world causes the board to hang. Signed-off-by: Peter Griffin Reviewed-by: Simon Glass --- include/configs/hikey.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/hikey.h b/include/configs/hikey.h index b7c22e8c48a..3af02132f87 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -42,7 +42,8 @@ #define PHYS_SDRAM_1 0x00000000 /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ -#define PHYS_SDRAM_1_SIZE 0x3f000000 +#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -- cgit v1.3.1 From d7e8b2b98a0daad6bc2e91c2bc9f3414705b7f89 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 12 Sep 2015 11:50:08 -0600 Subject: arm: Remove da830evm board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-davinci/Kconfig | 3 - board/davinci/da8xxevm/Kconfig | 13 -- board/davinci/da8xxevm/da830evm.c | 209 ---------------------------- configs/da830evm_defconfig | 9 -- include/configs/da830evm.h | 279 -------------------------------------- 5 files changed, 513 deletions(-) delete mode 100644 board/davinci/da8xxevm/da830evm.c delete mode 100644 configs/da830evm_defconfig delete mode 100644 include/configs/da830evm.h (limited to 'include') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 8079fabd6f3..a8d3e2f2307 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -8,9 +8,6 @@ config TARGET_IPAM390 bool "IPAM390 board" select SUPPORT_SPL -config TARGET_DA830EVM - bool "DA830 EVM board" - config TARGET_DA850EVM bool "DA850 EVM board" select SUPPORT_SPL diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index 33bfcc3558e..7d0de1d0fa5 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -1,16 +1,3 @@ -if TARGET_DA830EVM - -config SYS_BOARD - default "da8xxevm" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "da830evm" - -endif - if TARGET_DA850EVM config SYS_BOARD diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c deleted file mode 100644 index c40587ff098..00000000000 --- a/board/davinci/da8xxevm/da830evm.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. - * - * Base on code from TI. Original Notices follow: - * - * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/ - * - * Modified for DA8xx EVM. - * - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * ----------------------------------------------------------------- - * - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - * ---------------------------------------------------------------------------- - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_DAVINCI_MMC -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static const struct pinmux_resource pinmuxes[] = { -#ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi0_pins_base), - PINMUX_ITEM(spi0_pins_scs0), - PINMUX_ITEM(spi0_pins_ena), -#endif - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(i2c0_pins), -#ifdef CONFIG_USB_DA8XX - PINMUX_ITEM(usb_pins), -#endif -#ifdef CONFIG_USE_NAND - PINMUX_ITEM(emifa_pins), - PINMUX_ITEM(emifa_pins_cs0), - PINMUX_ITEM(emifa_pins_cs2), - PINMUX_ITEM(emifa_pins_cs3), -#endif -#if defined(CONFIG_DRIVER_TI_EMAC) - PINMUX_ITEM(emac_pins_rmii), - PINMUX_ITEM(emac_pins_mdio), - PINMUX_ITEM(emac_pins_rmii_clk_source), -#endif -#ifdef CONFIG_DAVINCI_MMC - PINMUX_ITEM(mmc0_pins_8bit) -#endif -}; - -static const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_SPI0 }, /* Serial Flash */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_GPIO }, -#ifdef CONFIG_DAVINCI_MMC - { DAVINCI_LPSC_MMC_SD }, -#endif - -}; - -#ifdef CONFIG_DAVINCI_MMC -static struct davinci_mmc mmc_sd0 = { - .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, - .host_caps = MMC_MODE_8BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .version = MMC_CTLR_VERSION_2, -}; - -int board_mmc_init(bd_t *bis) -{ - mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); - - printf("%x\n", mmc_sd0.input_clk); - - /* Add slot-0 to mmc subsystem */ - return davinci_mmc_init(bis, &mmc_sd0); -} -#endif - -int board_init(void) -{ -#ifndef CONFIG_USE_IRQ - irq_init(); -#endif - -#ifdef CONFIG_NAND_DAVINCI - /* EMIFA 100MHz clock select */ - writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2, - &davinci_syscfg_regs->cfgchip3); - /* NAND CS setup */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(2) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(2) | - DAVINCI_ABCR_RHOLD(0) | - DAVINCI_ABCR_TA(2) | - DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->ab2cr); -#endif - - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* - * Power on required peripherals - * ARM does not have access by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) - return 1; - - /* setup the SUSPSRC for ARM to control emulation suspend */ - writel(readl(&davinci_syscfg_regs->suspsrc) & - ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART2), - &davinci_syscfg_regs->suspsrc); - - /* configure pinmux settings */ - if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) - return 1; - - /* enable the console UART */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart2_ctrl_regs->pwremu_mgmt); - - return(0); -} - - -#ifdef CONFIG_NAND_DAVINCI -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - - return 0; -} -#endif - -#if defined(CONFIG_DRIVER_TI_EMAC) - -#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */ - -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - u_int8_t mac_addr[6]; - u_int8_t switch_start_cmd[2] = { 0x01, 0x23 }; - struct eth_device *dev; - - /* Read Ethernet MAC address from EEPROM */ - if (dvevm_read_mac_address(mac_addr)) - /* set address env if not already set */ - davinci_sync_env_enetaddr(mac_addr); - - /* read the address back from env */ - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) - return -1; - - /* enable the Ethernet switch in the 3 port PHY */ - if (i2c_write(PHY_SW_I2C_ADDR, 0, 0, - switch_start_cmd, sizeof(switch_start_cmd))) { - printf("Ethernet switch start failed!\n"); - return -1; - } - - /* finally, initialise the driver */ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - dev = eth_get_dev(); - - /* provide the resulting addr to the driver */ - memcpy(dev->enetaddr, mac_addr, 6); - dev->write_hwaddr(dev); - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/configs/da830evm_defconfig b/configs/da830evm_defconfig deleted file mode 100644 index 3dda85779ae..00000000000 --- a/configs/da830evm_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_TARGET_DA830EVM=y -CONFIG_SYS_PROMPT="U-Boot > " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h deleted file mode 100644 index 7ac3224e6e9..00000000000 --- a/include/configs/da830evm.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (C) 2008 Texas Instruments, Inc - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_USE_SPIFLASH - -/* - * SoC Configuration - */ -#define CONFIG_MACH_DAVINCI_DA830_EVM -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA830 /* TI DA830 SoC */ -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0xc1080000 - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Start */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (32 << 20)) -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* - * I2C Configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ - -/* - * I2C EEPROM definitions for catalyst 24W256 EEPROM chip - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * Flash & Environment - */ -#ifdef CONFIG_USE_NAND -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_OFFSET (512 << 10) -#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#endif - -#ifdef CONFIG_USE_NOR -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE -#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ -#define CONFIG_SYS_FLASH_SPL_ACCESS -#endif - -#ifdef CONFIG_USE_SPIFLASH -#undef CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#define CONFIG_ENV_OFFSET (256 << 10) -#define CONFIG_ENV_SECT_SIZE 4096 -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -#endif - -/* - * USB configuration - */ -#define CONFIG_USB_DA8XX /* Platform hookup to MUSB controller */ -#define CONFIG_USB_MUSB_HCD - -/* - * U-Boot general configuration - */ -#undef CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "" -#define CONFIG_BOOTDELAY 3 - -/* - * U-Boot commands - */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#ifdef CONFIG_USE_NAND -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#endif - -#ifdef CONFIG_USE_SPIFLASH -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#endif - -/* SD/MMC configuration */ -#ifndef CONFIG_USE_NAND -#define CONFIG_MMC -#define CONFIG_DAVINCI_MMC_SD1 -#define CONFIG_GENERIC_MMC -#define CONFIG_DAVINCI_MMC -#endif - -/* - * Enable MMC commands only when - * MMC support is present - */ -#if defined(CONFIG_MMC) || defined(CONFIG_USB_DA8XX) -#define CONFIG_DOS_PARTITION /* include support for FAT/storage */ -#define CONFIG_CMD_FAT /* include support for FAT cmd */ -#endif - -#ifdef CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#endif - -#if !defined(CONFIG_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV -#endif - -#ifdef CONFIG_USB_DA8XX - -#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */ -#define CONFIG_CMD_USB /* include support for usb cmd */ - -#define CONFIG_USB_STORAGE /* MSC class support */ -#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ - -#ifdef CONFIG_USB_KEYBOARD /* HID class support */ -#define CONFIG_SYS_USB_EVENT_POLL -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ - -#endif /* CONFIG_USB_MUSB_HCD */ - -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "DA830EVM" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_DA8XX */ - -#ifdef CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=davinci_nand.1" -#define PART_BOOT "512k(bootloader)ro," -#define PART_PARAMS "512k(params)ro," -#define PART_KERNEL "4m(kernel)," -#define PART_REST "-(filesystem)" -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From b352182a0050574c4068b7b8baa9dde1eae2757a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 12 Sep 2015 11:50:09 -0600 Subject: arm: Remove wireless_space board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- arch/arm/mach-kirkwood/Kconfig | 4 - board/LaCie/wireless_space/Kconfig | 12 -- board/LaCie/wireless_space/MAINTAINERS | 6 - board/LaCie/wireless_space/Makefile | 12 -- board/LaCie/wireless_space/kwbimage.cfg | 71 ----------- board/LaCie/wireless_space/wireless_space.c | 165 ------------------------- configs/wireless_space_defconfig | 6 - include/configs/wireless_space.h | 179 ---------------------------- 8 files changed, 455 deletions(-) delete mode 100644 board/LaCie/wireless_space/Kconfig delete mode 100644 board/LaCie/wireless_space/MAINTAINERS delete mode 100644 board/LaCie/wireless_space/Makefile delete mode 100644 board/LaCie/wireless_space/kwbimage.cfg delete mode 100644 board/LaCie/wireless_space/wireless_space.c delete mode 100644 configs/wireless_space_defconfig delete mode 100644 include/configs/wireless_space.h (limited to 'include') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index c053602a509..aab5d19b5fb 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -34,9 +34,6 @@ config TARGET_NET2BIG_V2 config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" -config TARGET_WIRELESS_SPACE - bool "LaCie Wireless_space Board" - config TARGET_IB62X0 bool "ib62x0 Board" @@ -64,7 +61,6 @@ source "board/iomega/iconnect/Kconfig" source "board/keymile/km_arm/Kconfig" source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig" -source "board/LaCie/wireless_space/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig deleted file mode 100644 index 75a2fc5a756..00000000000 --- a/board/LaCie/wireless_space/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WIRELESS_SPACE - -config SYS_BOARD - default "wireless_space" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "wireless_space" - -endif diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS deleted file mode 100644 index c32ecb8b73c..00000000000 --- a/board/LaCie/wireless_space/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WIRELESS_SPACE BOARD -M: Albert ARIBAUD -S: Maintained -F: board/LaCie/wireless_space/ -F: include/configs/wireless_space.h -F: configs/wireless_space_defconfig diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile deleted file mode 100644 index 90a84f48926..00000000000 --- a/board/LaCie/wireless_space/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := wireless_space.o ../common/common.o diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg deleted file mode 100644 index 037248b3c60..00000000000 --- a/board/LaCie/wireless_space/kwbimage.cfg +++ /dev/null @@ -1,71 +0,0 @@ -# -# Copyright (C) 2012 Albert ARIBAUD -# -# Based on netspace_v2 kwbimage.cfg: -# Copyright (C) 2011 Simon Guinot -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand # Boot from NAND flash -NAND_PAGE_SIZE 800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Values taken from image original LaCie U-Boot header dump! - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register - -DATA 0xFFD01404 0x37743000 # DDR Controller Control Low - -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) - -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) - -DATA 0xFFD01410 0x0000CCCC # DDR Address Control - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control - -DATA 0xFFD01418 0x00000000 # DDR Operation - -DATA 0xFFD0141C 0x00000662 # DDR Mode - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High - -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) - -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -DATA 0xFFD20134 0x66666666 -DATA 0xFFD20138 0x66666666 -DATA 0xFFD10000 0x01112222 -DATA 0xFFD1000C 0x00000000 -DATA 0xFFD10104 0x00000000 -DATA 0xFFD10100 0x40000000 -# End of Header extension -DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c deleted file mode 100644 index 8620e4b5d13..00000000000 --- a/board/LaCie/wireless_space/wireless_space.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#include "../common/common.h" -#include "netdev.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* GPIO configuration: start FAN at low speed, USB and HDD */ - -#define WIRELESS_SPACE_OE_LOW 0xFF006808 -#define WIRELESS_SPACE_OE_HIGH 0x0000F989 -#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 -#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 - -#define WIRELESS_SPACE_REAR_BUTTON 13 -#define WIRELESS_SPACE_FRONT_BUTTON 43 - -const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Fan speed (bit 1) */ - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP13_GPIO, /* Red led */ - MPP14_GPIO, /* USB fuse */ - MPP15_SATA0_ACTn, - MPP16_GPIO, /* SATA 0 power */ - MPP17_GPIO, /* SATA 1 power */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, /* Gigabit Ethernet 1 */ - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GE1_8, - MPP29_GE1_9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GE1_14, - MPP35_GE1_15, - MPP36_GPIO, /* Fan speed (bit 2) */ - MPP37_GPIO, /* Fan speed (bit 0) */ - MPP38_GPIO, /* Fan power */ - MPP39_GPIO, /* Fan rotation fail */ - MPP40_GPIO, /* Ethernet switch link */ - MPP41_GPIO, /* USB enable host vbus */ - MPP42_GPIO, /* LED clock control */ - MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ - MPP44_GPIO, /* Red LED on/off */ - MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ - MPP46_GPIO, /* Green LED on/off */ - MPP47_GPIO, /* LED (blue, green) SATA activity blink */ - MPP48_GPIO, /* Blue LED on/off */ - 0 -}; - -struct mv88e61xx_config swcfg = { - .name = "egiga0", - .vlancfg = MV88E61XX_VLANCFG_ROUTER, - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, - .led_init = MV88E61XX_LED_INIT_EN, - .mdip = MV88E61XX_MDIP_NOCHANGE, - .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = 0x20, - .ports_enabled = 0x3F, -}; - -int board_early_init_f(void) -{ - /* Gpio configuration */ - mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - /* Machine number */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* Boot parameters address */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) - if (!getenv("ethaddr")) { - uchar mac[6]; - if (lacie_read_mac_address(mac) == 0) - eth_setenv_enetaddr("ethaddr", mac); - } -#endif - return 0; -} -#endif - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and initialize PHY */ -void reset_phy(void) -{ - /* configure switch on egiga0 */ - mv88e61xx_switch_initialize(&swcfg); -} -#endif - -#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) -/* Return GPIO button status */ -static int -do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (strcmp(argv[1], "button") == 0) { - if (strcmp(argv[2], "rear") == 0) - /* invert GPIO result for intuitive while/until use */ - return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); - else if (strcmp(argv[2], "front") == 0) - return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); - else - return -1; - } else { - return -1; - } -} - -U_BOOT_CMD(ws, 3, 0, do_ws, - "Return GPIO button status 0=off 1=on", - "- ws button rear|front: test buttons' states\n" -); -#endif diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig deleted file mode 100644 index 5551d27d6cb..00000000000 --- a/configs/wireless_space_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_TARGET_WIRELESS_SPACE=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h deleted file mode 100644 index 191ac1b73f1..00000000000 --- a/include/configs/wireless_space.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2011 Albert ARIBAUD - * - * Based on the netspace_v2 code which is - * Copyright (C) 2011 Simon Guinot - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_WIRELESS_SPACE_H -#define _CONFIG_WIRELESS_SPACE_H - -/* - * Machine number definition - */ -#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ -#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE -#define CONFIG_IDENT_STRING " Wireless Space" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -/* SoC name */ -#define CONFIG_KW88F6281 -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB - -/* - * Core clock definition - */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -/* - * SDRAM configuration - */ -#define CONFIG_NR_DRAM_BANKS 1 - -/* - * Different SDRAM configuration and size for some of the boards derived - * from the Network Space v2 - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Remove or override few declarations from mv-common.h */ -#undef CONFIG_RBTREE -#undef CONFIG_SYS_IDE_MAXBUS -#undef CONFIG_SYS_IDE_MAXDEVICE -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ -#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ -#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ -#define CONFIG_MII -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_NETCONSOLE -#define CONFIG_MV88E61XX_SWITCH -#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE -#define CONFIG_MV88E61XX_CMD -#define CONFIG_CMD_TFTPPUT -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /* CONFIG_MVSATA_IDE */ - -/* - * Enable GPI0 support - */ -#define CONFIG_KIRKWOOD_GPIO - -/* - * Enable I2C support - */ -#ifdef CONFIG_CMD_I2C -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ -#endif /* CONFIG_CMD_I2C */ - -/* - * Partition support - */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - -/* - * File systems support - */ -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - -/* - * Use the HUSH parser - */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Console configuration - */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* - * Enable device tree support - */ -#define CONFIG_OF_LIBFDT - -/* - * Environment variables configurations - */ - -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ -#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ - -/* - * Board-specific command to make using buttons etc easier - */ - -#define CONFIG_WIRELESS_SPACE_CMD - -/* - * Default environment variables - */ -#define CONFIG_PREBOOT - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#define CONFIG_BOOTCOMMAND \ - "if run usbload || run diskload; then bootm; fi" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootfile=uImage\0" \ - "loadaddr=0x800000\0" \ - "autoload=no\0" \ - "netconsole=" \ - "set stdin $stdin,nc; " \ - "set stdout $stdout,nc; " \ - "set stderr $stderr,nc;\0" \ - "diskload=ide reset && " \ - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ - "usbload=usb start && " \ - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ - "preboot=" \ - "dhcp && run netconsole\0" - -#endif /* _CONFIG_WIRELESS_SPACE_H */ -- cgit v1.3.1 From daf6d399aef850447f55820457e4dbce91a0521d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Sep 2015 17:29:33 +0200 Subject: sunxi: sunxi-common.h cleanup Move some #define-s around from one #ifdef block to another to reduce the number of #ifdef blocks (note this causes no functional changes even though the conditions are not always exactly the same) and move generic #include statements to the top. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- include/configs/sunxi-common.h | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 48cc4ed6f62..7c1507ba04f 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -13,6 +13,7 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H +#include #include #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT @@ -39,23 +40,14 @@ #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#include /* get chip and board defs */ - -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) -# define CONFIG_DW_SERIAL -#endif - -/* - * Display CPU information - */ -#define CONFIG_DISPLAY_CPUINFO - /* Serial & console */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #define CONFIG_SYS_NS16550_CLK 24000000 -#ifndef CONFIG_DM_SERIAL +#ifdef CONFIG_DM_SERIAL +# define CONFIG_DW_SERIAL +#else # define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE @@ -65,6 +57,7 @@ #endif /* CPU */ +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_CACHELINE_SIZE 64 /* -- cgit v1.3.1 From 5c965ed901c09bd046a99c7dc9269e3be2829604 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Sep 2015 17:16:54 +0200 Subject: sunxi: Tweak various memory addresses For the upcoming nand support we need a bigger heap, esp. ubi[fs] uses quite a bit of memory, increase the heap size to 64 MB. Our video code returns unused reserved framebuffer memory to the kernel before booting it. Drop the #ifdef-ery and simply always reserve 16 MB. Adjust bootm_size for the above changes. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- include/configs/sunxi-common.h | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7c1507ba04f..648e4e86564 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -145,8 +145,8 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ #endif -/* 4MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) +/* 64MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) /* * Miscellaneous configurable options @@ -275,11 +275,7 @@ extern int soft_i2c_gpio_scl; * The amount of RAM to keep free at the top of RAM when relocating u-boot, * to use as framebuffer. This must be a multiple of 4096. */ -#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 -#define CONFIG_SUNXI_MAX_FB_SIZE (12 << 20) -#else -#define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20) -#endif +#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) /* Do we want to initialize a simple FB? */ #define CONFIG_VIDEO_DT_SIMPLEFB @@ -386,12 +382,12 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ /* - * 240M RAM (256M minimum minus space for the framebuffer), + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end. */ #define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0xf000000\0" \ + "bootm_size=0xa000000\0" \ "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \ "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \ "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \ -- cgit v1.3.1 From f3b589c09b43a231706f11ab391e5ea7f9670f12 Mon Sep 17 00:00:00 2001 From: Bernhard Nortmann Date: Thu, 17 Sep 2015 18:52:53 +0200 Subject: sunxi: add "fel" boot target This patch makes use of the previous changes to add a new "fel" boot target for sunxi boards. When booting via FEL, it's often desirable to work around the absence of other (usable) boot devices - or to be able to override them, deviating from the standard boot sequence. To achieve this, the "fel" boot target gets the highest priority, but won't actually do anything unless certain criteria are met. The "bootcmd_fel" implementation proposed here first tests if an actual FEL boot takes place (using the "fel_booted" env var), and secondly checks that "fel_scriptaddr" was set (originating from the 'loader', i.e. the sunxi-tools fel utility). If both checks pass, then it will try to execute the boot script (boot.scr) at the given address. In case of an error (e.g. an invalid image), the source command might return "false", causing "distro_bootcmd" to proceed with the next boot target. Signed-off-by: Bernhard Nortmann Acked-by: Siarhei Siamashka Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 648e4e86564..e1ba7914cda 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -412,7 +412,18 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +/* FEL boot support, auto-execute boot.scr if a script address was provided */ +#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ + "bootcmd_fel=" \ + "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ + "echo '(FEL boot)'; " \ + "source ${fel_scriptaddr}; " \ + "fi\0" +#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ + "fel " + #define BOOT_TARGET_DEVICES(func) \ + func(FEL, fel, na) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ -- cgit v1.3.1 From eaa8a195cc2372349276bf7d581a9e1e2cc83511 Mon Sep 17 00:00:00 2001 From: Bernhard Nortmann Date: Mon, 14 Sep 2015 15:29:43 +0200 Subject: net: expose eth_is_active() function to test network device state The previous eth_device struct returned by eth_get_dev() allowed code to directly query the state member field. However, with CONFIG_DM_ETH this data gets encapsulated (i.e. private), and eth_get_dev() returns a udevice struct 'abstraction' instead. This breaks legacy code relying on the former behaviour - e.g. netconsole. (see http://lists.denx.de/pipermail/u-boot/2015-June/216528.html) The patch introduces a method to retrieve the ethernet device state in a 'clean' and uniform way, supporting both legacy code and driver model. The new function eth_is_active() accepts a device struct pointer and tests it for ETH_STATE_ACTIVE. Signed-off-by: Bernhard Nortmann Reviewed-by: Simon Glass Acked-by: Joe Hershberger --- include/net.h | 4 ++++ net/eth.c | 18 +++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/net.h b/include/net.h index f1671e38dea..3a787cc4e98 100644 --- a/include/net.h +++ b/include/net.h @@ -149,7 +149,9 @@ struct udevice *eth_get_dev(void); /* get the current device */ */ struct udevice *eth_get_dev_by_name(const char *devname); unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ + /* Used only when NetConsole is enabled */ +int eth_is_active(struct udevice *dev); /* Test device for active state */ int eth_init_state_only(void); /* Set active state */ void eth_halt_state_only(void); /* Set passive state */ #endif @@ -195,6 +197,8 @@ static inline unsigned char *eth_get_ethaddr(void) return NULL; } +/* Used only when NetConsole is enabled */ +int eth_is_active(struct eth_device *dev); /* Test device for active state */ /* Set active state */ static inline __attribute__((always_inline)) int eth_init_state_only(void) { diff --git a/net/eth.c b/net/eth.c index 26520d30388..2e24b55726b 100644 --- a/net/eth.c +++ b/net/eth.c @@ -389,6 +389,17 @@ void eth_halt(void) priv->state = ETH_STATE_PASSIVE; } +int eth_is_active(struct udevice *dev) +{ + struct eth_device_priv *priv; + + if (!dev || !device_active(dev)) + return 0; + + priv = dev_get_uclass_priv(dev); + return priv->state == ETH_STATE_ACTIVE; +} + int eth_send(void *packet, int length) { struct udevice *current; @@ -580,7 +591,7 @@ UCLASS_DRIVER(eth) = { .per_device_auto_alloc_size = sizeof(struct eth_device_priv), .flags = DM_UC_FLAG_SEQ_ALIAS, }; -#endif +#endif /* #ifdef CONFIG_DM_ETH */ #ifndef CONFIG_DM_ETH @@ -918,6 +929,11 @@ void eth_halt(void) eth_current->state = ETH_STATE_PASSIVE; } +int eth_is_active(struct eth_device *dev) +{ + return dev && dev->state == ETH_STATE_ACTIVE; +} + int eth_send(void *packet, int length) { if (!eth_current) -- cgit v1.3.1 From ac1eefebf515035f7b0b14ed06baf36b99da6b35 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Wed, 16 Sep 2015 11:34:14 +0800 Subject: ARM: at91: sama5: add support for CONFIG_ENV_IS_IN_MMC If defined CONFIG_ENV_IS_IN_MMC, then u-boot environment is saved in mmc's raw sectors. Otherwise, u-boot environment is saved as a file: uboot.env. Signed-off-by: Josh Wu Reviewed-by: Bo Shen --- include/configs/at91-sama5_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 3d6b0ae0c32..a5990cec030 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -53,6 +53,13 @@ #define CONFIG_CMD_DHCP #ifdef CONFIG_SYS_USE_MMC + +#ifdef CONFIG_ENV_IS_IN_MMC +/* Use raw reserved sectors to save environment */ +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else /* u-boot env in sd/mmc card */ #define CONFIG_ENV_IS_IN_FAT #define CONFIG_FAT_WRITE @@ -60,6 +67,7 @@ #define FAT_ENV_DEVICE_AND_PART "0" #define FAT_ENV_FILE "uboot.env" #define CONFIG_ENV_SIZE 0x4000 +#endif #define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \ "setenv dtb_name at91-${board_name}.dtb; " \ -- cgit v1.3.1 From aca5d0830aab91680c2ef44e9cb2999cbea19f2f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 28 Sep 2015 11:36:05 +0200 Subject: arm, at91: small updates for the smartweb board - add CONFIG_BOOT_RETRY_TIME to 30 - fex LED colors - fix button pressed combination - add CONFIG_USB_HOST_ETHER CONFIG_USB_ETHER_ASIX CONFIG_USB_ETHER_MCS7830 Signed-off-by: Heiko Schocher Signed-off-by: Matthias Michel --- board/siemens/smartweb/smartweb.c | 25 ++++++++++++++----------- include/configs/smartweb.h | 4 ++++ 2 files changed, 18 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 2d424882a9c..d82f1b73a71 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -90,7 +90,8 @@ static void smartweb_macb_hw_init(void) pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), &pioa->pudr); at91_phy_reset(); @@ -101,7 +102,8 @@ static void smartweb_macb_hw_init(void) pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), &pioa->puer); /* Initialize EMAC=MACB hardware */ @@ -141,13 +143,6 @@ int board_early_init_f(void) int board_init(void) { - /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - smartweb_nand_hw_init(); -#ifdef CONFIG_MACB - smartweb_macb_hw_init(); -#endif /* power LED red */ at91_set_gpio_output(AT91_PIN_PC6, 0); at91_set_gpio_output(AT91_PIN_PC7, 1); @@ -163,6 +158,13 @@ int board_init(void) at91_udc_probe(&board_udc_data); #endif + /* Adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + smartweb_nand_hw_init(); +#ifdef CONFIG_MACB + smartweb_macb_hw_init(); +#endif return 0; } @@ -197,6 +199,7 @@ void matrix_init(void) void spl_board_init(void) { + /* power LED orange */ at91_set_gpio_output(AT91_PIN_PC6, 1); at91_set_gpio_output(AT91_PIN_PC7, 1); /* alarm LED orange */ @@ -212,8 +215,8 @@ void spl_board_init(void) /* check if both button are pressed */ if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && - at91_get_gpio_value(AT91_PIN_PA29) == 0) { - debug("Recovery button pressed\n"); + at91_get_gpio_value(AT91_PIN_PA29) == 0) { + smartweb_nand_hw_init(); nand_init(); spl_nand_erase_one(0, 0); } diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d189c3fde97..e11c016aedb 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -117,6 +117,9 @@ * */ #define CONFIG_MACB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_RMII /* use reduced MII inteface */ #define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ #define CONFIG_AT91_WANTS_COMMON_PHY @@ -182,6 +185,7 @@ /* General Boot Parameter */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ -- cgit v1.3.1 From b9a1609915f68bad51b15cb12546723519a9be41 Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Thu, 1 Oct 2015 22:48:04 +0200 Subject: tbs2910: explicitly set boot address Set missing boot address in bootm command. This fixes the error: Wrong Image Format for bootm command ERROR: can't get kernel image! Reported-by: Uwe Scheffler Signed-off-by: Soeren Moch Tested-by: Uwe Scheffler --- include/configs/tbs2910.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 70b440340ff..4534695598b 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -190,7 +190,7 @@ "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ "rdinit=/sbin/init enable_wait_mode=off\0" \ "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ - "mmc read 0x10800000 0x800 0x4000; bootm\0" \ + "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ "run bootargs_upd; " \ -- cgit v1.3.1 From 03544c6640e8a969f8409eac637f4780e1eabb1d Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\\\(3ADEV\\\\)" Date: Mon, 21 Sep 2015 22:43:38 +0200 Subject: I2C: mxc_i2c: make I2C1 and I2C2 optional The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) --- README | 8 ++++++-- drivers/i2c/mxc_i2c.c | 6 ++++++ include/configs/apf27.h | 2 ++ include/configs/aristainetos-common.h | 2 ++ include/configs/cgtqmx6eval.h | 2 ++ include/configs/cm_fx6.h | 2 ++ include/configs/embestmx6boards.h | 2 ++ include/configs/flea3.h | 2 ++ include/configs/gw_ventana.h | 2 ++ include/configs/imx31_phycore.h | 2 ++ include/configs/ls1021aqds.h | 2 ++ include/configs/ls1021atwr.h | 2 ++ include/configs/ls2085a_common.h | 2 ++ include/configs/m53evk.h | 2 ++ include/configs/mx25pdk.h | 2 ++ include/configs/mx35pdk.h | 2 ++ include/configs/mx53ard.h | 2 ++ include/configs/mx53evk.h | 2 ++ include/configs/mx53loco.h | 2 ++ include/configs/mx53smd.h | 2 ++ include/configs/mx6qsabreauto.h | 2 ++ include/configs/mx6sabresd.h | 2 ++ include/configs/mx6slevk.h | 2 ++ include/configs/mx6sxsabresd.h | 2 ++ include/configs/mx6ul_14x14_evk.h | 2 ++ include/configs/mx7dsabresd.h | 2 +- include/configs/nitrogen6x.h | 2 ++ include/configs/novena.h | 2 ++ include/configs/ot1200.h | 2 ++ include/configs/platinum.h | 2 ++ include/configs/tbs2910.h | 2 ++ include/configs/titanium.h | 2 ++ include/configs/tqma6.h | 2 ++ include/configs/usbarmory.h | 2 ++ include/configs/vf610twr.h | 2 ++ include/configs/wandboard.h | 2 ++ include/configs/warp.h | 2 ++ include/configs/woodburn_common.h | 2 ++ 38 files changed, 83 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/README b/README index a13705ae7a8..c22b60b49bc 100644 --- a/README +++ b/README @@ -2359,16 +2359,20 @@ CBFS (Coreboot Filesystem) support - drivers/i2c/i2c_mxc.c - activate this driver with CONFIG_SYS_I2C_MXC + - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 + - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 + - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 + - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE + - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED + - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE If those defines are not set, default value is 100000 for speed, and 0 for slave. - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - drivers/i2c/rcar_i2c.c: - activate this driver with CONFIG_SYS_I2C_RCAR diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f1056e21a2c..0f977d706d4 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -612,16 +612,22 @@ static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) /* * Register mxc i2c adapters */ +#ifdef CONFIG_SYS_I2C_MXC_I2C1 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C1_SPEED, CONFIG_SYS_MXC_I2C1_SLAVE, 0) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C2 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C2_SPEED, CONFIG_SYS_MXC_I2C2_SLAVE, 1) +#endif + #ifdef CONFIG_SYS_I2C_MXC_I2C3 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 43fbdd3d11d..49fbcac7760 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -317,6 +317,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 20afdd6bc07..f03297e1377 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -189,6 +189,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7f diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 7158ab0f2b8..e0aa4b08949 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -39,6 +39,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 12734a10bfd..05132047b78 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -198,6 +198,8 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_MXC_I2C3_SPEED 400000 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 58cee96ac31..f55ba9f7066 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -33,6 +33,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 5b4b0119573..f646feefa9e 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -52,6 +52,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ #define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 231bea7855c..484d76305fd 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -107,6 +107,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 86f327c8278..3bea71b969e 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -38,6 +38,8 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b44f3264e31..f73900fe30c 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -389,6 +389,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 7dcb719b013..f6bd5fcece1 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -275,6 +275,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 2dbb5f70a98..55b909ceaca 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -97,6 +97,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 35058e222ac..8853d8fcc06 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -172,6 +172,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ #endif diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index bd7216e47b6..04140865f48 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -115,6 +115,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* RTC */ #define CONFIG_RTC_IMXDI diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index c9983f3f58c..6bfdaa6432f 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -42,6 +42,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 0479195d6d7..b889c254ccb 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 82c8af802f0..4f304ed89f9 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -41,6 +41,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Configs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index ad2629da723..3a65861e5e9 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -76,6 +76,8 @@ /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Controller */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index bcdb0543605..e46f2eeecbb 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -38,6 +38,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 11cf538b0ad..1c998058a94 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -51,6 +51,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5f635ca6c5a..e9e3b27f363 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -44,6 +44,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 51b297a1a35..ae395035423 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -35,6 +35,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 381eaa24d53..edf7d3f93a0 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -127,6 +127,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 465ddee8817..d5faae6a7b9 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -54,6 +54,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC only for 9X9 EVK */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index ada5de8acaa..f16f9c1271e 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -47,7 +47,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index dd4cb0f8931..b1137713e1e 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -43,6 +43,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID diff --git a/include/configs/novena.h b/include/configs/novena.h index 0970fd75483..cd426be18c6 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -102,6 +102,8 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MXC diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 0d06fce1eb2..426ec7246f7 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -44,6 +44,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/platinum.h b/include/configs/platinum.h index d65143240b6..bb7e8451838 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -45,6 +45,8 @@ /* I2C config */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 4534695598b..17b0213362e 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -167,6 +167,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID diff --git a/include/configs/titanium.h b/include/configs/titanium.h index 1b4ca295bc8..acfa84ab2cd 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -33,6 +33,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f7fade12f1b..295e16303ca 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -62,6 +62,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 4a7702cd092..714e3e2ca21 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -67,6 +67,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* Fuse */ #define CONFIG_CMD_FUSE diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index c5131af3403..324ba8f0ccd 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -110,6 +110,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index f4e9cf20c53..6e8aec267de 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -37,6 +37,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/warp.h b/include/configs/warp.h index fa102bbae72..3e9a5a3ef37 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -98,6 +98,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 5d9f5297ce8..fc4656567da 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -47,6 +47,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MXC_SPI -- cgit v1.3.1 From 931a1d2a14191266b675fe9db9afd227e372a919 Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Mon, 21 Sep 2015 22:43:39 +0200 Subject: vf610: add support for Phytec PCM052 Devices supported are: - NFC (NAND FLASH) - MMC - QSPI (SPI NOR FLASH) - I2C (only bus 2) - I2C RTC - I2C EEPROM - FEC Patch-series: 2 - remove useless CONFIG_SYS_SPD_BUS_NUM from config - remove include of config_cmd_default.h - remove duplicate CONFIG_CMD_NET Signed-off-by: Albert ARIBAUD (3ADEV) --- arch/arm/Kconfig | 5 + board/phytec/pcm052/Kconfig | 15 ++ board/phytec/pcm052/MAINTAINERS | 6 + board/phytec/pcm052/Makefile | 7 + board/phytec/pcm052/imximage.cfg | 17 ++ board/phytec/pcm052/pcm052.c | 515 +++++++++++++++++++++++++++++++++++++++ configs/pcm052_defconfig | 6 + include/configs/pcm052.h | 231 ++++++++++++++++++ 8 files changed, 802 insertions(+) create mode 100644 board/phytec/pcm052/Kconfig create mode 100644 board/phytec/pcm052/MAINTAINERS create mode 100644 board/phytec/pcm052/Makefile create mode 100644 board/phytec/pcm052/imximage.cfg create mode 100644 board/phytec/pcm052/pcm052.c create mode 100644 configs/pcm052_defconfig create mode 100644 include/configs/pcm052.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0b07e08db6c..3a336e6fdfe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -538,6 +538,10 @@ config TARGET_COLIBRI_VF bool "Support Colibri VF50/61" select CPU_V7 +config TARGET_PCM052 + bool "Support pcm-052" + select CPU_V7 + config ARCH_ZYNQ bool "Xilinx Zynq Platform" select CPU_V7 @@ -753,6 +757,7 @@ source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" +source "board/phytec/pcm052/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig new file mode 100644 index 00000000000..d67a69a747a --- /dev/null +++ b/board/phytec/pcm052/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PCM052 + +config SYS_BOARD + default "pcm052" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "vf610" + +config SYS_CONFIG_NAME + default "pcm052" + +endif diff --git a/board/phytec/pcm052/MAINTAINERS b/board/phytec/pcm052/MAINTAINERS new file mode 100644 index 00000000000..a877436bd38 --- /dev/null +++ b/board/phytec/pcm052/MAINTAINERS @@ -0,0 +1,6 @@ +PCM052 BOARD +M: Albert ARIBAUD (3ADEV) +S: Maintained +F: board/phytec/pcm052/ +F: include/configs/pcm052.h +F: configs/pcm052_defconfig diff --git a/board/phytec/pcm052/Makefile b/board/phytec/pcm052/Makefile new file mode 100644 index 00000000000..144f4e73161 --- /dev/null +++ b/board/phytec/pcm052/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pcm052.o diff --git a/board/phytec/pcm052/imximage.cfg b/board/phytec/pcm052/imximage.cfg new file mode 100644 index 00000000000..f5a97475cb3 --- /dev/null +++ b/board/phytec/pcm052/imximage.cfg @@ -0,0 +1,17 @@ +/* + * Copyright 2015 3ADEV + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Offset 0x400, valid for both SD and NAND boot */ +BOOT_OFFSET FLASH_OFFSET_STANDARD diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c new file mode 100644 index 00000000000..e4f61e1b927 --- /dev/null +++ b/board/phytec/pcm052/pcm052.c @@ -0,0 +1,515 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h + * do not match our settings. Let us (re)define our own settings here. + */ + +#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm +#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) +#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_INPUT_DIFFERENTIAL) + +enum { + PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), + PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), + PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), + PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), + PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), +}; + +static struct ddrmc_cr_setting pcm052_cr_settings[] = { + /* not in the datasheets, but in the original code */ + { 0x00002000, 105 }, + { 0x00000020, 110 }, + /* AXI */ + { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 }, + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, + { DDRMC_CR120_AXI0_PRI1_RPRI(2) | + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, + { DDRMC_CR121_AXI0_PRI3_RPRI(2) | + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | + DDRMC_CR122_AXI0_PRIRLX(100), 122 }, + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, + { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, + { DDRMC_CR126_PHY_RDLAT(11), 126 }, + { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 }, + { DDRMC_CR137_PHYCTL_DL(2), 137 }, + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | + DDRMC_CR139_PHY_WRLV_DLL(3) | + DDRMC_CR139_PHY_WRLV_EN(3), 139 }, + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 }, + { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 }, + { DDRMC_CR158_TWR(6), 158 }, + { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) | + DDRMC_CR161_TODTH_WR(6), 161 }, + /* end marker */ + { 0, -1 } +}; + +/* PHY settings -- most of them differ from default in imx-regs.h */ + +#define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213 +#define PCM052_DDRMC_PHY_CTRL 0x00290000 +#define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00 +#define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020 + +static struct ddrmc_phy_setting pcm052_phy_settings[] = { + { PCM052_DDRMC_PHY_DQ_TIMING, 0 }, + { PCM052_DDRMC_PHY_DQ_TIMING, 16 }, + { PCM052_DDRMC_PHY_DQ_TIMING, 32 }, + { PCM052_DDRMC_PHY_DQ_TIMING, 48 }, + { DDRMC_PHY_DQS_TIMING, 1 }, + { DDRMC_PHY_DQS_TIMING, 17 }, + { DDRMC_PHY_DQS_TIMING, 33 }, + { DDRMC_PHY_DQS_TIMING, 49 }, + { PCM052_DDRMC_PHY_CTRL, 2 }, + { PCM052_DDRMC_PHY_CTRL, 18 }, + { PCM052_DDRMC_PHY_CTRL, 34 }, + { DDRMC_PHY_MASTER_CTRL, 3 }, + { DDRMC_PHY_MASTER_CTRL, 19 }, + { DDRMC_PHY_MASTER_CTRL, 35 }, + { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 }, + { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 }, + { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 }, + { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 }, + { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 }, + + /* end marker */ + { 0, -1 } +}; + +int dram_init(void) +{ + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 4, + .tfaw = 18, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 14040, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 10, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 1542, + .trfc = 64, + .tref_int = 5, + .tpdex = 3, + .txpdll = 10, + .txsnr = 68, + .txsr = 506, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; + + static const iomux_v3_cfg_t pcm052_pads[] = { + PCM052_VF610_PAD_DDR_A15__DDR_A_15, + PCM052_VF610_PAD_DDR_A14__DDR_A_14, + PCM052_VF610_PAD_DDR_A13__DDR_A_13, + PCM052_VF610_PAD_DDR_A12__DDR_A_12, + PCM052_VF610_PAD_DDR_A11__DDR_A_11, + PCM052_VF610_PAD_DDR_A10__DDR_A_10, + PCM052_VF610_PAD_DDR_A9__DDR_A_9, + PCM052_VF610_PAD_DDR_A8__DDR_A_8, + PCM052_VF610_PAD_DDR_A7__DDR_A_7, + PCM052_VF610_PAD_DDR_A6__DDR_A_6, + PCM052_VF610_PAD_DDR_A5__DDR_A_5, + PCM052_VF610_PAD_DDR_A4__DDR_A_4, + PCM052_VF610_PAD_DDR_A3__DDR_A_3, + PCM052_VF610_PAD_DDR_A2__DDR_A_2, + PCM052_VF610_PAD_DDR_A1__DDR_A_1, + PCM052_VF610_PAD_DDR_A0__DDR_A_0, + PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, + PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, + PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, + PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, + PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, + PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, + PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, + PCM052_VF610_PAD_DDR_D15__DDR_D_15, + PCM052_VF610_PAD_DDR_D14__DDR_D_14, + PCM052_VF610_PAD_DDR_D13__DDR_D_13, + PCM052_VF610_PAD_DDR_D12__DDR_D_12, + PCM052_VF610_PAD_DDR_D11__DDR_D_11, + PCM052_VF610_PAD_DDR_D10__DDR_D_10, + PCM052_VF610_PAD_DDR_D9__DDR_D_9, + PCM052_VF610_PAD_DDR_D8__DDR_D_8, + PCM052_VF610_PAD_DDR_D7__DDR_D_7, + PCM052_VF610_PAD_DDR_D6__DDR_D_6, + PCM052_VF610_PAD_DDR_D5__DDR_D_5, + PCM052_VF610_PAD_DDR_D4__DDR_D_4, + PCM052_VF610_PAD_DDR_D3__DDR_D_3, + PCM052_VF610_PAD_DDR_D2__DDR_D_2, + PCM052_VF610_PAD_DDR_D1__DDR_D_1, + PCM052_VF610_PAD_DDR_D0__DDR_D_0, + PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, + PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, + PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, + PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, + PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, + PCM052_VF610_PAD_DDR_WE__DDR_WE_B, + PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, + PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, + PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, + PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, + PCM052_VF610_PAD_DDR_RESETB, + }; + + imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, 2); + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) + +static void setup_iomux_enet(void) +{ + static const iomux_v3_cfg_t enet0_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); +} + +/* + * I2C2 is the only I2C used, on pads PTA22/PTA23. + */ + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t i2c_pads[] = { + VF610_PAD_PTA22__I2C2_SCL, + VF610_PAD_PTA23__I2C2_SDA, + }; + + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); +} + +#ifdef CONFIG_NAND_VF610_NFC +static void setup_iomux_nfc(void) +{ + static const iomux_v3_cfg_t nfc_pads[] = { + VF610_PAD_PTD31__NF_IO15, + VF610_PAD_PTD30__NF_IO14, + VF610_PAD_PTD29__NF_IO13, + VF610_PAD_PTD28__NF_IO12, + VF610_PAD_PTD27__NF_IO11, + VF610_PAD_PTD26__NF_IO10, + VF610_PAD_PTD25__NF_IO9, + VF610_PAD_PTD24__NF_IO8, + VF610_PAD_PTD23__NF_IO7, + VF610_PAD_PTD22__NF_IO6, + VF610_PAD_PTD21__NF_IO5, + VF610_PAD_PTD20__NF_IO4, + VF610_PAD_PTD19__NF_IO3, + VF610_PAD_PTD18__NF_IO2, + VF610_PAD_PTD17__NF_IO1, + VF610_PAD_PTD16__NF_IO0, + VF610_PAD_PTB24__NF_WE_B, + VF610_PAD_PTB25__NF_CE0_B, + VF610_PAD_PTB27__NF_RE_B, + VF610_PAD_PTC26__NF_RB_B, + VF610_PAD_PTC27__NF_ALE, + VF610_PAD_PTC28__NF_CLE + }; + + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); +} +#endif + +static void setup_iomux_qspi(void) +{ + static const iomux_v3_cfg_t qspi0_pads[] = { + VF610_PAD_PTD0__QSPI0_A_QSCK, + VF610_PAD_PTD1__QSPI0_A_CS0, + VF610_PAD_PTD2__QSPI0_A_DATA3, + VF610_PAD_PTD3__QSPI0_A_DATA2, + VF610_PAD_PTD4__QSPI0_A_DATA1, + VF610_PAD_PTD5__QSPI0_A_DATA0, + VF610_PAD_PTD7__QSPI0_B_QSCK, + VF610_PAD_PTD8__QSPI0_B_CS0, + VF610_PAD_PTD9__QSPI0_B_DATA3, + VF610_PAD_PTD10__QSPI0_B_DATA2, + VF610_PAD_PTD11__QSPI0_B_DATA1, + VF610_PAD_PTD12__QSPI0_B_DATA0, + }; + + imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); +} + +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) + +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {ESDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* eSDHC1 is always present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t esdhc1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), + }; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads( + esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} + +static void clock_init(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; + + clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, + CCM_CCGR0_UART1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, + CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, + CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | + CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | + CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | + CCM_CCGR2_QSPI0_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, + CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, + CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | + CCM_CCGR4_GPC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, + CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, + CCM_CCGR7_SDHC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, + CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, + CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); + + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, + ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, + ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); + + clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, + CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); + clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, + CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | + CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | + CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | + CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | + CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | + CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); + clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, + CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | + CCM_CACRR_ARM_CLK_DIV(0)); + clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | + CCM_CSCMR1_QSPI0_CLK_SEL(3) | + CCM_CSCMR1_NFC_CLK_SEL(0)); + clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, + CCM_CSCDR1_RMII_CLK_EN); + clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | + CCM_CSCDR2_NFC_EN); + clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, + CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | + CCM_CSCDR3_QSPI0_X2_DIV(1) | + CCM_CSCDR3_QSPI0_X4_DIV(3) | + CCM_CSCDR3_NFC_PRE_DIV(5)); + clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, + CCM_CSCMR2_RMII_CLK_SEL(0)); +} + +static void mscm_init(void) +{ + struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; + int i; + + for (i = 0; i < MSCM_IRSPRC_NUM; i++) + writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + clock_init(); + mscm_init(); + setup_iomux_uart(); + setup_iomux_enet(); + setup_iomux_i2c(); + setup_iomux_qspi(); + setup_iomux_nfc(); + + return 0; +} + +int board_init(void) +{ + struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Enable external 32K Oscillator + * + * The internal clock experiences significant drift + * so we must use the external oscillator in order + * to maintain correct time in the hwclock + */ + setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); + + return 0; +} + +int checkboard(void) +{ + puts("Board: PCM-052\n"); + + return 0; +} diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig new file mode 100644 index 00000000000..e8dc4028780 --- /dev/null +++ b/configs/pcm052_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_PCM052=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES=y diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h new file mode 100644 index 00000000000..903f94c17e4 --- /dev/null +++ b/include/configs/pcm052.h @@ -0,0 +1,231 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the phytec PCM-052 SoM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_VF610 + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_FSL_LPUART +#define LPUART_BASE UART1_BASE + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_UART_PORT (1) +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_CMD_IMLS + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#ifdef CONFIG_CMD_NAND +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +#define CONFIG_JFFS2_NAND + +/* UBI */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=NAND,nor0=qspi0-a,nor1=qspi0-b" +#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ + ",384k(bootloader)"\ + ",128k(env1)"\ + ",128k(env2)"\ + ",3840k(kernel)"\ + ",-(rootfs)"\ + ",qspi0-a:-(jffs2),qspio0-b:-(jffs2)" +#endif + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +/* QSPI Configs*/ +#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC + +/* RTC (actually an RV-4162 but M41T62-compatible) */ +#define CONFIG_CMD_DATE +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 + +/* EEPROM (24FC256) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_SYS_TEXT_BASE 0x3f408000 +#define CONFIG_BOARD_SIZE_LIMIT 524288 + +#define CONFIG_BOOTCOMMAND "run bootcmd_sd" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=uImage\0" \ + "bootargs_base=setenv bootargs rw mem=256M " \ + "console=ttymxc1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "root=/dev/mtdblock2 rootfstype=jffs2\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; mmc rescan; " \ + "fatload mmc 0:1 ${loadaddr} ${bootfile}; bootm ${loadaddr}\0" \ + "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ + "tftpboot ${loadaddr} ${tftploc}${bootfile}; bootm\0" \ + "bootcmd_nand='run bootargs_base bootargs_nand bootargs_mtd; " \ + "nand read ${loadaddr} 0x000E0000 0x3C0000; " \ + "bootm ${loadaddr}\0" \ + "tftploc=/path/to/tftp/directory/\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "update_kernel_from_sd=mw.b $(loadaddr) 0xff 0x3C0000; " \ + "mmc rescan; fatload mmc 0:2 ${loadaddr} ${bootfile}; " \ + "nand erase 0xE0000 0x3C0000; " \ + "nand write.i ${loadaddr} 0xE0000 0x3C0000\0" \ + "update_rootfs_from_tftp=mw.b ${loadaddr} 0xff 0x8F20000; " \ + "tftp ${loadaddr} ${tftp}${filesys}; " \ + "nand erase 0x4A0000 0x8F20000; " \ + "nand write.i ${loadaddr} 0x4A0000 0x8F20000\0" \ + "filesys=rootfs.jffs2\0" + +/* miscellaneous commands */ +#define CONFIG_CMD_ELF + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE_REDUND (8 * 1024) +#define CONFIG_ENV_OFFSET_REDUND 0xA0000 +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#endif -- cgit v1.3.1 From 7daaac5281db0788cde895a0add38ad5195b5be1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 23 Sep 2015 00:52:33 -0300 Subject: mx6sabre_common: Add DFU support Add DFU support. Tested by flashing SPL and u-boot.img into SPI NOR flash with the following commands: => setenv dfu_alt_info ${dfu_alt_info_spl} => run dfuspi On the host PC: $ sudo dfu-util -D SPL -a spl On the target: CTRL+C => setenv dfu_alt_info ${dfu_alt_info_img} => run dfuspi On the host PC: $ sudo dfu-util -D u-boot.img -a u-boot Signed-off-by: Fabio Estevam --- include/configs/mx6sabre_common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 2970b831098..9dcc64ea579 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -80,6 +80,10 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ + "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ + "dfu_alt_info_spl=spl raw 0x400\0" \ + "dfu_alt_info_img=u-boot raw 0x10000\0" \ + "dfu_alt_info=spl raw 0x400\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -244,6 +248,12 @@ #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 + +/* USB Device Firmware Update support */ +#define CONFIG_CMD_DFU +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_MMC +#define CONFIG_DFU_SF #endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ -- cgit v1.3.1 From 930c514d47a29e1f94a5b61fe965400a4f5635c3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 Sep 2015 12:34:01 -0600 Subject: ARM: tegra: expand all SPL sizes to be consistent The size allocation for SPL is increased in all cases to match the already-expanded value used on Tegra124. This is both for general consistency, and because the seaboard build trips over the limit already when using one of the ARM compilers packaged with 14.04. For the record, when building Seaboard: arm-linux-gnueabi- SPL is too big by 0x36 bytes arm-linux-gnueabihf- SPL fits by 0x2a bytes arm-none-eabi- SPL fits by 0xa bytes (Those figures are from builds with the expanded SPL size allocation, relative to the non-expanded SPL size limit; they're better by about 6 bytes in the more constrained build.) Fixes: ba521994229c ("tegra124: Expand SPL space by 8KB") Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra114-common.h | 2 +- include/configs/tegra20-common.h | 2 +- include/configs/tegra210-common.h | 2 +- include/configs/tegra30-common.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 252e607d73f..671071ba981 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -34,7 +34,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 0841f33bfc9..00e85c48c41 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -32,7 +32,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x0010E000 +#define CONFIG_SYS_TEXT_BASE 0x00110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index e6c815212d7..8f35a7bf3dc 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -26,7 +26,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* Generic Interrupt Controller */ #define CONFIG_GICV2 diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 3e8e3c1e5bd..9afd86484bb 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -31,7 +31,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: -- cgit v1.3.1 From 03d1d568a04b3d67e0f09b598554c2b74e31224f Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Tue, 15 Sep 2015 18:28:20 +0800 Subject: configs: ls1021atwr: Enable DSPI for LS1021ATWR DSPI2 can be verified when boot from QSPI now. Signed-off-by: Yuan Yao Reviewed-by: Jagan Teki --- include/configs/ls1021atwr.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f6bd5fcece1..02cc09c82b7 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -310,12 +310,16 @@ #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SPI_FLASH_STMICRO +/* DSPI */ +#define CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_ATMEL +#endif + /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) #define CONFIG_CMD_SF #define CONFIG_DM_SPI_FLASH #endif -#endif /* * Video -- cgit v1.3.1 From c0ae9703b427df0272a7559bdd3d9c9e5c1d6482 Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:17:59 +0100 Subject: vexpress64: fix checkpatch warnings This patch fixes a couple of checkpatch warnings on the vexpress64 config. Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 6107c64dd2a..53b0f74e0fa 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -194,7 +194,8 @@ #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ "root=/dev/sda1 rw " \ "rootwait "\ - "earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\ + "earlyprintk=pl011,0x7ff80000 debug "\ + "user_debug=31 "\ "loglevel=9" /* Copy the kernel and FDT to DRAM memory and boot */ @@ -222,7 +223,8 @@ #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ "smhload ${fdt_name} ${fdt_addr}; " \ - "smhload ${initrd_name} ${initrd_addr} initrd_end; " \ + "smhload ${initrd_name} ${initrd_addr} "\ + "initrd_end; " \ "fdt addr ${fdt_addr}; fdt resize; " \ "fdt chosen ${initrd_addr} ${initrd_end}; " \ "booti $kernel_addr - $fdt_addr" -- cgit v1.3.1 From 0d3012af5a395d25bb0ab67946158e5bf8d33d5b Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:18:01 +0100 Subject: vexpress64: increase max gunzip size vexpress64 kernels are usually over 8 MBytes in length, so setting the max uImage length to 64 Mbytes should give us plenty of scope for expansion. I mostly chose this length to match other board configs that use "(64 << 20)". Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 53b0f74e0fa..c54baf8c7bb 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -41,6 +41,8 @@ #error "Unknown board variant" #endif +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT -- cgit v1.3.1 From fc04b923541d984b1544056fd3bfa8129d4e5aac Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:18:02 +0100 Subject: vexpress64: fvp dram: add DRAM configuration Create an additional FVP configuration to boot images pre-loaded into DRAM. Sometimes it's preferential to boot the model by loading the files directly into DRAM via model parameters, rather than using SemiHosting. An example of model parmaters that are used to pre-load the files into DRAM: --data cluster0.cpu0=Image@0x80080000 \ --data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \ --data cluster0.cpu0=uInitrd@0x84000000 Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij [trini: Update board/armltd/vexpress64/Kconfig logic] Signed-off-by: Tom Rini --- arch/arm/Kconfig | 9 +++++++++ board/armltd/vexpress64/Kconfig | 2 +- board/armltd/vexpress64/MAINTAINERS | 5 +++++ configs/vexpress_aemv8a_dram_defconfig | 19 +++++++++++++++++++ include/configs/vexpress_aemv8a.h | 25 +++++++++++++++++++++++-- 5 files changed, 57 insertions(+), 3 deletions(-) create mode 100644 configs/vexpress_aemv8a_dram_defconfig (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3a336e6fdfe..798135574a7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -567,6 +567,15 @@ config TARGET_VEXPRESS64_BASE_FVP select ARM64 select SEMIHOSTING +config TARGET_VEXPRESS64_BASE_FVP_DRAM + bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM" + select ARM64 + help + This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides + the default config to allow the user to load the images directly into + DRAM using model parameters rather than by using semi-hosting to load + the files from the host filesystem. + config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 90144184334..e05f353b80b 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,4 +1,4 @@ -if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO +if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || TARGET_VEXPRESS64_BASE_FVP_DRAM config SYS_BOARD default "vexpress64" diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 0ba044d7ff8..15b0a086464 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -10,6 +10,11 @@ M: Linus Walleij S: Maintained F: configs/vexpress_aemv8a_semi_defconfig +VEXPRESS_AEMV8A_DRAM BOARD +M: Ryan Harkin +S: Maintained +F: configs/vexpress_aemv8a_dram_defconfig + JUNO DEVELOPMENT PLATFORM BOARD M: Linus Walleij S: Maintained diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig new file mode 100644 index 00000000000..e9fc8706f47 --- /dev/null +++ b/configs/vexpress_aemv8a_dram_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="vexpress64" +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_PROMPT="VExpress64# " diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index c54baf8c7bb..c1e2e111c94 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -30,7 +30,8 @@ #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" /* Link Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ + defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_TEXT_BASE 0x88000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) @@ -103,7 +104,8 @@ #define GICR_BASE (0x2f100000) #else -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ + defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -233,6 +235,25 @@ #define CONFIG_BOOTDELAY 1 +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x80080000\0" \ + "initrd_addr=0x84000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ + "0x1c090000 debug user_debug=31 "\ + "androidboot.hardware=fvpbase "\ + "root=/dev/vda2 rw "\ + "rootwait "\ + "loglevel=9" + +#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" + +#define CONFIG_BOOTDELAY 1 + #else #error "Unknown board variant" #endif -- cgit v1.3.1 From 74e264b49fc5aa20ef6f2c9e00560f81c08c667c Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:18:03 +0100 Subject: vexpress64: juno: add androidboot.hardware=juno Linaro's Juno Android builds requires the androidboot.hardware parameter be set to a know board name. Non-Android kernels ignore this extra parameter because they don't contain code to parse it. Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index c1e2e111c94..f9fa2cef12e 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -200,6 +200,7 @@ "rootwait "\ "earlyprintk=pl011,0x7ff80000 debug "\ "user_debug=31 "\ + "androidboot.hardware=juno "\ "loglevel=9" /* Copy the kernel and FDT to DRAM memory and boot */ -- cgit v1.3.1 From 4a6bdb59e1b33b62fce79c417b0ecc958408fec8 Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:18:06 +0100 Subject: vexpress64: juno: add optional initrd Some OS images require an initrd on Juno. If the file ramdisk.img exists in NOR flash, then we load it and pass the address to the kernel. Otherwise, we pass the "-" parameter as before. Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index f9fa2cef12e..99dd8b6b624 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -189,6 +189,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_name=Image\0" \ "kernel_addr=0x80000000\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr=0x84000000\0" \ "fdt_name=juno\0" \ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ @@ -207,7 +209,12 @@ #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ "afs load ${fdt_name} ${fdt_addr} ; " \ "fdt addr ${fdt_addr}; fdt resize; " \ - "booti ${kernel_addr} - ${fdt_addr}" + "if afs load ${initrd_name} ${initrd_addr} ; "\ + "then "\ + " setenv initrd_param ${initrd_addr}; "\ + " else setenv initrd_param -; "\ + "fi ; " \ + "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" #define CONFIG_BOOTDELAY 1 -- cgit v1.3.1 From ecbed5d6f4f96457dee8846c611056cb0d630642 Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:18:07 +0100 Subject: vexpress64: juno: add alternate kernel and device tree filenames The latest Juno firmware stores the files in NOR flash as "norkern" for kernel binary, "board.dtb" for the device tree binary. The "old" firmware used the name "Image" for the kernel binary and "juno" for the device tree binary. Rather than just change the default U-Boot configuration to use the new names, breaking users with the old firmware, attempt to load the default filename first. If that fails, attempt to load the alternate filename. I've echo'd that we are loading the alternate file to counter the output from "afs load" shown if the first load attempt fails. For example, I see output like this on my Juno board when it's configured the with the "old" firmware: image "norkern" not found in flash Loading Image instead of norkern loaded region 0 from 08500000 to 80000000, 00AB6318 bytes image "board.dtb" not found in flash Loading juno instead of board.dtb loaded region 0 from 0A000000 to 83000000, 00003188 bytes Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 99dd8b6b624..259f6aca82d 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -187,11 +187,13 @@ * be copied into DRAM */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ + "kernel_name=norkern\0" \ + "kernel_alt_name=Image\0" \ "kernel_addr=0x80000000\0" \ "initrd_name=ramdisk.img\0" \ "initrd_addr=0x84000000\0" \ - "fdt_name=juno\0" \ + "fdt_name=board.dtb\0" \ + "fdt_alt_name=juno\0" \ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ @@ -207,7 +209,17 @@ /* Copy the kernel and FDT to DRAM memory and boot */ #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ + "if test $? -eq 1; then "\ + " echo Loading ${kernel_alt_name} instead of "\ + "${kernel_name}; "\ + " afs load ${kernel_alt_name} ${kernel_addr};"\ + "fi ; "\ "afs load ${fdt_name} ${fdt_addr} ; " \ + "if test $? -eq 1; then "\ + " echo Loading ${fdt_alt_name} instead of "\ + "${fdt_name}; "\ + " afs load ${fdt_alt_name} ${fdt_addr}; "\ + "fi ; "\ "fdt addr ${fdt_addr}; fdt resize; " \ "if afs load ${initrd_name} ${initrd_addr} ; "\ "then "\ -- cgit v1.3.1 From 492f24e886a032c56e16647e69e536edb2be8e5d Mon Sep 17 00:00:00 2001 From: Ryan Harkin Date: Fri, 9 Oct 2015 17:18:08 +0100 Subject: vexpress64: juno: use /dev/sda2 This patch changes the default "root=" parameter to "/dev/sda2". Many linux based distros use /dev/sda1 for their boot partition; this is often not a rootfs that can be used by the "root=" parameter. Linaro images use /dev/sda1 as a boot partition, although this of a different nature to a distro image. Linaro uses /dev/sda2 for the rootfs partition. Signed-off-by: Ryan Harkin Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 259f6aca82d..ef3014d68b1 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -200,7 +200,7 @@ /* Assume we boot with root on the first partition of a USB stick */ #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ - "root=/dev/sda1 rw " \ + "root=/dev/sda2 rw " \ "rootwait "\ "earlyprintk=pl011,0x7ff80000 debug "\ "user_debug=31 "\ -- cgit v1.3.1 From 689821fd766fb4855deafd04eaffeef5b2c6579e Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Thu, 8 Oct 2015 21:12:25 +0300 Subject: ti: omap3: config: remove 1 from boolean define CONFIG_TWL4030_POWER is a boolean define variable. It is either defined or not defined and should not have a value assigned to it. Remove the value. Signed-off-by: Igor Grinberg --- include/configs/ti_omap3_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index be231a55136..e399a879ac3 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -66,7 +66,7 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* TWL4030 */ -#define CONFIG_TWL4030_POWER 1 +#define CONFIG_TWL4030_POWER /* SPL */ #define CONFIG_SPL_TEXT_BASE 0x40200800 -- cgit v1.3.1 From 04386f656bbc35abd7718a4bbbba7fcfb4f59aef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 2 Oct 2015 08:20:35 +0200 Subject: Revert "powerpc: ppc4xx: remove lwmon5 support" This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be. I'll add support to lwmon5 in the next patch and will remove support for the broken lcd4_lwmon5 as well. Signed-off-by: Stefan Roese Cc: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 5 + arch/powerpc/include/asm/global_data.h | 6 + board/lwmon5/Kconfig | 9 + board/lwmon5/MAINTAINERS | 7 + board/lwmon5/Makefile | 9 + board/lwmon5/config.mk | 18 + board/lwmon5/init.S | 75 ++++ board/lwmon5/kbd.c | 490 +++++++++++++++++++++++ board/lwmon5/lwmon5.c | 558 ++++++++++++++++++++++++++ board/lwmon5/sdram.c | 247 ++++++++++++ configs/lcd4_lwmon5_defconfig | 6 + configs/lwmon5_defconfig | 4 + doc/README.scrapyard | 1 - drivers/video/mb862xx.c | 3 +- include/configs/lwmon5.h | 692 +++++++++++++++++++++++++++++++++ 15 files changed, 2128 insertions(+), 2 deletions(-) create mode 100644 board/lwmon5/Kconfig create mode 100644 board/lwmon5/MAINTAINERS create mode 100644 board/lwmon5/Makefile create mode 100644 board/lwmon5/config.mk create mode 100644 board/lwmon5/init.S create mode 100644 board/lwmon5/kbd.c create mode 100644 board/lwmon5/lwmon5.c create mode 100644 board/lwmon5/sdram.c create mode 100644 configs/lcd4_lwmon5_defconfig create mode 100644 configs/lwmon5_defconfig create mode 100644 include/configs/lwmon5.h (limited to 'include') diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 23ecc895fbc..8d3ba8d73f6 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -8,6 +8,10 @@ choice prompt "Target select" optional +config TARGET_LWMON5 + bool "Support lwmon5" + select SUPPORT_SPL + config TARGET_T3CORP bool "Support t3corp" @@ -165,6 +169,7 @@ source "board/gdsys/405ex/Kconfig" source "board/gdsys/dlvision/Kconfig" source "board/gdsys/gdppc440etx/Kconfig" source "board/gdsys/intip/Kconfig" +source "board/lwmon5/Kconfig" source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 2527ef88deb..4090975bf5e 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -106,6 +106,12 @@ struct arch_global_data { #ifdef CONFIG_SYS_FPGA_COUNT unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; #endif +#if defined(CONFIG_WD_MAX_RATE) + unsigned long long wdt_last; /* trace watch-dog triggering rate */ +#endif +#if defined(CONFIG_LWMON5) + unsigned long kbd_status; +#endif }; #include diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig new file mode 100644 index 00000000000..90566d825bc --- /dev/null +++ b/board/lwmon5/Kconfig @@ -0,0 +1,9 @@ +if TARGET_LWMON5 + +config SYS_BOARD + default "lwmon5" + +config SYS_CONFIG_NAME + default "lwmon5" + +endif diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS new file mode 100644 index 00000000000..7402ab67580 --- /dev/null +++ b/board/lwmon5/MAINTAINERS @@ -0,0 +1,7 @@ +LWMON5 BOARD +M: Stefan Roese +S: Maintained +F: board/lwmon5/ +F: include/configs/lwmon5.h +F: configs/lcd4_lwmon5_defconfig +F: configs/lwmon5_defconfig diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile new file mode 100644 index 00000000000..02478ca0c85 --- /dev/null +++ b/board/lwmon5/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = lwmon5.o kbd.o sdram.o +extra-y += init.o diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk new file mode 100644 index 00000000000..d0348e8024d --- /dev/null +++ b/board/lwmon5/config.mk @@ -0,0 +1,18 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# lwmon5 (440EPx) +# + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S new file mode 100644 index 00000000000..e5207c2b40b --- /dev/null +++ b/board/lwmon5/init.S @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (C) 2002 Scott McNutt + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + +#ifdef CONFIG_SYS_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) +#endif + + /* TLB-entry for PCI Memory */ + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG) + + /* TLB-entry for the FPGA Chip select 2 */ + tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G) + + /* TLB-entry for the FPGA Chip select 3 */ + tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G) + + /* TLB-entry for the LIME Controller */ + tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I) + + /*TLB-entry PCI registers*/ + tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG) + + /* TLB-entry for peripherals */ + tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) + + tlbtab_end diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c new file mode 100644 index 00000000000..97962daf939 --- /dev/null +++ b/board/lwmon5/kbd.c @@ -0,0 +1,490 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2001, 2002 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include + +#include +#include /* for strdup */ + +DECLARE_GLOBAL_DATA_PTR; + +static void kbd_init (void); +static int compare_magic (uchar *kbd_data, uchar *str); + +/*--------------------- Local macros and constants --------------------*/ +#define _NOT_USED_ 0xFFFFFFFF + +/*------------------------- dspic io expander -----------------------*/ +#define DSPIC_PON_STATUS_REG 0x80A +#define DSPIC_PON_INV_STATUS_REG 0x80C +#define DSPIC_PON_KEY_REG 0x810 +/*------------------------- Keyboard controller -----------------------*/ +/* command codes */ +#define KEYBD_CMD_READ_KEYS 0x01 +#define KEYBD_CMD_READ_VERSION 0x02 +#define KEYBD_CMD_READ_STATUS 0x03 +#define KEYBD_CMD_RESET_ERRORS 0x10 + +/* status codes */ +#define KEYBD_STATUS_MASK 0x3F +#define KEYBD_STATUS_H_RESET 0x20 +#define KEYBD_STATUS_BROWNOUT 0x10 +#define KEYBD_STATUS_WD_RESET 0x08 +#define KEYBD_STATUS_OVERLOAD 0x04 +#define KEYBD_STATUS_ILLEGAL_WR 0x02 +#define KEYBD_STATUS_ILLEGAL_RD 0x01 + +/* Number of bytes returned from Keyboard Controller */ +#define KEYBD_VERSIONLEN 2 /* version information */ + +/* + * This is different from the "old" lwmon dsPIC kbd controller + * implementation. Now the controller still answers with 9 bytes, + * but the last 3 bytes are always "0x06 0x07 0x08". So we just + * set the length to compare to 6 instead of 9. + */ +#define KEYBD_DATALEN 6 /* normal key scan data */ + +/* maximum number of "magic" key codes that can be assigned */ + +static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; +static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR; + +static uchar *key_match (uchar *); + +#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ + +/*********************************************************************** +F* Function: int board_postclk_init (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: This function is the board_postclk_init() method implementation +Z* for the lwmon board. + * + ***********************************************************************/ +int board_postclk_init (void) +{ + kbd_init(); + + return (0); +} + +static void kbd_init (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar tmp_data[KEYBD_DATALEN]; + uchar val, errcd; + int i; + + i2c_set_bus_num(0); + + gd->arch.kbd_status = 0; + + /* Forced by PIC. Delays <= 175us loose */ + udelay(1000); + + /* Read initial keyboard error code */ + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &errcd, 1); + /* clear unused bits */ + errcd &= KEYBD_STATUS_MASK; + /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ + errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); + if (errcd) { + gd->arch.kbd_status |= errcd << 8; + } + /* Reset error code and verify */ + val = KEYBD_CMD_RESET_ERRORS; + i2c_write (kbd_addr, 0, 0, &val, 1); + udelay(1000); /* delay NEEDED by keyboard PIC !!! */ + + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &val, 1); + + val &= KEYBD_STATUS_MASK; /* clear unused bits */ + if (val) { /* permanent error, report it */ + gd->arch.kbd_status |= val; + return; + } + + /* + * Read current keyboard state. + * + * After the error reset it may take some time before the + * keyboard PIC picks up a valid keyboard scan - the total + * scan time is approx. 1.6 ms (information by Martin Rajek, + * 28 Sep 2002). We read a couple of times for the keyboard + * to stabilize, using a big enough delay. + * 10 times should be enough. If the data is still changing, + * we use what we get :-( + */ + + memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ + for (i=0; i<10; ++i) { + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { + /* consistent state, done */ + break; + } + /* remeber last state, delay, and retry */ + memcpy (tmp_data, kbd_data, KEYBD_DATALEN); + udelay (5000); + } +} + + +/* Read a register from the dsPIC. */ +int _dspic_read(ushort reg, ushort *data) +{ + uchar buf[sizeof(*data)]; + int rval; + + if (i2c_read(dspic_addr, reg, 2, buf, 2)) + return -1; + + rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data)); + *data = (buf[0] << 8) | buf[1]; + + return rval; +} + + +/*********************************************************************** +F* Function: int misc_init_r (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned, even in the case of a keyboard +P* error. + * +Z* Intention: This function is the misc_init_r() method implementation +Z* for the lwmon board. +Z* The keyboard controller is initialized and the result +Z* of a read copied to the environment variable "keybd". +Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for +Z* this key, and if found display to the LCD will be enabled. +Z* The keys in "keybd" are checked against the magic +Z* keycommands defined in the environment. +Z* See also key_match(). + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int misc_init_r_kbd (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar kbd_init_status = gd->arch.kbd_status >> 8; + uchar kbd_status = gd->arch.kbd_status; + uchar val; + ushort data, inv_data; + char *str; + int i; + + if (kbd_init_status) { + printf ("KEYBD: Error %02X\n", kbd_init_status); + } + if (kbd_status) { /* permanent error, report it */ + printf ("*** Keyboard error code %02X ***\n", kbd_status); + sprintf (keybd_env, "%02X", kbd_status); + setenv ("keybd", keybd_env); + return 0; + } + + /* + * Now we know that we have a working keyboard, so disable + * all output to the LCD except when a key press is detected. + */ + + if ((console_assign (stdout, "serial") < 0) || + (console_assign (stderr, "serial") < 0)) { + printf ("Can't assign serial port as output device\n"); + } + + /* Read Version */ + val = KEYBD_CMD_READ_VERSION; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); + printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); + + /* Read current keyboard state */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + /* read out start key from bse01 received via can */ + _dspic_read(DSPIC_PON_STATUS_REG, &data); + /* check highbyte from status register */ + if (data > 0xFF) { + _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data); + + /* check inverse data */ + if ((data+inv_data) == 0xFFFF) { + /* don't overwrite local key */ + if (kbd_data[1] == 0) { + /* read key value */ + _dspic_read(DSPIC_PON_KEY_REG, &data); + str = (char *)&data; + /* swap bytes */ + kbd_data[1] = str[1]; + kbd_data[2] = str[0]; + printf("CAN received startkey: 0x%X\n", data); + } + } + } + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ +#ifdef KEYBD_SET_DEBUGMODE + if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ + if ((console_assign (stdout, "lcd") < 0) || + (console_assign (stderr, "lcd") < 0)) { + printf ("Can't assign LCD display as output device\n"); + } + } +#endif /* KEYBD_SET_DEBUGMODE */ +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + return (0); +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + uchar compare[KEYBD_DATALEN-1]; + char *nxt; + int i; + + /* Don't include modifier byte */ + memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + +/*********************************************************************** +F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* + * +P* Parameters: uchar *kbd_data +P* - The keys to match against our magic definitions +P* +P* Returnvalue: uchar * +P* - != NULL: Pointer to the corresponding command(s) +P* NULL: No magic is about to happen + * +Z* Intention: Check if pressed key(s) match magic sequence, +Z* and return the command string associated with that key(s). +Z* +Z* If no key press was decoded, NULL is returned. +Z* +Z* Note: the first character of the argument will be +Z* overwritten with the "magic charcter code" of the +Z* decoded key(s), or '\0'. +Z* +Z* Note: the string points to static environment data +Z* and must be saved before you call any function that +Z* modifies the environment. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + debug ("### Check magic \"%s\"\n", magic); + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); + debug ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<>"); + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } + debug ("### Delete PREBOOT\n"); + *kbd_data = '\0'; + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/*********************************************************************** +F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, +F* int argc, char * const argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char * const argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: Implement the "kbd" command. +Z* The keyboard status is read. The result is printed on +Z* the console and written into the "keybd" environment +Z* variable. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar val; + int i; + +#if 0 /* Done in kbd_init */ + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "read keyboard status", + "" +); + +/*----------------------------- Utilities -----------------------------*/ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar val; + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); +} +#endif diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c new file mode 100644 index 00000000000..e9aa0b77de5 --- /dev/null +++ b/board/lwmon5/lwmon5.c @@ -0,0 +1,558 @@ +/* + * (C) Copyright 2007-2013 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; + +ulong flash_get_size(ulong base, int banknum); +int misc_init_r_kbd(void); + +int board_early_init_f(void) +{ + u32 sdr0_pfc1, sdr0_pfc2; + u32 reg; + + /* PLB Write pipelining disabled. Denali Core workaround */ + mtdcr(PLB4A0_ACR, 0xDE000000); + mtdcr(PLB4A1_ACR, 0xDE000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ + mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ + mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ + mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ + mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + /* Trace Pins are disabled. SDR0_PFC0 Register */ + mtsdr(SDR0_PFC0, 0x0); + + /* select Ethernet pins */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + /* SMII via ZMII */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | + SDR0_PFC1_SELECT_CONFIG_6; + mfsdr(SDR0_PFC2, sdr0_pfc2); + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | + SDR0_PFC2_SELECT_CONFIG_6; + + /* enable SPI (SCP) */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; + + mtsdr(SDR0_PFC2, sdr0_pfc2); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + mtsdr(SDR0_PFC4, 0x80000000); + + /* PCI arbiter disabled */ + /* PCI Host Configuration disbaled */ + mfsdr(SDR0_PCI0, reg); + reg = 0; + mtsdr(SDR0_PCI0, 0x00000000 | reg); + + gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); + +#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* enable the CAN transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); + + reg = 0; /* reuse as counter */ + out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, + in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) + & ~CONFIG_SYS_DSPIC_TEST_MASK); + while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { + udelay(1000); + } + if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { + /* set "boot error" flag */ + out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, + in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | + CONFIG_SYS_DSPIC_TEST_MASK); + } +#endif + + /* + * Reset PHY's: + * The PHY's need a 2nd reset pulse, since the MDIO address is latched + * upon reset, and with the first reset upon powerup, the addresses are + * not latched reliable, since the IRQ line is multiplexed with an + * MDIO address. A 2nd reset at this time will make sure, that the + * correct address is latched. + */ + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); + udelay(1000); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); + udelay(1000); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); + + return 0; +} + +/* + * Override weak default with board specific version + */ +phys_addr_t cfi_flash_bank_addr(int bank) +{ + return lwmon5_cfi_flash_bank_addr[bank]; +} + +/* + * Override the weak default mapping function with a board specific one + */ +u32 flash_get_bank_size(int cs, int idx) +{ + return flash_info[idx].size; +} + +int board_early_init_r(void) +{ + u32 val0, val1; + + /* + * lwmon5 is manufactured in 2 different board versions: + * The lwmon5a board has 64MiB NOR flash instead of the + * 128MiB of the original lwmon5. Unfortunately the CFI driver + * will report 2 banks of 64MiB even for the smaller flash + * chip, since the bank is mirrored. To fix this, we bring + * one bank into CFI query mode and read its response. This + * enables us to detect the real number of flash devices/ + * banks which will be used later on by the common CFI driver. + */ + + /* Put bank 0 into CFI command mode and read */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); + val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); + val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); + + /* Reset flash again out of query mode */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); + + /* When not identical, we have 2 different flash devices/banks */ + if (val0 != val1) + return 0; + + /* + * Now we're sure that we're running on a LWMON5a board with + * only 64MiB NOR flash in one bank: + * + * Set flash base address and bank count for CFI driver probing. + */ + cfi_flash_num_flash_banks = 1; + lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; + + return 0; +} + +int misc_init_r(void) +{ + u32 pbcr; + int size_val = 0; + u32 reg; +#ifndef CONFIG_LCD4_LWMON5 + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1, sdr0_srst; +#endif + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + mfebc(PB0CR, pbcr); + size_val = ffs(gd->bd->bi_flashsize) - 21; + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(PB0CR, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, + &flash_info[cfi_flash_num_flash_banks - 1]); + + /* Env protection ON by default */ + flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[cfi_flash_num_flash_banks - 1]); + +#ifndef CONFIG_LCD4_LWMON5 + /* + * USB suff... + */ + + /* Reset USB */ + /* Reset of USB2PHY0 must be active at least 10 us */ + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); + udelay(2000); + + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | + SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | + SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); + udelay(2000); + + /* Errata CHIP_6 */ + + /* 1. Set internal PHY configuration */ + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* + * An 8-bit/60MHz interface is the only possible alternative + * when connecting the Device to the PHY + */ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /* 2. De-assert internal PHY reset */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst); + + /* 3. Wait for more than 1 ms */ + udelay(2000); + + /* 4. De-assert USB 2.0 Host main reset */ + mfsdr(SDR0_SRST0, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst); + udelay(1000); + + /* 5. De-assert reset of OPB2 cores */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; + mtsdr(SDR0_SRST1, sdr0_srst); + udelay(1000); + + /* 6. Set EHCI Configure FLAG */ + + /* 7. Reassert internal PHY reset: */ + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); + udelay(1000); +#endif + + /* + * Clear resets + */ + mtsdr(SDR0_SRST1, 0x00000000); + mtsdr(SDR0_SRST0, 0x00000000); + +#ifndef CONFIG_LCD4_LWMON5 + printf("USB: Host(int phy) Device(ext phy)\n"); +#endif + + /* + * Clear PLB4A0_ACR[WRP] + * This fix will make the MAL burst disabling patch for the Linux + * EMAC driver obsolete. + */ + reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; + mtdcr(PLB4A0_ACR, reg); + +#ifndef CONFIG_LCD4_LWMON5 + /* + * Init matrix keyboard + */ + misc_init_r_kbd(); +#endif + + return 0; +} + +int checkboard(void) +{ + char buf[64]; + int i = getenv_f("serial#", buf, sizeof(buf)); + + printf("Board: %s", __stringify(CONFIG_HOSTNAME)); + + if (i > 0) { + puts(", serial# "); + puts(buf); + } + putc('\n'); + + return (0); +} + +void hw_watchdog_reset(void) +{ + int val; +#if defined(CONFIG_WD_MAX_RATE) + unsigned long long ct = get_ticks(); + + /* + * Don't allow watch-dog triggering more frequently than + * the predefined value CONFIG_WD_MAX_RATE [ticks]. + */ + if (ct >= gd->arch.wdt_last) { + if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE) + return; + } else { + /* Time base counter had been reset */ + if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) < + CONFIG_WD_MAX_RATE) + return; + } + gd->arch.wdt_last = get_ticks(); +#endif + + /* + * Toggle watchdog output + */ + val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0; + gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val); +} + +int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return cmd_usage(cmdtp); + + if ((strcmp(argv[1], "on") == 0)) + gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1); + else if ((strcmp(argv[1], "off") == 0)) + gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); + else + return cmd_usage(cmdtp); + + return 0; +} + +U_BOOT_CMD( + eepromwp, 2, 0, do_eeprom_wp, + "eeprom write protect off/on", + " - enable (on) or disable (off) I2C EEPROM write protect" +); + +#if defined(CONFIG_VIDEO) +#include +#include + +extern GraphicDevice mb862xx; + +static const gdc_regs init_regs [] = { + { 0x0100, 0x00000f00 }, + { 0x0020, 0x801401df }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x00000000 }, + { 0x002c, 0x00000000 }, + { 0x0110, 0x00000000 }, + { 0x0114, 0x00000000 }, + { 0x0118, 0x01df0280 }, + { 0x0004, 0x031f0000 }, + { 0x0008, 0x027f027f }, + { 0x000c, 0x015f028f }, + { 0x0010, 0x020c0000 }, + { 0x0014, 0x01df01ea }, + { 0x0018, 0x00000000 }, + { 0x001c, 0x01e00280 }, + { 0x0100, 0x80010f00 }, + { 0x0, 0x0 } +}; + +const gdc_regs *board_get_regs(void) +{ + return init_regs; +} + +/* Returns Lime base address */ +unsigned int board_video_init(void) +{ + /* + * Reset Lime controller + */ + gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); + udelay(500); + gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); + + mb862xx.winSizeX = 640; + mb862xx.winSizeY = 480; + mb862xx.gdfBytesPP = 2; + mb862xx.gdfIndex = GDF_15BIT_555RGB; + + return CONFIG_SYS_LIME_BASE_0; +} + +#define DEFAULT_BRIGHTNESS 0x64 + +static void board_backlight_brightness(int brightness) +{ + if (brightness > 0) { + /* pwm duty, lamp on */ + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness); + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701); + } else { + /* lamp off */ + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00); + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00); + } +} + +void board_backlight_switch(int flag) +{ + char * param; + int rc; + + if (flag) { + param = getenv("brightness"); + rc = param ? simple_strtol(param, NULL, 10) : -1; + if (rc < 0) + rc = DEFAULT_BRIGHTNESS; + } else { + rc = 0; + } + board_backlight_brightness(rc); +} + +#if defined(CONFIG_CONSOLE_EXTRA_INFO) +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str(int line_number, char *info) +{ + if (line_number == 1) + strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); + else + info [0] = '\0'; +} +#endif /* CONFIG_CONSOLE_EXTRA_INFO */ +#endif /* CONFIG_VIDEO */ + +void board_reset(void) +{ + gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); +} + +#ifdef CONFIG_SPL_OS_BOOT +/* + * lwmon5 specific implementation of spl_start_uboot() + * + * RETURN + * 0 if booting into OS is selected (default) + * 1 if booting into U-Boot is selected + */ +int spl_start_uboot(void) +{ + char s[8]; + + env_init(); + getenv_f("boot_os", s, sizeof(s)); + if ((s != NULL) && (strcmp(s, "yes") == 0)) + return 0; + + return 1; +} + +/* + * This function is called from the SPL U-Boot version for + * early init stuff, that needs to be done for OS (e.g. Linux) + * booting. Doing it later in the real U-Boot would not work + * in case that the SPL U-Boot boots Linux directly. + */ +void spl_board_init(void) +{ + const gdc_regs *regs = board_get_regs(); + + /* + * Setup PFC registers, mainly for ethernet support + * later on in Linux + */ + board_early_init_f(); + + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + + /* + * Clear resets + */ + mtsdr(SDR0_SRST1, 0x00000000); + mtsdr(SDR0_SRST0, 0x00000000); + + /* + * Reset Lime controller + */ + gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); + udelay(500); + gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); + + out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF); + udelay(300); + out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR); + + while (regs->index) { + out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) + + regs->index, regs->value); + regs++; + } + + board_backlight_brightness(DEFAULT_BRIGHTNESS); +} +#endif diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c new file mode 100644 index 00000000000..5dfbb0bc256 --- /dev/null +++ b/board/lwmon5/sdram.c @@ -0,0 +1,247 @@ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2007-2013 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include +#include + +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CONFIG_4xx_DCACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CONFIG_4xx_DCACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + +/*-----------------------------------------------------------------------------+ + * Prototypes + *-----------------------------------------------------------------------------*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); +extern void dcbz_area(u32 start_address, u32 num_bytes); + +static u32 is_ecc_enabled(void) +{ + u32 val; + + mfsdram(DDR0_22, val); + val &= DDR0_22_CTRL_RAW_MASK; + if (val) + return 1; + else + return 0; +} + +void board_add_ram_info(int use_default) +{ + PPC4xx_SYS_INFO board_cfg; + u32 val; + + if (is_ecc_enabled()) + puts(" (ECC"); + else + puts(" (ECC not"); + + get_sys_info(&board_cfg); + printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000); + + mfsdram(DDR0_03, val); + val = DDR0_03_CASLAT_DECODE(val); + printf(", CL%d)", val); +} + +#ifdef CONFIG_DDR_ECC +static void wait_ddr_idle(void) +{ + /* + * Controller idle status cannot be determined for Denali + * DDR2 code. Just return here. + */ +} + +static void program_ecc(u32 start_address, + u32 num_bytes, + u32 tlb_word2_i_value) +{ + u32 val; + u32 current_addr = start_address; + u32 size; + int bytes_remaining; + + sync(); + wait_ddr_idle(); + + /* + * Because of 440EPx errata CHIP 11, we don't touch the last 256 + * bytes of SDRAM. + */ + bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE; + + /* + * We have to write the ECC bytes by zeroing and flushing in smaller + * steps, since the whole 256MByte takes too long for the external + * watchdog. + */ + while (bytes_remaining > 0) { + size = min((64 << 20), bytes_remaining); + + /* Write zero's to SDRAM */ + dcbz_area(current_addr, size); + + /* Write modified dcache lines back to memory */ + clean_dcache_range(current_addr, current_addr + size); + + current_addr += 64 << 20; + bytes_remaining -= 64 << 20; + WATCHDOG_RESET(); + } + + sync(); + wait_ddr_idle(); + + /* Clear error status */ + mfsdram(DDR0_00, val); + mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + + /* Set 'int_mask' parameter to functionnal value */ + mfsdram(DDR0_01, val); + mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); + + sync(); + wait_ddr_idle(); +} +#endif + +/************************************************************************* + * + * initdram -- 440EPx's DDR controller is a DENALI Core + * + ************************************************************************/ +phys_size_t initdram (int board_type) +{ +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) + /* CL=4 */ + mtsdram(DDR0_02, 0x00000000); + + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ + + mtsdram(DDR0_04, 0x0B030300); + mtsdram(DDR0_05, 0x02020308); + mtsdram(DDR0_06, 0x0003C812); + mtsdram(DDR0_07, 0x00090100); + mtsdram(DDR0_08, 0x03c80001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000100); + mtsdram(DDR0_11, 0x000CC800); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x1e000000); + mtsdram(DDR0_18, 0x1e1e1e1e); + mtsdram(DDR0_19, 0x1e1e1e1e); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); +#ifdef CONFIG_DDR_ECC + mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ +#else + mtsdram(DDR0_22, 0x00267F0B); +#endif + + mtsdram(DDR0_23, 0x01000000); + mtsdram(DDR0_24, 0x01010001); + + mtsdram(DDR0_26, 0x2D93028A); + mtsdram(DDR0_27, 0x0784682B); + + mtsdram(DDR0_28, 0x00000080); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000008); + + mtsdram(DDR0_43, 0x050A0200); + mtsdram(DDR0_44, 0x00000005); + mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ + + denali_wait_for_dlllock(); + +#if defined(CONFIG_DDR_DATA_EYE) + /* -----------------------------------------------------------+ + * Perform data eye search if requested. + * ----------------------------------------------------------*/ + program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, + TLB_WORD2_I_ENABLE); + denali_core_search_data_eye(); + remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); +#endif + + /* + * Program tlb entries for this size (dynamic) + */ + program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, + MY_TLB_WORD2_I_ENABLE); + +#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_4xx_DCACHE) + /* + * If ECC is enabled, initialize the parity bits. + */ + program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); +#else /* CONFIG_4xx_DCACHE */ + /* + * Setup 2nd TLB with same physical address but different virtual address + * with cache enabled. This is done for fast ECC generation. + */ + program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); + + /* + * If ECC is enabled, initialize the parity bits. + */ + program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); + + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); +#endif /* CONFIG_4xx_DCACHE */ +#endif /* CONFIG_DDR_ECC */ + + /* + * Clear possible errors resulting from data-eye-search. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); +#endif /* CONFIG_SPL_BUILD */ + + return (CONFIG_SYS_MBYTES_SDRAM << 20); +} diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig new file mode 100644 index 00000000000..b911dbd67df --- /dev/null +++ b/configs/lcd4_lwmon5_defconfig @@ -0,0 +1,6 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_LWMON5=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5" +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig new file mode 100644 index 00000000000..0a6da688cb9 --- /dev/null +++ b/configs/lwmon5_defconfig @@ -0,0 +1,4 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_LWMON5=y +# CONFIG_CMD_SETEXPR is not set diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 9cda0bdedcc..c7b4fa3de28 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -19,7 +19,6 @@ zeus powerpc ppc4xx - - Stefan Roese sbc405 powerpc ppc4xx - - pcs440ep powerpc ppc4xx - - Stefan Roese p3p440 powerpc ppc4xx - - Stefan Roese -lwmon5 powerpc ppc4xx - - Stefan Roese csb272/csb472 powerpc ppc4xx - - Tolunay Orkun alpr powerpc ppc4xx - - Stefan Roese cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 868c51254d3..1c74e97c5e9 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -419,7 +419,8 @@ void *video_hw_init (void) board_disp_init (); #endif -#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) +#if (defined(CONFIG_LWMON5) || \ + defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h new file mode 100644 index 00000000000..513167e2ef1 --- /dev/null +++ b/include/configs/lwmon5.h @@ -0,0 +1,692 @@ +/* + * (C) Copyright 2007-2013 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * lwmon5.h - configuration for lwmon5 board + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Liebherr extra version info + */ +#define CONFIG_IDENT_STRING " - v2.0" + +/* + * High Level Configuration Options + */ +#define CONFIG_LWMON5 1 /* Board is lwmon5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ + +#ifdef CONFIG_LCD4_LWMON5 +#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ +#define CONFIG_HOSTNAME lcd4_lwmon5 +#else +#define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_HOSTNAME lwmon5 +#endif + +#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ + +#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ +#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_BOARD_RESET /* Call board_reset */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ + +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ +#define CONFIG_SYS_LIME_BASE_0 0xc0000000 +#define CONFIG_SYS_LIME_BASE_1 0xc1000000 +#define CONFIG_SYS_LIME_BASE_2 0xc2000000 +#define CONFIG_SYS_LIME_BASE_3 0xc3000000 +#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 +#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 +#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) + +#ifndef CONFIG_LCD4_LWMON5 +#define CONFIG_SYS_USB2D0_BASE 0xe0000100 +#define CONFIG_SYS_USB_DEVICE 0xe0000000 +#define CONFIG_SYS_USB_HOST 0xe0000400 +#endif + +/* + * Initial RAM & stack pointer + * + * On LWMON5 we use D-cache as init-ram and stack pointer. We also move + * the POST_WORD from OCM to a 440EPx register that preserves it's + * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) + * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) + */ +#ifndef CONFIG_LCD4_LWMON5 +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#else +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#endif +/* unused GPT0 COMP reg */ +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) +#define CONFIG_SYS_OCM_SIZE (16 << 10) +/* 440EPx errata CHIP 11: don't use last 4kbytes */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) + +/* Additional registers for watchdog timer post test */ +#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) +#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) +#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR +#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR +#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 +#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 +#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 +#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 +#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 +#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CONFIG_SYS_FLASH0 0xFC000000 +#define CONFIG_SYS_FLASH1 0xF8000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } + +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ + +#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * DDR SDRAM + */ +#define CONFIG_SYS_MBYTES_SDRAM 256 +#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#ifndef CONFIG_LCD4_LWMON5 +#define CONFIG_DDR_ECC /* enable ECC */ +#endif + +#ifndef CONFIG_LCD4_LWMON5 +/* POST support */ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ECC | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_OCM | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_SPR | \ + CONFIG_SYS_POST_UART | \ + CONFIG_SYS_POST_SYSMON | \ + CONFIG_SYS_POST_WATCHDOG | \ + CONFIG_SYS_POST_DSP | \ + CONFIG_SYS_POST_BSPEC1 | \ + CONFIG_SYS_POST_BSPEC2 | \ + CONFIG_SYS_POST_BSPEC3 | \ + CONFIG_SYS_POST_BSPEC4 | \ + CONFIG_SYS_POST_BSPEC5) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } + +#define CONFIG_POST_UART { \ + "UART test", \ + "uart", \ + "This test verifies the UART operation.", \ + POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ + &uart_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_UART \ + } + +#define CONFIG_POST_WATCHDOG { \ + "Watchdog timer test", \ + "watchdog", \ + "This test checks the watchdog timer.", \ + POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ + &lwmon5_watchdog_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_WATCHDOG \ + } + +#define CONFIG_POST_BSPEC1 { \ + "dsPIC init test", \ + "dspic_init", \ + "This test returns result of dsPIC READY test run earlier.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_init_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC1 \ + } + +#define CONFIG_POST_BSPEC2 { \ + "dsPIC test", \ + "dspic", \ + "This test gets result of dsPIC POST and dsPIC version.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC2 \ + } + +#define CONFIG_POST_BSPEC3 { \ + "FPGA test", \ + "fpga", \ + "This test checks FPGA registers and memory.", \ + POST_RAM | POST_ALWAYS | POST_MANUAL, \ + &fpga_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC3 \ + } + +#define CONFIG_POST_BSPEC4 { \ + "GDC test", \ + "gdc", \ + "This test checks GDC registers and memory.", \ + POST_RAM | POST_ALWAYS | POST_MANUAL,\ + &gdc_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC4 \ + } + +#define CONFIG_POST_BSPEC5 { \ + "SYSMON1 test", \ + "sysmon1", \ + "This test checks GPIO_62_EPX pin indicating power failure.", \ + POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ + &sysmon1_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_BSPEC5 \ + } + +#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ +#define CONFIG_LOGBUFFER +/* Reserve GPT0_COMP1-COMP5 for logbuffer header */ +#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) +#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ +#endif + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F + +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ +#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ +#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ +#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ + +#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \ + CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\ + CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ + CONFIG_SYS_I2C_DSPIC_ADDR, \ + CONFIG_SYS_I2C_DSPIC_2_ADDR, \ + CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\ + CONFIG_SYS_I2C_DSPIC_IO_ADDR } + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +/* Update size in "reg" property of NOR FLASH device tree nodes */ +#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE + +#define CONFIG_FIT /* enable FIT image support */ + +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ + +#define CONFIG_PREBOOT "setenv bootdelay 15" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=lwmon5\0" \ + "netdev=eth0\0" \ + "unlock=yes\0" \ + "logversion=2\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ + "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty addmisc;bootm\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ + "bootfile=/tftpboot/lwmon5/uImage\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ + "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ + "cp.b 200000 FFF80000 80000\0" \ + "upd=run load update\0" \ + "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ + "autoscr 200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_PPC4xx_EMAC +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 300 + +#define CONFIG_HAS_ETH0 +#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* Video console */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP + +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN + +#ifndef CONFIG_LCD4_LWMON5 +/* + * USB/EHCI + */ +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ +#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ +#define CONFIG_USB_STORAGE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif + +#ifndef CONFIG_LCD4_LWMON5 +#ifdef CONFIG_440EPX +#define CONFIG_CMD_USB +#endif +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +#ifndef CONFIG_LCD4_LWMON5 +#ifndef DEBUG +#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ +#endif +#define CONFIG_WD_PERIOD 40000 /* in usec */ +#define CONFIG_WD_MAX_RATE 66600 /* in ticks */ +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the 40x Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03000280 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) + +/* Memory Bank 1 (Lime) initialization */ +#define CONFIG_SYS_EBC_PB1AP 0x01004380 +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) + +/* Memory Bank 2 (FPGA) initialization */ +#define CONFIG_SYS_EBC_PB2AP 0x01004400 +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) + +/* Memory Bank 3 (FPGA2) initialization */ +#define CONFIG_SYS_EBC_PB3AP 0x01004400 +#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) + +#define CONFIG_SYS_EBC_CFG 0xb8400000 + +/* + * Graphics (Fujitsu Lime) + */ +/* SDRAM Clock frequency adjustment register */ +#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 +#if 1 /* 133MHz is not tested enough, use 100MHz for now */ +/* Lime Clock frequency is to set 100MHz */ +#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 +#else +/* Lime Clock frequency for 133MHz */ +#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 +#endif + +/* SDRAM Parameter register */ +#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC +/* + * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + * and pixel flare on display when 133MHz was configured. According to + * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed + * Grade + */ +#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ +#else +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ +#endif + +/* + * GPIO Setup + */ +#define CONFIG_SYS_GPIO_PHY1_RST 12 +#define CONFIG_SYS_GPIO_FLASH_WP 14 +#define CONFIG_SYS_GPIO_PHY0_RST 22 +#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 +#define CONFIG_SYS_GPIO_DSPIC_READY 51 +#define CONFIG_SYS_GPIO_CAN_ENABLE 53 +#define CONFIG_SYS_GPIO_LSB_ENABLE 54 +#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 +#define CONFIG_SYS_GPIO_HIGHSIDE 56 +#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 +#define CONFIG_SYS_GPIO_BOARD_RESET 58 +#define CONFIG_SYS_GPIO_LIME_S 59 +#define CONFIG_SYS_GPIO_LIME_RST 60 +#define CONFIG_SYS_GPIO_SYSMON_STATUS 62 +#define CONFIG_SYS_GPIO_WATCHDOG 63 + +/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ +#ifdef CONFIG_LCD4_LWMON5 +#define GPIO49_VAL 0 +#else +#define GPIO49_VAL 1 +#endif + +/* + * PPC440 GPIO Configuration + */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * SPL related defines + */ +#ifdef CONFIG_LCD4_LWMON5 +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NOR_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ +#define CONFIG_SYS_SPL_MAX_LEN (64 << 10) +#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ +#define CONFIG_SPL_SERIAL_SUPPORT + +/* Place BSS for SPL near end of SDRAM */ +#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20) +#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) + +#define CONFIG_SPL_OS_BOOT +/* Place patched DT blob (fdt) at this address */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 + +#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin" + +/* Settings for real U-Boot to be loaded from NOR flash */ +#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_UBOOT_START 0x01002100 + +#define CONFIG_SYS_OS_BASE 0xf8000000 +#define CONFIG_SYS_FDT_BASE 0xf87c0000 +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From c0c7a5542819d9f49db1cc05f9cec05e6a3f1bb3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 2 Oct 2015 08:20:36 +0200 Subject: ppc4xx: Convert lwmon5 board to generic board Add CONFIG_SYS_GENERIC_BOARD to lwmon5.h and CONFIG_DISPLAY_BOARDINFO to Kconfig file. Signed-off-by: Stefan Roese Cc: Masahiro Yamada --- board/lwmon5/Kconfig | 4 ++++ include/configs/lwmon5.h | 2 ++ 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig index 90566d825bc..7b8c605a070 100644 --- a/board/lwmon5/Kconfig +++ b/board/lwmon5/Kconfig @@ -6,4 +6,8 @@ config SYS_BOARD config SYS_CONFIG_NAME default "lwmon5" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 513167e2ef1..2a50bfea161 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -23,6 +23,8 @@ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_SYS_GENERIC_BOARD + #ifdef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ #define CONFIG_HOSTNAME lcd4_lwmon5 -- cgit v1.3.1 From b6b5e394db62ac17e496dce9e6e9451435c8be62 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 2 Oct 2015 08:20:37 +0200 Subject: ppc4xx: Remove lcd4_lwmon5 support This platform has not gone into production. So lets remove it. Signed-off-by: Stefan Roese Cc: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 1 - board/lwmon5/MAINTAINERS | 1 - board/lwmon5/lwmon5.c | 8 ------ board/lwmon5/sdram.c | 2 -- configs/lcd4_lwmon5_defconfig | 6 ---- include/configs/lwmon5.h | 63 +---------------------------------------- 6 files changed, 1 insertion(+), 80 deletions(-) delete mode 100644 configs/lcd4_lwmon5_defconfig (limited to 'include') diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 8d3ba8d73f6..ce58d865124 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -10,7 +10,6 @@ choice config TARGET_LWMON5 bool "Support lwmon5" - select SUPPORT_SPL config TARGET_T3CORP bool "Support t3corp" diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS index 7402ab67580..3ea1888cea9 100644 --- a/board/lwmon5/MAINTAINERS +++ b/board/lwmon5/MAINTAINERS @@ -3,5 +3,4 @@ M: Stefan Roese S: Maintained F: board/lwmon5/ F: include/configs/lwmon5.h -F: configs/lcd4_lwmon5_defconfig F: configs/lwmon5_defconfig diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index e9aa0b77de5..8ad67128411 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -187,11 +187,9 @@ int misc_init_r(void) u32 pbcr; int size_val = 0; u32 reg; -#ifndef CONFIG_LCD4_LWMON5 unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1, sdr0_srst; -#endif /* * FLASH stuff... @@ -222,7 +220,6 @@ int misc_init_r(void) CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, &flash_info[cfi_flash_num_flash_banks - 1]); -#ifndef CONFIG_LCD4_LWMON5 /* * USB suff... */ @@ -296,7 +293,6 @@ int misc_init_r(void) /* 7. Reassert internal PHY reset: */ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); udelay(1000); -#endif /* * Clear resets @@ -304,9 +300,7 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); -#ifndef CONFIG_LCD4_LWMON5 printf("USB: Host(int phy) Device(ext phy)\n"); -#endif /* * Clear PLB4A0_ACR[WRP] @@ -316,12 +310,10 @@ int misc_init_r(void) reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; mtdcr(PLB4A0_ACR, reg); -#ifndef CONFIG_LCD4_LWMON5 /* * Init matrix keyboard */ misc_init_r_kbd(); -#endif return 0; } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 5dfbb0bc256..bcb344940bd 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -147,7 +147,6 @@ static void program_ecc(u32 start_address, ************************************************************************/ phys_size_t initdram (int board_type) { -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) /* CL=4 */ mtsdram(DDR0_02, 0x00000000); @@ -241,7 +240,6 @@ phys_size_t initdram (int board_type) * exceptions are enabled. */ set_mcsr(get_mcsr()); -#endif /* CONFIG_SPL_BUILD */ return (CONFIG_SYS_MBYTES_SDRAM << 20); } diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig deleted file mode 100644 index b911dbd67df..00000000000 --- a/configs/lcd4_lwmon5_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_LWMON5=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5" -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 2a50bfea161..26136a52cee 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -25,13 +25,8 @@ #define CONFIG_SYS_GENERIC_BOARD -#ifdef CONFIG_LCD4_LWMON5 -#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ -#define CONFIG_HOSTNAME lcd4_lwmon5 -#else #define CONFIG_SYS_TEXT_BASE 0xFFF80000 #define CONFIG_HOSTNAME lwmon5 -#endif #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ @@ -67,11 +62,9 @@ #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) -#ifndef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 -#endif /* * Initial RAM & stack pointer @@ -81,20 +74,13 @@ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) */ -#ifndef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) -#endif + /* unused GPT0 COMP reg */ #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) #define CONFIG_SYS_OCM_SIZE (16 << 10) @@ -168,11 +154,8 @@ #define CONFIG_SYS_MBYTES_SDRAM 256 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#ifndef CONFIG_LCD4_LWMON5 #define CONFIG_DDR_ECC /* enable ECC */ -#endif -#ifndef CONFIG_LCD4_LWMON5 /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_CPU | \ @@ -281,7 +264,6 @@ #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -#endif /* * I2C @@ -401,7 +383,6 @@ #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN -#ifndef CONFIG_LCD4_LWMON5 /* * USB/EHCI */ @@ -417,7 +398,6 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION -#endif /* * BOOTP options @@ -448,11 +428,9 @@ #define CONFIG_CMD_BMP #endif -#ifndef CONFIG_LCD4_LWMON5 #ifdef CONFIG_440EPX #define CONFIG_CMD_USB #endif -#endif /* * Miscellaneous configurable options @@ -485,13 +463,11 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ -#ifndef CONFIG_LCD4_LWMON5 #ifndef DEBUG #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ #endif #define CONFIG_WD_PERIOD 40000 /* in usec */ #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ -#endif /* * For booting Linux, the board info and command line data @@ -572,12 +548,7 @@ #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 #define CONFIG_SYS_GPIO_WATCHDOG 63 -/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ -#ifdef CONFIG_LCD4_LWMON5 -#define GPIO49_VAL 0 -#else #define GPIO49_VAL 1 -#endif /* * PPC440 GPIO Configuration @@ -659,36 +630,4 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif -/* - * SPL related defines - */ -#ifdef CONFIG_LCD4_LWMON5 -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NOR_SUPPORT -#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ -#define CONFIG_SYS_SPL_MAX_LEN (64 << 10) -#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ -#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ -#define CONFIG_SPL_SERIAL_SUPPORT - -/* Place BSS for SPL near end of SDRAM */ -#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20) -#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) - -#define CONFIG_SPL_OS_BOOT -/* Place patched DT blob (fdt) at this address */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 - -#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin" - -/* Settings for real U-Boot to be loaded from NOR flash */ -#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_UBOOT_START 0x01002100 - -#define CONFIG_SYS_OS_BASE 0xf8000000 -#define CONFIG_SYS_FDT_BASE 0xf87c0000 -#endif - #endif /* __CONFIG_H */ -- cgit v1.3.1 From 027b728d4aafb5cf97abc804944a77b837b0f07f Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 6 Oct 2015 20:03:53 -0700 Subject: Add support for LZ4 decompression algorithm This patch adds support for LZ4-compressed FIT image contents. This algorithm has a slightly worse compression ration than LZO while being nearly twice as fast to decompress. When loading images from a fast storage medium this usually results in a boot time win. Sandbox-tested only since I don't have a U-Boot development system set up right now. The code was imported unchanged from coreboot where it's proven to work, though. I'm mostly interested in getting this recognized by mkImage for use in a downstream project. Signed-off-by: Julius Werner Acked-by: Simon Glass --- common/bootm.c | 9 ++ common/image.c | 1 + configs/sandbox_defconfig | 1 + include/common.h | 3 + include/image.h | 1 + lib/Kconfig | 18 ++++ lib/Makefile | 1 + lib/lz4.c | 243 ++++++++++++++++++++++++++++++++++++++++++++++ lib/lz4_wrapper.c | 137 ++++++++++++++++++++++++++ test/compression.c | 57 +++++++++++ 10 files changed, 471 insertions(+) create mode 100644 lib/lz4.c create mode 100644 lib/lz4_wrapper.c (limited to 'include') diff --git a/common/bootm.c b/common/bootm.c index c0d0d09411f..58936ca4978 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -389,6 +389,15 @@ int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, break; } #endif /* CONFIG_LZO */ +#ifdef CONFIG_LZ4 + case IH_COMP_LZ4: { + size_t size = unc_len; + + ret = ulz4fn(image_buf, image_len, load_buf, &size); + image_len = size; + break; + } +#endif /* CONFIG_LZ4 */ default: printf("Unimplemented compression type %d\n", comp); return BOOTM_ERR_UNIMPLEMENTED; diff --git a/common/image.c b/common/image.c index 1325e07953e..c33749d51d8 100644 --- a/common/image.c +++ b/common/image.c @@ -167,6 +167,7 @@ static const table_entry_t uimage_comp[] = { { IH_COMP_GZIP, "gzip", "gzip compressed", }, { IH_COMP_LZMA, "lzma", "lzma compressed", }, { IH_COMP_LZO, "lzo", "lzo compressed", }, + { IH_COMP_LZ4, "lz4", "lz4 compressed", }, { -1, "", "", }, }; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index ae96b63e972..b2675c706d3 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -56,6 +56,7 @@ CONFIG_USB_STORAGE=y CONFIG_SYS_VSNPRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y +CONFIG_LZ4=y CONFIG_ERRNO_STR=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y diff --git a/include/common.h b/include/common.h index 68b24d0778d..ecb1f0682ed 100644 --- a/include/common.h +++ b/include/common.h @@ -826,6 +826,9 @@ int gzwrite(unsigned char *src, int len, u64 startoffs, u64 szexpected); +/* lib/lz4_wrapper.c */ +int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn); + /* lib/qsort.c */ void qsort(void *base, size_t nmemb, size_t size, int(*compar)(const void *, const void *)); diff --git a/include/image.h b/include/image.h index 8a864aeb227..08ae24a86b8 100644 --- a/include/image.h +++ b/include/image.h @@ -259,6 +259,7 @@ struct lmb; #define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ #define IH_COMP_LZMA 3 /* lzma Compression Used */ #define IH_COMP_LZO 4 /* lzo Compression Used */ +#define IH_COMP_LZ4 5 /* lz4 Compression Used */ #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ diff --git a/lib/Kconfig b/lib/Kconfig index 067307276ec..a8f8460d1de 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -100,6 +100,24 @@ config SHA_PROG_HW_ACCEL is performed in hardware. endmenu +menu "Compression Support" + +config LZ4 + bool "Enable LZ4 decompression support" + help + If this option is set, support for LZ4 compressed images + is included. The LZ4 algorithm can run in-place as long as the + compressed image is loaded to the end of the output buffer, and + trades lower compression ratios for much faster decompression. + + NOTE: This implements the release version of the LZ4 frame + format as generated by default by the 'lz4' command line tool. + This is not the same as the outdated, less efficient legacy + frame format currently (2015) implemented in the Linux kernel + (generated by 'lz4 -l'). The two formats are incompatible. + +endmenu + config ERRNO_STR bool "Enable function for getting errno-related string message" help diff --git a/lib/Makefile b/lib/Makefile index 96f832edd2d..3eecefaa79f 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o obj-y += initcall.o obj-$(CONFIG_LMB) += lmb.o obj-y += ldiv.o +obj-$(CONFIG_LZ4) += lz4_wrapper.o obj-$(CONFIG_MD5) += md5.o obj-y += net_utils.o obj-$(CONFIG_PHYSMEM) += physmem.o diff --git a/lib/lz4.c b/lib/lz4.c new file mode 100644 index 00000000000..f518341af5c --- /dev/null +++ b/lib/lz4.c @@ -0,0 +1,243 @@ +/* + LZ4 - Fast LZ compression algorithm + Copyright (C) 2011-2015, Yann Collet. + + SPDX-License-Identifier: BSD-2-Clause + + You can contact the author at : + - LZ4 source repository : https://github.com/Cyan4973/lz4 + - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c +*/ + + +/************************************** +* Reading and writing into memory +**************************************/ + +/* customized version of memcpy, which may overwrite up to 7 bytes beyond dstEnd */ +static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd) +{ + BYTE* d = (BYTE*)dstPtr; + const BYTE* s = (const BYTE*)srcPtr; + BYTE* e = (BYTE*)dstEnd; + do { LZ4_copy8(d,s); d+=8; s+=8; } while (d oend-MFLIMIT)) oexit = oend-MFLIMIT; /* targetOutputSize too high => decode everything */ + if ((endOnInput) && (unlikely(outputSize==0))) return ((inputSize==1) && (*ip==0)) ? 0 : -1; /* Empty output buffer */ + if ((!endOnInput) && (unlikely(outputSize==0))) return (*ip==0?1:-1); + + + /* Main Loop */ + while (1) + { + unsigned token; + size_t length; + const BYTE* match; + + /* get literal length */ + token = *ip++; + if ((length=(token>>ML_BITS)) == RUN_MASK) + { + unsigned s; + do + { + s = *ip++; + length += s; + } + while (likely((endOnInput)?ip(partialDecoding?oexit:oend-MFLIMIT)) || (ip+length>iend-(2+1+LASTLITERALS))) ) + || ((!endOnInput) && (cpy>oend-COPYLENGTH))) + { + if (partialDecoding) + { + if (cpy > oend) goto _output_error; /* Error : write attempt beyond end of output buffer */ + if ((endOnInput) && (ip+length > iend)) goto _output_error; /* Error : read attempt beyond end of input buffer */ + } + else + { + if ((!endOnInput) && (cpy != oend)) goto _output_error; /* Error : block decoding must stop exactly there */ + if ((endOnInput) && ((ip+length != iend) || (cpy > oend))) goto _output_error; /* Error : input must be consumed */ + } + memcpy(op, ip, length); + ip += length; + op += length; + break; /* Necessarily EOF, due to parsing restrictions */ + } + LZ4_wildCopy(op, ip, cpy); + ip += length; op = cpy; + + /* get offset */ + match = cpy - LZ4_readLE16(ip); ip+=2; + if ((checkOffset) && (unlikely(match < lowLimit))) goto _output_error; /* Error : offset outside destination buffer */ + + /* get matchlength */ + length = token & ML_MASK; + if (length == ML_MASK) + { + unsigned s; + do + { + if ((endOnInput) && (ip > iend-LASTLITERALS)) goto _output_error; + s = *ip++; + length += s; + } while (s==255); + if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)op)) goto _output_error; /* overflow detection */ + } + length += MINMATCH; + + /* check external dictionary */ + if ((dict==usingExtDict) && (match < lowPrefix)) + { + if (unlikely(op+length > oend-LASTLITERALS)) goto _output_error; /* doesn't respect parsing restriction */ + + if (length <= (size_t)(lowPrefix-match)) + { + /* match can be copied as a single segment from external dictionary */ + match = dictEnd - (lowPrefix-match); + memmove(op, match, length); op += length; + } + else + { + /* match encompass external dictionary and current segment */ + size_t copySize = (size_t)(lowPrefix-match); + memcpy(op, dictEnd - copySize, copySize); + op += copySize; + copySize = length - copySize; + if (copySize > (size_t)(op-lowPrefix)) /* overlap within current segment */ + { + BYTE* const endOfMatch = op + copySize; + const BYTE* copyFrom = lowPrefix; + while (op < endOfMatch) *op++ = *copyFrom++; + } + else + { + memcpy(op, lowPrefix, copySize); + op += copySize; + } + } + continue; + } + + /* copy repeated sequence */ + cpy = op + length; + if (unlikely((op-match)<8)) + { + const size_t dec64 = dec64table[op-match]; + op[0] = match[0]; + op[1] = match[1]; + op[2] = match[2]; + op[3] = match[3]; + match += dec32table[op-match]; + LZ4_copy4(op+4, match); + op += 8; match -= dec64; + } else { LZ4_copy8(op, match); op+=8; match+=8; } + + if (unlikely(cpy>oend-12)) + { + if (cpy > oend-LASTLITERALS) goto _output_error; /* Error : last LASTLITERALS bytes must be literals */ + if (op < oend-8) + { + LZ4_wildCopy(op, match, oend-8); + match += (oend-8) - op; + op = oend-8; + } + while (op +#include +#include +#include + +static u16 LZ4_readLE16(const void *src) { return le16_to_cpu(*(u16 *)src); } +static void LZ4_copy4(void *dst, const void *src) { *(u32 *)dst = *(u32 *)src; } +static void LZ4_copy8(void *dst, const void *src) { *(u64 *)dst = *(u64 *)src; } + +typedef uint8_t BYTE; +typedef uint16_t U16; +typedef uint32_t U32; +typedef int32_t S32; +typedef uint64_t U64; + +#define FORCE_INLINE static inline __attribute__((always_inline)) + +/* Unaltered (except removing unrelated code) from github.com/Cyan4973/lz4. */ +#include "lz4.c" /* #include for inlining, do not link! */ + +#define LZ4F_MAGIC 0x184D2204 + +struct lz4_frame_header { + u32 magic; + union { + u8 flags; + struct { + u8 reserved0:2; + u8 has_content_checksum:1; + u8 has_content_size:1; + u8 has_block_checksum:1; + u8 independent_blocks:1; + u8 version:2; + }; + }; + union { + u8 block_descriptor; + struct { + u8 reserved1:4; + u8 max_block_size:3; + u8 reserved2:1; + }; + }; + /* + u64 content_size iff has_content_size is set */ + /* + u8 header_checksum */ +} __packed; + +struct lz4_block_header { + union { + u32 raw; + struct { + u32 size:31; + u32 not_compressed:1; + }; + }; + /* + size bytes of data */ + /* + u32 block_checksum iff has_block_checksum is set */ +} __packed; + +int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn) +{ + const void *end = dst + *dstn; + const void *in = src; + void *out = dst; + int has_block_checksum; + int ret; + *dstn = 0; + + { /* With in-place decompression the header may become invalid later. */ + const struct lz4_frame_header *h = in; + + if (srcn < sizeof(*h) + sizeof(u64) + sizeof(u8)) + return -EINVAL; /* input overrun */ + + /* We assume there's always only a single, standard frame. */ + if (le32_to_cpu(h->magic) != LZ4F_MAGIC || h->version != 1) + return -EPROTONOSUPPORT; /* unknown format */ + if (h->reserved0 || h->reserved1 || h->reserved2) + return -EINVAL; /* reserved must be zero */ + if (!h->independent_blocks) + return -EPROTONOSUPPORT; /* we can't support this yet */ + has_block_checksum = h->has_block_checksum; + + in += sizeof(*h); + if (h->has_content_size) + in += sizeof(u64); + in += sizeof(u8); + } + + while (1) { + struct lz4_block_header b = { .raw = le32_to_cpu(*(u32 *)in) }; + in += sizeof(struct lz4_block_header); + + if (in - src + b.size > srcn) { + ret = -EINVAL; /* input overrun */ + break; + } + + if (!b.size) { + ret = 0; /* decompression successful */ + break; + } + + if (b.not_compressed) { + size_t size = min((ptrdiff_t)b.size, end - out); + memcpy(out, in, size); + out += size; + if (size < b.size) { + ret = -ENOBUFS; /* output overrun */ + break; + } + } else { + /* constant folding essential, do not touch params! */ + ret = LZ4_decompress_generic(in, out, b.size, + end - out, endOnInputSize, + full, 0, noDict, out, NULL, 0); + if (ret < 0) { + ret = -EPROTO; /* decompression error */ + break; + } + out += ret; + } + + in += b.size; + if (has_block_checksum) + in += sizeof(u32); + } + + *dstn = out - dst; + return ret; +} diff --git a/test/compression.c b/test/compression.c index 7ef3a8c9f57..be4e04e6cc0 100644 --- a/test/compression.c +++ b/test/compression.c @@ -95,6 +95,28 @@ static const char lzo_compressed[] = "\x73\x61\x67\x65\x73\x2e\x0a\x11\x00\x00\x00\x00\x00\x00"; static const unsigned long lzo_compressed_size = 334; +/* lz4 -z /tmp/plain.txt > /tmp/plain.lz4 */ +static const char lz4_compressed[] = + "\x04\x22\x4d\x18\x64\x70\xb9\x01\x01\x00\x00\xff\x19\x49\x20\x61" + "\x6d\x20\x61\x20\x68\x69\x67\x68\x6c\x79\x20\x63\x6f\x6d\x70\x72" + "\x65\x73\x73\x61\x62\x6c\x65\x20\x62\x69\x74\x20\x6f\x66\x20\x74" + "\x65\x78\x74\x2e\x0a\x28\x00\x3d\xf1\x25\x54\x68\x65\x72\x65\x20" + "\x61\x72\x65\x20\x6d\x61\x6e\x79\x20\x6c\x69\x6b\x65\x20\x6d\x65" + "\x2c\x20\x62\x75\x74\x20\x74\x68\x69\x73\x20\x6f\x6e\x65\x20\x69" + "\x73\x20\x6d\x69\x6e\x65\x2e\x0a\x49\x66\x20\x49\x20\x77\x32\x00" + "\xd1\x6e\x79\x20\x73\x68\x6f\x72\x74\x65\x72\x2c\x20\x74\x45\x00" + "\xf4\x0b\x77\x6f\x75\x6c\x64\x6e\x27\x74\x20\x62\x65\x20\x6d\x75" + "\x63\x68\x20\x73\x65\x6e\x73\x65\x20\x69\x6e\x0a\xcf\x00\x50\x69" + "\x6e\x67\x20\x6d\x12\x00\x00\x32\x00\xf0\x11\x20\x66\x69\x72\x73" + "\x74\x20\x70\x6c\x61\x63\x65\x2e\x20\x41\x74\x20\x6c\x65\x61\x73" + "\x74\x20\x77\x69\x74\x68\x20\x6c\x7a\x6f\x2c\x63\x00\xf5\x14\x77" + "\x61\x79\x2c\x0a\x77\x68\x69\x63\x68\x20\x61\x70\x70\x65\x61\x72" + "\x73\x20\x74\x6f\x20\x62\x65\x68\x61\x76\x65\x20\x70\x6f\x6f\x72" + "\x6c\x79\x4e\x00\x30\x61\x63\x65\x27\x01\x01\x95\x00\x01\x2d\x01" + "\xb0\x0a\x6d\x65\x73\x73\x61\x67\x65\x73\x2e\x0a\x00\x00\x00\x00" + "\x9d\x12\x8c\x9d"; +static const unsigned long lz4_compressed_size = 276; + #define TEST_BUFFER_SIZE 512 @@ -227,6 +249,39 @@ static int uncompress_using_lzo(void *in, unsigned long in_size, return (ret != LZO_E_OK); } +static int compress_using_lz4(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + /* There is no lz4 compression in u-boot, so fake it. */ + assert(in_size == strlen(plain)); + assert(memcmp(plain, in, in_size) == 0); + + if (lz4_compressed_size > out_max) + return -1; + + memcpy(out, lz4_compressed, lz4_compressed_size); + if (out_size) + *out_size = lz4_compressed_size; + + return 0; +} + +static int uncompress_using_lz4(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + int ret; + size_t input_size = in_size; + size_t output_size = out_max; + + ret = ulz4fn(in, input_size, out, &output_size); + if (out_size) + *out_size = output_size; + + return (ret != 0); +} + #define errcheck(statement) if (!(statement)) { \ fprintf(stderr, "\tFailed: %s\n", #statement); \ ret = 1; \ @@ -325,6 +380,7 @@ static int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, err += run_test("bzip2", compress_using_bzip2, uncompress_using_bzip2); err += run_test("lzma", compress_using_lzma, uncompress_using_lzma); err += run_test("lzo", compress_using_lzo, uncompress_using_lzo); + err += run_test("lz4", compress_using_lz4, uncompress_using_lz4); printf("ut_compression %s\n", err == 0 ? "ok" : "FAILED"); @@ -401,6 +457,7 @@ static int do_ut_image_decomp(cmd_tbl_t *cmdtp, int flag, int argc, err |= run_bootm_test(IH_COMP_BZIP2, compress_using_bzip2); err |= run_bootm_test(IH_COMP_LZMA, compress_using_lzma); err |= run_bootm_test(IH_COMP_LZO, compress_using_lzo); + err |= run_bootm_test(IH_COMP_LZ4, compress_using_lz4); err |= run_bootm_test(IH_COMP_NONE, compress_using_none); printf("ut_image_decomp %s\n", err == 0 ? "ok" : "FAILED"); -- cgit v1.3.1 From e392b923ed6d6acff08b0a7aa5f457fff80fb0de Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Tue, 29 Sep 2015 10:27:09 +0100 Subject: arndale: Apply Cortex-A15 errata #773022 and #774769 We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell --- README | 4 +++- arch/arm/cpu/armv7/nonsec_virt.S | 14 ++++++++++++++ include/configs/arndale.h | 4 ++++ 3 files changed, 21 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/README b/README index c22b60b49bc..0dc657d0a58 100644 --- a/README +++ b/README @@ -681,8 +681,10 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 - CONFIG_ARM_ERRATA_794072 CONFIG_ARM_ERRATA_761320 + CONFIG_ARM_ERRATA_773022 + CONFIG_ARM_ERRATA_774769 + CONFIG_ARM_ERRATA_794072 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 30d81db8b81..31d1c9e3484 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -53,6 +53,20 @@ _secure_monitor: bl psci_arch_init #endif +#ifdef CONFIG_ARM_ERRATA_773022 + mrc p15, 0, r5, c1, c0, 1 + orr r5, r5, #(1 << 1) + mcr p15, 0, r5, c1, c0, 1 + isb +#endif + +#ifdef CONFIG_ARM_ERRATA_774769 + mrc p15, 0, r5, c1, c0, 1 + orr r5, r5, #(1 << 25) + mcr p15, 0, r5, c1, c0, 1 + isb +#endif + mrc p15, 0, r5, c1, c1, 0 @ read SCR bic r5, r5, #0x4a @ clear IRQ, EA, nET bits orr r5, r5, #0x31 @ enable NS, AW, FW bits diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 437a7454146..b08f3412275 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -49,6 +49,10 @@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 +/* CPU Errata */ +#define CONFIG_ARM_ERRATA_773022 +#define CONFIG_ARM_ERRATA_774769 + /* Power */ #define CONFIG_POWER #define CONFIG_POWER_I2C -- cgit v1.3.1 From 040ef8f5652a5dd85485e88945ed7b0f0fa3cce5 Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD (3ADEV)" Date: Sun, 11 Oct 2015 20:06:39 +0200 Subject: pcm052: fix MTD partitioning MTD partitioning in current pcm052 configuration is inconsistent. Fix it across MTDPARTS_DEFAULT, CONFIG_EXTRA_ENV_SETTINGS, and CONFIG_ENV_OFFSET[_REDUND]. Signed-off-by: Albert ARIBAUD (3ADEV) --- include/configs/pcm052.h | 120 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 85 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 903f94c17e4..150698ecaa9 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -60,14 +60,15 @@ #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE -#define MTDIDS_DEFAULT "nand0=NAND,nor0=qspi0-a,nor1=qspi0-b" +#define MTDIDS_DEFAULT "nand0=NAND" #define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ ",384k(bootloader)"\ ",128k(env1)"\ ",128k(env2)"\ - ",3840k(kernel)"\ - ",-(rootfs)"\ - ",qspi0-a:-(jffs2),qspio0-b:-(jffs2)" + ",128k(dtb)"\ + ",6144k(kernel)"\ + ",65536k(ramdisk)"\ + ",450944k(root)" #endif #define CONFIG_MMC @@ -135,36 +136,85 @@ #define CONFIG_BOARD_SIZE_LIMIT 524288 #define CONFIG_BOOTCOMMAND "run bootcmd_sd" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile=uImage\0" \ - "bootargs_base=setenv bootargs rw mem=256M " \ - "console=ttymxc1,115200n8\0" \ - "bootargs_sd=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 rootwait\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.imx\0" \ + "blsec_addr=0x81000000\0" \ + "blimg_addr=0x81000400\0" \ + "kernel_file=zImage\0" \ + "kernel_addr=0x82000000\0" \ + "fdt_file=vf610-pcm052.dtb\0" \ + "fdt_addr=0x81000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "tftploc=/path/to/tftp/directory/\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "bootargs_base=setenv bootargs rw mem=256M " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ - "bootargs_nand=setenv bootargs ${bootargs} " \ - "root=/dev/mtdblock2 rootfstype=jffs2\0" \ - "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; mmc rescan; " \ - "fatload mmc 0:1 ${loadaddr} ${bootfile}; bootm ${loadaddr}\0" \ - "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ - "tftpboot ${loadaddr} ${tftploc}${bootfile}; bootm\0" \ - "bootcmd_nand='run bootargs_base bootargs_nand bootargs_mtd; " \ - "nand read ${loadaddr} 0x000E0000 0x3C0000; " \ - "bootm ${loadaddr}\0" \ - "tftploc=/path/to/tftp/directory/\0" \ - "nfs_root=/path/to/nfs/root\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "update_kernel_from_sd=mw.b $(loadaddr) 0xff 0x3C0000; " \ - "mmc rescan; fatload mmc 0:2 ${loadaddr} ${bootfile}; " \ - "nand erase 0xE0000 0x3C0000; " \ - "nand write.i ${loadaddr} 0xE0000 0x3C0000\0" \ - "update_rootfs_from_tftp=mw.b ${loadaddr} 0xff 0x8F20000; " \ - "tftp ${loadaddr} ${tftp}${filesys}; " \ - "nand erase 0x4A0000 0x8F20000; " \ - "nand write.i ${loadaddr} 0x4A0000 0x8F20000\0" \ - "filesys=rootfs.jffs2\0" + "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ + "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ + "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ + "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} ramdisk; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_tftp=mtdparts default; " \ + "nand read ${blsec_addr} bootloader; " \ + "mw.b ${blimg_addr} 0xff 0x5FC00; " \ + "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ + "nand erase.part bootloader; " \ + "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ + "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ + "${kernel_file}; " \ + "then mtdparts default; " \ + "nand erase.part kernel; " \ + "nand write ${kernel_addr} kernel ${filesize}; " \ + "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ + "nand erase.part dtb; " \ + "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ + "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "then setenv fdtsize ${filesize}; " \ + "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ + "mtdparts default; " \ + "nand erase.part dtb; " \ + "nand write ${fdt_addr} dtb ${fdtsize}; " \ + "nand erase.part kernel; " \ + "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ + "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then mtdparts default; " \ + "nand erase.part root; " \ + "ubi part root; " \ + "ubi create rootfs; " \ + "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then mtdparts default; " \ + "nand erase.part ramdisk; " \ + "nand write ${ram_addr} ramdisk ${filesize}; fi\0" /* miscellaneous commands */ #define CONFIG_CMD_ELF @@ -220,9 +270,9 @@ #ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_OFFSET 0xA0000 #define CONFIG_ENV_SIZE_REDUND (8 * 1024) -#define CONFIG_ENV_OFFSET_REDUND 0xA0000 +#define CONFIG_ENV_OFFSET_REDUND 0xC0000 #endif #define CONFIG_OF_LIBFDT -- cgit v1.3.1 From f532727d16ebd3f8f9464aa503a1990f2f3b3211 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 3 Oct 2015 14:20:59 -0300 Subject: imx_watchdog: Add a header file for watchdog registers Create fsl_wdog.h to store the watchdog registers and bit fields. This can be useful when accesses to the watchdog block are made from other parts, such as arch/arm/ cpu code. Signed-off-by: Fabio Estevam --- drivers/watchdog/imx_watchdog.c | 14 +------------- include/fsl_wdog.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 13 deletions(-) create mode 100644 include/fsl_wdog.h (limited to 'include') diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 9a77a54192b..0d775956bff 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,19 +8,7 @@ #include #include #include - -struct watchdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ -}; - -#define WCR_WDZST 0x01 -#define WCR_WDBG 0x02 -#define WCR_WDE 0x04 /* WDOG enable */ -#define WCR_WDT 0x08 -#define WCR_SRS 0x10 -#define SET_WCR_WT(x) (x << 8) +#include #ifdef CONFIG_IMX_WATCHDOG void hw_watchdog_reset(void) diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h new file mode 100644 index 00000000000..d15a70cedba --- /dev/null +++ b/include/fsl_wdog.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +struct watchdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ +}; + +#define WCR_WDZST 0x01 +#define WCR_WDBG 0x02 +#define WCR_WDE 0x04 +#define WCR_WDT 0x08 +#define WCR_SRS 0x10 +#define SET_WCR_WT(x) (x << 8) -- cgit v1.3.1