From 97c0db6ca524116472bd6c7e875283ca91158262 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 13 Mar 2023 14:31:34 -0700 Subject: config_distro_bootcmd: remove booting environment variables from SPL environment SPL environments don't need commands that they can never use. Avoid errors with CONFIG_IS_ENABLED conversions by skipping them now. Signed-off-by: Troy Kisky Reviewed-by: Simon Glass --- include/config_distro_bootcmd.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 9d2a225e7eb..2a136b96a6d 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -35,11 +35,15 @@ #devtypel "_boot=" \ BOOTENV_SHARED_BLKDEV_BODY(devtypel) +#define BOOTENV_DEV_BLKDEV_NONE(devtypeu, devtypel, instance) + #define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "devnum=" #instance "; " \ "run " #devtypel "_boot\0" +#define BOOTENV_DEV_NAME_BLKDEV_NONE(devtypeu, devtypel, instance) + #define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -59,6 +63,10 @@ #define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) #define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_SHARED_MMC +#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_SHARED_MMC #define BOOTENV_DEV_MMC \ @@ -190,6 +198,10 @@ #define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata) #define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_SHARED_SATA +#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_SHARED_SATA #define BOOTENV_DEV_SATA \ @@ -293,6 +305,11 @@ BOOTENV_SHARED_BLKDEV_BODY(usb) #define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_RUN_NET_USB_START +#define BOOTENV_SHARED_USB +#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_RUN_NET_USB_START #define BOOTENV_SHARED_USB @@ -395,6 +412,9 @@ "\0" #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ "dhcp " +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_DEV_DHCP BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_DHCP BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_DEV_DHCP \ BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP @@ -413,6 +433,9 @@ "fi\0" #define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \ "pxe " +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_DEV_PXE BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_PXE BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_DEV_PXE \ BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE -- cgit v1.3.1 From 55e4505dd2cc3085174862711891122ef02741da Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 13 Mar 2023 14:31:35 -0700 Subject: ofnode: fdt_support definitions needed if OF_CONTROL is enabled With the use of CONFIG_IS_ENABLED in code, instead of at the preprocessor level, these defines are still needed if OF_CONTROL is enabled. Signed-off-by: Troy Kisky Reviewed-by: Simon Glass --- include/fdt_support.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 5638bd4f165..eeb83e6251d 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -7,7 +7,8 @@ #ifndef __FDT_SUPPORT_H #define __FDT_SUPPORT_H -#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC) +#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \ + !defined(USE_HOSTCC) #include #include -- cgit v1.3.1 From 1781ec67f43ae6fcaec628831b09a587f5cab174 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Mon, 13 Mar 2023 14:31:44 -0700 Subject: power: pmic: add dm style definitions if not CONFIG_IS_ENABLED(POWER_LEGACY) This avoids an error in converting to CONFIG_IS_ENABLED(DM_PMIC). Many boards SPL code needs these definitions to compile, even if the functions are not linked. Signed-off-by: Troy Kisky Reviewed-by: Simon Glass --- include/power/pmic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/power/pmic.h b/include/power/pmic.h index 70f2709bd0b..636221692d0 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -86,7 +86,7 @@ struct pmic { #endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ /* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ -#ifdef CONFIG_DM_PMIC +#if defined(CONFIG_DM_PMIC) || !CONFIG_IS_ENABLED(POWER_LEGACY) /** * U-Boot PMIC Framework * ===================== -- cgit v1.3.1 From 6ab7c3d6bab1584e43f0c0a7e92134811b78bc61 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Fri, 5 May 2023 10:39:39 +0200 Subject: Fix sparse checks processing A lot of errors are encountered when building with sparse checking activated (make C=1 or make C=2). Many of them are fixed in Linux. Resynchronise Makefile and include/linux/build_bug.h with Linux kernel sources by porting the following Linux commits into u-boot: - 6c49f359ca14 ("kbuild: disable sparse warnings about unknown attributes") - 80591e61a0f7 ("kbuild: tell sparse about the $ARCH") - 8788994376d8 ("linux/build_bug.h: change type to int") - 527edbc18a70 ("build_bug.h: remove most of dummy BUILD_BUG_ON stubs for Sparse") - c60d3b79423a ("build_bug.h: remove negative-array fallback for BUILD_BUG_ON()") - 14e83077d55f ("include: drop pointless __compiler_offsetof indirection") Also revert commit aa9e891c63 ("include/linux/stddef.h: avoid 'warning: preprocessor token offsetof redefined'") because the error it creates is worse than the warning it is trying to fix. Signed-off-by: Christophe Leroy --- Makefile | 6 +++++- include/linux/build_bug.h | 40 ++++++++-------------------------------- include/linux/stddef.h | 8 +------- 3 files changed, 14 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index fb02bba08fb..3f5249ceb52 100644 --- a/Makefile +++ b/Makefile @@ -423,7 +423,8 @@ DTC_MIN_VERSION := 010406 CHECK = sparse CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ - -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) + -Wbitwise -Wno-return-void -Wno-unknown-attribute \ + -D__CHECK_ENDIAN__ $(CF) KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ @@ -1032,6 +1033,9 @@ ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),) LDFLAGS_u-boot += -Ttext $(CONFIG_TEXT_BASE) endif +# make the checker run with the right architecture +CHECKFLAGS += --arch=$(ARCH) + # insure the checker run with the right endianness CHECKFLAGS += $(if $(CONFIG_CPU_BIG_ENDIAN),-mbig-endian,-mlittle-endian) diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index 9c7088bafa4..20c2dc7f4bd 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -4,15 +4,16 @@ #include #ifdef __CHECKER__ -#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) -#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) #define BUILD_BUG_ON_ZERO(e) (0) -#define BUILD_BUG_ON_NULL(e) ((void *)0) -#define BUILD_BUG_ON_INVALID(e) (0) -#define BUILD_BUG_ON_MSG(cond, msg) (0) -#define BUILD_BUG_ON(condition) (0) -#define BUILD_BUG() (0) #else /* __CHECKER__ */ +/* + * Force a compilation error if condition is true, but also produce a + * result (of value 0 and type int), so the expression can be used + * e.g. in a structure initializer (or where-ever else comma expressions + * aren't permitted). + */ +#define BUILD_BUG_ON_ZERO(e) ((int)sizeof(struct { int:(-!!(e)); })) +#endif /* __CHECKER__ */ /* Force a compilation error if a constant expression is not a power of 2 */ #define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \ @@ -20,15 +21,6 @@ #define BUILD_BUG_ON_NOT_POWER_OF_2(n) \ BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) -/* - * Force a compilation error if condition is true, but also produce a - * result (of value 0 and type size_t), so the expression can be used - * e.g. in a structure initializer (or where-ever else comma expressions - * aren't permitted). - */ -#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); })) -#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); })) - /* * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the * expression but avoids the generation of any code, even if that expression @@ -52,23 +44,9 @@ * If you have some code which relies on certain constants being equal, or * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to * detect if someone changes it. - * - * The implementation uses gcc's reluctance to create a negative array, but gcc - * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to - * inline functions). Luckily, in 4.3 they added the "error" function - * attribute just for this type of case. Thus, we use a negative sized array - * (should always create an error on gcc versions older than 4.4) and then call - * an undefined function with the error attribute (should always create an - * error on gcc 4.3 and later). If for some reason, neither creates a - * compile-time error, we'll still have a link-time error, which is harder to - * track down. */ -#ifndef __OPTIMIZE__ -#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) -#else #define BUILD_BUG_ON(condition) \ BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) -#endif /** * BUILD_BUG - break compile if used. @@ -98,6 +76,4 @@ #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) -#endif /* __CHECKER__ */ - #endif /* _LINUX_BUILD_BUG_H */ diff --git a/include/linux/stddef.h b/include/linux/stddef.h index a7f546fdfe5..c732eef65ac 100644 --- a/include/linux/stddef.h +++ b/include/linux/stddef.h @@ -14,13 +14,7 @@ #include #endif -#ifndef __CHECKER__ #undef offsetof -#ifdef __compiler_offsetof -#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER) -#else -#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER) -#endif -#endif +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -- cgit v1.3.1 From 41e289bb1f6032694900afad017320d26f411066 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 May 2023 14:07:24 -0400 Subject: arm: Remove ti816x_evm board and ti816x SoC support This platform is currently unmaintained and untested, so remove it. Further, as it is the only TI816X SoC example, remove related files as well. Signed-off-by: Tom Rini --- arch/arm/dts/Makefile | 1 - arch/arm/dts/dm8168-evm-u-boot.dtsi | 12 - arch/arm/dts/dm8168-evm.dts | 171 ------- arch/arm/dts/dm816x-clocks.dtsi | 246 ---------- arch/arm/dts/dm816x.dtsi | 517 --------------------- arch/arm/include/asm/arch-am33xx/clock.h | 4 - arch/arm/include/asm/arch-am33xx/clock_ti81xx.h | 118 ----- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 6 - arch/arm/include/asm/arch-am33xx/emac_defs.h | 37 -- arch/arm/include/asm/arch-am33xx/hardware.h | 2 - arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 62 --- arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 5 - arch/arm/include/asm/arch-am33xx/mux.h | 2 - arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 362 --------------- arch/arm/include/asm/arch-am33xx/omap.h | 4 - arch/arm/include/asm/arch-am33xx/spl.h | 14 +- arch/arm/mach-omap2/Kconfig | 11 - arch/arm/mach-omap2/am33xx/Kconfig | 10 - arch/arm/mach-omap2/am33xx/Makefile | 4 +- arch/arm/mach-omap2/am33xx/clock_ti816x.c | 407 ---------------- arch/arm/mach-omap2/am33xx/ddr.c | 9 - arch/arm/mach-omap2/am33xx/ti816x_emif4.c | 165 ------- arch/arm/mach-omap2/boot-common.c | 20 +- board/ti/ti816x/Kconfig | 15 - board/ti/ti816x/MAINTAINERS | 6 - board/ti/ti816x/Makefile | 10 - board/ti/ti816x/evm.c | 140 ------ configs/ti816x_evm_defconfig | 82 ---- drivers/i2c/Kconfig | 1 - drivers/net/ti/davinci_emac.c | 4 +- include/configs/ti816x_evm.h | 63 --- 31 files changed, 5 insertions(+), 2505 deletions(-) delete mode 100644 arch/arm/dts/dm8168-evm-u-boot.dtsi delete mode 100644 arch/arm/dts/dm8168-evm.dts delete mode 100644 arch/arm/dts/dm816x-clocks.dtsi delete mode 100644 arch/arm/dts/dm816x.dtsi delete mode 100644 arch/arm/include/asm/arch-am33xx/clock_ti81xx.h delete mode 100644 arch/arm/include/asm/arch-am33xx/emac_defs.h delete mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h delete mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h delete mode 100644 arch/arm/mach-omap2/am33xx/clock_ti816x.c delete mode 100644 arch/arm/mach-omap2/am33xx/ti816x_emif4.c delete mode 100644 board/ti/ti816x/Kconfig delete mode 100644 board/ti/ti816x/MAINTAINERS delete mode 100644 board/ti/ti816x/Makefile delete mode 100644 board/ti/ti816x/evm.c delete mode 100644 configs/ti816x_evm_defconfig delete mode 100644 include/configs/ti816x_evm.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 935b2f1517f..35f50f4b156 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -449,7 +449,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am4372-generic.dtb \ am437x-cm-t43.dtb dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb -dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ diff --git a/arch/arm/dts/dm8168-evm-u-boot.dtsi b/arch/arm/dts/dm8168-evm-u-boot.dtsi deleted file mode 100644 index f939df27e47..00000000000 --- a/arch/arm/dts/dm8168-evm-u-boot.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dm8168-evm U-Boot Additions - * - * Copyright (C) 2020 Dario Binacchi - */ - -/ { - ocp { - bootph-all; - }; -}; diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts deleted file mode 100644 index 70255ab2598..00000000000 --- a/arch/arm/dts/dm8168-evm.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm816x.dtsi" -#include - -/ { - model = "DM8168 EVM"; - compatible = "ti,dm8168-evm", "ti,dm8168"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000 /* 1 GB */ - 0xc0000000 0x40000000>; /* 1 GB */ - }; - - /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dm816x_pinmux { - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ - >; - }; - - mmc_pins: pinmux_mmc_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ - DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ - DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ - DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ - DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ - DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ - DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ - >; - }; -}; - -&i2c1 { - extgpio0: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c2 { - extgpio1: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29f2g16aadwp"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - flash@0 { - compatible = "w25x32"; - spi-max-frequency = <48000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -/* At least dm8168-evm rev c won't support multipoint, later may */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - mentor,multipoint = <0>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - mentor,multipoint = <0>; -}; diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi deleted file mode 100644 index f7a839dabf8..00000000000 --- a/arch/arm/dts/dm816x-clocks.dtsi +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&scrm { - main_fapll: main_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x400 0x40>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names = "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; - - ddr_fapll: ddr_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x440 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>; - clock-output-names = "ddr_pll_clk1", - "ddr_pll_clk2", - "ddr_pll_clk3", - "ddr_pll_clk4"; - }; - - video_fapll: video_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x470 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>; - clock-output-names = "video_pll_clk1", - "video_pll_clk2", - "video_pll_clk3"; - }; - - audio_fapll: audio_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x4a0 0x30>; - clocks = <&main_fapll 7>, < &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>; - clock-output-names = "audio_pll_clk1", - "audio_pll_clk2", - "audio_pll_clk3", - "audio_pll_clk4", - "audio_pll_clk5"; - }; -}; - -&scrm_clocks { - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clkin_ck: sys_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; -}; - -/* 0x48180000 */ -&prcm_clocks { - clkout_pre_ck: clkout_pre_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 - &audio_fapll 1>; - reg = <0x100>; - }; - - clkout_div_ck: clkout_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x100>; - }; - - clkout_ck: clkout_ck@100 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout_div_ck>; - ti,bit-shift = <7>; - reg = <0x100>; - }; - - /* CM_DPLL clocks p1795 */ - sysclk1_ck: sysclk1_ck@300 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 1>; - ti,max-div = <7>; - reg = <0x0300>; - }; - - sysclk2_ck: sysclk2_ck@304 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 2>; - ti,max-div = <7>; - reg = <0x0304>; - }; - - sysclk3_ck: sysclk3_ck@308 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 3>; - ti,max-div = <7>; - reg = <0x0308>; - }; - - sysclk4_ck: sysclk4_ck@30c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,max-div = <1>; - reg = <0x030c>; - }; - - sysclk5_ck: sysclk5_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclk4_ck>; - ti,max-div = <1>; - reg = <0x0310>; - }; - - sysclk6_ck: sysclk6_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,dividers = <2>, <4>; - reg = <0x0314>; - }; - - sysclk10_ck: sysclk10_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&ddr_fapll 2>; - ti,max-div = <7>; - reg = <0x0324>; - }; - - sysclk24_ck: sysclk24_ck@3b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 5>; - ti,max-div = <7>; - reg = <0x03b4>; - }; - - mpu_ck: mpu_ck@15dc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sysclk2_ck>; - ti,bit-shift = <1>; - reg = <0x15dc>; - }; - - audio_pll_a_ck: audio_pll_a_ck@35c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&audio_fapll 1>; - ti,max-div = <7>; - reg = <0x035c>; - }; - - sysclk18_ck: sysclk18_ck@378 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; - reg = <0x0378>; - }; - - timer1_fck: timer1_fck@390 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0390>; - }; - - timer2_fck: timer2_fck@394 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0394>; - }; - - timer3_fck: timer3_fck@398 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0398>; - }; - - timer4_fck: timer4_fck@39c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x039c>; - }; - - timer5_fck: timer5_fck@3a0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a0>; - }; - - timer6_fck: timer6_fck@3a4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a4>; - }; - - timer7_fck: timer7_fck@3a8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a8>; - }; -}; diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi deleted file mode 100644 index c4a8653b7f0..00000000000 --- a/arch/arm/dts/dm816x.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -/ { - compatible = "ti,dm816"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = ð0; - ethernet1 = ð1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the dm816x interconnect. - * The real dm816x interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - reg = <0x44000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - prcm: prcm@48180000 { - compatible = "ti,dm816-prcm", "simple-bus"; - reg = <0x48180000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48180000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@48140000 { - compatible = "ti,dm816-scrm", "simple-bus"; - reg = <0x48140000 0x21000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x48140000 0x21000>; - - dm816x_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x50a>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xf>; - }; - - /* Device Configuration Registers */ - scm_conf: syscon@600 { - compatible = "syscon", "simple-bus"; - reg = <0x600 0x110>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x110>; - - usb_phy0: usb-phy@20 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x20 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - - usb_phy1: usb-phy@28 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x28 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - }; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; - interrupts = <12 13 14>; - #dma-cells = <1>; - }; - - elm: elm@48080000 { - compatible = "ti,816-elm"; - ti,hwmods = "elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@48032000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x48032000 0x1000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <100>; - dmas = <&edma 52>; - dma-names = "rxtx"; - gpmc,num-cs = <6>; - gpmc,num-waitpins = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c1: i2c@48028000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <70>; - dmas = <&edma 58 &edma 59>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <71>; - dmas = <&edma 60 &edma 61>; - dma-names = "tx", "rx"; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm816-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - rtc: rtc@480c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x480c0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480c8000 0x2000>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <0 0 0>; - }; - }; - - spinbox: spinbox@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x2000>; - ti,hwmods = "spinbox"; - #hwlock-cells = <1>; - }; - - mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4a100800 0x100>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - phy1: ethernet-phy@1 { - reg = <2>; - }; - }; - - eth0: ethernet@4a100000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac0"; - reg = <0x4a100000 0x800 - 0x4a100900 0x3700>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <40 41 42 43>; - phy-handle = <&phy0>; - }; - - eth1: ethernet@4a120000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac1"; - reg = <0x4a120000 0x4000>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <44 45 46 47>; - phy-handle = <&phy1>; - }; - - mcspi1: spi@48030000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48030000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 &edma 17 - &edma 18 &edma 19 - &edma 20 &edma 21 - &edma 22 &edma 23>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x11000>; - ti,hwmods = "mmc1"; - interrupts = <64>; - dmas = <&edma 24 &edma 25>; - dma-names = "tx", "rx"; - }; - - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48042000 { - compatible = "ti,dm816-timer"; - reg = <0x48042000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,dm816-timer"; - reg = <0x48044000 0x2000>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,dm816-timer"; - reg = <0x48046000 0x2000>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,dm816-timer"; - reg = <0x48048000 0x2000>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,dm816-timer"; - reg = <0x4804a000 0x2000>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - uart1: serial@48020000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x48020000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 &edma 27>; - dma-names = "tx", "rx"; - }; - - uart2: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x48022000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 &edma 29>; - dma-names = "tx", "rx"; - }; - - uart3: serial@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x48024000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 &edma 31>; - dma-names = "tx", "rx"; - }; - - /* NOTE: USB needs a transceiver driver for phys to work */ - usb: usb_otg_hs@47401000 { - compatible = "ti,am33xx-usb"; - reg = <0x47401000 0x400000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0: usb@47401000 { - compatible = "ti,musb-dm816"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-dm816"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; - }; - - wd_timer2: wd_timer@480c2000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x480c2000 0x1000>; - interrupts = <0>; - }; - }; -}; - -#include "dm816x-clocks.dtsi" diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index ad25b3e8aa0..67400c2c63a 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,10 +13,6 @@ #include #include -#if defined(CONFIG_TI816X) -#include -#endif - #define LDELAY 1000000 /*CM___CLKCTRL */ diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h deleted file mode 100644 index d22d9587063..00000000000 --- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * ti81xx.h - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - */ - -#ifndef _CLOCK_TI81XX_H_ -#define _CLOCK_TI81XX_H_ - -#define PRCM_MOD_EN 0x2 - -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI816X) - unsigned int ocmc1clkstctrl; -#endif - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; -#if defined(CONFIG_TI816X) - unsigned int resv1[1]; - unsigned int timer1clkctrl; - unsigned int timer2clkctrl; - unsigned int timer3clkctrl; - unsigned int timer4clkctrl; - unsigned int timer5clkctrl; - unsigned int timer6clkctrl; - unsigned int timer7clkctrl; -#endif - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI816X) - unsigned int resv3[1]; - unsigned int sdioclkctrl; -#endif - unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI816X) - unsigned int ocmc1clkctrl; -#endif - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; -#if defined(CONFIG_TI816X) - unsigned int resv6[1]; -#endif - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; -#if defined(CONFIG_TI816X) - unsigned int sr0clkctrl; - unsigned int sr1clkctrl; -#endif -}; - -#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 15a5b641ffa..1a031071073 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -369,15 +369,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -#ifdef CONFIG_TI816X -void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, - const struct dmm_lisa_map_regs *lisa_regs, int nrs); -#else void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); -#endif void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h deleted file mode 100644 index eb6516da93c..00000000000 --- a/arch/arm/include/asm/arch-am33xx/emac_defs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Texas Instruments - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - */ - -#ifndef _EMAC_DEFS_H_ -#define _EMAC_DEFS_H_ - -#ifdef CONFIG_TI816X -#define EMAC_BASE_ADDR (0x4A100000) -#define EMAC_WRAPPER_BASE_ADDR (0x4A100900) -#define EMAC_WRAPPER_RAM_ADDR (0x4A102000) -#define EMAC_MDIO_BASE_ADDR (0x4A100800) -#define EMAC_MDIO_BUS_FREQ (250000000UL) -#define EMAC_MDIO_CLOCK_FREQ (2000000UL) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif - -#endif /* _EMAC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 2d7f9da3652..387f053ce68 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -14,8 +14,6 @@ #include #ifdef CONFIG_AM33XX #include -#elif defined(CONFIG_TI816X) -#include #elif defined(CONFIG_AM43XX) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h deleted file mode 100644 index 78b79486ed4..00000000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * hardware_ti816x.h - * - * TI816x hardware specific header - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - * Based on TI-PSP-04.00.02.14 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AM33XX_HARDWARE_TI816X_H -#define __AM33XX_HARDWARE_TI816X_H - -/* UART */ -#define UART0_BASE 0x48020000 -#define UART1_BASE 0x48022000 -#define UART2_BASE 0x48024000 - -/* Watchdog Timer */ -#define WDT_BASE 0x480C2000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48198358 -#define VTP1_CTRL_ADDR 0x4819A358 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x48198000 -#define DDR_PHY_DATA_ADDR 0x481980C8 -#define DDR_PHY_CMD_ADDR2 0x4819A000 -#define DDR_PHY_DATA_ADDR2 0x4819A0C8 -#define DDR_DATA_REGS_NR 4 - - -#define DDRPHY_0_CONFIG_BASE 0x48198000 -#define DDRPHY_1_CONFIG_BASE 0x4819A000 -#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ - DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index ed15d15c5b3..b1b189631af 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -24,9 +24,4 @@ #define OMAP_HSMMC1_BASE 0x48060000 #define OMAP_HSMMC2_BASE 0x481D8000 -#if defined(CONFIG_TI816X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 48 /* MHz */ -#endif - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 7cf973710d1..ebb2d303dfe 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -20,8 +20,6 @@ #ifdef CONFIG_AM33XX #include -#elif defined(CONFIG_TI816X) -#include #elif defined(CONFIG_AM43XX) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h deleted file mode 100644 index a6a8a988a0c..00000000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * mux_ti816x.h - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI816X_H_ -#define _MUX_TI816X_H_ - -#include - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) (val) /* used for Readability */ - - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; - int pincntl271; - int pincntl272; - int pincntl273; - int pincntl274; - int pincntl275; - int pincntl276; - int pincntl277; - int pincntl278; - int pincntl279; - int pincntl280; - int pincntl281; - int pincntl282; - int pincntl283; - int pincntl284; - int pincntl285; - int pincntl286; - int pincntl287; - int pincntl288; - int pincntl289; - int pincntl290; - int pincntl291; - int pincntl292; - int pincntl293; - int pincntl294; - int pincntl295; - int pincntl296; - int pincntl297; - int pincntl298; - int pincntl299; - int pincntl300; - int pincntl301; - int pincntl302; - int pincntl303; - int pincntl304; - int pincntl305; - int pincntl306; - int pincntl307; - int pincntl308; - int pincntl309; - int pincntl310; - int pincntl311; - int pincntl312; - int pincntl313; - int pincntl314; - int pincntl315; - int pincntl316; - int pincntl317; - int pincntl318; - int pincntl319; - int pincntl320; - int pincntl321; - int pincntl322; - int pincntl323; -}; - -#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 4c71dbf3ab6..53046deed56 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -20,10 +20,6 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI816X) -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 -#define NON_SECURE_SRAM_IMG_END 0x4031B800 #elif defined(CONFIG_AM43XX) #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 6bd3ca0d076..9ddb346dc96 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,19 +9,7 @@ #define BOOT_DEVICE_NONE 0x00 #define BOOT_DEVICE_MMC2_2 0xFF -#if defined(CONFIG_TI816X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAND 0x04 -#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x06 -#define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_USB 0x45 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_AM33XX) +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_XIP 0x01 #define BOOT_DEVICE_XIPWAIT 0x02 #define BOOT_DEVICE_NAND 0x05 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 309b967b0dd..8465b5426d8 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -77,16 +77,6 @@ config OMAP54XX imply SPL_SERIAL imply SYS_I2C_OMAP24XX -config TI816X - bool "TI816X SoC" - select SPECIFY_CONSOLE_INDEX - imply NAND_OMAP_ELM - imply NAND_OMAP_GPMC - help - Support for AM335x SOC from Texas Instruments. - The AM335x high performance SOC features a Cortex-A8 - ARM core and more. - config AM43XX bool "AM43XX SoC" select SPECIFY_CONSOLE_INDEX @@ -203,7 +193,6 @@ source "board/BuR/brppt1/Kconfig" source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" -source "board/ti/ti816x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" source "board/compulab/cm_t43/Kconfig" diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 1299aec055e..8cb0c57163b 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -1,13 +1,3 @@ -if TI816X - -config TARGET_TI816X_EVM - bool "Support ti816x_evm" - help - This option specifies support for the TI8168 EVM development platform - with PG2.0 silicon and DDR3 DRAM. - -endif - if AM33XX config AM33XX_CHILISOM diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index bf94d345dae..2aa8013527e 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -9,13 +9,11 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) obj-y += clock.o endif -obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif -obj-$(CONFIG_TI816X) += ti816x_emif4.o obj-y += board.o obj-y += mux.o obj-y += prcm-regs.o diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c deleted file mode 100644 index ec4cc753812..00000000000 --- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * clock_ti816x.c - * - * Clocks for TI816X based boards - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - * - * Based on TI-PSP-04.00.02.14 : - * - * Copyright (C) 2009, Texas Instruments, Incorporated - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#define CM_PLL_BASE (CTRL_BASE + 0x0400) - -/* Main PLL */ -#define MAIN_N 64 -#define MAIN_P 0x1 -#define MAIN_INTFREQ1 0x8 -#define MAIN_FRACFREQ1 0x800000 -#define MAIN_MDIV1 0x2 -#define MAIN_INTFREQ2 0xE -#define MAIN_FRACFREQ2 0x0 -#define MAIN_MDIV2 0x1 -#define MAIN_INTFREQ3 0x8 -#define MAIN_FRACFREQ3 0xAAAAB0 -#define MAIN_MDIV3 0x3 -#define MAIN_INTFREQ4 0x9 -#define MAIN_FRACFREQ4 0x55554F -#define MAIN_MDIV4 0x3 -#define MAIN_INTFREQ5 0x9 -#define MAIN_FRACFREQ5 0x374BC6 -#define MAIN_MDIV5 0xC -#define MAIN_MDIV6 0x48 -#define MAIN_MDIV7 0x4 - -/* DDR PLL */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x2 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 - -#define CONTROL_STATUS (CTRL_BASE + 0x40) -#define DDR_RCD (CTRL_BASE + 0x070C) -#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) -#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) - -#define INTCPS_SYSCONFIG 0x48200010 -#define CM_SYSCLK10_CLKSEL 0x48180324 - -struct cm_pll { - unsigned int mainpll_ctrl; /* offset 0x400 */ - unsigned int mainpll_pwd; - unsigned int mainpll_freq1; - unsigned int mainpll_div1; - unsigned int mainpll_freq2; - unsigned int mainpll_div2; - unsigned int mainpll_freq3; - unsigned int mainpll_div3; - unsigned int mainpll_freq4; - unsigned int mainpll_div4; - unsigned int mainpll_freq5; - unsigned int mainpll_div5; - unsigned int resv0[1]; - unsigned int mainpll_div6; - unsigned int resv1[1]; - unsigned int mainpll_div7; - unsigned int ddrpll_ctrl; /* offset 0x440 */ - unsigned int ddrpll_pwd; - unsigned int resv2[1]; - unsigned int ddrpll_div1; - unsigned int ddrpll_freq2; - unsigned int ddrpll_div2; - unsigned int ddrpll_freq3; - unsigned int ddrpll_div3; - unsigned int ddrpll_freq4; - unsigned int ddrpll_div4; - unsigned int ddrpll_freq5; - unsigned int ddrpll_div5; - unsigned int videopll_ctrl; /* offset 0x470 */ - unsigned int videopll_pwd; - unsigned int videopll_freq1; - unsigned int videopll_div1; - unsigned int videopll_freq2; - unsigned int videopll_div2; - unsigned int videopll_freq3; - unsigned int videopll_div3; - unsigned int resv3[4]; - unsigned int audiopll_ctrl; /* offset 0x4A0 */ - unsigned int audiopll_pwd; - unsigned int resv4[2]; - unsigned int audiopll_freq2; - unsigned int audiopll_div2; - unsigned int audiopll_freq3; - unsigned int audiopll_div3; - unsigned int audiopll_freq4; - unsigned int audiopll_div4; - unsigned int audiopll_freq5; - unsigned int audiopll_div5; -}; - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; -const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - /* Wait for dmm to be fully functional, including OCP */ - while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) - ; -} - -void enable_emif_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->fwclkctrl); - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - - /* Wait for clocks to be active */ - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - /* Wait for emif0 to be fully functional, including OCP */ - while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) - ; - /* Wait for emif1 to be fully functional, including OCP */ - while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) - ; -} - -/* assume delay is aprox at least 1us */ -static void ddr_delay(int d) -{ - int i; - - /* - * read a control register. - * this is a bit more delay and cannot be optimized by the compiler - * assuming one read takes 200 cycles and A8 is runing 1 GHz - * somewhat conservative setting - */ - for (i = 0; i < 50*d; i++) - readl(CONTROL_STATUS); -} - -static void main_pll_init_ti816x(void) -{ - u32 main_pll_ctrl = 0; - - /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFFB; - main_pll_ctrl |= BIT(2); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Enable PLL by setting BIT3 in its ctrl reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFF7; - main_pll_ctrl |= BIT(3); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Write the values of N,P in the CTRL reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFF; - main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Power up clock1-7 */ - writel(0x0, &cmpll->mainpll_pwd); - - /* Program the freq and divider values for clock1-7 */ - writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), - &cmpll->mainpll_freq1); - writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), - &cmpll->mainpll_freq2); - writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), - &cmpll->mainpll_freq3); - writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), - &cmpll->mainpll_freq4); - writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), - &cmpll->mainpll_freq5); - writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); - - writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); - - writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); - - /* Wait for PLL to lock */ - while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) - ; - - /* Put the PLL in normal mode, disable bypass */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFFB; - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); -} - -static void ddr_pll_bypass_ti816x(void) -{ - u32 ddr_pll_ctrl = 0; - - /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFFFFFFFB; - ddr_pll_ctrl |= BIT(2); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); -} - -static void ddr_pll_init_ti816x(void) -{ - u32 ddr_pll_ctrl = 0; - /* Enable PLL by setting BIT3 in its ctrl reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFFFFFFF7; - ddr_pll_ctrl |= BIT(3); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); - - /* Write the values of N,P in the CTRL reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFF; - ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); - - ddr_delay(10); - - /* Power up clock1-5 */ - writel(0x0, &cmpll->ddrpll_pwd); - - /* Program the freq and divider values for clock1-3 */ - writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); - ddr_delay(1); - writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); - writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), - &cmpll->ddrpll_freq2); - writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); - writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); - ddr_delay(1); - writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); - ddr_delay(1); - writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), - &cmpll->ddrpll_freq3); - ddr_delay(1); - writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), - &cmpll->ddrpll_freq3); - - ddr_delay(5); - - /* Wait for PLL to lock */ - while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) - ; - - /* Power up RCD */ - writel(BIT(0), DDR_RCD); -} - -static void peripheral_enable(void) -{ - /* Wake-up the l3_slow clock */ - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - - /* - * Note on Timers: - * There are 8 timers(0-7) out of which timer 0 is a secure timer. - * Timer 0 mux should not be changed - * - * To access the timer registers we need the to be - * enabled which is what we do in the first step - */ - - /* Enable timer1 */ - writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); - /* Select timer1 clock to be CLKIN (27MHz) */ - writel(BIT(1), CM_TIMER1_CLKSEL); - - /* Wait for timer1 to be ON-ACTIVE */ - while (((readl(&cmalwon->l3slowclkstctrl) - & (0x80000<<1))>>20) != 1) - ; - /* Wait for timer1 to be enabled */ - while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) - ; - /* Active posted mode */ - writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); - while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) - ; - /* Start timer1 */ - writel(BIT(0), (DM_TIMER1_BASE + 0x38)); - - /* eFuse */ - writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); - while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) - ; - - /* Enable gpio0 */ - writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); - while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) - ; - writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl); - - /* Enable gpio1 */ - writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl); - while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN) - ; - writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl); - - /* Enable spi */ - writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); - while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) - ; - - /* Enable i2c0 */ - writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); - while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) - ; - - /* Enable ethernet0 */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - - /* Enable hsmmc */ - writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); - while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) - ; -} - -void setup_clocks_for_console(void) -{ - /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ - writel(0x0, CM_SYSCLK10_CLKSEL); - - ddr_pll_bypass_ti816x(); - - /* Enable uart0-2 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); - while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); - while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) - ; - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -void prcm_init(void) -{ - /* Enable the control */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - main_pll_init_ti816x(); - ddr_pll_init_ti816x(); - - /* - * With clk freqs setup to desired values, - * enable the required peripherals - */ - peripheral_enable(); -} diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index f8434ecf575..5f970d93f0a 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -182,14 +182,6 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) */ void config_sdram(const struct emif_regs *regs, int nr) { -#ifdef CONFIG_TI816X - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); - writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */ - writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */ - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); -#else if (regs->zq_config) { writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); @@ -211,7 +203,6 @@ void config_sdram(const struct emif_regs *regs, int nr) /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */ if (regs->ocp_config) writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); -#endif } /** diff --git a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c deleted file mode 100644 index 707ea807ac2..00000000000 --- a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * ti816x_emif4.c - * - * TI816x emif4 configuration file - * - * Copyright (C) 2017, Konsulko Group - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/********************************************************************* - * Init DDR3 on TI816X EVM - *********************************************************************/ -static void ddr_init_settings(const struct cmd_control *ctrl, int emif) -{ - /* - * setup use_rank_delays to 1. This is only necessary when - * multiple ranks are in use. Though the EVM does not have - * multiple ranks, this is a good value to set. - */ - writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS - writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS - writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS - writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS - - config_cmd_ctrl(ctrl, emif); - - /* for ddr3 this needs to be set to 1 */ - writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ - writel(0x1, DDRPHY_CONFIG_BASE + 0x104); - writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); - writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); - writel(0x1, DDRPHY_CONFIG_BASE + 0x240); - writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); - writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4); - writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0); - - /* - * This represents the initial value for the leveling process. The - * value is a ratio - so 0x100 represents one cycle. The real delay - * is determined through the leveling process. - * - * During the leveling process, 0x20 is subtracted from the value, so - * we have added that to the value we want to set. We also set the - * values such that byte3 completes leveling after byte2 and byte1 - * after byte0. - */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */ - - - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x100); - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4); - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x248); - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC); - - writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */ -} - -static void ddr3_sw_levelling(const struct ddr_data *data, int emif) -{ - /* Set the correct value to DDR_VTP_CTRL_0 */ - writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); - - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108)); - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC)); - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250)); - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4)); - - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC)); - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180)); - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224)); - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8)); - - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120)); - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4)); - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268)); - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C)); - - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8)); - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C)); - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210)); - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4)); -} - -static struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; - -#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) -void config_dmm(const struct dmm_lisa_map_regs *regs) -{ - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); - - /* Enable Tiled Access */ - writel(0x80000000, DMM_PAT_BASE_ADDR); -} - -void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, - const struct dmm_lisa_map_regs *lisa_regs, int nrs) -{ - int i; - - enable_emif_clocks(); - - for (i = 0; i < nrs; i++) - ddr_init_settings(ctrl, i); - - enable_dmm_clocks(); - - /* Program the DMM to for non-interleaved configuration */ - config_dmm(lisa_regs); - - /* Program EMIF CFG Registers */ - for (i = 0; i < nrs; i++) { - set_sdram_timings(regs, i); - config_sdram(regs, i); - } - - udelay(1000); - for (i = 0; i < nrs; i++) - ddr3_sw_levelling(data, i); - - udelay(50000); /* Some delay needed */ -} diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 9a342a1bf95..a2dd5f6df01 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -74,23 +74,6 @@ void save_omap_boot_params(void) */ if (boot_device == BOOT_DEVICE_QSPI_4) boot_device = BOOT_DEVICE_SPI; -#endif -#ifdef CONFIG_TI816X - /* - * On PG2.0 and later TI816x the values we get when booting are not the - * same as on PG1.0, which is what the defines are based on. Update - * them as needed. - */ - if (get_cpu_rev() != 1) { - if (boot_device == 0x05) { - omap_boot_params->boot_device = BOOT_DEVICE_NAND; - boot_device = BOOT_DEVICE_NAND; - } - if (boot_device == 0x08) { - omap_boot_params->boot_device = BOOT_DEVICE_MMC1; - boot_device = BOOT_DEVICE_MMC1; - } - } #endif /* * When booting from peripheral booting, the boot device is not usable @@ -183,8 +166,7 @@ void save_omap_boot_params(void) gd->arch.omap_boot_mode = boot_mode; -#if !defined(CONFIG_TI816X) && \ - !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) +#if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) /* CH flags */ diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig deleted file mode 100644 index 95973b47f1e..00000000000 --- a/board/ti/ti816x/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TI816X_EVM - -config SYS_BOARD - default "ti816x" - -config SYS_VENDOR - default "ti" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "ti816x_evm" - -endif diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS deleted file mode 100644 index fd9a98fc762..00000000000 --- a/board/ti/ti816x/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TI816X BOARD -M: Tom Rini -S: Maintained -F: board/ti/ti816x/ -F: include/configs/ti816x_evm.h -F: configs/ti816x_evm_defconfig diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile deleted file mode 100644 index f12712aea64..00000000000 --- a/board/ti/ti816x/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2013, Adeneo Embedded -# Antoine Tenart, -# -# Based on TI-PSP-04.00.02.14 : -# -# Copyright (C) 2009, Texas Instruments, Incorporated - -obj-y := evm.o diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c deleted file mode 100644 index 8c708355d4c..00000000000 --- a/board/ti/ti816x/evm.c +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * evm.c - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; -#if defined(CONFIG_MTD_RAW_NAND) - gpmc_init(); -#endif - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - printf(" not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - else - printf("Unable to read MAC address. Set \n"); - } - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -static struct module_pin_mux mmc_pin_mux[] = { - { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, - { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { -1 }, -}; - -void set_uart_mux_conf(void) {} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(mmc_pin_mux); -} - -/* - * EMIF Paramters. Refer the EMIF register documentation and the - * memory datasheet for details. This is for 796 MHz. - */ -#define EMIF_TIM1 0x1779C9FE -#define EMIF_TIM2 0x50608074 -#define EMIF_TIM3 0x009F857F -#define EMIF_SDREF 0x10001841 -#define EMIF_SDCFG 0x62A73832 -#define EMIF_PHYCFG 0x00000110 -static const struct emif_regs ddr3_emif_regs = { - .sdram_config = EMIF_SDCFG, - .ref_ctrl = EMIF_SDREF, - .sdram_tim1 = EMIF_TIM1, - .sdram_tim2 = EMIF_TIM2, - .sdram_tim3 = EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, -}; - -static const struct cmd_control ddr3_ctrl = { - .cmd0csratio = 0x100, - .cmd0iclkout = 0x001, - .cmd1csratio = 0x100, - .cmd1iclkout = 0x001, - .cmd2csratio = 0x100, - .cmd2iclkout = 0x001, -}; - -/* These values are obtained from the CCS app */ -#define RD_DQS_GATE (0x1B3) -#define RD_DQS (0x35) -#define WR_DQS (0x93) -static struct ddr_data ddr3_data = { - .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), - .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), - .datawiratio0 = ((0x20<<10) | 0x20<<0), - .datagiratio0 = ((0x20<<10) | 0x20<<0), - .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), - .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), -}; - -static const struct dmm_lisa_map_regs evm_lisa_map_regs = { - .dmm_lisa_map_0 = 0x00000000, - .dmm_lisa_map_1 = 0x00000000, - .dmm_lisa_map_2 = 0x80640300, - .dmm_lisa_map_3 = 0xC0640320, -}; - -void sdram_init(void) -{ - /* - * Pass in our DDR3 config information and that we have 2 EMIFs to - * configure. - */ - config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs, - &evm_lisa_map_regs, 2); -} -#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig deleted file mode 100644 index a4bc9932979..00000000000 --- a/configs/ti816x_evm_defconfig +++ /dev/null @@ -1,82 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x1C0000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm" -CONFIG_SPL_TEXT_BASE=0x40400000 -CONFIG_TI816X=y -CONFIG_TARGET_TI816X_EVM=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x1E0000 -CONFIG_SYS_CLK_FREQ=27000000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk" -CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}" -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_MISC_INIT_R is not set -CONFIG_SPL_MAX_SIZE=0xfff1b400 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_BASE=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_DNS2=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -# CONFIG_USE_PRIVATE_LIBGCC is not set diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 05b14d2451c..5e81698143a 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -744,7 +744,6 @@ config SYS_I2C_SPEED config SYS_I2C_BUS_MAX int "Max I2C busses" depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA - default 2 if TI816X default 3 if OMAP34XX || AM33XX || AM43XX default 4 if ARCH_SOCFPGA || OMAP44XX default 5 if OMAP54XX diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 29d2fc9b54e..034877a7690 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -833,9 +833,9 @@ static int davinci_emac_probe(struct udevice *dev) #endif } -#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ - !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)) + !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) for (i = 0; i < num_phy; i++) { if (phy[i].is_phy_connected(i)) phy[i].auto_negotiate(i); diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h deleted file mode 100644 index ac6d46f917b..00000000000 --- a/include/configs/ti816x_evm.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti816x_evm.h - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - */ - -#ifndef __CONFIG_TI816X_EVM_H -#define __CONFIG_TI816X_EVM_H - -#include -#include - -#define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/** - * Platform/Board specific defs - */ -#define CFG_SYS_TIMERBASE 0x4802E000 - -/* - * NS16550 Configuration - */ -#define CFG_SYS_NS16550_CLK (48000000) -#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ - -/* allow overwriting serial config and ethaddr */ - - -/* - * GPMC NAND block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#define CFG_SYS_NAND_BASE 0x8000000 - -/* NAND: SPL related configs */ - -/* NAND: device related configs */ -/* NAND: driver related configs */ -#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CFG_SYS_NAND_ECCSIZE 512 -#define CFG_SYS_NAND_ECCBYTES 14 - -/* SPL */ -/* Defines for SPL */ - -#endif -- cgit v1.3.1 From 4ee992f7cf907d269d20a26d90513ef67b371dd5 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 May 2023 14:52:10 +0100 Subject: imx: fix header inclusion guards It seems like the header inclusion guards for some IMX related headers were misspelled or got out of sync. Make the preprocessor symbols for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-imx8m/sys_proto.h | 2 +- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 +- arch/arm/include/asm/arch-imx9/sys_proto.h | 2 +- include/imx_sip.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h index 55b46afaf78..4ed8e954e31 100644 --- a/arch/arm/include/asm/arch-imx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -4,7 +4,7 @@ */ #ifndef __ARCH_IMX8M_SYS_PROTO_H -#define __ARCH_NMX8M_SYS_PROTO_H +#define __ARCH_IMX8M_SYS_PROTO_H #include #include diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 5bbae21e37c..95bf753a766 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -4,7 +4,7 @@ */ #ifndef __ARCH_IMX8ULP_SYS_PROTO_H -#define __ARCH_NMX8ULP_SYS_PROTO_H +#define __ARCH_IMX8ULP_SYS_PROTO_H #include diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index ba97f92f5ae..2f7a1292758 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -4,7 +4,7 @@ */ #ifndef __ARCH_IMX9_SYS_PROTO_H -#define __ARCH_NMX9_SYS_PROTO_H +#define __ARCH_IMX9_SYS_PROTO_H #include diff --git a/include/imx_sip.h b/include/imx_sip.h index 1b873f231be..ebbb3a16d7e 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -4,7 +4,7 @@ */ #ifndef _IMX_SIP_H__ -#define _IMX_SIP_H_ +#define _IMX_SIP_H__ #define IMX_SIP_GPC 0xC2000000 #define IMX_SIP_GPC_PM_DOMAIN 0x03 -- cgit v1.3.1 From a179217e68e5c0c91004b1084e04091a80a6bb7e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 May 2023 14:52:14 +0100 Subject: faraday: remove orphaned header file Commit 11232139e399 ("nds32: Remove the architecture") removed the nds32 architecture, and with it the last user of the Faraday AHB controller header file. Consequently remove that header file as well. This was found because the inclusion guard was misspelled. Signed-off-by: Andre Przywara Reviewed-by: Tom Rini --- include/faraday/ftahbc020s.h | 46 -------------------------------------------- 1 file changed, 46 deletions(-) delete mode 100644 include/faraday/ftahbc020s.h (limited to 'include') diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h deleted file mode 100644 index e628156c151..00000000000 --- a/include/faraday/ftahbc020s.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation - */ - -/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ -#ifndef __FTAHBC020S_H -#define __FTAHBC202S_H - -/* Registers Offsets */ - -/* - * AHB Slave BSR, offset: n * 4, n=0~31 - */ -#ifndef __ASSEMBLY__ -struct ftahbc02s { - unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ - unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ - unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ - unsigned int cr; /* 0x88 - Ctrl Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register - */ -#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) -#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) -/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ -#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ - -/* - * FTAHBC020S_PCR - Priority Control Register - */ -#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ - -/* - * FTAHBC020S_CR - Interrupt Control Register - */ -#define FTAHBC020S_CR_INTSTS (1 << 24) -#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) -#define FTAHBC020S_CR_INTSMASK (1 << 16) -#define FTAHBC020S_CR_REMAP (1 << 0) - -#endif /* __FTAHBC020S_H */ -- cgit v1.3.1 From f1671205fa44084b334027a267c86e5be2ea7c1a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 May 2023 12:34:47 -0400 Subject: include: Remove unused header files As part of various code clean-ups we have on occasion missed removing unused header files. None of these files are referenced anywhere else at this point. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-bcmcygnus/configs.h | 18 - arch/arm/include/asm/arch-bcmnsp/configs.h | 17 - arch/arm/include/asm/arch-imxrt/imxrt.h | 10 - arch/arm/include/asm/arch-lpc32xx/gpio_grp.h | 39 - arch/arm/include/asm/arch-mx27/mxcmmc.h | 11 - arch/arm/include/asm/arch-mx6/opos6ul.h | 11 - arch/arm/include/asm/arch-mxs/regs-uartapp.h | 219 --- arch/arm/include/asm/arch-omap3/omap3-regs.h | 78 -- arch/arm/include/asm/arch-omap5/mux_omap5.h | 317 ----- arch/arm/include/asm/iproc-common/configs.h | 14 - arch/arm/include/asm/iproc-common/iproc_sdhci.h | 12 - arch/arm/include/asm/kona-common/kona_sdhci.h | 11 - arch/arm/mach-at91/include/mach/at91_rtt.h | 32 - arch/arm/mach-davinci/include/mach/aintc_defs.h | 35 - .../arm/mach-keystone/include/mach/xhci-keystone.h | 24 - arch/powerpc/include/asm/mc146818rtc.h | 27 - arch/powerpc/include/asm/pci_io.h | 43 - arch/riscv/include/asm/arch-fu740/eeprom.h | 15 - arch/sh/include/asm/mmc.h | 14 - include/.gitignore | 4 - include/ali512x.h | 37 - include/andestech/andes_pcu.h | 354 ----- include/asm-generic/types.h | 9 - include/dp83848.h | 84 -- include/ds1722.h | 14 - include/exynos_lcd.h | 81 -- include/faraday/ftpci100.h | 84 -- include/faraday/ftsdmc020.h | 90 -- include/faraday/ftsdmc021.h | 139 -- include/lcd_console.h | 102 -- include/lcdvideo.h | 69 - include/linux/mc146818rtc.h | 86 -- include/linux/mtd/doc2000.h | 207 --- include/linux/mtd/ndfc.h | 67 - include/linux_logo.h | 1445 -------------------- include/lxt971a.h | 131 -- include/mc13783.h | 63 - include/mc34704.h | 45 - include/mc9sdz60.h | 66 - include/mii_phy.h | 8 - include/mk48t59.h | 47 - include/mpc106.h | 140 -- include/mpc86xx.h | 90 -- include/mvmfp.h | 99 -- include/pca9564.h | 35 - include/sja1000.h | 43 - include/sym53c8xx.h | 552 -------- include/synopsys/dwcddr21mctl.h | 324 ----- include/video_easylogo.h | 26 - 49 files changed, 5488 deletions(-) delete mode 100644 arch/arm/include/asm/arch-bcmcygnus/configs.h delete mode 100644 arch/arm/include/asm/arch-bcmnsp/configs.h delete mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h delete mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio_grp.h delete mode 100644 arch/arm/include/asm/arch-mx27/mxcmmc.h delete mode 100644 arch/arm/include/asm/arch-mx6/opos6ul.h delete mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h delete mode 100644 arch/arm/include/asm/arch-omap3/omap3-regs.h delete mode 100644 arch/arm/include/asm/arch-omap5/mux_omap5.h delete mode 100644 arch/arm/include/asm/iproc-common/configs.h delete mode 100644 arch/arm/include/asm/iproc-common/iproc_sdhci.h delete mode 100644 arch/arm/include/asm/kona-common/kona_sdhci.h delete mode 100644 arch/arm/mach-at91/include/mach/at91_rtt.h delete mode 100644 arch/arm/mach-davinci/include/mach/aintc_defs.h delete mode 100644 arch/arm/mach-keystone/include/mach/xhci-keystone.h delete mode 100644 arch/powerpc/include/asm/mc146818rtc.h delete mode 100644 arch/powerpc/include/asm/pci_io.h delete mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h delete mode 100644 arch/sh/include/asm/mmc.h delete mode 100644 include/.gitignore delete mode 100644 include/ali512x.h delete mode 100644 include/andestech/andes_pcu.h delete mode 100644 include/asm-generic/types.h delete mode 100644 include/dp83848.h delete mode 100644 include/ds1722.h delete mode 100644 include/exynos_lcd.h delete mode 100644 include/faraday/ftpci100.h delete mode 100644 include/faraday/ftsdmc020.h delete mode 100644 include/faraday/ftsdmc021.h delete mode 100644 include/lcd_console.h delete mode 100644 include/lcdvideo.h delete mode 100644 include/linux/mc146818rtc.h delete mode 100644 include/linux/mtd/doc2000.h delete mode 100644 include/linux/mtd/ndfc.h delete mode 100644 include/linux_logo.h delete mode 100644 include/lxt971a.h delete mode 100644 include/mc13783.h delete mode 100644 include/mc34704.h delete mode 100644 include/mc9sdz60.h delete mode 100644 include/mii_phy.h delete mode 100644 include/mk48t59.h delete mode 100644 include/mpc106.h delete mode 100644 include/mpc86xx.h delete mode 100644 include/mvmfp.h delete mode 100644 include/pca9564.h delete mode 100644 include/sja1000.h delete mode 100644 include/sym53c8xx.h delete mode 100644 include/synopsys/dwcddr21mctl.h delete mode 100644 include/video_easylogo.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h deleted file mode 100644 index fd8dad394ad..00000000000 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2017 Broadcom. - */ - -#ifndef __ARCH_CONFIGS_H -#define __ARCH_CONFIGS_H - -#include - -/* uArchitecture specifics */ - -/* Serial Info */ -#define CFG_SYS_NS16550_CLK 100000000 -#define CFG_SYS_NS16550_CLK_DIV 54 -#define CFG_SYS_NS16550_COM3 0x18023000 - -#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h deleted file mode 100644 index 0d4baf3c007..00000000000 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __ARCH_CONFIGS_H -#define __ARCH_CONFIGS_H - -#include - -/* uArchitecture specifics */ - -/* Serial Info */ -#define CFG_SYS_NS16550_CLK 0x03b9aca0 -#define CFG_SYS_NS16550_COM1 0x18000300 - -#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h deleted file mode 100644 index 14f7c769b0c..00000000000 --- a/arch/arm/include/asm/arch-imxrt/imxrt.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -#ifndef _ASM_ARCH_IMXRT_H -#define _ASM_ARCH_IMXRT_H - -#endif /* _ASM_ARCH_IMXRT_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h deleted file mode 100644 index 762bbeee0a6..00000000000 --- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LPC32xx GPIO interface macro for pin mapping. - * - * (C) Copyright 2015 DENX Software Engineering GmbH - * Written-by: Sylvain Lemieux - */ - -#ifndef _LPC32XX_GPIO_GRP_H -#define _LPC32XX_GPIO_GRP_H - -/* - * Macro to map the pin for the lpc32xx_gpio driver. - * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159; - * mapping is done per register, as group of 32. - * (see drivers/gpio/lpc32xx_gpio.c for details). - * - macros can be use with the following pins: - * P0.0 - P0.7 - * P1.0 - P1.23 - * P2.0 - P2.12 - * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28 - * P3 GPO_0 - GPO_23 - * P3 GPIO_0 - GPIO_5 (output register only) - */ -#define LPC32XX_GPIO_P0_GRP 0 -#define LPC32XX_GPIO_P1_GRP 32 -#define LPC32XX_GPIO_P2_GRP 64 -#define LPC32XX_GPO_P3_GRP 96 -#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25) -#define LPC32XX_GPI_P3_GRP 128 - -/* - * A specific GPIO can be selected with this macro - * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1) - * See the LPC32x0 User's guide for GPIO group numbers - */ -#define LPC32XX_GPIO(x, y) ((x) + (y)) - -#endif /* _LPC32XX_GPIO_GRP_H */ diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h deleted file mode 100644 index 52fb0ab5782..00000000000 --- a/arch/arm/include/asm/arch-mx27/mxcmmc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2009 Ilya Yanok - */ - -#ifndef ASM_ARCH_MXCMMC_H -#define ASM_ARCH_MXCMMC_H - -int mxc_mmc_init(struct bd_info *bis); - -#endif diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h deleted file mode 100644 index b55a54cf1c9..00000000000 --- a/arch/arm/include/asm/arch-mx6/opos6ul.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Armadeus Systems - */ - -#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__ -#define __ARCH_ARM_MX6UL_OPOS6UL_H__ - -int opos6ul_board_late_init(void); - -#endif diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h deleted file mode 100644 index d89cf27b6a1..00000000000 --- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h +++ /dev/null @@ -1,219 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale MXS UARTAPP Register Definitions - * - * Copyright (C) 2013 Andreas Wass - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ARCH_ARM___MXS_UARTAPP_H -#define __ARCH_ARM___MXS_UARTAPP_H - -#include - -#ifndef __ASSEMBLY__ -struct mxs_uartapp_regs { - mxs_reg_32(hw_uartapp_ctrl0) - mxs_reg_32(hw_uartapp_ctrl1) - mxs_reg_32(hw_uartapp_ctrl2) - mxs_reg_32(hw_uartapp_linectrl) - mxs_reg_32(hw_uartapp_linectrl2) - mxs_reg_32(hw_uartapp_intr) - mxs_reg_32(hw_uartapp_data) - mxs_reg_32(hw_uartapp_stat) - mxs_reg_32(hw_uartapp_debug) - mxs_reg_32(hw_uartapp_version) - mxs_reg_32(hw_uartapp_autobaud) -}; -#endif - -#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) -#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) -#define UARTAPP_CTRL0_RUN_MASK (1 << 29) -#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) -#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) -#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 -#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) -#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL1_RUN_MASK (1 << 28) - -#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) -#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) -#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) -#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) -#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) -#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) -#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) -#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) -#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 -#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) - -#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) -#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 -#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) -#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) -#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) -#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) -#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) -#define UARTAPP_CTRL2_RTS_MASK (1 << 11) -#define UARTAPP_CTRL2_DTR_MASK (1 << 10) -#define UARTAPP_CTRL2_RXE_MASK (1 << 9) -#define UARTAPP_CTRL2_TXE_MASK (1 << 8) -#define UARTAPP_CTRL2_LBE_MASK (1 << 7) -#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) - -#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) -#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) -#define UARTAPP_CTRL2_UARTEN_MASK 0x01 - -#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) -#define UARTAPP_LINECTRL_BRK_MASK 1 - -#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) - -#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) -#define UARTAPP_INTR_OEIEN_MASK (1 << 26) -#define UARTAPP_INTR_BEIEN_MASK (1 << 25) -#define UARTAPP_INTR_PEIEN_MASK (1 << 24) -#define UARTAPP_INTR_FEIEN_MASK (1 << 23) -#define UARTAPP_INTR_RTIEN_MASK (1 << 22) -#define UARTAPP_INTR_TXIEN_MASK (1 << 21) -#define UARTAPP_INTR_RXIEN_MASK (1 << 20) -#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) -#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) -#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) -#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) - -#define UARTAPP_INTR_ABDIS_MASK (1 << 11) -#define UARTAPP_INTR_OEIS_MASK (1 << 10) -#define UARTAPP_INTR_BEIS_MASK (1 << 9) -#define UARTAPP_INTR_PEIS_MASK (1 << 8) -#define UARTAPP_INTR_FEIS_MASK (1 << 7) -#define UARTAPP_INTR_RTIS_MASK (1 << 6) -#define UARTAPP_INTR_TXIS_MASK (1 << 5) -#define UARTAPP_INTR_RXIS_MASK (1 << 4) -#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) -#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) -#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) -#define UARTAPP_INTR_RIMIS_MASK 0x1 - -#define UARTAPP_DATA_DATA_OFFSET 0 -#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF -#define UARTAPP_STAT_PRESENT_MASK (1 << 31) -#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) -#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) - -#define UARTAPP_STAT_HISPEED_MASK (1 << 30) -#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) -#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) - -#define UARTAPP_STAT_BUSY_MASK (1 << 29) -#define UARTAPP_STAT_CTS_MASK (1 << 28) -#define UARTAPP_STAT_TXFE_MASK (1 << 27) -#define UARTAPP_STAT_RXFF_MASK (1 << 26) -#define UARTAPP_STAT_TXFF_MASK (1 << 25) -#define UARTAPP_STAT_RXFE_MASK (1 << 24) -#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 -#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) - -#define UARTAPP_STAT_OERR_MASK (1 << 19) -#define UARTAPP_STAT_BERR_MASK (1 << 18) -#define UARTAPP_STAT_PERR_MASK (1 << 17) -#define UARTAPP_STAT_FERR_MASK (1 << 16) -#define UARTAPP_STAT_RXCOUNT_OFFSET 0 -#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF - -#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 -#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) - -#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 -#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) - -#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) -#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) -#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) -#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) -#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) -#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 - -#define UARTAPP_VERSION_MAJOR_OFFSET 24 -#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) - -#define UARTAPP_VERSION_MINOR_OFFSET 16 -#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) - -#define UARTAPP_VERSION_STEP_OFFSET 0 -#define UARTAPP_VERSION_STEP_MASK 0xFFFF - -#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 -#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) - -#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 -#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) - -#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) -#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) -#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) -#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) -#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 -#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h deleted file mode 100644 index 7b3c6c7ab57..00000000000 --- a/arch/arm/include/asm/arch-omap3/omap3-regs.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2011 Comelit Group SpA, Luca Ceresoli - */ - -#ifndef _OMAP3_REGS_H -#define _OMAP3_REGS_H - -/* - * Register definitions for OMAP3 processors. - */ - -/* - * GPMC_CONFIG1 - GPMC_CONFIG7 - */ - -/* Values for GPMC_CONFIG1 - signal control parameters */ -#define WRAPBURST (1 << 31) -#define READMULTIPLE (1 << 30) -#define READTYPE (1 << 29) -#define WRITEMULTIPLE (1 << 28) -#define WRITETYPE (1 << 27) -#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) -#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) -#define WAITREADMONITORING (1 << 22) -#define WAITWRITEMONITORING (1 << 21) -#define WAITMONITORINGTIME(x) (((x) & 3) << 18) -#define WAITPINSELECT(x) (((x) & 3) << 16) -#define DEVICESIZE(x) (((x) & 3) << 12) -#define DEVICESIZE_8BIT DEVICESIZE(0) -#define DEVICESIZE_16BIT DEVICESIZE(1) -#define DEVICETYPE(x) (((x) & 3) << 10) -#define DEVICETYPE_NOR DEVICETYPE(0) -#define DEVICETYPE_NAND DEVICETYPE(2) -#define MUXADDDATA (1 << 9) -#define TIMEPARAGRANULARITY (1 << 4) -#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) - -/* Values for GPMC_CONFIG2 - CS timing */ -#define CSWROFFTIME(x) (((x) & 0x1f) << 16) -#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) -#define CSEXTRADELAY (1 << 7) -#define CSONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG3 - nADV timing */ -#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) -#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) -#define ADVEXTRADELAY (1 << 7) -#define ADVONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG4 - nWE and nOE timing */ -#define WEOFFTIME(x) (((x) & 0x1f) << 24) -#define WEEXTRADELAY (1 << 23) -#define WEONTIME(x) (((x) & 0xf) << 16) -#define OEOFFTIME(x) (((x) & 0x1f) << 8) -#define OEEXTRADELAY (1 << 7) -#define OEONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ -#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) -#define RDACCESSTIME(x) (((x) & 0x1f) << 16) -#define WRCYCLETIME(x) (((x) & 0x1f) << 8) -#define RDCYCLETIME(x) (((x) & 0x1f) << 0) - -/* Values for GPMC_CONFIG6 - misc timings */ -#define WRACCESSTIME(x) (((x) & 0x1f) << 24) -#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) -#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) -#define CYCLE2CYCLESAMECSEN (1 << 7) -#define CYCLE2CYCLEDIFFCSEN (1 << 6) -#define BUSTURNAROUND(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG7 - CS address mapping configuration */ -#define MASKADDRESS(x) (((x) & 0xf) << 8) -#define CSVALID (1 << 6) -#define BASEADDRESS(x) (((x) & 0x3f) << 0) - -#endif /* _OMAP3_REGS_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h deleted file mode 100644 index 2460646e364..00000000000 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ /dev/null @@ -1,317 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff - * Aneesh V - * Balaji Krishnamoorthy - */ -#ifndef _MUX_OMAP5_H_ -#define _MUX_OMAP5_H_ - -#include - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define EMMC_CLK 0x0040 -#define EMMC_CMD 0x0042 -#define EMMC_DATA0 0x0044 -#define EMMC_DATA1 0x0046 -#define EMMC_DATA2 0x0048 -#define EMMC_DATA3 0x004a -#define EMMC_DATA4 0x004c -#define EMMC_DATA5 0x004e -#define EMMC_DATA6 0x0050 -#define EMMC_DATA7 0x0052 -#define C2C_CLKOUT0 0x0054 -#define C2C_CLKOUT1 0x0056 -#define C2C_CLKIN0 0x0058 -#define C2C_CLKIN1 0x005a -#define C2C_DATAIN0 0x005c -#define C2C_DATAIN1 0x005e -#define C2C_DATAIN2 0x0060 -#define C2C_DATAIN3 0x0062 -#define C2C_DATAIN4 0x0064 -#define C2C_DATAIN5 0x0066 -#define C2C_DATAIN6 0x0068 -#define C2C_DATAIN7 0x006a -#define C2C_DATAOUT0 0x006c -#define C2C_DATAOUT1 0x006e -#define C2C_DATAOUT2 0x0070 -#define C2C_DATAOUT3 0x0072 -#define C2C_DATAOUT4 0x0074 -#define C2C_DATAOUT5 0x0076 -#define C2C_DATAOUT6 0x0078 -#define C2C_DATAOUT7 0x007a -#define C2C_DATA8 0x007c -#define C2C_DATA9 0x007e -#define C2C_DATA10 0x0080 -#define C2C_DATA11 0x0082 -#define C2C_DATA12 0x0084 -#define C2C_DATA13 0x0086 -#define C2C_DATA14 0x0088 -#define C2C_DATA15 0x008a -#define LLIA_WAKEREQOUT 0x008c -#define LLIB_WAKEREQOUT 0x008e -#define HSI1_ACREADY 0x0090 -#define HSI1_CAREADY 0x0092 -#define HSI1_ACWAKE 0x0094 -#define HSI1_CAWAKE 0x0096 -#define HSI1_ACFLAG 0x0098 -#define HSI1_ACDATA 0x009a -#define HSI1_CAFLAG 0x009c -#define HSI1_CADATA 0x009e -#define UART1_TX 0x00a0 -#define UART1_CTS 0x00a2 -#define UART1_RX 0x00a4 -#define UART1_RTS 0x00a6 -#define HSI2_CAREADY 0x00a8 -#define HSI2_ACREADY 0x00aa -#define HSI2_CAWAKE 0x00ac -#define HSI2_ACWAKE 0x00ae -#define HSI2_CAFLAG 0x00b0 -#define HSI2_CADATA 0x00b2 -#define HSI2_ACFLAG 0x00b4 -#define HSI2_ACDATA 0x00b6 -#define UART2_RTS 0x00b8 -#define UART2_CTS 0x00ba -#define UART2_RX 0x00bc -#define UART2_TX 0x00be -#define USBB1_HSIC_STROBE 0x00c0 -#define USBB1_HSIC_DATA 0x00c2 -#define USBB2_HSIC_STROBE 0x00c4 -#define USBB2_HSIC_DATA 0x00c6 -#define TIMER10_PWM_EVT 0x00c8 -#define DSIPORTA_TE0 0x00ca -#define DSIPORTA_LANE0X 0x00cc -#define DSIPORTA_LANE0Y 0x00ce -#define DSIPORTA_LANE1X 0x00d0 -#define DSIPORTA_LANE1Y 0x00d2 -#define DSIPORTA_LANE2X 0x00d4 -#define DSIPORTA_LANE2Y 0x00d6 -#define DSIPORTA_LANE3X 0x00d8 -#define DSIPORTA_LANE3Y 0x00da -#define DSIPORTA_LANE4X 0x00dc -#define DSIPORTA_LANE4Y 0x00de -#define DSIPORTC_LANE0X 0x00e0 -#define DSIPORTC_LANE0Y 0x00e2 -#define DSIPORTC_LANE1X 0x00e4 -#define DSIPORTC_LANE1Y 0x00e6 -#define DSIPORTC_LANE2X 0x00e8 -#define DSIPORTC_LANE2Y 0x00ea -#define DSIPORTC_LANE3X 0x00ec -#define DSIPORTC_LANE3Y 0x00ee -#define DSIPORTC_LANE4X 0x00f0 -#define DSIPORTC_LANE4Y 0x00f2 -#define DSIPORTC_TE0 0x00f4 -#define TIMER9_PWM_EVT 0x00f6 -#define I2C4_SCL 0x00f8 -#define I2C4_SDA 0x00fa -#define MCSPI2_CLK 0x00fc -#define MCSPI2_SIMO 0x00fe -#define MCSPI2_SOMI 0x0100 -#define MCSPI2_CS0 0x0102 -#define RFBI_DATA15 0x0104 -#define RFBI_DATA14 0x0106 -#define RFBI_DATA13 0x0108 -#define RFBI_DATA12 0x010a -#define RFBI_DATA11 0x010c -#define RFBI_DATA10 0x010e -#define RFBI_DATA9 0x0110 -#define RFBI_DATA8 0x0112 -#define RFBI_DATA7 0x0114 -#define RFBI_DATA6 0x0116 -#define RFBI_DATA5 0x0118 -#define RFBI_DATA4 0x011a -#define RFBI_DATA3 0x011c -#define RFBI_DATA2 0x011e -#define RFBI_DATA1 0x0120 -#define RFBI_DATA0 0x0122 -#define RFBI_WE 0x0124 -#define RFBI_CS0 0x0126 -#define RFBI_A0 0x0128 -#define RFBI_RE 0x012a -#define RFBI_HSYNC0 0x012c -#define RFBI_TE_VSYNC0 0x012e -#define GPIO6_182 0x0130 -#define GPIO6_183 0x0132 -#define GPIO6_184 0x0134 -#define GPIO6_185 0x0136 -#define GPIO6_186 0x0138 -#define GPIO6_187 0x013a -#define HDMI_CEC 0x013c -#define HDMI_HPD 0x013e -#define HDMI_DDC_SCL 0x0140 -#define HDMI_DDC_SDA 0x0142 -#define CSIPORTC_LANE0X 0x0144 -#define CSIPORTC_LANE0Y 0x0146 -#define CSIPORTC_LANE1X 0x0148 -#define CSIPORTC_LANE1Y 0x014a -#define CSIPORTB_LANE0X 0x014c -#define CSIPORTB_LANE0Y 0x014e -#define CSIPORTB_LANE1X 0x0150 -#define CSIPORTB_LANE1Y 0x0152 -#define CSIPORTB_LANE2X 0x0154 -#define CSIPORTB_LANE2Y 0x0156 -#define CSIPORTA_LANE0X 0x0158 -#define CSIPORTA_LANE0Y 0x015a -#define CSIPORTA_LANE1X 0x015c -#define CSIPORTA_LANE1Y 0x015e -#define CSIPORTA_LANE2X 0x0160 -#define CSIPORTA_LANE2Y 0x0162 -#define CSIPORTA_LANE3X 0x0164 -#define CSIPORTA_LANE3Y 0x0166 -#define CSIPORTA_LANE4X 0x0168 -#define CSIPORTA_LANE4Y 0x016a -#define CAM_SHUTTER 0x016c -#define CAM_STROBE 0x016e -#define CAM_GLOBALRESET 0x0170 -#define TIMER11_PWM_EVT 0x0172 -#define TIMER5_PWM_EVT 0x0174 -#define TIMER6_PWM_EVT 0x0176 -#define TIMER8_PWM_EVT 0x0178 -#define I2C3_SCL 0x017a -#define I2C3_SDA 0x017c -#define GPIO8_233 0x017e -#define GPIO8_234 0x0180 -#define ABE_CLKS 0x0182 -#define ABEDMIC_DIN1 0x0184 -#define ABEDMIC_DIN2 0x0186 -#define ABEDMIC_DIN3 0x0188 -#define ABEDMIC_CLK1 0x018a -#define ABEDMIC_CLK2 0x018c -#define ABEDMIC_CLK3 0x018e -#define ABESLIMBUS1_CLOCK 0x0190 -#define ABESLIMBUS1_DATA 0x0192 -#define ABEMCBSP2_DR 0x0194 -#define ABEMCBSP2_DX 0x0196 -#define ABEMCBSP2_FSX 0x0198 -#define ABEMCBSP2_CLKX 0x019a -#define ABEMCPDM_UL_DATA 0x019c -#define ABEMCPDM_DL_DATA 0x019e -#define ABEMCPDM_FRAME 0x01a0 -#define ABEMCPDM_LB_CLK 0x01a2 -#define WLSDIO_CLK 0x01a4 -#define WLSDIO_CMD 0x01a6 -#define WLSDIO_DATA0 0x01a8 -#define WLSDIO_DATA1 0x01aa -#define WLSDIO_DATA2 0x01ac -#define WLSDIO_DATA3 0x01ae -#define UART5_RX 0x01b0 -#define UART5_TX 0x01b2 -#define UART5_CTS 0x01b4 -#define UART5_RTS 0x01b6 -#define I2C2_SCL 0x01b8 -#define I2C2_SDA 0x01ba -#define MCSPI1_CLK 0x01bc -#define MCSPI1_SOMI 0x01be -#define MCSPI1_SIMO 0x01c0 -#define MCSPI1_CS0 0x01c2 -#define MCSPI1_CS1 0x01c4 -#define I2C5_SCL 0x01c6 -#define I2C5_SDA 0x01c8 -#define PERSLIMBUS2_CLOCK 0x01ca -#define PERSLIMBUS2_DATA 0x01cc -#define UART6_TX 0x01ce -#define UART6_RX 0x01d0 -#define UART6_CTS 0x01d2 -#define UART6_RTS 0x01d4 -#define UART3_CTS_RCTX 0x01d6 -#define UART3_RTS_IRSD 0x01d8 -#define UART3_TX_IRTX 0x01da -#define UART3_RX_IRRX 0x01dc -#define USBB3_HSIC_STROBE 0x01de -#define USBB3_HSIC_DATA 0x01e0 -#define SDCARD_CLK 0x01e2 -#define SDCARD_CMD 0x01e4 -#define SDCARD_DATA2 0x01e6 -#define SDCARD_DATA3 0x01e8 -#define SDCARD_DATA0 0x01ea -#define SDCARD_DATA1 0x01ec -#define USBD0_HS_DP 0x01ee -#define USBD0_HS_DM 0x01f0 -#define I2C1_PMIC_SCL 0x01f2 -#define I2C1_PMIC_SDA 0x01f4 -#define USBD0_SS_RX 0x01f6 - -#define LLIA_WAKEREQIN 0x0040 -#define LLIB_WAKEREQIN 0x0042 -#define DRM_EMU0 0x0044 -#define DRM_EMU1 0x0046 -#define JTAG_NTRST 0x0048 -#define JTAG_TCK 0x004a -#define JTAG_RTCK 0x004c -#define JTAG_TMSC 0x004e -#define JTAG_TDI 0x0050 -#define JTAG_TDO 0x0052 -#define SYS_32K 0x0054 -#define FREF_CLK_IOREQ 0x0056 -#define FREF_CLK0_OUT 0x0058 -#define FREF_CLK1_OUT 0x005a -#define FREF_CLK2_OUT 0x005c -#define FREF_CLK2_REQ 0x005e -#define FREF_CLK1_REQ 0x0060 -#define SYS_NRESPWRON 0x0062 -#define SYS_NRESWARM 0x0064 -#define SYS_PWR_REQ 0x0066 -#define SYS_NIRQ1 0x0068 -#define SYS_NIRQ2 0x006a -#define SR_PMIC_SCL 0x006c -#define SR_PMIC_SDA 0x006e -#define SYS_BOOT0 0x0070 -#define SYS_BOOT1 0x0072 -#define SYS_BOOT2 0x0074 -#define SYS_BOOT3 0x0076 -#define SYS_BOOT4 0x0078 -#define SYS_BOOT5 0x007a - -#endif /* _MUX_OMAP5_H_ */ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h deleted file mode 100644 index ce831bc13a7..00000000000 --- a/arch/arm/include/asm/iproc-common/configs.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __IPROC_COMMON_CONFIGS_H -#define __IPROC_COMMON_CONFIGS_H - -#include - -/* Memory Info */ -#define CFG_SYS_SDRAM_BASE 0x61000000 - -#endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/arch/arm/include/asm/iproc-common/iproc_sdhci.h deleted file mode 100644 index 4e299217fcf..00000000000 --- a/arch/arm/include/asm/iproc-common/iproc_sdhci.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: */ -/* - * Copyright 2019 Broadcom - * - */ - -#ifndef __IPROC_SDHCI_H -#define __IPROC_SDHCI_H - -int iproc_sdhci_init(int dev_index, u32 quirks); - -#endif diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h deleted file mode 100644 index 22db651a4eb..00000000000 --- a/arch/arm/include/asm/kona-common/kona_sdhci.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __KONA_SDHCI_H -#define __KONA_SDHCI_H - -int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks); - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h deleted file mode 100644 index ba88c441e33..00000000000 --- a/arch/arm/mach-at91/include/mach/at91_rtt.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Real-time Timer - * Based on AT91SAM9XE datasheet - */ - -#ifndef AT91_RTT_H -#define AT91_RTT_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_rtt { - u32 mr; /* Mode Register RW 0x00008000 */ - u32 ar; /* Alarm Register RW 0xFFFFFFFF */ - u32 vr; /* Value Register RO 0x00000000 */ - u32 sr; /* Status Register RO 0x00000000 */ -} at91_rtt_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_RTT_MR_RTPRES 0x0000ffff -#define AT91_RTT_MR_ALMIEN 0x00010000 -#define AT91_RTT_RTTINCIEN 0x00020000 -#define AT91_RTT_RTTRST 0x00040000 - -#define AT91_RTT_SR_ALMS 0x00000001 -#define AT91_RTT_SR_RTTINC 0x00000002 - -#endif diff --git a/arch/arm/mach-davinci/include/mach/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h deleted file mode 100644 index 7419a58bd17..00000000000 --- a/arch/arm/mach-davinci/include/mach/aintc_defs.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#ifndef _DV_AINTC_DEFS_H_ -#define _DV_AINTC_DEFS_H_ - -struct dv_aintc_regs { - unsigned int fiq0; /* 0x00 */ - unsigned int fiq1; /* 0x04 */ - unsigned int irq0; /* 0x08 */ - unsigned int irq1; /* 0x0c */ - unsigned int fiqentry; /* 0x10 */ - unsigned int irqentry; /* 0x14 */ - unsigned int eint0; /* 0x18 */ - unsigned int eint1; /* 0x1c */ - unsigned int intctl; /* 0x20 */ - unsigned int eabase; /* 0x24 */ - unsigned char rsvd0[8]; /* 0x28 */ - unsigned int intpri0; /* 0x30 */ - unsigned int intpri1; /* 0x34 */ - unsigned int intpri2; /* 0x38 */ - unsigned int intpri3; /* 0x3c */ - unsigned int intpri4; /* 0x40 */ - unsigned int intpri5; /* 0x44 */ - unsigned int intpri6; /* 0x48 */ - unsigned int intpri7; /* 0x4c */ -}; - -#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) - -#define DV_AINTC_INTCTL_IDMODE (1 << 2) - -#endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/mach-keystone/include/mach/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h deleted file mode 100644 index 989b0c31580..00000000000 --- a/arch/arm/mach-keystone/include/mach/xhci-keystone.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * USB 3.0 DRD Controller - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - */ - -#ifndef __ASSEMBLY__ -#include -#endif - -#define USB3_PHY_REF_SSP_EN BIT(29) -#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) - -/* KEYSTONE2 XHCI PHY register structure */ -struct keystone_xhci_phy { - unsigned int phy_utmi; /* ctl0 */ - unsigned int phy_pipe; /* ctl1 */ - unsigned int phy_param_ctrl_1; /* ctl2 */ - unsigned int phy_param_ctrl_2; /* ctl3 */ - unsigned int phy_clock; /* ctl4 */ - unsigned int phy_pll; /* ctl5 */ -}; diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h deleted file mode 100644 index 5f806c4ec21..00000000000 --- a/arch/powerpc/include/asm/mc146818rtc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Machine dependent access functions for RTC registers. - */ -#ifndef __ASM_PPC_MC146818RTC_H -#define __ASM_PPC_MC146818RTC_H - -#include - -#ifndef RTC_PORT -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ -#endif - -/* - * The yet supported machines all access the RTC index register via - * an ISA port access but the way to access the date register differs ... - */ -#define CMOS_READ(addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -inb_p(RTC_PORT(1)); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -outb_p((val),RTC_PORT(1)); \ -}) - -#endif /* __ASM_PPC_MC146818RTC_H */ diff --git a/arch/powerpc/include/asm/pci_io.h b/arch/powerpc/include/asm/pci_io.h deleted file mode 100644 index 9b738c383f7..00000000000 --- a/arch/powerpc/include/asm/pci_io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* originally from linux source (asm-ppc/io.h). - * Sanity added by Rob Taylor, Flying Pig Systems, 2000 - */ -#ifndef _PCI_IO_H_ -#define _PCI_IO_H_ - -#include "io.h" - - -#define pci_read_le16(addr, dest) \ - __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le16(addr, val) \ - __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - - -#define pci_read_le32(addr, dest) \ - __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le32(addr, val) \ -__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - -#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr)) -#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) - -#if !defined(__BIG_ENDIAN) -#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr)) -#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr)) -#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b)) -#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b)) -#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b)) -#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b)) -#endif - - -#endif /* _PCI_IO_H_ */ diff --git a/arch/riscv/include/asm/arch-fu740/eeprom.h b/arch/riscv/include/asm/arch-fu740/eeprom.h deleted file mode 100644 index 0e1220e558e..00000000000 --- a/arch/riscv/include/asm/arch-fu740/eeprom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 SiFive, Inc. - * - * Zong Li - */ - -#ifndef _ASM_RISCV_EEPROM_H -#define _ASM_RISCV_EEPROM_H - -#define PCB_REVISION_REV3 0x3 - -u8 get_pcb_revision_from_eeprom(void); - -#endif /* _ASM_RISCV_EEPROM_H */ diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h deleted file mode 100644 index 5732b2bca3b..00000000000 --- a/arch/sh/include/asm/mmc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Renesas SuperH MMCIF driver. - * - * Copyright (C) 2012 Nobuhiro Iwamatsu - * Copyright (C) 2012 Renesas Solutions Corp. - * - */ -#ifndef _SH_MMC_H_ -#define _SH_MMC_H_ - -int mmcif_mmc_init(void); - -#endif /* _SH_MMC_H_ */ diff --git a/include/.gitignore b/include/.gitignore deleted file mode 100644 index 8e41a9511d4..00000000000 --- a/include/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/autoconf.mk* -/bmp_logo.h -/bmp_logo_data.h -/config.h diff --git a/include/ali512x.h b/include/ali512x.h deleted file mode 100644 index 6bb67009c1f..00000000000 --- a/include/ali512x.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - */ - -#ifndef __ASM_IC_ALI512X_H_ -#define __ASM_IC_ALI512X_H_ - -# define ALI_INDEX 0x3f0 -# define ALI_DATA 0x3f1 - -# define ALI_ENABLED 1 -# define ALI_DISABLED 0 - -# define ALI_UART1 0 -# define ALI_UART2 1 - -/* setup functions */ -void ali512x_init(void); -void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel); -void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel); -void ali512x_set_uart(int enabled, int index, u16 io, u8 irq); -void ali512x_set_rtc(int enabled, u16 io, u8 irq); -void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq); -void ali512x_set_cio(int enabled); - - -/* common I/O functions */ -void ali512x_cio_function(int pin, int special, int inv, int input); -void ali512x_cio_out(int pin, int value); -int ali512x_cio_in(int pin); - -/* misc features */ -void ali512x_set_uart2_irda(int enabled); - -#endif diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h deleted file mode 100644 index d24b82d18ef..00000000000 --- a/include/andestech/andes_pcu.h +++ /dev/null @@ -1,354 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin - */ - -/* - * Andes Power Control Unit - */ -#ifndef __ANDES_PCU_H -#define __ANDES_PCU_H - -#ifndef __ASSEMBLY__ - -struct pcs { - unsigned int cr; /* PCSx Configuration (clock scaling) */ - unsigned int parm; /* PCSx Parameter*/ - unsigned int stat1; /* PCSx Status 1 */ - unsigned int stat2; /* PCSx Stusts 2 */ - unsigned int pdd; /* PCSx PDD */ -}; - -struct andes_pcu { - unsigned int rev; /* 0x00 - PCU Revision */ - unsigned int spinfo; /* 0x04 - Scratch Pad Info */ - unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ - unsigned int soc_id; /* 0x10 - SoC ID */ - unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ - unsigned int soc_apb; /* 0x18 - SoC APB configuration */ - unsigned int rsvd2; /* 0x1C */ - unsigned int dcsrcr0; /* 0x20 - Driving Capability - and Slew Rate Control 0 */ - unsigned int dcsrcr1; /* 0x24 - Driving Capability - and Slew Rate Control 1 */ - unsigned int dcsrcr2; /* 0x28 - Driving Capability - and Slew Rate Control 2 */ - unsigned int rsvd3; /* 0x2C */ - unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ - unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ - unsigned int dmaes; /* 0x38 - DMA Engine Selection */ - unsigned int rsvd4; /* 0x3C */ - unsigned int oscc; /* 0x40 - OSC Control */ - unsigned int pwmcd; /* 0x44 - PWM Clock divider */ - unsigned int socmisc; /* 0x48 - SoC Misc. */ - unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ - unsigned int bsmcr; /* 0x80 - BSM Controrl */ - unsigned int bsmst; /* 0x84 - BSM Status */ - unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ - unsigned int west; /* 0x8C - Wakeup Event Status */ - unsigned int rsttiming; /* 0x90 - Reset Timing */ - unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ - unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ - struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ - unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ - struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ - unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ - struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ - unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ - struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ - unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ - struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ - unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ - struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ - unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ - struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ - unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ - struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ - unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ - struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ - unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ - unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager - Scratch Pad Memory 0 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * PCU Revision Register (ro) - */ -#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) -#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) - -/* - * Scratch Pad Info Register (ro) - */ -#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) -#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) - -/* - * SoC ID Register (ro) - */ -#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) -#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) -#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) - -/* - * SoC AHB Configuration Register (ro) - */ -#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) -#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) -#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) -#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) -#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) -#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) -#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) -#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) -#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) -#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) -#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) -#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) -#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) -#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) -#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) -#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) -#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) -#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) -#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) -#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) - -/* - * SoC APB Configuration Register (ro) - */ -#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) -#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) -#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) -#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) -#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) -#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) -#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) -#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) -#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) -#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) -#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) -#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) -#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) - -/* - * Driving Capability and Slew Rate Control Register 0 (rw) - */ -#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) -#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) -#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) -#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) -#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) - -/* - * Driving Capability and Slew Rate Control Register 1 (rw) - */ -#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) - -/* - * Driving Capability and Slew Rate Control Register 2 (rw) - */ -#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) -#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) -#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) -#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) -#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) -#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) -#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) -#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) - -/* - * Multi-function Port Setting Register 0 (rw) - */ -#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) -#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) -#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) -#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) -#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) -#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) -#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) - -/* - * Multi-function Port Setting Register 1 (rw) - */ -#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) -#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) -#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) -#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) -#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) -#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) -#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) -#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) -#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) -#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) -#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) -#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) -#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) -#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) -#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) -#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) - -/* - * DMA Engine Selection Register (rw) - */ -#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) -#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) -#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) -#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) -#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) -#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) -#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) -#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) - -/* - * OSC Control Register (rw) - */ -#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) -#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) -#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) -#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) -#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) -#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) - -/* - * PWM Clock Divider Register (rw) - */ -#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) - -/* - * SoC Misc. Register (rw) - */ -#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) -#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) -#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) -#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) -#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) -#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) -#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) -#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) -#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) -#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) -#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) -#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) -#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) -#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) -#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) -#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) -#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) -#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) -#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) -#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) -#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) -#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) -#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) -#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) -#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) -#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) -#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) -#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) -#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) -#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) - -/* - * BSM Control Register (rw) - */ -#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) -#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) -#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) -#define ANDES_PCU_BSMCR_IE(x) ((x) << 31) - -/* - * BSM Status Register - */ -#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) -#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) -#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) - -/* - * Wakeup Event Sensitivity Register (rw) - */ -#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) - -/* - * Wakeup Event Status Register (ro) - */ -#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) - -/* - * Reset Timing Register - */ -#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) -#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) -#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) -#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) - -/* - * PCU Interrupt Status Register - */ -#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) -#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) -#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) -#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) -#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) -#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) -#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) -#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) -#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) -#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) - -/* - * PCSx Configuration Register - */ -#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) -#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) -#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) -#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ - -/* - * PCSx Parameter Register (rw) - */ -#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) -#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) -#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) - -/* - * PCSx Status Register 1 - */ -#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) -#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) - -/* - * PCSx Status Register 2 - */ -#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) -#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) - -/* - * PCSx PDD Register - * This is reserved for PCS(1-7) - */ -#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) -#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) -#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) -#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) - -#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) -#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) -#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) -#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) -#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) -#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) -#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) -#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) -#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) - -#endif /* __ANDES_PCU_H */ diff --git a/include/asm-generic/types.h b/include/asm-generic/types.h deleted file mode 100644 index 7c076c56ce0..00000000000 --- a/include/asm-generic/types.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_GENERIC_TYPES_H -#define _ASM_GENERIC_TYPES_H -/* - * int-ll64 is used everywhere now. - */ -#include - -#endif /* _ASM_GENERIC_TYPES_H */ diff --git a/include/dp83848.h b/include/dp83848.h deleted file mode 100644 index f1bc3d86f26..00000000000 --- a/include/dp83848.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * DP83848 ethernet Physical layer - * - * Copyright (C) 2007 Sergey Kubushyn - * - */ - - -/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ - -#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ -#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ -#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ -#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ -#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ -#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ -#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ -#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ -#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ -#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ - -/*--Bit definitions: DP83848_CTL_REG */ -#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ -#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ -#define DP83848_SPEED_SELECT (1 << 13) -#define DP83848_AUTONEG (1 << 12) -#define DP83848_POWER_DOWN (1 << 11) -#define DP83848_ISOLATE (1 << 10) -#define DP83848_RESTART_AUTONEG (1 << 9) -#define DP83848_DUPLEX_MODE (1 << 8) -#define DP83848_COLLISION_TEST (1 << 7) - -/*--Bit definitions: DP83848_STAT_REG */ -#define DP83848_100BASE_T4 (1 << 15) -#define DP83848_100BASE_TX_FD (1 << 14) -#define DP83848_100BASE_TX_HD (1 << 13) -#define DP83848_10BASE_T_FD (1 << 12) -#define DP83848_10BASE_T_HD (1 << 11) -#define DP83848_MF_PREAMB_SUPPR (1 << 6) -#define DP83848_AUTONEG_COMP (1 << 5) -#define DP83848_RMT_FAULT (1 << 4) -#define DP83848_AUTONEG_ABILITY (1 << 3) -#define DP83848_LINK_STATUS (1 << 2) -#define DP83848_JABBER_DETECT (1 << 1) -#define DP83848_EXTEND_CAPAB (1 << 0) - -/*--definitions: DP83848_PHYID1 */ -#define DP83848_PHYID1_OUI 0x2000 -#define DP83848_PHYID2_OUI 0x5c90 - -/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ -#define DP83848_NP (1 << 15) -#define DP83848_ACK (1 << 14) -#define DP83848_RF (1 << 13) -#define DP83848_PAUSE (1 << 10) -#define DP83848_T4 (1 << 9) -#define DP83848_TX_FDX (1 << 8) -#define DP83848_TX_HDX (1 << 7) -#define DP83848_10_FDX (1 << 6) -#define DP83848_10_HDX (1 << 5) -#define DP83848_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: DP83848_ANER */ -#define DP83848_PDF (1 << 4) -#define DP83848_LP_NP_ABLE (1 << 3) -#define DP83848_NP_ABLE (1 << 2) -#define DP83848_PAGE_RX (1 << 1) -#define DP83848_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: DP83848_PHY_STAT */ -#define DP83848_RX_ERR_LATCH (1 << 13) -#define DP83848_POLARITY_STAT (1 << 12) -#define DP83848_FALSE_CAR_SENSE (1 << 11) -#define DP83848_SIG_DETECT (1 << 10) -#define DP83848_DESCRAM_LOCK (1 << 9) -#define DP83848_PAGE_RCV (1 << 8) -#define DP83848_PHY_RMT_FAULT (1 << 6) -#define DP83848_JABBER (1 << 5) -#define DP83848_AUTONEG_COMPLETE (1 << 4) -#define DP83848_LOOPBACK_STAT (1 << 3) -#define DP83848_DUPLEX (1 << 2) -#define DP83848_SPEED (1 << 1) -#define DP83848_LINK (1 << 0) diff --git a/include/ds1722.h b/include/ds1722.h deleted file mode 100644 index e115696ceae..00000000000 --- a/include/ds1722.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _DS1722_H_ -#define _DS1722_H_ - -#define DS1722_RESOLUTION_8BIT 0x0 -#define DS1722_RESOLUTION_9BIT 0x1 -#define DS1722_RESOLUTION_10BIT 0x2 -#define DS1722_RESOLUTION_11BIT 0x3 -#define DS1722_RESOLUTION_12BIT 0x4 - -int ds1722_probe(int dev); - -#endif /* _DS1722_H_ */ diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h deleted file mode 100644 index 484bd36334f..00000000000 --- a/include/exynos_lcd.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * exynos_lcd.h - Exynos LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _EXYNOS_LCD_H_ -#define _EXYNOS_LCD_H_ - -enum { - FIMD_RGB_INTERFACE = 1, - FIMD_CPU_INTERFACE = 2, -}; - -enum exynos_fb_rgb_mode_t { - MODE_RGB_P = 0, - MODE_BGR_P = 1, - MODE_RGB_S = 2, - MODE_BGR_S = 3, -}; - -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_freq; /* Frequency */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel */ - - /* Horizontal control register. Timing from data sheet */ - u_char vl_hspw; /* Horz sync pulse width */ - u_char vl_hfpd; /* Wait before of line */ - u_char vl_hbpd; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vspw; /* Vertical sync pulse width */ - u_char vl_vfpd; /* Wait before of frame */ - u_char vl_vbpd; /* Wait end of frame */ - u_char vl_cmd_allow_len; /* Wait end of frame */ - - unsigned int win_id; - unsigned int init_delay; - unsigned int power_on_delay; - unsigned int reset_delay; - unsigned int interface_mode; - unsigned int mipi_enabled; - unsigned int dp_enabled; - unsigned int cs_setup; - unsigned int wr_setup; - unsigned int wr_act; - unsigned int wr_hold; - unsigned int logo_on; - unsigned int logo_width; - unsigned int logo_height; - int logo_x_offset; - int logo_y_offset; - unsigned long logo_addr; - unsigned int rgb_mode; - unsigned int resolution; - - /* parent clock name(MPLL, EPLL or VPLL) */ - unsigned int pclk_name; - /* ratio value for source clock from parent clock. */ - unsigned int sclk_div; - - unsigned int dual_lcd_enabled; - struct exynos_fb *reg; - struct exynos_platform_mipi_dsim *dsim_platform_data_dt; -} vidinfo_t; - -#endif diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h deleted file mode 100644 index 8801bd13508..00000000000 --- a/include/faraday/ftpci100.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation - * - * Copyright (C) 2010 Andes Technology Corporation - * Gavin Guo, Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation - */ - -#ifndef __FTPCI100_H -#define __FTPCI100_H - -/* AHB Control Registers */ -#include -struct ftpci100_ahbc { - unsigned int iosize; /* 0x00 - I/O Space Size Signal */ - unsigned int prot; /* 0x04 - AHB Protection */ - unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ - unsigned int conf; /* 0x28 - PCI Configuration */ - unsigned int data; /* 0x2c - PCI Configuration DATA */ -}; - -/* - * FTPCI100_IOSIZE_REG's constant definitions - */ -#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ - -/* - * PCI Configuration Register - */ -#define PCI_INT_MASK 0x4c -#define PCI_MEM_BASE_SIZE1 0x50 -#define PCI_MEM_BASE_SIZE2 0x54 -#define PCI_MEM_BASE_SIZE3 0x58 - -/* - * PCI_INT_MASK's bit definitions - */ -#define PCI_INTA_ENABLE (1 << 22) -#define PCI_INTB_ENABLE (1 << 23) -#define PCI_INTC_ENABLE (1 << 24) -#define PCI_INTD_ENABLE (1 << 25) - -/* - * PCI_MEM_BASE_SIZE1's constant definitions - */ -#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ - -#define FTPCI100_MAX_FUNCTIONS 20 -#define PCI_IRQ_LINES 4 - -#define MAX_BUS_NUM 256 -#define MAX_DEV_NUM 32 -#define MAX_FUN_NUM 8 - -#define PCI_MAX_BAR_PER_FUNC 6 - -/* - * PCI_MEM_SIZE - */ -#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) - -/* This definition is used by pci_ftpci_init() */ -#define FTPCI100_BRIDGE_VENDORID 0x159b -#define FTPCI100_BRIDGE_DEVICEID 0x4321 - -void pci_ftpci_init(void); - -struct pcibar { - unsigned int size; - unsigned int addr; -}; - -struct pci_config { - unsigned int bus; - unsigned int dev; /* device */ - unsigned int func; - unsigned int pin; - unsigned short v_id; /* vendor id */ - unsigned short d_id; /* device id */ - struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; -}; - -#endif diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h deleted file mode 100644 index d74da16ef28..00000000000 --- a/include/faraday/ftsdmc020.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h deleted file mode 100644 index e0e5eb339e1..00000000000 --- a/include/faraday/ftsdmc021.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin - */ - -/* - * FTSDMC021 - SDRAM Controller - */ -#ifndef __FTSDMC021_H -#define __FTSDMC021_H - -#ifndef __ASSEMBLY__ -#include -struct ftsdmc021 { - unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ - unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ - unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ - unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ - unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ - unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ - unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ - unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ - unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ - unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ - unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ - unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ - unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ - unsigned int frr; /* 0x34 - Flush Request Register */ - unsigned int ebisr; /* 0x38 - EBI Support Register */ - unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ - unsigned int crr; /* 0x100 - Controller Revision Reg */ - unsigned int cfr; /* 0x104 - Controller Feature Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Timing Parameter 1 Register - */ -#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ -#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ -#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ -#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ -#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ -#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parameter 2 Register - */ -#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ -/* b(16:19) - Initial Refresh Times */ -#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) -/* b(20:23) - Initial Pre-Charge Times */ -#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * SDRAM Configuration Register 1 - */ -#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ -#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ -#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ -#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ -/* b(16) MA2T: Double Memory Address Cycle Enable */ -#define FTSDMC021_CR1_MA2T(x) (1 << 16) -/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ -#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) - -/* - * Configuration Register 2 - */ -#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ -#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ -#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ -#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ -#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ -#define FTSDMC021_CR2_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC021_BANK_ENABLE (1 << 12) - -/* 12-bit base address of external bank. - * Default value is 0x800. - * The 12-bit equals to the haddr[31:20] of AHB address bus. */ -#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) - -/* - * Read Arbitration Grant Window Register - */ -#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) -#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) -#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) -#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) -#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) -#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) -#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) -#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) - -/* - * Flush Request Register - */ -#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) -#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ - -/* - * External Bus Interface Support Register (EBISR) - */ -#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ -#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ -#define FTSDMC021_EBISR_POPREC (1 << 13) -#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ - -/* - * Controller Revision Register (CRR, Read Only) - */ -#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) -#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) -#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) - -/* - * Controller Feature Register (CFR, Read Only) - */ -#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) -#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) -#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) -#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) -#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) -#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) -#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) -#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) -#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) -#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) -#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) - -#endif /* __FTSDMC021_H */ diff --git a/include/lcd_console.h b/include/lcd_console.h deleted file mode 100644 index 061a6a41bbd..00000000000 --- a/include/lcd_console.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ - */ - -/* By default we scroll by a single line */ - -struct console_t { - short curr_col, curr_row; - short cols, rows; - void *fbbase; - u32 lcdsizex, lcdsizey, lcdrot; - void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c); - void (*fp_console_moverow)(struct console_t *pcons, - u32 rowdst, u32 rowsrc); - void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr); -}; - -/** - * console_calc_rowcol() - calculate available rows / columns wihtin a given - * screen-size based on used VIDEO_FONT. - * - * @pcons: Pointer to struct console_t - * @sizex: size X of the screen in pixel - * @sizey: size Y of the screen in pixel - */ -void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey); -/** - * lcd_init_console() - Initialize lcd console parameters - * - * Setup the address of console base, and the number of rows and columns the - * console has. - * - * @address: Console base address - * @vl_rows: Number of rows in the console - * @vl_cols: Number of columns in the console - * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise - */ -void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot); -/** - * lcd_set_col() - Set the number of the current lcd console column - * - * Set the number of the console column where the cursor is. - * - * @col: Column number - */ -void lcd_set_col(short col); - -/** - * lcd_set_row() - Set the number of the current lcd console row - * - * Set the number of the console row where the cursor is. - * - * @row: Row number - */ -void lcd_set_row(short row); - -/** - * lcd_position_cursor() - Position the cursor on the screen - * - * Position the cursor at the given coordinates on the screen. - * - * @col: Column number - * @row: Row number - */ -void lcd_position_cursor(unsigned col, unsigned row); - -/** - * lcd_get_screen_rows() - Get the total number of screen rows - * - * @return: Number of screen rows - */ -int lcd_get_screen_rows(void); - -/** - * lcd_get_screen_columns() - Get the total number of screen columns - * - * @return: Number of screen columns - */ -int lcd_get_screen_columns(void); - -/** - * lcd_putc() - Print to screen a single character at the location of the cursor - * - * @c: The character to print - */ -void lcd_putc(const char c); - -/** - * lcd_puts() - Print to screen a string at the location of the cursor - * - * @s: The string to print - */ -void lcd_puts(const char *s); - -/** - * lcd_printf() - Print to screen a formatted string at location of the cursor - * - * @fmt: The formatted string to print - * @...: The arguments for the formatted string - */ -void lcd_printf(const char *fmt, ...); diff --git a/include/lcdvideo.h b/include/lcdvideo.h deleted file mode 100644 index f0640a53852..00000000000 --- a/include/lcdvideo.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * MPC823 LCD and Video Controller - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - */ -#ifndef __LCDVIDEO_H__ -#define __LCDVIDEO_H__ - - -/* LCD Controller Configuration Register. -*/ -#define LCCR_BNUM ((uint)0xfffe0000) -#define LCCR_EIEN ((uint)0x00010000) -#define LCCR_IEN ((uint)0x00008000) -#define LCCR_IRQL ((uint)0x00007000) -#define LCCR_CLKP ((uint)0x00000800) -#define LCCR_OEP ((uint)0x00000400) -#define LCCR_HSP ((uint)0x00000200) -#define LCCR_VSP ((uint)0x00000100) -#define LCCR_DP ((uint)0x00000080) -#define LCCR_BPIX ((uint)0x00000060) -#define LCCR_LBW ((uint)0x00000010) -#define LCCR_SPLT ((uint)0x00000008) -#define LCCR_CLOR ((uint)0x00000004) -#define LCCR_TFT ((uint)0x00000002) -#define LCCR_PON ((uint)0x00000001) - -/* Define the bit shifts to load values into the register. -*/ -#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) - -#define LCCR_BNUM_BIT ((uint)14) -#define LCCR_EIEN_BIT ((uint)15) -#define LCCR_IEN_BIT ((uint)16) -#define LCCR_IROL_BIT ((uint)19) -#define LCCR_CLKP_BIT ((uint)20) -#define LCCR_OEP_BIT ((uint)21) -#define LCCR_HSP_BIT ((uint)22) -#define LCCR_VSP_BIT ((uint)23) -#define LCCR_DP_BIT ((uint)24) -#define LCCR_BPIX_BIT ((uint)26) -#define LCCR_LBW_BIT ((uint)27) -#define LCCR_SPLT_BIT ((uint)28) -#define LCCR_CLOR_BIT ((uint)29) -#define LCCR_TFT_BIT ((uint)30) -#define LCCR_PON_BIT ((uint)31) - -/* LCD Horizontal control register. -*/ -#define LCHCR_BO ((uint)0x01000000) -#define LCHCR_AT ((uint)0x00e00000) -#define LCHCR_HPC ((uint)0x001ffc00) -#define LCHCR_WBL ((uint)0x000003ff) - -#define LCHCR_AT_BIT ((uint)10) -#define LCHCR_HPC_BIT ((uint)21) -#define LCHCR_WBL_BIT ((uint)31) - -/* LCD Vertical control register. -*/ -#define LCVCR_VPW ((uint)0xf0000000) -#define LCVCR_LCD_AC ((uint)0x01e00000) -#define LCVCR_VPC ((uint)0x001ff800) -#define LCVCR_WBF ((uint)0x000003ff) - -#define LCVCR_VPW_BIT ((uint)3) -#define LCVCR_LCD_AC_BIT ((uint)10) -#define LCVCR_VPC_BIT ((uint)20) - -#endif /* __LCDVIDEO_H__ */ diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h deleted file mode 100644 index 0644d92b3ca..00000000000 --- a/include/linux/mc146818rtc.h +++ /dev/null @@ -1,86 +0,0 @@ -/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM - * Copyright Torsten Duwe 1993 - * derived from Data Sheet, Copyright Motorola 1984 (!). - * It was written to be part of the Linux operating system. - */ -/* permission is hereby granted to copy, modify and redistribute this code - * in terms of the GNU Library General Public License, Version 2 or later, - * at your option. - */ - -#ifndef _MC146818RTC_H -#define _MC146818RTC_H - -#include -#include /* get the user-level API */ -#include /* register access macros */ - -/********************************************************************** - * register summary - **********************************************************************/ -#define RTC_SECONDS 0 -#define RTC_SECONDS_ALARM 1 -#define RTC_MINUTES 2 -#define RTC_MINUTES_ALARM 3 -#define RTC_HOURS 4 -#define RTC_HOURS_ALARM 5 -/* RTC_*_alarm is always true if 2 MSBs are set */ -# define RTC_ALARM_DONT_CARE 0xC0 - -#define RTC_DAY_OF_WEEK 6 -#define RTC_DAY_OF_MONTH 7 -#define RTC_MONTH 8 -#define RTC_YEAR 9 - -/* control registers - Moto names - */ -#define RTC_REG_A 10 -#define RTC_REG_B 11 -#define RTC_REG_C 12 -#define RTC_REG_D 13 - -/********************************************************************** - * register details - **********************************************************************/ -#define RTC_FREQ_SELECT RTC_REG_A - -/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, - * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, - * totalling to a max high interval of 2.228 ms. - */ -# define RTC_UIP 0x80 -# define RTC_DIV_CTL 0x70 - /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ -# define RTC_REF_CLCK_4MHZ 0x00 -# define RTC_REF_CLCK_1MHZ 0x10 -# define RTC_REF_CLCK_32KHZ 0x20 - /* 2 values for divider stage reset, others for "testing purposes only" */ -# define RTC_DIV_RESET1 0x60 -# define RTC_DIV_RESET2 0x70 - /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ -# define RTC_RATE_SELECT 0x0F - -/**********************************************************************/ -#define RTC_CONTROL RTC_REG_B -# define RTC_SET 0x80 /* disable updates for clock setting */ -# define RTC_PIE 0x40 /* periodic interrupt enable */ -# define RTC_AIE 0x20 /* alarm interrupt enable */ -# define RTC_UIE 0x10 /* update-finished interrupt enable */ -# define RTC_SQWE 0x08 /* enable square-wave output */ -# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -/**********************************************************************/ -#define RTC_INTR_FLAGS RTC_REG_C -/* caution - cleared by read */ -# define RTC_IRQF 0x80 /* any of the following 3 is active */ -# define RTC_PF 0x40 -# define RTC_AF 0x20 -# define RTC_UF 0x10 - -/**********************************************************************/ -#define RTC_VALID RTC_REG_D -# define RTC_VRT 0x80 /* valid RAM and time */ -/**********************************************************************/ -#endif /* _MC146818RTC_H */ diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h deleted file mode 100644 index a72cb7d20b7..00000000000 --- a/include/linux/mtd/doc2000.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Linux driver for Disk-On-Chip devices - * - * Copyright © 1999 Machine Vision Holdings, Inc. - * Copyright © 1999-2010 David Woodhouse - * Copyright © 2002-2003 Greg Ungerer - * Copyright © 2002-2003 SnapGear Inc - * - */ - -#ifndef __MTD_DOC2000_H__ -#define __MTD_DOC2000_H__ - -#include -#if 0 -#include -#endif - -#define DoC_Sig1 0 -#define DoC_Sig2 1 - -#define DoC_ChipID 0x1000 -#define DoC_DOCStatus 0x1001 -#define DoC_DOCControl 0x1002 -#define DoC_FloorSelect 0x1003 -#define DoC_CDSNControl 0x1004 -#define DoC_CDSNDeviceSelect 0x1005 -#define DoC_ECCConf 0x1006 -#define DoC_2k_ECCStatus 0x1007 - -#define DoC_CDSNSlowIO 0x100d -#define DoC_ECCSyndrome0 0x1010 -#define DoC_ECCSyndrome1 0x1011 -#define DoC_ECCSyndrome2 0x1012 -#define DoC_ECCSyndrome3 0x1013 -#define DoC_ECCSyndrome4 0x1014 -#define DoC_ECCSyndrome5 0x1015 -#define DoC_AliasResolution 0x101b -#define DoC_ConfigInput 0x101c -#define DoC_ReadPipeInit 0x101d -#define DoC_WritePipeTerm 0x101e -#define DoC_LastDataRead 0x101f -#define DoC_NOP 0x1020 - -#define DoC_Mil_CDSN_IO 0x0800 -#define DoC_2k_CDSN_IO 0x1800 - -#define DoC_Mplus_NOP 0x1002 -#define DoC_Mplus_AliasResolution 0x1004 -#define DoC_Mplus_DOCControl 0x1006 -#define DoC_Mplus_AccessStatus 0x1008 -#define DoC_Mplus_DeviceSelect 0x1008 -#define DoC_Mplus_Configuration 0x100a -#define DoC_Mplus_OutputControl 0x100c -#define DoC_Mplus_FlashControl 0x1020 -#define DoC_Mplus_FlashSelect 0x1022 -#define DoC_Mplus_FlashCmd 0x1024 -#define DoC_Mplus_FlashAddress 0x1026 -#define DoC_Mplus_FlashData0 0x1028 -#define DoC_Mplus_FlashData1 0x1029 -#define DoC_Mplus_ReadPipeInit 0x102a -#define DoC_Mplus_LastDataRead 0x102c -#define DoC_Mplus_LastDataRead1 0x102d -#define DoC_Mplus_WritePipeTerm 0x102e -#define DoC_Mplus_ECCSyndrome0 0x1040 -#define DoC_Mplus_ECCSyndrome1 0x1041 -#define DoC_Mplus_ECCSyndrome2 0x1042 -#define DoC_Mplus_ECCSyndrome3 0x1043 -#define DoC_Mplus_ECCSyndrome4 0x1044 -#define DoC_Mplus_ECCSyndrome5 0x1045 -#define DoC_Mplus_ECCConf 0x1046 -#define DoC_Mplus_Toggle 0x1046 -#define DoC_Mplus_DownloadStatus 0x1074 -#define DoC_Mplus_CtrlConfirm 0x1076 -#define DoC_Mplus_Power 0x1fff - -/* How to access the device? - * On ARM, it'll be mmap'd directly with 32-bit wide accesses. - * On PPC, it's mmap'd and 16-bit wide. - * Others use readb/writeb - */ -#if defined(__arm__) -#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0) -#define DOC_IOREMAP_LEN 0x8000 -#elif defined(__ppc__) -#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0) -#define DOC_IOREMAP_LEN 0x4000 -#else -#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg)) -#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg)) -#define DOC_IOREMAP_LEN 0x2000 - -#endif - -#if defined(__i386__) || defined(__x86_64__) -#define USE_MEMCPY -#endif - -/* These are provided to directly use the DoC_xxx defines */ -#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg) -#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg) - -#define DOC_MODE_RESET 0 -#define DOC_MODE_NORMAL 1 -#define DOC_MODE_RESERVED1 2 -#define DOC_MODE_RESERVED2 3 - -#define DOC_MODE_CLR_ERR 0x80 -#define DOC_MODE_RST_LAT 0x10 -#define DOC_MODE_BDECT 0x08 -#define DOC_MODE_MDWREN 0x04 - -#define DOC_ChipID_Doc2k 0x20 -#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */ -#define DOC_ChipID_DocMil 0x30 -#define DOC_ChipID_DocMilPlus32 0x40 -#define DOC_ChipID_DocMilPlus16 0x41 - -#define CDSN_CTRL_FR_B 0x80 -#define CDSN_CTRL_FR_B0 0x40 -#define CDSN_CTRL_FR_B1 0x80 - -#define CDSN_CTRL_ECC_IO 0x20 -#define CDSN_CTRL_FLASH_IO 0x10 -#define CDSN_CTRL_WP 0x08 -#define CDSN_CTRL_ALE 0x04 -#define CDSN_CTRL_CLE 0x02 -#define CDSN_CTRL_CE 0x01 - -#define DOC_ECC_RESET 0 -#define DOC_ECC_ERROR 0x80 -#define DOC_ECC_RW 0x20 -#define DOC_ECC__EN 0x08 -#define DOC_TOGGLE_BIT 0x04 -#define DOC_ECC_RESV 0x02 -#define DOC_ECC_IGNORE 0x01 - -#define DOC_FLASH_CE 0x80 -#define DOC_FLASH_WP 0x40 -#define DOC_FLASH_BANK 0x02 - -/* We have to also set the reserved bit 1 for enable */ -#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV) -#define DOC_ECC_DIS (DOC_ECC_RESV) - -struct Nand { - char floor, chip; - unsigned long curadr; - unsigned char curmode; - /* Also some erase/write/pipeline info when we get that far */ -}; - -#define MAX_FLOORS 4 -#define MAX_CHIPS 4 - -#define MAX_FLOORS_MIL 1 -#define MAX_CHIPS_MIL 1 - -#define MAX_FLOORS_MPLUS 2 -#define MAX_CHIPS_MPLUS 1 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -struct DiskOnChip { - unsigned long physadr; - void __iomem *virtadr; - unsigned long totlen; - unsigned char ChipID; /* Type of DiskOnChip */ - int ioreg; - - unsigned long mfr; /* Flash IDs - only one type of flash per device */ - unsigned long id; - int chipshift; - char page256; - char pageadrlen; - char interleave; /* Internal interleaving - Millennium Plus style */ - unsigned long erasesize; - - int curfloor; - int curchip; - - int numchips; - struct Nand *chips; - struct mtd_info *nextdoc; -/* XXX U-BOOT XXX */ -#if 0 - struct mutex lock; -#endif -}; - -int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]); - -/* XXX U-BOOT XXX */ -#if 1 -/* - * NAND Flash Manufacturer ID Codes - */ -#define NAND_MFR_TOSHIBA 0x98 -#define NAND_MFR_SAMSUNG 0xec -#endif - -#endif /* __MTD_DOC2000_H__ */ diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h deleted file mode 100644 index d0558a98262..00000000000 --- a/include/linux/mtd/ndfc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * linux/include/linux/mtd/ndfc.h - * - * Copyright (c) 2006 Thomas Gleixner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Info: - * Contains defines, datastructures for ndfc nand controller - * - */ -#ifndef __LINUX_MTD_NDFC_H -#define __LINUX_MTD_NDFC_H - -/* NDFC Register definitions */ -#define NDFC_CMD 0x00 -#define NDFC_ALE 0x04 -#define NDFC_DATA 0x08 -#define NDFC_ECC 0x10 -#define NDFC_BCFG0 0x30 -#define NDFC_BCFG1 0x34 -#define NDFC_BCFG2 0x38 -#define NDFC_BCFG3 0x3c -#define NDFC_CCR 0x40 -#define NDFC_STAT 0x44 -#define NDFC_HWCTL 0x48 -#define NDFC_REVID 0x50 - -#define NDFC_STAT_IS_READY 0x01000000 - -#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ -#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ -#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ -#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ -#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ -#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ -#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ -#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ -#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ -#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ -#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ -#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ -#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ -#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ -#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ -#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ - -#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ -#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ -#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ -#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ -#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ - -#define NDFC_MAX_BANKS 4 - -struct ndfc_controller_settings { - uint32_t ccr_settings; - uint64_t ndfc_erpn; -}; - -struct ndfc_chip_settings { - uint32_t bank_settings; -}; - -#endif diff --git a/include/linux_logo.h b/include/linux_logo.h deleted file mode 100644 index 9aa712eb4e0..00000000000 --- a/include/linux_logo.h +++ /dev/null @@ -1,1445 +0,0 @@ -/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $ - * include/linux/linux_logo.h: This is a linux logo - * to be displayed on boot. - * - * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu) - * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) - * - * You can put anything here, but: - * LINUX_LOGO_COLORS has to be less than 224 - * image size has to be 80x80 - * values have to start from 0x20 - * (i.e. RGB(linux_logo_red[0], - * linux_logo_green[0], - * linux_logo_blue[0]) is color 0x20) - * BW image has to be 80x80 as well, with MS bit - * on the left - * Serial_console ascii image can be any size, - * but should contain %s to display the version - */ - -#if LINUX_LOGO_COLORS == 214 - -unsigned char linux_logo_red[] __initdata = { - 0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9, - 0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6, - 0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2, - 0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54, - 0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74, - 0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E, - 0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38, - 0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3, - 0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA, - 0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC, - 0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B, - 0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52, - 0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2, - 0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6, - 0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF, - 0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46, - 0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6, - 0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA, - 0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E, - 0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7, - 0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4, - 0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA, - 0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59, - 0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB, - 0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6, - 0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72, - 0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4 -}; - -unsigned char linux_logo_green[] __initdata = { - 0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5, - 0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86, - 0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96, - 0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54, - 0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74, - 0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42, - 0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24, - 0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C, - 0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2, - 0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D, - 0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E, - 0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A, - 0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE, - 0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE, - 0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB, - 0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E, - 0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E, - 0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A, - 0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62, - 0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6, - 0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA, - 0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6, - 0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45, - 0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92, - 0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA, - 0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56, - 0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE -}; - -unsigned char linux_logo_blue[] __initdata = { - 0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7, - 0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20, - 0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40, - 0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56, - 0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74, - 0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11, - 0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A, - 0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11, - 0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C, - 0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C, - 0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E, - 0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C, - 0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94, - 0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC, - 0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91, - 0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C, - 0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C, - 0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74, - 0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04, - 0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2, - 0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10, - 0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C, - 0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E, - 0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C, - 0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C, - 0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24, - 0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7 -}; - -unsigned char linux_logo[] __initdata = { - 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C, - 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95, - 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, - 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6, - 0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55, - 0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A, - 0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, - 0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, - 0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, - 0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, - 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95, - 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB, - 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C, - 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C, - 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C, - 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, - 0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, - 0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, - 0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, - 0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, - 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95, - 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70, - 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, - 0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, - 0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95, - 0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1, - 0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, - 0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, - 0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, - 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1, - 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95, - 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB, - 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0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4, - 0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A, - 0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95, - 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6, - 0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD, - 0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1, - 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94, - 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95, - 0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, - 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95, - 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C, - 0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C, - 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95, - 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF, - 0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1, - 0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70, - 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55, - 0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1, - 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55, - 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95, - 0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95, - 0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95, - 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, - 0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D, - 0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, - 0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB, - 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, - 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95, - 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95, - 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, - 0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C, - 0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, - 0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, - 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55, - 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, - 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95, - 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6, - 0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55, - 0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95, - 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, - 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, - 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, - 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, - 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55 -}; - -#endif - -#ifdef INCLUDE_LINUX_LOGOBW - -unsigned char linux_logo_bw[] __initdata = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, - 0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, - 0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, - 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7, - 0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, - 0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, - 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4, - 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C, - 0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF, - 0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF, - 0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29, - 0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F, - 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00, - 0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, - 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF, - 0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19, - 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E, - 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00, - 0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, - 0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF, - 0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11, - 0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06, - 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00, - 0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1, - 0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF, - 0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10, - 0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00, - 0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00, - 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7, - 0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, - 0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, - 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01, - 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, - 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F, - 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, - 0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18, - 0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03, - 0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00, - 0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF, - 0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01, - 0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00, - 0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00, - 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40, - 0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF, - 0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23, - 0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00, - 0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80, - 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00, - 0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF, - 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04, - 0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10, - 0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80, - 0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00, - 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF, - 0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, - 0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0, - 0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40, - 0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00, - 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF, - 0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40, - 0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0, - 0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF, - 0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F, - 0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF, - 0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F, - 0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F, - 0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07, - 0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -}; - -#endif - -#ifdef INCLUDE_LINUX_LOGO16 - -unsigned char linux_logo16_red[] __initdata = { - 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5, - 0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8 -}; - -unsigned char linux_logo16_green[] __initdata = { - 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5, - 0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8 -}; - -unsigned char linux_logo16_blue[] __initdata = { - 0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5, - 0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8 -}; - -unsigned char linux_logo16[] __initdata = { - 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-#endif diff --git a/include/lxt971a.h b/include/lxt971a.h deleted file mode 100644 index a5dd82b62a8..00000000000 --- a/include/lxt971a.h +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ - * @Author: Markus Pietrek - * @References: [1] NS9750 Hardware Reference, December 2003 - * [2] Intel LXT971 Datasheet #249414 Rev. 02 - * [3] NS7520 Linux Ethernet Driver - */ - -#ifndef __LXT971A_H__ -#define __LXT971A_H__ - -/* PHY definitions (LXT971A) [2] */ -#define PHY_LXT971_PORT_CFG (0x10) -#define PHY_LXT971_STAT2 (0x11) -#define PHY_LXT971_INT_ENABLE (0x12) -#define PHY_LXT971_INT_STATUS (0x13) -#define PHY_LXT971_LED_CFG (0x14) -#define PHY_LXT971_DIG_CFG (0x1A) -#define PHY_LXT971_TX_CTRL (0x1E) - -/* PORT_CFG Port Configuration Register Bit Fields */ -#define PHY_LXT971_PORT_CFG_RES1 (0x8000) -#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) -#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000) -#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000) -#define PHY_LXT971_PORT_CFG_RES2 (0x0800) -#define PHY_LXT971_PORT_CFG_JABBER (0x0400) -#define PHY_LXT971_PORT_CFG_SQE (0x0200) -#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100) -#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080) -#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040) -#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020) -#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018) -#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010) -#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001) -#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000) -#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004) -#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002) -#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001) - -/* STAT2 Status Register #2 Bit Fields */ -#define PHY_LXT971_STAT2_RES1 (0x8000) -#define PHY_LXT971_STAT2_100BTX (0x4000) -#define PHY_LXT971_STAT2_TX_STATUS (0x2000) -#define PHY_LXT971_STAT2_RX_STATUS (0x1000) -#define PHY_LXT971_STAT2_COL_STATUS (0x0800) -#define PHY_LXT971_STAT2_LINK (0x0400) -#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200) -#define PHY_LXT971_STAT2_AUTO_NEG (0x0100) -#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080) -#define PHY_LXT971_STAT2_RES2 (0x0040) -#define PHY_LXT971_STAT2_POLARITY (0x0020) -#define PHY_LXT971_STAT2_PAUSE (0x0010) -#define PHY_LXT971_STAT2_ERROR (0x0008) -#define PHY_LXT971_STAT2_RES3 (0x0007) - -/* INT_ENABLE Interrupt Enable Register Bit Fields */ -#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00) -#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080) -#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040) -#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020) -#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010) -#define PHY_LXT971_INT_ENABLE_RES2 (0x000C) -#define PHY_LXT971_INT_ENABLE_INTEN (0x0002) -#define PHY_LXT971_INT_ENABLE_TINT (0x0001) - -/* INT_STATUS Interrupt Status Register Bit Fields */ -#define PHY_LXT971_INT_STATUS_RES1 (0xFF00) -#define PHY_LXT971_INT_STATUS_ANDONE (0x0080) -#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040) -#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020) -#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010) -#define PHY_LXT971_INT_STATUS_RES2 (0x0008) -#define PHY_LXT971_INT_STATUS_MDINT (0x0004) -#define PHY_LXT971_INT_STATUS_RES3 (0x0003) - -/* LED_CFG Interrupt LED Configuration Register Bit Fields */ -#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C) -#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008) -#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004) -#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C) -#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C) -#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008) -#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004) -#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000) -#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002) -#define PHY_LXT971_LED_CFG_RES1 (0x0001) - -/* only one of these values must be shifted for each SHIFT_LED? */ -#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F) -#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E) -#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D) -#define PHY_LXT971_LED_CFG_LINK_RX (0x000C) -#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B) -#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A) -#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009) -#define PHY_LXT971_LED_CFG_TEST_ON (0x0008) -#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007) -#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006) -#define PHY_LXT971_LED_CFG_DUPLEX (0x0005) -#define PHY_LXT971_LED_CFG_LINK (0x0004) -#define PHY_LXT971_LED_CFG_COLLISION (0x0003) -#define PHY_LXT971_LED_CFG_RECEIVE (0x0002) -#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001) -#define PHY_LXT971_LED_CFG_SPEED (0x0000) - -/* DIG_CFG Digitial Configuration Register Bit Fields */ -#define PHY_LXT971_DIG_CFG_RES1 (0xF000) -#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800) -#define PHY_LXT971_DIG_CFG_RES2 (0x0400) -#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200) -#define PHY_LXT971_DIG_CFG_RES3 (0x01FF) - -#define PHY_LXT971_MDIO_MAX_CLK (8000000) -#define PHY_MDIO_MAX_CLK (2500000) - -/* TX_CTRL Transmit Control Register Bit Fields - documentation is buggy for this register, therefore setting not included */ - -typedef enum -{ - PHY_NONE = 0x0000, /* no PHY detected yet */ - PHY_LXT971A = 0x0013 -} PhyType; - -#endif /* __LXT971A_H__ */ diff --git a/include/mc13783.h b/include/mc13783.h deleted file mode 100644 index c7ee03b0f9f..00000000000 --- a/include/mc13783.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - */ - - -#ifndef __MC13783_H__ -#define __MC13783_H__ - -/* REG_MODE_0 */ -#define VAUDIOEN (1 << 0) -#define VAUDIOSTBY (1 << 1) -#define VAUDIOMODE (1 << 2) -#define VIOHIEN (1 << 3) -#define VIOHISTBY (1 << 4) -#define VIOHIMODE (1 << 5) -#define VIOLOEN (1 << 6) -#define VIOLOSTBY (1 << 7) -#define VIOLOMODE (1 << 8) -#define VDIGEN (1 << 9) -#define VDIGSTBY (1 << 10) -#define VDIGMODE (1 << 11) -#define VGENEN (1 << 12) -#define VGENSTBY (1 << 13) -#define VGENMODE (1 << 14) -#define VRFDIGEN (1 << 15) -#define VRFDIGSTBY (1 << 16) -#define VRFDIGMODE (1 << 17) -#define VRFREFEN (1 << 18) -#define VRFREFSTBY (1 << 19) -#define VRFREFMODE (1 << 20) -#define VRFCPEN (1 << 21) -#define VRFCPSTBY (1 << 22) -#define VRFCPMODE (1 << 23) - -/* REG_MODE_1 */ -#define VSIMEN (1 << 0) -#define VSIMSTBY (1 << 1) -#define VSIMMODE (1 << 2) -#define VESIMEN (1 << 3) -#define VESIMSTBY (1 << 4) -#define VESIMMODE (1 << 5) -#define VCAMEN (1 << 6) -#define VCAMSTBY (1 << 7) -#define VCAMMODE (1 << 8) -#define VRFBGEN (1 << 9) -#define VRFBGSTBY (1 << 10) -#define VVIBEN (1 << 11) -#define VRF1EN (1 << 12) -#define VRF1STBY (1 << 13) -#define VRF1MODE (1 << 14) -#define VRF2EN (1 << 15) -#define VRF2STBY (1 << 16) -#define VRF2MODE (1 << 17) -#define VMMC1EN (1 << 18) -#define VMMC1STBY (1 << 19) -#define VMMC1MODE (1 << 20) -#define VMMC2EN (1 << 21) -#define VMMC2STBY (1 << 22) -#define VMMC2MODE (1 << 23) - -#endif diff --git a/include/mc34704.h b/include/mc34704.h deleted file mode 100644 index b837ddaa1d9..00000000000 --- a/include/mc34704.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __MC34704_H__ -#define __MC34704_H__ - -enum { - MC34704_RESERVED0_REG = 0, /* 0x00 */ - MC34704_GENERAL1_REG, /* 0x01 */ - MC34704_GENERAL2_REG, /* 0x02 */ - MC34704_GENERAL3_REG, /* 0x03 */ - MC34704_RESERVED4_REG, /* 0x04 */ - MC34704_VGSET2_REG, /* 0x05 */ - MC34704_REG2SET1_REG, /* 0x06 */ - MC34704_REG2SET2_REG, /* 0x07 */ - MC34704_REG3SET1_REG, /* 0x08 */ - MC34704_REG3SET2_REG, /* 0x09 */ - MC34704_REG4SET1_REG, /* 0x0a */ - MC34704_REG4SET2_REG, /* 0x0b */ - MC34704_REG5SET1_REG, /* 0x0c */ - MC34704_REG5SET2_REG, /* 0x0d */ - MC34704_REG5SET3_REG, /* 0x0e */ - MC34704_RESERVEDF_REG, /* 0x0f */ - MC34704_RESERVED10_REG, /* 0x10 */ - MC34704_RESERVED11_REG, /* 0x11 */ - MC34704_RESERVED12_REG, /* 0x12 */ - MC34704_FSW2SET_REG, /* 0x13 */ - MC34704_RESERVED14_REG, /* 0x14 */ - MC34704_REG8SET1_REG, /* 0x15 */ - MC34704_REG8SET2_REG, /* 0x16 */ - MC34704_REG8SET3_REG, /* 0x17 */ - MC34704_FAULTS_REG, /* 0x18 */ - MC34704_I2CSET1, /* 0x19 */ - MC34704_NUM_OF_REGS, -}; - -/* GENERAL2 register fields */ -#define ONOFFE (1 << 0) -#define ONOFFD (1 << 1) -#define ONOFFA (1 << 3) -#define ALLOFF (1 << 4) - -#endif /* __MC34704_H__ */ diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h deleted file mode 100644 index ffe376bf507..00000000000 --- a/include/mc9sdz60.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 Marc Kleine-Budde - * - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MC9SDZ60_H -#define __ASM_ARCH_MC9SDZ60_H - -/** - * Register addresses for the MC9SDZ60 - * - * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h - * but not include/linux/mfd/mc9s08dz60/pmic.h - * - */ -enum mc9sdz60_reg { - MC9SDZ60_REG_VERSION = 0x00, - /* reserved 0x01 */ - MC9SDZ60_REG_SECS = 0x02, - MC9SDZ60_REG_MINS = 0x03, - MC9SDZ60_REG_HRS = 0x04, - MC9SDZ60_REG_DAY = 0x05, - MC9SDZ60_REG_DATE = 0x06, - MC9SDZ60_REG_MONTH = 0x07, - MC9SDZ60_REG_YEAR = 0x08, - MC9SDZ60_REG_ALARM_SECS = 0x09, - MC9SDZ60_REG_ALARM_MINS = 0x0a, - MC9SDZ60_REG_ALARM_HRS = 0x0b, - /* reserved 0x0c */ - /* reserved 0x0d */ - MC9SDZ60_REG_TS_CONTROL = 0x0e, - MC9SDZ60_REG_X_LOW = 0x0f, - MC9SDZ60_REG_Y_LOW = 0x10, - MC9SDZ60_REG_XY_HIGH = 0x11, - MC9SDZ60_REG_X_LEFT_LOW = 0x12, - MC9SDZ60_REG_X_LEFT_HIGH = 0x13, - MC9SDZ60_REG_X_RIGHT = 0x14, - MC9SDZ60_REG_Y_TOP_LOW = 0x15, - MC9SDZ60_REG_Y_TOP_HIGH = 0x16, - MC9SDZ60_REG_Y_BOTTOM = 0x17, - /* reserved 0x18 */ - /* reserved 0x19 */ - MC9SDZ60_REG_RESET_1 = 0x1a, - MC9SDZ60_REG_RESET_2 = 0x1b, - MC9SDZ60_REG_POWER_CTL = 0x1c, - MC9SDZ60_REG_DELAY_CONFIG = 0x1d, - /* reserved 0x1e */ - /* reserved 0x1f */ - MC9SDZ60_REG_GPIO_1 = 0x20, - MC9SDZ60_REG_GPIO_2 = 0x21, - MC9SDZ60_REG_KPD_1 = 0x22, - MC9SDZ60_REG_KPD_2 = 0x23, - MC9SDZ60_REG_KPD_CONTROL = 0x24, - MC9SDZ60_REG_INT_ENABLE_1 = 0x25, - MC9SDZ60_REG_INT_ENABLE_2 = 0x26, - MC9SDZ60_REG_INT_FLAG_1 = 0x27, - MC9SDZ60_REG_INT_FLAG_2 = 0x28, - MC9SDZ60_REG_DES_FLAG = 0x29, -}; - -extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg); -extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val); - -#endif /* __ASM_ARCH_MC9SDZ60_H */ diff --git a/include/mii_phy.h b/include/mii_phy.h deleted file mode 100644 index f0d3e628231..00000000000 --- a/include/mii_phy.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _MII_PHY_H_ -#define _MII_PHY_H_ - -void mii_discover_phy(void); -unsigned short mii_phy_read(unsigned short reg); -void mii_phy_write(unsigned short reg, unsigned short val); - -#endif diff --git a/include/mk48t59.h b/include/mk48t59.h deleted file mode 100644 index f95d349c17f..00000000000 --- a/include/mk48t59.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - */ - -/* - * Date & Time support for the MK48T59 RTC - */ - - -#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE) - -#define RTC_PORT_ADDR0 0x70 -#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 -#define RTC_PORT_DATA 0x76 - -/* RTC Offsets */ -#define RTC_SECONDS 0x1FF9 -#define RTC_MINUTES 0x1FFA -#define RTC_HOURS 0x1FFB -#define RTC_DAY_OF_WEEK 0x1FFC -#define RTC_DAY_OF_MONTH 0x1FFD -#define RTC_MONTH 0x1FFE -#define RTC_YEAR 0x1FFF - -#define RTC_CONTROLA 0x1FF8 -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 -#define RTC_CA_CALIB_SIGN 0x20 -#define RTC_CA_CALIB_MASK 0x1f - -#define RTC_CONTROLB 0x1FF9 -#define RTC_CB_STOP 0x80 - -#define RTC_WATCHDOG 0x1FF7 -#define RTC_WDS 0x80 -#define RTC_WD_RB_16TH 0x0 -#define RTC_WD_RB_4TH 0x1 -#define RTC_WD_RB_1 0x2 -#define RTC_WD_RB_4 0x3 - -void rtc_set_watchdog(short multi, short res); -void *nvram_read(void *dest, const short src, size_t count); -void nvram_write(short dest, const void *src, size_t count); - -#endif diff --git a/include/mpc106.h b/include/mpc106.h deleted file mode 100644 index 2157b32407a..00000000000 --- a/include/mpc106.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - */ - -#ifndef _MPC106_PCI_H -#define _MPC106_PCI_H - -/* - * Defines for the MPC106 PCI Config address and data registers followed by - * defines for the standard PCI device configuration header. - */ -#define PCIDEVID_MPC106 0x0 - -/* - * MPC106 Registers - */ -#define MPC106_REG 0x80000000 - -#ifdef CONFIG_SYS_ADDRESS_MAP_A -#define MPC106_REG_ADDR 0x80000cf8 -#define MPC106_REG_DATA 0x80000cfc -#define MPC106_ISA_IO_PHYS 0x80000000 -#define MPC106_ISA_IO_BUS 0x00000000 -#define MPC106_ISA_IO_SIZE 0x00800000 -#define MPC106_PCI_IO_PHYS 0x81000000 -#define MPC106_PCI_IO_BUS 0x01000000 -#define MPC106_PCI_IO_SIZE 0x3e800000 -#define MPC106_PCI_MEM_PHYS 0xc0000000 -#define MPC106_PCI_MEM_BUS 0x00000000 -#define MPC106_PCI_MEM_SIZE 0x3f000000 -#define MPC106_PCI_MEMORY_PHYS 0x00000000 -#define MPC106_PCI_MEMORY_BUS 0x80000000 -#define MPC106_PCI_MEMORY_SIZE 0x80000000 -#else -#define MPC106_REG_ADDR 0xfec00cf8 -#define MPC106_REG_DATA 0xfee00cfc -#define MPC106_ISA_MEM_PHYS 0xfd000000 -#define MPC106_ISA_MEM_BUS 0x00000000 -#define MPC106_ISA_MEM_SIZE 0x01000000 -#define MPC106_ISA_IO_PHYS 0xfe000000 -#define MPC106_ISA_IO_BUS 0x00000000 -#define MPC106_ISA_IO_SIZE 0x00800000 -#define MPC106_PCI_IO_PHYS 0xfe800000 -#define MPC106_PCI_IO_BUS 0x00800000 -#define MPC106_PCI_IO_SIZE 0x00400000 -#define MPC106_PCI_MEM_PHYS 0x80000000 -#define MPC106_PCI_MEM_BUS 0x80000000 -#define MPC106_PCI_MEM_SIZE 0x7d000000 -#define MPC106_PCI_MEMORY_PHYS 0x00000000 -#define MPC106_PCI_MEMORY_BUS 0x00000000 -#define MPC106_PCI_MEMORY_SIZE 0x40000000 -#endif - -#define CMD_SERR 0x0100 -#define PCI_CMD_MASTER 0x0004 -#define PCI_CMD_MEMEN 0x0002 -#define PCI_CMD_IOEN 0x0001 - -#define PCI_STAT_NO_RSV_BITS 0xffff - -#define PCI_BUSNUM 0x40 -#define PCI_SUBBUSNUM 0x41 -#define PCI_DISCOUNT 0x42 - -#define PCI_PICR1 0xA8 -#define PICR1_CF_CBA(value) ((value & 0xff) << 24) -#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) -#define PICR1_PROC_TYPE_603 0x40000 -#define PICR1_PROC_TYPE_604 0x60000 -#define PICR1_MCP_EN 0x800 -#define PICR1_CF_DPARK 0x200 -#define PICR1_CF_LOOP_SNOOP 0x10 -#define PICR1_CF_L2_COPY_BACK 0x2 -#define PICR1_CF_L2_CACHE_MASK 0x3 -#define PICR1_CF_APARK 0x8 -#define PICR1_ADDRESS_MAP 0x10000 -#define PICR1_XIO_MODE 0x80000 -#define PICR1_CF_CACHE_1G 0x200000 - -#define PCI_PICR2 0xAC -#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) -#define PICR2_CF_FLUSH_L2 0x10000000 -#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) -#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) -#define PICR2_CF_INV_MODE 0x00001000 -#define PICR2_CF_MOD_HIGH 0x00020000 -#define PICR2_CF_HIT_HIGH 0x00010000 -#define PICR2_L2_SIZE_256K 0x00000000 -#define PICR2_L2_SIZE_512K 0x00000010 -#define PICR2_L2_SIZE_1MB 0x00000020 -#define PICR2_L2_EN 0x40000000 -#define PICR2_L2_UPDATE_EN 0x80000000 -#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 -#define PICR2_CF_FAST_CASTOUT 0x00000080 -#define PICR2_CF_WDATA 0x00000001 -#define PICR2_CF_DATA_RAM_PBURST 0x00400000 - -/* - * Memory controller - */ -#define MPC106_MCCR1 0xF0 -#define MCCR1_TYPE_EDO 0x00020000 -#define MCCR1_BK0_9BITS 0x0 -#define MCCR1_BK0_10BITS 0x1 -#define MCCR1_BK0_11BITS 0x2 -#define MCCR1_BK0_12BITS 0x3 -#define MCCR1_BK1_9BITS 0x0 -#define MCCR1_BK1_10BITS 0x4 -#define MCCR1_BK1_11BITS 0x8 -#define MCCR1_BK1_12BITS 0xC -#define MCCR1_BK2_9BITS 0x00 -#define MCCR1_BK2_10BITS 0x10 -#define MCCR1_BK2_11BITS 0x20 -#define MCCR1_BK2_12BITS 0x30 -#define MCCR1_BK3_9BITS 0x00 -#define MCCR1_BK3_10BITS 0x40 -#define MCCR1_BK3_11BITS 0x80 -#define MCCR1_BK3_12BITS 0xC0 -#define MCCR1_MEMGO 0x00080000 - -#define MPC106_MCCR2 0xF4 -#define MPC106_MCCR3 0xF8 -#define MPC106_MCCR4 0xFC - -#define MPC106_MSAR1 0x80 -#define MPC106_EMSAR1 0x88 -#define MPC106_EMSAR2 0x8C -#define MPC106_MEAR1 0x90 -#define MPC106_EMEAR1 0x98 -#define MPC106_EMEAR2 0x9C - -#define MPC106_MBER 0xA0 -#define MBER_BANK0 0x1 -#define MBER_BANK1 0x2 -#define MBER_BANK2 0x4 -#define MBER_BANK3 0x8 - -#endif diff --git a/include/mpc86xx.h b/include/mpc86xx.h deleted file mode 100644 index ea8d17d557e..00000000000 --- a/include/mpc86xx.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor. - * Jeffrey Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -#ifndef __MPC86xx_H__ -#define __MPC86xx_H__ - -#include - -#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/* - * platform register addresses - */ - -#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008) - -/* - * l2cr values. Look in config_.h for the actual setup - */ -#define l2cr 1017 - -#define L2CR_L2E 0x80000000 /* bit 0 - enable */ -#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ -#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ -#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ -#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ -#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ -#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ -#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ - -#define HID0_XBSEN 0x00000100 -#define HID0_HIGH_BAT_EN 0x00800000 -#define HID0_XAEN 0x00020000 - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long freq_processor; - unsigned long freq_systembus; - unsigned long freq_localbus; -} MPC86xx_SYS_INFO; - -#define l1icache_enable icache_enable - -void l2cache_enable(void); -void l1dcache_enable(void); - -static __inline__ unsigned long get_hid0 (void) -{ - unsigned long hid0; - asm volatile("mfspr %0, 1008" : "=r" (hid0) :); - return hid0; -} - -static __inline__ unsigned long get_hid1 (void) -{ - unsigned long hid1; - asm volatile("mfspr %0, 1009" : "=r" (hid1) :); - return hid1; -} - -static __inline__ void set_hid0 (unsigned long hid0) -{ - asm volatile("mtspr 1008, %0" : : "r" (hid0)); -} - -static __inline__ void set_hid1 (unsigned long hid1) -{ - asm volatile("mtspr 1009, %0" : : "r" (hid1)); -} - - -static __inline__ unsigned long get_l2cr (void) -{ - unsigned long l2cr_val; - asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); - return l2cr_val; -} - -void setup_ddr_bat(phys_addr_t dram_size); -extern void setup_bats(void); - -#endif /* _ASMLANGUAGE */ -#endif /* __MPC86xx_H__ */ diff --git a/include/mvmfp.h b/include/mvmfp.h deleted file mode 100644 index de86ffd5e2d..00000000000 --- a/include/mvmfp.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef __MVMFP_H -#define __MVMFP_H - -/* - * Header file for MultiFunctionPin (MFP) Configururation framework - * - * Processors Supported: - * 1. Marvell ARMADA100 Processors - * - * processor to be supported should be added here - */ - -/* - * MFP configuration is represented by a 32-bit unsigned integer - */ -#ifdef CONFIG_MVMFP_V2 -#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ - /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ - /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ - /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ - /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ - /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ - /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ - /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) -#else -#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ - /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ - /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ - /* bit 12 - Unused */ \ - /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ - /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ - /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ - /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) -#endif - -/* - * to facilitate the definition, the following macros are provided - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) -#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) -#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) - -#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) -#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) -#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) -#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) -#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) -#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) -#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) -#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) - -#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) -#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) -#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) -#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) -#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) - -#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) -#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) -#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) -#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) -#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) - -#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) - -#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) -#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) -#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) -#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) - -#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) -#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) -#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) -#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) -#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) - -#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ - | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ - | MFP_AF_MASK) -#define MFP_EOC 0xffffffff /* indicates end-of-conf */ - -/* Functions */ -void mfp_config(u32 *mfp_cfgs); - -#endif /* __MVMFP_H */ diff --git a/include/pca9564.h b/include/pca9564.h deleted file mode 100644 index 99e8bcd9adb..00000000000 --- a/include/pca9564.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * File: include/pca9564.h - * Author: - * - * Created: 2009-06-23 - * Description: PCA9564 i2c bridge driver - * - * Modified: - * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ - * - * Bugs: - */ - -#ifndef _PCA9564_H -#define _PCA9564_H - -/* Clock speeds for the bus */ -#define PCA_CON_330kHz 0x00 -#define PCA_CON_288kHz 0x01 -#define PCA_CON_217kHz 0x02 -#define PCA_CON_146kHz 0x03 -#define PCA_CON_88kHz 0x04 -#define PCA_CON_59kHz 0x05 -#define PCA_CON_44kHz 0x06 -#define PCA_CON_36kHz 0x07 - -#define PCA_CON_AA 0x80 /* Assert Acknowledge */ -#define PCA_CON_ENSIO 0x40 /* Enable */ -#define PCA_CON_STA 0x20 /* Start */ -#define PCA_CON_STO 0x10 /* Stop */ -#define PCA_CON_SI 0x08 /* Serial Interrupt */ -#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */ - -#endif diff --git a/include/sja1000.h b/include/sja1000.h deleted file mode 100644 index 6ceb6f4d48f..00000000000 --- a/include/sja1000.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009, Matthias Fuchs - * - * SJA1000 register layout for basic CAN mode - */ - -#ifndef _SJA1000_H_ -#define _SJA1000_H_ - -/* - * SJA1000 register layout in basic can mode - */ -struct sja1000_basic_s { - u8 cr; - u8 cmr; - u8 sr; - u8 ir; - u8 ac; - u8 am; - u8 btr0; - u8 btr1; - u8 oc; - u8 txb[10]; - u8 rxb[10]; - u8 unused; - u8 cdr; -}; - -/* control register */ -#define CR_RR 0x01 - -/* output control register */ -#define OC_MODE0 0x01 -#define OC_MODE1 0x02 -#define OC_POL0 0x04 -#define OC_TN0 0x08 -#define OC_TP0 0x10 -#define OC_POL1 0x20 -#define OC_TN1 0x40 -#define OC_TP1 0x80 - -#endif diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h deleted file mode 100644 index 7628c33195d..00000000000 --- a/include/sym53c8xx.h +++ /dev/null @@ -1,552 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * Most of these definitions are derived from - * linux/drivers/scsi/sym53c8xx_defs.h - */ - -#ifndef _SYM53C8XX_DEFS_H -#define _SYM53C8XX_DEFS_H - - -#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ - -#define SCNTL1 0x01 /* no reset */ - #define ISCON 0x10 /* connected to scsi */ - #define CRST 0x08 /* force reset */ - #define IARB 0x02 /* immediate arbitration */ - -#define SCNTL2 0x02 /* no disconnect expected */ - #define SDU 0x80 /* cmd: disconnect will raise error */ - #define CHM 0x40 /* sta: chained mode */ - #define WSS 0x08 /* sta: wide scsi send [W]*/ - #define WSR 0x01 /* sta: wide scsi received [W]*/ - -#define SCNTL3 0x03 /* cnf system clock dependent */ - #define EWS 0x08 /* cmd: enable wide scsi [W]*/ - #define ULTRA 0x80 /* cmd: ULTRA enable */ - /* bits 0-2, 7 rsvd for C1010 */ - -#define SCID 0x04 /* cnf host adapter scsi address */ - #define RRE 0x40 /* r/w:e enable response to resel. */ - #define SRE 0x20 /* r/w:e enable response to select */ - -#define SXFER 0x05 /* ### Sync speed and count */ - /* bits 6-7 rsvd for C1010 */ - -#define SDID 0x06 /* ### Destination-ID */ - -#define GPREG 0x07 /* ??? IO-Pins */ - -#define SFBR 0x08 /* ### First byte in phase */ - -#define SOCL 0x09 - #define CREQ 0x80 /* r/w: SCSI-REQ */ - #define CACK 0x40 /* r/w: SCSI-ACK */ - #define CBSY 0x20 /* r/w: SCSI-BSY */ - #define CSEL 0x10 /* r/w: SCSI-SEL */ - #define CATN 0x08 /* r/w: SCSI-ATN */ - #define CMSG 0x04 /* r/w: SCSI-MSG */ - #define CC_D 0x02 /* r/w: SCSI-C_D */ - #define CI_O 0x01 /* r/w: SCSI-I_O */ - -#define SSID 0x0a - -#define SBCL 0x0b - -#define DSTAT 0x0c - #define DFE 0x80 /* sta: dma fifo empty */ - #define MDPE 0x40 /* int: master data parity error */ - #define BF 0x20 /* int: script: bus fault */ - #define ABRT 0x10 /* int: script: command aborted */ - #define SSI 0x08 /* int: script: single step */ - #define SIR 0x04 /* int: script: interrupt instruct. */ - #define IID 0x01 /* int: script: illegal instruct. */ - -#define SSTAT0 0x0d - #define ILF 0x80 /* sta: data in SIDL register lsb */ - #define ORF 0x40 /* sta: data in SODR register lsb */ - #define OLF 0x20 /* sta: data in SODL register lsb */ - #define AIP 0x10 /* sta: arbitration in progress */ - #define LOA 0x08 /* sta: arbitration lost */ - #define WOA 0x04 /* sta: arbitration won */ - #define IRST 0x02 /* sta: scsi reset signal */ - #define SDP 0x01 /* sta: scsi parity signal */ - -#define SSTAT1 0x0e - #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ - -#define SSTAT2 0x0f - #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ - #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ - #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ - #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ - #define LDSC 0x02 /* sta: disconnect & reconnect */ - -#define DSA 0x10 /* --> Base page */ -#define DSA1 0x11 -#define DSA2 0x12 -#define DSA3 0x13 - -#define ISTAT 0x14 /* --> Main Command and status */ - #define CABRT 0x80 /* cmd: abort current operation */ - #define SRST 0x40 /* mod: reset chip */ - #define SIGP 0x20 /* r/w: message from host to ncr */ - #define SEM 0x10 /* r/w: message between host + ncr */ - #define CON 0x08 /* sta: connected to scsi */ - #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ - #define SIP 0x02 /* sta: scsi-interrupt */ - #define DIP 0x01 /* sta: host/script interrupt */ - - -#define CTEST0 0x18 -#define CTEST1 0x19 -#define CTEST2 0x1a - #define CSIGP 0x40 - /* bits 0-2,7 rsvd for C1010 */ - -#define CTEST3 0x1b - #define FLF 0x08 /* cmd: flush dma fifo */ - #define CLF 0x04 /* cmd: clear dma fifo */ - #define FM 0x02 /* mod: fetch pin mode */ - #define WRIE 0x01 /* mod: write and invalidate enable */ - /* bits 4-7 rsvd for C1010 */ - -#define DFIFO 0x20 -#define CTEST4 0x21 - #define BDIS 0x80 /* mod: burst disable */ - #define MPEE 0x08 /* mod: master parity error enable */ - -#define CTEST5 0x22 - #define DFS 0x20 /* mod: dma fifo size */ - /* bits 0-1, 3-7 rsvd for C1010 */ -#define CTEST6 0x23 - -#define DBC 0x24 /* ### Byte count and command */ -#define DNAD 0x28 /* ### Next command register */ -#define DSP 0x2c /* --> Script Pointer */ -#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ - -#define SCRATCHA 0x34 /* Temporary register a */ -#define SCRATCHA1 0x35 -#define SCRATCHA2 0x36 -#define SCRATCHA3 0x37 - -#define DMODE 0x38 - #define BL_2 0x80 /* mod: burst length shift value +2 */ - #define BL_1 0x40 /* mod: burst length shift value +1 */ - #define ERL 0x08 /* mod: enable read line */ - #define ERMP 0x04 /* mod: enable read multiple */ - #define BOF 0x02 /* mod: burst op code fetch */ - #define MAN 0x01 /* mod: manual start */ - -#define DIEN 0x39 -#define SBR 0x3a - -#define DCNTL 0x3b /* --> Script execution control */ - #define CLSE 0x80 /* mod: cache line size enable */ - #define PFF 0x40 /* cmd: pre-fetch flush */ - #define PFEN 0x20 /* mod: pre-fetch enable */ - #define SSM 0x10 /* mod: single step mode */ - #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ - #define STD 0x04 /* cmd: start dma mode */ - #define IRQD 0x02 /* mod: irq disable */ - #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ - /* bits 0-1 rsvd for C1010 */ - -#define ADDER 0x3c - -#define SIEN 0x40 /* -->: interrupt enable */ -#define SIST 0x42 /* <--: interrupt status */ - #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ - #define STO 0x0400/* sta: timeout (select) */ - #define GEN 0x0200/* sta: timeout (general) */ - #define HTH 0x0100/* sta: timeout (handshake) */ - #define MA 0x80 /* sta: phase mismatch */ - #define CMP 0x40 /* sta: arbitration complete */ - #define SEL 0x20 /* sta: selected by another device */ - #define RSL 0x10 /* sta: reselected by another device*/ - #define SGE 0x08 /* sta: gross error (over/underflow)*/ - #define UDC 0x04 /* sta: unexpected disconnect */ - #define RST 0x02 /* sta: scsi bus reset detected */ - #define PAR 0x01 /* sta: scsi parity error */ - -#define SLPAR 0x44 -#define SWIDE 0x45 -#define MACNTL 0x46 -#define GPCNTL 0x47 -#define STIME0 0x48 /* cmd: timeout for select&handshake*/ -#define STIME1 0x49 /* cmd: timeout user defined */ -#define RESPID 0x4a /* sta: Reselect-IDs */ - -#define STEST0 0x4c - -#define STEST1 0x4d - #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ - #define DBLEN 0x08 /* clock doubler running */ - #define DBLSEL 0x04 /* clock doubler selected */ - - -#define STEST2 0x4e - #define ROF 0x40 /* reset scsi offset (after gross error!) */ - #define EXT 0x02 /* extended filtering */ - -#define STEST3 0x4f - #define TE 0x80 /* c: tolerAnt enable */ - #define HSC 0x20 /* c: Halt SCSI Clock */ - #define CSF 0x02 /* c: clear scsi fifo */ - -#define SIDL 0x50 /* Lowlevel: latched from scsi data */ -#define STEST4 0x52 - #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ - #define SMODE_HVD 0x40 /* High Voltage Differential */ - #define SMODE_SE 0x80 /* Single Ended */ - #define SMODE_LVD 0xc0 /* Low Voltage Differential */ - #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ - /* bits 0-5 rsvd for C1010 */ - -#define SODL 0x54 /* Lowlevel: data out to scsi data */ - -#define SBDL 0x58 /* Lowlevel: data from scsi data */ - - -/*----------------------------------------------------------- -** -** Utility macros for the script. -** -**----------------------------------------------------------- -*/ - -#define REG(r) (r) - -/*----------------------------------------------------------- -** -** SCSI phases -** -** DT phases illegal for ncr driver. -** -**----------------------------------------------------------- -*/ - -#define SCR_DATA_OUT 0x00000000 -#define SCR_DATA_IN 0x01000000 -#define SCR_COMMAND 0x02000000 -#define SCR_STATUS 0x03000000 -#define SCR_DT_DATA_OUT 0x04000000 -#define SCR_DT_DATA_IN 0x05000000 -#define SCR_MSG_OUT 0x06000000 -#define SCR_MSG_IN 0x07000000 - -#define SCR_ILG_OUT 0x04000000 -#define SCR_ILG_IN 0x05000000 - -/*----------------------------------------------------------- -** -** Data transfer via SCSI. -** -**----------------------------------------------------------- -** -** MOVE_ABS (LEN) -** <> -** -** MOVE_IND (LEN) -** <> -** -** MOVE_TBL -** <> -** -**----------------------------------------------------------- -*/ - -#define OPC_MOVE 0x08000000 - -#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) - -#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) -#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) -#define SCR_CHMOV_TBL (0x10000000) - - -/*----------------------------------------------------------- -** -** Selection -** -**----------------------------------------------------------- -** -** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] -** <> -** -** SEL_TBL | << dnad_offset>> [ | REL_JMP] -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_SEL_ABS 0x40000000 -#define SCR_SEL_ABS_ATN 0x41000000 -#define SCR_SEL_TBL 0x42000000 -#define SCR_SEL_TBL_ATN 0x43000000 - - -#define SCR_JMP_REL 0x04000000 -#define SCR_ID(id) (((unsigned long)(id)) << 16) - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** WAIT_DISC -** dummy: <> -** -** WAIT_RESEL -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_WAIT_DISC 0x48000000 -#define SCR_WAIT_RESEL 0x50000000 - -/*----------------------------------------------------------- -** -** Bit Set / Reset -** -**----------------------------------------------------------- -** -** SET (flags {|.. }) -** -** CLR (flags {|.. }) -** -**----------------------------------------------------------- -*/ - -#define SCR_SET(f) (0x58000000 | (f)) -#define SCR_CLR(f) (0x60000000 | (f)) - -#define SCR_CARRY 0x00000400 -#define SCR_TRG 0x00000200 -#define SCR_ACK 0x00000040 -#define SCR_ATN 0x00000008 - - -/*----------------------------------------------------------- -** -** Memory to memory move -** -**----------------------------------------------------------- -** -** COPY (bytecount) -** << source_address >> -** << destination_address >> -** -** SCR_COPY sets the NO FLUSH option by default. -** SCR_COPY_F does not set this option. -** -** For chips which do not support this option, -** ncr_copy_and_bind() will remove this bit. -**----------------------------------------------------------- -*/ - -#define SCR_NO_FLUSH 0x01000000 - -#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) -#define SCR_COPY_F(n) (0xc0000000 | (n)) - -/*----------------------------------------------------------- -** -** Register move and binary operations -** -**----------------------------------------------------------- -** -** SFBR_REG (reg, op, data) reg = SFBR op data -** << 0 >> -** -** REG_SFBR (reg, op, data) SFBR = reg op data -** << 0 >> -** -** REG_REG (reg, op, data) reg = reg op data -** << 0 >> -** -**----------------------------------------------------------- -** On 810A, 860, 825A, 875, 895 and 896 chips the content -** of SFBR register can be used as data (SCR_SFBR_DATA). -** The 896 has additionnal IO registers starting at -** offset 0x80. Bit 7 of register offset is stored in -** bit 7 of the SCRIPTS instruction first DWORD. -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ - -#define SCR_SFBR_REG(reg,op,data) \ - (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_SFBR(reg,op,data) \ - (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_REG(reg,op,data) \ - (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - - -#define SCR_LOAD 0x00000000 -#define SCR_SHL 0x01000000 -#define SCR_OR 0x02000000 -#define SCR_XOR 0x03000000 -#define SCR_AND 0x04000000 -#define SCR_SHR 0x05000000 -#define SCR_ADD 0x06000000 -#define SCR_ADDC 0x07000000 - -#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ - -/*----------------------------------------------------------- -** -** FROM_REG (reg) SFBR = reg -** << 0 >> -** -** TO_REG (reg) reg = SFBR -** << 0 >> -** -** LOAD_REG (reg, data) reg = -** << 0 >> -** -** LOAD_SFBR(data) SFBR = -** << 0 >> -** -**----------------------------------------------------------- -*/ - -#define SCR_FROM_REG(reg) \ - SCR_REG_SFBR(reg,SCR_OR,0) - -#define SCR_TO_REG(reg) \ - SCR_SFBR_REG(reg,SCR_OR,0) - -#define SCR_LOAD_REG(reg,data) \ - SCR_REG_REG(reg,SCR_LOAD,data) - -#define SCR_LOAD_SFBR(data) \ - (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) - -/*----------------------------------------------------------- -** -** LOAD from memory to register. -** STORE from register to memory. -** -** Only supported by 810A, 860, 825A, 875, 895 and 896. -** -**----------------------------------------------------------- -** -** LOAD_ABS (LEN) -** <> -** -** LOAD_REL (LEN) (DSA relative) -** <> -** -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) -#define SCR_NO_FLUSH2 0x02000000 -#define SCR_DSA_REL2 0x10000000 - -#define SCR_LOAD_R(reg, how, n) \ - (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_STORE_R(reg, how, n) \ - (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) -#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) -#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) -#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) - -#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) -#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) -#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) -#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) - - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** JUMP [ | IFTRUE/IFFALSE ( ... ) ] -** <
> -** -** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** CALL [ | IFTRUE/IFFALSE ( ... ) ] -** <
> -** -** CALLR [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** RETURN [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** INT [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] -** <> -** -** Conditions: -** WHEN (phase) -** IF (phase) -** CARRYSET -** DATA (data, mask) -** -**----------------------------------------------------------- -*/ - -#define SCR_NO_OP 0x80000000 -#define SCR_JUMP 0x80080000 -#define SCR_JUMP64 0x80480000 -#define SCR_JUMPR 0x80880000 -#define SCR_CALL 0x88080000 -#define SCR_CALLR 0x88880000 -#define SCR_RETURN 0x90080000 -#define SCR_INT 0x98080000 -#define SCR_INT_FLY 0x98180000 - -#define IFFALSE(arg) (0x00080000 | (arg)) -#define IFTRUE(arg) (0x00000000 | (arg)) - -#define WHEN(phase) (0x00030000 | (phase)) -#define IF(phase) (0x00020000 | (phase)) - -#define DATA(D) (0x00040000 | ((D) & 0xff)) -#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) - -#define CARRYSET (0x00200000) - - -#define SIR_COMPLETE 0x10000000 -/* script errors */ -#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 -#define SIR_CMD_OUT_ILL_PH 0x00000002 -#define SIR_STATUS_ILL_PH 0x00000003 -#define SIR_MSG_RECEIVED 0x00000004 -#define SIR_DATA_IN_ERR 0x00000005 -#define SIR_DATA_OUT_ERR 0x00000006 -#define SIR_SCRIPT_ERROR 0x00000007 -#define SIR_MSG_OUT_NO_CMD 0x00000008 -#define SIR_MSG_OVER7 0x00000009 -/* Fly interrupt */ -#define INT_ON_FY 0x00000080 - -/* Hardware errors are defined in scsi.h */ - -#define SCSI_IDENTIFY 0xC0 - -#endif diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h deleted file mode 100644 index 6bb5cff3056..00000000000 --- a/include/synopsys/dwcddr21mctl.h +++ /dev/null @@ -1,324 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin - */ - -/* - * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller - */ -#ifndef __DWCDDR21MCTL_H -#define __DWCDDR21MCTL_H - -#ifndef __ASSEMBLY__ -struct dwcddr21mctl { - unsigned int ccr; /* Controller Configuration */ - unsigned int dcr; /* DRAM Configuration */ - unsigned int iocr; /* I/O Configuration */ - unsigned int csr; /* Controller Status */ - unsigned int drr; /* DRAM refresh */ - unsigned int tpr0; /* SDRAM Timing Parameters 0 */ - unsigned int tpr1; /* SDRAM Timing Parameters 1 */ - unsigned int tpr2; /* SDRAM Timing Parameters 2 */ - unsigned int gdllcr; /* Global DLL Control */ - unsigned int dllcr[10]; /* DLL Control */ - unsigned int rslr[4]; /* Rank System Lantency */ - unsigned int rdgr[4]; /* Rank DQS Gating */ - unsigned int dqtr[9]; /* DQ Timing */ - unsigned int dqstr; /* DQS Timing */ - unsigned int dqsbtr; /* DQS_b Timing */ - unsigned int odtcr; /* ODT Configuration */ - unsigned int dtr[2]; /* Data Training */ - unsigned int dtar; /* Data Training Address */ - unsigned int rsved[82]; /* Reserved */ - unsigned int mr; /* Mode Register */ - unsigned int emr; /* Extended Mode Register */ - unsigned int emr2; /* Extended Mode Register 2 */ - unsigned int emr3; /* Extended Mode Register 3 */ - unsigned int hpcr[32]; /* Host Port Configurarion */ - unsigned int pqcr[8]; /* Priority Queue Configuration */ - unsigned int mmgcr; /* Memory Manager General Config */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Control Configuration Register - */ -#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) -#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) -#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) -#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) -#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) -#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) -#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) -#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) -#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) -#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) -#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28) -#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) -#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) -#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) - -/* - * DRAM Configuration Register - */ -#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) -#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1) -#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) -#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12) -#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13) -#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25) -#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27) -#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31) - -/* - * I/O Configuration Register - */ -#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8) -#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26) -#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29) -#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30) -#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31) - -/* - * Controller Status Register - */ -#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0) -#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18) -#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19) -#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20) -#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21) -#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22) - -/* - * DRAM Refresh Register - */ -#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0) -#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8) -#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 0 - */ -#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2) -#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5) -#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16) -#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21) -#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25) -#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 1 - */ -#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2) -#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3) -#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14) -#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23) -#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27) -#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 2 - */ -#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0) -#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10) -#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15) - -/* - * Global DLL Control Register - */ -#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2) -#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5) -#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9) -#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11) -#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12) -#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20) -#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29) - -/* - * DLL Control Register 0-9 - */ -#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14) -#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18) -#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19) -#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31) - -/* - * Rank System Lantency Register - */ -#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24) - -/* - * Rank DQS Gating Register - */ -#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2) -#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4) -#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6) -#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8) -#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14) -#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16) - -/* - * DQ Timing Register - */ -#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16) -#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20) -#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28) - -/* - * DQS Timing Register - */ -#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24) - -/* - * DQS_b (DQSBTR) Timing Register - */ -#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24) - -/* - * ODT Configuration Register - */ -#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16) -#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20) -#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28) - -/* - * Data Training Register - */ -#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */ -#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */ -#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */ -#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */ - -#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */ -#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */ -#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */ -#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */ - -/* - * Data Training Address Register - */ -#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0) -#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12) -#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28) - -/* - * Mode Register - */ -#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_MR_BT(x) ((x) << 3) -#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4) -#define DWCDDR21MCTL_MR_TM(x) ((x) << 7) -#define DWCDDR21MCTL_MR_DR(x) ((x) << 8) -#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_MR_PD(x) ((x) << 12) - -/* - * Extended Mode register - */ -#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0) -#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1) -#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2) -#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6) -#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7) -#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10) -#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11) -#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12) - -#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x) -#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x) - -#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0)) -#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1)) -#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0)) -#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1)) - -/* - * Extended Mode register 2 - */ -#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3) -#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7) - -/* - * Extended Mode register 3: [15:0] reserved for JEDEC. - */ - -/* - * Host port Configuration register 0-31 - */ -#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0) - -/* - * Priority Queue Configuration register 0-7 - */ -#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8) -#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12) -#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20) -#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25) -#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28) - -/* - * Memory Manager General Configuration register - */ -#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0) - -#endif /* __DWCDDR21MCTL_H */ diff --git a/include/video_easylogo.h b/include/video_easylogo.h deleted file mode 100644 index ce93868da0e..00000000000 --- a/include/video_easylogo.h +++ /dev/null @@ -1,26 +0,0 @@ -/* -** video easylogo -** ============== -** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) -** AIRVENT SAM s.p.a - RIMINI(ITALY) -** -** This utility is still under construction! -*/ - -#ifndef _EASYLOGO_H_ -#define _EASYLOGO_H_ - -#if 0 -#define ENABLE_ASCII_BANNERS -#endif - -typedef struct { - unsigned char *data; - int width; - int height; - int bpp; - int pixel_size; - int size; -} fastimage_t ; - -#endif /* _EASYLOGO_H_ */ -- cgit v1.3.1 From 51bcd02dceca12a5ff2c215bbae8c4ec8ac88b87 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Mon, 22 May 2023 14:22:37 +0200 Subject: linux/unaligned: remove unused access_ok.h linux/unaligned/access_ok.h is unused, so remove it. Signed-off-by: Jens Wiklander Reviewed-by: Ilias Apalodimas --- include/linux/unaligned/access_ok.h | 66 ------------------------------------- 1 file changed, 66 deletions(-) delete mode 100644 include/linux/unaligned/access_ok.h (limited to 'include') diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h deleted file mode 100644 index 5f46eee23c3..00000000000 --- a/include/linux/unaligned/access_ok.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _LINUX_UNALIGNED_ACCESS_OK_H -#define _LINUX_UNALIGNED_ACCESS_OK_H - -#include - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpup((__le16 *)p); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpup((__le32 *)p); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpup((__le64 *)p); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpup((__be16 *)p); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpup((__be32 *)p); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpup((__be64 *)p); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ - *((__le16 *)p) = cpu_to_le16(val); -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ - *((__le32 *)p) = cpu_to_le32(val); -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ - *((__le64 *)p) = cpu_to_le64(val); -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ - *((__be16 *)p) = cpu_to_be16(val); -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ - *((__be32 *)p) = cpu_to_be32(val); -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ - *((__be64 *)p) = cpu_to_be64(val); -} - -#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */ -- cgit v1.3.1 From 60f1ba7b68f25a8d6eff65928ac87fdbfb80add4 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Mon, 22 May 2023 14:22:38 +0200 Subject: asm-generic: simplify unaligned.h The get_unaligned()/put_unaligned() implementations are more complex than necessary. Move everything into one file and use a more compact implementation based on packed struct access and byte swapping macros. This patch is based on the Linux kernel commit 803f4e1eab7a ("asm-generic: simplify asm/unaligned.h") by Arnd Bergmann. Signed-off-by: Jens Wiklander Reviewed-by: Ilias Apalodimas --- include/asm-generic/unaligned.h | 89 +++++++++++++++++++++++++++++++++-------- 1 file changed, 73 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 3d33a5a063e..9e5d93ec304 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -1,24 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _GENERIC_UNALIGNED_H #define _GENERIC_UNALIGNED_H #include -#include -#include -#include - -/* - * Select endianness - */ -#if defined(__LITTLE_ENDIAN) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#elif defined(__BIG_ENDIAN) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#else -#error invalid endian -#endif +#define __get_unaligned_t(type, ptr) ({ \ + const struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \ + __pptr->x; \ +}) + +#define __put_unaligned_t(type, val, ptr) do { \ + struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \ + __pptr->x = (val); \ +} while (0) + +#define get_unaligned(ptr) __get_unaligned_t(typeof(*(ptr)), (ptr)) +#define put_unaligned(val, ptr) __put_unaligned_t(typeof(*(ptr)), (val), (ptr)) + +static inline u16 get_unaligned_le16(const void *p) +{ + return le16_to_cpu(__get_unaligned_t(__le16, p)); +} + +static inline u32 get_unaligned_le32(const void *p) +{ + return le32_to_cpu(__get_unaligned_t(__le32, p)); +} + +static inline u64 get_unaligned_le64(const void *p) +{ + return le64_to_cpu(__get_unaligned_t(__le64, p)); +} + +static inline void put_unaligned_le16(u16 val, void *p) +{ + __put_unaligned_t(__le16, cpu_to_le16(val), p); +} + +static inline void put_unaligned_le32(u32 val, void *p) +{ + __put_unaligned_t(__le32, cpu_to_le32(val), p); +} + +static inline void put_unaligned_le64(u64 val, void *p) +{ + __put_unaligned_t(__le64, cpu_to_le64(val), p); +} + +static inline u16 get_unaligned_be16(const void *p) +{ + return be16_to_cpu(__get_unaligned_t(__be16, p)); +} + +static inline u32 get_unaligned_be32(const void *p) +{ + return be32_to_cpu(__get_unaligned_t(__be32, p)); +} + +static inline u64 get_unaligned_be64(const void *p) +{ + return be64_to_cpu(__get_unaligned_t(__be64, p)); +} + +static inline void put_unaligned_be16(u16 val, void *p) +{ + __put_unaligned_t(__be16, cpu_to_be16(val), p); +} + +static inline void put_unaligned_be32(u32 val, void *p) +{ + __put_unaligned_t(__be32, cpu_to_be32(val), p); +} + +static inline void put_unaligned_be64(u64 val, void *p) +{ + __put_unaligned_t(__be64, cpu_to_be64(val), p); +} /* Allow unaligned memory access */ void allow_unaligned(void); -- cgit v1.3.1 From 1e4d965b592fb2f790948eed2db8010bda674fc5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 29 Apr 2023 19:21:46 -0600 Subject: acpi: Put the version numbers in a central place At present two acpi files are built every time since they use a version number from version.h This is not necessary. Make use of the same technique as for the version string, so that they are build only when they change. Signed-off-by: Simon Glass --- cmd/version.c | 2 ++ include/version_string.h | 2 ++ lib/acpi/acpi_table.c | 15 +++++++-------- test/dm/acpi.c | 16 +++++++--------- 4 files changed, 18 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/cmd/version.c b/cmd/version.c index 190ef6a9061..87e1fa4159c 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -19,6 +19,8 @@ U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING const char version_string[] = U_BOOT_VERSION_STRING; +const unsigned short version_num = U_BOOT_VERSION_NUM; +const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH; static int do_version(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/include/version_string.h b/include/version_string.h index a89a6e43705..a7d07e4cc7c 100644 --- a/include/version_string.h +++ b/include/version_string.h @@ -4,5 +4,7 @@ #define __VERSION_STRING_H__ extern const char version_string[]; +extern const unsigned short version_num; +extern const unsigned char version_num_patch; #endif /* __VERSION_STRING_H__ */ diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 7c4189e2434..a8d4b470001 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -11,8 +11,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -25,12 +24,12 @@ * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to * value 0x20210401. */ -#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ - (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ - (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ - ((U_BOOT_VERSION_NUM % 10) << 16) | \ - (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ - ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ +#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \ + (((version_num / 100) % 10) << 24) | \ + (((version_num / 10) % 10) << 20) | \ + ((version_num % 10) << 16) | \ + (((version_num_patch / 10) % 10) << 12) | \ + ((version_num_patch % 10) << 8) | \ 0x01) int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 9634fc2e900..818f71572c7 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -11,10 +11,8 @@ #include #include #include -#include -#include #include -#include +#include #include #include #include @@ -26,12 +24,12 @@ #define BUF_SIZE 4096 -#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ - (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ - (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ - ((U_BOOT_VERSION_NUM % 10) << 16) | \ - (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ - ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ +#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \ + (((version_num / 100) % 10) << 24) | \ + (((version_num / 10) % 10) << 20) | \ + ((version_num % 10) << 16) | \ + (((version_num_patch / 10) % 10) << 12) | \ + ((version_num_patch % 10) << 8) | \ 0x01) /** -- cgit v1.3.1 From cccea18813c44c15b2709edcfba1048e42d28404 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Wed, 7 Jun 2023 14:41:51 +0900 Subject: efi_loader: add the number of image entries in efi_capsule_update_info The number of image array entries global variable is required to support EFI capsule update. This information is exposed as a num_image_type_guids variable, but this information should be included in the efi_capsule_update_info structure. This commit adds the num_images member in the efi_capsule_update_info structure. All board files supporting EFI capsule update are updated. Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas --- arch/arm/mach-rockchip/board.c | 4 ++-- board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 2 +- board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 2 +- board/emulation/qemu-arm/qemu-arm.c | 2 +- board/kontron/pitx_imx8m/pitx_imx8m.c | 2 +- board/kontron/sl-mx8mm/sl-mx8mm.c | 2 +- board/kontron/sl28/sl28.c | 2 +- board/rockchip/evb_rk3399/evb-rk3399.c | 2 +- board/sandbox/sandbox.c | 2 +- board/socionext/developerbox/developerbox.c | 2 +- board/st/stm32mp1/stm32mp1.c | 2 +- board/xilinx/common/board.c | 2 +- include/efi_loader.h | 3 ++- lib/efi_loader/efi_firmware.c | 6 +++--- lib/fwu_updates/fwu.c | 2 +- 15 files changed, 19 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index f1f70c81d0c..8daa74b3eb7 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -41,7 +41,7 @@ static bool updatable_image(struct disk_partition *info) uuid_str_to_bin(info->type_guid, image_type_guid.b, UUID_STR_FORMAT_GUID); - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) { ret = true; break; @@ -59,7 +59,7 @@ static void set_image_index(struct disk_partition *info, int index) uuid_str_to_bin(info->type_guid, image_type_guid.b, UUID_STR_FORMAT_GUID); - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) { fw_images[i].image_index = index; break; diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 466174679e8..b79a2380aa5 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -54,10 +54,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index b373e45df95..af070ec315c 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -50,10 +50,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "mmc 2=flash-bin raw 0x42 0x1D00 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_phys_sdram_size(phys_size_t *size) diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 34ed3e8ae63..dfea0d92a3c 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -47,10 +47,10 @@ struct efi_fw_image fw_images[] = { }; struct efi_capsule_update_info update_info = { + .num_images = ARRAY_SIZE(fw_images) .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ static struct mm_region qemu_arm64_mem_map[] = { diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index fcda86bc1b1..4548e7c1dff 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -43,10 +43,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_early_init_f(void) diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 250195694ba..ddb509eb66b 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -29,10 +29,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "sf 0:0=flash-bin raw 0x400 0x1f0000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_phys_sdram_size(phys_size_t *size) diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 89948e087f1..4ab221c12bf 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -40,10 +40,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "sf 0:0=u-boot-bin raw 0x210000 0x1d0000;" "u-boot-env raw 0x3e0000 0x20000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_early_init_f(void) diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index c99ffdd75e8..3c773d0930c 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -18,10 +18,10 @@ static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0}; struct efi_capsule_update_info update_info = { + .num_images = ROCKPI4_UPDATABLE_IMAGES, .images = fw_images, }; -u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES; #endif #ifndef CONFIG_SPL_BUILD diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 2e44bdf0df3..c7b6cb78fff 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -67,10 +67,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "sf 0:0=u-boot-bin raw 0x100000 0x50000;" "u-boot-env raw 0x150000 0x200000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ #if !CONFIG_IS_ENABLED(OF_PLATDATA) diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 16e14d4f7f5..d92e1d09627 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -41,10 +41,10 @@ struct efi_capsule_update_info update_info = { .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;" "fip.bin raw 180000 78000;" "optee.bin raw 500000 100000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ static struct mm_region sc2a11_mem_map[] = { diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 1a1b1844c8c..5b28ccd32e6 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -92,10 +92,10 @@ struct efi_fw_image fw_images[1]; struct efi_capsule_update_info update_info = { + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_early_init_f(void) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index d071ebfb9cc..0328d68e751 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -52,10 +52,10 @@ struct efi_fw_image fw_images[] = { }; struct efi_capsule_update_info update_info = { + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ #define EEPROM_HEADER_MAGIC 0xdaaddeed diff --git a/include/efi_loader.h b/include/efi_loader.h index b395eef9e79..941d63467ce 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1078,15 +1078,16 @@ struct efi_fw_image { * platforms which enable capsule updates * * @dfu_string: String used to populate dfu_alt_info + * @num_images: The number of images array entries * @images: Pointer to an array of updatable images */ struct efi_capsule_update_info { const char *dfu_string; + int num_images; struct efi_fw_image *images; }; extern struct efi_capsule_update_info update_info; -extern u8 num_image_type_guids; /** * Install the ESRT system table. diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 93e2b01c07a..cc650e1443d 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -131,7 +131,7 @@ static efi_status_t efi_fill_image_desc_array( struct efi_fw_image *fw_array; int i; - total_size = sizeof(*image_info) * num_image_type_guids; + total_size = sizeof(*image_info) * update_info.num_images; if (*image_info_size < total_size) { *image_info_size = total_size; @@ -141,13 +141,13 @@ static efi_status_t efi_fill_image_desc_array( *image_info_size = total_size; fw_array = update_info.images; - *descriptor_count = num_image_type_guids; + *descriptor_count = update_info.num_images; *descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION; *descriptor_size = sizeof(*image_info); *package_version = 0xffffffff; /* not supported */ *package_version_name = NULL; /* not supported */ - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { image_info[i].image_index = fw_array[i].image_index; image_info[i].image_type_id = fw_array[i].image_type_id; image_info[i].image_id = fw_array[i].image_index; diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index 5313d073020..3b1785e7b1e 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -151,7 +151,7 @@ static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id) index = *image_index; image = update_info.images; - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { if (index == image[i].image_index) { guidcpy(image_type_id, &image[i].image_type_id); return 0; -- cgit v1.3.1 From 79fedab62af1efe301a9aaa6ecb4cb49431cac83 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 31 May 2023 19:53:04 +0200 Subject: ARM: rmobile: Drop eagle.h config of R8A77970 V3M Eagle board The eagle.h is now empty and only includes rcar-gen3-common.h . Use rcar-gen3-common.h directly instead and drop eagle.h . No functional change. Signed-off-by: Marek Vasut --- board/renesas/eagle/Kconfig | 2 +- include/configs/eagle.h | 19 ------------------- 2 files changed, 1 insertion(+), 20 deletions(-) delete mode 100644 include/configs/eagle.h (limited to 'include') diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig index 1e0710e73e1..4d12843b4e9 100644 --- a/board/renesas/eagle/Kconfig +++ b/board/renesas/eagle/Kconfig @@ -10,6 +10,6 @@ config SYS_VENDOR default "renesas" config SYS_CONFIG_NAME - default "eagle" + default "rcar-gen3-common" endif diff --git a/include/configs/eagle.h b/include/configs/eagle.h deleted file mode 100644 index c751f75a7d0..00000000000 --- a/include/configs/eagle.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/eagle.h - * This file is Eagle board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - */ - -#ifndef __EAGLE_H -#define __EAGLE_H - -#include "rcar-gen3-common.h" - -/* Environment compatibility */ - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - -#endif /* __EAGLE_H */ -- cgit v1.3.1 From ed2f65f0105dacb98e5c4d2b435dd009de06c2d1 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 23 Apr 2019 23:44:57 +0300 Subject: ARM: renesas: Add R8A77980 V3HSK board and CPLD code Add board code for the R8A77980 V3HSK board. Add CPLD sysreset driver to the R-Car V3H SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut Signed-off-by: Valentine Barshak Signed-off-by: Hai Pham Signed-off-by: Tam Nguyen Signed-off-by: Marek Vasut [Marek: Sync configs and board code with V3H Condor, squash CPLD driver in] --- arch/arm/dts/Makefile | 1 + arch/arm/dts/r8a77980-v3hsk-u-boot.dts | 42 ++++++++ arch/arm/mach-rmobile/Kconfig.rcar3 | 6 ++ board/renesas/v3hsk/Kconfig | 15 +++ board/renesas/v3hsk/Makefile | 15 +++ board/renesas/v3hsk/cpld.c | 180 +++++++++++++++++++++++++++++++++ configs/r8a77980_v3hsk_defconfig | 83 +++++++++++++++ include/configs/v3hsk.h | 28 +++++ 8 files changed, 370 insertions(+) create mode 100644 arch/arm/dts/r8a77980-v3hsk-u-boot.dts create mode 100644 board/renesas/v3hsk/Kconfig create mode 100644 board/renesas/v3hsk/Makefile create mode 100644 board/renesas/v3hsk/cpld.c create mode 100644 configs/r8a77980_v3hsk_defconfig create mode 100644 include/configs/v3hsk.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dd917ae1b36..4b19a93ceea 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1052,6 +1052,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77970-eagle-u-boot.dtb \ r8a77970-v3msk-u-boot.dtb \ r8a77980-condor-u-boot.dtb \ + r8a77980-v3hsk-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \ r8a77995-draak-u-boot.dtb diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts new file mode 100644 index 00000000000..d083df65f9a --- /dev/null +++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Eagle board + * + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#include "r8a77980-v3hsk.dts" +#include "r8a77980-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; + +&i2c0 { + cpld { + compatible = "renesas,v3hsk-cpld"; + reg = <0x70>; + u-boot,i2c-offset-len = <2>; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3 index 46d274273af..ad35d1058f2 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar3 +++ b/arch/arm/mach-rmobile/Kconfig.rcar3 @@ -99,6 +99,11 @@ config TARGET_CONDOR help Support for Renesas R-Car Gen3 Condor platform +config TARGET_V3HSK + bool "V3HSK board" + help + Support for Renesas R-Car Gen3 V3HSK platform + config TARGET_DRAAK bool "Draak board" imply R8A77995 @@ -171,6 +176,7 @@ source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" +source "board/renesas/v3hsk/Kconfig" source "board/renesas/v3msk/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" source "board/hoperun/hihope-rzg2/Kconfig" diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig new file mode 100644 index 00000000000..531ceb788f4 --- /dev/null +++ b/board/renesas/v3hsk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_V3HSK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "v3hsk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "v3hsk" + +endif diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile new file mode 100644 index 00000000000..a9d597edd58 --- /dev/null +++ b/board/renesas/v3hsk/Makefile @@ -0,0 +1,15 @@ +# +# board/renesas/v3hsk/Makefile +# +# Copyright (C) 2019 Renesas Electronics Corporation +# Copyright (C) 2019 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-$(CONFIG_SYSRESET) += cpld.o +endif diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c new file mode 100644 index 00000000000..6016f6daef9 --- /dev/null +++ b/board/renesas/v3hsk/cpld.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V3HSK board CPLD access support + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define CPLD_ADDR_PRODUCT_0 0x0000 /* R */ +#define CPLD_ADDR_PRODUCT_1 0x0001 /* R */ +#define CPLD_ADDR_PRODUCT_2 0x0002 /* R */ +#define CPLD_ADDR_PRODUCT_3 0x0003 /* R */ +#define CPLD_ADDR_CPLD_VERSION_D 0x0004 /* R */ +#define CPLD_ADDR_CPLD_VERSION_M 0x0005 /* R */ +#define CPLD_ADDR_CPLD_VERSION_Y_0 0x0006 /* R */ +#define CPLD_ADDR_CPLD_VERSION_Y_1 0x0007 /* R */ +#define CPLD_ADDR_MODE_SET_0 0x0008 /* R */ +#define CPLD_ADDR_MODE_SET_1 0x0009 /* R */ +#define CPLD_ADDR_MODE_SET_2 0x000A /* R */ +#define CPLD_ADDR_MODE_SET_3 0x000B /* R */ +#define CPLD_ADDR_MODE_SET_4 0x000C /* R */ +#define CPLD_ADDR_MODE_LAST_0 0x0018 /* R */ +#define CPLD_ADDR_MODE_LAST_1 0x0019 /* R */ +#define CPLD_ADDR_MODE_LAST_2 0x001A /* R */ +#define CPLD_ADDR_MODE_LAST_3 0x001B /* R */ +#define CPLD_ADDR_MODE_LAST_4 0x001C /* R */ +#define CPLD_ADDR_DIPSW4 0x0020 /* R */ +#define CPLD_ADDR_DIPSW5 0x0021 /* R */ +#define CPLD_ADDR_RESET 0x0024 /* R/W */ +#define CPLD_ADDR_POWER_CFG 0x0025 /* R/W */ +#define CPLD_ADDR_PERI_CFG_0 0x0030 /* R/W */ +#define CPLD_ADDR_PERI_CFG_1 0x0031 /* R/W */ +#define CPLD_ADDR_PERI_CFG_2 0x0032 /* R/W */ +#define CPLD_ADDR_PERI_CFG_3 0x0033 /* R/W */ +#define CPLD_ADDR_LEDS 0x0034 /* R/W */ +#define CPLD_ADDR_LEDS_CFG 0x0035 /* R/W */ +#define CPLD_ADDR_UART_CFG 0x0036 /* R/W */ +#define CPLD_ADDR_UART_STATUS 0x0037 /* R */ + +#define CPLD_ADDR_PCB_VERSION_0 0x1000 /* R */ +#define CPLD_ADDR_PCB_VERSION_1 0x1001 /* R */ +#define CPLD_ADDR_SOC_VERSION_0 0x1002 /* R */ +#define CPLD_ADDR_SOC_VERSION_1 0x1003 /* R */ +#define CPLD_ADDR_PCB_SN_0 0x1004 /* R */ +#define CPLD_ADDR_PCB_SN_1 0x1005 /* R */ + +static u16 cpld_read(struct udevice *dev, u16 addr) +{ + u8 data[2]; + + /* Random flash reads require 2 reads: first read is unreliable */ + if (addr >= CPLD_ADDR_PCB_VERSION_0) + dm_i2c_read(dev, addr, data, 2); + + /* Only the second byte read is valid */ + dm_i2c_read(dev, addr, data, 2); + return data[1]; +} + +static void cpld_write(struct udevice *dev, u16 addr, u8 data) +{ + dm_i2c_write(dev, addr, &data, 1); +} + +static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + u16 addr, val; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_DRIVER_GET(sysreset_renesas_v3hsk), + &dev); + if (ret) + return ret; + + if (argc == 2 && strcmp(argv[1], "info") == 0) { + printf("Product: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) | + (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) | + (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) | + cpld_read(dev, CPLD_ADDR_PRODUCT_0)); + printf("CPLD version: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) | + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) | + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) | + cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D)); + printf("Mode setting (MD0..26): 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) | + (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) | + (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) | + cpld_read(dev, CPLD_ADDR_MODE_LAST_0)); + printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n", + cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff, + (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf); + printf("Power config: 0x%08x\n", + cpld_read(dev, CPLD_ADDR_POWER_CFG)); + printf("Periferals config: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) | + (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) | + (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) | + cpld_read(dev, CPLD_ADDR_PERI_CFG_0)); + printf("PCB version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_PCB_VERSION_1), + cpld_read(dev, CPLD_ADDR_PCB_VERSION_0)); + printf("SOC version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_SOC_VERSION_1), + cpld_read(dev, CPLD_ADDR_SOC_VERSION_0)); + printf("PCB S/N: %d\n", + (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) | + cpld_read(dev, CPLD_ADDR_PCB_SN_0)); + return 0; + } + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) { + printf("cpld invalid addr\n"); + return CMD_RET_USAGE; + } + + if (argc == 3 && strcmp(argv[1], "read") == 0) { + printf("0x%x\n", cpld_read(dev, addr)); + } else if (argc == 4 && strcmp(argv[1], "write") == 0) { + val = simple_strtoul(argv[3], NULL, 16); + cpld_write(dev, addr, val); + } + + return 0; +} + +U_BOOT_CMD(cpld, 4, 1, do_cpld, + "CPLD access", + "info\n" + "cpld read addr\n" + "cpld write addr val\n" +); + +static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; +} + +static int renesas_v3hsk_sysreset_probe(struct udevice *dev) +{ + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + return 0; +} + +static struct sysreset_ops renesas_v3hsk_sysreset = { + .request = renesas_v3hsk_sysreset_request, +}; + +static const struct udevice_id renesas_v3hsk_sysreset_ids[] = { + { .compatible = "renesas,v3hsk-cpld" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysreset_renesas_v3hsk) = { + .name = "renesas_v3hsk_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_v3hsk_sysreset, + .probe = renesas_v3hsk_sysreset_probe, + .of_match = renesas_v3hsk_sysreset_ids, +}; diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig new file mode 100644 index 00000000000..564ff2d783c --- /dev/null +++ b/configs/r8a77980_v3hsk_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=16666666 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot" +CONFIG_SPL_TEXT_BASE=0xe6318000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77980=y +CONFIG_TARGET_V3HSK=y +CONFIG_SPL_STACK=0xe6304000 +CONFIG_SYS_LOAD_ADDR=0x58000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb" +# CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_SH_ETHER=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_SYSRESET=y diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h new file mode 100644 index 00000000000..58c2e88c0b7 --- /dev/null +++ b/include/configs/v3hsk.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/v3hsk.h + * This file is V3HSK board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#ifndef __V3HSK_H +#define __V3HSK_H + +#include "rcar-gen3-common.h" + +/* Environment compatibility */ + +/* SH Ether */ +#define CFG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_PHY_ADDR 0x0 +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID +#define CFG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ + +#endif /* __V3HSK_H */ -- cgit v1.3.1 From 167994f295e29de417bdb7b05e02fe5fd9b0d054 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 6 Mar 2023 17:18:28 -0600 Subject: fwu: move meta-data management in core Instead of each i/f having to implement their own meta-data verification and storage, move the logic in common code. This simplifies the i/f code much simpler and compact. Signed-off-by: Jassi Brar Reviewed-by: Ilias Apalodimas Tested-by: Sughosh Ganu --- drivers/fwu-mdata/fwu-mdata-uclass.c | 34 +++++++++ include/fwu.h | 41 +++++++++++ lib/fwu_updates/fwu.c | 133 +++++++++++++++++++++++++++++++++-- 3 files changed, 202 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c index b477e9603fb..e03773c584a 100644 --- a/drivers/fwu-mdata/fwu-mdata-uclass.c +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c @@ -16,6 +16,40 @@ #include #include +/** + * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() + * + * Return: 0 if OK, -ve on error + */ +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +{ + const struct fwu_mdata_ops *ops = device_get_ops(dev); + + if (!ops->read_mdata) { + log_debug("read_mdata() method not defined\n"); + return -ENOSYS; + } + + return ops->read_mdata(dev, mdata, primary); +} + +/** + * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata() + * + * Return: 0 if OK, -ve on error + */ +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +{ + const struct fwu_mdata_ops *ops = device_get_ops(dev); + + if (!ops->write_mdata) { + log_debug("write_mdata() method not defined\n"); + return -ENOSYS; + } + + return ops->write_mdata(dev, mdata, primary); +} + /** * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers * @dev: FWU metadata device diff --git a/include/fwu.h b/include/fwu.h index 0919ced812c..e3bede18433 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -24,6 +24,26 @@ struct fwu_mdata_gpt_blk_priv { * @update_mdata() - Update the FWU metadata copy */ struct fwu_mdata_ops { + /** + * read_mdata() - Populate the asked FWU metadata copy + * @dev: FWU metadata device + * @mdata: Output FWU mdata read + * @primary: If primary or secondary copy of metadata is to be read + * + * Return: 0 if OK, -ve on error + */ + int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); + + /** + * write_mdata() - Write the given FWU metadata copy + * @dev: FWU metadata device + * @mdata: Copy of the FWU metadata to write + * @primary: If primary or secondary copy of metadata is to be written + * + * Return: 0 if OK, -ve on error + */ + int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); + /** * check_mdata() - Check if the FWU metadata is valid * @dev: FWU device @@ -126,6 +146,27 @@ struct fwu_mdata_ops { EFI_GUID(0x0c996046, 0xbcc0, 0x4d04, 0x85, 0xec, \ 0xe1, 0xfc, 0xed, 0xf1, 0xc6, 0xf8) +/** + * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() + */ +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); + +/** + * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata() + */ +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); + +/** + * fwu_get_verified_mdata() - Read, verify and return the FWU metadata + * + * Read both the metadata copies from the storage media, verify their checksum, + * and ascertain that both copies match. If one of the copies has gone bad, + * restore it from the good copy. + * + * Return: 0 if OK, -ve on error + */ +int fwu_get_verified_mdata(struct fwu_mdata *mdata); + /** * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies * diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index 3b1785e7b1e..77142c5376c 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -15,13 +15,13 @@ #include #include +#include + +static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */ +static struct udevice *g_dev; static u8 in_trial; static u8 boottime_check; -#include -#include -#include - enum { IMAGE_ACCEPT_SET = 1, IMAGE_ACCEPT_CLEAR, @@ -161,6 +161,127 @@ static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id) return -ENOENT; } +/** + * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided + * @mdata: FWU metadata structure + * @part: Bitmask of FWU metadata partitions to be written to + * + * Return: 0 if OK, -ve on error + */ +static int fwu_sync_mdata(struct fwu_mdata *mdata, int part) +{ + void *buf = &mdata->version; + int err; + + if (part == BOTH_PARTS) { + err = fwu_sync_mdata(mdata, SECONDARY_PART); + if (err) + return err; + part = PRIMARY_PART; + } + + /* + * Calculate the crc32 for the updated FWU metadata + * and put the updated value in the FWU metadata crc32 + * field + */ + mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); + + err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART); + if (err) { + log_err("Unable to write %s mdata\n", + part == PRIMARY_PART ? "primary" : "secondary"); + return err; + } + + /* update the cached copy of meta-data */ + memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata)); + + return 0; +} + +static inline int mdata_crc_check(struct fwu_mdata *mdata) +{ + void *buf = &mdata->version; + u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); + + return calc_crc32 == mdata->crc32 ? 0 : -EINVAL; +} + +/** + * fwu_get_verified_mdata() - Read, verify and return the FWU metadata + * @mdata: Output FWU metadata read or NULL + * + * Read both the metadata copies from the storage media, verify their checksum, + * and ascertain that both copies match. If one of the copies has gone bad, + * restore it from the good copy. + * + * Return: 0 if OK, -ve on error + */ +int fwu_get_verified_mdata(struct fwu_mdata *mdata) +{ + int err; + bool parts_ok[2] = { false }; + struct fwu_mdata s, *parts_mdata[2]; + + parts_mdata[0] = &g_mdata; + parts_mdata[1] = &s; + + /* if mdata already read and ready */ + err = mdata_crc_check(parts_mdata[0]); + if (!err) + goto ret_mdata; + /* else read, verify and, if needed, fix mdata */ + + for (int i = 0; i < 2; i++) { + parts_ok[i] = false; + err = fwu_read_mdata(g_dev, parts_mdata[i], !i); + if (!err) { + err = mdata_crc_check(parts_mdata[i]); + if (!err) + parts_ok[i] = true; + else + log_debug("mdata : %s crc32 failed\n", i ? "secondary" : "primary"); + } + } + + if (parts_ok[0] && parts_ok[1]) { + /* + * Before returning, check that both the + * FWU metadata copies are the same. + */ + err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata)); + if (!err) + goto ret_mdata; + + /* + * If not, populate the secondary partition from the + * primary partition copy. + */ + log_info("Both FWU metadata copies are valid but do not match."); + log_info(" Restoring the secondary partition from the primary\n"); + parts_ok[1] = false; + } + + for (int i = 0; i < 2; i++) { + if (parts_ok[i]) + continue; + + memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata)); + err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART); + if (err) { + log_debug("mdata : %s write failed\n", i ? "secondary" : "primary"); + return err; + } + } + +ret_mdata: + if (!err && mdata) + memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata)); + + return err; +} + /** * fwu_verify_mdata() - Verify the FWU metadata * @mdata: FWU metadata structure @@ -436,8 +557,8 @@ int fwu_get_image_index(u8 *image_index) } } - log_debug("Partition with the image type %pUs not found\n", - &image_type_id); + log_err("Partition with the image type %pUs not found\n", + &image_type_id); out: return ret; -- cgit v1.3.1 From 246ec2a12c437ff821e452104f3f564e5d25fa91 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 6 Mar 2023 17:18:41 -0600 Subject: fwu: meta-data: switch to management by common code The common code can now read, verify and fix meta-data copies while exposing one consistent structure to users. Only the .read_mdata() and .write_mdata() callbacks of fwu_mdata_ops are needed. Get rid of .get_mdata() .update_mdata() .get_mdata_part_num() .read_mdata_partition() and .write_mdata_partition() and also the corresponding wrapper functions. Signed-off-by: Jassi Brar Reviewed-by: Etienne Carriere Reviewed-by: Ilias Apalodimas Tested-by: Sughosh Ganu --- cmd/fwu_mdata.c | 17 +-- drivers/fwu-mdata/fwu-mdata-uclass.c | 165 ------------------------ drivers/fwu-mdata/gpt_blk.c | 124 +----------------- include/fwu.h | 199 ----------------------------- lib/fwu_updates/fwu.c | 235 +++++------------------------------ 5 files changed, 38 insertions(+), 702 deletions(-) (limited to 'include') diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c index f04af27de63..9b70340368a 100644 --- a/cmd/fwu_mdata.c +++ b/cmd/fwu_mdata.c @@ -43,23 +43,10 @@ static void print_mdata(struct fwu_mdata *mdata) int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { - struct udevice *dev; int ret = CMD_RET_SUCCESS, res; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata mdata; - if (uclass_get_device(UCLASS_FWU_MDATA, 0, &dev) || !dev) { - log_err("Unable to get FWU metadata device\n"); - return CMD_RET_FAILURE; - } - - res = fwu_check_mdata_validity(); - if (res < 0) { - log_err("FWU Metadata check failed\n"); - ret = CMD_RET_FAILURE; - goto out; - } - - res = fwu_get_mdata(dev, &mdata); + res = fwu_get_verified_mdata(&mdata); if (res < 0) { log_err("Unable to get valid FWU metadata\n"); ret = CMD_RET_FAILURE; diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c index e03773c584a..0a8edaaa418 100644 --- a/drivers/fwu-mdata/fwu-mdata-uclass.c +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c @@ -14,7 +14,6 @@ #include #include -#include /** * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() @@ -50,170 +49,6 @@ int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) return ops->write_mdata(dev, mdata, primary); } -/** - * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->get_mdata_part_num) { - log_debug("get_mdata_part_num() method not defined\n"); - return -ENOSYS; - } - - return ops->get_mdata_part_num(dev, mdata_parts); -} - -/** - * fwu_read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read - * - * Read the FWU metadata from the specified partition number - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->read_mdata_partition) { - log_debug("read_mdata_partition() method not defined\n"); - return -ENOSYS; - } - - return ops->read_mdata_partition(dev, mdata, part_num); -} - -/** - * fwu_write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->write_mdata_partition) { - log_debug("write_mdata_partition() method not defined\n"); - return -ENOSYS; - } - - return ops->write_mdata_partition(dev, mdata, part_num); -} - -/** - * fwu_mdata_check() - Check if the FWU metadata is valid - * @dev: FWU metadata device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_mdata_check(struct udevice *dev) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->check_mdata) { - log_debug("check_mdata() method not defined\n"); - return -ENOSYS; - } - - return ops->check_mdata(dev); -} - -/** - * fwu_get_mdata() - Get a FWU metadata copy - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Note: This function is to be called first when modifying any fields - * in the metadata. The sequence of calls to modify any field in the - * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by - * 3) fwu_update_mdata - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->get_mdata) { - log_debug("get_mdata() method not defined\n"); - return -ENOSYS; - } - - return ops->get_mdata(dev, mdata); -} - -/** - * fwu_update_mdata() - Update the FWU metadata - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Note: This function is not to be called directly to update the - * metadata fields. The sequence of function calls should be - * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata() - * - * The sequence of updating the partitions should be, update the - * primary metadata partition (first partition encountered), followed - * by updating the secondary partition. With this update sequence, in - * the rare scenario that the two metadata partitions are valid but do - * not match, maybe due to power outage at the time of updating the - * metadata copies, the secondary partition can be updated from the - * primary. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata) -{ - void *buf; - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->update_mdata) { - log_debug("get_mdata() method not defined\n"); - return -ENOSYS; - } - - /* - * Calculate the crc32 for the updated FWU metadata - * and put the updated value in the FWU metadata crc32 - * field - */ - buf = &mdata->version; - mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); - - return ops->update_mdata(dev, mdata); -} - UCLASS_DRIVER(fwu_mdata) = { .id = UCLASS_FWU_MDATA, .name = "fwu-mdata", diff --git a/drivers/fwu-mdata/gpt_blk.c b/drivers/fwu-mdata/gpt_blk.c index 1b071c8ed29..c7284916c4e 100644 --- a/drivers/fwu-mdata/gpt_blk.c +++ b/drivers/fwu-mdata/gpt_blk.c @@ -28,7 +28,7 @@ static uint g_mdata_part[2]; /* = {0, 0} to check against uninit parts */ static int gpt_get_mdata_partitions(struct blk_desc *desc) { - int i, ret; + int i; u32 nparts; efi_guid_t part_type_guid; struct disk_partition info; @@ -52,12 +52,12 @@ static int gpt_get_mdata_partitions(struct blk_desc *desc) if (nparts != 2) { log_debug("Expect two copies of the FWU metadata instead of %d\n", nparts); - ret = -EINVAL; - } else { - ret = 0; + g_mdata_part[0] = 0; + g_mdata_part[1] = 0; + return -EINVAL; } - return ret; + return 0; } static int gpt_get_mdata_disk_part(struct blk_desc *desc, @@ -125,115 +125,6 @@ static int gpt_read_write_mdata(struct blk_desc *desc, return 0; } -static int fwu_gpt_update_mdata(struct udevice *dev, struct fwu_mdata *mdata) -{ - int ret; - struct blk_desc *desc; - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - desc = dev_get_uclass_plat(priv->blk_dev); - - ret = gpt_get_mdata_partitions(desc); - if (ret < 0) { - log_debug("Error getting the FWU metadata partitions\n"); - return -ENOENT; - } - - /* First write the primary partition */ - ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, g_mdata_part[0]); - if (ret < 0) { - log_debug("Updating primary FWU metadata partition failed\n"); - return ret; - } - - /* And now the replica */ - ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, g_mdata_part[1]); - if (ret < 0) { - log_debug("Updating secondary FWU metadata partition failed\n"); - return ret; - } - - return 0; -} - -static int gpt_get_mdata(struct blk_desc *desc, struct fwu_mdata *mdata) -{ - int ret; - - ret = gpt_get_mdata_partitions(desc); - if (ret < 0) { - log_debug("Error getting the FWU metadata partitions\n"); - return -ENOENT; - } - - ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, g_mdata_part[0]); - if (ret < 0) { - log_debug("Failed to read the FWU metadata from the device\n"); - return -EIO; - } - - ret = fwu_verify_mdata(mdata, 1); - if (!ret) - return 0; - - /* - * Verification of the primary FWU metadata copy failed. - * Try to read the replica. - */ - memset(mdata, '\0', sizeof(struct fwu_mdata)); - ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, g_mdata_part[1]); - if (ret < 0) { - log_debug("Failed to read the FWU metadata from the device\n"); - return -EIO; - } - - ret = fwu_verify_mdata(mdata, 0); - if (!ret) - return 0; - - /* Both the FWU metadata copies are corrupted. */ - return -EIO; -} - -static int fwu_gpt_get_mdata(struct udevice *dev, struct fwu_mdata *mdata) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_get_mdata(dev_get_uclass_plat(priv->blk_dev), mdata); -} - -static int fwu_gpt_get_mdata_partitions(struct udevice *dev, uint *mdata_parts) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - int err; - - err = gpt_get_mdata_partitions(dev_get_uclass_plat(priv->blk_dev)); - if (!err) { - mdata_parts[0] = g_mdata_part[0]; - mdata_parts[1] = g_mdata_part[1]; - } - - return err; -} - -static int fwu_gpt_read_mdata_partition(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev), - mdata, MDATA_READ, part_num); -} - -static int fwu_gpt_write_mdata_partition(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev), - mdata, MDATA_WRITE, part_num); -} - static int fwu_get_mdata_device(struct udevice *dev, struct udevice **mdata_dev) { u32 phandle; @@ -309,11 +200,6 @@ static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, static const struct fwu_mdata_ops fwu_gpt_blk_ops = { .read_mdata = fwu_gpt_read_mdata, .write_mdata = fwu_gpt_write_mdata, - .get_mdata = fwu_gpt_get_mdata, - .update_mdata = fwu_gpt_update_mdata, - .get_mdata_part_num = fwu_gpt_get_mdata_partitions, - .read_mdata_partition = fwu_gpt_read_mdata_partition, - .write_mdata_partition = fwu_gpt_write_mdata_partition, }; static const struct udevice_id fwu_mdata_ids[] = { diff --git a/include/fwu.h b/include/fwu.h index e3bede18433..7b600ce0d7e 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -18,11 +18,6 @@ struct fwu_mdata_gpt_blk_priv { struct udevice *blk_dev; }; -/** - * @mdata_check: check the validity of the FWU metadata partitions - * @get_mdata() - Get a FWU metadata copy - * @update_mdata() - Update the FWU metadata copy - */ struct fwu_mdata_ops { /** * read_mdata() - Populate the asked FWU metadata copy @@ -43,78 +38,6 @@ struct fwu_mdata_ops { * Return: 0 if OK, -ve on error */ int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); - - /** - * check_mdata() - Check if the FWU metadata is valid - * @dev: FWU device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - */ - int (*check_mdata)(struct udevice *dev); - - /** - * get_mdata() - Get a FWU metadata copy - * @dev: FWU device - * @mdata: Pointer to FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Return: 0 if OK, -ve on error - */ - int (*get_mdata)(struct udevice *dev, struct fwu_mdata *mdata); - - /** - * update_mdata() - Update the FWU metadata - * @dev: FWU device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Return: 0 if OK, -ve on error - */ - int (*update_mdata)(struct udevice *dev, struct fwu_mdata *mdata); - - /** - * get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned. - * - * Return: 0 if OK, -ve on error - */ - int (*get_mdata_part_num)(struct udevice *dev, uint *mdata_parts); - - /** - * read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read - * - * Read the FWU metadata from the specified partition number - * - * Return: 0 if OK, -ve on error - */ - int (*read_mdata_partition)(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num); - - /** - * write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number - * - * Return: 0 if OK, -ve on error - */ - int (*write_mdata_partition)(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num); }; #define FWU_MDATA_VERSION 0x1 @@ -167,102 +90,6 @@ int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); */ int fwu_get_verified_mdata(struct fwu_mdata *mdata); -/** - * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies - * - * Read both the metadata copies from the storage media, verify their - * checksum, and ascertain that both copies match. If one of the copies - * has gone bad, restore it from the good copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_check_mdata_validity(void); - -/** - * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned - * through the array. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts); - -/** - * fwu_read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read - * - * Read the FWU metadata from the specified partition number - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num); - -/** - * fwu_write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num); - -/** - * fwu_get_mdata() - Get a FWU metadata copy - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Note: This function is to be called first when modifying any fields - * in the metadata. The sequence of calls to modify any field in the - * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by - * 3) fwu_update_mdata - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata); - -/** - * fwu_update_mdata() - Update the FWU metadata - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Note: This function is not to be called directly to update the - * metadata fields. The sequence of function calls should be - * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata() - * - * The sequence of updating the partitions should be, update the - * primary metadata partition (first partition encountered), followed - * by updating the secondary partition. With this update sequence, in - * the rare scenario that the two metadata partitions are valid but do - * not match, maybe due to power outage at the time of updating the - * metadata copies, the secondary partition can be updated from the - * primary. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata); - /** * fwu_get_active_index() - Get active_index from the FWU metadata * @active_idxp: active_index value to be read @@ -303,18 +130,6 @@ int fwu_set_active_index(uint active_idx); */ int fwu_get_image_index(u8 *image_index); -/** - * fwu_mdata_check() - Check if the FWU metadata is valid - * @dev: FWU metadata device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_mdata_check(struct udevice *dev); - /** * fwu_revert_boot_index() - Revert the active index in the FWU metadata * @@ -327,20 +142,6 @@ int fwu_mdata_check(struct udevice *dev); */ int fwu_revert_boot_index(void); -/** - * fwu_verify_mdata() - Verify the FWU metadata - * @mdata: FWU metadata structure - * @pri_part: FWU metadata partition is primary or secondary - * - * Verify the FWU metadata by computing the CRC32 for the metadata - * structure and comparing it against the CRC32 value stored as part - * of the structure. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part); - /** * fwu_accept_image() - Set the Acceptance bit for the image * @img_type_id: GUID of the image type for which the accepted bit is to be diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index 77142c5376c..c34838435e6 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -33,26 +33,6 @@ enum { BOTH_PARTS, }; -static int fwu_get_dev_mdata(struct udevice **dev, struct fwu_mdata *mdata) -{ - int ret; - - ret = uclass_first_device_err(UCLASS_FWU_MDATA, dev); - if (ret) { - log_debug("Cannot find fwu device\n"); - return ret; - } - - if (!mdata) - return 0; - - ret = fwu_get_mdata(*dev, mdata); - if (ret < 0) - log_debug("Unable to get valid FWU metadata\n"); - - return ret; -} - static int trial_counter_update(u16 *trial_state_ctr) { bool delete; @@ -282,136 +262,6 @@ ret_mdata: return err; } -/** - * fwu_verify_mdata() - Verify the FWU metadata - * @mdata: FWU metadata structure - * @pri_part: FWU metadata partition is primary or secondary - * - * Verify the FWU metadata by computing the CRC32 for the metadata - * structure and comparing it against the CRC32 value stored as part - * of the structure. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part) -{ - u32 calc_crc32; - void *buf; - - buf = &mdata->version; - calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); - - if (calc_crc32 != mdata->crc32) { - log_debug("crc32 check failed for %s FWU metadata partition\n", - pri_part ? "primary" : "secondary"); - return -EINVAL; - } - - return 0; -} - -/** - * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies - * - * Read both the metadata copies from the storage media, verify their checksum, - * and ascertain that both copies match. If one of the copies has gone bad, - * restore it from the good copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_check_mdata_validity(void) -{ - int ret; - struct udevice *dev; - struct fwu_mdata pri_mdata; - struct fwu_mdata secondary_mdata; - uint mdata_parts[2]; - uint valid_partitions, invalid_partitions; - - ret = fwu_get_dev_mdata(&dev, NULL); - if (ret) - return ret; - - /* - * Check if the platform has defined its own - * function to check the metadata partitions' - * validity. If so, that takes precedence. - */ - ret = fwu_mdata_check(dev); - if (!ret || ret != -ENOSYS) - return ret; - - /* - * Two FWU metadata partitions are expected. - * If we don't have two, user needs to create - * them first - */ - valid_partitions = 0; - ret = fwu_get_mdata_part_num(dev, mdata_parts); - if (ret < 0) { - log_debug("Error getting the FWU metadata partitions\n"); - return -ENOENT; - } - - ret = fwu_read_mdata_partition(dev, &pri_mdata, mdata_parts[0]); - if (!ret) { - ret = fwu_verify_mdata(&pri_mdata, 1); - if (!ret) - valid_partitions |= PRIMARY_PART; - } - - ret = fwu_read_mdata_partition(dev, &secondary_mdata, mdata_parts[1]); - if (!ret) { - ret = fwu_verify_mdata(&secondary_mdata, 0); - if (!ret) - valid_partitions |= SECONDARY_PART; - } - - if (valid_partitions == (PRIMARY_PART | SECONDARY_PART)) { - /* - * Before returning, check that both the - * FWU metadata copies are the same. If not, - * populate the secondary partition from the - * primary partition copy. - */ - if (!memcmp(&pri_mdata, &secondary_mdata, - sizeof(struct fwu_mdata))) { - ret = 0; - } else { - log_info("Both FWU metadata copies are valid but do not match."); - log_info(" Restoring the secondary partition from the primary\n"); - ret = fwu_write_mdata_partition(dev, &pri_mdata, - mdata_parts[1]); - if (ret) - log_debug("Restoring secondary FWU metadata partition failed\n"); - } - goto out; - } - - if (!(valid_partitions & BOTH_PARTS)) { - log_info("Both FWU metadata partitions invalid\n"); - ret = -EBADMSG; - goto out; - } - - invalid_partitions = valid_partitions ^ BOTH_PARTS; - ret = fwu_write_mdata_partition(dev, - (invalid_partitions == PRIMARY_PART) ? - &secondary_mdata : &pri_mdata, - (invalid_partitions == PRIMARY_PART) ? - mdata_parts[0] : mdata_parts[1]); - - if (ret) - log_debug("Restoring %s FWU metadata partition failed\n", - (invalid_partitions == PRIMARY_PART) ? - "primary" : "secondary"); - -out: - return ret; -} - /** * fwu_get_active_index() - Get active_index from the FWU metadata * @active_idx: active_index value to be read @@ -424,19 +274,14 @@ out: */ int fwu_get_active_index(uint *active_idx) { - int ret; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; - - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; + int ret = 0; + struct fwu_mdata *mdata = &g_mdata; /* * Found the FWU metadata partition, now read the active_index * value */ - *active_idx = mdata.active_index; + *active_idx = mdata->active_index; if (*active_idx >= CONFIG_FWU_NUM_BANKS) { log_debug("Active index value read is incorrect\n"); ret = -EINVAL; @@ -457,30 +302,25 @@ int fwu_get_active_index(uint *active_idx) int fwu_set_active_index(uint active_idx) { int ret; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata *mdata = &g_mdata; if (active_idx >= CONFIG_FWU_NUM_BANKS) { log_debug("Invalid active index value\n"); return -EINVAL; } - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - /* * Update the active index and previous_active_index fields * in the FWU metadata */ - mdata.previous_active_index = mdata.active_index; - mdata.active_index = active_idx; + mdata->previous_active_index = mdata->active_index; + mdata->active_index = active_idx; /* * Now write this updated FWU metadata to both the * FWU metadata partitions */ - ret = fwu_update_mdata(dev, &mdata); + ret = fwu_sync_mdata(mdata, BOTH_PARTS); if (ret) { log_debug("Failed to update FWU metadata partitions\n"); ret = -EIO; @@ -510,15 +350,10 @@ int fwu_get_image_index(u8 *image_index) u8 alt_num; uint update_bank; efi_guid_t *image_guid, image_type_id; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata *mdata = &g_mdata; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_bank_info; - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - ret = fwu_plat_get_update_index(&update_bank); if (ret) { log_debug("Failed to get the FWU update bank\n"); @@ -539,11 +374,11 @@ int fwu_get_image_index(u8 *image_index) */ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { if (!guidcmp(&image_type_id, - &mdata.img_entry[i].image_type_uuid)) { - img_entry = &mdata.img_entry[i]; + &mdata->img_entry[i].image_type_uuid)) { + img_entry = &mdata->img_entry[i]; img_bank_info = &img_entry->img_bank_info[update_bank]; image_guid = &img_bank_info->image_uuid; - ret = fwu_plat_get_alt_num(dev, image_guid, &alt_num); + ret = fwu_plat_get_alt_num(g_dev, image_guid, &alt_num); if (ret) { log_debug("alt_num not found for partition with GUID %pUs\n", image_guid); @@ -578,26 +413,21 @@ int fwu_revert_boot_index(void) { int ret; u32 cur_active_index; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; - - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; + struct fwu_mdata *mdata = &g_mdata; /* * Swap the active index and previous_active_index fields * in the FWU metadata */ - cur_active_index = mdata.active_index; - mdata.active_index = mdata.previous_active_index; - mdata.previous_active_index = cur_active_index; + cur_active_index = mdata->active_index; + mdata->active_index = mdata->previous_active_index; + mdata->previous_active_index = cur_active_index; /* * Now write this updated FWU metadata to both the * FWU metadata partitions */ - ret = fwu_update_mdata(dev, &mdata); + ret = fwu_sync_mdata(mdata, BOTH_PARTS); if (ret) { log_debug("Failed to update FWU metadata partitions\n"); ret = -EIO; @@ -624,16 +454,11 @@ int fwu_revert_boot_index(void) static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action) { int ret, i; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata *mdata = &g_mdata; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_bank_info; - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - - img_entry = &mdata.img_entry[0]; + img_entry = &mdata->img_entry[0]; for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) { img_bank_info = &img_entry[i].img_bank_info[bank]; @@ -642,7 +467,7 @@ static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action) else img_bank_info->accepted = 0; - ret = fwu_update_mdata(dev, &mdata); + ret = fwu_sync_mdata(mdata, BOTH_PARTS); goto out; } } @@ -777,8 +602,6 @@ static int fwu_boottime_checks(void *ctx, struct event *event) { int ret; u32 boot_idx, active_idx; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; /* Don't have boot time checks on sandbox */ if (IS_ENABLED(CONFIG_SANDBOX)) { @@ -786,9 +609,17 @@ static int fwu_boottime_checks(void *ctx, struct event *event) return 0; } - ret = fwu_check_mdata_validity(); - if (ret) - return 0; + ret = uclass_first_device_err(UCLASS_FWU_MDATA, &g_dev); + if (ret) { + log_debug("Cannot find fwu device\n"); + return ret; + } + + ret = fwu_get_verified_mdata(NULL); + if (ret) { + log_debug("Unable to read meta-data\n"); + return ret; + } /* * Get the Boot Index, i.e. the bank from @@ -824,11 +655,7 @@ static int fwu_boottime_checks(void *ctx, struct event *event) if (efi_init_obj_list() != EFI_SUCCESS) return 0; - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - - in_trial = in_trial_state(&mdata); + in_trial = in_trial_state(&g_mdata); if (!in_trial || (ret = fwu_trial_count_update()) > 0) ret = trial_counter_update(NULL); -- cgit v1.3.1 From 1e917a69e51dc27627dd667a70843cb0ac270849 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 6 Mar 2023 17:18:48 -0600 Subject: fwu: rename fwu_get_verified_mdata to fwu_get_mdata fwu_get_mdata() sounds more appropriate than fwu_get_verified_mdata() Signed-off-by: Jassi Brar Reviewed-by: Etienne Carriere Reviewed-by: Ilias Apalodimas Tested-by: Sughosh Ganu --- cmd/fwu_mdata.c | 2 +- include/fwu.h | 4 ++-- lib/fwu_updates/fwu.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c index 9b70340368a..5ecda455df6 100644 --- a/cmd/fwu_mdata.c +++ b/cmd/fwu_mdata.c @@ -46,7 +46,7 @@ int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag, int ret = CMD_RET_SUCCESS, res; struct fwu_mdata mdata; - res = fwu_get_verified_mdata(&mdata); + res = fwu_get_mdata(&mdata); if (res < 0) { log_err("Unable to get valid FWU metadata\n"); ret = CMD_RET_FAILURE; diff --git a/include/fwu.h b/include/fwu.h index 7b600ce0d7e..6affb73c4fb 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -80,7 +80,7 @@ int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * fwu_get_verified_mdata() - Read, verify and return the FWU metadata + * fwu_get_mdata() - Read, verify and return the FWU metadata * * Read both the metadata copies from the storage media, verify their checksum, * and ascertain that both copies match. If one of the copies has gone bad, @@ -88,7 +88,7 @@ int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); * * Return: 0 if OK, -ve on error */ -int fwu_get_verified_mdata(struct fwu_mdata *mdata); +int fwu_get_mdata(struct fwu_mdata *mdata); /** * fwu_get_active_index() - Get active_index from the FWU metadata diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index c34838435e6..525ac49af37 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -189,7 +189,7 @@ static inline int mdata_crc_check(struct fwu_mdata *mdata) } /** - * fwu_get_verified_mdata() - Read, verify and return the FWU metadata + * fwu_get_mdata() - Read, verify and return the FWU metadata * @mdata: Output FWU metadata read or NULL * * Read both the metadata copies from the storage media, verify their checksum, @@ -198,7 +198,7 @@ static inline int mdata_crc_check(struct fwu_mdata *mdata) * * Return: 0 if OK, -ve on error */ -int fwu_get_verified_mdata(struct fwu_mdata *mdata) +int fwu_get_mdata(struct fwu_mdata *mdata) { int err; bool parts_ok[2] = { false }; @@ -615,7 +615,7 @@ static int fwu_boottime_checks(void *ctx, struct event *event) return ret; } - ret = fwu_get_verified_mdata(NULL); + ret = fwu_get_mdata(NULL); if (ret) { log_debug("Unable to read meta-data\n"); return ret; -- cgit v1.3.1 From 4898679e190770ad19917dfc01bc192df0cdfdee Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Wed, 31 May 2023 00:29:14 -0500 Subject: FWU: Add FWU metadata access driver for MTD storage regions In the FWU Multi Bank Update feature, the information about the updatable images is stored as part of the metadata, on a separate region. Add a driver for reading from and writing to the metadata when the updatable images and the metadata are stored on a raw MTD region. The code is divided into core under drivers/fwu-mdata/ and some helper functions clubbed together under lib/fwu_updates/ Signed-off-by: Masami Hiramatsu Signed-off-by: Jassi Brar --- drivers/fwu-mdata/Kconfig | 15 +++ drivers/fwu-mdata/Makefile | 1 + drivers/fwu-mdata/raw_mtd.c | 269 ++++++++++++++++++++++++++++++++++++++++++++ include/fwu.h | 32 ++++++ lib/fwu_updates/Makefile | 1 + lib/fwu_updates/fwu_mtd.c | 185 ++++++++++++++++++++++++++++++ 6 files changed, 503 insertions(+) create mode 100644 drivers/fwu-mdata/raw_mtd.c create mode 100644 lib/fwu_updates/fwu_mtd.c (limited to 'include') diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig index 36c4479a59e..42736a5e43b 100644 --- a/drivers/fwu-mdata/Kconfig +++ b/drivers/fwu-mdata/Kconfig @@ -6,6 +6,11 @@ config FWU_MDATA FWU Metadata partitions reside on the same storage device which contains the other FWU updatable firmware images. +choice + prompt "Storage Layout Scheme" + depends on FWU_MDATA + default FWU_MDATA_GPT_BLK + config FWU_MDATA_GPT_BLK bool "FWU Metadata access for GPT partitioned Block devices" select PARTITION_TYPE_GUID @@ -14,3 +19,13 @@ config FWU_MDATA_GPT_BLK help Enable support for accessing FWU Metadata on GPT partitioned block devices. + +config FWU_MDATA_MTD + bool "Raw MTD devices" + depends on MTD + help + Enable support for accessing FWU Metadata on non-partitioned + (or non-GPT partitioned, e.g. partition nodes in devicetree) + MTD devices. + +endchoice diff --git a/drivers/fwu-mdata/Makefile b/drivers/fwu-mdata/Makefile index 3fee64c10c9..06c49747ba8 100644 --- a/drivers/fwu-mdata/Makefile +++ b/drivers/fwu-mdata/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_FWU_MDATA) += fwu-mdata-uclass.o obj-$(CONFIG_FWU_MDATA_GPT_BLK) += gpt_blk.o +obj-$(CONFIG_FWU_MDATA_MTD) += raw_mtd.o diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c new file mode 100644 index 00000000000..17e45179738 --- /dev/null +++ b/drivers/fwu-mdata/raw_mtd.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_FWU_MDATA + +#include +#include +#include + +#include +#include + +/* Internal helper structure to move data around */ +struct fwu_mdata_mtd_priv { + struct mtd_info *mtd; + char pri_label[50]; + char sec_label[50]; + u32 pri_offset; + u32 sec_offset; +}; + +enum fwu_mtd_op { + FWU_MTD_READ, + FWU_MTD_WRITE, +}; + +extern struct fwu_mtd_image_info fwu_mtd_images[]; + +static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size) +{ + return !do_div(size, mtd->erasesize); +} + +static int mtd_io_data(struct mtd_info *mtd, u32 offs, u32 size, void *data, + enum fwu_mtd_op op) +{ + struct mtd_oob_ops io_op = {}; + u64 lock_len; + size_t len; + void *buf; + int ret; + + if (!mtd_is_aligned_with_block_size(mtd, offs)) { + log_err("Offset unaligned with a block (0x%x)\n", mtd->erasesize); + return -EINVAL; + } + + /* This will expand erase size to align with the block size */ + lock_len = round_up(size, mtd->erasesize); + + ret = mtd_unlock(mtd, offs, lock_len); + if (ret && ret != -EOPNOTSUPP) + return ret; + + if (op == FWU_MTD_WRITE) { + struct erase_info erase_op = {}; + + erase_op.mtd = mtd; + erase_op.addr = offs; + erase_op.len = lock_len; + erase_op.scrub = 0; + + ret = mtd_erase(mtd, &erase_op); + if (ret) + goto lock; + } + + /* Also, expand the write size to align with the write size */ + len = round_up(size, mtd->writesize); + + buf = memalign(ARCH_DMA_MINALIGN, len); + if (!buf) { + ret = -ENOMEM; + goto lock; + } + memset(buf, 0xff, len); + + io_op.mode = MTD_OPS_AUTO_OOB; + io_op.len = len; + io_op.datbuf = buf; + + if (op == FWU_MTD_WRITE) { + memcpy(buf, data, size); + ret = mtd_write_oob(mtd, offs, &io_op); + } else { + ret = mtd_read_oob(mtd, offs, &io_op); + if (!ret) + memcpy(data, buf, size); + } + free(buf); + +lock: + mtd_lock(mtd, offs, lock_len); + + return ret; +} + +static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + struct mtd_info *mtd = mtd_priv->mtd; + u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset; + + return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ); +} + +static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + struct mtd_info *mtd = mtd_priv->mtd; + u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset; + + return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE); +} + +static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset) +{ + ofnode node, parts_node; + fdt_addr_t size = 0; + + parts_node = ofnode_by_compatible(dev_ofnode(dev), "fixed-partitions"); + node = ofnode_by_prop_value(parts_node, "label", part_name, strlen(part_name) + 1); + if (!ofnode_valid(node)) { + log_err("Warning: Failed to find partition by label <%s>\n", part_name); + return -ENOENT; + } + + *offset = ofnode_get_addr_size_index_notrans(node, 0, &size); + + return (int)size; +} + +static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + const fdt32_t *phandle_p = NULL; + struct udevice *mtd_dev; + struct mtd_info *mtd; + const char *label; + fdt_addr_t offset; + int ret, size; + u32 phandle; + ofnode bank; + int off_img; + + /* Find the FWU mdata storage device */ + phandle_p = ofnode_get_property(dev_ofnode(dev), + "fwu-mdata-store", &size); + if (!phandle_p) { + log_err("FWU meta data store not defined in device-tree\n"); + return -ENOENT; + } + + phandle = fdt32_to_cpu(*phandle_p); + + ret = device_get_global_by_ofnode(ofnode_get_by_phandle(phandle), + &mtd_dev); + if (ret) { + log_err("FWU: failed to get mtd device\n"); + return ret; + } + + mtd_probe_devices(); + + mtd_for_each_device(mtd) { + if (mtd->dev == mtd_dev) { + mtd_priv->mtd = mtd; + log_debug("Found the FWU mdata mtd device %s\n", mtd->name); + break; + } + } + if (!mtd_priv->mtd) { + log_err("Failed to find mtd device by fwu-mdata-store\n"); + return -ENODEV; + } + + /* Get the offset of primary and secondary mdata */ + ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 0, &label); + if (ret) + return ret; + strncpy(mtd_priv->pri_label, label, 50); + + ret = flash_partition_offset(mtd_dev, mtd_priv->pri_label, &offset); + if (ret <= 0) + return ret; + mtd_priv->pri_offset = offset; + + ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 1, &label); + if (ret) + return ret; + strncpy(mtd_priv->sec_label, label, 50); + + ret = flash_partition_offset(mtd_dev, mtd_priv->sec_label, &offset); + if (ret <= 0) + return ret; + mtd_priv->sec_offset = offset; + + off_img = 0; + + ofnode_for_each_subnode(bank, dev_ofnode(dev)) { + int bank_num, bank_offset, bank_size; + const char *bank_name; + ofnode image; + + ofnode_read_u32(bank, "id", &bank_num); + bank_name = ofnode_read_string(bank, "label"); + bank_size = flash_partition_offset(mtd_dev, bank_name, &offset); + if (bank_size <= 0) + return bank_size; + bank_offset = offset; + log_debug("Bank%d: %s [0x%x - 0x%x]\n", + bank_num, bank_name, bank_offset, bank_offset + bank_size); + + ofnode_for_each_subnode(image, bank) { + int image_num, image_offset, image_size; + const char *uuid; + + if (off_img == CONFIG_FWU_NUM_BANKS * + CONFIG_FWU_NUM_IMAGES_PER_BANK) { + log_err("DT provides more images than configured!\n"); + break; + } + + uuid = ofnode_read_string(image, "uuid"); + ofnode_read_u32(image, "id", &image_num); + ofnode_read_u32(image, "offset", &image_offset); + ofnode_read_u32(image, "size", &image_size); + + fwu_mtd_images[off_img].start = bank_offset + image_offset; + fwu_mtd_images[off_img].size = image_size; + fwu_mtd_images[off_img].bank_num = bank_num; + fwu_mtd_images[off_img].image_num = image_num; + strcpy(fwu_mtd_images[off_img].uuidbuf, uuid); + log_debug("\tImage%d: %s @0x%x\n\n", + image_num, uuid, bank_offset + image_offset); + off_img++; + } + } + + return 0; +} + +static int fwu_mdata_mtd_probe(struct udevice *dev) +{ + /* Ensure the metadata can be read. */ + return fwu_get_mdata(NULL); +} + +static struct fwu_mdata_ops fwu_mtd_ops = { + .read_mdata = fwu_mtd_read_mdata, + .write_mdata = fwu_mtd_write_mdata, +}; + +static const struct udevice_id fwu_mdata_ids[] = { + { .compatible = "u-boot,fwu-mdata-mtd" }, + { } +}; + +U_BOOT_DRIVER(fwu_mdata_mtd) = { + .name = "fwu-mdata-mtd", + .id = UCLASS_FWU_MDATA, + .of_match = fwu_mdata_ids, + .ops = &fwu_mtd_ops, + .probe = fwu_mdata_mtd_probe, + .of_to_plat = fwu_mdata_mtd_of_to_plat, + .priv_auto = sizeof(struct fwu_mdata_mtd_priv), +}; diff --git a/include/fwu.h b/include/fwu.h index 6affb73c4fb..ac5c5de8706 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -8,6 +8,8 @@ #include #include +#include +#include #include @@ -18,6 +20,12 @@ struct fwu_mdata_gpt_blk_priv { struct udevice *blk_dev; }; +struct fwu_mtd_image_info { + u32 start, size; + int bank_num, image_num; + char uuidbuf[UUID_STR_LEN + 1]; +}; + struct fwu_mdata_ops { /** * read_mdata() - Populate the asked FWU metadata copy @@ -251,4 +259,28 @@ u8 fwu_empty_capsule_checks_pass(void); */ int fwu_trial_state_ctr_start(void); +/** + * fwu_gen_alt_info_from_mtd() - Parse dfu_alt_info from metadata in mtd + * @buf: Buffer into which the dfu_alt_info is filled + * @len: Maximum characters that can be written in buf + * @mtd: Pointer to underlying MTD device + * + * Parse dfu_alt_info from metadata in mtd. Used for setting the env. + * + * Return: 0 if OK, -ve on error + */ +int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd); + +/** + * fwu_mtd_get_alt_num() - Mapping of fwu_plat_get_alt_num for MTD device + * @image_guid: Image GUID for which DFU alt number needs to be retrieved + * @alt_num: Pointer to the alt_num + * @mtd_dev: Name of mtd device instance + * + * To map fwu_plat_get_alt_num onto mtd based metadata implementation. + * + * Return: 0 if OK, -ve on error + */ +int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev); + #endif /* _FWU_H_ */ diff --git a/lib/fwu_updates/Makefile b/lib/fwu_updates/Makefile index 1993088e5b1..c9e3c06b489 100644 --- a/lib/fwu_updates/Makefile +++ b/lib/fwu_updates/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o +obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c new file mode 100644 index 00000000000..b73111ae24d --- /dev/null +++ b/lib/fwu_updates/fwu_mtd.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct fwu_mtd_image_info +fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK]; + +static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf) +{ + int num_images = ARRAY_SIZE(fwu_mtd_images); + + for (int i = 0; i < num_images; i++) + if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf)) + return &fwu_mtd_images[i]; + + return NULL; +} + +int fwu_mtd_get_alt_num(efi_guid_t *image_id, u8 *alt_num, + const char *mtd_dev) +{ + struct fwu_mtd_image_info *mtd_img_info; + char uuidbuf[UUID_STR_LEN + 1]; + fdt_addr_t offset, size = 0; + struct dfu_entity *dfu; + int i, nalt, ret; + + mtd_probe_devices(); + + uuid_bin_to_str(image_id->b, uuidbuf, UUID_STR_FORMAT_STD); + + mtd_img_info = mtd_img_by_uuid(uuidbuf); + if (!mtd_img_info) { + log_err("%s: Not found partition for image %s\n", __func__, uuidbuf); + return -ENOENT; + } + + offset = mtd_img_info->start; + size = mtd_img_info->size; + + ret = dfu_init_env_entities(NULL, NULL); + if (ret) + return -ENOENT; + + nalt = 0; + list_for_each_entry(dfu, &dfu_list, list) + nalt++; + + if (!nalt) { + log_warning("No entities in dfu_alt_info\n"); + dfu_free_entities(); + return -ENOENT; + } + + ret = -ENOENT; + for (i = 0; i < nalt; i++) { + dfu = dfu_get_entity(i); + + /* Only MTD RAW access */ + if (!dfu || dfu->dev_type != DFU_DEV_MTD || + dfu->layout != DFU_RAW_ADDR || + dfu->data.mtd.start != offset || + dfu->data.mtd.size != size) + continue; + + *alt_num = dfu->alt; + ret = 0; + break; + } + + dfu_free_entities(); + + log_debug("%s: %s -> %d\n", __func__, uuidbuf, *alt_num); + return ret; +} + +/** + * fwu_plat_get_alt_num() - Get the DFU Alt Num for the image from the platform + * @dev: FWU device + * @image_id: Image GUID for which DFU alt number needs to be retrieved + * @alt_num: Pointer to the alt_num + * + * Get the DFU alt number from the platform for the image specified by the + * image GUID. + * + * Note: This is a weak function and platforms can override this with + * their own implementation for obtaining the alt number value. + * + * Return: 0 if OK, -ve on error + */ +__weak int fwu_plat_get_alt_num(struct udevice *dev, efi_guid_t *image_id, + u8 *alt_num) +{ + return fwu_mtd_get_alt_num(image_id, alt_num, "nor1"); +} + +static int gen_image_alt_info(char *buf, size_t len, int sidx, + struct fwu_image_entry *img, struct mtd_info *mtd) +{ + char *p = buf, *end = buf + len; + int i; + + p += snprintf(p, end - p, "mtd %s", mtd->name); + if (end < p) { + log_err("%s:%d Run out of buffer\n", __func__, __LINE__); + return -E2BIG; + } + + /* + * List the image banks in the FWU mdata and search the corresponding + * partition based on partition's uuid. + */ + for (i = 0; i < CONFIG_FWU_NUM_BANKS; i++) { + struct fwu_mtd_image_info *mtd_img_info; + struct fwu_image_bank_info *bank; + char uuidbuf[UUID_STR_LEN + 1]; + u32 offset, size; + + /* Query a partition by image UUID */ + bank = &img->img_bank_info[i]; + uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD); + + mtd_img_info = mtd_img_by_uuid(uuidbuf); + if (!mtd_img_info) { + log_err("%s: Not found partition for image %s\n", __func__, uuidbuf); + break; + } + + offset = mtd_img_info->start; + size = mtd_img_info->size; + + p += snprintf(p, end - p, "%sbank%d raw %x %x", + i == 0 ? "=" : ";", i, offset, size); + if (end < p) { + log_err("%s:%d Run out of buffer\n", __func__, __LINE__); + return -E2BIG; + } + } + + if (i == CONFIG_FWU_NUM_BANKS) + return 0; + + return -ENOENT; +} + +int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd) +{ + struct fwu_mdata mdata; + int i, l, ret; + + ret = fwu_get_mdata(&mdata); + if (ret < 0) { + log_err("Failed to get the FWU mdata.\n"); + return ret; + } + + for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { + ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS, + &mdata.img_entry[i], mtd); + if (ret) + break; + + l = strlen(buf); + /* Replace the last ';' with '&' if there is another image. */ + if (i != CONFIG_FWU_NUM_IMAGES_PER_BANK - 1 && l) + buf[l - 1] = '&'; + len -= l; + buf += l; + } + + return ret; +} -- cgit v1.3.1 From 6b403ca4dcf4c68e2792c4e8b28e03b3cfe5db45 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Wed, 31 May 2023 00:29:56 -0500 Subject: fwu: DeveloperBox: add support for FWU Add code to support FWU_MULTI_BANK_UPDATE. The platform does not have gpt-partition storage for Banks and MetaData, rather it used SPI-NOR backed mtd regions for the purpose. Signed-off-by: Jassi Brar --- board/socionext/developerbox/Makefile | 1 + board/socionext/developerbox/developerbox.c | 8 ++ board/socionext/developerbox/fwu_plat.c | 37 +++++++ configs/synquacer_developerbox_defconfig | 8 ++ doc/board/socionext/developerbox.rst | 154 ++++++++++++++++++++++++++-- include/configs/synquacer.h | 10 ++ 6 files changed, 212 insertions(+), 6 deletions(-) create mode 100644 board/socionext/developerbox/fwu_plat.c (limited to 'include') diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile index 4a46de995a0..1acd067a7e4 100644 --- a/board/socionext/developerbox/Makefile +++ b/board/socionext/developerbox/Makefile @@ -7,3 +7,4 @@ # obj-y := developerbox.o +obj-$(CONFIG_FWU_MDATA_MTD) += fwu_plat.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index d92e1d09627..204e5a41a5b 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -20,6 +20,13 @@ #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { +#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE) + { + .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID, + .fw_name = u"DEVELOPERBOX-FIP", + .image_index = 1, + }, +#else { .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID, .fw_name = u"DEVELOPERBOX-UBOOT", @@ -35,6 +42,7 @@ struct efi_fw_image fw_images[] = { .fw_name = u"DEVELOPERBOX-OPTEE", .image_index = 3, }, +#endif }; struct efi_capsule_update_info update_info = { diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c new file mode 100644 index 00000000000..e724e702bdc --- /dev/null +++ b/board/socionext/developerbox/fwu_plat.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include + +#define DFU_ALT_BUF_LEN 256 + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + struct mtd_info *mtd; + int ret; + + memset(buf, 0, sizeof(buf)); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor1"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 0c37897c9ac..8e7236b5723 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -97,3 +97,11 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y +CONFIG_FWU_MULTI_BANK_UPDATE=y +CONFIG_FWU_MDATA=y +CONFIG_FWU_MDATA_MTD=y +CONFIG_FWU_NUM_BANKS=2 +CONFIG_FWU_NUM_IMAGES_PER_BANK=1 +CONFIG_CMD_FWU_METADATA=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst index 2d943c23be7..aa7080e26cd 100644 --- a/doc/board/socionext/developerbox.rst +++ b/doc/board/socionext/developerbox.rst @@ -57,14 +57,20 @@ Installation You can install the SNI_NOR_UBOOT.fd via NOR flash writer. -Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. -Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine +or other mezzanine which can connect to the LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the +board on again. The flash writer program will be started automatically; +don't forget to turn the DSW2-7 off again after flashing. -*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* +*!!CAUTION!! If you write the U-Boot image on wrong address, the board can +be bricked. See below page if you need to recover the bricked board. See +the following page for more details* https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html -When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: +When the serial flasher is running correctly it will show the following boot +messages printed to the LS-UART0 console:: /*------------------------------------------*/ @@ -81,7 +87,143 @@ Once the flasher tool is running we are ready flash the UEFI image:: flash rawwrite 200000 100000 >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << -*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* +*!!NOTE!! The flasher command parameter is different from the command for +board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the +size 100000 (1-five-0, 1M in hex).* -After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and +reset the board. + +Enable FWU Multi Bank Update +============================ + +DeveloperBox supports the FWU Multi Bank Update. You *MUST* update both +*SCP firmware* and *TF-A* for this feature. This will change the layout and +the boot process but you can switch back to the normal one by changing +the DSW 1-4 off. + +Configure U-Boot +---------------- + +To enable the FWU Multi Bank Update on the DeveloperBox board the +configs/synquacer_developerbox_defconfig enables default FWU configuration :: + + CONFIG_FWU_MULTI_BANK_UPDATE=y + CONFIG_FWU_MDATA=y + CONFIG_FWU_MDATA_MTD=y + CONFIG_FWU_NUM_BANKS=2 + CONFIG_FWU_NUM_IMAGES_PER_BANK=1 + CONFIG_CMD_FWU_METADATA=y + +And build it:: + + cd u-boot/ + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make synquacer_developerbox_defconfig + make -j `noproc` + cd ../ + +By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are +set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image +which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional). +You can use fiptool to compose the FIP image from those firmware images. + +Rebuild SCP firmware +-------------------- + +Rebuild SCP firmware which supports FWU Multi Bank Update as below:: + + cd SCP-firmware/ + OUT=./build/product/synquacer + ROMFW_FILE=$OUT/scp_romfw/$SCP_BUILD_MODE/bin/scp_romfw.bin + RAMFW_FILE=$OUT/scp_ramfw/$SCP_BUILD_MODE/bin/scp_ramfw.bin + ROMRAMFW_FILE=scp_romramfw_release.bin + + make CC=arm-none-eabi-gcc PRODUCT=synquacer MODE=release + tr "\000" "\377" < /dev/zero | dd of=${ROMRAMFW_FILE} bs=1 count=196608 + dd if=${ROMFW_FILE} of=${ROMRAMFW_FILE} bs=1 conv=notrunc seek=0 + dd if=${RAMFW_FILE} of=${ROMRAMFW_FILE} bs=1 seek=65536 + cd ../ + +And you can get the `scp_romramfw_release.bin` file. + +Rebuild OPTEE firmware +---------------------- + +Rebuild OPTEE to use in new-layout FIP as below:: + + cd optee_os/ + make -j`nproc` PLATFORM=synquacer ARCH=arm \ + CROSS_COMPILE64=aarch64-linux-gnu- CFG_ARM64_core=y \ + CFG_CRYPTO_WITH_CE=y CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y \ + CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 CFG_TEE_TA_LOG_LEVEL=1 + cp out/arm-plat-synquacer/core/tee-pager_v2.bin ../arm-trusted-firmware/ + +The produced `tee-pager_v2.bin` is to be used while building TF-A next. + + +Rebuild TF-A and FIP +-------------------- + +Rebuild TF-A which supports FWU Multi Bank Update as below:: + + cd arm-trusted-firmware/ + make CROSS_COMPILE=aarch64-linux-gnu- -j`nproc` PLAT=synquacer \ + TRUSTED_BOARD_BOOT=1 SPD=opteed SQ_RESET_TO_BL2=1 GENERATE_COT=1 \ + MBEDTLS_DIR=../mbedtls BL32=tee-pager_v2.bin \ + BL33=../u-boot/u-boot.bin all fip fiptool + +And make a FIP image.:: + + cp build/synquacer/release/fip.bin SPI_NOR_NEWFIP.fd + tools/fiptool/fiptool update --tb-fw build/synquacer/release/bl2.bin SPI_NOR_NEWFIP.fd + +UUIDs for the FWU Multi Bank Update +----------------------------------- + +FWU multi-bank update requires some UUIDs. The DeveloperBox platform uses +following UUIDs. + + - Location UUID for the FIP image: 17e86d77-41f9-4fd7-87ec-a55df9842de5 + - Image type UUID for the FIP image: 10c36d7d-ca52-b843-b7b9-f9d6c501d108 + - Image UUID for Bank0 : 5a66a702-99fd-4fef-a392-c26e261a2828 + - Image UUID for Bank1 : a8f868a1-6e5c-4757-878d-ce63375ef2c0 + +These UUIDs are used for making a FWU metadata image. + +u-boot$ ./tools/mkfwumdata -i 1 -b 2 \ + 17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \ + ../devbox-fwu-mdata.img + +Create Accept & Revert capsules + +u-boot$ ./tools/mkeficapsule -A -g 7d6dc310-52ca-43b8-b7b9-f9d6c501d108 NEWFIP_accept.Cap +u-boot$ ./tools/mkeficapsule -R NEWFIP_revert.Cap + +Install via flash writer +------------------------ + +As explained in above section, the new FIP image and the FWU metadata image +can be installed via NOR flash writer. + +Once the flasher tool is running we are ready to flash the images.:: +Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.:: + + flash rawwrite 600000 180000 + flash rawwrite a00000 180000 + >> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) << + + flash rawwrite 500000 1000 + flash rawwrite 530000 1000 + >> Send devbox-fwu-mdata.img via XMODEM (Control-A S in minicom) << + +And write the new SCP firmware.:: + + flash write cm3 + >> Send scp_romramfw_release.bin via XMODEM (Control-A S in minicom) << + +At last, turn on the DSW 3-4 on the board, and reboot. +Note that if DSW 3-4 is turned off, the DeveloperBox will boot from +the original EDK2 firmware (or non-FWU U-Boot if you already installed). diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 8f44c6f66a9..cd7359c2f8a 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -40,19 +40,29 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEFAULT_DFU_ALT_INFO +#else #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ "mtd nor1=u-boot.bin raw 200000 100000;" \ "fip.bin raw 180000 78000;" \ "optee.bin raw 500000 100000\0" +#endif /* GUIDs for capsule updatable firmware images */ #define DEVELOPERBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \ 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00) +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEVELOPERBOX_FIP_IMAGE_GUID \ + EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \ + 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08) +#else #define DEVELOPERBOX_FIP_IMAGE_GUID \ EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \ 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98) +#endif #define DEVELOPERBOX_OPTEE_IMAGE_GUID \ EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \ -- cgit v1.3.1 From 495fc04b6d24f3d4cb1661c85e2da1a7fa35ac92 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 31 May 2023 00:51:25 +0200 Subject: net: phy: Unpublish phy_connect_dev() The phy_connect_dev() is legacy API, now that there are no users, make it internal to phy.c and unpublish it from headers. Signed-off-by: Marek Vasut Reviewed-by: Ramon Fried --- drivers/net/phy/phy.c | 4 ++-- include/phy.h | 9 --------- 2 files changed, 2 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 0eeb0cb3a85..ae21acb059b 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -812,8 +812,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask) return get_phy_device_by_mask(bus, phy_mask); } -void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, - phy_interface_t interface) +static void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, + phy_interface_t interface) { /* Soft Reset the PHY */ phy_reset(phydev); diff --git a/include/phy.h b/include/phy.h index 247223d92be..f023a3c2685 100644 --- a/include/phy.h +++ b/include/phy.h @@ -223,15 +223,6 @@ static inline struct phy_device *fixed_phy_create(ofnode node) #endif -/** - * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices - * @phydev: PHY device - * @dev: Ethernet device - * @interface: type of MAC-PHY interface - */ -void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, - phy_interface_t interface); - /** * phy_connect() - Creates a PHY device for the Ethernet interface * Creates a PHY device for the PHY at the given address, if one doesn't exist -- cgit v1.3.1 From 1be82afa807cc3cfacab29e3de0975d2cd99fa5d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 May 2023 09:17:16 +0200 Subject: global: Use proper project name U-Boot Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong Acked-by: Ilias Apalodimas Reviewed-by: Stefan Roese Reviewed-by: Qu Wenruo Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com --- arch/Kconfig.nxp | 2 +- arch/arc/include/asm/io.h | 2 +- arch/arm/cpu/armv7/Kconfig | 2 +- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 2 +- arch/arm/dts/fsl-ls1028a.dtsi | 2 +- arch/arm/dts/meson-g12-common-u-boot.dtsi | 2 +- arch/arm/dts/meson-gx-u-boot.dtsi | 2 +- arch/arm/dts/rk3328-evb-u-boot.dtsi | 2 +- arch/arm/dts/rk3328.dtsi | 2 +- .../include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 2 +- .../include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- board/bosch/acc/acc.c | 2 +- board/bosch/shc/README | 2 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +- board/hisilicon/poplar/README | 2 +- board/isee/igep003x/board.c | 2 +- board/isee/igep00x0/igep00x0.c | 2 +- board/keymile/Kconfig | 8 ++++---- board/keymile/README | 2 +- board/kontron/sl-mx6ul/spl.c | 2 +- board/phytec/pcm058/README | 18 +++++++++--------- board/synopsys/hsdk/hsdk.c | 14 +++++++------- boot/boot_fit.c | 2 +- cmd/ufs.c | 2 +- common/spl/spl.c | 2 +- common/spl/spl_mmc.c | 2 +- doc/README.pcap | 2 +- doc/README.s5p4418 | 2 +- doc/SPL/README.spl-secure-boot | 4 ++-- doc/board/amlogic/p201.rst | 2 +- doc/board/amlogic/p212.rst | 2 +- doc/board/amlogic/s400.rst | 2 +- doc/board/emulation/qemu-arm.rst | 2 +- doc/board/nxp/ls1046ardb.rst | 2 +- doc/board/nxp/mx6sabresd.rst | 2 +- doc/board/rockchip/rockchip.rst | 6 +++--- doc/board/sifive/unmatched.rst | 2 +- doc/board/st/stm32mp1.rst | 2 +- doc/board/xen/xenguest_arm64.rst | 10 +++++----- doc/develop/driver-model/bind.rst | 2 +- doc/develop/driver-model/fs_firmware_loader.rst | 6 +++--- doc/develop/uefi/uefi.rst | 2 +- doc/usage/cmd/source.rst | 2 +- doc/usage/dfu.rst | 2 +- drivers/clk/clk-mux.c | 2 +- drivers/gpio/gpio-fxl6408.c | 2 +- drivers/mtd/nand/raw/Kconfig | 6 +++--- drivers/mtd/nand/raw/fsl_ifc_spl.c | 4 ++-- drivers/net/pfe_eth/pfe_hw.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 2 +- drivers/spi/spi-qup.c | 2 +- dts/Kconfig | 4 ++-- fs/btrfs/compat.h | 2 +- fs/btrfs/extent-io.h | 2 +- include/fsl_validate.h | 4 ++-- include/zynqmp_firmware.h | 2 +- test/py/tests/test_android/test_avb.py | 2 +- test/py/tests/test_cat/conftest.py | 2 +- test/py/tests/test_efi_bootmgr/conftest.py | 2 +- test/py/tests/test_efi_capsule/conftest.py | 2 +- test/py/tests/test_efi_secboot/conftest.py | 4 ++-- test/py/tests/test_eficonfig/conftest.py | 2 +- test/py/tests/test_fs/conftest.py | 12 ++++++------ test/py/tests/test_scp03.py | 2 +- test/py/tests/test_xxd/conftest.py | 2 +- 66 files changed, 103 insertions(+), 103 deletions(-) (limited to 'include') diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 6e1c44b7ea8..e75226bc434 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH default "" help Set the key hash for U-Boot here if public/private key pair used to - sign U-boot are different from the SRK hash put in the fuse. Example + sign U-Boot are different from the SRK hash put in the fuse. Example of a key hash is 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. Otherwise leave this empty. diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 6adc0ed42ba..c818b8bdaec 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -80,7 +80,7 @@ static inline void sync(void) /* * We add memory barriers for __raw_readX / __raw_writeX accessors same way as - * it is done for readX and writeX accessors as lots of U-boot driver uses + * it is done for readX and writeX accessors as lots of U-Boot driver uses * __raw_readX / __raw_writeX instead of proper accessor with barrier. */ #define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index e33e53636a0..ccc2f208677 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -110,7 +110,7 @@ config ARMV7_LPAE config ARMV7_SET_CORTEX_SMPEN bool help - Enable the ARM Cortex ACTLR.SMP enable bit in U-boot. + Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot. config SPL_ARMV7_SET_CORTEX_SMPEN bool diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 7d5cf1594da..9f0fb369f77 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -145,7 +145,7 @@ config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help PSCI is Power State Coordination Interface defined by ARM. - The PSCI in U-boot provides a general framework and each platform + The PSCI in U-Boot provides a general framework and each platform can implement their own specific PSCI functions. Say Y here to enable PSCI support on ARMv8 platform. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 6f3fe7ca6e0..1ddf9473a30 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -125,7 +125,7 @@ mcinitcmd: This environment variable is defined to initiate MC and DPL deploymen from the location where it is stored(NOR, NAND, SD, SATA, USB)during u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied - during U-boot booting.However the MC, DPC and DPL can be applied from + during U-Boot booting.However the MC, DPC and DPL can be applied from console independently. The variable needs to be set from the console once and then on rebooting the parameters set in the variable will automatically be diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 06b36cc6586..dde0c4091f1 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -51,7 +51,7 @@ idle-states { /* - * PSCI node is not added default, U-boot will add missing + * PSCI node is not added default, U-Boot will add missing * parts if it determines to use PSCI. */ entry-method = "psci"; diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index efa6a0570bd..8070b62af5b 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -5,7 +5,7 @@ */ / { - /* Keep HW order from U-boot */ + /* Keep HW order from U-Boot */ aliases { /delete-property/ mmc0; /delete-property/ mmc1; diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi index 9f123ab0421..9e0620f395e 100644 --- a/arch/arm/dts/meson-gx-u-boot.dtsi +++ b/arch/arm/dts/meson-gx-u-boot.dtsi @@ -5,7 +5,7 @@ */ / { - /* Keep HW order from U-boot */ + /* Keep HW order from U-Boot */ aliases { /delete-property/ mmc0; /delete-property/ mmc1; diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 4bfa0c2330b..95e497970ee 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -41,7 +41,7 @@ }; &gmac2phy { - /* Integrated PHY unsupported by U-boot */ + /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 27e45d5886a..e8d8f00be8a 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -984,7 +984,7 @@ }; /* - * U-boot Specific Change + * U-Boot Specific Change * * The OTG controller must come after the USB host pair for it * to work. This is likely due to lack of support for the USB diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index 1b02d484d98..c18c51ed2c7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -22,7 +22,7 @@ * * -PCIe * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: + * file. U-Boot will scan the PCI bus and for each device discovered: * -allocate a streamID * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' * -set a msi-map entry in the PEXn controller node in the diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index b36b6d3889f..140849d4e1f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -23,7 +23,7 @@ * * -PCIe * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: + * file. U-Boot will scan the PCI bus and for each device discovered: * -allocate a streamID * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' * -set a msi-map entry in the PEXn controller node in the diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index 4a0603d0f3f..62388b345e1 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -559,7 +559,7 @@ int board_mmc_init(struct bd_info *bis) gpio_direction_input(USDHC2_CD_GPIO); /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC2 * mmc1 USDHC4 */ diff --git a/board/bosch/shc/README b/board/bosch/shc/README index 2f206e0d551..74704cdc115 100644 --- a/board/bosch/shc/README +++ b/board/bosch/shc/README @@ -68,7 +68,7 @@ Netboot - see also doc/SPL/README.am335x-network - set the jumper into netboot mode -- compile the U-boot sources with: +- compile the U-Boot sources with: make am335x_shc_netboot_defconfig make all - copy the images into your tftp boot directory diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 1b08a2c5abf..af19a658b54 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -86,7 +86,7 @@ int board_mmc_init(struct bd_info *bis) int i, ret; /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc2 USDHC3 (eMMC) */ diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README index 99ed6ce295e..77dcc3ba115 100644 --- a/board/hisilicon/poplar/README +++ b/board/hisilicon/poplar/README @@ -30,7 +30,7 @@ CONNECTORS One connector for Smart Card One connector for TSI Note of warning: ================ -U-boot has a *strong* dependency with the l-loader and the arm trusted firmware +U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware repositories. The boot sequence is: diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 5462a3dea22..7dbb0800892 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards * and control IGEP0034 green and red LEDs. - * U-boot configures these pins as input pullup to detect board revision: + * U-Boot configures these pins as input pullup to detect board revision: * IGEP0034-LITE = 0b00 * IGEP0034 (FULL) = 0b01 * IGEP0033 = 0b1X diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index f1599306e61..0f0a9c592fc 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -47,7 +47,7 @@ U_BOOT_DRVINFO(igep_uart) = { * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because * this functionality is shared by USB HOST. - * Once USB reset is applied, U-boot configures these pins as input pullup to + * Once USB reset is applied, U-Boot configures these pins as input pullup to * detect board and revision: * IGEP0020-RF = 0b00 * IGEP0020-RC = 0b01 diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index bf899d005c4..c6576aa6523 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -123,7 +123,7 @@ config SYS_IVM_EEPROM_PAGE_LEN Page size of inventory in EEPROM. config PG_WCOM_UBOOT_UPDATE_SUPPORTED - bool "Enable U-boot Field Fail-Safe Update Functionality" + bool "Enable U-Boot Field Fail-Safe Update Functionality" select EVENT default n help @@ -132,7 +132,7 @@ config PG_WCOM_UBOOT_UPDATE_SUPPORTED from parallel NOR flash. config PG_WCOM_UBOOT_BOOTPACKAGE - bool "U-boot Is Part Of Factory Boot-Package Image" + bool "U-Boot Is Part Of Factory Boot-Package Image" default n help Indicates that u-boot will be a part of the factory programmed @@ -140,7 +140,7 @@ config PG_WCOM_UBOOT_BOOTPACKAGE Has to be set for original u-boot programmed at factory. config PG_WCOM_UBOOT_UPDATE_TEXT_BASE - hex "Text Base For U-boot Programmed Outside Factory" + hex "Text Base For U-Boot Programmed Outside Factory" default 0xFFFFFFFF help Text base of an updated u-boot that is not factory programmed but @@ -148,7 +148,7 @@ config PG_WCOM_UBOOT_UPDATE_TEXT_BASE Has to be set for original u-boot programmed at factory. config PG_WCOM_UBOOT_UPDATE - bool "U-boot Is Part Of Factory Boot-Package Image" + bool "U-Boot Is Part Of Factory Boot-Package Image" default n help Indicates that u-boot will be a part of the embedded software and diff --git a/board/keymile/README b/board/keymile/README index 4e5cfb142a3..99f27e576aa 100644 --- a/board/keymile/README +++ b/board/keymile/README @@ -1,4 +1,4 @@ -Field Fail-Save U-boot Update +Field Fail-Save U-Boot Update ----------------------------- Field Fail-Save u-boot update is a feature that allows save u-boot update of FOX and XMC products that are rolled out in the field. diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index bae0e70a657..a9d370bc854 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -101,7 +101,7 @@ int board_mmc_init(struct bd_info *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README index 687366bffbd..4b6984cd54f 100644 --- a/board/phytec/pcm058/README +++ b/board/phytec/pcm058/README @@ -37,12 +37,12 @@ not supported. Flashing U-Boot onto an SD card ------------------------------- -After a successful build, the generated SPL and U-boot binaries can be copied +After a successful build, the generated SPL and U-Boot binaries can be copied to an SD card. Adjust the SD card device as necessary: $ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1 -This is equivalent to separately copying the SPL and U-boot using: +This is equivalent to separately copying the SPL and U-Boot using: $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 @@ -50,11 +50,11 @@ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 The default bootscripts expect a kernel fit-image file named "fitImage" in the first partition and Linux ext4 rootfs in the second partition. -Flashing U-boot to the SPI Flash, for booting Linux from NAND +Flashing U-Boot to the SPI Flash, for booting Linux from NAND ------------------------------------------------------------- -The SD card created above can also be used to install the SPL and U-boot into -the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot. +The SD card created above can also be used to install the SPL and U-Boot into +the SPI flash. Boot U-Boot from the SD card as above, and stop at the autoboot. Then, clear the SPI flash: @@ -64,13 +64,13 @@ Then, clear the SPI flash: Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and copy to the SPI. The SPL is expected at an offset of 0x400, and its size is maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000 -bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks, +bytes. Assume U-Boot should fit into 640KiB, therefore 0x500 512-byte blocks, totalling 0xA0000 bytes. Adding these together: => mmc read ${loadaddr} 0x2 0x688 => sf write ${loadaddr} 0x400 0xD1000 -The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to +The SPL is located at offset 0x400, and U-Boot at 0x31400 in SPI flash, as to match the SD Card layout. This would allow, instead of reading from the SD Card above, with networking and TFTP correctly configured, the equivalent of: @@ -84,7 +84,7 @@ image) and "root" (which contains a ubifs root filesystem). The "bootm_size" variable in the environment -------------------------------------------- -By default, U-boot relocates the device tree towards the upper end of the RAM, +By default, U-Boot relocates the device tree towards the upper end of the RAM, which kernels using CONFIG_HIGHMEM=y may not be able to access during early -boot. With the bootm_size variable set to 0x30000000, U-boot relocates the +boot. With the bootm_size variable set to 0x30000000, U-Boot relocates the device tree to below this address instead. diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 4308c7e440a..6cbc89ae787 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -583,7 +583,7 @@ enum hsdk_axi_masters { * * Please read ARC HS Development IC Specification, section 17.2 for more * information about apertures configuration. - * NOTE: we intentionally modify default settings in U-boot. Default settings + * NOTE: we intentionally modify default settings in U-Boot. Default settings * are specified in "Table 111 CREG Address Decoder register reset values". */ @@ -942,7 +942,7 @@ static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc, int ret; if (board_mismatch()) { - printf("ERR: U-boot is not configured for this board!\n"); + printf("ERR: U-Boot is not configured for this board!\n"); return CMD_RET_FAILURE; } @@ -983,10 +983,10 @@ U_BOOT_CMD( /* * We may simply use static variable here to store init status, but we also want - * to avoid the situation when we reload U-boot via MDB after previous + * to avoid the situation when we reload U-Boot via MDB after previous * init is done but HW reset (board reset) isn't done. So let's store the * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will - * survive after U-boot is reloaded via MDB. + * survive after U-Boot is reloaded via MDB. */ #define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY) /* must be equal to INIT_MARKER_REGISTER reset value */ @@ -1008,7 +1008,7 @@ static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc, int ret; if (board_mismatch()) { - printf("ERR: U-boot is not configured for this board!\n"); + printf("ERR: U-Boot is not configured for this board!\n"); return CMD_RET_FAILURE; } @@ -1258,11 +1258,11 @@ int checkboard(void) printf("Board: Synopsys %s\n", board_name(get_board_type_runtime())); if (board_mismatch()) - printf("WARN: U-boot is configured NOT for this board but for %s!\n", + printf("WARN: U-Boot is configured NOT for this board but for %s!\n", board_name(get_board_type_config())); reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE; - printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled"); + printf("U-Boot autostart: %s\n", reg ? "enabled" : "disabled"); return 0; }; diff --git a/boot/boot_fit.c b/boot/boot_fit.c index 4a493b36847..9d394126563 100644 --- a/boot/boot_fit.c +++ b/boot/boot_fit.c @@ -67,7 +67,7 @@ void *locate_dtb_in_fit(const void *fit) header = (struct legacy_img_hdr *)fit; if (image_get_magic(header) != FDT_MAGIC) { - debug("No FIT image appended to U-boot\n"); + debug("No FIT image appended to U-Boot\n"); return NULL; } diff --git a/cmd/ufs.c b/cmd/ufs.c index d4a1e66c1bd..143e946370f 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /** - * ufs.c - UFS specific U-boot commands + * ufs.c - UFS specific U-Boot commands * * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com * diff --git a/common/spl/spl.c b/common/spl/spl.c index 72078a8ebc8..28124a8bdf6 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -321,7 +321,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image, spl_image->fdt_addr = (void *)dt_data; if (spl_image->os == IH_OS_U_BOOT) { - /* HACK: U-boot expects FDT at a specific address */ + /* HACK: U-Boot expects FDT at a specific address */ fdt_hack = spl_image->load_addr + spl_image->size; fdt_hack = (fdt_hack + 3) & ~3; debug("Relocating FDT to %p\n", spl_image->fdt_addr); diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index a0722167044..a665091b00f 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -250,7 +250,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image, return ret; if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) { - puts("Expected image is not found. Trying to start U-boot\n"); + puts("Expected image is not found. Trying to start U-Boot\n"); return -ENOENT; } diff --git a/doc/README.pcap b/doc/README.pcap index 8e30b93c663..10318ef0a9e 100644 --- a/doc/README.pcap +++ b/doc/README.pcap @@ -1,6 +1,6 @@ PCAP: -U-boot supports live Ethernet packet capture in PCAP(2.4) format. +U-Boot supports live Ethernet packet capture in PCAP(2.4) format. This is enabled by CONFIG_CMD_PCAP. The capture is stored on physical memory, and should be copied to diff --git a/doc/README.s5p4418 b/doc/README.s5p4418 index ac724d08a04..8ec7b05fd26 100644 --- a/doc/README.s5p4418 +++ b/doc/README.s5p4418 @@ -38,7 +38,7 @@ The source code for (the used?) LUbuntu 16.04 can be found at [5]. Links ===== -[1] FriendlyArm U-boot v2016.01: +[1] FriendlyArm U-Boot v2016.01: https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01 diff --git a/doc/SPL/README.spl-secure-boot b/doc/SPL/README.spl-secure-boot index f2f8d788837..982fbec654d 100644 --- a/doc/SPL/README.spl-secure-boot +++ b/doc/SPL/README.spl-secure-boot @@ -12,7 +12,7 @@ Methodology The SPL image is responsible for loading the next stage boot loader, which is the main u-boot image. For secure boot process on these platforms ROM verifies -SPL image, so to continue chain of trust SPL image verifies U-boot image using +SPL image, so to continue chain of trust SPL image verifies U-Boot image using spl_validate_uboot(). This function uses QorIQ Trust Architecture header -(appended to U-boot image) to validate the U-boot binary just before passing +(appended to U-Boot image) to validate the U-Boot binary just before passing control to it. diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst index 28aae98d990..13b732fc7e4 100644 --- a/doc/board/amlogic/p201.rst +++ b/doc/board/amlogic/p201.rst @@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/p212.rst b/doc/board/amlogic/p212.rst index c1b73e83b17..a872f32f0f4 100644 --- a/doc/board/amlogic/p212.rst +++ b/doc/board/amlogic/p212.rst @@ -50,7 +50,7 @@ the git tree published by the board vendor: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/s400.rst b/doc/board/amlogic/s400.rst index 59dda823755..205e7c38fa3 100644 --- a/doc/board/amlogic/s400.rst +++ b/doc/board/amlogic/s400.rst @@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 16f66388eb1..b42d924cc66 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -54,7 +54,7 @@ Note that for some odd reason qemu-system-aarch64 needs to be explicitly told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument ensures that output appears on the terminal. Use Ctrl-A X to quit. -Additional persistent U-boot environment support can be added as follows: +Additional persistent U-Boot environment support can be added as follows: - Create envstore.img using qemu-img:: diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index 35465d00612..49b4842b306 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -150,7 +150,7 @@ Then, launch openocd like:: openocd -f u-boot.tcl -You should see the U-boot SPL banner followed by the banner for U-Boot proper +You should see the U-Boot SPL banner followed by the banner for U-Boot proper in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a long time. If you don't see it, something has gone wrong. After a while, you should see the prompt. You can load an image using semihosting by running:: diff --git a/doc/board/nxp/mx6sabresd.rst b/doc/board/nxp/mx6sabresd.rst index fe15ba7b798..c9869f4a73a 100644 --- a/doc/board/nxp/mx6sabresd.rst +++ b/doc/board/nxp/mx6sabresd.rst @@ -53,7 +53,7 @@ This will generate the SPL and u-boot-dtb.img binaries. - Boot first from SD card as shown in the previous section -In U-boot change the eMMC partition config:: +In U-Boot change the eMMC partition config:: => mmc partconf 2 1 0 0 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 99376fb54c9..4c555e1c9c1 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -333,12 +333,12 @@ Note: Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. If all other boot options fail then it enters into a BootROM mode on the USB OTG port. -This method loads TPL/SPL on NAND with U-boot and kernel on SD card. +This method loads TPL/SPL on NAND with U-Boot and kernel on SD card. SD Card ^^^^^^^ -U-boot expects a GPT partition map and a boot directory structure with files on the SD card. +U-Boot expects a GPT partition map and a boot directory structure with files on the SD card. .. code-block:: none @@ -363,7 +363,7 @@ Boot partition: zImage rk3066a-mk808.dtb -To write a U-boot image to the SD card (assumed to be /dev/sda): +To write a U-Boot image to the SD card (assumed to be /dev/sda): .. code-block:: bash diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst index de2aab59bb1..c515949066f 100644 --- a/doc/board/sifive/unmatched.rst +++ b/doc/board/sifive/unmatched.rst @@ -558,7 +558,7 @@ for partitions one through three respectively. --new=3:10280:10535 --change-name=3:env --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \ /dev/mtdblock0 -Write U-boot SPL and U-boot to their partitions. +Write U-Boot SPL and U-Boot to their partitions. .. code-block:: none diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index c0b1daa0418..63b44776ffc 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -345,7 +345,7 @@ Build Procedure - BL33=u-boot-nodtb.bin - BL33_CFG=u-boot.dtb - You can also update a existing FIP after U-boot compilation with fiptool, + You can also update a existing FIP after U-Boot compilation with fiptool, a tool provided by TF-A_:: # fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb fip-stm32mp157c-ev1.bin diff --git a/doc/board/xen/xenguest_arm64.rst b/doc/board/xen/xenguest_arm64.rst index 1327f88f990..e9bdaf7ffb2 100644 --- a/doc/board/xen/xenguest_arm64.rst +++ b/doc/board/xen/xenguest_arm64.rst @@ -6,7 +6,7 @@ Xen guest ARM64 board This board specification ------------------------ -This board is to be run as a virtual Xen [1] guest with U-boot as its primary +This board is to be run as a virtual Xen [1] guest with U-Boot as its primary bootloader. Xen is a type 1 hypervisor that allows multiple operating systems to run simultaneously on a single physical server. Xen is capable of running virtual machines in both full virtualization and para-virtualization (PV) @@ -16,7 +16,7 @@ Paravirtualized drivers are a special type of device drivers that are used in a guest system in the Xen domain and perform I/O operations using a special interface provided by the virtualization system and the host system. -Xen support for U-boot is implemented by introducing a new Xen guest ARM64 +Xen support for U-Boot is implemented by introducing a new Xen guest ARM64 board and porting essential drivers from MiniOS [3] as well as some of the work previously done by NXP [4]: @@ -39,7 +39,7 @@ previously done by NXP [4]: Board limitations ----------------- -1. U-boot runs without MMU enabled at the early stages. +1. U-Boot runs without MMU enabled at the early stages. According to Xen on ARM ABI (xen/include/public/arch-arm.h): all memory which is shared with other entities in the system (including the hypervisor and other guests) must reside in memory which is mapped as Normal Inner @@ -54,14 +54,14 @@ Board limitations 2. No serial console until MMU is up. Because data cache maintenance is required until the MMU setup the early/debug serial console is not implemented. Therefore, we do not have - usual prints like U-boot’s banner etc. until the serial driver is + usual prints like U-Boot’s banner etc. until the serial driver is initialized. 3. Single RAM bank supported. If a Xen guest is given much memory it is possible that Xen allocates two memory banks for it. The first one is allocated under 4GB address space and in some cases may represent the whole guest’s memory. It is assumed that - U-boot most likely won’t require high memory bank for its work andlaunching + U-Boot most likely won’t require high memory bank for its work andlaunching OS, so it is enough to take the first one. diff --git a/doc/develop/driver-model/bind.rst b/doc/develop/driver-model/bind.rst index b19661b5fe2..0d0d40734c9 100644 --- a/doc/develop/driver-model/bind.rst +++ b/doc/develop/driver-model/bind.rst @@ -7,7 +7,7 @@ Binding/unbinding a driver This document aims to describe the bind and unbind commands. For debugging purpose, it should be useful to bind or unbind a driver from -the U-boot command line. +the U-Boot command line. The unbind command calls the remove device driver callback and unbind the device from its driver. diff --git a/doc/develop/driver-model/fs_firmware_loader.rst b/doc/develop/driver-model/fs_firmware_loader.rst index b0823700a90..149b8b436ec 100644 --- a/doc/develop/driver-model/fs_firmware_loader.rst +++ b/doc/develop/driver-model/fs_firmware_loader.rst @@ -92,9 +92,9 @@ For example of getting DT phandle from /chosen and creating instance: if (ret) return ret; -Firmware loader driver is also designed to support U-boot environment +Firmware loader driver is also designed to support U-Boot environment variables, so all these data from FDT can be overwritten -through the U-boot environment variable during run time. +through the U-Boot environment variable during run time. For examples: @@ -110,7 +110,7 @@ fw_ubi_volume: When above environment variables are set, environment values would be used instead of data from FDT. The benefit of this design allows user to change storage attribute data -at run time through U-boot console and saving the setting as default +at run time through U-Boot console and saving the setting as default environment values in the storage for the next power cycle, so no compilation is required for both driver and FDT. diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index ffe25ca2318..ef0987c355c 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -330,7 +330,7 @@ bit in OsIndications variable with => setenv -e -nv -bs -rt -v OsIndications =0x0000000000000004 -Since U-boot doesn't currently support SetVariable at runtime, its value +Since U-Boot doesn't currently support SetVariable at runtime, its value won't be taken over across the reboot. If this is the case, you can skip this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS) set. diff --git a/doc/usage/cmd/source.rst b/doc/usage/cmd/source.rst index 61a45059096..a5c5204a28b 100644 --- a/doc/usage/cmd/source.rst +++ b/doc/usage/cmd/source.rst @@ -161,7 +161,7 @@ The boot scripts (boot.scr) is created with: mkimage -T script -n 'Test script' -d boot.txt boot.scr -The script can be execute in U-boot like this: +The script can be execute in U-Boot like this: .. code-block:: diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst index ed47ff561e3..68cacbbef66 100644 --- a/doc/usage/dfu.rst +++ b/doc/usage/dfu.rst @@ -9,7 +9,7 @@ Overview The Device Firmware Upgrade (DFU) allows to download and upload firmware to/from U-Boot connected over USB. -U-boot follows the Universal Serial Bus Device Class Specification for +U-Boot follows the Universal Serial Bus Device Class Specification for Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org). U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 184d426d0b3..017f25f7a5a 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -184,7 +184,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, if (!mux) return ERR_PTR(-ENOMEM); - /* U-boot specific assignments */ + /* U-Boot specific assignments */ mux->parent_names = parent_names; mux->num_parents = num_parents; diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index 902da050fbf..ca7aa14eeb2 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -27,7 +27,7 @@ * https://patchwork.kernel.org/patch/9148419/ * - the Toradex version by Max Krummenacher : * http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx - * - the U-boot PCA953x driver by Peng Fan : + * - the U-Boot PCA953x driver by Peng Fan : * drivers/gpio/pca953x_gpio.c * * TODO: diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d115fcf841f..d624589a892 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -553,7 +553,7 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS bool "Enable use of 1st stage bootloader timing for NAND" depends on NAND_ZYNQ help - This flag prevent U-boot reconfigure NAND flash controller and reuse + This flag prevent U-Boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. config NAND_OCTEONTX @@ -732,10 +732,10 @@ config SYS_NAND_BAD_BLOCK_POS default 5 if HAS_NAND_SMALL_BADBLOCK_POS config SYS_NAND_U_BOOT_LOCATIONS - bool "Define U-boot binaries locations in NAND" + bool "Define U-Boot binaries locations in NAND" help Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. - This option should not be enabled when compiling U-boot for boards + This option should not be enabled when compiling U-Boot for boards defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/.h file. diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 60a865b5667..c67065eaf8c 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -275,8 +275,8 @@ void nand_boot(void) #ifdef CONFIG_CHAIN_OF_TRUST /* - * U-Boot header is appended at end of U-boot image, so - * calculate U-boot header address using U-boot header size. + * U-Boot header is appended at end of U-Boot image, so + * calculate U-Boot header address using U-Boot header size. */ #define FSL_U_BOOT_HDR_ADDR \ ((CFG_SYS_NAND_U_BOOT_START + \ diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c index 4db6f3158c3..9f2f92d116d 100644 --- a/drivers/net/pfe_eth/pfe_hw.c +++ b/drivers/net/pfe_eth/pfe_hw.c @@ -814,7 +814,7 @@ static inline void class_set_config(struct class_cfg *cfg) writel(0x1, CLASS_AXI_CTRL); /*Make Util AXI transactions non-bufferable */ - /*Util is disabled in U-boot, do it from here */ + /*Util is disabled in U-Boot, do it from here */ writel(0x1, UTIL_AXI_CTRL); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index e063b51c6dd..a7e0099045f 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 -/* Used to distinguish between different possible callers (U-boot/Linux) */ +/* Used to distinguish between different possible callers (U-Boot/Linux) */ #define COMPHY_CALLER_UBOOT (0x1 << 21) #define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 7b64532e50b..572cef1694c 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -9,7 +9,7 @@ * Author: Robert Marko * Author: Luka Kovacic * - * Based on stock U-boot and Linux drivers + * Based on stock U-Boot and Linux drivers */ #include diff --git a/dts/Kconfig b/dts/Kconfig index 3b7489f0f87..9152f5885e9 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -171,7 +171,7 @@ config OF_LIST default DEFAULT_DEVICE_TREE help This option specifies a list of device tree files to use for DT - control. These will be packaged into a FIT. At run-time, U-boot + control. These will be packaged into a FIT. At run-time, U-Boot or SPL will select the correct DT to use by examining the hardware (e.g. reading a board ID value). This is a list of device tree files (without the directory or .dtb suffix) @@ -254,7 +254,7 @@ config DTB_RESELECT config MULTI_DTB_FIT bool "Support embedding several DTBs in a FIT image for u-boot" help - This option provides hooks to allow U-boot to parse an + This option provides hooks to allow U-Boot to parse an appended FIT image and enable board specific code to then select the correct DTB to be used. Use this if you need to support multiple DTBs but don't use the SPL. diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h index 9cf8a10c76c..02173dea5f4 100644 --- a/fs/btrfs/compat.h +++ b/fs/btrfs/compat.h @@ -46,7 +46,7 @@ /* * Read data from device specified by @desc and @part * - * U-boot equivalent of pread(). + * U-Boot equivalent of pread(). * * Return the bytes of data read. * Return <0 for error. diff --git a/fs/btrfs/extent-io.h b/fs/btrfs/extent-io.h index 6b0c87da969..5c5c579d1ea 100644 --- a/fs/btrfs/extent-io.h +++ b/fs/btrfs/extent-io.h @@ -8,7 +8,7 @@ * Use pointer to provide better alignment. * - Remove max_cache_size related interfaces * Includes free_extent_buffer_nocache() - * As we don't cache eb in U-boot. + * As we don't cache eb in U-Boot. * - Include headers * * Write related functions are kept as we still need to modify dummy extent diff --git a/include/fsl_validate.h b/include/fsl_validate.h index fbcbd424967..66a5883f1f7 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -275,9 +275,9 @@ int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); /* - * This function is used to validate the main U-boot binary from + * This function is used to validate the main U-Boot binary from * SPL just before passing control to it using QorIQ Trust - * Architecture header (appended to U-boot image). + * Architecture header (appended to U-Boot image). */ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f7a4a39d350..1192d5902dc 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -35,7 +35,7 @@ enum pm_api_id { PM_FPGA_LOAD = 22, PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, - /* ID 25 is been used by U-boot to process secure boot images */ + /* ID 25 is been used by U-Boot to process secure boot images */ /* Secure library generic API functions */ PM_SECURE_SHA = 26, PM_SECURE_RSA = 27, diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py index bc5c5b55821..238b48c90fa 100644 --- a/test/py/tests/test_android/test_avb.py +++ b/test/py/tests/test_android/test_avb.py @@ -5,7 +5,7 @@ # Android Verified Boot 2.0 Test """ -This tests Android Verified Boot 2.0 support in U-boot: +This tests Android Verified Boot 2.0 support in U-Boot: For additional details about how to build proper vbmeta partition check doc/android/avb2.rst diff --git a/test/py/tests/test_cat/conftest.py b/test/py/tests/test_cat/conftest.py index 058fe523521..fc396f50d32 100644 --- a/test/py/tests/test_cat/conftest.py +++ b/test/py/tests/test_cat/conftest.py @@ -13,7 +13,7 @@ def cat_data(u_boot_config): """Set up a file system to be used in cat tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_cat' image_path = u_boot_config.persistent_data_dir + '/cat.img' diff --git a/test/py/tests/test_efi_bootmgr/conftest.py b/test/py/tests/test_efi_bootmgr/conftest.py index eabafa54298..0eca025058e 100644 --- a/test/py/tests/test_efi_bootmgr/conftest.py +++ b/test/py/tests/test_efi_bootmgr/conftest.py @@ -12,7 +12,7 @@ def efi_bootmgr_data(u_boot_config): """Set up a file system to be used in UEFI bootmanager tests. Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index a337e629362..3e585b6c3d2 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -17,7 +17,7 @@ def efi_capsule_data(request, u_boot_config): for testing. request -- Pytest request object. - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' data_dir = mnt_point + CAPSULE_DATA_DIR diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py index 30ff7029438..ff7ac7c8101 100644 --- a/test/py/tests/test_efi_secboot/conftest.py +++ b/test/py/tests/test_efi_secboot/conftest.py @@ -14,7 +14,7 @@ def efi_boot_env(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A path to disk image to be used for testing @@ -139,7 +139,7 @@ def efi_boot_env_intca(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_eficonfig/conftest.py b/test/py/tests/test_eficonfig/conftest.py index f289df03626..0a82fbefd75 100644 --- a/test/py/tests/test_eficonfig/conftest.py +++ b/test/py/tests/test_eficonfig/conftest.py @@ -14,7 +14,7 @@ def efi_eficonfig_data(u_boot_config): tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index 9329ec6f1b2..0d87d180c7b 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -97,7 +97,7 @@ def pytest_generate_tests(metafunc): # Helper functions # def fstype_to_ubname(fs_type): - """Convert a file system type to an U-boot specific string + """Convert a file system type to an U-Boot specific string A generated string can be used as part of file system related commands or a config name in u-boot. Currently fat16 and fat32 are handled @@ -217,7 +217,7 @@ def fs_obj_basic(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for basic fs test, i.e. a triplet of file system type, @@ -339,7 +339,7 @@ def fs_obj_ext(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for extended fs test, i.e. a triplet of file system type, @@ -440,7 +440,7 @@ def fs_obj_mkdir(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for mkdir test, i.e. a duplet of file system type and @@ -471,7 +471,7 @@ def fs_obj_unlink(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for unlink test, i.e. a duplet of file system type and @@ -551,7 +551,7 @@ def fs_obj_symlink(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for basic fs test, i.e. a triplet of file system type, diff --git a/test/py/tests/test_scp03.py b/test/py/tests/test_scp03.py index 1f689252ddf..1a104b365f7 100644 --- a/test/py/tests/test_scp03.py +++ b/test/py/tests/test_scp03.py @@ -5,7 +5,7 @@ # SCP03 command test """ -This tests SCP03 command in U-boot. +This tests SCP03 command in U-Boot. For additional details check doc/usage/scp03.rst """ diff --git a/test/py/tests/test_xxd/conftest.py b/test/py/tests/test_xxd/conftest.py index 59285aadf40..f35b8f11136 100644 --- a/test/py/tests/test_xxd/conftest.py +++ b/test/py/tests/test_xxd/conftest.py @@ -13,7 +13,7 @@ def xxd_data(u_boot_config): """Set up a file system to be used in xxd tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_xxd' image_path = u_boot_config.persistent_data_dir + '/xxd.img' -- cgit v1.3.1 From e9500ba9e032bc5e976578e256582c86fcb62d0d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 May 2023 10:42:07 +0200 Subject: video: Add support for RGBA8888 format Add support for RGBA8888 32bpp format where pixels are picked in 32-bit integers, where the colors are stored in memory such that R is at lowest address, G after that, B after that, and A last. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/aa1de54b7d4ff46df6858f76d52634e0c5c71a4a.1684312924.git.michal.simek@amd.com --- drivers/video/video-uclass.c | 10 ++++++++-- include/video.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 8396bdfb11e..1b66a8061a7 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -220,14 +220,20 @@ u32 video_index_to_colour(struct video_priv *priv, unsigned int idx) break; case VIDEO_BPP32: if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { - if (priv->format == VIDEO_X2R10G10B10) + switch (priv->format) { + case VIDEO_X2R10G10B10: return (colours[idx].r << 22) | (colours[idx].g << 12) | (colours[idx].b << 2); - else + case VIDEO_RGBA8888: + return (colours[idx].r << 24) | + (colours[idx].g << 16) | + (colours[idx].b << 8) | 0xff; + default: return (colours[idx].r << 16) | (colours[idx].g << 8) | (colours[idx].b << 0); + } } break; default: diff --git a/include/video.h b/include/video.h index 29c4f51efb0..03434a81234 100644 --- a/include/video.h +++ b/include/video.h @@ -64,6 +64,7 @@ enum video_log2_bpp { enum video_format { VIDEO_UNKNOWN, + VIDEO_RGBA8888, VIDEO_X8B8G8R8, VIDEO_X8R8G8B8, VIDEO_X2R10G10B10, -- cgit v1.3.1 From dbec4f0b7f0c4c56fddb6cc3b70dbafba456985e Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 17 May 2023 10:42:11 +0200 Subject: xilinx: zynqmp: Enable the vidconsole by default Add the vidconsole flags for video serial console. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f1b58d1d1052bf2d8cb8b25af44ecbb567ebbd4a.1684312924.git.michal.simek@amd.com --- include/configs/xilinx_zynqmp.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 011f0034c50..995427db63c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -60,6 +60,9 @@ "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ "script_size_f=0x80000\0" \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ #if defined(CONFIG_MMC_SDHCI_ZYNQ) # define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) -- cgit v1.3.1 From 3e697627400fea74f2d4c5e63dac31eb557e9a83 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 23 May 2023 16:47:43 +0300 Subject: net: ldpaa_eth: fix the memory layout of the dpmac_get_counters() API Each MC commands has a specific predefined memory layout that gets interpreted by the firmware. The dpmac_get_counters() API memory layout is wrong, thus the results returned by the command are incorrect. Fix this by updating the offset of the counter field. Signed-off-by: Ioana Ciornei Reviewed-by: Ramon Fried Signed-off-by: Peng Fan --- include/fsl-mc/fsl_dpmac.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 1cea123a316..8f5e17fe222 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -84,7 +84,7 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPMAC_CMD_GET_COUNTER(cmd, type) \ - MC_CMD_OP(cmd, 1, 0, 64, enum dpmac_counter, type) + MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type) /* cmd, param, offset, width, type, arg_name */ #define DPMAC_RSP_GET_COUNTER(cmd, counter) \ -- cgit v1.3.1 From 13ca5c2f56a172a3df1d5b84a084ed437ea26cde Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 23 May 2023 16:47:44 +0300 Subject: net: ldpaa_eth: transform dpni_statistics from a struct to a union In order to simplify code, dpni_statistics can be written as a union. Using the raw accessors we can just loop through all the statistics from a page without trying to access each an every one independently. Make this change to a union. Signed-off-by: Ioana Ciornei Reviewed-by: Ramon Fried Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpni.c | 2 +- drivers/net/ldpaa_eth/ldpaa_eth.c | 4 +- include/fsl-mc/fsl_dpni.h | 143 +++++++++++++++++++++++++++----------- 3 files changed, 105 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index 5290be20c85..a31abbff71b 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -491,7 +491,7 @@ int dpni_get_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, uint8_t page, - struct dpni_statistics *stat) + union dpni_statistics *stat) { struct mc_command cmd = { 0 }; int err; diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 2cb6e9b7d70..fe901baf5a4 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -68,7 +68,7 @@ static const char *dpni_statistics[][DPNI_STATS_PER_PAGE] = { }; static void print_dpni_stats(const char *strings[], - struct dpni_statistics dpni_stats) + union dpni_statistics dpni_stats) { uint64_t *stat; int i; @@ -86,7 +86,7 @@ static void ldpaa_eth_get_dpni_counter(void) { int err = 0; unsigned int page = 0; - struct dpni_statistics dpni_stats; + union dpni_statistics dpni_stats; printf("DPNI counters ..\n"); for (page = 0; page < 3; page++) { diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index e5e7338192f..fc57c375ac1 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -258,13 +258,13 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_STATISTICS(cmd, stat) \ do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \ - MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \ - MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \ - MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \ + MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->raw.counter[0]); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->raw.counter[1]); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->raw.counter[2]); \ + MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->raw.counter[3]); \ + MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->raw.counter[4]); \ + MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->raw.counter[5]); \ + MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->raw.counter[6]); \ } while (0) enum net_prot { @@ -1257,40 +1257,101 @@ int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, enum dpni_confirmation_mode mode); -struct dpni_statistics { - /** - * Page_0 statistics structure - * @ingress_all_frames: Ingress frame count - * @ingress_all_bytes: Ingress byte count - * @ingress_multicast_frames: Ingress multicast frame count - * @ingress_multicast_bytes: Ingress multicast byte count - * @ingress_broadcast_frames: Ingress broadcast frame count - * @ingress_broadcast_bytes: Ingress broadcast byte count - * - * Page_1 statistics structure - * @egress_all_frames: Egress frame count - * @egress_all_bytes: Egress byte count - * @egress_multicast_frames: Egress multicast frame count - * @egress_multicast_bytes: Egress multicast byte count - * @egress_broadcast_frames: Egress broadcast frame count - * @egress_broadcast_bytes: Egress broadcast byte count - * - * Page_2 statistics structure - * @ingress_filtered_frames: Ingress filtered frame count - * @ingress_discarded_frames: Ingress discarded frame count - * @ingress_nobuffer_discards: Ingress discarded frame count due to - * lack of buffers. - * @egress_discarded_frames: Egress discarded frame count - * @egress_confirmed_frames: Egress confirmed frame count - */ - uint64_t counter0; - uint64_t counter1; - uint64_t counter2; - uint64_t counter3; - uint64_t counter4; - uint64_t counter5; - uint64_t counter6; +#define DPNI_STATISTICS_CNT 7 + +/** + * union dpni_statistics - Union describing the DPNI statistics + * @page_0: Page_0 statistics structure + * @page_0.ingress_all_frames: Ingress frame count + * @page_0.ingress_all_bytes: Ingress byte count + * @page_0.ingress_multicast_frames: Ingress multicast frame count + * @page_0.ingress_multicast_bytes: Ingress multicast byte count + * @page_0.ingress_broadcast_frames: Ingress broadcast frame count + * @page_0.ingress_broadcast_bytes: Ingress broadcast byte count + * @page_1: Page_1 statistics structure + * @page_1.egress_all_frames: Egress frame count + * @page_1.egress_all_bytes: Egress byte count + * @page_1.egress_multicast_frames: Egress multicast frame count + * @page_1.egress_multicast_bytes: Egress multicast byte count + * @page_1.egress_broadcast_frames: Egress broadcast frame count + * @page_1.egress_broadcast_bytes: Egress broadcast byte count + * @page_2: Page_2 statistics structure + * @page_2.ingress_filtered_frames: Ingress filtered frame count + * @page_2.ingress_discarded_frames: Ingress discarded frame count + * @page_2.ingress_nobuffer_discards: Ingress discarded frame count due to + * lack of buffers + * @page_2.egress_discarded_frames: Egress discarded frame count + * @page_2.egress_confirmed_frames: Egress confirmed frame count + * @page_3: Page_3 statistics structure + * @page_3.egress_dequeue_bytes: Cumulative count of the number of bytes + * dequeued from egress FQs + * @page_3.egress_dequeue_frames: Cumulative count of the number of frames + * dequeued from egress FQs + * @page_3.egress_reject_bytes: Cumulative count of the number of bytes in + * egress frames whose enqueue was rejected + * @page_3.egress_reject_frames: Cumulative count of the number of egress + * frames whose enqueue was rejected + * @page_4: Page_4 statistics structure: congestion points + * @page_4.cgr_reject_frames: number of rejected frames due to congestion point + * @page_4.cgr_reject_bytes: number of rejected bytes due to congestion point + * @page_5: Page_5 statistics structure: policer + * @page_5.policer_cnt_red: NUmber of red colored frames + * @page_5.policer_cnt_yellow: number of yellow colored frames + * @page_5.policer_cnt_green: number of green colored frames + * @page_5.policer_cnt_re_red: number of recolored red frames + * @page_5.policer_cnt_re_yellow: number of recolored yellow frames + * @page_6: Page_6 statistics structure + * @page_6.tx_pending_frames: total number of frames pending in egress FQs + * @raw: raw statistics structure, used to index counters + */ +union dpni_statistics { + struct { + u64 ingress_all_frames; + u64 ingress_all_bytes; + u64 ingress_multicast_frames; + u64 ingress_multicast_bytes; + u64 ingress_broadcast_frames; + u64 ingress_broadcast_bytes; + } page_0; + struct { + u64 egress_all_frames; + u64 egress_all_bytes; + u64 egress_multicast_frames; + u64 egress_multicast_bytes; + u64 egress_broadcast_frames; + u64 egress_broadcast_bytes; + } page_1; + struct { + u64 ingress_filtered_frames; + u64 ingress_discarded_frames; + u64 ingress_nobuffer_discards; + u64 egress_discarded_frames; + u64 egress_confirmed_frames; + } page_2; + struct { + u64 egress_dequeue_bytes; + u64 egress_dequeue_frames; + u64 egress_reject_bytes; + u64 egress_reject_frames; + } page_3; + struct { + u64 cgr_reject_frames; + u64 cgr_reject_bytes; + } page_4; + struct { + u64 policer_cnt_red; + u64 policer_cnt_yellow; + u64 policer_cnt_green; + u64 policer_cnt_re_red; + u64 policer_cnt_re_yellow; + } page_5; + struct { + u64 tx_pending_frames; + } page_6; + struct { + u64 counter[DPNI_STATISTICS_CNT]; + } raw; }; /** @@ -1308,7 +1369,7 @@ int dpni_get_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, uint8_t page, - struct dpni_statistics *stat); + union dpni_statistics *stat); /** * dpni_reset_statistics() - Clears DPNI statistics -- cgit v1.3.1 From 22df08d82eeb0ffd5aa3b7f15ca978dfb5cc8377 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 23 May 2023 16:47:46 +0300 Subject: net: ldpaa_eth: extend debug capabilities with DPMAC statistics The ldpaa_eth driver already had a DPMAC statistics dump, this patch extends the list of stats and adds a bit more structure to the code. For a bit more context, the DPAA2 u-boot software architecture uses a default network interface object - a DPNI - which, at runtime, will get connected to the currently used DPMAC object. Each time the .stop() eth callback is called, the DPMAC is destroyed thus any previous counters will get lost. As a preparation for the next patches, we add a software kept set of DPMAC counters which will get updated before each destroy operation takes place. Signed-off-by: Ioana Ciornei Reviewed-by: Ramon Fried Signed-off-by: Peng Fan --- drivers/net/ldpaa_eth/ldpaa_eth.c | 114 +++++++++++++------------------------- drivers/net/ldpaa_eth/ldpaa_eth.h | 34 ++++++++++++ include/fsl-mc/fsl_dpmac.h | 5 +- 3 files changed, 76 insertions(+), 77 deletions(-) (limited to 'include') diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 907e51da6e1..53c5b8ba2b1 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -79,8 +79,33 @@ static void ldpaa_eth_add_dpni_stats(struct udevice *dev, u64 *data) priv->dpni_stats[i] += data[i]; } -#ifdef DEBUG +static void ldpaa_eth_collect_dpmac_stats(struct udevice *dev, u64 *data) +{ + struct ldpaa_eth_priv *priv = dev_get_priv(dev); + int err, i; + u64 value; + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) { + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, i, + &value); + if (err) + printf("dpmac_get_counter(%d) failed\n", i); + + *(data + i) = value; + } +} + +static void ldpaa_eth_add_dpmac_stats(struct udevice *dev, u64 *data) +{ + struct ldpaa_eth_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) + priv->dpmac_stats[i] += data[i]; +} + +#ifdef DEBUG static void ldpaa_eth_dump_dpni_stats(struct udevice *dev, u64 *data) { int i; @@ -90,82 +115,13 @@ static void ldpaa_eth_dump_dpni_stats(struct udevice *dev, u64 *data) printf(" %s: %llu\n", ldpaa_eth_dpni_stat_strings[i], data[i]); } -static void ldpaa_eth_get_dpmac_counter(struct udevice *dev) +static void ldpaa_eth_dump_dpmac_stats(struct udevice *dev, u64 *data) { - struct ldpaa_eth_priv *priv = dev_get_priv(dev); - int err = 0; - u64 value; - - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_BYTE, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); - return; - } - printf("\nDPMAC counters ..\n"); - printf("DPMAC_CNT_ING_BYTE=%lld\n", value); - - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_FRAME_DISCARD, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD failed\n"); - return; - } - printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value); - - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_ALIGN_ERR, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n"); - return; - } - printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value); - - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_BYTE, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); - return; - } - printf("DPMAC_CNT_ING_BYTE=%lld\n", value); - - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_ERR_FRAME, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n"); - return; - } - printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value); - - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_EGR_BYTE , - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n"); - return; - } - printf("DPMAC_CNT_EGR_BYTE =%lld\n", value); + int i; - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_EGR_ERR_FRAME , - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n"); - return; - } - printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value); + printf("DPMAC counters:\n"); + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) + printf(" %s: %llu\n", ldpaa_eth_dpmac_stat_strings[i], data[i]); } #endif @@ -559,9 +515,15 @@ static void ldpaa_eth_stop(struct udevice *dev) } kfree(data); + data = kzalloc(sizeof(u64) * LDPAA_ETH_DPMAC_NUM_STATS, GFP_KERNEL); + if (data) { + ldpaa_eth_collect_dpmac_stats(dev, data); + ldpaa_eth_add_dpmac_stats(dev, data); #ifdef DEBUG - ldpaa_eth_get_dpmac_counter(dev); + ldpaa_eth_dump_dpmac_stats(dev, data); #endif + } + kfree(data); err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle, &dpmac_endpoint); diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index 62dc9dd3102..af082e34cae 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -142,6 +142,39 @@ static const char ldpaa_eth_dpni_stat_strings[][ETH_GSTRING_LEN] = { #define LDPAA_ETH_DPNI_NUM_STATS ARRAY_SIZE(ldpaa_eth_dpni_stat_strings) +static const char ldpaa_eth_dpmac_stat_strings[][ETH_GSTRING_LEN] = { + [DPMAC_CNT_ING_ALL_FRAME] = "[mac] rx all frames", + [DPMAC_CNT_ING_GOOD_FRAME] = "[mac] rx frames ok", + [DPMAC_CNT_ING_ERR_FRAME] = "[mac] rx frame errors", + [DPMAC_CNT_ING_FRAME_DISCARD] = "[mac] rx frame discards", + [DPMAC_CNT_ING_UCAST_FRAME] = "[mac] rx u-cast", + [DPMAC_CNT_ING_BCAST_FRAME] = "[mac] rx b-cast", + [DPMAC_CNT_ING_MCAST_FRAME] = "[mac] rx m-cast", + [DPMAC_CNT_ING_FRAME_64] = "[mac] rx 64 bytes", + [DPMAC_CNT_ING_FRAME_127] = "[mac] rx 65-127 bytes", + [DPMAC_CNT_ING_FRAME_255] = "[mac] rx 128-255 bytes", + [DPMAC_CNT_ING_FRAME_511] = "[mac] rx 256-511 bytes", + [DPMAC_CNT_ING_FRAME_1023] = "[mac] rx 512-1023 bytes", + [DPMAC_CNT_ING_FRAME_1518] = "[mac] rx 1024-1518 bytes", + [DPMAC_CNT_ING_FRAME_1519_MAX] = "[mac] rx 1519-max bytes", + [DPMAC_CNT_ING_FRAG] = "[mac] rx frags", + [DPMAC_CNT_ING_JABBER] = "[mac] rx jabber", + [DPMAC_CNT_ING_ALIGN_ERR] = "[mac] rx align errors", + [DPMAC_CNT_ING_OVERSIZED] = "[mac] rx oversized", + [DPMAC_CNT_ING_VALID_PAUSE_FRAME] = "[mac] rx pause", + [DPMAC_CNT_ING_BYTE] = "[mac] rx bytes", + [DPMAC_CNT_EGR_GOOD_FRAME] = "[mac] tx frames ok", + [DPMAC_CNT_EGR_UCAST_FRAME] = "[mac] tx u-cast", + [DPMAC_CNT_EGR_MCAST_FRAME] = "[mac] tx m-cast", + [DPMAC_CNT_EGR_BCAST_FRAME] = "[mac] tx b-cast", + [DPMAC_CNT_EGR_ERR_FRAME] = "[mac] tx frame errors", + [DPMAC_CNT_EGR_UNDERSIZED] = "[mac] tx undersized", + [DPMAC_CNT_EGR_VALID_PAUSE_FRAME] = "[mac] tx b-pause", + [DPMAC_CNT_EGR_BYTE] = "[mac] tx bytes", +}; + +#define LDPAA_ETH_DPMAC_NUM_STATS ARRAY_SIZE(ldpaa_eth_dpmac_stat_strings) + struct ldpaa_eth_priv { struct phy_device *phy; int phy_mode; @@ -159,6 +192,7 @@ struct ldpaa_eth_priv { /* SW kept statistics */ u64 dpni_stats[LDPAA_ETH_DPNI_NUM_STATS]; + u64 dpmac_stats[LDPAA_ETH_DPMAC_NUM_STATS]; }; struct dprc_endpoint dpmac_endpoint; diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 8f5e17fe222..1fa26ef3805 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -412,6 +412,8 @@ int dpmac_set_link_state(struct fsl_mc_io *mc_io, * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including * pause frames. + * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including + * pause frames. */ enum dpmac_counter { DPMAC_CNT_ING_FRAME_64, @@ -440,7 +442,8 @@ enum dpmac_counter { DPMAC_CNT_EGR_BCAST_FRAME, DPMAC_CNT_EGR_UCAST_FRAME, DPMAC_CNT_EGR_ERR_FRAME, - DPMAC_CNT_ING_GOOD_FRAME + DPMAC_CNT_ING_GOOD_FRAME, + DPMAC_CNT_EGR_GOOD_FRAME, }; /** -- cgit v1.3.1 From c85e96d0d1e53196abc389f6b1bfabefb3336aea Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 23 May 2023 16:47:47 +0300 Subject: cmd: net: add a 'net stats' command to dump network statistics Add a new option to the 'net' command which can be used to dump network statistics. To do this, 3 new callbacks are added to the eth_ops structure: .get_sset_count(), .get_strings(), .get_stats(). These callbacks have the same functions as in Linux: to return the number of counters, the strings which describe those counters and the actual values. Signed-off-by: Ioana Ciornei Reviewed-by: Ramon Fried Signed-off-by: Peng Fan --- cmd/net.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++++- include/net.h | 6 ++++++ 2 files changed, 59 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/cmd/net.c b/cmd/net.c index 68d406291ef..dfe811f41ac 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -691,8 +692,58 @@ static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const ar return CMD_RET_SUCCESS; } +static int do_net_stats(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int nstats, err, i, off; + struct udevice *dev; + u64 *values; + u8 *strings; + + if (argc < 2) + return CMD_RET_USAGE; + + err = uclass_get_device_by_name(UCLASS_ETH, argv[1], &dev); + if (err) { + printf("Could not find device %s\n", argv[1]); + return CMD_RET_FAILURE; + } + + if (!eth_get_ops(dev)->get_sset_count || + !eth_get_ops(dev)->get_strings || + !eth_get_ops(dev)->get_stats) { + printf("Driver does not implement stats dump!\n"); + return CMD_RET_FAILURE; + } + + nstats = eth_get_ops(dev)->get_sset_count(dev); + strings = kcalloc(nstats, ETH_GSTRING_LEN, GFP_KERNEL); + if (!strings) + return CMD_RET_FAILURE; + + values = kcalloc(nstats, sizeof(u64), GFP_KERNEL); + if (!values) + goto err_free_strings; + + eth_get_ops(dev)->get_strings(dev, strings); + eth_get_ops(dev)->get_stats(dev, values); + + off = 0; + for (i = 0; i < nstats; i++) { + printf(" %s: %llu\n", &strings[off], values[i]); + off += ETH_GSTRING_LEN; + }; + + return CMD_RET_SUCCESS; + +err_free_strings: + kfree(strings); + + return CMD_RET_FAILURE; +} + static struct cmd_tbl cmd_net[] = { U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""), + U_BOOT_CMD_MKENT(stats, 2, 0, do_net_stats, "", ""), }; static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -714,9 +765,10 @@ static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } U_BOOT_CMD( - net, 2, 1, do_net, + net, 3, 1, do_net, "NET sub-system", "list - list available devices\n" + "stats - dump statistics for specified device\n" ); #if defined(CONFIG_CMD_NCSI) diff --git a/include/net.h b/include/net.h index 785cb1059ef..e254df7d7f4 100644 --- a/include/net.h +++ b/include/net.h @@ -167,6 +167,9 @@ enum eth_recv_flags { * to the network stack. This function should fill in the * eth_pdata::enetaddr field - optional * set_promisc: Enable or Disable promiscuous mode + * get_sset_count: Number of statistics counters + * get_string: Names of the statistic counters + * get_stats: The values of the statistic counters */ struct eth_ops { int (*start)(struct udevice *dev); @@ -178,6 +181,9 @@ struct eth_ops { int (*write_hwaddr)(struct udevice *dev); int (*read_rom_hwaddr)(struct udevice *dev); int (*set_promisc)(struct udevice *dev, bool enable); + int (*get_sset_count)(struct udevice *dev); + void (*get_strings)(struct udevice *dev, u8 *data); + void (*get_stats)(struct udevice *dev, u64 *data); }; #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops) -- cgit v1.3.1 From c761028e34fe18e0cd63fd80d1317cf17c8895bf Mon Sep 17 00:00:00 2001 From: Florin Chiculita Date: Wed, 31 May 2023 18:02:18 +0300 Subject: board: fsl: lx2160ardb: add dts fixup function for RevC and newer Since the new RevC LX2160A-RDB board has its 10G Aquantia PHYs at different MDIO bus addresses, we must update both the kernel DTS and u-boot's DTS (in case of DM_ETH) in case the board is indeed RevC or newer. Use the newly introduced get_board_rev() function to trigger a fixup of the kernel DTS to properly match the actual PHY addresses. All this is encapsulated in the fdt_fixup_board_phy_revc() function which will be used in the next patch. Use the newly fdt_fixup_board_phy_revc() function introduced to update both kernel's DTS and u-boot's DTS. Signed-off-by: Florin Chiculita Signed-off-by: Ioana Ciornei Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- board/freescale/lx2160a/eth_lx2160ardb.c | 107 +++++++++++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 7 ++ board/freescale/lx2160a/lx2160a.h | 6 ++ include/configs/lx2160ardb.h | 5 ++ 4 files changed, 125 insertions(+) (limited to 'include') diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index 533f606effa..c5dfefe1f34 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -8,6 +8,7 @@ #include #include #include +#include "lx2160a.h" DECLARE_GLOBAL_DATA_PTR; @@ -36,3 +37,109 @@ void reset_phy(void) #endif } #endif /* CONFIG_RESET_PHY_R */ + +static int fdt_get_dpmac_node(void *fdt, int dpmac_id) +{ + char dpmac_str[11] = "dpmacs@00"; + int offset, dpmacs_offset; + + /* get the dpmac offset */ + dpmacs_offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + if (dpmacs_offset < 0) + dpmacs_offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (dpmacs_offset < 0) { + printf("dpmacs node not found in device tree\n"); + return dpmacs_offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + sprintf(dpmac_str, "ethernet@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + printf("dpmac@%x/ethernet@%x node not found in device tree\n", + dpmac_id, dpmac_id); + return offset; + } + } + + return offset; +} + +static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr) +{ + char dpmac_str[] = "dpmacs@00"; + const u32 *phyhandle; + int offset; + int err; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* get dpmac phy-handle */ + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + offset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyhandle)); + if (offset < 0) { + printf("Could not get the ph node offset for dpmac %d\n", + dpmac_id); + return offset; + } + + phy_addr = cpu_to_fdt32(phy_addr); + err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr)); + if (err < 0) { + printf("Could not set phy node's reg for dpmac %d: %s.\n", + dpmac_id, fdt_strerror(err)); + return err; + } + + return 0; +} + +static int fdt_delete_phy_handle(void *fdt, int dpmac_id) +{ + const u32 *phyhandle; + int offset; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* verify if the node has a phy-handle */ + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) + return 0; + + return fdt_delprop(fdt, offset, "phy-handle"); +} + +int fdt_fixup_board_phy_revc(void *fdt) +{ + int ret; + + if (get_board_rev() < 'C') + return 0; + + /* DPMACs 3,4 have their Aquantia PHYs at new addresses */ + ret = fdt_update_phy_addr(fdt, 3, AQR113C_PHY_ADDR1); + if (ret) + return ret; + + ret = fdt_update_phy_addr(fdt, 4, AQR113C_PHY_ADDR2); + if (ret) + return ret; + + /* There is no PHY for the DPMAC2, so remove the phy-handle */ + return fdt_delete_phy_handle(fdt, 2); +} diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 4d406ac8f1c..d631a11ff66 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -133,6 +133,11 @@ int board_fix_fdt(void *fdt) fdt_setprop(fdt, off, "reg-names", reg_names, names_len); } + /* Fixup u-boot's DTS in case this is a revC board and + * we're using DM_ETH. + */ + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH)) + fdt_fixup_board_phy_revc(fdt); return 0; } #endif @@ -636,6 +641,8 @@ void fdt_fixup_board_enet(void *fdt) if (get_mc_boot_status() == 0 && (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) + fdt_fixup_board_phy_revc(fdt); } else { fdt_status_fail(fdt, offset); } diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h index 13673fca382..61a8bb95906 100644 --- a/board/freescale/lx2160a/lx2160a.h +++ b/board/freescale/lx2160a/lx2160a.h @@ -60,11 +60,17 @@ #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) u8 get_board_rev(void); +int fdt_fixup_board_phy_revc(void *fdt); #else static inline u8 get_board_rev(void) { return 0; } + +static inline int fdt_fixup_board_phy_revc(void *fdt) +{ + return 0; +} #endif #endif /* __LX2160_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 8cc4e0db03f..6404b359111 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -11,6 +11,11 @@ /* RTC */ #define CFG_SYS_RTC_BUS_NUM 4 +#if defined(CONFIG_FSL_MC_ENET) +#define AQR113C_PHY_ADDR1 0x0 +#define AQR113C_PHY_ADDR2 0x08 +#endif + /* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 #define I2C_EMC2305_ADDR 0x4D -- cgit v1.3.1 From f21d326be420e2710673974d85debd2c345cc0c7 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:29 +0300 Subject: net: fsl-mc: remove unused MC APIs There are multiple MC APIs which were added years ago but they are not used at all in the u-boot source code. Remove all these APIs. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpio/dpio.c | 15 -- drivers/net/fsl-mc/dpmac.c | 89 ------- drivers/net/fsl-mc/dpni.c | 100 -------- drivers/net/fsl-mc/dprc.c | 173 -------------- include/fsl-mc/fsl_dpbp.h | 14 -- include/fsl-mc/fsl_dpio.h | 13 -- include/fsl-mc/fsl_dpmac.h | 120 ---------- include/fsl-mc/fsl_dpni.h | 434 ---------------------------------- include/fsl-mc/fsl_dprc.h | 513 ----------------------------------------- 9 files changed, 1471 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c index 8884455963d..30ecc9124b2 100644 --- a/drivers/net/fsl-mc/dpio/dpio.c +++ b/drivers/net/fsl-mc/dpio/dpio.c @@ -123,21 +123,6 @@ int dpio_disable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET, - cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - int dpio_get_attributes(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c index 43a2ff43f88..f6def987c10 100644 --- a/drivers/net/fsl-mc/dpmac.c +++ b/drivers/net/fsl-mc/dpmac.c @@ -95,95 +95,6 @@ int dpmac_destroy(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpmac_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_attr *attr) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPMAC_RSP_GET_ATTRIBUTES(cmd, attr); - - return 0; -} - -int dpmac_mdio_read(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ, - cmd_flags, - token); - DPMAC_CMD_MDIO_READ(cmd, cfg); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPMAC_RSP_MDIO_READ(cmd, cfg->data); - - return 0; -} - -int dpmac_mdio_write(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE, - cmd_flags, - token); - DPMAC_CMD_MDIO_WRITE(cmd, cfg); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - int err = 0; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - DPMAC_RSP_GET_LINK_CFG(cmd, cfg); - - return 0; -} - int dpmac_set_link_state(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index a31abbff71b..d0596a8e38d 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -18,16 +18,6 @@ int dpni_prepare_cfg(const struct dpni_cfg *cfg, return 0; } -int dpni_extract_cfg(struct dpni_cfg *cfg, - const uint8_t *cfg_buf) -{ - uint64_t *params = (uint64_t *)cfg_buf; - - DPNI_EXT_CFG(params, cfg); - - return 0; -} - int dpni_open(struct fsl_mc_io *mc_io, uint32_t cmd_flags, int dpni_id, @@ -198,23 +188,6 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, return 0; } -int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_error_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR, - cmd_flags, - token); - DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, @@ -322,48 +295,6 @@ int dpni_get_link_state(struct fsl_mc_io *mc_io, return 0; } - -int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC, - cmd_flags, - token); - DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t mac_addr[6]) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr); - - return 0; -} - int dpni_add_mac_addr(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, @@ -381,23 +312,6 @@ int dpni_add_mac_addr(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR, - cmd_flags, - token); - DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *major_ver, @@ -511,17 +425,3 @@ int dpni_get_statistics(struct fsl_mc_io *mc_io, return 0; } - -int dpni_reset_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c index e0a2865ab8f..2be56e24a18 100644 --- a/drivers/net/fsl-mc/dprc.c +++ b/drivers/net/fsl-mc/dprc.c @@ -117,179 +117,6 @@ int dprc_destroy_container(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dprc_reset_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT, - cmd_flags, - token); - DPRC_CMD_RESET_CONTAINER(cmd, child_container_id); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dprc_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_attributes *attr) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_ATTRIBUTES(cmd, attr); - - return 0; -} - -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *obj_count) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_OBJ_COUNT(cmd, *obj_count); - - return 0; -} - -int dprc_get_obj(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int obj_index, - struct dprc_obj_desc *obj_desc) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ, - cmd_flags, - token); - DPRC_CMD_GET_OBJ(cmd, obj_index); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_OBJ(cmd, obj_desc); - - return 0; -} - -int dprc_get_res_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - int *res_count) -{ - struct mc_command cmd = { 0 }; - int err; - - *res_count = 0; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT, - cmd_flags, - token); - DPRC_CMD_GET_RES_COUNT(cmd, type); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_RES_COUNT(cmd, *res_count); - - return 0; -} - -int dprc_get_res_ids(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - struct dprc_res_ids_range_desc *range_desc) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS, - cmd_flags, - token); - DPRC_CMD_GET_RES_IDS(cmd, range_desc, type); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_RES_IDS(cmd, range_desc); - - return 0; -} - -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *obj_type, - int obj_id, - uint8_t region_index, - struct dprc_region_desc *region_desc) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG, - cmd_flags, - token); - DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_OBJ_REGION(cmd, region_desc); - - return 0; -} - int dprc_connect(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 2278ac952ea..477a08ef268 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -155,20 +155,6 @@ int dpbp_disable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token); -/** - * dpbp_is_enabled() - Check if the DPBP is enabled. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @en: Returns '1' if object is enabled; '0' otherwise - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_is_enabled(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *en); - /** * dpbp_reset() - Reset the DPBP, returns the object to initial state. * @mc_io: Pointer to MC portal's I/O object diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 7788e1962e6..9d52a8e42f8 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -21,7 +21,6 @@ #define DPIO_CMDID_ENABLE 0x0021 #define DPIO_CMDID_DISABLE 0x0031 #define DPIO_CMDID_GET_ATTR 0x0041 -#define DPIO_CMDID_RESET 0x0051 /* cmd, param, offset, width, type, arg_name */ #define DPIO_CMD_OPEN(cmd, dpio_id) \ @@ -177,18 +176,6 @@ int dpio_disable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token); -/** - * dpio_reset() - Reset the DPIO, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); - /** * struct dpio_attr - Structure representing DPIO attributes * @id: DPIO object ID diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 1fa26ef3805..eebfe548cc6 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -21,12 +21,8 @@ #define DPMAC_CMDID_DESTROY 0x98c1 #define DPMAC_CMDID_GET_API_VERSION 0xa0c1 -#define DPMAC_CMDID_GET_ATTR 0x0041 #define DPMAC_CMDID_RESET 0x0051 -#define DPMAC_CMDID_MDIO_READ 0x0c01 -#define DPMAC_CMDID_MDIO_WRITE 0x0c11 -#define DPMAC_CMDID_GET_LINK_CFG 0x0c21 #define DPMAC_CMDID_SET_LINK_STATE 0x0c31 #define DPMAC_CMDID_GET_COUNTER 0x0c41 @@ -38,42 +34,6 @@ #define DPMAC_CMD_OPEN(cmd, dpmac_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ - MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ - MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ - MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_MDIO_READ(cmd, data) \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ - MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ -} while (0) - /* cmd, param, offset, width, type, arg_name */ #define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ do { \ @@ -251,62 +211,6 @@ struct dpmac_attr { uint32_t max_rate; }; -/** - * dpmac_get_attributes - Retrieve DPMAC attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_attr *attr); - -/** - * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters - * @phy_addr: MDIO device address - * @reg: Address of the register within the Clause 45 PHY device from which data - * is to be read - * @data: Data read/write from/to MDIO - */ -struct dpmac_mdio_cfg { - uint8_t phy_addr; - uint8_t reg; - uint16_t data; -}; - -/** - * dpmac_mdio_read() - Perform MDIO read transaction - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Structure with MDIO transaction parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_mdio_read(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg); - -/** - * dpmac_mdio_write() - Perform MDIO write transaction - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Structure with MDIO transaction parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_mdio_write(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg); - /* DPMAC link configuration/state options */ /* Enable auto-negotiation */ @@ -318,30 +222,6 @@ int dpmac_mdio_write(struct fsl_mc_io *mc_io, /* Enable a-symmetric pause frames */ #define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL -/** - * struct dpmac_link_cfg - Structure representing DPMAC link configuration - * @rate: Link's rate - in Mbps - * @options: Enable/Disable DPMAC link cfg features (bitmap) - */ -struct dpmac_link_cfg { - uint32_t rate; - uint64_t options; -}; - -/** - * dpmac_get_link_cfg() - Get Ethernet link configuration - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Returned structure with the link configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_cfg *cfg); - /** * struct dpmac_link_state - DPMAC link configuration request * @rate: Rate in Mbps diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index fc57c375ac1..fa15a141f1f 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -24,21 +24,15 @@ #define DPNI_CMDID_SET_POOLS 0x2002 #define DPNI_CMDID_SET_BUFFER_LAYOUT 0x2651 -#define DPNI_CMDID_GET_BUFFER_LAYOUT 0x2641 -#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B1 #define DPNI_CMDID_GET_QDID 0x2101 #define DPNI_CMDID_GET_TX_DATA_OFFSET 0x2121 #define DPNI_CMDID_GET_LINK_STATE 0x2151 #define DPNI_CMDID_SET_LINK_CFG 0x21A1 -#define DPNI_CMDID_SET_PRIM_MAC 0x2241 -#define DPNI_CMDID_GET_PRIM_MAC 0x2251 #define DPNI_CMDID_ADD_MAC_ADDR 0x2261 -#define DPNI_CMDID_REMOVE_MAC_ADDR 0x2271 #define DPNI_CMDID_GET_STATISTICS 0x25D1 -#define DPNI_CMDID_RESET_STATISTICS 0x25E1 #define DPNI_CMDID_GET_QUEUE 0x25F1 #define DPNI_CMDID_SET_QUEUE 0x2601 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661 @@ -59,18 +53,6 @@ do { \ MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_EXT_CFG(param, cfg) \ -do { \ - MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ - MC_EXT_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ - MC_EXT_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ - MC_EXT_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ - MC_EXT_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ - MC_EXT_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ - MC_EXT_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ -} while (0) - /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_CREATE(cmd, cfg) \ do { \ @@ -128,14 +110,6 @@ do { \ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ - MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ - MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ -} while (0) - /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ do { \ @@ -173,28 +147,6 @@ do { \ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ do { \ @@ -206,17 +158,6 @@ do { \ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - #define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \ do { \ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ @@ -267,60 +208,6 @@ do { \ MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->raw.counter[6]); \ } while (0) -enum net_prot { - NET_PROT_NONE = 0, - NET_PROT_PAYLOAD, - NET_PROT_ETH, - NET_PROT_VLAN, - NET_PROT_IPV4, - NET_PROT_IPV6, - NET_PROT_IP, - NET_PROT_TCP, - NET_PROT_UDP, - NET_PROT_UDP_LITE, - NET_PROT_IPHC, - NET_PROT_SCTP, - NET_PROT_SCTP_CHUNK_DATA, - NET_PROT_PPPOE, - NET_PROT_PPP, - NET_PROT_PPPMUX, - NET_PROT_PPPMUX_SUBFRM, - NET_PROT_L2TPV2, - NET_PROT_L2TPV3_CTRL, - NET_PROT_L2TPV3_SESS, - NET_PROT_LLC, - NET_PROT_LLC_SNAP, - NET_PROT_NLPID, - NET_PROT_SNAP, - NET_PROT_MPLS, - NET_PROT_IPSEC_AH, - NET_PROT_IPSEC_ESP, - NET_PROT_UDP_ENC_ESP, /* RFC 3948 */ - NET_PROT_MACSEC, - NET_PROT_GRE, - NET_PROT_MINENCAP, - NET_PROT_DCCP, - NET_PROT_ICMP, - NET_PROT_IGMP, - NET_PROT_ARP, - NET_PROT_CAPWAP_DATA, - NET_PROT_CAPWAP_CTRL, - NET_PROT_RFC2684, - NET_PROT_ICMPV6, - NET_PROT_FCOE, - NET_PROT_FIP, - NET_PROT_ISCSI, - NET_PROT_GTP, - NET_PROT_USER_DEFINED_L2, - NET_PROT_USER_DEFINED_L3, - NET_PROT_USER_DEFINED_L4, - NET_PROT_USER_DEFINED_L5, - NET_PROT_USER_DEFINED_SHIM1, - NET_PROT_USER_DEFINED_SHIM2, - - NET_PROT_DUMMY_LAST -}; - /** * Data Path Network Interface API * Contains initialization APIs and runtime control APIs for DPNI @@ -455,46 +342,6 @@ struct dpni_cfg { } adv; }; -/** - * struct dpni_extended_cfg - Structure representing extended DPNI configuration - * @tc_cfg: TCs configuration - * @ipr_cfg: IP reassembly configuration - */ -struct dpni_extended_cfg { - /** - * struct tc_cfg - TC configuration - * @max_dist: Maximum distribution size for Rx traffic class; - * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, - * 112,128,192,224,256,384,448,512,768,896,1024; - * value '0' will be treated as '1'. - * other unsupported values will be round down to the nearest - * supported value. - * @max_fs_entries: Maximum FS entries for Rx traffic class; - * '0' means no support for this TC; - */ - struct { - uint16_t max_dist; - uint16_t max_fs_entries; - } tc_cfg[DPNI_MAX_TC]; - /** - * struct ipr_cfg - Structure representing IP reassembly configuration - * @max_reass_frm_size: Maximum size of the reassembled frame - * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments - * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments - * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly - * process - * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly - * process - */ - struct { - uint16_t max_reass_frm_size; - uint16_t min_frag_size_ipv4; - uint16_t min_frag_size_ipv6; - uint16_t max_open_frames_ipv4; - uint16_t max_open_frames_ipv6; - } ipr_cfg; -}; - /** * dpni_prepare_cfg() - function prepare parameters * @cfg: cfg structure @@ -666,87 +513,6 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, uint16_t token, struct dpni_attr *attr); -/** - * dpni_extract_cfg() - extract the parameters - * @cfg: cfg structure - * @cfg_buf: 256 bytes of DMA-able memory - * - * This function has to be called after dpni_get_attributes() - */ -int dpni_extract_cfg(struct dpni_cfg *cfg, - const uint8_t *cfg_buf); - -/** - * DPNI errors - */ - -/** - * Extract out of frame header error - */ -#define DPNI_ERROR_EOFHE 0x00020000 -/** - * Frame length error - */ -#define DPNI_ERROR_FLE 0x00002000 -/** - * Frame physical error - */ -#define DPNI_ERROR_FPE 0x00001000 -/** - * Parsing header error - */ -#define DPNI_ERROR_PHE 0x00000020 -/** - * Parser L3 checksum error - */ -#define DPNI_ERROR_L3CE 0x00000004 -/** - * Parser L3 checksum error - */ -#define DPNI_ERROR_L4CE 0x00000001 - -/** - * enum dpni_error_action - Defines DPNI behavior for errors - * @DPNI_ERROR_ACTION_DISCARD: Discard the frame - * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow - * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue - */ -enum dpni_error_action { - DPNI_ERROR_ACTION_DISCARD = 0, - DPNI_ERROR_ACTION_CONTINUE = 1, - DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 -}; - -/** - * struct dpni_error_cfg - Structure representing DPNI errors treatment - * @errors: Errors mask; use 'DPNI_ERROR__ - * @error_action: The desired action for the errors mask - * @set_frame_annotation: Set to '1' to mark the errors in frame annotation - * status (FAS); relevant only for the non-discard action - */ -struct dpni_error_cfg { - uint32_t errors; - enum dpni_error_action error_action; - int set_frame_annotation; -}; - -/** - * dpni_set_errors_behavior() - Set errors behavior - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Errors configuration - * - * this function may be called numerous times with different - * error masks - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_error_cfg *cfg); - /* DPNI buffer layout modification options */ /* Select to modify the time-stamp setting */ @@ -787,22 +553,6 @@ struct dpni_buffer_layout { uint16_t data_tail_room; }; -/** - * dpni_get_buffer_layout() - Retrieve buffer layout attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Returns buffer layout attributes - * @type: DPNI queue type - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type); - /** * dpni_set_buffer_layout() - Set buffer layout configuration. * @mc_io: Pointer to MC portal's I/O object @@ -910,34 +660,6 @@ int dpni_get_link_state(struct fsl_mc_io *mc_io, uint16_t token, struct dpni_link_state *state); -/** - * dpni_set_primary_mac_addr() - Set the primary MAC address - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to set as primary address - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); - -/** - * dpni_get_primary_mac_addr() - Get the primary MAC address - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: Returned MAC address - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t mac_addr[6]); - /** * dpni_add_mac_addr() - Add MAC address filter * @mc_io: Pointer to MC portal's I/O object @@ -952,20 +674,6 @@ int dpni_add_mac_addr(struct fsl_mc_io *mc_io, uint16_t token, const uint8_t mac_addr[6]); -/** - * dpni_remove_mac_addr() - Remove MAC address filter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to remove - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); - /** * enum dpni_dest - DPNI destination types * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and @@ -985,137 +693,6 @@ enum dpni_dest { DPNI_DEST_DPCON = 2 }; -/** - * struct dpni_dest_cfg - Structure representing DPNI destination parameters - * @dest_type: Destination type - * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type - * @priority: Priority selection within the DPIO or DPCON channel; valid values - * are 0-1 or 0-7, depending on the number of priorities in that - * channel; not relevant for 'DPNI_DEST_NONE' option - */ -struct dpni_dest_cfg { - enum dpni_dest dest_type; - int dest_id; - uint8_t priority; -}; - -/** - * enum dpni_flc_type - DPNI FLC types - * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value - * @DPNI_FLC_STASH: select the FLC to be used for stash control - */ -enum dpni_flc_type { - DPNI_FLC_USER_DEFINED = 0, - DPNI_FLC_STASH = 1, -}; - -/** - * enum dpni_stash_size - DPNI FLC stashing size - * @DPNI_STASH_SIZE_0B: no stash - * @DPNI_STASH_SIZE_64B: stashes 64 bytes - * @DPNI_STASH_SIZE_128B: stashes 128 bytes - * @DPNI_STASH_SIZE_192B: stashes 192 bytes - */ -enum dpni_stash_size { - DPNI_STASH_SIZE_0B = 0, - DPNI_STASH_SIZE_64B = 1, - DPNI_STASH_SIZE_128B = 2, - DPNI_STASH_SIZE_192B = 3, -}; - -/* DPNI FLC stash options */ - -/* stashes the whole annotation area (up to 192 bytes) */ -#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 - -/** - * struct dpni_flc_cfg - Structure representing DPNI FLC configuration - * @flc_type: FLC type - * @options: Mask of available options; - * use 'DPNI_FLC_STASH_' values - * @frame_data_size: Size of frame data to be stashed - * @flow_context_size: Size of flow context to be stashed - * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED': - * this value will be provided in the frame descriptor - * (FD[FLC]) - * 2. In case flc_type is 'DPNI_FLC_STASH': - * this value will be I/O virtual address of the - * flow-context; - * Must be cacheline-aligned and DMA-able memory - */ -struct dpni_flc_cfg { - enum dpni_flc_type flc_type; - uint32_t options; - enum dpni_stash_size frame_data_size; - enum dpni_stash_size flow_context_size; - uint64_t flow_context; -}; - -/* DPNI queue modification options */ - -/* Select to modify the user's context associated with the queue */ -#define DPNI_QUEUE_OPT_USER_CTX 0x00000001 -/* Select to modify the queue's destination */ -#define DPNI_QUEUE_OPT_DEST 0x00000002 -/** Select to modify the flow-context parameters; - * not applicable for Tx-conf/Err queues as the FD comes from the user - */ -#define DPNI_QUEUE_OPT_FLC 0x00000004 -/* Select to modify the queue's order preservation */ -#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 -/* Select to modify the queue's tail-drop threshold */ -#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 - -/** - * struct dpni_queue_cfg - Structure representing queue configuration - * @options: Flags representing the suggested modifications to the queue; - * Use any combination of 'DPNI_QUEUE_OPT_' flags - * @user_ctx: User context value provided in the frame descriptor of each - * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' - * is contained in 'options' - * @dest_cfg: Queue destination parameters; - * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options' - * @flc_cfg: Flow context configuration; in case the TC's distribution - * is either NONE or HASH the FLC's settings of flow#0 are used. - * in the case of FS (flow-steering) the flow's FLC settings - * are used. - * valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options' - * @order_preservation_en: enable/disable order preservation; - * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained - * in 'options' - * @tail_drop_threshold: set the queue's tail drop threshold in bytes; - * '0' value disable the threshold; maximum value is 0xE000000; - * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained - * in 'options' - */ -struct dpni_queue_cfg { - uint32_t options; - uint64_t user_ctx; - struct dpni_dest_cfg dest_cfg; - struct dpni_flc_cfg flc_cfg; - int order_preservation_en; - uint32_t tail_drop_threshold; -}; - -/** - * struct dpni_queue_attr - Structure representing queue attributes - * @user_ctx: User context value provided in the frame descriptor of each - * dequeued frame - * @dest_cfg: Queue destination configuration - * @flc_cfg: Flow context configuration - * @order_preservation_en: enable/disable order preservation - * @tail_drop_threshold: queue's tail drop threshold in bytes; - * @fqid: Virtual fqid value to be used for dequeue operations - */ -struct dpni_queue_attr { - uint64_t user_ctx; - struct dpni_dest_cfg dest_cfg; - struct dpni_flc_cfg flc_cfg; - int order_preservation_en; - uint32_t tail_drop_threshold; - uint32_t fqid; -}; - /* DPNI Tx flow modification options */ /* Select to modify the settings for dedicate Tx confirmation/error */ @@ -1371,15 +948,4 @@ int dpni_get_statistics(struct fsl_mc_io *mc_io, uint8_t page, union dpni_statistics *stat); -/** - * dpni_reset_statistics() - Clears DPNI statistics - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_reset_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); #endif /* _FSL_DPNI_H */ diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 950ecb07569..0b95a06a911 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -15,20 +15,12 @@ /* Command IDs */ #define DPRC_CMDID_CLOSE 0x8001 #define DPRC_CMDID_OPEN 0x8051 -#define DPRC_CMDID_CREATE 0x9051 -#define DPRC_CMDID_GET_ATTR 0x0041 -#define DPRC_CMDID_RESET_CONT 0x0051 #define DPRC_CMDID_GET_API_VERSION 0xa051 #define DPRC_CMDID_CREATE_CONT 0x1511 #define DPRC_CMDID_DESTROY_CONT 0x1521 #define DPRC_CMDID_GET_CONT_ID 0x8301 -#define DPRC_CMDID_GET_OBJ_COUNT 0x1591 -#define DPRC_CMDID_GET_OBJ 0x15A1 -#define DPRC_CMDID_GET_RES_COUNT 0x15B1 -#define DPRC_CMDID_GET_RES_IDS 0x15C1 -#define DPRC_CMDID_GET_OBJ_REG 0x15E1 #define DPRC_CMDID_CONNECT 0x1671 #define DPRC_CMDID_DISCONNECT 0x1681 @@ -77,268 +69,6 @@ do { \ #define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->container_id); \ - MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ - MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_count) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ(cmd, obj_index) \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_index) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ - MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ - MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ - MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ - MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ - MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ - MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ - MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ - MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ - MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ - MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ - MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ - MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ - MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ - MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ - MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ - MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ - MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ - MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ - MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ - MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ - MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ - MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ - MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ - MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ - MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ - MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ - MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ - MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ - MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ - MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ - MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ - MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ - MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ - MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ - MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ - MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ - MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ - MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ - MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ - MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ - MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ - MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ - MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ - MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ - MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ - MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ - MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ - MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ - MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ - MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ - MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ - MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ - MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ - MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ - MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ - MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ - MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ - MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ - MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ - MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ - MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ - MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ - MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ - MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ - MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ - MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ - MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ - MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ - MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ - MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ - MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_RES_COUNT(cmd, type) \ -do { \ - MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \ - MC_RSP_OP(cmd, 0, 0, 32, int, res_count) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \ -do { \ - MC_CMD_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ - range_desc->iter_status); \ - MC_CMD_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ - MC_CMD_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ - MC_CMD_OP(cmd, 2, 0, 8, char, type[0]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, type[1]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, type[2]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, type[3]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, type[4]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, type[5]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, type[6]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, type[7]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, type[8]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, type[9]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, type[10]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, type[11]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, type[12]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, type[13]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, type[14]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ - range_desc->iter_status);\ - MC_RSP_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ - MC_RSP_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, region_index);\ - MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ -} while (0) - -/* param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, region_desc->base_offset);\ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, region_desc->size); \ - MC_RSP_OP(cmd, 2, 32, 4, enum dprc_region_type, region_desc->type);\ - MC_RSP_OP(cmd, 3, 0, 32, uint32_t, region_desc->flags);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, label[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, label[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, label[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, label[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, label[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, label[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, label[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, label[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, label[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, label[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, label[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, label[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, label[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, label[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, label[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, label[15]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ -} while (0) - /* cmd, param, offset, width, type, arg_name */ #define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \ do { \ @@ -615,249 +345,6 @@ int dprc_destroy_container(struct fsl_mc_io *mc_io, uint16_t token, int child_container_id); -/** - * dprc_reset_container - Reset child container. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @child_container_id: ID of the container to reset - * - * In case a software context crashes or becomes non-responsive, the parent - * may wish to reset its resources container before the software context is - * restarted. - * - * This routine informs all objects assigned to the child container that the - * container is being reset, so they may perform any cleanup operations that are - * needed. All objects handles that were owned by the child container shall be - * closed. - * - * Note that such request may be submitted even if the child software context - * has not crashed, but the resulting object cleanup operations will not be - * aware of that. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_reset_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id); - -/** - * struct dprc_attributes - Container attributes - * @container_id: Container's ID - * @icid: Container's ICID - * @portal_id: Container's portal ID - * @options: Container's options as set at container's creation - * @version: DPRC version - */ -struct dprc_attributes { - int container_id; - uint16_t icid; - int portal_id; - uint64_t options; -}; - -/** - * dprc_get_attributes() - Obtains container attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @attributes: Returned container attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_attributes *attributes); - -/** - * dprc_get_obj_count() - Obtains the number of objects in the DPRC - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_count: Number of objects assigned to the DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *obj_count); - -/* Objects Attributes Flags */ - -/* Opened state - Indicates that an object is open by at least one owner */ -#define DPRC_OBJ_STATE_OPEN 0x00000001 -/* Plugged state - Indicates that the object is plugged */ -#define DPRC_OBJ_STATE_PLUGGED 0x00000002 - -/** - * Shareability flag - Object flag indicating no memory shareability. - * the object generates memory accesses that are non coherent with other - * masters; - * user is responsible for proper memory handling through IOMMU configuration. - */ -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 - -/** - * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() - * @type: Type of object: NULL terminated string - * @id: ID of logical object resource - * @vendor: Object vendor identifier - * @ver_major: Major version number - * @ver_minor: Minor version number - * @irq_count: Number of interrupts supported by the object - * @region_count: Number of mappable regions supported by the object - * @state: Object state: combination of DPRC_OBJ_STATE_ states - * @label: Object label - * @flags: Object's flags - */ -struct dprc_obj_desc { - char type[16]; - int id; - uint16_t vendor; - uint16_t ver_major; - uint16_t ver_minor; - uint8_t irq_count; - uint8_t region_count; - uint32_t state; - char label[16]; - uint16_t flags; -}; - -/** - * dprc_get_obj() - Get general information on an object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_index: Index of the object to be queried (< obj_count) - * @obj_desc: Returns the requested object descriptor - * - * The object descriptors are retrieved one by one by incrementing - * obj_index up to (not including) the value of obj_count returned - * from dprc_get_obj_count(). dprc_get_obj_count() must - * be called prior to dprc_get_obj(). - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int obj_index, - struct dprc_obj_desc *obj_desc); - -/** - * dprc_get_res_count() - Obtains the number of free resources that are - * assigned to this container, by pool type - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @type: pool type - * @res_count: Returned number of free resources of the given - * resource type that are assigned to this DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_res_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - int *res_count); - -/** - * enum dprc_iter_status - Iteration status - * @DPRC_ITER_STATUS_FIRST: Perform first iteration - * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed - * @DPRC_ITER_STATUS_LAST: Indicates last iteration - */ -enum dprc_iter_status { - DPRC_ITER_STATUS_FIRST = 0, - DPRC_ITER_STATUS_MORE = 1, - DPRC_ITER_STATUS_LAST = 2 -}; - -/** - * struct dprc_res_ids_range_desc - Resource ID range descriptor - * @base_id: Base resource ID of this range - * @last_id: Last resource ID of this range - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE, - * additional iterations are needed, until the returned marker is - * DPRC_ITER_STATUS_LAST - */ -struct dprc_res_ids_range_desc { - int base_id; - int last_id; - enum dprc_iter_status iter_status; -}; - -/** - * dprc_get_res_ids() - Obtains IDs of free resources in the container - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @type: pool type - * @range_desc: range descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_res_ids(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - struct dprc_res_ids_range_desc *range_desc); - -/* Region flags */ -/* Cacheable - Indicates that region should be mapped as cacheable */ -#define DPRC_REGION_CACHEABLE 0x00000001 - -/** - * enum dprc_region_type - Region type - * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region - * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region - */ -enum dprc_region_type { - DPRC_REGION_TYPE_MC_PORTAL, - DPRC_REGION_TYPE_QBMAN_PORTAL -}; - -/** - * struct dprc_region_desc - Mappable region descriptor - * @base_offset: Region offset from region's base address. - * For DPMCP and DPRC objects, region base is offset from SoC MC portals - * base address; For DPIO, region base is offset from SoC QMan portals - * base address - * @size: Region size (in bytes) - * @flags: Region attributes - * @type: Portal region type - */ -struct dprc_region_desc { - uint32_t base_offset; - uint32_t size; - uint32_t flags; - enum dprc_region_type type; -}; - -/** - * dprc_get_obj_region() - Get region information for a specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_type: Object type as returned in dprc_get_obj() - * @obj_id: Unique object instance as returned in dprc_get_obj() - * @region_index: The specific region to query - * @region_desc: Returns the requested region descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *obj_type, - int obj_id, - uint8_t region_index, - struct dprc_region_desc *region_desc); /** * struct dprc_endpoint - Endpoint description for link connect/disconnect * operations -- cgit v1.3.1 From 694dc0dd7904f6680f0523f993433e40c4dc1fd9 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:30 +0300 Subject: net: fsl-mc: sync DPBP MC APIs Sync the Data Path Buffer Pool APIs to their latest form, this means the layout of each command is created based on structures which clearly describe the endianness of each field rather than some macros. The command version is kept in place, meaning that the minimum MC version accepted is not changed in any way. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpbp.c | 180 +++++++++++++++++++++++++++++------------ include/fsl-mc/fsl_dpbp.h | 193 ++++++++------------------------------------ include/fsl-mc/fsl_mc_cmd.h | 24 ++++++ 3 files changed, 188 insertions(+), 209 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpbp.c b/drivers/net/fsl-mc/dpbp.c index c609efb9abc..5e17ccf73d3 100644 --- a/drivers/net/fsl-mc/dpbp.c +++ b/drivers/net/fsl-mc/dpbp.c @@ -3,25 +3,40 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2023 NXP */ #include #include #include -int dpbp_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpbp_id, - uint16_t *token) +/** + * dpbp_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpbp_id: DPBP unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpbp_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token) { + struct dpbp_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN, - cmd_flags, - 0); - DPBP_CMD_OPEN(cmd, dpbp_id); + cmd_flags, 0); + cmd_params = (struct dpbp_cmd_open *)cmd.params; + cmd_params->dpbp_id = cpu_to_le32(dpbp_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -29,14 +44,23 @@ int dpbp_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return err; } -int dpbp_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -48,11 +72,26 @@ int dpbp_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpbp_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpbp_cfg *cfg, - uint32_t *obj_id) +/** + * dpbp_create() - Create the DPBP object. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id; use in subsequent API calls + * + * Create the DPBP object, allocate required resources and + * perform required initialization. + * + * This function accepts an authentication token of a parent + * container that this object should be assigned to and returns + * an object id. This object_id will be used in all subsequent calls to + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpbp_cfg *cfg, u32 *obj_id) { struct mc_command cmd = { 0 }; int err; @@ -61,8 +100,7 @@ int dpbp_create(struct fsl_mc_io *mc_io, /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE, - cmd_flags, - dprc_token); + cmd_flags, dprc_token); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -70,33 +108,46 @@ int dpbp_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpbp_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpbp_destroy() - Destroy the DPBP object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @obj_id: ID of DPBP object + * + * Return: '0' on Success; error code otherwise. + */ +int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 obj_id) { + struct dpbp_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY, - cmd_flags, - dprc_token); + cmd_flags, dprc_token); - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpbp_cmd_destroy *)cmd.params; + cmd_params->object_id = cpu_to_le32(obj_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpbp_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_enable() - Enable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -108,48 +159,66 @@ int dpbp_enable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpbp_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_disable() - Disable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE, - cmd_flags, - token); + cmd_flags, token); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpbp_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_reset() - Reset the DPBP, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET, - cmd_flags, - token); + cmd_flags, token); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpbp_get_attributes - Retrieve DPBP attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpbp_attr *attr) { + struct dpbp_rsp_get_attributes *rsp_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR, - cmd_flags, - token); + cmd_flags, token); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -157,15 +226,24 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPBP_RSP_GET_ATTRIBUTES(cmd, attr); + rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params; + attr->bpid = le16_to_cpu(rsp_params->bpid); + attr->id = le32_to_cpu(rsp_params->id); return 0; } -int dpbp_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpbp_get_api_version - Get Data Path Buffer Pool API version + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of Buffer Pool API + * @minor_ver: Minor version of Buffer Pool API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 477a08ef268..3f3e6c40707 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Freescale Layerscape MC I/O wrapper + * Data Path Buffer Pool API + * Contains initialization APIs and runtime control APIs for DPBP * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ -/*! - * @file fsl_dpbp.h - * @brief Data Path Buffer Pool API + * Copyright 2017-2023 NXP */ + #ifndef __FSL_DPBP_H #define __FSL_DPBP_H @@ -27,146 +26,50 @@ #define DPBP_CMDID_DISABLE 0x0031 #define DPBP_CMDID_GET_ATTR 0x0041 #define DPBP_CMDID_RESET 0x0051 -#define DPBP_CMDID_IS_ENABLED 0x0061 -/* cmd, param, offset, width, type, arg_name */ -#define DPBP_CMD_OPEN(cmd, dpbp_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id) +#pragma pack(push, 1) -/* cmd, param, offset, width, type, arg_name */ -#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \ - MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ -} while (0) +struct dpbp_cmd_open { + __le32 dpbp_id; +}; -/* Data Path Buffer Pool API - * Contains initialization APIs and runtime control APIs for DPBP - */ +struct dpbp_cmd_destroy { + __le32 object_id; +}; + +struct dpbp_rsp_get_attributes { + __le16 pad; + __le16 bpid; + __le32 id; +}; + +#pragma pack(pop) struct fsl_mc_io; -/** - * dpbp_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpbp_id: DPBP unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpbp_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpbp_id, - uint16_t *token); +int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token); -/** - * dpbp_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpbp_cfg - Structure representing DPBP configuration * @options: place holder */ struct dpbp_cfg { - uint32_t options; + u32 options; }; -/** - * dpbp_create() - Create the DPBP object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @token: Returned token; use in subsequent API calls - * - * Create the DPBP object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpbp_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpbp_cfg *cfg, - uint32_t *obj_id); +int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpbp_cfg *cfg, u32 *obj_id); -/** - * dpbp_destroy() - Destroy the DPBP object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; error code otherwise. - */ -int dpbp_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 obj_id); -/** - * dpbp_enable() - Enable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpbp_disable() - Disable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); - -/** - * dpbp_reset() - Reset the DPBP, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpbp_attr - Structure representing DPBP attributes @@ -176,40 +79,14 @@ int dpbp_reset(struct fsl_mc_io *mc_io, * acquire/release operations on buffers */ struct dpbp_attr { - uint32_t id; - uint16_t bpid; + u32 id; + u16 bpid; }; -/** - * dpbp_get_attributes - Retrieve DPBP attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpbp_attr *attr); - -/** - * dpbp_get_api_version - Retrieve DPBP Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPBP major version - * @minor_ver: DPBP minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpbp_attr *attr); -/** @} */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* __FSL_DPBP_H */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 591cda96851..6fe5fa4edda 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -19,6 +19,15 @@ static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width) return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); } +struct mc_cmd_header { + u8 src_id; + u8 flags_hw; + u8 status; + u8 flags_sw; + __le16 token; + __le16 cmd_id; +}; + struct mc_command { uint64_t header; uint64_t params[MC_CMD_NUM_OF_PARAMS]; @@ -179,4 +188,19 @@ static inline void mc_cmd_read_api_version(struct mc_command *cmd, *minor_ver = le16_to_cpu(rsp_params->minor_ver); } +static inline uint16_t mc_cmd_hdr_read_token(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 token = le16_to_cpu(hdr->token); + + return token; +} + +static inline uint32_t mc_cmd_read_object_id(struct mc_command *cmd) +{ + struct mc_rsp_create *rsp_params; + + rsp_params = (struct mc_rsp_create *)cmd->params; + return le32_to_cpu(rsp_params->object_id); +} #endif /* __FSL_MC_CMD_H */ -- cgit v1.3.1 From 018bc358d3cceba71f003bdc96a1b58ed1ffb32e Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:31 +0300 Subject: net: fsl-mc: sync DPMAC MC APIs Sync the Data Path MAC APIs to their latest form, this means the layout of each command is created based on structures which clearly describe the endianness of each field rather than some macros. The command version is kept in place, meaning that the minimum MC version accepted is not changed in any way. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpmac.c | 185 ++++++++++++++++++++++++---------- include/fsl-mc/fsl_dpmac.h | 240 ++++++++++++++++----------------------------- 2 files changed, 215 insertions(+), 210 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c index f6def987c10..5d4f6c67fd0 100644 --- a/drivers/net/fsl-mc/dpmac.c +++ b/drivers/net/fsl-mc/dpmac.c @@ -11,19 +11,33 @@ #include #include -int dpmac_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpmac_id, - uint16_t *token) +/** + * dpmac_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpmac_id: DPMAC unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpmac_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token) { + struct dpmac_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, - cmd_flags, - 0); - DPMAC_CMD_OPEN(cmd, dpmac_id); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, cmd_flags, 0); + cmd_params = (struct dpmac_cmd_open *)cmd.params; + cmd_params->dpmac_id = cpu_to_le32(dpmac_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -31,39 +45,63 @@ int dpmac_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return err; } -int dpmac_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpmac_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, - token); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, token); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpmac_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpmac_cfg *cfg, - uint32_t *obj_id) +/** + * dpmac_create() - Create the DPMAC object. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id + * + * Create the DPMAC object, allocate required resources and + * perform required initialization. + * + * The function accepts an authentication token of a parent + * container that this object should be assigned to. The token + * can be '0' so the object will be assigned to the default container. + * The newly created object can be opened with the returned + * object id and using the container's associated tokens and MC portals. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpmac_cfg *cfg, u32 *obj_id) { + struct dpmac_cmd_create *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, - cmd_flags, - dprc_token); - DPMAC_CMD_CREATE(cmd, cfg); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, cmd_flags, dprc_token); + cmd_params = (struct dpmac_cmd_create *)cmd.params; + cmd_params->mac_id = cpu_to_le32(cfg->mac_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -71,53 +109,87 @@ int dpmac_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpmac_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpmac_destroy() - Destroy the DPMAC object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; error code otherwise. + */ +int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) { + struct dpmac_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY, cmd_flags, dprc_token); - - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpmac_cmd_destroy *)cmd.params; + cmd_params->dpmac_id = cpu_to_le32(object_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpmac_set_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpmac_set_link_state() - Set the Ethernet link status + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @link_state: Link state configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpmac_link_state *link_state) { + struct dpmac_cmd_set_link_state *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, - cmd_flags, - token); - DPMAC_CMD_SET_LINK_STATE(cmd, link_state); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, cmd_flags, token); + cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params; + cmd_params->options = cpu_to_le64(link_state->options); + cmd_params->rate = cpu_to_le32(link_state->rate); + cmd_params->up = dpmac_get_field(link_state->up, STATE); + dpmac_set_field(cmd_params->up, STATE_VALID, link_state->state_valid); + cmd_params->supported = cpu_to_le64(link_state->supported); + cmd_params->advertising = cpu_to_le64(link_state->advertising); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpmac_get_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpmac_counter type, - uint64_t *counter) +/** + * dpmac_get_counter() - Read a specific DPMAC counter + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @type: The requested counter + * @counter: Returned counter value + * + * Return: The requested counter; '0' otherwise. + */ +int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpmac_counter type, uint64_t *counter) { + struct dpmac_cmd_get_counter *dpmac_cmd; + struct dpmac_rsp_get_counter *dpmac_rsp; struct mc_command cmd = { 0 }; int err = 0; @@ -125,36 +197,43 @@ int dpmac_get_counter(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER, cmd_flags, token); - DPMAC_CMD_GET_COUNTER(cmd, type); + dpmac_cmd = (struct dpmac_cmd_get_counter *)cmd.params; + dpmac_cmd->type = type; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); if (err) return err; - DPMAC_RSP_GET_COUNTER(cmd, *counter); + dpmac_rsp = (struct dpmac_rsp_get_counter *)cmd.params; + *counter = le64_to_cpu(dpmac_rsp->counter); return 0; } -int dpmac_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpmac_get_api_version() - Get Data Path MAC version + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of data path mac API + * @minor_ver: Minor version of data path mac API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; - /* prepare command */ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION, - cmd_flags, 0); + cmd_flags, + 0); - /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; - /* retrieve response parameters */ mc_cmd_read_api_version(&cmd, major_ver, minor_ver); return 0; diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index eebfe548cc6..a8e9e4684a5 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -26,29 +26,54 @@ #define DPMAC_CMDID_SET_LINK_STATE 0x0c31 #define DPMAC_CMDID_GET_COUNTER 0x0c41 -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_CREATE(cmd, cfg) \ - MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ - MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_GET_COUNTER(cmd, type) \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) +/* Macros for accessing command fields smaller than 1byte */ +#define DPMAC_MASK(field) \ + GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \ + DPMAC_##field##_SHIFT) +#define dpmac_set_field(var, field, val) \ + ((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field))) +#define dpmac_get_field(var, field) \ + (((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpmac_cmd_open { + __le32 dpmac_id; +}; + +struct dpmac_cmd_create { + __le32 mac_id; +}; + +struct dpmac_cmd_destroy { + __le32 dpmac_id; +}; + +#define DPMAC_STATE_SIZE 1 +#define DPMAC_STATE_SHIFT 0 +#define DPMAC_STATE_VALID_SIZE 1 +#define DPMAC_STATE_VALID_SHIFT 1 + +struct dpmac_cmd_set_link_state { + __le64 options; + __le32 rate; + __le32 pad; + /* only least significant bit is valid */ + u8 up; + u8 pad0[7]; + __le64 supported; + __le64 advertising; +}; + +struct dpmac_cmd_get_counter { + u8 type; +}; + +struct dpmac_rsp_get_counter { + __le64 pad; + __le64 counter; +}; + +#pragma pack(pop) /* Data Path MAC API * Contains initialization APIs and runtime control APIs for DPMAC @@ -56,42 +81,27 @@ do { \ struct fsl_mc_io; -/** - * dpmac_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpmac_id: DPMAC unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpmac_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpmac_id, - uint16_t *token); +int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token); + +int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** - * dpmac_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. + * struct dpmac_cfg - Structure representing DPMAC configuration + * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, + * the MAC IDs are continuous. + * For example: 2 WRIOPs, 16 MACs in each: + * MAC IDs for the 1st WRIOP: 1-16, + * MAC IDs for the 2nd WRIOP: 17-32. */ -int dpmac_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +struct dpmac_cfg { + int mac_id; +}; + +int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpmac_cfg *cfg, u32 *obj_id); + +int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); /** * enum dpmac_link_type - DPMAC link type @@ -131,60 +141,6 @@ enum dpmac_eth_if { DPMAC_ETH_IF_XFI }; -/** - * struct dpmac_cfg - Structure representing DPMAC configuration - * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, - * the MAC IDs are continuous. - * For example: 2 WRIOPs, 16 MACs in each: - * MAC IDs for the 1st WRIOP: 1-16, - * MAC IDs for the 2nd WRIOP: 17-32. - */ -struct dpmac_cfg { - int mac_id; -}; - -/** - * dpmac_create() - Create the DPMAC object. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPMAC object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpmac_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpmac_cfg *cfg, - uint32_t *obj_id); - -/** - * dpmac_destroy() - Destroy the DPMAC object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: DPMAC object id - * - * Return: '0' on Success; error code otherwise. - */ -int dpmac_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); - /* DPMAC IRQ Index and Events */ /* IRQ index */ @@ -208,7 +164,7 @@ struct dpmac_attr { int phy_id; enum dpmac_link_type link_type; enum dpmac_eth_if eth_if; - uint32_t max_rate; + u32 max_rate; }; /* DPMAC link configuration/state options */ @@ -227,27 +183,21 @@ struct dpmac_attr { * @rate: Rate in Mbps * @options: Enable/Disable DPMAC link cfg features (bitmap) * @up: Link state + * @state_valid: Ignore/Update the state of the link + * @supported: Speeds capability of the phy (bitmap) + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpmac_link_state { - uint32_t rate; - uint64_t options; - int up; + u32 rate; + u64 options; + int up; + int state_valid; + u64 supported; + u64 advertising; }; -/** - * dpmac_set_link_state() - Set the Ethernet link status - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @link_state: Link state configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_set_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_state *link_state); - +int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpmac_link_state *link_state); /** * enum dpni_counter - DPNI counter types * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad. @@ -326,34 +276,10 @@ enum dpmac_counter { DPMAC_CNT_EGR_GOOD_FRAME, }; -/** - * dpmac_get_counter() - Read a specific DPMAC counter - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @type: The requested counter - * @counter: Returned counter value - * - * Return: The requested counter; '0' otherwise. - */ -int dpmac_get_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpmac_counter type, - uint64_t *counter); -/** - * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPMAC major version - * @minor_ver: DPMAC minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_api_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t *major_ver, - uint16_t *minor_ver); +int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpmac_counter type, u64 *counter); + +int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* __FSL_DPMAC_H */ -- cgit v1.3.1 From 95f309a4f81153f30edd52bb2ce0fad1d69bdb7a Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:32 +0300 Subject: net: fsl-mc: sync DPRC MC APIs Sync the Data Resource Container APIs to their latest form, this means the layout of each command is created based on structures which clearly describe the endianness of each field rather than some macros. The command version is kept in place, meaning that the minimum MC version accepted is not changed in any way. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dprc.c | 232 +++++++++++++++++++------ include/fsl-mc/fsl_dprc.h | 424 +++++++++++----------------------------------- 2 files changed, 280 insertions(+), 376 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c index 2be56e24a18..d1a74ab47a9 100644 --- a/drivers/net/fsl-mc/dprc.c +++ b/drivers/net/fsl-mc/dprc.c @@ -3,16 +3,22 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include #include #include -int dprc_get_container_id(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int *container_id) +/** + * dprc_get_container_id - Get container ID associated with a given portal. + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Requested container id + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id) { struct mc_command cmd = { 0 }; int err; @@ -28,23 +34,33 @@ int dprc_get_container_id(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPRC_RSP_GET_CONTAINER_ID(cmd, *container_id); + *container_id = (int)mc_cmd_read_object_id(&cmd); return 0; } -int dprc_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int container_id, - uint16_t *token) +/** + * dprc_open() - Open DPRC object for use + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Container ID to open + * @token: Returned token of DPRC object + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Required before any operation on the object. + */ +int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token) { + struct dprc_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags, 0); - DPRC_CMD_OPEN(cmd, container_id); + cmd_params = (struct dprc_cmd_open *)cmd.params; + cmd_params->container_id = cpu_to_le32(container_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -52,14 +68,23 @@ int dprc_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return 0; } -int dprc_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dprc_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -71,22 +96,35 @@ int dprc_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dprc_create_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_cfg *cfg, - int *child_container_id, - uint64_t *child_portal_paddr) +/** + * dprc_create_container() - Create child container + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @cfg: Child container configuration + * @child_container_id: Returned child container ID + * @child_portal_offset:Returned child portal offset from MC portal base + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dprc_cfg *cfg, int *child_container_id, + uint64_t *child_portal_offset) { + struct dprc_cmd_create_container *cmd_params; + struct dprc_rsp_create_container *rsp_params; struct mc_command cmd = { 0 }; - int err; + int err, i; /* prepare command */ - DPRC_CMD_CREATE_CONTAINER(cmd, cfg); - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT, - cmd_flags, - token); + cmd_flags, token); + cmd_params = (struct dprc_cmd_create_container *)cmd.params; + cmd_params->options = cpu_to_le32(cfg->options); + cmd_params->icid = cpu_to_le32(cfg->icid); + cmd_params->portal_id = cpu_to_le32(cfg->portal_id); + for (i = 0; i < 16; i++) + cmd_params->label[i] = cfg->label[i]; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -94,80 +132,156 @@ int dprc_create_container(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id, - *child_portal_paddr); + rsp_params = (struct dprc_rsp_create_container *)cmd.params; + *child_container_id = le32_to_cpu(rsp_params->child_container_id); + *child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr); return 0; } -int dprc_destroy_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_destroy_container() - Destroy child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to destroy + * + * This function terminates the child container, so following this call the + * child container ID becomes invalid. + * + * Notes: + * - All resources and objects of the destroyed container are returned to the + * parent container or destroyed if were created be the destroyed container. + * - This function destroy all the child containers of the specified + * container prior to destroying the container itself. + * + * warning: Only the parent container is allowed to destroy a child policy + * Container 0 can't be destroyed + * + * Return: '0' on Success; Error code otherwise. + * + */ +int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, int child_container_id) { + struct dprc_cmd_destroy_container *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT, - cmd_flags, - token); - DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id); + cmd_flags, token); + cmd_params = (struct dprc_cmd_destroy_container *)cmd.params; + cmd_params->child_container_id = cpu_to_le32(child_container_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dprc_connect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_connect() - Connect two endpoints to create a network link between them + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint1: Endpoint 1 configuration parameters + * @endpoint2: Endpoint 2 configuration parameters + * @cfg: Connection configuration. The connection configuration + * is ignored for connections made to DPMAC objects, where + * rate is retrieved from the MAC configuration. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dprc_endpoint *endpoint1, const struct dprc_endpoint *endpoint2, const struct dprc_connection_cfg *cfg) { + struct dprc_cmd_connect *cmd_params; struct mc_command cmd = { 0 }; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT, cmd_flags, token); - DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg); + cmd_params = (struct dprc_cmd_connect *)cmd.params; + cmd_params->ep1_id = cpu_to_le32(endpoint1->id); + cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id); + cmd_params->ep2_id = cpu_to_le32(endpoint2->id); + cmd_params->ep2_interface_id = cpu_to_le16(endpoint2->if_id); + cmd_params->max_rate = cpu_to_le32(cfg->max_rate); + cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate); + for (i = 0; i < 16; i++) { + cmd_params->ep1_type[i] = endpoint1->type[i]; + cmd_params->ep2_type[i] = endpoint2->type[i]; + } /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dprc_disconnect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_disconnect() - Disconnect one endpoint to remove its network connection + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint: Endpoint configuration parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dprc_endpoint *endpoint) { + struct dprc_cmd_disconnect *cmd_params; struct mc_command cmd = { 0 }; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT, cmd_flags, token); - DPRC_CMD_DISCONNECT(cmd, endpoint); + cmd_params = (struct dprc_cmd_disconnect *)cmd.params; + cmd_params->id = cpu_to_le32(endpoint->id); + cmd_params->interface_id = cpu_to_le32(endpoint->if_id); + for (i = 0; i < 16; i++) + cmd_params->type[i] = endpoint->type[i]; /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dprc_get_connection(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_get_connection() - Get connected endpoint and link status if connection + * exists. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint1: Endpoint 1 configuration parameters + * @endpoint2: Returned endpoint 2 configuration parameters + * @state: Returned link state: + * 1 - link is up; + * 0 - link is down; + * -1 - no connection (endpoint2 information is irrelevant) + * + * Return: '0' on Success; -ENAVAIL if connection does not exist. + */ +int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dprc_endpoint *endpoint1, - struct dprc_endpoint *endpoint2, - int *state) + struct dprc_endpoint *endpoint2, int *state) { + struct dprc_cmd_get_connection *cmd_params; + struct dprc_rsp_get_connection *rsp_params; struct mc_command cmd = { 0 }; - int err; + int err, i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION, cmd_flags, token); - DPRC_CMD_GET_CONNECTION(cmd, endpoint1); + cmd_params = (struct dprc_cmd_get_connection *)cmd.params; + cmd_params->ep1_id = cpu_to_le32(endpoint1->id); + cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id); + for (i = 0; i < 16; i++) + cmd_params->ep1_type[i] = endpoint1->type[i]; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -175,15 +289,27 @@ int dprc_get_connection(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPRC_RSP_GET_CONNECTION(cmd, endpoint2, *state); + rsp_params = (struct dprc_rsp_get_connection *)cmd.params; + endpoint2->id = le32_to_cpu(rsp_params->ep2_id); + endpoint2->if_id = le16_to_cpu(rsp_params->ep2_interface_id); + *state = le32_to_cpu(rsp_params->state); + for (i = 0; i < 16; i++) + endpoint2->type[i] = rsp_params->ep2_type[i]; return 0; } -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dprc_get_api_version - Get Data Path Resource Container API version + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of Data Path Resource Container API + * @minor_ver: Minor version of Data Path Resource Container API + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 0b95a06a911..fb95ac544a0 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -3,7 +3,7 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPRC_H #define _FSL_DPRC_H @@ -26,161 +26,71 @@ #define DPRC_CMDID_DISCONNECT 0x1681 #define DPRC_CMDID_GET_CONNECTION 0x16C1 -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \ - MC_RSP_OP(cmd, 0, 0, 32, int, container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_OPEN(cmd, container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \ - MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \ - MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ - MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \ - MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[3]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[4]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[5]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[6]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[7]); \ - MC_CMD_OP(cmd, 3, 0, 8, char, endpoint1->type[8]); \ - MC_CMD_OP(cmd, 3, 8, 8, char, endpoint1->type[9]); \ - MC_CMD_OP(cmd, 3, 16, 8, char, endpoint1->type[10]); \ - MC_CMD_OP(cmd, 3, 24, 8, char, endpoint1->type[11]); \ - MC_CMD_OP(cmd, 3, 32, 8, char, endpoint1->type[12]); \ - MC_CMD_OP(cmd, 3, 40, 8, char, endpoint1->type[13]); \ - MC_CMD_OP(cmd, 3, 48, 8, char, endpoint1->type[14]); \ - MC_CMD_OP(cmd, 3, 56, 8, char, endpoint1->type[15]); \ - MC_CMD_OP(cmd, 4, 0, 32, uint32_t, cfg->max_rate); \ - MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \ - MC_CMD_OP(cmd, 5, 0, 8, char, endpoint2->type[0]); \ - MC_CMD_OP(cmd, 5, 8, 8, char, endpoint2->type[1]); \ - MC_CMD_OP(cmd, 5, 16, 8, char, endpoint2->type[2]); \ - MC_CMD_OP(cmd, 5, 24, 8, char, endpoint2->type[3]); \ - MC_CMD_OP(cmd, 5, 32, 8, char, endpoint2->type[4]); \ - MC_CMD_OP(cmd, 5, 40, 8, char, endpoint2->type[5]); \ - MC_CMD_OP(cmd, 5, 48, 8, char, endpoint2->type[6]); \ - MC_CMD_OP(cmd, 5, 56, 8, char, endpoint2->type[7]); \ - MC_CMD_OP(cmd, 6, 0, 8, char, endpoint2->type[8]); \ - MC_CMD_OP(cmd, 6, 8, 8, char, endpoint2->type[9]); \ - MC_CMD_OP(cmd, 6, 16, 8, char, endpoint2->type[10]); \ - MC_CMD_OP(cmd, 6, 24, 8, char, endpoint2->type[11]); \ - MC_CMD_OP(cmd, 6, 32, 8, char, endpoint2->type[12]); \ - MC_CMD_OP(cmd, 6, 40, 8, char, endpoint2->type[13]); \ - MC_CMD_OP(cmd, 6, 48, 8, char, endpoint2->type[14]); \ - MC_CMD_OP(cmd, 6, 56, 8, char, endpoint2->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_DISCONNECT(cmd, endpoint) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint->id); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, endpoint->type[0]); \ - MC_CMD_OP(cmd, 1, 8, 8, char, endpoint->type[1]); \ - MC_CMD_OP(cmd, 1, 16, 8, char, endpoint->type[2]); \ - MC_CMD_OP(cmd, 1, 24, 8, char, endpoint->type[3]); \ - MC_CMD_OP(cmd, 1, 32, 8, char, endpoint->type[4]); \ - MC_CMD_OP(cmd, 1, 40, 8, char, endpoint->type[5]); \ - MC_CMD_OP(cmd, 1, 48, 8, char, endpoint->type[6]); \ - MC_CMD_OP(cmd, 1, 56, 8, char, endpoint->type[7]); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint->type[8]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint->type[9]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint->type[10]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint->type[11]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint->type[12]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint->type[13]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint->type[14]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \ - MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \ - MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \ - MC_CMD_OP(cmd, 1, 24, 8, char, endpoint1->type[3]); \ - MC_CMD_OP(cmd, 1, 32, 8, char, endpoint1->type[4]); \ - MC_CMD_OP(cmd, 1, 40, 8, char, endpoint1->type[5]); \ - MC_CMD_OP(cmd, 1, 48, 8, char, endpoint1->type[6]); \ - MC_CMD_OP(cmd, 1, 56, 8, char, endpoint1->type[7]); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[8]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[9]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[10]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[11]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[12]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[13]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[14]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \ -do { \ - MC_RSP_OP(cmd, 3, 0, 32, int, endpoint2->id); \ - MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \ - MC_RSP_OP(cmd, 4, 0, 8, char, endpoint2->type[0]); \ - MC_RSP_OP(cmd, 4, 8, 8, char, endpoint2->type[1]); \ - MC_RSP_OP(cmd, 4, 16, 8, char, endpoint2->type[2]); \ - MC_RSP_OP(cmd, 4, 24, 8, char, endpoint2->type[3]); \ - MC_RSP_OP(cmd, 4, 32, 8, char, endpoint2->type[4]); \ - MC_RSP_OP(cmd, 4, 40, 8, char, endpoint2->type[5]); \ - MC_RSP_OP(cmd, 4, 48, 8, char, endpoint2->type[6]); \ - MC_RSP_OP(cmd, 4, 56, 8, char, endpoint2->type[7]); \ - MC_RSP_OP(cmd, 5, 0, 8, char, endpoint2->type[8]); \ - MC_RSP_OP(cmd, 5, 8, 8, char, endpoint2->type[9]); \ - MC_RSP_OP(cmd, 5, 16, 8, char, endpoint2->type[10]); \ - MC_RSP_OP(cmd, 5, 24, 8, char, endpoint2->type[11]); \ - MC_RSP_OP(cmd, 5, 32, 8, char, endpoint2->type[12]); \ - MC_RSP_OP(cmd, 5, 40, 8, char, endpoint2->type[13]); \ - MC_RSP_OP(cmd, 5, 48, 8, char, endpoint2->type[14]); \ - MC_RSP_OP(cmd, 5, 56, 8, char, endpoint2->type[15]); \ - MC_RSP_OP(cmd, 6, 0, 32, int, state); \ -} while (0) +#pragma pack(push, 1) +struct dprc_cmd_open { + __le32 container_id; +}; + +struct dprc_cmd_create_container { + __le32 options; + __le32 icid; + __le32 pad1; + __le32 portal_id; + u8 label[16]; +}; + +struct dprc_rsp_create_container { + __le64 pad0; + __le32 child_container_id; + __le32 pad1; + __le64 child_portal_addr; +}; + +struct dprc_cmd_destroy_container { + __le32 child_container_id; +}; + +struct dprc_cmd_connect { + __le32 ep1_id; + __le16 ep1_interface_id; + __le16 pad0; + + __le32 ep2_id; + __le16 ep2_interface_id; + __le16 pad1; + + u8 ep1_type[16]; + + __le32 max_rate; + __le32 committed_rate; + + u8 ep2_type[16]; +}; + +struct dprc_cmd_disconnect { + __le32 id; + __le32 interface_id; + u8 type[16]; +}; + +struct dprc_cmd_get_connection { + __le32 ep1_id; + __le16 ep1_interface_id; + __le16 pad; + + u8 ep1_type[16]; +}; + +struct dprc_rsp_get_connection { + __le64 pad[3]; + __le32 ep2_id; + __le16 ep2_interface_id; + __le16 pad1; + u8 ep2_type[16]; + __le32 state; +}; + +#pragma pack(pop) /* Data Path Resource Container API * Contains DPRC API for managing and querying DPAA resources @@ -193,7 +103,7 @@ struct fsl_mc_io; * container, in case the ICID is not selected by the user and should be * allocated by the DPRC from the pool of ICIDs. */ -#define DPRC_GET_ICID_FROM_POOL (uint16_t)(~(0)) +#define DPRC_GET_ICID_FROM_POOL (u16)(~(0)) /** * Set this value as the portal_id value in dprc_cfg structure when creating a @@ -202,48 +112,11 @@ struct fsl_mc_io; */ #define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0)) -/** - * dprc_get_container_id() - Get container ID associated with a given portal. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Requested container ID - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_container_id(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int *container_id); +int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id); -/** - * dprc_open() - Open DPRC object for use - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Container ID to open - * @token: Returned token of DPRC object - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Required before any operation on the object. - */ -int dprc_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int container_id, - uint16_t *token); +int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token); -/** - * dprc_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * Container general options @@ -293,71 +166,18 @@ int dprc_close(struct fsl_mc_io *mc_io, * @label: Object's label */ struct dprc_cfg { - uint16_t icid; + u16 icid; int portal_id; uint64_t options; char label[16]; }; -/** - * dprc_create_container() - Create child container - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @cfg: Child container configuration - * @child_container_id: Returned child container ID - * @child_portal_offset: Returned child portal offset from MC portal base - * - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_create_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_cfg *cfg, - int *child_container_id, - uint64_t *child_portal_offset); - -/** - * dprc_destroy_container() - Destroy child container. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @child_container_id: ID of the container to destroy - * - * This function terminates the child container, so following this call the - * child container ID becomes invalid. - * - * Notes: - * - All resources and objects of the destroyed container are returned to the - * parent container or destroyed if were created be the destroyed container. - * - This function destroy all the child containers of the specified - * container prior to destroying the container itself. - * - * warning: Only the parent container is allowed to destroy a child policy - * Container 0 can't be destroyed - * - * Return: '0' on Success; Error code otherwise. - * - */ -int dprc_destroy_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id); +int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dprc_cfg *cfg, int *child_container_id, + uint64_t *child_portal_offset); -/** - * struct dprc_endpoint - Endpoint description for link connect/disconnect - * operations - * @type: Endpoint object type: NULL terminated string - * @id: Endpoint object ID - * @if_id: Interface ID; should be set for endpoints with multiple - * interfaces ("dpsw", "dpdmux"); for others, always set to 0 - */ -struct dprc_endpoint { - char type[16]; - int id; - uint16_t if_id; -}; +int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + int child_container_id); /** * struct dprc_connection_cfg - Connection configuration. @@ -366,79 +186,37 @@ struct dprc_endpoint { * @max_rate: Maximum rate (Mbits/s) */ struct dprc_connection_cfg { - uint32_t committed_rate; - uint32_t max_rate; + u32 committed_rate; + u32 max_rate; }; /** - * dprc_connect() - Connect two endpoints to create a network link between them - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @endpoint1: Endpoint 1 configuration parameters - * @endpoint2: Endpoint 2 configuration parameters - * @cfg: Connection configuration. The connection configuration is ignored for - * connections made to DPMAC objects, where rate is retrieved from the - * MAC configuration. - * - * Return: '0' on Success; Error code otherwise. + * struct dprc_endpoint - Endpoint description for link connect/disconnect + * operations + * @type: Endpoint object type: NULL terminated string + * @id: Endpoint object ID + * @if_id: Interface ID; should be set for endpoints with multiple + * interfaces ("dpsw", "dpdmux"); for others, always set to 0 */ -int dprc_connect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint1, - const struct dprc_endpoint *endpoint2, - const struct dprc_connection_cfg *cfg); +struct dprc_endpoint { + char type[16]; + int id; + u16 if_id; +}; -/** - * dprc_disconnect() - Disconnect one endpoint to remove its network connection - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @endpoint: Endpoint configuration parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_disconnect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint); +int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint1, + const struct dprc_endpoint *endpoint2, + const struct dprc_connection_cfg *cfg); -/** -* dprc_get_connection() - Get connected endpoint and link status if connection -* exists. -* @mc_io: Pointer to MC portal's I/O object -* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -* @token: Token of DPRC object -* @endpoint1: Endpoint 1 configuration parameters -* @endpoint2: Returned endpoint 2 configuration parameters -* @state: Returned link state: -* 1 - link is up; -* 0 - link is down; -* -1 - no connection (endpoint2 information is irrelevant) -* -* Return: '0' on Success; -ENAVAIL if connection does not exist. -*/ -int dprc_get_connection(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint1, - struct dprc_endpoint *endpoint2, - int *state); +int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint); -/** - * dprc_get_api_version - Retrieve DPRC Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPRC major version - * @minor_ver: DPRC minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint1, + struct dprc_endpoint *endpoint2, int *state); + +int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPRC_H */ -- cgit v1.3.1 From 207c8157709e3be8fb3338b5840de4a01767b79b Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:33 +0300 Subject: net: fsl-mc: sync DPNI MC APIs Sync the Data Path Network Interface APIs to their latest form, this means the layout of each command is created based on structures which clearly describe the endianness of each field rather than some macros. The command version is kept in place, meaning that the minimum MC version accepted is not changed in any way. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpni.c | 582 +++++++++++++++----- drivers/net/fsl-mc/mc.c | 14 +- drivers/net/ldpaa_eth/ldpaa_eth.c | 22 +- include/fsl-mc/fsl_dpni.h | 1101 +++++++++++++++++-------------------- 4 files changed, 990 insertions(+), 729 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index d0596a8e38d..5b815a45a99 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -1,36 +1,43 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include #include #include -int dpni_prepare_cfg(const struct dpni_cfg *cfg, - uint8_t *cfg_buf) -{ - uint64_t *params = (uint64_t *)cfg_buf; - - DPNI_PREP_CFG(params, cfg); - - return 0; -} - -int dpni_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpni_id, - uint16_t *token) +/** + * dpni_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpni_id: DPNI unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpni_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token) { + struct dpni_cmd_open *cmd_params; struct mc_command cmd = { 0 }; + int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN, cmd_flags, 0); - DPNI_CMD_OPEN(cmd, dpni_id); + cmd_params = (struct dpni_cmd_open *)cmd.params; + cmd_params->dpni_id = cpu_to_le32(dpni_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -38,14 +45,23 @@ int dpni_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return 0; } -int dpni_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -58,12 +74,32 @@ int dpni_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpni_cfg *cfg, - uint32_t *obj_id) +/** + * dpni_create() - Create the DPNI object + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id + * + * Create the DPNI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * The function accepts an authentication token of a parent + * container that this object should be assigned to. The token + * can be '0' so the object will be assigned to the default container. + * The newly created object can be opened with the returned + * object id and using the container's associated tokens and MC portals. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpni_cfg *cfg, u32 *obj_id) { + struct dpni_cmd_create *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -71,7 +107,19 @@ int dpni_create(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE, cmd_flags, dprc_token); - DPNI_CMD_CREATE(cmd, cfg); + cmd_params = (struct dpni_cmd_create *)cmd.params; + cmd_params->options = cpu_to_le32(cfg->options); + cmd_params->num_queues = cfg->num_queues; + cmd_params->num_tcs = cfg->num_tcs; + cmd_params->mac_filter_entries = cfg->mac_filter_entries; + cmd_params->num_rx_tcs = cfg->num_rx_tcs; + cmd_params->vlan_filter_entries = cfg->vlan_filter_entries; + cmd_params->qos_entries = cfg->qos_entries; + cmd_params->fs_entries = cpu_to_le16(cfg->fs_entries); + cmd_params->num_cgs = cfg->num_cgs; + cmd_params->num_opr = cfg->num_opr; + cmd_params->dist_key_size = cfg->dist_key_size; + cmd_params->num_channels = cfg->num_channels; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -79,50 +127,94 @@ int dpni_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpni_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpni_destroy() - Destroy the DPNI object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) { + struct dpni_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY, cmd_flags, dprc_token); - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpni_cmd_destroy *)cmd.params; + cmd_params->dpni_id = cpu_to_le32(object_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_set_pools(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_set_pools() - Set buffer pools configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Buffer pools configuration + * + * mandatory for DPNI operation + * warning:Allowed only when DPNI is disabled + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dpni_pools_cfg *cfg) { struct mc_command cmd = { 0 }; + struct dpni_cmd_set_pools *cmd_params; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS, cmd_flags, token); - DPNI_CMD_SET_POOLS(cmd, cfg); + cmd_params = (struct dpni_cmd_set_pools *)cmd.params; + cmd_params->num_dpbp = cfg->num_dpbp; + cmd_params->pool_options = cfg->pool_options; + for (i = 0; i < DPNI_MAX_DPBP; i++) { + cmd_params->pool[i].dpbp_id = + cpu_to_le16(cfg->pools[i].dpbp_id); + cmd_params->pool[i].priority_mask = + cfg->pools[i].priority_mask; + cmd_params->buffer_size[i] = + cpu_to_le16(cfg->pools[i].buffer_size); + cmd_params->backup_pool_mask |= + DPNI_BACKUP_POOL(cfg->pools[i].backup_pool, i); + } /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_enable() - Enable the DPNI, allow sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -135,9 +227,15 @@ int dpni_enable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_disable() - Disable the DPNI, stop sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -150,9 +248,15 @@ int dpni_disable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_reset() - Reset the DPNI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -165,59 +269,121 @@ int dpni_reset(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_get_attributes() - Retrieve DPNI attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @attr: Object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpni_attr *attr) { struct mc_command cmd = { 0 }; + struct dpni_rsp_get_attr *rsp_params; + int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR, cmd_flags, token); + /* send command to mc*/ err = mc_send_command(mc_io, &cmd); if (err) return err; /* retrieve response parameters */ - DPNI_RSP_GET_ATTR(cmd, attr); + rsp_params = (struct dpni_rsp_get_attr *)cmd.params; + attr->options = le32_to_cpu(rsp_params->options); + attr->num_queues = rsp_params->num_queues; + attr->num_rx_tcs = rsp_params->num_rx_tcs; + attr->num_tx_tcs = rsp_params->num_tx_tcs; + attr->mac_filter_entries = rsp_params->mac_filter_entries; + attr->vlan_filter_entries = rsp_params->vlan_filter_entries; + attr->num_channels = rsp_params->num_channels; + attr->qos_entries = rsp_params->qos_entries; + attr->fs_entries = le16_to_cpu(rsp_params->fs_entries); + attr->num_opr = le16_to_cpu(rsp_params->num_opr); + attr->qos_key_size = rsp_params->qos_key_size; + attr->fs_key_size = rsp_params->fs_key_size; + attr->wriop_version = le16_to_cpu(rsp_params->wriop_version); + attr->num_cgs = rsp_params->num_cgs; return 0; } -int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type) +/** + * dpni_set_buffer_layout() - Set buffer layout configuration. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue this configuration applies to + * @layout: Buffer layout configuration + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Allowed only when DPNI is disabled + */ +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, + const struct dpni_buffer_layout *layout) { + struct dpni_cmd_set_buffer_layout *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT, cmd_flags, token); - DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, type); + cmd_params = (struct dpni_cmd_set_buffer_layout *)cmd.params; + cmd_params->qtype = qtype; + cmd_params->options = cpu_to_le16((u16)layout->options); + dpni_set_field(cmd_params->flags, PASS_TS, layout->pass_timestamp); + dpni_set_field(cmd_params->flags, PASS_PR, layout->pass_parser_result); + dpni_set_field(cmd_params->flags, PASS_FS, layout->pass_frame_status); + dpni_set_field(cmd_params->flags, PASS_SWO, layout->pass_sw_opaque); + cmd_params->private_data_size = cpu_to_le16(layout->private_data_size); + cmd_params->data_align = cpu_to_le16(layout->data_align); + cmd_params->head_room = cpu_to_le16(layout->data_head_room); + cmd_params->tail_room = cpu_to_le16(layout->data_tail_room); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_qdid(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *qdid) +/** + * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used + * for enqueue operations + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue to receive QDID for + * @qdid: Returned virtual QDID value that should be used as an argument + * in all enqueue operations + * + * Return: '0' on Success; Error code otherwise. + * + * If dpni object is created using multiple Tc channels this function will return + * qdid value for the first channel + */ +int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 *qdid) { struct mc_command cmd = { 0 }; + struct dpni_cmd_get_qdid *cmd_params; + struct dpni_rsp_get_qdid *rsp_params; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID, cmd_flags, token); + cmd_params = (struct dpni_cmd_get_qdid *)cmd.params; + cmd_params->qtype = qtype; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -225,17 +391,26 @@ int dpni_get_qdid(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPNI_RSP_GET_QDID(cmd, *qdid); + rsp_params = (struct dpni_rsp_get_qdid *)cmd.params; + *qdid = le16_to_cpu(rsp_params->qdid); return 0; } -int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *data_offset) +/** + * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @data_offset: Tx data offset (from start of buffer) + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u16 *data_offset) { struct mc_command cmd = { 0 }; + struct dpni_rsp_get_tx_data_offset *rsp_params; int err; /* prepare command */ @@ -249,34 +424,54 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset); + rsp_params = (struct dpni_rsp_get_tx_data_offset *)cmd.params; + *data_offset = le16_to_cpu(rsp_params->data_offset); return 0; } -int dpni_set_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_set_link_cfg() - set the link configuration. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dpni_link_cfg *cfg) { struct mc_command cmd = { 0 }; + struct dpni_cmd_set_link_cfg *cmd_params; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG, cmd_flags, token); - DPNI_CMD_SET_LINK_CFG(cmd, cfg); + cmd_params = (struct dpni_cmd_set_link_cfg *)cmd.params; + cmd_params->rate = cpu_to_le32(cfg->rate); + cmd_params->options = cpu_to_le64(cfg->options); + cmd_params->advertising = cpu_to_le64(cfg->advertising); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_get_link_state() - Return the link state (either up or down) + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @state: Returned link state; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpni_link_state *state) { struct mc_command cmd = { 0 }; + struct dpni_rsp_get_link_state *rsp_params; int err; /* prepare command */ @@ -290,138 +485,279 @@ int dpni_get_link_state(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPNI_RSP_GET_LINK_STATE(cmd, state); + rsp_params = (struct dpni_rsp_get_link_state *)cmd.params; + state->up = dpni_get_field(rsp_params->flags, LINK_STATE); + state->state_valid = dpni_get_field(rsp_params->flags, STATE_VALID); + state->rate = le32_to_cpu(rsp_params->rate); + state->options = le64_to_cpu(rsp_params->options); + state->supported = le64_to_cpu(rsp_params->supported); + state->advertising = le64_to_cpu(rsp_params->advertising); return 0; } -int dpni_add_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]) +/** + * dpni_add_mac_addr() - Add MAC address filter + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mac_addr: MAC address to add + * @flags :0 - tc_id and flow_id will be ignored. + * Pkt with this mac_id will be passed to the next + * classification stages + * DPNI_MAC_SET_QUEUE_ACTION + * Pkt with this mac will be forward directly to + * queue defined by the tc_id and flow_id + * @tc_id : Traffic class selection (0-7) + * @flow_id : Selects the specific queue out of the set allocated for the + * same as tc_id. Value must be in range 0 to NUM_QUEUES - 1 + * Return: '0' on Success; Error code otherwise. + */ +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const u8 mac_addr[6], u8 flags, + u8 tc_id, u8 flow_id) { + struct dpni_cmd_add_mac_addr *cmd_params; struct mc_command cmd = { 0 }; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR, cmd_flags, token); - DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr); + cmd_params = (struct dpni_cmd_add_mac_addr *)cmd.params; + cmd_params->flags = flags; + cmd_params->tc_id = tc_id; + cmd_params->fq_id = flow_id; + + for (i = 0; i < 6; i++) + cmd_params->mac_addr[i] = mac_addr[5 - i]; /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpni_get_api_version() - Get Data Path Network Interface API version + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of data path network interface API + * @minor_ver: Minor version of data path network interface API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; - /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION, - cmd_flags, 0); + cmd_flags, + 0); - /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; - /* retrieve response parameters */ mc_cmd_read_api_version(&cmd, major_ver, minor_ver); return 0; } -int dpni_set_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - const struct dpni_queue *queue) +/** + * dpni_set_queue() - Set queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue - all queue types are supported, although + * the command is ignored for Tx + * @tc: Traffic class, in range 0 to NUM_TCS - 1 + * @index: Selects the specific queue out of the set allocated for the + * same TC. Value must be in range 0 to NUM_QUEUES - 1 + * @options: A combination of DPNI_QUEUE_OPT_ values that control what + * configuration options are set on the queue + * @queue: Queue structure + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + u8 options, const struct dpni_queue *queue) { struct mc_command cmd = { 0 }; + struct dpni_cmd_set_queue *cmd_params; + /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE, cmd_flags, token); - DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue); + cmd_params = (struct dpni_cmd_set_queue *)cmd.params; + cmd_params->qtype = qtype; + cmd_params->tc = (u8)(param & 0xff); + cmd_params->channel_id = (u8)((param >> 8) & 0xff); + cmd_params->index = index; + cmd_params->options = options; + cmd_params->dest_id = cpu_to_le32(queue->destination.id); + cmd_params->dest_prio = queue->destination.priority; + dpni_set_field(cmd_params->flags, DEST_TYPE, queue->destination.type); + dpni_set_field(cmd_params->flags, STASH_CTRL, queue->flc.stash_control); + dpni_set_field(cmd_params->flags, HOLD_ACTIVE, + queue->destination.hold_active); + cmd_params->flc = cpu_to_le64(queue->flc.value); + cmd_params->user_context = cpu_to_le64(queue->user_context); + cmd_params->cgid = queue->cgid; - /* send command to mc*/ + /* send command to mc */ return mc_send_command(mc_io, &cmd); } -int dpni_get_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - struct dpni_queue *queue) +/** + * dpni_get_queue() - Get queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue - all queue types are supported + * @param: Traffic class and channel ID. + * MSB - channel id; used only for DPNI_QUEUE_TX and + * DPNI_QUEUE_TX_CONFIRM, ignored for the rest + * LSB - traffic class + * Use macro DPNI_BUILD_PARAM() to build correct value. + * If dpni uses a single channel (uses only channel zero) + * the parameter can receive traffic class directly. + * @index: Selects the specific queue out of the set allocated for the + * same TC. Value must be in range 0 to NUM_QUEUES - 1 + * @queue: Queue configuration structure + * @qid: Queue identification + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + struct dpni_queue *queue, struct dpni_queue_id *qid) { struct mc_command cmd = { 0 }; + struct dpni_cmd_get_queue *cmd_params; + struct dpni_rsp_get_queue *rsp_params; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE, cmd_flags, token); - DPNI_CMD_GET_QUEUE(cmd, type, tc, index); + cmd_params = (struct dpni_cmd_get_queue *)cmd.params; + cmd_params->qtype = qtype; + cmd_params->tc = (u8)(param & 0xff); + cmd_params->index = index; + cmd_params->channel_id = (u8)((param >> 8) & 0xff); - /* send command to mc*/ + /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; /* retrieve response parameters */ - DPNI_RSP_GET_QUEUE(cmd, queue); + rsp_params = (struct dpni_rsp_get_queue *)cmd.params; + queue->destination.id = le32_to_cpu(rsp_params->dest_id); + queue->destination.priority = rsp_params->dest_prio; + queue->destination.type = dpni_get_field(rsp_params->flags, DEST_TYPE); + queue->flc.stash_control = dpni_get_field(rsp_params->flags, STASH_CTRL); + queue->destination.hold_active = dpni_get_field(rsp_params->flags, HOLD_ACTIVE); + queue->flc.value = le64_to_cpu(rsp_params->flc); + queue->user_context = le64_to_cpu(rsp_params->user_context); + qid->fqid = le32_to_cpu(rsp_params->fqid); + qid->qdbin = le16_to_cpu(rsp_params->qdbin); + if (dpni_get_field(rsp_params->flags, CGID_VALID)) + queue->cgid = rsp_params->cgid; + else + queue->cgid = -1; + return 0; } -int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_confirmation_mode mode) +/** + * dpni_set_tx_confirmation_mode() - Tx confirmation mode + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @ceetm_ch_idx: ceetm channel index + * @mode: Tx confirmation mode + * + * This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not + * selected at DPNI creation. + * Calling this function with 'mode' set to DPNI_CONF_DISABLE disables all + * transmit confirmation (including the private confirmation queues), regardless + * of previous settings; Note that in this case, Tx error frames are still + * enqueued to the general transmit errors queue. + * Calling this function with 'mode' set to DPNI_CONF_SINGLE switches all + * Tx confirmations to a shared Tx conf queue. 'index' field in dpni_get_queue + * command will be ignored. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 ceetm_ch_idx, enum dpni_confirmation_mode mode) { struct dpni_tx_confirmation_mode *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONFIRMATION_MODE, - cmd_flags, - token); - + cmd_flags, token); cmd_params = (struct dpni_tx_confirmation_mode *)cmd.params; + cmd_params->ceetm_ch_idx = ceetm_ch_idx; cmd_params->confirmation_mode = mode; /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t page, - union dpni_statistics *stat) +/** + * dpni_get_statistics() - Get DPNI statistics + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @page: Selects the statistics page to retrieve, see + * DPNI_GET_STATISTICS output. Pages are numbered 0 to 6. + * @param: Custom parameter for some pages used to select + * a certain statistic source, for example the TC. + * - page_0: not used + * - page_1: not used + * - page_2: not used + * - page_3: high_byte - channel_id, low_byte - traffic class + * - page_4: high_byte - queue_index have meaning only if dpni is + * created using option DPNI_OPT_CUSTOM_CG, low_byte - traffic class + * - page_5: not used + * - page_6: not used + * @stat: Structure containing the statistics + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 page, u16 param, union dpni_statistics *stat) { + struct dpni_cmd_get_statistics *cmd_params; + struct dpni_rsp_get_statistics *rsp_params; struct mc_command cmd = { 0 }; - int err; + int i, err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_STATISTICS, - cmd_flags, token); - DPNI_CMD_GET_STATISTICS(cmd, page); + cmd_flags, + token); + cmd_params = (struct dpni_cmd_get_statistics *)cmd.params; + cmd_params->page_number = page; + cmd_params->param = param; - /* send command to mc*/ + /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; /* retrieve response parameters */ - DPNI_RSP_GET_STATISTICS(cmd, stat); + rsp_params = (struct dpni_rsp_get_statistics *)cmd.params; + for (i = 0; i < DPNI_STATISTICS_CNT; i++) + stat->raw.counter[i] = le64_to_cpu(rsp_params->counter[i]); return 0; } diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 78a40f285aa..984616fb65c 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1353,10 +1353,9 @@ err: static int dpni_init(void) { - int err; - uint8_t cfg_buf[256] = {0}; - struct dpni_cfg dpni_cfg; + struct dpni_cfg dpni_cfg = {0}; uint16_t major_ver, minor_ver; + int err; dflt_dpni = calloc(sizeof(struct fsl_dpni_obj), 1); if (!dflt_dpni) { @@ -1365,14 +1364,6 @@ static int dpni_init(void) goto err_calloc; } - memset(&dpni_cfg, 0, sizeof(dpni_cfg)); - err = dpni_prepare_cfg(&dpni_cfg, &cfg_buf[0]); - if (err < 0) { - err = -ENODEV; - printf("dpni_prepare_cfg() failed: %d\n", err); - goto err_prepare_cfg; - } - err = dpni_create(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS, @@ -1429,7 +1420,6 @@ err_get_version: MC_CMD_NO_FLAGS, dflt_dpni->dpni_id); err_create: -err_prepare_cfg: free(dflt_dpni); err_calloc: return err; diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 8c0b5a3b6fd..87fbada06ba 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -58,7 +58,7 @@ static void ldpaa_eth_collect_dpni_stats(struct udevice *dev, u64 *data) continue; err = dpni_get_statistics(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - j, &dpni_stats); + j, 0, &dpni_stats); if (err) { memset(&dpni_stats, 0, sizeof(dpni_stats)); printf("dpni_get_stats(%d) failed\n", j); @@ -378,7 +378,8 @@ static int ldpaa_eth_open(struct udevice *dev) struct dpni_link_state link_state; #endif int err = 0; - struct dpni_queue d_queue; + struct dpni_queue d_queue_cfg = { 0 }; + struct dpni_queue_id d_queue; if (eth_is_active(dev)) return 0; @@ -422,7 +423,7 @@ static int ldpaa_eth_open(struct udevice *dev) goto err_dpni_bind; err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpni->dpni_handle, plat->enetaddr); + dflt_dpni->dpni_handle, plat->enetaddr, 0, 0, 0); if (err) { printf("dpni_add_mac_addr() failed\n"); return err; @@ -461,7 +462,7 @@ static int ldpaa_eth_open(struct udevice *dev) memset(&d_queue, 0, sizeof(struct dpni_queue)); err = dpni_get_queue(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, DPNI_QUEUE_RX, - 0, 0, &d_queue); + 0, 0, &d_queue_cfg, &d_queue); if (err) { printf("dpni_get_queue failed\n"); goto err_get_queue; @@ -470,7 +471,7 @@ static int ldpaa_eth_open(struct udevice *dev) priv->rx_dflt_fqid = d_queue.fqid; err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &priv->tx_qdid); + DPNI_QUEUE_TX, &priv->tx_qdid); if (err) { printf("dpni_get_qdid() failed\n"); goto err_qdid; @@ -845,7 +846,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) /* ...rx, ... */ err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &dflt_dpni->buf_layout, DPNI_QUEUE_RX); + DPNI_QUEUE_RX, &dflt_dpni->buf_layout); if (err) { printf("dpni_set_buffer_layout() failed"); goto err_buf_layout; @@ -857,7 +858,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) DPNI_BUF_LAYOUT_OPT_PARSER_RESULT); err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &dflt_dpni->buf_layout, DPNI_QUEUE_TX); + DPNI_QUEUE_TX, &dflt_dpni->buf_layout); if (err) { printf("dpni_set_buffer_layout() failed"); goto err_buf_layout; @@ -867,8 +868,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &dflt_dpni->buf_layout, - DPNI_QUEUE_TX_CONFIRM); + DPNI_QUEUE_TX_CONFIRM, &dflt_dpni->buf_layout); if (err) { printf("dpni_set_buffer_layout() failed"); goto err_buf_layout; @@ -923,7 +923,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) err = dpni_set_queue(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - DPNI_QUEUE_TX, 0, 0, &tx_queue); + DPNI_QUEUE_TX, 0, 0, 0, &tx_queue); if (err) { printf("dpni_set_queue() failed\n"); @@ -932,7 +932,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) err = dpni_set_tx_confirmation_mode(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - DPNI_CONF_DISABLE); + 0, DPNI_CONF_DISABLE); if (err) { printf("dpni_set_tx_confirmation_mode() failed\n"); return err; diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index fa15a141f1f..9bc475475df 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPNI_H #define _FSL_DPNI_H @@ -37,176 +37,229 @@ #define DPNI_CMDID_SET_QUEUE 0x2601 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661 -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_OPEN(cmd, dpni_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_PREP_CFG(param, cfg) \ -do { \ - MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ - MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ - MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ - MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ - MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ - MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ - MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->adv.options); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->adv.num_queues); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->adv.num_tcs); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->adv.mac_entries); \ - MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->adv.vlan_entries); \ - MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->adv.qos_entries); \ - MC_CMD_OP(cmd, 1, 32, 16, uint8_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_POOLS(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ - MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ - MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ - MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ - MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ - MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ - MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ - MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ - MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ - MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ - MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ - MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ - MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ - MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ - MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ - MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ - MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ - MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ - MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ - MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ - MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ - MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ - MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ - MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ - MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_ATTR(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->options);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_num_queues); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_num_tcs); \ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->max_mac_entries); \ - MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->max_vlan_entries); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->max_qos_entries); \ - MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fs_entries); \ - MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_qos_key_size); \ - MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_fs_key_size); \ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, queue); \ - MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \ - MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \ - MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \ - MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \ - MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \ - MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_QDID(cmd, qdid) \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ - MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_LINK_STATE(cmd, state) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ -} while (0) - -#define DPNI_RSP_GET_QUEUE(cmd, queue) \ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ - MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ - MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ - MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue)->fqid); \ - MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \ -} while (0) - -#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, (queue)->options); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ - MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ - MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ - MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_STATISTICS(cmd, page) \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_STATISTICS(cmd, stat) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->raw.counter[0]); \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->raw.counter[1]); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->raw.counter[2]); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->raw.counter[3]); \ - MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->raw.counter[4]); \ - MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->raw.counter[5]); \ - MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->raw.counter[6]); \ -} while (0) +/* Macros for accessing command fields smaller than 1byte */ +#define DPNI_MASK(field) \ + GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \ + DPNI_##field##_SHIFT) +#define dpni_set_field(var, field, val) \ + ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) +#define dpni_get_field(var, field) \ + (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpni_cmd_open { + __le32 dpni_id; +}; + +struct dpni_cmd_create { + __le32 options; + u8 num_queues; + u8 num_tcs; + u8 mac_filter_entries; + u8 num_channels; + u8 vlan_filter_entries; + u8 pad2; + u8 qos_entries; + u8 pad3; + __le16 fs_entries; + u8 num_rx_tcs; + u8 pad4; + u8 num_cgs; + __le16 num_opr; + u8 dist_key_size; +}; + +struct dpni_cmd_destroy { + __le32 dpni_id; +}; + +#define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) + +struct dpni_cmd_pool { + __le16 dpbp_id; + u8 priority_mask; + u8 pad; +}; + +struct dpni_cmd_set_pools { + u8 num_dpbp; + u8 backup_pool_mask; + u8 pad; + u8 pool_options; + struct dpni_cmd_pool pool[8]; + __le16 buffer_size[8]; +}; + +struct dpni_rsp_get_attr { + /* response word 0 */ + __le32 options; + u8 num_queues; + u8 num_rx_tcs; + u8 mac_filter_entries; + u8 num_tx_tcs; + /* response word 1 */ + u8 vlan_filter_entries; + u8 num_channels; + u8 qos_entries; + u8 pad2; + __le16 fs_entries; + __le16 num_opr; + /* response word 2 */ + u8 qos_key_size; + u8 fs_key_size; + __le16 wriop_version; + u8 num_cgs; +}; + +/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation + * buffer layouts, but they all share the same parameters. + * If one of the functions changes, below structure needs to be split. + */ + +#define DPNI_PASS_TS_SHIFT 0 +#define DPNI_PASS_TS_SIZE 1 +#define DPNI_PASS_PR_SHIFT 1 +#define DPNI_PASS_PR_SIZE 1 +#define DPNI_PASS_FS_SHIFT 2 +#define DPNI_PASS_FS_SIZE 1 +#define DPNI_PASS_SWO_SHIFT 3 +#define DPNI_PASS_SWO_SIZE 1 + +struct dpni_cmd_set_buffer_layout { + /* cmd word 0 */ + u8 qtype; + u8 pad0[3]; + __le16 options; + /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ + u8 flags; + u8 pad1; + /* cmd word 1 */ + __le16 private_data_size; + __le16 data_align; + __le16 head_room; + __le16 tail_room; +}; + +struct dpni_cmd_get_qdid { + u8 qtype; +}; + +struct dpni_rsp_get_qdid { + __le16 qdid; +}; + +struct dpni_rsp_get_tx_data_offset { + __le16 data_offset; +}; + +struct dpni_cmd_set_link_cfg { + __le64 pad0; + __le32 rate; + __le32 pad1; + __le64 options; + __le64 advertising; +}; + +#define DPNI_LINK_STATE_SHIFT 0 +#define DPNI_LINK_STATE_SIZE 1 +#define DPNI_STATE_VALID_SHIFT 1 +#define DPNI_STATE_VALID_SIZE 1 + +struct dpni_rsp_get_link_state { + __le32 pad0; + /* from LSB: up:1 */ + u8 flags; + u8 pad1[3]; + __le32 rate; + __le32 pad2; + __le64 options; + __le64 supported; + __le64 advertising; +}; + +struct dpni_cmd_add_mac_addr { + u8 flags; + u8 pad; + u8 mac_addr[6]; + u8 tc_id; + u8 fq_id; +}; + +struct dpni_cmd_get_queue { + u8 qtype; + u8 tc; + u8 index; + u8 channel_id; +}; + +#define DPNI_DEST_TYPE_SHIFT 0 +#define DPNI_DEST_TYPE_SIZE 4 +#define DPNI_CGID_VALID_SHIFT 5 +#define DPNI_CGID_VALID_SIZE 1 +#define DPNI_STASH_CTRL_SHIFT 6 +#define DPNI_STASH_CTRL_SIZE 1 +#define DPNI_HOLD_ACTIVE_SHIFT 7 +#define DPNI_HOLD_ACTIVE_SIZE 1 + +struct dpni_rsp_get_queue { + /* response word 0 */ + __le64 pad0; + /* response word 1 */ + __le32 dest_id; + __le16 pad1; + u8 dest_prio; + /* From LSB: dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 */ + u8 flags; + /* response word 2 */ + __le64 flc; + /* response word 3 */ + __le64 user_context; + /* response word 4 */ + __le32 fqid; + __le16 qdbin; + __le16 pad2; + /* response word 5*/ + u8 cgid; +}; + +struct dpni_cmd_set_queue { + /* cmd word 0 */ + u8 qtype; + u8 tc; + u8 index; + u8 options; + __le32 pad0; + /* cmd word 1 */ + __le32 dest_id; + __le16 pad1; + u8 dest_prio; + u8 flags; + /* cmd word 2 */ + __le64 flc; + /* cmd word 3 */ + __le64 user_context; + /* cmd word 4 */ + u8 cgid; + u8 channel_id; +}; + +struct dpni_tx_confirmation_mode { + u8 ceetm_ch_idx; + u8 pad1; + __le16 pad2; + u8 confirmation_mode; +}; + +struct dpni_cmd_get_statistics { + u8 page_number; + __le16 param; +}; + +struct dpni_rsp_get_statistics { + __le64 counter[7]; +}; + +#pragma pack(pop) /** * Data Path Network Interface API @@ -223,50 +276,17 @@ struct fsl_mc_io; #define DPNI_MAX_DPBP 8 /* All traffic classes considered; see dpni_set_rx_flow() */ -#define DPNI_ALL_TCS (uint8_t)(-1) +#define DPNI_ALL_TCS (u8)(-1) /* All flows within traffic class considered; see dpni_set_rx_flow() */ -#define DPNI_ALL_TC_FLOWS (uint16_t)(-1) +#define DPNI_ALL_TC_FLOWS (u16)(-1) /* Generate new flow ID; see dpni_set_tx_flow() */ -#define DPNI_NEW_FLOW_ID (uint16_t)(-1) +#define DPNI_NEW_FLOW_ID (u16)(-1) /* use for common tx-conf queue; see dpni_set_tx_conf_() */ -#define DPNI_COMMON_TX_CONF (uint16_t)(-1) +#define DPNI_COMMON_TX_CONF (u16)(-1) -/** - * dpni_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpni_id: DPNI unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpni_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpni_id, - uint16_t *token); +int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token); -/** - * dpni_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /* DPNI configuration options */ @@ -329,17 +349,84 @@ enum dpni_queue_type { DPNI_QUEUE_RX_ERR, }; +/** + * struct dpni_cfg - Structure representing DPNI configuration + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_SINGLE_SENDER + * DPNI_OPT_STASHING_DIS + * @fs_entries: Number of entries in the flow steering table. + * This table is used to select the ingress queue for + * ingress traffic, targeting a GPP core or another. + * In addition it can be used to discard traffic that + * matches the set rule. It is either an exact match table + * or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING + * bit in OPTIONS field. This field is ignored if + * DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise, + * value 0 defaults to 64. Maximum supported value is 1024. + * Note that the total number of entries is limited on the + * SoC to as low as 512 entries if TCAM is used. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. This is an exact match table used to filter + * ingress traffic based on VLAN IDs. Value 0 disables VLAN + * filtering. Maximum supported value is 16. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. This is an exact match table and allows both + * unicast and multicast entries. The primary MAC address + * of the network interface is not part of this table, + * this contains only entries in addition to it. This + * field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in + * OPTIONS field. Otherwise, value 0 defaults to 80. + * Maximum supported value is 80. + * @num_queues: Number of Tx and Rx queues used for traffic + * distribution. This is orthogonal to QoS and is only + * used to distribute traffic to multiple GPP cores. + * This configuration affects the number of Tx queues + * (logical FQs, all associated with a single CEETM queue), + * Rx queues and Tx confirmation queues, if applicable. + * Value 0 defaults to one queue. Maximum supported value + * is 8. + * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI. + * TCs can have different priority levels for the purpose + * of Tx scheduling (see DPNI_SET_TX_PRIORITIES), different + * BPs (DPNI_ SET_POOLS), policers. There are dedicated QM + * queues for traffic classes (including class queues on + * Tx). Value 0 defaults to one TC. Maximum supported value + * is 16. There are maximum 16 TCs for Tx and 8 TCs for Rx. + * When num_tcs>8 Tx will use this value but Rx will have + * only 8 traffic classes. + * @num_rx_tcs: if set to other value than zero represents number + * of TCs used for Rx. Maximum value is 8. If set to zero the + * number of Rx TCs will be initialized with the value provided + * in num_tcs parameter. + * @qos_entries: Number of entries in the QoS classification table. This + * table is used to select the TC for ingress traffic. It + * is either an exact match or a TCAM table, depending on + * DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This + * field is ignored if the DPNI has a single TC. Otherwise, + * a value of 0 defaults to 64. Maximum supported value + * is 64. + * @num_channels: Number of egress channels used by this dpni object. If + * set to zero the dpni object will use a single CEETM channel. + */ struct dpni_cfg { - uint8_t mac_addr[6]; - struct { - uint32_t options; - uint16_t fs_entries; - uint8_t num_queues; - uint8_t num_tcs; - uint8_t mac_entries; - uint8_t vlan_entries; - uint8_t qos_entries; - } adv; + u32 options; + u16 fs_entries; + u8 vlan_filter_entries; + u8 mac_filter_entries; + u8 num_queues; + u8 num_tcs; + u8 num_rx_tcs; + u8 qos_entries; + u8 num_cgs; + u16 num_opr; + u8 dist_key_size; + u8 num_channels; }; /** @@ -350,168 +437,108 @@ struct dpni_cfg { * This function has to be called before dpni_create() */ int dpni_prepare_cfg(const struct dpni_cfg *cfg, - uint8_t *cfg_buf); -/** - * dpni_create() - Create the DPNI object - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPNI object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpni_open() function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpni_cfg *cfg, - uint32_t *obj_id); + u8 *cfg_buf); -/** - * dpni_destroy() - Destroy the DPNI object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Return: '0' on Success; error code otherwise. - */ -int dpni_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpni_cfg *cfg, u32 *obj_id); + +int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); /** * struct dpni_pools_cfg - Structure representing buffer pools configuration - * @num_dpbp: Number of DPBPs - * @pools: Array of buffer pools parameters; The number of valid entries - * must match 'num_dpbp' value + * @num_dpbp: Number of DPBPs + * @pool_options: Buffer assignment options + * This field is a combination of DPNI_POOL_ASSOC_flags + * @pools: Array of buffer pools parameters; The number of valid entries + * must match 'num_dpbp' value + * @pools.dpbp_id: DPBP object ID + * @pools.priority: Priority mask that indicates TC's used with this buffer. + * I set to 0x00 MC will assume value 0xff. + * @pools.buffer_size: Buffer size + * @pools.backup_pool: Backup pool */ + +#define DPNI_POOL_ASSOC_QPRI 0 +#define DPNI_POOL_ASSOC_QDBIN 1 + struct dpni_pools_cfg { - uint8_t num_dpbp; - /** - * struct pools - Buffer pools parameters - * @dpbp_id: DPBP object ID - * @buffer_size: Buffer size - * @backup_pool: Backup pool - */ + u8 num_dpbp; + u8 pool_options; struct { int dpbp_id; - uint16_t buffer_size; + u8 priority_mask; + u16 buffer_size; int backup_pool; } pools[DPNI_MAX_DPBP]; }; -/** - * dpni_set_pools() - Set buffer pools configuration - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Buffer pools configuration - * - * mandatory for DPNI operation - * warning:Allowed only when DPNI is disabled - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_pools(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_pools_cfg *cfg); - -/** - * dpni_enable() - Enable the DPNI, allow sending and receiving frames. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dpni_pools_cfg *cfg); -/** - * dpni_disable() - Disable the DPNI, stop sending and receiving frames. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpni_reset() - Reset the DPNI, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpni_attr - Structure representing DPNI attributes - * @options: Mask of available options; reflects the value as was given in - * object's creation - * @max_num_queues: Number of queues available (for both Tx and Rx) - * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx) - * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx) - * @max_unicast_filters: Maximum number of unicast filters - * @max_multicast_filters: Maximum number of multicast filters - * @max_vlan_entries: Maximum number of VLAN filters - * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table - * @max_fs_entries: declares the maximum entries in flow steering table - * @max_qos_key_size: Maximum key size for the QoS look-up - * @max_fs_key_size: Maximum key size for the flow steering - * @wriop_version: Indicates revision of WRIOP hardware block + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_STASHING_DIS + * @num_queues: Number of Tx and Rx queues used for traffic distribution. + * @num_rx_tcs: Number of RX traffic classes (TCs), reserved for the DPNI. + * @num_tx_tcs: Number of TX traffic classes (TCs), reserved for the DPNI. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. + * @qos_entries: Number of entries in the QoS classification table. + * @fs_entries: Number of entries in the flow steering table. + * @qos_key_size: Size, in bytes, of the QoS look-up key. Defining a key larger + * than this when adding QoS entries will result + * in an error. + * @fs_key_size: Size, in bytes, of the flow steering look-up key. Defining a + * key larger than this when composing the hash + FS key + * will result in an error. + * @wriop_version: Version of WRIOP HW block. + * The 3 version values are stored on 6, 5, 5 bits + * respectively. + * Values returned: + * - 0x400 - WRIOP version 1.0.0, used on LS2080 and + * variants, + * - 0x421 - WRIOP version 1.1.1, used on LS2088 and + * variants, + * - 0x422 - WRIOP version 1.1.2, used on LS1088 and + * variants. + * - 0xC00 - WRIOP version 3.0.0, used on LX2160 and + * variants. */ struct dpni_attr { - uint32_t id; - uint32_t options; - uint8_t max_num_queues; - uint8_t max_num_tcs; - uint8_t max_mac_entries; - uint8_t max_vlan_entries; - uint8_t max_qos_entries; - uint16_t max_fs_entries; - uint8_t max_qos_key_size; - uint8_t max_fs_key_size; - uint16_t wriop_version; + u32 options; + u8 num_queues; + u8 num_rx_tcs; + u8 num_tx_tcs; + u8 mac_filter_entries; + u8 vlan_filter_entries; + u8 qos_entries; + u16 fs_entries; + u16 num_opr; + u8 qos_key_size; + u8 fs_key_size; + u16 wriop_version; + u8 num_cgs; + u8 num_channels; }; -/** - * dpni_get_attributes() - Retrieve DPNI attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @attr: Object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_attr *attr); +int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpni_attr *attr); /* DPNI buffer layout modification options */ @@ -529,77 +556,45 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, #define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020 /*!< Select to modify the data-tail-room setting */ #define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 +/* Select to modify the sw-opaque value setting */ +#define DPNI_BUF_LAYOUT_OPT_SW_OPAQUE 0x00000080 +/* Select to disable Scatter Gather and use single buffer */ +#define DPNI_BUF_LAYOUT_OPT_NO_SG 0x00000100 /** * struct dpni_buffer_layout - Structure representing DPNI buffer layout - * @options: Flags representing the suggested modifications to the buffer - * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_' flags - * @pass_timestamp: Pass timestamp value - * @pass_parser_result: Pass parser results - * @pass_frame_status: Pass frame status - * @private_data_size: Size kept for private data (in bytes) - * @data_align: Data alignment - * @data_head_room: Data head room - * @data_tail_room: Data tail room + * @options: Flags representing the suggested modifications to the + * buffer layout; + * Use any combination of 'DPNI_BUF_LAYOUT_OPT_' flags + * @pass_timestamp: Pass timestamp value + * @pass_parser_result: Pass parser results + * @pass_frame_status: Pass frame status + * @private_data_size: Size kept for private data (in bytes) + * @data_align: Data alignment + * @data_head_room: Data head room + * @data_tail_room: Data tail room */ struct dpni_buffer_layout { - uint16_t options; + u32 options; int pass_timestamp; int pass_parser_result; int pass_frame_status; - uint16_t private_data_size; - uint16_t data_align; - uint16_t data_head_room; - uint16_t data_tail_room; + int pass_sw_opaque; + u16 private_data_size; + u16 data_align; + u16 data_head_room; + u16 data_tail_room; }; -/** - * dpni_set_buffer_layout() - Set buffer layout configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Buffer layout configuration - * @type: DPNI queue type - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Allowed only when DPNI is disabled - */ -int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type); +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, + const struct dpni_buffer_layout *layout); -/** - * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used - * for enqueue operations - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @qdid: Returned virtual QDID value that should be used as an argument - * in all enqueue operations - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_qdid(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *qdid); +int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 *qdid); -/** - * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @data_offset: Tx data offset (from start of buffer) - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *data_offset); +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u16 *data_offset); /* Enable auto-negotiation */ #define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL @@ -614,65 +609,44 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, * struct - Structure representing DPNI link configuration * @rate: Rate * @options: Mask of available options; use 'DPNI_LINK_OPT_' values + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpni_link_cfg { - uint32_t rate; - uint64_t options; + u32 rate; + u64 options; + u64 advertising; }; -/** - * dpni_set_link_cfg() - set the link configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Link configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_link_cfg *cfg); +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dpni_link_cfg *cfg); /** * struct dpni_link_state - Structure representing DPNI link state - * @rate: Rate - * @options: Mask of available options; use 'DPNI_LINK_OPT_' values - * @up: Link state; '0' for down, '1' for up + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_' values + * @up: Link state; '0' for down, '1' for up + * @state_valid: Ignore/Update the state of the link + * @supported: Speeds capability of the phy (bitmap) + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpni_link_state { - uint32_t rate; - uint64_t options; + u32 rate; + u64 options; int up; + int state_valid; + u64 supported; + u64 advertising; }; -/** - * dpni_get_link_state() - Return the link state (either up or down) - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @state: Returned link state; - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_link_state *state); +int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpni_link_state *state); -/** - * dpni_add_mac_addr() - Add MAC address filter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to add - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_add_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const u8 mac_addr[6], u8 flags, + u8 tc_id, u8 flow_id); + +int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); /** * enum dpni_dest - DPNI destination types @@ -702,21 +676,6 @@ enum dpni_dest { /*!< Select to modify the L4 checksum generation setting */ #define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 -/** - * dpni_get_api_version - Retrieve DPNI Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPNI major version - * @minor_ver: DPNI minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); - /** * enum dpni_confirmation_mode - Defines DPNI options supported for Tx * confirmation @@ -726,7 +685,7 @@ int dpni_get_api_version(struct fsl_mc_io *mc_io, * confirmation queue * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated * with proper FD set-up to have buffers release to a Buffer Pool, otherwise - * buffers will be leaked. + * buffers will be leaked */ enum dpni_confirmation_mode { DPNI_CONF_AFFINE, @@ -734,106 +693,97 @@ enum dpni_confirmation_mode { DPNI_CONF_DISABLE, }; -struct dpni_tx_confirmation_mode { - uint32_t pad; - uint8_t confirmation_mode; -}; +/** + * stashes the whole annotation area (up to 192 bytes) + */ +#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 /** * struct dpni_queue - Queue structure - * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ - * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant - * for Tx queues. - * @flc: FLC value for traffic dequeued from this queue. - * @user_context: User data, presented to the user along with any frames - * from this queue. Not relevant for Tx queues. + * @destination - Destination structure + * @destination.id: ID of the destination, only relevant if DEST_TYPE is > 0. + * Identifies either a DPIO or a DPCON object. + * Not relevant for Tx queues. + * @destination.type: May be one of the following: + * 0 - No destination, queue can be manually + * queried, but will not push traffic or + * notifications to a DPIO; + * 1 - The destination is a DPIO. When traffic + * becomes available in the queue a FQDAN + * (FQ data available notification) will be + * generated to selected DPIO; + * 2 - The destination is a DPCON. The queue is + * associated with a DPCON object for the + * purpose of scheduling between multiple + * queues. The DPCON may be independently + * configured to generate notifications. + * Not relevant for Tx queues. + * @destination.hold_active: Hold active, maintains a queue scheduled for longer + * in a DPIO during dequeue to reduce spread of traffic. + * Only relevant if queues are + * not affined to a single DPIO. + * @user_context: User data, presented to the user along with any frames + * from this queue. Not relevant for Tx queues. + * @flc: FD FLow Context structure + * @flc.value: Default FLC value for traffic dequeued from + * this queue. Please check description of FD + * structure for more information. + * Note that FLC values set using dpni_add_fs_entry, + * if any, take precedence over values per queue. + * @flc.stash_control: Boolean, indicates whether the 6 lowest + * - significant bits are used for stash control. + * significant bits are used for stash control. If set, the 6 + * least significant bits in value are interpreted as follows: + * - bits 0-1: indicates the number of 64 byte units of context + * that are stashed. FLC value is interpreted as a memory address + * in this case, excluding the 6 LS bits. + * - bits 2-3: indicates the number of 64 byte units of frame + * annotation to be stashed. Annotation is placed at FD[ADDR]. + * - bits 4-5: indicates the number of 64 byte units of frame + * data to be stashed. Frame data is placed at FD[ADDR] + + * FD[OFFSET]. + * For more details check the Frame Descriptor section in the + * hardware documentation. + *@cgid :indicate the cgid to set relative to dpni */ struct dpni_queue { - /** - * struct destination - Destination structure - * @id: ID of the destination, only relevant if DEST_TYPE is > 0. - * Identifies either a DPIO or a DPCON object. Not relevant for Tx - * queues. - * @type: May be one of the following: - * 0 - No destination, queue can be manually queried, but won't - * push traffic or notifications to a DPIO; - * 1 - The destination is DPIO. When traffic becomes available in - * the queue a FQDAN (FQ data available notification) will be - * generated to selected DPIO; - * 2 - The destination is a DPCON. The queue is associated with a - * DPCON object for purpose of scheduling between multiple - * queues. The DPCON may be independently configured to - * generate notifications. Not relevant for Tx queues. - * @hold_active: Hold active - */ struct { - uint32_t id; + u16 id; enum dpni_dest type; char hold_active; - char stash_ctrl; + u8 priority; } destination; - uint8_t options; - uint32_t fqid; - uint16_t qdbin; - uint64_t flc; - uint64_t user_context; + u64 user_context; + struct { + u64 value; + char stash_control; + } flc; + int cgid; }; /** - * dpni_set_queue() - Set queue parameters - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @type: Type of queue - * @tc: Traffic class, in range 0 to NUM_TCS - 1 - * @index: Selects the specific queue out of the set allocated for the same - * TC. Value must be in range 0 to NUM_QUEUES - 1 - * @queue: Queue structure - * - * Return: '0' on Success; Error code otherwise. + * struct dpni_queue_id - Queue identification, used for enqueue commands + * or queue control + * @fqid: FQID used for enqueueing to and/or configuration of this + * specific FQ + * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. + * Only relevant for Tx queues. */ -int dpni_set_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - const struct dpni_queue *queue); +struct dpni_queue_id { + u32 fqid; + u16 qdbin; +}; -/** - * dpni_get_queue() - Get queue parameters - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @type: Type of queue - * @tc: Traffic class, in range 0 to NUM_TCS - 1 - * @index: Selects the specific queue out of the set allocated for the same - * TC. Value must be in range 0 to NUM_QUEUES - 1 - * @queue: Queue structure - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - struct dpni_queue *queue); +int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + u8 options, const struct dpni_queue *queue); -/** - * dpni_set_tx_confirmation_mode() - Set TX conf mode - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mode: DPNI confirmation mode type - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_confirmation_mode mode); +int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + struct dpni_queue *queue, struct dpni_queue_id *qid); + +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 ceetm_ch_idx, enum dpni_confirmation_mode mode); #define DPNI_STATISTICS_CNT 7 @@ -931,21 +881,6 @@ union dpni_statistics { } raw; }; -/** - * dpni_get_statistics() - Get DPNI statistics - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @page: Selects the statistics page to retrieve, see DPNI_GET_STATISTICS - * output. Pages are numbered 0 to 2. - * @stat: Structure containing the statistics - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t page, - union dpni_statistics *stat); - +int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 page, u16 param, union dpni_statistics *stat); #endif /* _FSL_DPNI_H */ -- cgit v1.3.1 From 4797269e74a7720fe5a5100b00e85841358907a4 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:34 +0300 Subject: net: fsl-mc: sync DPSPARSER MC APIs Sync the Data Path Soft Parser APIs to their latest form, this means the layout of each command is created based on structures which clearly describe the endianness of each field rather than some macros. The command version is kept in place, meaning that the minimum MC version accepted is not changed in any way. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpsparser.c | 124 +++++++++++++++++++++++++++--------- include/fsl-mc/fsl_dpsparser.h | 139 +++++++++-------------------------------- 2 files changed, 126 insertions(+), 137 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpsparser.c b/drivers/net/fsl-mc/dpsparser.c index cfd1ba66a05..09dfb8f1fc0 100644 --- a/drivers/net/fsl-mc/dpsparser.c +++ b/drivers/net/fsl-mc/dpsparser.c @@ -2,15 +2,29 @@ /* * Data Path Soft Parser * - * Copyright 2018 NXP + * Copyright 2018, 2023 NXP */ #include #include #include -int dpsparser_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *token) +/** + * dpsparser_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpsparser_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token) { struct mc_command cmd = { 0 }; int err; @@ -26,14 +40,23 @@ int dpsparser_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return err; } -int dpsparser_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) +/** + * dpsparser_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -45,9 +68,27 @@ int dpsparser_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpsparser_create(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +/** + * dpsparser_create() - Create the DPSPARSER object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Returned token; use in subsequent API calls + * + * Create the DPSPARSER object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpsparser_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 *obj_id) { struct mc_command cmd = { 0 }; @@ -64,36 +105,51 @@ int dpsparser_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpsparser_destroy(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +/** + * dpsparser_destroy() - Destroy the DPSPARSER object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * + * Return: '0' on Success; error code otherwise. + */ +int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 obj_id) { + struct dpsparser_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_DESTROY, cmd_flags, token); - - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpsparser_cmd_destroy *)cmd.params; + cmd_params->dpsparser_id = cpu_to_le32(obj_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpsparser_apply_spb(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u64 blob_addr, - u16 *error) +/** + * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified address. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * @blob_addr: Blob loading address + * @error: Error reported by MC related to SP Blob parsing and apply + * + * Return: '0' on Success; error code otherwise. + */ +int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u64 blob_addr, u16 *error) { + struct dpsparser_rsp_blob_report_error *rsp_params; + struct dpsparser_cmd_blob_set_address *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -101,7 +157,8 @@ int dpsparser_apply_spb(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_APPLY_SPB, cmd_flags, token); - DPSPARSER_CMD_BLOB_SET_ADDR(cmd, blob_addr); + cmd_params = (struct dpsparser_cmd_blob_set_address *)cmd.params; + cmd_params->blob_addr = cpu_to_le64(blob_addr); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -109,15 +166,24 @@ int dpsparser_apply_spb(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters: MC error code */ - DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, *error); + rsp_params = (struct dpsparser_rsp_blob_report_error *)cmd.params; + *error = le16_to_cpu(rsp_params->error); return 0; } -int dpsparser_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPSPARSER major version + * @minor_ver: DPSPARSER minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; diff --git a/include/fsl-mc/fsl_dpsparser.h b/include/fsl-mc/fsl_dpsparser.h index 48fb495059e..9619bb1413f 100644 --- a/include/fsl-mc/fsl_dpsparser.h +++ b/include/fsl-mc/fsl_dpsparser.h @@ -2,7 +2,7 @@ /* * Data Path Soft Parser API * - * Copyright 2018 NXP + * Copyright 2018, 2023 NXP */ #ifndef _FSL_DPSPARSER_H #define _FSL_DPSPARSER_H @@ -20,13 +20,26 @@ #define DPSPARSER_CMDID_APPLY_SPB 0x1181 -/* cmd, param, offset, width, type, arg_name */ -#define DPSPARSER_CMD_BLOB_SET_ADDR(cmd, addr) \ - MC_CMD_OP(cmd, 0, 0, 64, u64, addr) +#pragma pack(push, 1) -/* cmd, param, offset, width, type, arg_name */ -#define DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, err) \ - MC_RSP_OP(cmd, 0, 0, 16, u16, err) +struct dpsparser_cmd_destroy { + __le32 dpsparser_id; +}; + +struct dpsparser_cmd_blob_set_address { + __le64 blob_addr; +}; + +struct dpsparser_rsp_blob_report_error { + __le16 error; +}; + +struct dpsparser_rsp_get_api_version { + __le16 major; + __le16 minor; +}; + +#pragma pack(pop) /* Data Path Soft Parser API * Contains initialization APIs and runtime control APIs for DPSPARSER @@ -99,110 +112,20 @@ struct fsl_mc_io; NULL, \ } -/** - * dpsparser_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpsparser_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *token); - -/** - * dpsparser_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/** - * dpsparser_create() - Create the DPSPARSER object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Returned token; use in subsequent API calls - * - * Create the DPSPARSER object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpsparser_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_create(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token); + +int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); + +int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 *obj_id); -/** - * dpsparser_destroy() - Destroy the DPSPARSER object and release all its - * resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * - * Return: '0' on Success; error code otherwise. - */ -int dpsparser_destroy(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 obj_id); -/** - * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified - * address. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * @blob_addr: Blob loading address - * @error: Error reported by MC related to SP Blob parsing and apply - * - * Return: '0' on Success; error code otherwise. - */ -int dpsparser_apply_spb(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u64 blob_addr, - u16 *error); - -/** - * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPSPARSER major version - * @minor_ver: DPSPARSER minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u64 blob_addr, u16 *error); + +int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPSPARSER_H */ -- cgit v1.3.1 From 0aebee70bb0edc42a2e9d764b7993a8a048a2ea7 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:35 +0300 Subject: net: fsl-mc: sync DPIO MC APIs Sync the Data Path IO APIs to their latest form, this means the layout of each command is created based on structures which clearly describe the endianness of each field rather than some macros. The command version is kept in place, meaning that the minimum MC version accepted is not changed in any way. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpio/dpio.c | 179 ++++++++++++++++++++++------- include/fsl-mc/fsl_dpio.h | 251 ++++++++++++++--------------------------- 2 files changed, 220 insertions(+), 210 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c index 30ecc9124b2..d17210bf451 100644 --- a/drivers/net/fsl-mc/dpio/dpio.c +++ b/drivers/net/fsl-mc/dpio/dpio.c @@ -1,18 +1,34 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include #include #include -int dpio_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint32_t dpio_id, - uint16_t *token) +/** + * dpio_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpio_id: DPIO unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpio_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and any MC portals + * assigned to the parent container; this token must be used in + * all subsequent commands for this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id, + u16 *token) { + struct dpio_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -20,7 +36,8 @@ int dpio_open(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN, cmd_flags, 0); - DPIO_CMD_OPEN(cmd, dpio_id); + cmd_params = (struct dpio_cmd_open *)cmd.params; + cmd_params->dpio_id = cpu_to_le32(dpio_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -28,14 +45,20 @@ int dpio_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return 0; } -int dpio_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpio_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -48,12 +71,32 @@ int dpio_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpio_cfg *cfg, - uint32_t *obj_id) +/** + * dpio_create() - Create the DPIO object. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id + * + * Create the DPIO object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * The function accepts an authentication token of a parent + * container that this object should be assigned to. The token + * can be '0' so the object will be assigned to the default container. + * The newly created object can be opened with the returned + * object id and using the container's associated tokens and MC portals. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpio_cfg *cfg, u32 *obj_id) { + struct dpio_cmd_create *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -61,7 +104,11 @@ int dpio_create(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE, cmd_flags, dprc_token); - DPIO_CMD_CREATE(cmd, cfg); + cmd_params = (struct dpio_cmd_create *)cmd.params; + cmd_params->num_priorities = cfg->num_priorities; + dpio_set_field(cmd_params->channel_mode, + CHANNEL_MODE, + cfg->channel_mode); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -69,33 +116,54 @@ int dpio_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpio_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpio_destroy() - Destroy the DPIO object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) { + struct dpio_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY, - cmd_flags, - dprc_token); + cmd_flags, + dprc_token); /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpio_cmd_destroy *)cmd.params; + cmd_params->dpio_id = cpu_to_le32(object_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpio_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpio_enable() - Enable the DPIO, allow I/O portal operations. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -108,9 +176,15 @@ int dpio_enable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpio_disable() - Disable the DPIO, stop any I/O portal operation. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -123,11 +197,19 @@ int dpio_disable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpio_get_attributes() - Retrieve DPIO attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpio_attr *attr) { + struct dpio_rsp_get_attr *rsp_params; struct mc_command cmd = { 0 }; int err; @@ -142,29 +224,42 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPIO_RSP_GET_ATTR(cmd, attr); + rsp_params = (struct dpio_rsp_get_attr *)cmd.params; + attr->id = le32_to_cpu(rsp_params->id); + attr->qbman_portal_id = le16_to_cpu(rsp_params->qbman_portal_id); + attr->num_priorities = rsp_params->num_priorities; + attr->qbman_portal_ce_offset = le64_to_cpu(rsp_params->qbman_portal_ce_offset); + attr->qbman_portal_ci_offset = le64_to_cpu(rsp_params->qbman_portal_ci_offset); + attr->qbman_version = le32_to_cpu(rsp_params->qbman_version); + attr->clk = le32_to_cpu(rsp_params->clk); + attr->channel_mode = dpio_get_field(rsp_params->channel_mode, ATTR_CHANNEL_MODE); return 0; } -int dpio_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpio_get_api_version() - Get Data Path I/O API version + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of data path i/o API + * @minor_ver: Minor version of data path i/o API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; - /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION, - cmd_flags, 0); + cmd_flags, + 0); - /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; - /* retrieve response parameters */ mc_cmd_read_api_version(&cmd, major_ver, minor_ver); return 0; diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 9d52a8e42f8..375590fd975 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPIO_H @@ -22,29 +22,52 @@ #define DPIO_CMDID_DISABLE 0x0031 #define DPIO_CMDID_GET_ATTR 0x0041 -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_CMD_OPEN(cmd, dpio_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ - cfg->channel_mode);\ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_RSP_GET_ATTR(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ - MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ - MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ - MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ -} while (0) +/* Macros for accessing command fields smaller than 1byte */ +#define DPIO_MASK(field) \ + GENMASK(DPIO_##field##_SHIFT + DPIO_##field##_SIZE - 1, \ + DPIO_##field##_SHIFT) +#define dpio_set_field(var, field, val) \ + ((var) |= (((val) << DPIO_##field##_SHIFT) & DPIO_MASK(field))) +#define dpio_get_field(var, field) \ + (((var) & DPIO_MASK(field)) >> DPIO_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpio_cmd_open { + __le32 dpio_id; +}; + +#define DPIO_CHANNEL_MODE_SHIFT 0 +#define DPIO_CHANNEL_MODE_SIZE 2 + +struct dpio_cmd_create { + __le16 pad1; + /* from LSB: channel_mode:2 */ + u8 channel_mode; + u8 pad2; + u8 num_priorities; +}; + +struct dpio_cmd_destroy { + __le32 dpio_id; +}; + +#define DPIO_ATTR_CHANNEL_MODE_SHIFT 0 +#define DPIO_ATTR_CHANNEL_MODE_SIZE 4 + +struct dpio_rsp_get_attr { + __le32 id; + __le16 qbman_portal_id; + u8 num_priorities; + /* from LSB: channel_mode:4 */ + u8 channel_mode; + __le64 qbman_portal_ce_offset; + __le64 qbman_portal_ci_offset; + __le32 qbman_version; + __le32 pad; + __le32 clk; +}; + +#pragma pack(pop) /* Data Path I/O Portal API * Contains initialization APIs and runtime control APIs for DPIO @@ -52,44 +75,15 @@ do { \ struct fsl_mc_io; -/** - * dpio_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpio_id: DPIO unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpio_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint32_t dpio_id, - uint16_t *token); +int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id, + u16 *token); -/** - * dpio_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * enum dpio_channel_mode - DPIO notification channel mode - * @DPIO_NO_CHANNEL: No support for notification channel - * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a + * @DPIO_NO_CHANNEL: No support for notification channel + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a * dedicated channel in the DPIO; user should point the queue's * destination in the relevant interface to this DPIO */ @@ -100,131 +94,52 @@ enum dpio_channel_mode { /** * struct dpio_cfg - Structure representing DPIO configuration - * @channel_mode: Notification channel mode - * @num_priorities: Number of priorities for the notification channel (1-8); + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' */ struct dpio_cfg { - enum dpio_channel_mode channel_mode; - uint8_t num_priorities; + enum dpio_channel_mode channel_mode; + u8 num_priorities; }; -/** - * dpio_create() - Create the DPIO object. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPIO object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpio_open() function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpio_cfg *cfg, - uint32_t *obj_id); +int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpio_cfg *cfg, u32 *obj_id); -/** - * dpio_destroy() - Destroy the DPIO object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: Object ID of DPIO - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); -/** - * dpio_enable() - Enable the DPIO, allow I/O portal operations. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpio_disable() - Disable the DPIO, stop any I/O portal operation. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpio_attr - Structure representing DPIO attributes - * @id: DPIO object ID - * @version: DPIO version - * @qbman_portal_ce_offset: offset of the software portal cache-enabled area - * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area - * @qbman_portal_id: Software portal ID - * @channel_mode: Notification channel mode - * @num_priorities: Number of priorities for the notification channel (1-8); - * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' - * @qbman_version: QBMAN version + * @id: DPIO object ID + * @qbman_portal_ce_offset: Offset of the software portal cache-enabled area + * @qbman_portal_ci_offset: Offset of the software portal + * cache-inhibited area + * @qbman_portal_id: Software portal ID + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification + * channel (1-8); relevant only if + * 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version */ struct dpio_attr { - uint32_t id; - uint64_t qbman_portal_ce_offset; - uint64_t qbman_portal_ci_offset; - uint16_t qbman_portal_id; + int id; + u64 qbman_portal_ce_offset; + u64 qbman_portal_ci_offset; + u16 qbman_portal_id; enum dpio_channel_mode channel_mode; - uint8_t num_priorities; - uint32_t qbman_version; + u8 num_priorities; + u32 qbman_version; + u32 clk; }; -/** - * dpio_get_attributes() - Retrieve DPIO attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpio_attr *attr); - -/** - * dpio_get_api_version - Retrieve DPIO Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPIO major version - * @minor_ver: DPIO minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpio_attr *attr); +int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPIO_H */ -- cgit v1.3.1 From 5654ffa8f13a20f587bf15c31c4a52efab887ca3 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 31 May 2023 19:04:36 +0300 Subject: net: fsl-mc: sync remaining MC commands This patch targets the last remaining commands left to sync to their latest form - mainly the mc_get_version() API. Besides this, remove any macro which is now of no help. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- drivers/net/fsl-mc/dpmng.c | 20 ++++++++++++++++---- drivers/net/fsl-mc/fsl_dpmng_cmd.h | 17 +++++++++-------- drivers/net/fsl-mc/mc_sys.c | 13 +++++++++---- include/fsl-mc/fsl_dpmng.h | 13 +------------ include/fsl-mc/fsl_mc_cmd.h | 23 ----------------------- 5 files changed, 35 insertions(+), 51 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c index 8314243f356..147ca6da9e1 100644 --- a/drivers/net/fsl-mc/dpmng.c +++ b/drivers/net/fsl-mc/dpmng.c @@ -1,15 +1,24 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright 2013-2015 Freescale Semiconductor Inc. + * Copyright 2023 NXP */ #include #include #include #include "fsl_dpmng_cmd.h" -int mc_get_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - struct mc_version *mc_ver_info) +/** + * mc_get_version() - Retrieves the Management Complex firmware + * version information + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @mc_ver_info: Returned version information structure + * + * Return: '0' on Success; Error code otherwise. + */ +int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info) { + struct dpmng_rsp_get_version *rsp_params; struct mc_command cmd = { 0 }; int err; @@ -24,7 +33,10 @@ int mc_get_version(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPMNG_RSP_GET_VERSION(cmd, mc_ver_info); + rsp_params = (struct dpmng_rsp_get_version *)cmd.params; + mc_ver_info->revision = le32_to_cpu(rsp_params->revision); + mc_ver_info->major = le32_to_cpu(rsp_params->version_major); + mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor); return 0; } diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h index e18c88da097..e6efceab7ac 100644 --- a/drivers/net/fsl-mc/fsl_dpmng_cmd.h +++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef __FSL_DPMNG_CMD_H #define __FSL_DPMNG_CMD_H @@ -8,12 +8,13 @@ /* Command IDs */ #define DPMNG_CMDID_GET_VERSION 0x8311 -/* cmd, param, offset, width, type, arg_name */ -#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \ - MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \ -} while (0) +#pragma pack(push, 1) +struct dpmng_rsp_get_version { + __le32 revision; + __le32 version_major; + __le32 version_minor; +}; + +#pragma pack(pop) #endif /* __FSL_DPMNG_CMD_H */ diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c index b5ae2ea3eb5..4d32516b005 100644 --- a/drivers/net/fsl-mc/mc_sys.c +++ b/drivers/net/fsl-mc/mc_sys.c @@ -13,8 +13,13 @@ #include #include -#define MC_CMD_HDR_READ_CMDID(_hdr) \ - ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S)) +static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 cmd_id = le16_to_cpu(hdr->cmd_id); + + return cmd_id; +} /** * mc_send_command - Send MC command and wait for response @@ -52,8 +57,8 @@ int mc_send_command(struct fsl_mc_io *mc_io, if (status != MC_CMD_STATUS_OK) { printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n", mc_io->mmio_regs, - (unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header), - (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header), + (unsigned int)mc_cmd_hdr_read_token(cmd), + (unsigned int)mc_cmd_hdr_read_cmdid(cmd), (unsigned int)status); return -EIO; diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index 2148601e8a1..5dfc9ecc428 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -30,17 +30,6 @@ struct mc_version { uint32_t revision; }; -/** - * mc_get_version() - Retrieves the Management Complex firmware - * version information - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @mc_ver_info: Returned version information structure - * - * Return: '0' on Success; Error code otherwise. - */ -int mc_get_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - struct mc_version *mc_ver_info); +int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info); #endif /* __FSL_DPMNG_H */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 6fe5fa4edda..c239595ed57 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -83,29 +83,6 @@ enum mc_cmd_status { ((enum mc_cmd_status)mc_dec((_hdr), \ MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) -#define MC_CMD_HDR_READ_TOKEN(_hdr) \ - ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) - -#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ - ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) - -#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ - (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) - -#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ - ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) - -#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ - (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width))) - -/* cmd, param, offset, width, type, arg_name */ -#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \ - MC_RSP_OP(cmd, 0, 0, 32, uint32_t, obj_id) - -/* cmd, param, offset, width, type, arg_name */ -#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id) - static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, uint32_t cmd_flags, uint16_t token) -- cgit v1.3.1 From 163c5f60ebb492eb3bab75e299cb43e6d022653d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 8 Jun 2023 17:16:38 +0200 Subject: fdt_support: add fdt_copy_fixed_partitions function Add a new function fdt_copy_fixed_partitions to copy the fixed partition nodes from U-Boot device tree to Linux kernel device tree and to dynamically configure the MTD partitions. This function fdt_copy_fixed_partitions is only based on device tree with livetree compatible function and replace the function fdt_fixup_mtdparts based on mtdparts variable. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- common/fdt_support.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/fdt_support.h | 8 ++++++ 2 files changed, 81 insertions(+) (limited to 'include') diff --git a/common/fdt_support.c b/common/fdt_support.c index ffc59fd8b36..5e49078f8c3 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1051,6 +1051,79 @@ void fdt_fixup_mtdparts(void *blob, const struct node_info *node_info, } #endif +int fdt_copy_fixed_partitions(void *blob) +{ + ofnode node, subnode; + int off, suboff, res; + char path[256]; + int address_cells, size_cells; + u8 i, j, child_count; + + node = ofnode_by_compatible(ofnode_null(), "fixed-partitions"); + while (ofnode_valid(node)) { + /* copy the U-Boot fixed partition */ + address_cells = ofnode_read_simple_addr_cells(node); + size_cells = ofnode_read_simple_size_cells(node); + + res = ofnode_get_path(ofnode_get_parent(node), path, sizeof(path)); + if (res) + return res; + + off = fdt_path_offset(blob, path); + if (off < 0) + return -ENODEV; + + off = fdt_find_or_add_subnode(blob, off, "partitions"); + res = fdt_setprop_string(blob, off, "compatible", "fixed-partitions"); + if (res) + return res; + + res = fdt_setprop_u32(blob, off, "#address-cells", address_cells); + if (res) + return res; + + res = fdt_setprop_u32(blob, off, "#size-cells", size_cells); + if (res) + return res; + + /* + * parse partition in reverse order as fdt_find_or_add_subnode() only + * insert the new node after the parent's properties + */ + child_count = ofnode_get_child_count(node); + for (i = child_count; i > 0 ; i--) { + subnode = ofnode_first_subnode(node); + if (!ofnode_valid(subnode)) + break; + + for (j = 0; (j < i - 1); j++) + subnode = ofnode_next_subnode(subnode); + + if (!ofnode_valid(subnode)) + break; + + const u32 *reg; + int len; + + suboff = fdt_find_or_add_subnode(blob, off, ofnode_get_name(subnode)); + res = fdt_setprop_string(blob, suboff, "label", + ofnode_read_string(subnode, "label")); + if (res) + return res; + + reg = ofnode_get_property(subnode, "reg", &len); + res = fdt_setprop(blob, suboff, "reg", reg, len); + if (res) + return res; + } + + /* go to next fixed-partitions node */ + node = ofnode_by_compatible(node, "fixed-partitions"); + } + + return 0; +} + void fdt_del_node_and_alias(void *blob, const char *alias) { int off = fdt_path_offset(blob, alias); diff --git a/include/fdt_support.h b/include/fdt_support.h index eeb83e6251d..2cd83668982 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -256,6 +256,14 @@ static inline void fdt_fixup_mtdparts(void *fdt, } #endif +/** + * copy the fixed-partition nodes from U-Boot device tree to external blob + * + * @param blob FDT blob to update + * Return: 0 if ok, or non-zero on error + */ +int fdt_copy_fixed_partitions(void *blob); + void fdt_del_node_and_alias(void *blob, const char *alias); /** -- cgit v1.3.1 From d3126a32938c2881bb04391480dcb4b8f2529b7b Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 30 May 2023 14:26:21 +0200 Subject: config: stm32mp15: remove CONFIG_FASTBOOT_CMD_OEM_FORMAT Remove the support of the fastboot "oem format" command for STM32MP15x boards and removed the associated env variable "partitions". This command is not required; with fastboot tool, the GPT partition can be handle with "flash" command in "gpt" target (=CONFIG_FASTBOOT_GPT_NAME), for example: fastboot flash gpt gpt.bin This patch avoids to define the GPT partitioning in U-Boot environment, which is incompatible with planned modifications, for example to support TF-A firmware update. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15_basic_defconfig | 1 - configs/stm32mp15_defconfig | 1 - configs/stm32mp15_trusted_defconfig | 1 - include/configs/stm32mp15_common.h | 14 -------------- include/configs/stm32mp15_st_common.h | 1 - 5 files changed, 18 deletions(-) (limited to 'include') diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index bc83bdd0984..424ae5dbdfa 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -108,7 +108,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 10453a1ab43..12b9b549732 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -81,7 +81,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5657a67669e..5b94e0c6d2e 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -82,7 +82,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 7db72a19ed9..29a1197b5ae 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -92,19 +92,6 @@ "run distro_bootcmd;" \ "fi;\0" -#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT -/* eMMC default partitions for fastboot command: oem format */ -#define STM32MP_PARTS_DEFAULT \ - "partitions=" \ - "name=ssbl,size=2M;" \ - "name=bootfs,size=64MB,bootable;" \ - "name=vendorfs,size=16M;" \ - "name=rootfs,size=746M;" \ - "name=userfs,size=-\0" -#else -#define STM32MP_PARTS_DEFAULT -#endif - #define STM32MP_EXTRA \ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" @@ -138,7 +125,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 866cd7a719f..b45982a35b8 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -47,7 +47,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ ST_STM32MP1_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV -- cgit v1.3.1 From 763c6b8d7aeb6cee88dedf4be9b9ddaea47a7adb Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 24 Apr 2023 16:21:09 +0200 Subject: media: dt-bindings: media: Add macros for video interface bus types Add a new dt-bindings/media/video-interfaces.h header that defines macros corresponding to the bus types from media/video-interfaces.yaml. This allows avoiding hardcoded constants in device tree sources. Based on linux commit f7eeb0084593 ("media: dt-bindings: media: Add macros for video interface bus types") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/dt-bindings/media/video-interfaces.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/media/video-interfaces.h (limited to 'include') diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h new file mode 100644 index 00000000000..68ac4e05e37 --- /dev/null +++ b/include/dt-bindings/media/video-interfaces.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2022 Laurent Pinchart + */ + +#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ +#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ + +#define MEDIA_BUS_TYPE_CSI2_CPHY 1 +#define MEDIA_BUS_TYPE_CSI1 2 +#define MEDIA_BUS_TYPE_CCP2 3 +#define MEDIA_BUS_TYPE_CSI2_DPHY 4 +#define MEDIA_BUS_TYPE_PARALLEL 5 +#define MEDIA_BUS_TYPE_BT656 6 + +#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ -- cgit v1.3.1 From 08002ffd083d0caf8eea9c038a308dd45e2fb59c Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 24 Apr 2023 16:21:10 +0200 Subject: ARM: dts: stm32mp: alignment with v6.3 Device tree alignment with Linux kernel v6.3: - f5a058023239 - ARM: dts: stm32: add i2c nodes into stm32mp131.dtsi - 8539ebb435a5 - ARM: dts: stm32: enable i2c1 and i2c5 on stm32mp135f-dk.dts - 8539ebb435a5 - ARM: dts: stm32: add spi nodes into stm32mp131.dtsi - 15f72e0da4da - ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dk - ea99a5a02ebc - ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi - a306d8962a24 - ARM: dts: stm32: Rename mdio0 to mdio - 0a5ebb1f3367 - ARM: dts: stm32: Replace SAI format with dai-format DT property - ccdab19738a6 - ARM: dts: stm32: add adc support to stm32mp13 - 022932ab55fd - ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk - ab2806ddad9d - ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk - e46a180c060f - ARM: dts: stm32: add adc support on stm32mp135f-dk - 9ebf215fbae1 - ARM: dts: stm32: add PWR fixed regulators on stm32mp131 - 16f4ff60519a - ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131 - 4a47f0f3e936 - ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131 - 2a46bb66c47f - ARM: dts: stm32: add USB OTG HS support on stm32mp131 - 9ebf215fbae1 - ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk - 16f4ff60519a - ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk - c4e7254cf6dc - ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk - 44978e135916 - ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13 - 4f532403b1e5 - ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk - e1f15571c96c - ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13 - 6cc71374002e - ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk - 7ffd2266bd32 - ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcor-som - 21d83512bf2b - ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcom-som - 732dbcf52f74 - ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp151a-prtt1l - 003b7c6b24f4 - ARM: dts: stm32: remove sai kernel clock on stm32mp15xx-dkx - f2b17b39bfff - ARM: dts: stm32: rename sound card on stm32mp15xx-dkx - dee3cb759d3d - ARM: dts: stm32: Remove the pins-are-numbered property - ae8cf3b48727 - ARM: dts: stm32: add i2s nodes on stm32mp131 - 619746a27bd0 - ARM: dts: stm32: add sai nodes on stm32mp131 - c5e05d08ef90 - ARM: dts: stm32: add spdifrx node on stm32mp131 - 0a5afd3ee0d0 - ARM: dts: stm32: add dfsdm node on stm32mp131 - bf9d876bea2e - ARM: dts: stm32: add timers support on stm32mp131 - a3183748371d - ARM: dts: stm32: add timer pins muxing for stm32mp135f-dk - a9060c1326bc - ARM: dts: stm32: add timers support on stm32mp135f-dk - a12154058f75 - ARM: dts: stm32: Fix User button on stm32mp135f-dk - 2f33df889e99 - ARM: dts: stm32: Use new media bus type macros - 366384e49551 - ARM: dts: stm32: Update part number NVMEM description on stm32mp131 Signed-off-by: Patrick Delaunay Reviewed-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-pinctrl.dtsi | 138 ++++ arch/arm/dts/stm32mp131.dtsi | 993 ++++++++++++++++++++++++++- arch/arm/dts/stm32mp133.dtsi | 31 + arch/arm/dts/stm32mp135f-dk.dts | 235 ++++++- arch/arm/dts/stm32mp15-pinctrl.dtsi | 50 +- arch/arm/dts/stm32mp151.dtsi | 2 - arch/arm/dts/stm32mp157c-ev1.dts | 18 +- arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 8 +- arch/arm/dts/stm32mp15xx-dhcor-som.dtsi | 8 +- arch/arm/dts/stm32mp15xx-dkx.dtsi | 10 +- include/dt-bindings/clock/stm32mp13-clks.h | 2 +- include/dt-bindings/reset/stm32mp13-resets.h | 2 +- 12 files changed, 1459 insertions(+), 38 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index d2472cd8f1d..b2dce3a29f3 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,114 @@ #include &pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC1 in12 */ + }; + }; + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + + mcp23017_pins_a: mcp23017-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + pwm3_pins_a: pwm3-0 { + pins { + pinmux = ; /* TIM3_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = ; /* TIM3_CH4 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = ; /* TIM8_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = ; /* TIM8_CH3 */ + }; + }; + + pwm14_pins_a: pwm14-0 { + pins { + pinmux = ; /* TIM14_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm14_sleep_pins_a: pwm14-sleep-0 { + pins { + pinmux = ; /* TIM14_CH1 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -108,6 +216,36 @@ }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = , /* SPI5_SCK */ + ; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = , /* SPI5_SCK */ + , /* SPI5_MISO */ + ; /* SPI5_MOSI */ + }; + }; + + stm32g0_intn_pins_a: stm32g0-intn-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 6d82bf646d2..d94ba254726 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -77,6 +77,28 @@ always-on; }; + /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ + reg11: reg11 { + compatible = "regulator-fixed"; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + compatible = "regulator-fixed"; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -97,6 +119,284 @@ }; }; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000b000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi2: spi@4000b000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000c000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x4000d000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; @@ -106,6 +406,241 @@ status = "disabled"; }; + i2c1: i2c@40012000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + i2c-analog-filter; + status = "disabled"; + }; + + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + reg = <0x44004000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@44004000 { + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + ranges = <0 0x4400a000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + ranges = <0 0x4400b000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + reg = <0>; + #io-channel-cells = <1>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + reg = <1>; + #io-channel-cells = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + dma1: dma-controller@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; @@ -153,6 +688,314 @@ dma-channels = <16>; }; + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -181,6 +1024,111 @@ clocks = <&rcc SYSCFG>; }; + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -261,13 +1209,31 @@ clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; status = "disabled"; }; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; @@ -276,6 +1242,29 @@ status = "disabled"; }; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -294,6 +1283,7 @@ part_number_otp: part_number_otp@4 { reg = <0x4 0x2>; + bits = <0 12>; }; ts_cal1: calib@5c { reg = <0x5c 0x2>; @@ -314,7 +1304,6 @@ ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi index 531c263c9f4..df451c3c2a2 100644 --- a/arch/arm/dts/stm32mp133.dtsi +++ b/arch/arm/dts/stm32mp133.dtsi @@ -33,5 +33,36 @@ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = ; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; }; }; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index 52f86596ce1..c40686cb2b9 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -40,7 +40,7 @@ gpio-keys { compatible = "gpio-keys"; - user-pa13 { + button-user { label = "User-PA13"; linux,code = ; gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; @@ -59,6 +59,22 @@ }; }; + v3v3_sw: v3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_adc: vdd-adc { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -66,6 +82,101 @@ regulator-max-microvolt = <2900000>; regulator-always-on; }; + + vdd_usb: vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_usb_cc_pins_a>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <1000000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + mcp23017: pinctrl@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23017_pins_a>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,irq-mirror; + }; + + typec@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; + /* Alert pin on PI2 */ + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + /* Internal pull-up on PI2 */ + pinctrl-names = "default"; + pinctrl-0 = <&stm32g0_intn_pins_a>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + con_usb_c_g0_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <170>; + i2c-scl-falling-time-ns = <5>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; }; &iwdg2 { @@ -90,8 +201,130 @@ status = "okay"; }; +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers14 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm14_pins_a>; + pinctrl-1 = <&pwm14_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@13 { + status = "okay"; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3_sw>; + }; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usb_c_g0_ep>; + }; + }; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 2cc9341d43d..a9d2bec9901 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1261,7 +1261,7 @@ }; qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { + pins { pinmux = , /* QSPI_BK1_IO0 */ , /* QSPI_BK1_IO1 */ , /* QSPI_BK1_IO2 */ @@ -1270,12 +1270,6 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { - pinmux = ; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; }; qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { @@ -1283,13 +1277,12 @@ pinmux = , /* QSPI_BK1_IO0 */ , /* QSPI_BK1_IO1 */ , /* QSPI_BK1_IO2 */ - , /* QSPI_BK1_IO3 */ - ; /* QSPI_BK1_NCS */ + ; /* QSPI_BK1_IO3 */ }; }; qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { + pins { pinmux = , /* QSPI_BK2_IO0 */ , /* QSPI_BK2_IO1 */ , /* QSPI_BK2_IO2 */ @@ -1298,7 +1291,34 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { + }; + + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = , /* QSPI_BK2_IO0 */ + , /* QSPI_BK2_IO1 */ + , /* QSPI_BK2_IO2 */ + ; /* QSPI_BK2_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + }; + }; + + qspi_cs2_pins_a: qspi-cs2-0 { + pins { pinmux = ; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; @@ -1306,13 +1326,9 @@ }; }; - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { pins { - pinmux = , /* QSPI_BK2_IO0 */ - , /* QSPI_BK2_IO1 */ - , /* QSPI_BK2_IO2 */ - , /* QSPI_BK2_IO3 */ - ; /* QSPI_BK2_NCS */ + pinmux = ; /* QSPI_BK2_NCS */ }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 5d178b5d3c8..b3baacbb269 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1693,7 +1693,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; @@ -1822,7 +1821,6 @@ #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; - pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 2d5db41ed67..542226cfcfd 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -8,6 +8,7 @@ #include "stm32mp157c-ed1.dts" #include #include +#include / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -90,7 +91,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; - bus-type = <5>; + bus-type = ; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; @@ -144,7 +145,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -255,8 +256,16 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a + &qspi_bk2_pins_a + &qspi_cs2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a + &qspi_bk2_sleep_pins_a + &qspi_cs2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; @@ -393,6 +402,7 @@ st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; + connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index 83e2c87713f..de761743b24 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -429,8 +429,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 98033b51479..f36eec1b4ac 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -191,8 +191,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 34af90195d1..49b3e768c89 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -72,7 +72,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-DK"; + label = "STM32MP15-DK"; routing = "Playback" , "MCLK", "Capture" , "MCLK", @@ -149,7 +149,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -509,14 +509,12 @@ sai2a: audio-controller@4400b004 { #clock-cells = <0>; dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; status = "okay"; sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&cs42l51_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; @@ -534,7 +532,7 @@ sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&cs42l51_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h index 799dee5b802..da4cb756743 100644 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved * Author: Gabriel Fernandez for STMicroelectronics. */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h index 18ccb05db6c..1b83a01de8f 100644 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Gabriel Fernandez for STMicroelectronics. */ -- cgit v1.3.1 From 6d9f86571d10309f00dc9a7f3d8b9882cfd23ce4 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 22 Apr 2023 16:01:40 +0200 Subject: configs: stm32f746-disco: remove a useless comment Commit 8fc78fc73b7f9d ("configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs") made the comment useless. Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/configs/stm32f746-disco.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 34856d30040..9bf01cac47a 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -36,6 +36,4 @@ #define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) -/* For splashcreen */ - #endif /* __CONFIG_H */ -- cgit v1.3.1 From 2974e2cd287003a21d73b04ea6d11ede423db464 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Mon, 12 Jun 2023 09:09:15 +0100 Subject: fwu_metadata: make sure structures are packed The fwu metadata in the metadata partitions should/are packed to guarantee that the info is correct in all platforms. Also the size of them are used to calculate the crc32 and that is important to get it right. Signed-off-by: Rui Miguel Silva Reviewed-by: Ilias Apalodimas --- include/fwu_mdata.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h index 8fda4f4ac22..56189e2f40a 100644 --- a/include/fwu_mdata.h +++ b/include/fwu_mdata.h @@ -6,6 +6,7 @@ #if !defined _FWU_MDATA_H_ #define _FWU_MDATA_H_ +#include #include /** @@ -22,7 +23,7 @@ struct fwu_image_bank_info { efi_guid_t image_uuid; uint32_t accepted; uint32_t reserved; -}; +} __packed; /** * struct fwu_image_entry - information for a particular type of image @@ -38,7 +39,7 @@ struct fwu_image_entry { efi_guid_t image_type_uuid; efi_guid_t location_uuid; struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS]; -}; +} __packed; /** * struct fwu_mdata - FWU metadata structure for multi-bank updates @@ -62,6 +63,6 @@ struct fwu_mdata { uint32_t previous_active_index; struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK]; -}; +} __packed; #endif /* _FWU_MDATA_H_ */ -- cgit v1.3.1 From dc3abd8006c5fe715449302f9aaf79db190454fc Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Mon, 12 Jun 2023 09:09:16 +0100 Subject: nvmxip: move header to include Move header to include to allow external code to get the internal bdev structures to access block device operations. as at it, just add the UCLASS_NVMXIP string so we get the correct output in partitions listing. Signed-off-by: Rui Miguel Silva --- drivers/mtd/nvmxip/nvmxip.h | 32 -------------------------------- include/nvmxip.h | 32 ++++++++++++++++++++++++++++++++ test/dm/nvmxip.c | 2 +- 3 files changed, 33 insertions(+), 33 deletions(-) delete mode 100644 drivers/mtd/nvmxip/nvmxip.h create mode 100644 include/nvmxip.h (limited to 'include') diff --git a/drivers/mtd/nvmxip/nvmxip.h b/drivers/mtd/nvmxip/nvmxip.h deleted file mode 100644 index f4ef37725d2..00000000000 --- a/drivers/mtd/nvmxip/nvmxip.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2023 Arm Limited and/or its affiliates - * - * Authors: - * Abdellatif El Khlifi - */ - -#ifndef __DRIVER_NVMXIP_H__ -#define __DRIVER_NVMXIP_H__ - -#include - -#define NVMXIP_BLKDRV_NAME "nvmxip-blk" -#define NVMXIP_BLKDEV_NAME_SZ 20 - -/** - * struct nvmxip_plat - the NVMXIP driver plat - * - * @phys_base: NVM XIP device base address - * @lba_shift: block size shift count - * @lba: number of blocks - * - * The NVMXIP information read from the DT. - */ -struct nvmxip_plat { - phys_addr_t phys_base; - u32 lba_shift; - lbaint_t lba; -}; - -#endif /* __DRIVER_NVMXIP_H__ */ diff --git a/include/nvmxip.h b/include/nvmxip.h new file mode 100644 index 00000000000..f4ef37725d2 --- /dev/null +++ b/include/nvmxip.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 Arm Limited and/or its affiliates + * + * Authors: + * Abdellatif El Khlifi + */ + +#ifndef __DRIVER_NVMXIP_H__ +#define __DRIVER_NVMXIP_H__ + +#include + +#define NVMXIP_BLKDRV_NAME "nvmxip-blk" +#define NVMXIP_BLKDEV_NAME_SZ 20 + +/** + * struct nvmxip_plat - the NVMXIP driver plat + * + * @phys_base: NVM XIP device base address + * @lba_shift: block size shift count + * @lba: number of blocks + * + * The NVMXIP information read from the DT. + */ +struct nvmxip_plat { + phys_addr_t phys_base; + u32 lba_shift; + lbaint_t lba; +}; + +#endif /* __DRIVER_NVMXIP_H__ */ diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c index e934748eb5d..89bf481f616 100644 --- a/test/dm/nvmxip.c +++ b/test/dm/nvmxip.c @@ -17,7 +17,7 @@ #include #include #include -#include "../../drivers/mtd/nvmxip/nvmxip.h" +#include /* NVMXIP devices described in the device tree */ #define SANDBOX_NVMXIP_DEVICES 2 -- cgit v1.3.1 From bb922ca3eb4b92a27e98fb5d81bf22242e9d4f0e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Jun 2023 13:58:59 +0200 Subject: global: Use proper project name U-Boot (next) Use proper project name in DTs, messages and READMEs. Signed-off-by: Michal Simek --- arch/arm/dts/am335x-igep0033.dtsi | 2 +- arch/arm/dts/armada-3720-db.dts | 2 +- board/armadeus/opos6uldev/opos6uldev.env | 8 ++++---- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/ls1012afrdm/README | 4 ++-- board/freescale/ls1012aqds/README | 4 ++-- board/freescale/ls1012ardb/README | 8 ++++---- board/imgtec/boston/checkboard.c | 2 +- include/dt-bindings/memory/bcm-ns3-mc.h | 2 +- 9 files changed, 17 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi index ad57c74fafc..4488dcce012 100644 --- a/arch/arm/dts/am335x-igep0033.dtsi +++ b/arch/arm/dts/am335x-igep0033.dtsi @@ -175,7 +175,7 @@ }; partition@1 { - label = "U-boot"; + label = "U-Boot"; reg = <0x00080000 0x001e0000>; }; diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 3e5789f3720..1ee92406b74 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -180,7 +180,7 @@ reg = <0x0 0x200000>; }; partition@200000 { - label = "U-boot Env"; + label = "U-Boot Env"; reg = <0x200000 0x10000>; }; partition@210000 { diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env index 585f28ca858..f9002978710 100644 --- a/board/armadeus/opos6uldev/opos6uldev.env +++ b/board/armadeus/opos6uldev/opos6uldev.env @@ -42,8 +42,8 @@ flash_uboot_spl= setexpr sz ${filesize} / 0x200; setexpr sz ${sz} + 1; if mmc write ${loadaddr} 0x2 ${sz}; then - echo Flashing of U-boot SPL succeed; - else echo Flashing of U-boot SPL failed; + echo Flashing of U-Boot SPL succeed; + else echo Flashing of U-Boot SPL failed; fi; fi; download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img @@ -52,8 +52,8 @@ flash_uboot_img= setexpr sz ${filesize} / 0x200; setexpr sz ${sz} + 1; if mmc write ${loadaddr} 0x8a ${sz}; then - echo Flashing of U-boot image succeed; - else echo Flashing of U-boot image failed; + echo Flashing of U-Boot image succeed; + else echo Flashing of U-Boot image failed; fi; fi; update_uboot=run download_uboot_spl flash_uboot_spl diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index b47ce052516..87ed814d6a2 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -127,7 +127,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) &img_addr); if (res == 0) - printf("SPL: Validation of U-boot successful\n"); + printf("SPL: Validation of U-Boot successful\n"); } #ifdef CONFIG_SPL_FRAMEWORK diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README index 382b668fbec..e60ed606ec1 100644 --- a/board/freescale/ls1012afrdm/README +++ b/board/freescale/ls1012afrdm/README @@ -52,7 +52,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README index c1956f9fd78..e9b80cad506 100644 --- a/board/freescale/ls1012aqds/README +++ b/board/freescale/ls1012aqds/README @@ -53,7 +53,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README index 5b6f306a1d9..26b0485a7f8 100644 --- a/board/freescale/ls1012ardb/README +++ b/board/freescale/ls1012ardb/README @@ -48,8 +48,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 @@ -90,8 +90,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4030_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4030_0000 PPA FIT image | 2MB | 0x4040_0000 PFE firmware | 20K | 0x00a0_0000 Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c index 1b8a47d2549..c246a7b9d45 100644 --- a/board/imgtec/boston/checkboard.c +++ b/board/imgtec/boston/checkboard.c @@ -16,7 +16,7 @@ int checkboard(void) { u32 changelist; - lowlevel_display("U-boot "); + lowlevel_display("U-Boot "); printf("Board: MIPS Boston\n"); diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index 84795ec27a4..d2478d9ae31 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -28,7 +28,7 @@ #define BCM_NS3_MEM_SHARE_START 0x8d000000 #define BCM_NS3_MEM_SHARE_LEN 0x020fffff -/* ATF/U-boot/Linux error logs */ +/* ATF/U-Boot/Linux error logs */ #define BCM_NS3_MEM_ELOG_START 0x8f113000 #define BCM_NS3_MEM_ELOG_LEN 0x00100000 -- cgit v1.3.1 From 8ce6a2e1757718bb9e4e97f1fd7da94ba298fe73 Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Sat, 3 Jun 2023 19:32:54 +0530 Subject: spl: blk: Support loading images from fs Add a generic API to support loading of SPL payload from any supported filesystem on a given partition of a block device. Signed-off-by: Mayuresh Chitale --- common/spl/Kconfig | 1 + common/spl/Makefile | 1 + common/spl/spl_blk_fs.c | 134 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/block/Kconfig | 7 +++ include/spl.h | 3 ++ 5 files changed, 146 insertions(+) create mode 100644 common/spl/spl_blk_fs.c (limited to 'include') diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ae0d50744e6..865571d4579 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1268,6 +1268,7 @@ config SPL_NVME depends on BLK select HAVE_BLOCK_DEVICE select FS_LOADER + select SPL_BLK_FS help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). diff --git a/common/spl/Makefile b/common/spl/Makefile index 13db3df9933..5210ad0248c 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o +obj-$(CONFIG_$(SPL_TPL_)BLK_FS) += spl_blk_fs.o obj-$(CONFIG_$(SPL_TPL_)LEGACY_IMAGE_FORMAT) += spl_legacy.o obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c new file mode 100644 index 00000000000..d97adc4d39a --- /dev/null +++ b/common/spl/spl_blk_fs.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 + * Ventana Micro Systems Inc. + * + */ + +#include +#include +#include +#include + +struct blk_dev { + const char *ifname; + char dev_part_str[8]; +}; + +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, + ulong size, void *buf) +{ + loff_t actlen; + int ret; + struct blk_dev *dev = (struct blk_dev *)load->priv; + + ret = fs_set_blk_dev(dev->ifname, dev->dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev->ifname, dev->dev_part_str, ret); + return ret; + } + + ret = fs_read(load->filename, (ulong)buf, file_offset, size, &actlen); + if (ret < 0) { + printf("spl: error reading image %s. Err - %d\n", + load->filename, ret); + return ret; + } + + return actlen; +} + +int spl_blk_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + enum uclass_id uclass_id, int devnum, int partnum) +{ + const char *filename = CONFIG_SPL_PAYLOAD; + struct disk_partition part_info = {}; + struct legacy_img_hdr *header; + struct blk_desc *blk_desc; + loff_t actlen, filesize; + struct blk_dev dev; + int ret; + + blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum); + if (!blk_desc) { + printf("blk desc for %d %d not found\n", uclass_id, devnum); + goto out; + } + + blk_show_device(uclass_id, devnum); + header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + ret = part_get_info(blk_desc, 1, &part_info); + if (ret) { + printf("spl: no partition table found. Err - %d\n", ret); + goto out; + } + + dev.ifname = blk_get_uclass_name(uclass_id); + snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%d:%d", + devnum, partnum); + ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev.ifname, dev.dev_part_str, ret); + goto out; + } + + ret = fs_read(filename, (ulong)header, 0, + sizeof(struct legacy_img_hdr), &actlen); + if (ret) { + printf("spl: unable to read file %s. Err - %d\n", filename, + ret); + goto out; + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.read = spl_fit_read; + load.bl_len = 1; + load.filename = (void *)filename; + load.priv = &dev; + + return spl_load_simple_fit(spl_image, &load, 0, header); + } + + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) { + printf("spl: unable to parse image header. Err - %d\n", + ret); + goto out; + } + + ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev.ifname, dev.dev_part_str, ret); + goto out; + } + + ret = fs_size(filename, &filesize); + if (ret) { + printf("spl: unable to get file size: %s. Err - %d\n", + filename, ret); + goto out; + } + + ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev.ifname, dev.dev_part_str, ret); + goto out; + } + + ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize, + &actlen); + if (ret) + printf("spl: unable to read file %s. Err - %d\n", + filename, ret); +out: + return ret; +} diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 5a1aeb3d2b4..6baaa6f0711 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -107,6 +107,13 @@ config EFI_MEDIA For sandbox there is a test driver. +config SPL_BLK_FS + bool "Load images from filesystems on block devices" + depends on SPL_BLK + help + Use generic support to load images from fat/ext filesystems on + different types of block devices such as NVMe. + if EFI_MEDIA config EFI_MEDIA_SANDBOX diff --git a/include/spl.h b/include/spl.h index 7e0f5ac63b0..20e1eb32a44 100644 --- a/include/spl.h +++ b/include/spl.h @@ -672,6 +672,9 @@ int spl_load_image_ext(struct spl_image_info *spl_image, int spl_load_image_ext_os(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct blk_desc *block_dev, int partition); +int spl_blk_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + enum uclass_id uclass_id, int devnum, int partnum); /** * spl_early_init() - Set up device tree and driver model in SPL if enabled -- cgit v1.3.1 From fb93bd8d264c3198f321dc23a83559fcfcc275d4 Mon Sep 17 00:00:00 2001 From: Julien Panis Date: Mon, 29 May 2023 15:42:28 +0200 Subject: drivers: spi: omap3_spi: Initialize mode for all channels At first SPI transfers, multiple chip selects can be enabled simultaneously. This is due to chip select polarity, which is not properly initialized for all channels. This patch fixes the issue. Signed-off-by: Julien Panis --- drivers/spi/omap3_spi.c | 20 ++++++++++++++------ include/omap3_spi.h | 4 +++- 2 files changed, 17 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 1cbb5d46fd6..ff7b55f8707 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -347,20 +347,28 @@ static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) omap3_spi_write_chconf(priv, confr); } -static void spi_reset(struct mcspi *regs) +static void spi_reset(struct omap3_spi_priv *priv) { unsigned int tmp; - writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); + writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &priv->regs->sysconfig); do { - tmp = readl(®s->sysstatus); + tmp = readl(&priv->regs->sysstatus); } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE)); writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE | OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP | - OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); + OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &priv->regs->sysconfig); - writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); + writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &priv->regs->wakeupenable); + + /* + * Set the same default mode for each channel, especially CS polarity + * which must be common for all SPI slaves before any transfer. + */ + for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++) + _omap3_spi_set_mode(priv); + priv->cs = 0; } static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) @@ -430,7 +438,7 @@ static int omap3_spi_probe(struct udevice *dev) priv->pin_dir = plat->pin_dir; priv->wordlen = SPI_DEFAULT_WORDLEN; - spi_reset(priv->regs); + spi_reset(priv); return 0; } diff --git a/include/omap3_spi.h b/include/omap3_spi.h index cae37705830..5381431d438 100644 --- a/include/omap3_spi.h +++ b/include/omap3_spi.h @@ -46,6 +46,8 @@ #define OMAP4_MCSPI_REG_OFFSET 0x100 +#define OMAP4_MCSPI_CHAN_NB 4 + /* OMAP3 McSPI registers */ struct mcspi_channel { unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ @@ -64,7 +66,7 @@ struct mcspi { unsigned int wakeupenable; /* 0x20 */ unsigned int syst; /* 0x24 */ unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; + struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ /* channel1: 0x40 - 0x50, bus 0 & 1 */ /* channel2: 0x54 - 0x64, bus 0 & 1 */ -- cgit v1.3.1 From bf52766ddcd7c8ac572af615cc2d2a74e9e5ffe7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 31 May 2023 03:03:58 +0200 Subject: test: bdinfo: Add test for command bdinfo Add test for command bdinfo . Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- include/test/suites.h | 1 + test/cmd/Makefile | 1 + test/cmd/bdinfo.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++ test/cmd_ut.c | 6 ++ 4 files changed, 196 insertions(+) create mode 100644 test/cmd/bdinfo.c (limited to 'include') diff --git a/include/test/suites.h b/include/test/suites.h index 7349ce5aa60..1c7dc65966a 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -28,6 +28,7 @@ int cmd_ut_category(const char *name, const char *prefix, int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 055adc65a25..a3cf983739e 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_PAUSE) += test_pause.o endif obj-y += exit.o mem.o obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o +obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-$(CONFIG_CMD_FDT) += fdt.o obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o obj-$(CONFIG_CMD_LOADM) += loadm.o diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c new file mode 100644 index 00000000000..9068df79c4f --- /dev/null +++ b/test/cmd/bdinfo.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for bdinfo command + * + * Copyright 2023 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Declare a new bdinfo test */ +#define BDINFO_TEST(_name, _flags) UNIT_TEST(_name, _flags, bdinfo_test) + +static void bdinfo_test_num_l(struct unit_test_state *uts, + const char *name, ulong value) +{ + ut_assert_nextline("%-12s= 0x%0*lx", name, 2 * (int)sizeof(value), value); +} + +static void bdinfo_test_num_ll(struct unit_test_state *uts, + const char *name, unsigned long long value) +{ + ut_assert_nextline("%-12s= 0x%.*llx", name, 2 * (int)sizeof(ulong), value); +} + +static void test_eth(struct unit_test_state *uts) +{ + const int idx = eth_get_dev_index(); + uchar enetaddr[6]; + char name[10]; + int ret; + + if (idx) + sprintf(name, "eth%iaddr", idx); + else + strcpy(name, "ethaddr"); + + ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr); + + ut_assert_nextline("current eth = %s", eth_get_name()); + if (!ret) + ut_assert_nextline("%-12s= (not set)", name); + else + ut_assert_nextline("%-12s= %pM", name, enetaddr); + ut_assert_nextline("IP addr = %s", env_get("ipaddr")); +} + +static void test_video_info(struct unit_test_state *uts) +{ + const struct udevice *dev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) { + ut_assert_nextline("%-12s= %s %sactive", "Video", dev->name, + device_active(dev) ? "" : "in"); + if (device_active(dev)) { + struct video_priv *upriv = dev_get_uclass_priv(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + bdinfo_test_num_ll(uts, "FB base", (ulong)upriv->fb); + if (upriv->copy_fb) { + bdinfo_test_num_ll(uts, "FB copy", + (ulong)upriv->copy_fb); + bdinfo_test_num_l(uts, " copy size", + plat->copy_size); + } + ut_assert_nextline("%-12s= %dx%dx%d", "FB size", + upriv->xsize, upriv->ysize, + 1 << upriv->bpix); + } + } +} + +static void lmb_test_dump_region(struct unit_test_state *uts, + struct lmb_region *rgn, char *name) +{ + unsigned long long base, size, end; + enum lmb_flags flags; + int i; + + ut_assert_nextline(" %s.cnt = 0x%lx / max = 0x%lx", name, rgn->cnt, rgn->max); + + for (i = 0; i < rgn->cnt; i++) { + base = rgn->region[i].base; + size = rgn->region[i].size; + end = base + size - 1; + flags = rgn->region[i].flags; + + ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x", + name, i, base, end, size, flags); + } +} + +static void lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb) +{ + ut_assert_nextline("lmb_dump_all:"); + lmb_test_dump_region(uts, &lmb->memory, "memory"); + lmb_test_dump_region(uts, &lmb->reserved, "reserved"); +} + +static int bdinfo_test_move(struct unit_test_state *uts) +{ + struct bd_info *bd = gd->bd; + int i; + + /* Test moving the working BDINFO to a new location */ + ut_assertok(console_record_reset_enable()); + ut_assertok(run_commandf("bdinfo")); + + bdinfo_test_num_l(uts, "boot_params", 0); + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + bdinfo_test_num_l(uts, "DRAM bank", i); + bdinfo_test_num_ll(uts, "-> start", bd->bi_dram[i].start); + bdinfo_test_num_ll(uts, "-> size", bd->bi_dram[i].size); + } + } + + /* CONFIG_SYS_HAS_SRAM testing not supported */ + bdinfo_test_num_l(uts, "flashstart", 0); + bdinfo_test_num_l(uts, "flashsize", 0); + bdinfo_test_num_l(uts, "flashoffset", 0); + ut_assert_nextline("baudrate = %lu bps", + env_get_ulong("baudrate", 10, 1234)); + bdinfo_test_num_l(uts, "relocaddr", gd->relocaddr); + bdinfo_test_num_l(uts, "reloc off", gd->reloc_off); + ut_assert_nextline("%-12s= %u-bit", "Build", (uint)sizeof(void *) * 8); + + if (IS_ENABLED(CONFIG_CMD_NET)) + test_eth(uts); + + /* + * Make sure environment variable "fdtcontroladdr" address + * matches mapped control DT address. + */ + ut_assert(map_to_sysmem(gd->fdt_blob) == env_get_hex("fdtcontroladdr", 0x1234)); + bdinfo_test_num_l(uts, "fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob)); + bdinfo_test_num_l(uts, "new_fdt", (ulong)map_to_sysmem(gd->new_fdt)); + bdinfo_test_num_l(uts, "fdt_size", (ulong)gd->fdt_size); + + if (IS_ENABLED(CONFIG_VIDEO)) + test_video_info(uts); + + /* The gd->multi_dtb_fit may not be available, hence, #if below. */ +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) + bdinfo_test_num_l(uts, "multi_dtb_fit", (ulong)gd->multi_dtb_fit); +#endif + + if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) { + struct lmb lmb; + + lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + lmb_test_dump_all(uts, &lmb); + if (IS_ENABLED(CONFIG_OF_REAL)) + ut_assert_nextline("devicetree = %s", fdtdec_get_srcname()); + } + + ut_assertok(ut_check_console_end(uts)); + + return 0; +} + +BDINFO_TEST(bdinfo_test_move, UT_TESTF_CONSOLE_REC); + +int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(bdinfo_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(bdinfo_test); + + return cmd_ut_category("bdinfo", "bdinfo_test_", tests, n_ents, argc, argv); +} diff --git a/test/cmd_ut.c b/test/cmd_ut.c index d440da833a9..0cb514490b9 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -54,6 +54,9 @@ int cmd_ut_category(const char *name, const char *prefix, static struct cmd_tbl cmd_ut_sub[] = { U_BOOT_CMD_MKENT(all, CONFIG_SYS_MAXARGS, 1, do_ut_all, "", ""), U_BOOT_CMD_MKENT(info, 1, 1, do_ut_info, "", ""), +#ifdef CONFIG_CMD_BDI + U_BOOT_CMD_MKENT(bdinfo, CONFIG_SYS_MAXARGS, 1, do_ut_bdinfo, "", ""), +#endif #ifdef CONFIG_BOOTSTD U_BOOT_CMD_MKENT(bootstd, CONFIG_SYS_MAXARGS, 1, do_ut_bootstd, "", ""), @@ -176,6 +179,9 @@ static char ut_help_text[] = #ifdef CONFIG_CMD_ADDRMAP "\naddrmap - very basic test of addrmap command" #endif +#ifdef CONFIG_CMD_BDI + "\nbdinfo - bdinfo command" +#endif #ifdef CONFIG_SANDBOX "\nbloblist - bloblist implementation" #endif -- cgit v1.3.1 From e0afedb64085d02c7a3b156f77f6c71d0836e583 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 6 Jun 2023 20:37:42 +0900 Subject: stdio: Remove stdio_init() This function is not used by anyone. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- common/stdio.c | 8 -------- include/stdio_dev.h | 7 ------- 2 files changed, 15 deletions(-) (limited to 'include') diff --git a/common/stdio.c b/common/stdio.c index cbedfdda539..894cbd3fb44 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -386,11 +386,3 @@ int stdio_add_devices(void) return 0; } - -int stdio_init(void) -{ - stdio_init_tables(); - stdio_add_devices(); - - return 0; -} diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 3105928970d..77bf8a8970f 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -84,13 +84,6 @@ int stdio_init_tables(void); */ int stdio_add_devices(void); -/** - * stdio_init() - Sets up stdio ready for use - * - * This calls stdio_init_tables() and stdio_add_devices() - */ -int stdio_init(void); - void stdio_print_current_devices(void); /** -- cgit v1.3.1 From 8d72c796b41efc414635f444b8179f9e17e8c76f Mon Sep 17 00:00:00 2001 From: Igor Prusov Date: Fri, 5 May 2023 15:56:35 +0300 Subject: ARM: dts: Add Amlogic Meson A1 DT from Linux 6.3-rc7 Import Linux 6.3-rc7 Device tree and necessary bindings for Amlogic A1 board from 6a8f57ae2eb0 ("Linux 6.3-rc7"). Signed-off-by: Igor Prusov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230505125639.3605-2-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong --- arch/arm/dts/meson-a1.dtsi | 161 +++++++++++++++++++++++++++++++ include/dt-bindings/gpio/meson-a1-gpio.h | 73 ++++++++++++++ 2 files changed, 234 insertions(+) create mode 100644 arch/arm/dts/meson-a1.dtsi create mode 100644 include/dt-bindings/gpio/meson-a1-gpio.h (limited to 'include') diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi new file mode 100644 index 00000000000..6509329b85b --- /dev/null +++ b/arch/arm/dts/meson-a1.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + compatible = "amlogic,a1"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,meson-a1-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + reset: reset-controller@0 { + compatible = "amlogic,meson-a1-reset"; + reg = <0x0 0x0 0x0 0x8c>; + #reset-cells = <1>; + }; + + periphs_pinctrl: pinctrl@400 { + compatible = "amlogic,meson-a1-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@400 { + reg = <0x0 0x0400 0x0 0x003c>, + <0x0 0x0480 0x0 0x0118>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 62>; + }; + + }; + + uart_AO: serial@1c00 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x1c00 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@2000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x2000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff901000 { + compatible = "arm,gic-400"; + reg = <0x0 0xff901000 0x0 0x1000>, + <0x0 0xff902000 0x0 0x2000>, + <0x0 0xff904000 0x0 0x2000>, + <0x0 0xff906000 0x0 0x2000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; +}; diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h new file mode 100644 index 00000000000..40e57a5ff1d --- /dev/null +++ b/include/dt-bindings/gpio/meson-a1-gpio.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song + */ + +#ifndef _DT_BINDINGS_MESON_A1_GPIO_H +#define _DT_BINDINGS_MESON_A1_GPIO_H + +#define GPIOP_0 0 +#define GPIOP_1 1 +#define GPIOP_2 2 +#define GPIOP_3 3 +#define GPIOP_4 4 +#define GPIOP_5 5 +#define GPIOP_6 6 +#define GPIOP_7 7 +#define GPIOP_8 8 +#define GPIOP_9 9 +#define GPIOP_10 10 +#define GPIOP_11 11 +#define GPIOP_12 12 +#define GPIOB_0 13 +#define GPIOB_1 14 +#define GPIOB_2 15 +#define GPIOB_3 16 +#define GPIOB_4 17 +#define GPIOB_5 18 +#define GPIOB_6 19 +#define GPIOX_0 20 +#define GPIOX_1 21 +#define GPIOX_2 22 +#define GPIOX_3 23 +#define GPIOX_4 24 +#define GPIOX_5 25 +#define GPIOX_6 26 +#define GPIOX_7 27 +#define GPIOX_8 28 +#define GPIOX_9 29 +#define GPIOX_10 30 +#define GPIOX_11 31 +#define GPIOX_12 32 +#define GPIOX_13 33 +#define GPIOX_14 34 +#define GPIOX_15 35 +#define GPIOX_16 36 +#define GPIOF_0 37 +#define GPIOF_1 38 +#define GPIOF_2 39 +#define GPIOF_3 40 +#define GPIOF_4 41 +#define GPIOF_5 42 +#define GPIOF_6 43 +#define GPIOF_7 44 +#define GPIOF_8 45 +#define GPIOF_9 46 +#define GPIOF_10 47 +#define GPIOF_11 48 +#define GPIOF_12 49 +#define GPIOA_0 50 +#define GPIOA_1 51 +#define GPIOA_2 52 +#define GPIOA_3 53 +#define GPIOA_4 54 +#define GPIOA_5 55 +#define GPIOA_6 56 +#define GPIOA_7 57 +#define GPIOA_8 58 +#define GPIOA_9 59 +#define GPIOA_10 60 +#define GPIOA_11 61 + +#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ -- cgit v1.3.1 From 0e3f7e9c982ef2624dde81f67f4b5307b5c8eb09 Mon Sep 17 00:00:00 2001 From: Igor Prusov Date: Fri, 5 May 2023 15:56:37 +0300 Subject: ARM: meson: add A1 support Add support for Amlogic A1 SoC family. Signed-off-by: Igor Prusov Signed-off-by: Evgeny Bachinin Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230505125639.3605-4-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong --- arch/arm/include/asm/arch-meson/a1.h | 20 ++++++++++++ arch/arm/mach-meson/Kconfig | 6 ++++ arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/board-a1.c | 59 ++++++++++++++++++++++++++++++++++++ include/configs/meson64.h | 3 ++ 5 files changed, 89 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/a1.h create mode 100644 arch/arm/mach-meson/board-a1.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-meson/a1.h b/arch/arm/include/asm/arch-meson/a1.h new file mode 100644 index 00000000000..86d1a68de8c --- /dev/null +++ b/arch/arm/include/asm/arch-meson/a1.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 SberDevices, Inc. + * Author: Igor Prusov + */ + +#ifndef __MESON_A1_H__ +#define __MESON_A1_H__ + +#define A1_SYSCTRL_BASE 0xfe005800 + +/* SYSCTRL registers */ +#define A1_SYSCTRL_ADDR(off) (A1_SYSCTRL_BASE + ((off) << 2)) + +#define A1_SYSCTRL_SEC_STATUS_REG4 A1_SYSCTRL_ADDR(0xc4) + +#define A1_SYSCTRL_MEM_SIZE_MASK 0xFFFF0000 +#define A1_SYSCTRL_MEM_SIZE_SHIFT 16 + +#endif /* __MESON_A1_H__ */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 6cba2c40dda..519ed563c05 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -51,6 +51,12 @@ config MESON_G12A help Select this if your SoC is an S905X/D2 +config MESON_A1 + bool "A1" + select MESON64_COMMON + help + Select this if your SoC is an A113L + endchoice config SYS_SOC diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index a9e4046f809..535b0878b91 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -6,3 +6,4 @@ obj-y += board-common.o sm.o board-info.o obj-$(CONFIG_MESON_GX) += board-gx.o obj-$(CONFIG_MESON_AXG) += board-axg.o obj-$(CONFIG_MESON_G12A) += board-g12a.o +obj-$(CONFIG_MESON_A1) += board-a1.o diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c new file mode 100644 index 00000000000..967bb671822 --- /dev/null +++ b/arch/arm/mach-meson/board-a1.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 SberDevices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +phys_size_t get_effective_memsize(void) +{ + return ((readl(A1_SYSCTRL_SEC_STATUS_REG4) & A1_SYSCTRL_MEM_SIZE_MASK) + >> A1_SYSCTRL_MEM_SIZE_SHIFT) * SZ_1M; +} + +void meson_init_reserved_memory(__maybe_unused void *fdt) +{ +} + +int meson_get_boot_device(void) +{ + return -ENOSYS; +} + +static struct mm_region a1_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7FE00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * This mem region contains in/out shared memory with bl31, + * hence it's marked as NORMAL memory type + */ + .virt = 0xFFE00000UL, + .phys = 0xFFE00000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = a1_mem_map; diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 9244601284b..801cdae4708 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -11,6 +11,9 @@ #if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) #define GICD_BASE 0xffc01000 #define GICC_BASE 0xffc02000 +#elif defined(CONFIG_MESON_A1) +#define GICD_BASE 0xff901000 +#define GICC_BASE 0xff902000 #else /* MESON GXL and GXBB */ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 -- cgit v1.3.1 From 959426e026bef448ae2f1e3843f1e757f556d156 Mon Sep 17 00:00:00 2001 From: Alexey Romanov Date: Wed, 31 May 2023 12:31:55 +0300 Subject: dt-bindings: power: add Meson A1 PWRC bindings We can use them in secure pwrc driver. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230531093156.29240-3-avromanov@sberdevices.ru Signed-off-by: Neil Armstrong --- include/dt-bindings/power/meson-a1-power.h | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/meson-a1-power.h (limited to 'include') diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h new file mode 100644 index 00000000000..8e39dfc0b62 --- /dev/null +++ b/include/dt-bindings/power/meson-a1-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2023 SberDevices, Inc. + * Author: Alexey Romanov + */ + +#ifndef _DT_BINDINGS_MESON_A1_POWER_H +#define _DT_BINDINGS_MESON_A1_POWER_H + +#define PWRC_DSPA_ID 8 +#define PWRC_DSPB_ID 9 +#define PWRC_UART_ID 10 +#define PWRC_DMC_ID 11 +#define PWRC_I2C_ID 12 +#define PWRC_PSRAM_ID 13 +#define PWRC_ACODEC_ID 14 +#define PWRC_AUDIO_ID 15 +#define PWRC_OTP_ID 16 +#define PWRC_DMA_ID 17 +#define PWRC_SD_EMMC_ID 18 +#define PWRC_RAMA_ID 19 +#define PWRC_RAMB_ID 20 +#define PWRC_IR_ID 21 +#define PWRC_SPICC_ID 22 +#define PWRC_SPIFC_ID 23 +#define PWRC_USB_ID 24 +#define PWRC_NIC_ID 25 +#define PWRC_PDMIN_ID 26 +#define PWRC_RSA_ID 27 +#define PWRC_MAX_ID 28 + +#endif -- cgit v1.3.1 From 4e99899bd546b7cd60735df4b18da6eabdc38cb1 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 15 Jun 2023 11:12:43 +0100 Subject: riscv: dts: sync mpfs-icicle devicetree with linux The "notable" disappearances are: - the pac193x stanza - there's nothing in mainline linux w.r.t. bindings for this & what is going to appear in mainline linux is going to be incompatible with what is currently in U-Boot. - operating points - these operating points should not be set at the soc.dtsi level as they may not be possible depending on the design programmed to the FPGA - clock output names - there are defines for the clock indices, these should not be needed - the dt maintainers in linux NAKed using defines for IRQ numbers - the qspi nand, which is not part of the icicle's default configuration is removed. Reviewed-by: Padmarao Begari Tested-by: Padmarao Begari Signed-off-by: Conor Dooley Reviewed-by: Rick Chen --- arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi | 71 ++++ arch/riscv/dts/mpfs-icicle-kit.dts | 184 ++++++--- arch/riscv/dts/mpfs.dtsi | 434 +++++++++------------ include/dt-bindings/clock/microchip-mpfs-clock.h | 29 +- .../interrupt-controller/microchip-mpfs-plic.h | 196 ---------- .../dt-bindings/interrupt-controller/riscv-hart.h | 17 - 6 files changed, 413 insertions(+), 518 deletions(-) create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi delete mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h (limited to 'include') diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi new file mode 100644 index 00000000000..1069134f2e1 --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; + + core_pwm0: pwm@40000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask = /bits/ 32 <0>; + #pwm-cells = <3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + status = "disabled"; + }; + + i2c2: i2c@40000200 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x40000200 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts index 3c56400b929..8aa5fb17d64 100644 --- a/arch/riscv/dts/mpfs-icicle-kit.dts +++ b/arch/riscv/dts/mpfs-icicle-kit.dts @@ -7,29 +7,63 @@ /dts-v1/; #include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" +#include +#include /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 / { model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-reference-rtlv2210", - "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; aliases { - serial1 = &uart1; ethernet0 = &mac1; - spi0 = &qspi; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; }; chosen { - stdout-path = "serial1"; + stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = ; }; + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + color = ; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = ; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = ; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = ; + label = "led4"; + }; + }; + ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; @@ -54,83 +88,121 @@ }; }; -&refclk { - clock-frequency = <125000000>; +&core_pwm0 { + status = "okay"; }; -&uart1 { +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; status = "okay"; }; -&mmc { +&i2c0 { status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + status = "enabled"; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@9 { + reg = <9>; + }; + + phy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { bus-width = <4>; disable-wp; - cap-mmc-highspeed; cap-sd-highspeed; - card-detect-delay = <200>; + cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; + status = "okay"; }; -&i2c1 { +&mmuart1 { status = "okay"; - clock-frequency = <100000>; +}; - pac193x: pac193x@10 { - compatible = "microchip,pac1934"; - reg = <0x10>; - samp-rate = <64>; - status = "okay"; - ch1: channel0 { - uohms-shunt-res = <10000>; - rail-name = "VDDREG"; - channel_enabled; - }; - ch2: channel1 { - uohms-shunt-res = <10000>; - rail-name = "VDDA25"; - channel_enabled; - }; - ch3: channel2 { - uohms-shunt-res = <10000>; - rail-name = "VDD25"; - channel_enabled; - }; - ch4: channel3 { - uohms-shunt-res = <10000>; - rail-name = "VDDA_REG"; - channel_enabled; - }; - }; +&mmuart2 { + status = "okay"; }; -&mac1 { +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&pcie { status = "okay"; - phy-mode = "sgmii"; - phy-handle = <&phy1>; - phy1: ethernet-phy@9 { - reg = <9>; - ti,fifo-depth = <0x1>; - }; }; &qspi { status = "okay"; - num-cs = <1>; +}; - flash0: flash@0 { - compatible = "spi-nand"; - reg = <0x0>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-max-frequency = <20000000>; - spi-cpol; - spi-cpha; - }; +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; }; diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi index 891dd0918b2..6012a285070 100644 --- a/arch/riscv/dts/mpfs.dtsi +++ b/arch/riscv/dts/mpfs.dtsi @@ -2,8 +2,6 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ #include "dt-bindings/clock/microchip-mpfs-clock.h" -#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h" -#include "dt-bindings/interrupt-controller/riscv-hart.h" / { #address-cells = <2>; @@ -11,9 +9,6 @@ model = "Microchip PolarFire SoC"; compatible = "microchip,mpfs"; - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -28,12 +23,7 @@ riscv,isa = "rv64imac"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu0_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -59,13 +49,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -91,13 +77,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -123,13 +105,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -155,273 +133,322 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; - refclk: refclk { + refclk: mssrefclk { compatible = "fixed-clock"; #clock-cells = <0>; }; + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + mboxes = <&mbox 0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; - compatible = "microchip,mpfs-soc", "simple-bus"; + compatible = "simple-bus"; ranges; - clint: clint@2000000 { - compatible = "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = - <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER - &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER - &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER - &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER - &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; - }; - - cachecontroller: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; + cctrllr: cache-controller@2010000 { + compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = ; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; cache-size = <2097152>; cache-unified; + interrupt-parent = <&plic>; + interrupts = <1>, <3>, <4>, <2>; }; - pdma: pdma@3000000 { - compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = ; - #dma-cells = <1>; + clint: clint@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 { - compatible = "sifive,plic-1.0.0"; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; + #address-cells = <0>; #interrupt-cells = <1>; - riscv,ndev = <186>; interrupt-controller; - interrupts-extended = <&cpu0_intc HART_INT_M_EXT - &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT - &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT - &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT - &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + riscv,ndev = <186>; + }; + + pdma: dma-controller@3000000 { + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <5 6>, <7 8>, <9 10>, <11 12>; + dma-channels = <4>; + #dma-cells = <1>; }; clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + #reset-cells = <1>; }; - /* Common node entry for eMMC/SD */ - mmc: mmc@20008000 { - compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - clocks = <&clkcfg CLK_MMC>; - interrupt-parent = <&plic>; - interrupts = ; - max-frequency = <200000000>; + ccc_se: clock-controller@38010000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells = <1>; status = "disabled"; }; - uart0: serial@20000000 { + ccc_nw: clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <90>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART0>; status = "disabled"; /* Reserved for the HSS */ }; - uart1: serial@20100000 { + mmuart1: serial@20100000 { compatible = "ns16550a"; reg = <0x0 0x20100000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <91>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART1>; status = "disabled"; }; - uart2: serial@20102000 { + mmuart2: serial@20102000 { compatible = "ns16550a"; reg = <0x0 0x20102000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <92>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART2>; status = "disabled"; }; - uart3: serial@20104000 { + mmuart3: serial@20104000 { compatible = "ns16550a"; reg = <0x0 0x20104000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <93>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART3>; status = "disabled"; }; - uart4: serial@20106000 { + mmuart4: serial@20106000 { compatible = "ns16550a"; reg = <0x0 0x20106000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <94>; clocks = <&clkcfg CLK_MMUART4>; + current-speed = <115200>; + status = "disabled"; + }; + + /* Common node entry for emmc/sd */ + mmc: mmc@20008000 { + compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + clocks = <&clkcfg CLK_MMC>; + max-frequency = <200000000>; status = "disabled"; }; spi0: spi@20108000 { compatible = "microchip,mpfs-spi"; - reg = <0x0 0x20108000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI0>; - interrupt-parent = <&plic>; - interrupts = ; - num-cs = <8>; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; status = "disabled"; }; spi1: spi@20109000 { compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0x0 0x20109000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI1>; interrupt-parent = <&plic>; - interrupts = ; - num-cs = <8>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; status = "disabled"; }; i2c0: i2c@2010a000 { - compatible = "microchip,mpfs-i2c"; + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; reg = <0x0 0x2010a000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C0>; - interrupt-parent = <&plic>; - interrupts = ; #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; status = "disabled"; }; i2c1: i2c@2010b000 { - compatible = "microchip,mpfs-i2c"; + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; reg = <0x0 0x2010b000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C1>; - interrupt-parent = <&plic>; - interrupts = ; #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; status = "disabled"; }; can0: can@2010c000 { - compatible = "microchip,mpfs-can-uio"; + compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; clocks = <&clkcfg CLK_CAN0>; interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <56>; status = "disabled"; }; can1: can@2010d000 { - compatible = "microchip,mpfs-can-uio"; + compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; clocks = <&clkcfg CLK_CAN1>; interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <57>; status = "disabled"; }; mac0: ethernet@20110000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC0>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; mac1: ethernet@20112000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC1>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; gpio0: gpio@20120000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20120000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO0>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -429,10 +456,11 @@ gpio1: gpio@20121000 { compatible = "microchip,mpfs-gpio"; - reg = <000 0x20121000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO1>; + reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -441,9 +469,10 @@ gpio2: gpio@20122000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20122000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO2>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -452,118 +481,31 @@ rtc: rtc@20124000 { compatible = "microchip,mpfs-rtc"; reg = <0x0 0x20124000 0x0 0x1000>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; status = "disabled"; }; usb: usb@20201000 { - compatible = "microchip,mpfs-usb-host"; + compatible = "microchip,mpfs-musb"; reg = <0x0 0x20201000 0x0 0x1000>; - reg-names = "mc","control"; - clocks = <&clkcfg CLK_USB>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; interrupt-names = "dma","mc"; - dr_mode = "host"; - status = "disabled"; - }; - - qspi: qspi@21000000 { - compatible = "microchip,mpfs-qspi"; - reg = <0x0 0x21000000 0x0 0x1000>; - clocks = <&clkcfg CLK_QSPI>; - interrupt-parent = <&plic>; - interrupts = ; - num-cs = <8>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; - interrupts = ; + interrupts = <96>; #mbox-cells = <1>; status = "disabled"; }; - - pcie: pcie@2000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; - clock-names = "fic0", "fic1", "fic3"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = ; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent = <&pcie>; - msi-controller; - mchp,axi-m-atr0 = <0x10 0x0>; - status = "disabled"; - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - #address-cells = <1>; - #size-cells = <1>; - mboxes = <&mbox 0>; - }; - - hwrandom: hwrandom { - compatible = "microchip,mpfs-rng"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - serialnum: serialnum { - compatible = "microchip,mpfs-serial-number"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - fpgadigest: fpgadigest { - compatible = "microchip,mpfs-digest"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - devicecert: cert { - compatible = "microchip,mpfs-device-cert"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - signature: signature { - compatible = "microchip,mpfs-signature"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; }; }; diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h index c7ed0a8db78..79775a5134c 100644 --- a/include/dt-bindings/clock/microchip-mpfs-clock.h +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -1,7 +1,7 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2020 Microchip Technology Inc. - * Padmarao Begari + * Daire McNamara, + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ @@ -45,4 +45,27 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h deleted file mode 100644 index eba1bac7dfb..00000000000 --- a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H - -#define PLIC_INT_INVALID 0 -#define PLIC_INT_L2_METADATA_CORR 1 -#define PLIC_INT_L2_METADATA_UNCORR 2 -#define PLIC_INT_L2_DATA_CORR 3 -#define PLIC_INT_L2_DATA_UNCORR 4 -#define PLIC_INT_DMA_CH0_DONE 5 -#define PLIC_INT_DMA_CH0_ERR 6 -#define PLIC_INT_DMA_CH1_DONE 7 -#define PLIC_INT_DMA_CH1_ERR 8 -#define PLIC_INT_DMA_CH2_DONE 9 -#define PLIC_INT_DMA_CH2_ERR 10 -#define PLIC_INT_DMA_CH3_DONE 11 -#define PLIC_INT_DMA_CH3_ERR 12 - -#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13 -#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14 -#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15 -#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16 -#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17 -#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18 -#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19 -#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20 -#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21 -#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22 -#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23 -#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24 -#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25 -#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26 -#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27 -#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28 -#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29 -#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30 -#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31 -#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32 -#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33 -#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34 -#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35 -#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36 -#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37 -#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38 -#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39 -#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40 -#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41 -#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42 -#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43 -#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44 -#define PLIC_INT_GPIO1_BIT18 45 -#define PLIC_INT_GPIO1_BIT19 46 -#define PLIC_INT_GPIO1_BIT20 47 -#define PLIC_INT_GPIO1_BIT21 48 -#define PLIC_INT_GPIO1_BIT22 49 -#define PLIC_INT_GPIO1_BIT23 50 -#define PLIC_INT_GPIO0_NON_DIRECT 51 -#define PLIC_INT_GPIO1_NON_DIRECT 52 -#define PLIC_INT_GPIO2_NON_DIRECT 53 -#define PLIC_INT_SPI0 54 -#define PLIC_INT_SPI1 55 -#define PLIC_INT_CAN0 56 -#define PLIC_INT_CAN1 57 -#define PLIC_INT_I2C0_MAIN 58 -#define PLIC_INT_I2C0_ALERT 59 -#define PLIC_INT_I2C0_SUS 60 -#define PLIC_INT_I2C1_MAIN 61 -#define PLIC_INT_I2C1_ALERT 62 -#define PLIC_INT_I2C1_SUS 63 -#define PLIC_INT_MAC0_INT 64 -#define PLIC_INT_MAC0_QUEUE1 65 -#define PLIC_INT_MAC0_QUEUE2 66 -#define PLIC_INT_MAC0_QUEUE3 67 -#define PLIC_INT_MAC0_EMAC 68 -#define PLIC_INT_MAC0_MMSL 69 -#define PLIC_INT_MAC1_INT 70 -#define PLIC_INT_MAC1_QUEUE1 71 -#define PLIC_INT_MAC1_QUEUE2 72 -#define PLIC_INT_MAC1_QUEUE3 73 -#define PLIC_INT_MAC1_EMAC 74 -#define PLIC_INT_MAC1_MMSL 75 -#define PLIC_INT_DDRC_TRAIN 76 -#define PLIC_INT_SCB_INTERRUPT 77 -#define PLIC_INT_ECC_ERROR 78 -#define PLIC_INT_ECC_CORRECT 79 -#define PLIC_INT_RTC_WAKEUP 80 -#define PLIC_INT_RTC_MATCH 81 -#define PLIC_INT_TIMER1 82 -#define PLIC_INT_TIMER2 83 -#define PLIC_INT_ENVM 84 -#define PLIC_INT_QSPI 85 -#define PLIC_INT_USB_DMA 86 -#define PLIC_INT_USB_MC 87 -#define PLIC_INT_MMC_MAIN 88 -#define PLIC_INT_MMC_WAKEUP 89 -#define PLIC_INT_MMUART0 90 -#define PLIC_INT_MMUART1 91 -#define PLIC_INT_MMUART2 92 -#define PLIC_INT_MMUART3 93 -#define PLIC_INT_MMUART4 94 -#define PLIC_INT_G5C_DEVRST 95 -#define PLIC_INT_G5C_MESSAGE 96 -#define PLIC_INT_USOC_VC_INTERRUPT 97 -#define PLIC_INT_USOC_SMB_INTERRUPT 98 -#define PLIC_INT_E51_0_MAINTENACE 99 -#define PLIC_INT_WDOG0_MRVP 100 -#define PLIC_INT_WDOG1_MRVP 101 -#define PLIC_INT_WDOG2_MRVP 102 -#define PLIC_INT_WDOG3_MRVP 103 -#define PLIC_INT_WDOG4_MRVP 104 -#define PLIC_INT_WDOG0_TOUT 105 -#define PLIC_INT_WDOG1_TOUT 106 -#define PLIC_INT_WDOG2_TOUT 107 -#define PLIC_INT_WDOG3_TOUT 108 -#define PLIC_INT_WDOG4_TOUT 109 -#define PLIC_INT_G5C_MSS_SPI 110 -#define PLIC_INT_VOLT_TEMP_ALARM 111 -#define PLIC_INT_ATHENA_COMPLETE 112 -#define PLIC_INT_ATHENA_ALARM 113 -#define PLIC_INT_ATHENA_BUS_ERROR 114 -#define PLIC_INT_USOC_AXIC_US 115 -#define PLIC_INT_USOC_AXIC_DS 116 -#define PLIC_INT_SPARE 117 -#define PLIC_INT_FABRIC_F2H_0 118 -#define PLIC_INT_FABRIC_F2H_1 119 -#define PLIC_INT_FABRIC_F2H_2 120 -#define PLIC_INT_FABRIC_F2H_3 121 -#define PLIC_INT_FABRIC_F2H_4 122 -#define PLIC_INT_FABRIC_F2H_5 123 -#define PLIC_INT_FABRIC_F2H_6 124 -#define PLIC_INT_FABRIC_F2H_7 125 -#define PLIC_INT_FABRIC_F2H_8 126 -#define PLIC_INT_FABRIC_F2H_9 127 -#define PLIC_INT_FABRIC_F2H_10 128 -#define PLIC_INT_FABRIC_F2H_11 129 -#define PLIC_INT_FABRIC_F2H_12 130 -#define PLIC_INT_FABRIC_F2H_13 131 -#define PLIC_INT_FABRIC_F2H_14 132 -#define PLIC_INT_FABRIC_F2H_15 133 -#define PLIC_INT_FABRIC_F2H_16 134 -#define PLIC_INT_FABRIC_F2H_17 135 -#define PLIC_INT_FABRIC_F2H_18 136 -#define PLIC_INT_FABRIC_F2H_19 137 -#define PLIC_INT_FABRIC_F2H_20 138 -#define PLIC_INT_FABRIC_F2H_21 139 -#define PLIC_INT_FABRIC_F2H_22 140 -#define PLIC_INT_FABRIC_F2H_23 141 -#define PLIC_INT_FABRIC_F2H_24 142 -#define PLIC_INT_FABRIC_F2H_25 143 -#define PLIC_INT_FABRIC_F2H_26 144 -#define PLIC_INT_FABRIC_F2H_27 145 -#define PLIC_INT_FABRIC_F2H_28 146 -#define PLIC_INT_FABRIC_F2H_29 147 -#define PLIC_INT_FABRIC_F2H_30 148 -#define PLIC_INT_FABRIC_F2H_31 149 -#define PLIC_INT_FABRIC_F2H_32 150 -#define PLIC_INT_FABRIC_F2H_33 151 -#define PLIC_INT_FABRIC_F2H_34 152 -#define PLIC_INT_FABRIC_F2H_35 153 -#define PLIC_INT_FABRIC_F2H_36 154 -#define PLIC_INT_FABRIC_F2H_37 155 -#define PLIC_INT_FABRIC_F2H_38 156 -#define PLIC_INT_FABRIC_F2H_39 157 -#define PLIC_INT_FABRIC_F2H_40 158 -#define PLIC_INT_FABRIC_F2H_41 159 -#define PLIC_INT_FABRIC_F2H_42 160 -#define PLIC_INT_FABRIC_F2H_43 161 -#define PLIC_INT_FABRIC_F2H_44 162 -#define PLIC_INT_FABRIC_F2H_45 163 -#define PLIC_INT_FABRIC_F2H_46 164 -#define PLIC_INT_FABRIC_F2H_47 165 -#define PLIC_INT_FABRIC_F2H_48 166 -#define PLIC_INT_FABRIC_F2H_49 167 -#define PLIC_INT_FABRIC_F2H_50 168 -#define PLIC_INT_FABRIC_F2H_51 169 -#define PLIC_INT_FABRIC_F2H_52 170 -#define PLIC_INT_FABRIC_F2H_53 171 -#define PLIC_INT_FABRIC_F2H_54 172 -#define PLIC_INT_FABRIC_F2H_55 173 -#define PLIC_INT_FABRIC_F2H_56 174 -#define PLIC_INT_FABRIC_F2H_57 175 -#define PLIC_INT_FABRIC_F2H_58 176 -#define PLIC_INT_FABRIC_F2H_59 177 -#define PLIC_INT_FABRIC_F2H_60 178 -#define PLIC_INT_FABRIC_F2H_61 179 -#define PLIC_INT_FABRIC_F2H_62 180 -#define PLIC_INT_FABRIC_F2H_63 181 -#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182 -#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183 -#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184 -#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185 -#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */ diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h deleted file mode 100644 index c4331b8521b..00000000000 --- a/include/dt-bindings/interrupt-controller/riscv-hart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H - -#define HART_INT_U_SOFT 0 -#define HART_INT_S_SOFT 1 -#define HART_INT_M_SOFT 3 -#define HART_INT_U_TIMER 4 -#define HART_INT_S_TIMER 5 -#define HART_INT_M_TIMER 7 -#define HART_INT_U_EXT 8 -#define HART_INT_S_EXT 9 -#define HART_INT_M_EXT 11 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ -- cgit v1.3.1 From 12f66e2197c59e500d1e2ee359bb2ce22d748290 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Tue, 4 Jul 2023 19:13:21 +0800 Subject: board: ae350: Add missing env variables for booti The 'booti' command is unable to boot Image.gz due to the absence of required environment variables 'kernel_comp_addr_r' and 'kernel_comp_size'. This commit adds these variables and reorganizes the memory layout to prevent any overlap between binaries and files. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- include/configs/ae350.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf296f..23e4801379d 100644 --- a/include/configs/ae350.h +++ b/include/configs/ae350.h @@ -83,11 +83,15 @@ #include #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00080000\0" \ - "pxefile_addr_r=0x01f00000\0" \ - "scriptaddr=0x01f00000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02800000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x00600000\0" \ + "kernel_comp_addr_r=0x04600000\0" \ + "kernel_comp_size=0x04000000\0" \ + "pxefile_addr_r=0x08600000\0" \ + "scriptaddr=0x08700000\0" \ + "fdt_addr_r=0x08800000\0" \ + "ramdisk_addr_r=0x08900000\0" \ BOOTENV #endif /* __CONFIG_H */ -- cgit v1.3.1