From 01c8b664d23829b254e6745a75123c5b9d512520 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 24 Nov 2022 11:36:03 +0100 Subject: dt-bindings: stm32mp13: add clock & reset support for STM32MP13 Add support of stm32mp13 DT bindings of clock and reset. Signed-off-by: Gabriel Fernandez Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/dt-bindings/clock/stm32mp13-clks.h | 229 +++++++++++++++++++++++++++ include/dt-bindings/reset/stm32mp13-resets.h | 100 ++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h create mode 100644 include/dt-bindings/reset/stm32mp13-resets.h (limited to 'include') diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h new file mode 100644 index 00000000000..799dee5b802 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ +#define _DT_BINDINGS_STM32MP13_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* PLL */ +#define PLL1 6 +#define PLL2 7 +#define PLL3 8 +#define PLL4 9 + +/* ODF */ +#define PLL1_P 10 +#define PLL1_Q 11 +#define PLL1_R 12 +#define PLL2_P 13 +#define PLL2_Q 14 +#define PLL2_R 15 +#define PLL3_P 16 +#define PLL3_Q 17 +#define PLL3_R 18 +#define PLL4_P 19 +#define PLL4_Q 20 +#define PLL4_R 21 + +#define PCLK1 22 +#define PCLK2 23 +#define PCLK3 24 +#define PCLK4 25 +#define PCLK5 26 +#define PCLK6 27 + +/* SYSTEM CLOCK */ +#define CK_PER 28 +#define CK_MPU 29 +#define CK_AXI 30 +#define CK_MLAHB 31 + +/* BASE TIMER */ +#define CK_TIMG1 32 +#define CK_TIMG2 33 +#define CK_TIMG3 34 + +/* AUX */ +#define RTC 35 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 36 +#define CK_TRACE 37 + +/* MCO clocks */ +#define CK_MCO1 38 +#define CK_MCO2 39 + +/* IP clocks */ +#define SYSCFG 40 +#define VREF 41 +#define DTS 42 +#define PMBCTRL 43 +#define HDP 44 +#define IWDG2 45 +#define STGENRO 46 +#define USART1 47 +#define RTCAPB 48 +#define TZC 49 +#define TZPC 50 +#define IWDG1 51 +#define BSEC 52 +#define DMA1 53 +#define DMA2 54 +#define DMAMUX1 55 +#define DMAMUX2 56 +#define GPIOA 57 +#define GPIOB 58 +#define GPIOC 59 +#define GPIOD 60 +#define GPIOE 61 +#define GPIOF 62 +#define GPIOG 63 +#define GPIOH 64 +#define GPIOI 65 +#define CRYP1 66 +#define HASH1 67 +#define BKPSRAM 68 +#define MDMA 69 +#define CRC1 70 +#define USBH 71 +#define DMA3 72 +#define TSC 73 +#define PKA 74 +#define AXIMC 75 +#define MCE 76 +#define ETH1TX 77 +#define ETH2TX 78 +#define ETH1RX 79 +#define ETH2RX 80 +#define ETH1MAC 81 +#define ETH2MAC 82 +#define ETH1STP 83 +#define ETH2STP 84 + +/* IP clocks with parents */ +#define SDMMC1_K 85 +#define SDMMC2_K 86 +#define ADC1_K 87 +#define ADC2_K 88 +#define FMC_K 89 +#define QSPI_K 90 +#define RNG1_K 91 +#define USBPHY_K 92 +#define STGEN_K 93 +#define SPDIF_K 94 +#define SPI1_K 95 +#define SPI2_K 96 +#define SPI3_K 97 +#define SPI4_K 98 +#define SPI5_K 99 +#define I2C1_K 100 +#define I2C2_K 101 +#define I2C3_K 102 +#define I2C4_K 103 +#define I2C5_K 104 +#define TIM2_K 105 +#define TIM3_K 106 +#define TIM4_K 107 +#define TIM5_K 108 +#define TIM6_K 109 +#define TIM7_K 110 +#define TIM12_K 111 +#define TIM13_K 112 +#define TIM14_K 113 +#define TIM1_K 114 +#define TIM8_K 115 +#define TIM15_K 116 +#define TIM16_K 117 +#define TIM17_K 118 +#define LPTIM1_K 119 +#define LPTIM2_K 120 +#define LPTIM3_K 121 +#define LPTIM4_K 122 +#define LPTIM5_K 123 +#define USART1_K 124 +#define USART2_K 125 +#define USART3_K 126 +#define UART4_K 127 +#define UART5_K 128 +#define USART6_K 129 +#define UART7_K 130 +#define UART8_K 131 +#define DFSDM_K 132 +#define FDCAN_K 133 +#define SAI1_K 134 +#define SAI2_K 135 +#define ADFSDM_K 136 +#define USBO_K 137 +#define LTDC_PX 138 +#define ETH1CK_K 139 +#define ETH1PTP_K 140 +#define ETH2CK_K 141 +#define ETH2PTP_K 142 +#define DCMIPP_K 143 +#define SAES_K 144 +#define DTS_K 145 + +/* DDR */ +#define DDRC1 146 +#define DDRC1LP 147 +#define DDRC2 148 +#define DDRC2LP 149 +#define DDRPHYC 150 +#define DDRPHYCLP 151 +#define DDRCAPB 152 +#define DDRCAPBLP 153 +#define AXIDCG 154 +#define DDRPHYCAPB 155 +#define DDRPHYCAPBLP 156 +#define DDRPERFM 157 + +#define ADC1 158 +#define ADC2 159 +#define SAI1 160 +#define SAI2 161 + +#define STM32MP1_LAST_CLK 162 + +/* SCMI clock identifiers */ +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_HSE_DIV2 5 +#define CK_SCMI_PLL2_Q 6 +#define CK_SCMI_PLL2_R 7 +#define CK_SCMI_PLL3_P 8 +#define CK_SCMI_PLL3_Q 9 +#define CK_SCMI_PLL3_R 10 +#define CK_SCMI_PLL4_P 11 +#define CK_SCMI_PLL4_Q 12 +#define CK_SCMI_PLL4_R 13 +#define CK_SCMI_MPU 14 +#define CK_SCMI_AXI 15 +#define CK_SCMI_MLAHB 16 +#define CK_SCMI_CKPER 17 +#define CK_SCMI_PCLK1 18 +#define CK_SCMI_PCLK2 19 +#define CK_SCMI_PCLK3 20 +#define CK_SCMI_PCLK4 21 +#define CK_SCMI_PCLK5 22 +#define CK_SCMI_PCLK6 23 +#define CK_SCMI_CKTIMG1 24 +#define CK_SCMI_CKTIMG2 25 +#define CK_SCMI_CKTIMG3 26 +#define CK_SCMI_RTC 27 +#define CK_SCMI_RTCAPB 28 + +#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h new file mode 100644 index 00000000000..18ccb05db6c --- /dev/null +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ +#define _DT_BINDINGS_STM32MP13_RESET_H_ + +#define TIM2_R 13568 +#define TIM3_R 13569 +#define TIM4_R 13570 +#define TIM5_R 13571 +#define TIM6_R 13572 +#define TIM7_R 13573 +#define LPTIM1_R 13577 +#define SPI2_R 13579 +#define SPI3_R 13580 +#define USART3_R 13583 +#define UART4_R 13584 +#define UART5_R 13585 +#define UART7_R 13586 +#define UART8_R 13587 +#define I2C1_R 13589 +#define I2C2_R 13590 +#define SPDIF_R 13594 +#define TIM1_R 13632 +#define TIM8_R 13633 +#define SPI1_R 13640 +#define USART6_R 13645 +#define SAI1_R 13648 +#define SAI2_R 13649 +#define DFSDM_R 13652 +#define FDCAN_R 13656 +#define LPTIM2_R 13696 +#define LPTIM3_R 13697 +#define LPTIM4_R 13698 +#define LPTIM5_R 13699 +#define SYSCFG_R 13707 +#define VREF_R 13709 +#define DTS_R 13712 +#define PMBCTRL_R 13713 +#define LTDC_R 13760 +#define DCMIPP_R 13761 +#define DDRPERFM_R 13768 +#define USBPHY_R 13776 +#define STGEN_R 13844 +#define USART1_R 13888 +#define USART2_R 13889 +#define SPI4_R 13890 +#define SPI5_R 13891 +#define I2C3_R 13892 +#define I2C4_R 13893 +#define I2C5_R 13894 +#define TIM12_R 13895 +#define TIM13_R 13896 +#define TIM14_R 13897 +#define TIM15_R 13898 +#define TIM16_R 13899 +#define TIM17_R 13900 +#define DMA1_R 13952 +#define DMA2_R 13953 +#define DMAMUX1_R 13954 +#define DMA3_R 13955 +#define DMAMUX2_R 13956 +#define ADC1_R 13957 +#define ADC2_R 13958 +#define USBO_R 13960 +#define GPIOA_R 14080 +#define GPIOB_R 14081 +#define GPIOC_R 14082 +#define GPIOD_R 14083 +#define GPIOE_R 14084 +#define GPIOF_R 14085 +#define GPIOG_R 14086 +#define GPIOH_R 14087 +#define GPIOI_R 14088 +#define TSC_R 14095 +#define PKA_R 14146 +#define SAES_R 14147 +#define CRYP1_R 14148 +#define HASH1_R 14149 +#define RNG1_R 14150 +#define AXIMC_R 14160 +#define MDMA_R 14208 +#define MCE_R 14209 +#define ETH1MAC_R 14218 +#define FMC_R 14220 +#define QSPI_R 14222 +#define SDMMC1_R 14224 +#define SDMMC2_R 14225 +#define CRC1_R 14228 +#define USBH_R 14232 +#define ETH2MAC_R 14238 + +/* SCMI reset domain identifiers */ +#define RST_SCMI_LTDC 0 +#define RST_SCMI_MDMA 1 + +#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ -- cgit v1.3.1 From 1c03ab9f4bdf19d1ac7afc157788bd0102ccd969 Mon Sep 17 00:00:00 2001 From: Kautuk Consul Date: Wed, 7 Dec 2022 17:12:34 +0530 Subject: lib: Add common semihosting library We factor out the arch-independent parts of the ARM semihosting implementation as a common library so that it can be shared with RISC-V. Signed-off-by: Kautuk Consul Reviewed-by: Leo Yu-Chi Liang --- arch/arm/Kconfig | 46 ----------- arch/arm/lib/semihosting.c | 181 +------------------------------------------ include/semihosting.h | 11 +++ lib/Kconfig | 47 ++++++++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 247 insertions(+), 226 deletions(-) create mode 100644 lib/semihosting.c (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f68d0988b7..cac4fa09fd3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -413,52 +413,6 @@ config ARM_SMCCC This should be enabled if U-Boot needs to communicate with system firmware (for example, PSCI) according to SMCCC. -config SEMIHOSTING - bool "Support ARM semihosting" - help - Semihosting is a method for a target to communicate with a host - debugger. It uses special instructions which the debugger will trap - on and interpret. This allows U-Boot to read/write files, print to - the console, and execute arbitrary commands on the host system. - - Enabling this option will add support for reading and writing files - on the host system. If you don't have a debugger attached then trying - to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. - -config SEMIHOSTING_FALLBACK - bool "Recover gracefully when semihosting fails" - depends on SEMIHOSTING && ARM64 - default y - help - Normally, if U-Boot makes a semihosting call and no debugger is - attached, then it will panic due to a synchronous abort - exception. This config adds an exception handler which will allow - U-Boot to recover. Say 'y' if unsure. - -config SPL_SEMIHOSTING - bool "Support ARM semihosting in SPL" - depends on SPL - help - Semihosting is a method for a target to communicate with a host - debugger. It uses special instructions which the debugger will trap - on and interpret. This allows U-Boot to read/write files, print to - the console, and execute arbitrary commands on the host system. - - Enabling this option will add support for reading and writing files - on the host system. If you don't have a debugger attached then trying - to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. - -config SPL_SEMIHOSTING_FALLBACK - bool "Recover gracefully when semihosting fails in SPL" - depends on SPL_SEMIHOSTING && ARM64 - select ARMV8_SPL_EXCEPTION_VECTORS - default y - help - Normally, if U-Boot makes a semihosting call and no debugger is - attached, then it will panic due to a synchronous abort - exception. This config adds an exception handler which will allow - U-Boot to recover. Say 'y' if unsure. - config SYS_THUMB_BUILD bool "Build U-Boot using the Thumb instruction set" depends on !ARM64 diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 939c0f75132..7b7669bed06 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -5,20 +5,6 @@ */ #include -#include -#include - -#define SYSOPEN 0x01 -#define SYSCLOSE 0x02 -#define SYSWRITEC 0x03 -#define SYSWRITE0 0x04 -#define SYSWRITE 0x05 -#define SYSREAD 0x06 -#define SYSREADC 0x07 -#define SYSISERROR 0x08 -#define SYSSEEK 0x0A -#define SYSFLEN 0x0C -#define SYSERRNO 0x13 /* * Macro to force the compiler to *populate* memory (for an array or struct) @@ -39,7 +25,7 @@ /* * Call the handler */ -static long smh_trap(unsigned int sysnum, void *addr) +long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); register void *_addr asm("r1") = addr; @@ -59,168 +45,3 @@ static long smh_trap(unsigned int sysnum, void *addr) return result; } - -#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) -static bool _semihosting_enabled = true; -static bool try_semihosting = true; - -bool semihosting_enabled(void) -{ - if (try_semihosting) { - smh_trap(SYSERRNO, NULL); - try_semihosting = false; - } - - return _semihosting_enabled; -} - -void disable_semihosting(void) -{ - _semihosting_enabled = false; -} -#endif - -/** - * smh_errno() - Read the host's errno - * - * This gets the value of the host's errno and negates it. The host's errno may - * or may not be set, so only call this function if a previous semihosting call - * has failed. - * - * Return: a negative error value - */ -static int smh_errno(void) -{ - long ret = smh_trap(SYSERRNO, NULL); - - if (ret > 0 && ret < INT_MAX) - return -ret; - return -EIO; -} - -long smh_open(const char *fname, enum smh_open_mode mode) -{ - long fd; - struct smh_open_s { - const char *fname; - unsigned long mode; - size_t len; - } open; - - debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode); - - open.fname = fname; - open.len = strlen(fname); - open.mode = mode; - - /* Open the file on the host */ - fd = smh_trap(SYSOPEN, &open); - if (fd == -1) - return smh_errno(); - return fd; -} - -/** - * struct smg_rdwr_s - Arguments for read and write - * @fd: A file descriptor returned from smh_open() - * @memp: Pointer to a buffer of memory of at least @len bytes - * @len: The number of bytes to read or write - */ -struct smh_rdwr_s { - long fd; - void *memp; - size_t len; -}; - -long smh_read(long fd, void *memp, size_t len) -{ - long ret; - struct smh_rdwr_s read; - - debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); - - read.fd = fd; - read.memp = memp; - read.len = len; - - ret = smh_trap(SYSREAD, &read); - if (ret < 0) - return smh_errno(); - return len - ret; -} - -long smh_write(long fd, const void *memp, size_t len, ulong *written) -{ - long ret; - struct smh_rdwr_s write; - - debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); - - write.fd = fd; - write.memp = (void *)memp; - write.len = len; - - ret = smh_trap(SYSWRITE, &write); - *written = len - ret; - if (ret) - return smh_errno(); - return 0; -} - -long smh_close(long fd) -{ - long ret; - - debug("%s: fd %ld\n", __func__, fd); - - ret = smh_trap(SYSCLOSE, &fd); - if (ret == -1) - return smh_errno(); - return 0; -} - -long smh_flen(long fd) -{ - long ret; - - debug("%s: fd %ld\n", __func__, fd); - - ret = smh_trap(SYSFLEN, &fd); - if (ret == -1) - return smh_errno(); - return ret; -} - -long smh_seek(long fd, long pos) -{ - long ret; - struct smh_seek_s { - long fd; - long pos; - } seek; - - debug("%s: fd %ld pos %ld\n", __func__, fd, pos); - - seek.fd = fd; - seek.pos = pos; - - ret = smh_trap(SYSSEEK, &seek); - if (ret) - return smh_errno(); - return 0; -} - -int smh_getc(void) -{ - return smh_trap(SYSREADC, NULL); -} - -void smh_putc(char ch) -{ - smh_trap(SYSWRITEC, &ch); -} - -void smh_puts(const char *s) -{ - smh_trap(SYSWRITE0, (char *)s); -} diff --git a/include/semihosting.h b/include/semihosting.h index f1f73464e4f..4e844cbad87 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -17,6 +17,17 @@ #define SMH_T32_SVC 0xDFAB #define SMH_T32_HLT 0xBABC +/** + * smh_trap() - ARCH-specific semihosting call. + * + * Semihosting library/driver can use this function to do the + * actual semihosting calls. + * + * Return: Error code defined by semihosting spec. + */ + +long smh_trap(unsigned int sysnum, void *addr); + #if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) /** * semihosting_enabled() - Determine whether semihosting is supported diff --git a/lib/Kconfig b/lib/Kconfig index 6abe1d0a863..b8833e01837 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -71,6 +71,53 @@ config HAVE_PRIVATE_LIBGCC config LIB_UUID bool +config SEMIHOSTING + bool "Support semihosting" + depends on ARM + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails" + depends on SEMIHOSTING && ARM64 + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + +config SPL_SEMIHOSTING + bool "Support semihosting in SPL" + depends on SPL && ARM + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SPL_SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails in SPL" + depends on SPL_SEMIHOSTING && ARM64 + select ARMV8_SPL_EXCEPTION_VECTORS + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + config PRINTF bool default y diff --git a/lib/Makefile b/lib/Makefile index f2cfd1e4289..d77b33e7f48 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -146,6 +146,8 @@ obj-y += date.o obj-y += rtc-lib.o obj-$(CONFIG_LIB_ELF) += elf.o +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o + # # Build a fast OID lookup registry from include/linux/oid_registry.h # diff --git a/lib/semihosting.c b/lib/semihosting.c new file mode 100644 index 00000000000..831774e3566 --- /dev/null +++ b/lib/semihosting.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + * Copyright 2014 Broadcom Corporation + */ + +#include +#include +#include + +#define SYSOPEN 0x01 +#define SYSCLOSE 0x02 +#define SYSWRITEC 0x03 +#define SYSWRITE0 0x04 +#define SYSWRITE 0x05 +#define SYSREAD 0x06 +#define SYSREADC 0x07 +#define SYSISERROR 0x08 +#define SYSSEEK 0x0A +#define SYSFLEN 0x0C +#define SYSERRNO 0x13 + +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) +static bool _semihosting_enabled = true; +static bool try_semihosting = true; + +bool semihosting_enabled(void) +{ + if (try_semihosting) { + smh_trap(SYSERRNO, NULL); + try_semihosting = false; + } + + return _semihosting_enabled; +} + +void disable_semihosting(void) +{ + _semihosting_enabled = false; +} +#endif + +/** + * smh_errno() - Read the host's errno + * + * This gets the value of the host's errno and negates it. The host's errno may + * or may not be set, so only call this function if a previous semihosting call + * has failed. + * + * Return: a negative error value + */ +static int smh_errno(void) +{ + long ret = smh_trap(SYSERRNO, NULL); + + if (ret > 0 && ret < INT_MAX) + return -ret; + return -EIO; +} + +long smh_open(const char *fname, enum smh_open_mode mode) +{ + long fd; + struct smh_open_s { + const char *fname; + unsigned long mode; + size_t len; + } open; + + debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode); + + open.fname = fname; + open.len = strlen(fname); + open.mode = mode; + + /* Open the file on the host */ + fd = smh_trap(SYSOPEN, &open); + if (fd == -1) + return smh_errno(); + return fd; +} + +/** + * struct smg_rdwr_s - Arguments for read and write + * @fd: A file descriptor returned from smh_open() + * @memp: Pointer to a buffer of memory of at least @len bytes + * @len: The number of bytes to read or write + */ +struct smh_rdwr_s { + long fd; + void *memp; + size_t len; +}; + +long smh_read(long fd, void *memp, size_t len) +{ + long ret; + struct smh_rdwr_s read; + + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); + + read.fd = fd; + read.memp = memp; + read.len = len; + + ret = smh_trap(SYSREAD, &read); + if (ret < 0) + return smh_errno(); + return len - ret; +} + +long smh_write(long fd, const void *memp, size_t len, ulong *written) +{ + long ret; + struct smh_rdwr_s write; + + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); + + write.fd = fd; + write.memp = (void *)memp; + write.len = len; + + ret = smh_trap(SYSWRITE, &write); + *written = len - ret; + if (ret) + return smh_errno(); + return 0; +} + +long smh_close(long fd) +{ + long ret; + + debug("%s: fd %ld\n", __func__, fd); + + ret = smh_trap(SYSCLOSE, &fd); + if (ret == -1) + return smh_errno(); + return 0; +} + +long smh_flen(long fd) +{ + long ret; + + debug("%s: fd %ld\n", __func__, fd); + + ret = smh_trap(SYSFLEN, &fd); + if (ret == -1) + return smh_errno(); + return ret; +} + +long smh_seek(long fd, long pos) +{ + long ret; + struct smh_seek_s { + long fd; + long pos; + } seek; + + debug("%s: fd %ld pos %ld\n", __func__, fd, pos); + + seek.fd = fd; + seek.pos = pos; + + ret = smh_trap(SYSSEEK, &seek); + if (ret) + return smh_errno(); + return 0; +} + +int smh_getc(void) +{ + return smh_trap(SYSREADC, NULL); +} + +void smh_putc(char ch) +{ + smh_trap(SYSWRITEC, &ch); +} + +void smh_puts(const char *s) +{ + smh_trap(SYSWRITE0, (char *)s); +} -- cgit v1.3.1 From bcd4110702d38c5356c84da6dc286c565ec19db3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Nov 2022 11:42:02 +0100 Subject: dfu: Make DFU virtual backend SPL friendly Define stub for dfu_*_virt function in SPL, because CONFIG_SPL_DFU_VIRT is not defined. This patch avoids compilation issue in dfu_fill_entity() when CONFIG_SPL_DFU is activated because the dfu_fill_entity_virt() function is not available. Fixes: ec44cace4b8d2 ("dfu: add DFU virtual backend") Reported-by: Marek Vasut Signed-off-by: Patrick Delaunay Reviewed-by: Marek Vasut Tested-by: Marek Vasut --- include/dfu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dfu.h b/include/dfu.h index dcb9cd9d799..07922224ef1 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -495,7 +495,7 @@ static inline int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, } #endif -#ifdef CONFIG_DFU_VIRT +#if CONFIG_IS_ENABLED(DFU_VIRT) int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, char **argv, int argc); int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset, -- cgit v1.3.1 From 670789f5ba2f3330b137f637deb47671b8720c33 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 8 Nov 2022 10:07:19 +0100 Subject: mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase() This function is only used within this module, so it is no longer necessary to use EXPORT_SYMBOL_GPL(). This patch parallels the work done in the following patch: https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dario Binacchi Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com --- drivers/mtd/nand/core.c | 3 +-- include/linux/mtd/nand.h | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 99c29670c75..4b9dd6a9269 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -129,7 +129,7 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved); * * Return: 0 in case of success, a negative error code otherwise. */ -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) +static int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) { unsigned int entry; @@ -147,7 +147,6 @@ int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) return nand->ops->erase(nand, pos); } -EXPORT_SYMBOL_GPL(nanddev_erase); /** * nanddev_mtd_erase() - Generic mtd->_erase() implementation for NAND devices diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 7774c17ad5d..aeb38dec2e0 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -691,7 +691,6 @@ static inline bool nanddev_io_iter_end(struct nand_device *nand, bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos); bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos); -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos); int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos); /* BBT related functions */ -- cgit v1.3.1 From ed82586c4054c62c35e119f4f0a14619f0ad6c2e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 28 Nov 2022 00:03:53 +0000 Subject: sunxi: remove unused CONFIG_MMC_SUNXI_SLOT There is a CONFIG_MMC_SUNXI_SLOT definition in our sunxi_common.h config header, which was used to note the first MMC controller to initialise. The definition in that header was always set to 0, with no easy way of overriding this, and certainly none of the existing boards made any use of that (non-)feature. Remove that definition and replace it with a constant 0 in the only user, in board.c. It turns out that this is safe, as this is only used in the SPL, and the BROM also unconditionally initialises MMC0. This also removes the last legacy config symbol with SUN*I in it from the whitelist. Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Andre Przywara --- board/sunxi/board.c | 9 +++++++-- include/configs/sunxi-common.h | 3 --- scripts/config_whitelist.txt | 1 - 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 21a2407e062..4d2491b5a86 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -525,9 +525,14 @@ static void mmc_pinmux_setup(int sdc) int board_mmc_init(struct bd_info *bis) { + /* + * The BROM always accesses MMC port 0 (typically an SD card), and + * most boards seem to have such a slot. The others haven't reported + * any problem with unconditionally enabling this in the SPL. + */ if (!IS_ENABLED(CONFIG_UART0_PORT_F)) { - mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); - if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT)) + mmc_pinmux_setup(0); + if (!sunxi_mmc_init(0)) return -1; } diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 720768629d6..e89ad42ce8d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -75,9 +75,6 @@ #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #endif -/* mmc config */ -#define CONFIG_MMC_SUNXI_SLOT 0 - /* * Miscellaneous configurable options */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c0f55e41a50..ea71f9d2344 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -153,7 +153,6 @@ CONFIG_MISC_COMMON CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED CONFIG_MMC_DEFAULT_DEV -CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME -- cgit v1.3.1 From 63db1561f1db28c83dea1e219fe87e264a184eb4 Mon Sep 17 00:00:00 2001 From: Vincent Stehlé Date: Fri, 16 Dec 2022 17:55:04 +0100 Subject: efi: adjust ebbr to v2.1 in conformance profile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EFI Conformance Profile Table entry for EBBR appears in v2.1.0 of the EBBR specification[1]. Update naming accordingly. While at it, update the EBBR version referenced in the documentation. [1]: https://github.com/ARM-software/ebbr/releases/tag/v2.1.0 Signed-off-by: Vincent Stehlé Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- doc/develop/uefi/uefi.rst | 6 +++--- include/efi_api.h | 2 +- lib/efi_loader/Kconfig | 6 +++--- lib/efi_loader/efi_conformance.c | 8 ++++---- lib/efi_selftest/efi_selftest_ecpt.c | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index e0835beba41..a944c0fb803 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -14,7 +14,7 @@ Development target ------------------ The implementation of UEFI in U-Boot strives to reach the requirements described -in the "Embedded Base Boot Requirements (EBBR) Specification - Release v1.0" +in the "Embedded Base Boot Requirements (EBBR) Specification - Release v2.1.0" [2]. The "Server Base Boot Requirements System Software on ARM Platforms" [3] describes a superset of the EBBR specification and may be used as further reference. @@ -799,8 +799,8 @@ Links ----- * [1] http://uefi.org/specifications - UEFI specifications -* [2] https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf - - Embedded Base Boot Requirements (EBBR) Specification - Release v1.0 +* [2] https://github.com/ARM-software/ebbr/releases/download/v2.1.0/ebbr-v2.1.0.pdf - + Embedded Base Boot Requirements (EBBR) Specification - Release v2.1.0 * [3] https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11 - Server Base Boot Requirements System Software on ARM Platforms - Version 1.1 * [4] :doc:`iscsi` diff --git a/include/efi_api.h b/include/efi_api.h index 9bb0d44ac8d..00c98e0984d 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -232,7 +232,7 @@ enum efi_reset_type { #define EFI_CONFORMANCE_PROFILES_TABLE_VERSION 1 -#define EFI_CONFORMANCE_PROFILE_EBBR_2_0_GUID \ +#define EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID \ EFI_GUID(0xcce33c35, 0x74ac, 0x4087, 0xbc, 0xe7, \ 0x8b, 0x29, 0xb0, 0x2e, 0xeb, 0x27) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e2b643871bf..b498c72206f 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -384,8 +384,8 @@ config EFI_ECPT help Enabling this option created the ECPT UEFI table. -config EFI_EBBR_2_0_CONFORMANCE - bool "Add the EBBRv2.0 conformance entry to the ECPT table" +config EFI_EBBR_2_1_CONFORMANCE + bool "Add the EBBRv2.1 conformance entry to the ECPT table" depends on EFI_ECPT depends on EFI_LOADER_HII depends on EFI_RISCV_BOOT_PROTOCOL || !RISCV @@ -393,7 +393,7 @@ config EFI_EBBR_2_0_CONFORMANCE depends on EFI_UNICODE_COLLATION_PROTOCOL2 default y help - Enabling this option adds the EBBRv2.0 conformance entry to the ECPT UEFI table. + Enabling this option adds the EBBRv2.1 conformance entry to the ECPT UEFI table. config EFI_RISCV_BOOT_PROTOCOL bool "RISCV_EFI_BOOT_PROTOCOL support" diff --git a/lib/efi_loader/efi_conformance.c b/lib/efi_loader/efi_conformance.c index a49aae92497..3036d46349a 100644 --- a/lib/efi_loader/efi_conformance.c +++ b/lib/efi_loader/efi_conformance.c @@ -12,8 +12,8 @@ #include static const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID; -static const efi_guid_t efi_ebbr_2_0_guid = - EFI_CONFORMANCE_PROFILE_EBBR_2_0_GUID; +static const efi_guid_t efi_ebbr_2_1_guid = + EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID; /** * efi_ecpt_register() - Install the ECPT system table. @@ -38,9 +38,9 @@ efi_status_t efi_ecpt_register(void) return ret; } - if (CONFIG_IS_ENABLED(EFI_EBBR_2_0_CONFORMANCE)) + if (CONFIG_IS_ENABLED(EFI_EBBR_2_1_CONFORMANCE)) guidcpy(&ecpt->conformance_profiles[num_entries++], - &efi_ebbr_2_0_guid); + &efi_ebbr_2_1_guid); ecpt->version = EFI_CONFORMANCE_PROFILES_TABLE_VERSION; ecpt->number_of_profiles = num_entries; diff --git a/lib/efi_selftest/efi_selftest_ecpt.c b/lib/efi_selftest/efi_selftest_ecpt.c index e8cc13545db..09c5e96c5e1 100644 --- a/lib/efi_selftest/efi_selftest_ecpt.c +++ b/lib/efi_selftest/efi_selftest_ecpt.c @@ -10,7 +10,7 @@ #include static const efi_guid_t guid_ecpt = EFI_CONFORMANCE_PROFILES_TABLE_GUID; -static const efi_guid_t guid_ebbr_2_0 = EFI_CONFORMANCE_PROFILE_EBBR_2_0_GUID; +static const efi_guid_t guid_ebbr_2_1 = EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID; /* * ecpt_find_guid() - find GUID in EFI Conformance Profile Table @@ -53,9 +53,9 @@ static int execute(void) return EFI_ST_FAILURE; } - if (CONFIG_IS_ENABLED(EFI_EBBR_2_0_CONFORMANCE)) { + if (CONFIG_IS_ENABLED(EFI_EBBR_2_1_CONFORMANCE)) { ++expected_entries; - if (ecpt_find_guid(ecpt, &guid_ebbr_2_0)) + if (ecpt_find_guid(ecpt, &guid_ebbr_2_1)) return EFI_ST_FAILURE; } -- cgit v1.3.1 From 4d89330b8ac1852e14f079ead75021a17b4b744e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 9 Sep 2022 22:18:45 +0200 Subject: rockchip: rk3128-cru: sync the clock dt-binding header from Linux In order to update the DT for rk3128 sync the clock dt-binding header. This is the state as of v6.0 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3128.dtsi | 6 +- drivers/clk/rockchip/clk_rk3128.c | 8 +- include/dt-bindings/clock/rk3128-cru.h | 222 +++++++++++++++++++++++---------- 3 files changed, 160 insertions(+), 76 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 5d2499c1324..3c5f54f6406 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -172,7 +172,7 @@ interrupts = , ; #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; + clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; }; @@ -530,8 +530,8 @@ pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; rockchip,spi-src-clk = <0>; num-cs = <2>; - clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spi","pclk_spi0"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; dmas = <&pdma 8>, <&pdma 9>; #dma-cells = <2>; dma-names = "tx", "rx"; diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index d5b2b63dd79..13e176cdad1 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -438,7 +438,7 @@ static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) VIO1_SEL_GPLL << VIO1_PLL_SHIFT | (src_clk_div - 1) << VIO1_DIV_SHIFT); break; - case DCLK_LCDC: + case DCLK_VOP: if (pll_para_config(hz, &cpll_config)) return -1; rkclk_set_pll(cru, CLK_CODEC, &cpll_config); @@ -471,7 +471,7 @@ static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id) div = (con >> 8) & 0x1f; parent = GPLL_HZ; break; - case DCLK_LCDC: + case DCLK_VOP: con = readl(&cru->cru_clksel_con[27]); div = (con >> 8) & 0xfff; parent = rkclk_pll_get_rate(cru, CLK_CODEC); @@ -497,7 +497,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk) return rk3128_peri_get_pclk(priv->cru, clk->id); case SCLK_SARADC: return rk3128_saradc_get_clk(priv->cru); - case DCLK_LCDC: + case DCLK_VOP: case ACLK_VIO0: case ACLK_VIO1: return rk3128_vop_get_rate(priv->cru, clk->id); @@ -515,7 +515,7 @@ static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case 0 ... 63: return 0; - case DCLK_LCDC: + case DCLK_VOP: case ACLK_VIO0: case ACLK_VIO1: new_rate = rk3128_vop_set_clk(priv->cru, diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index cfb3afbb285..6a47825dac5 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H @@ -9,30 +10,31 @@ /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 +#define PLL_GPLL_DIV2 6 +#define PLL_GPLL_DIV3 7 /* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 #define SCLK_SDMMC 68 #define SCLK_SDIO 69 #define SCLK_EMMC 71 -#define SCLK_NANDC 76 #define SCLK_UART0 77 #define SCLK_UART1 78 #define SCLK_UART2 79 -#define SCLK_I2S 82 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 #define SCLK_SPDIF 83 #define SCLK_TIMER0 85 #define SCLK_TIMER1 86 #define SCLK_TIMER2 87 #define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 #define SCLK_SARADC 91 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 #define SCLK_I2S_OUT 113 #define SCLK_SDMMC_DRV 114 #define SCLK_SDIO_DRV 115 @@ -40,115 +42,173 @@ #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 +#define SCLK_VOP 122 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_HEVC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 +#define SCLK_PVTM_FUNC 145 +#define SCLK_PVTM_CORE 146 +#define SCLK_PVTM_GPU 147 +#define SCLK_MIPI_24M 148 +#define SCLK_PVTM 149 +#define SCLK_CIF_SRC 150 +#define SCLK_CIF_OUT_SRC 151 +#define SCLK_CIF_OUT 152 +#define SCLK_SFC 153 +#define SCLK_USB480M 154 -#define DCLK_LCDC 190 +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_EBC 191 /* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_VIO0 197 -#define ACLK_VIO1 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 +#define ACLK_VIO0 192 +#define ACLK_VIO1 193 +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VEPU 196 +#define ACLK_VDPU 197 +#define ACLK_CIF 198 +#define ACLK_IEP 199 +#define ACLK_LCDC0 204 +#define ACLK_RGA 205 #define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_SARADC 318 +#define PCLK_WDT 319 #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_MIPI 325 +#define PCLK_EFUSE 326 +#define PCLK_HDMI 327 +#define PCLK_ACODEC 328 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 #define PCLK_I2C2 334 #define PCLK_I2C3 335 -#define PCLK_SPI 338 +#define PCLK_SPI0 338 #define PCLK_UART0 341 #define PCLK_UART1 342 #define PCLK_UART2 343 +#define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 +#define PCLK_CPU 354 #define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 +#define PCLK_GMAC 367 +#define PCLK_PMU_PRE 368 +#define PCLK_SIM_CARD 369 /* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 +#define HCLK_SPDIF 440 +#define HCLK_GPS 441 +#define HCLK_USBHOST 442 +#define HCLK_I2S_8CH 443 +#define HCLK_I2S_2CH 444 +#define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 +#define HCLK_CPU 460 +#define HCLK_VEPU 461 +#define HCLK_VDPU 462 +#define HCLK_LCDC0 463 +#define HCLK_EBC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_CIF 470 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_CRYPTO 476 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 #define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 +#define SRST_L2C 15 -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 +#define SRST_CPUSYS_H 18 +#define SRST_AHB2APBSYS_H 19 +#define SRST_SPDIF 20 #define SRST_INTMEM 21 #define SRST_ROM 22 #define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 +#define SRST_I2S_2CH 24 +#define SRST_I2S_8CH 25 +#define SRST_GPU_PVTM 26 +#define SRST_FUNC_PVTM 27 +#define SRST_CORE_PVTM 29 #define SRST_EFUSE_P 30 #define SRST_ACODEC_P 31 #define SRST_GPIO0 32 #define SRST_GPIO1 33 #define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_MIPIPHY_P 36 #define SRST_UART0 39 #define SRST_UART1 40 #define SRST_UART2 41 #define SRST_I2C0 43 #define SRST_I2C1 44 #define SRST_I2C2 45 +#define SRST_I2C3 46 #define SRST_SFC 47 -#define SRST_PWM0 48 +#define SRST_PWM 48 +#define SRST_DAP_PO 50 #define SRST_DAP 51 #define SRST_DAP_SYS 52 +#define SRST_CRYPTO 53 #define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 +#define SRST_GMAC 56 +#define SRST_PERIPH_SYS_A 57 +#define SRST_PERIPH_SYS_H 58 +#define SRST_PERIPH_SYS_P 59 +#define SRST_SMART_CARD 60 #define SRST_CPU_PERI 61 #define SRST_EMEM_PERI 62 #define SRST_USB_PERI 63 -#define SRST_DMA2 64 -#define SRST_MAC 66 +#define SRST_DMA 64 +#define SRST_GPS 67 #define SRST_NANDC 68 #define SRST_USBOTG0 69 #define SRST_OTGC0 71 @@ -156,34 +216,58 @@ #define SRST_OTGC1 74 #define SRST_DDRMSCH 79 -#define SRST_MMC0 81 +#define SRST_SDMMC 81 #define SRST_SDIO 82 #define SRST_EMMC 83 -#define SRST_SPI0 84 +#define SRST_SPI 84 #define SRST_WDT 86 #define SRST_SARADC 87 #define SRST_DDRPHY 88 #define SRST_DDRPHY_P 89 #define SRST_DDRCTRL 90 #define SRST_DDRCTRL_P 91 +#define SRST_TSP 92 +#define SRST_TSP_CLKIN 93 +#define SRST_HOST0_ECHI 94 #define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_VIO0_A 98 #define SRST_VIO_BUS_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 #define SRST_UTMI0 103 #define SRST_UTMI1 104 #define SRST_USBPOR 105 +#define SRST_IEP_A 106 +#define SRST_IEP_H 107 +#define SRST_RGA_A 108 +#define SRST_RGA_H 109 +#define SRST_CIF0 110 +#define SRST_PMU 111 #define SRST_VCODEC_A 112 #define SRST_VCODEC_H 113 #define SRST_VIO1_A 114 -#define SRST_HEVC 115 +#define SRST_HEVC_CORE 115 #define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 +#define SRST_PMU_NIU_P 117 +#define SRST_LCDC0_S 119 #define SRST_GPU 120 #define SRST_GPU_NIU_A 122 +#define SRST_EBC_A 123 +#define SRST_EBC_H 124 -#define SRST_DBG_P 131 +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_VIO_MIPI_DSI 137 #endif -- cgit v1.3.1 From e86c789ca372b52e5872d9c9d5081be420cc4b6b Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Thu, 10 Nov 2022 14:49:16 +0530 Subject: rockpi4: board: Add firmware image information for capsule updates Add information that will be needed for enabling the UEFI capsule update feature on the RockPi4 boards. With the feature enabled, it would be possible to update the idbloader and u-boot.itb images on the RockPi4B and RockPi4C variants. Signed-off-by: Sughosh Ganu Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/misc.h | 1 + board/rockchip/evb_rk3399/evb-rk3399.c | 55 ++++++++++++++++++++++++++++++- include/configs/rk3399_common.h | 16 +++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h index b6b03c934ed..4155af8c3b0 100644 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ b/arch/arm/include/asm/arch-rockchip/misc.h @@ -11,3 +11,4 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset, u8 *cpuid); int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); int rockchip_setup_macaddr(void); +void rockchip_capsule_update_board_setup(void); diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index abb76585cf8..f56b379b937 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -5,11 +5,25 @@ #include #include +#include #include #include #include +#include #include +#define ROCKPI4_UPDATABLE_IMAGES 2 + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0}; + +struct efi_capsule_update_info update_info = { + .images = fw_images, +}; + +u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES; +#endif + #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) { @@ -29,4 +43,43 @@ int board_early_init_f(void) out: return 0; } -#endif + +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) +static bool board_is_rockpi_4b(void) +{ + return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) && + of_machine_is_compatible("radxa,rockpi4b"); +} + +static bool board_is_rockpi_4c(void) +{ + return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) && + of_machine_is_compatible("radxa,rockpi4c"); +} + +void rockchip_capsule_update_board_setup(void) +{ + if (board_is_rockpi_4b()) { + efi_guid_t idbldr_image_type_guid = + ROCKPI_4B_IDBLOADER_IMAGE_GUID; + efi_guid_t uboot_image_type_guid = ROCKPI_4B_UBOOT_IMAGE_GUID; + + guidcpy(&fw_images[0].image_type_id, &idbldr_image_type_guid); + guidcpy(&fw_images[1].image_type_id, &uboot_image_type_guid); + + fw_images[0].fw_name = u"ROCKPI4B-IDBLOADER"; + fw_images[1].fw_name = u"ROCKPI4B-UBOOT"; + } else if (board_is_rockpi_4c()) { + efi_guid_t idbldr_image_type_guid = + ROCKPI_4C_IDBLOADER_IMAGE_GUID; + efi_guid_t uboot_image_type_guid = ROCKPI_4C_UBOOT_IMAGE_GUID; + + guidcpy(&fw_images[0].image_type_id, &idbldr_image_type_guid); + guidcpy(&fw_images[1].image_type_id, &uboot_image_type_guid); + + fw_images[0].fw_name = u"ROCKPI4C-IDBLOADER"; + fw_images[1].fw_name = u"ROCKPI4C-UBOOT"; + } +} +#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */ +#endif /* !CONFIG_SPL_BUILD */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2f9aee58197..f0a9ab8f83c 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -24,6 +24,22 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 +#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ + 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) + +#define ROCKPI_4B_UBOOT_IMAGE_GUID \ + EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ + 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) + +#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ + 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) + +#define ROCKPI_4C_UBOOT_IMAGE_GUID \ + EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ + 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) + #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ -- cgit v1.3.1