From 2884e5df697b49c98b8766b5f1964d6573eadfe5 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 28 May 2024 11:59:38 +0200 Subject: board: toradex: verdin-imx8mm: increase maximum addressable ram to 4GB Add support for SKUs with higher memory sizes. Actual memory size is auto-detected. Signed-off-by: Emanuele Ghidoli --- include/configs/verdin-imx8mm.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 34238d3b505..12d2b682305 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -58,8 +58,10 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (long)(SZ_2G + SZ_1G) +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (long)(SZ_1G) /* USB Configs */ #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -- cgit v1.2.3 From cff451e03ff3c9612723c8ab2b8b5be525538936 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 28 May 2024 15:35:13 +0200 Subject: board: phytec: phycore_imx8mp: Add support for different RAM sizes Add support for different RAM sizes and speed grades on the phyCORE-i.MX8MP. Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz, 4GB 2GHz and 8GB 2GHz RAM. The RAM size and speed grade is detected by the information stored in the EEPROM on the SoM. Co-developed-by: Benjamin Hahn Signed-off-by: Benjamin Hahn Co-developed-by: Yannic Moog Signed-off-by: Yannic Moog Co-developed-by: Yashwanth Varakala Signed-off-by: Yashwanth Varakala Signed-off-by: Teresa Remmet --- include/configs/phycore_imx8mp.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 206c4d50d27..299fabc6a99 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -22,6 +22,8 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0x80000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ #endif /* __PHYCORE_IMX8MP_H */ -- cgit v1.2.3 From fb95661116fb4269883721afd80578e6d88ce043 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 28 May 2024 16:15:10 -0300 Subject: imx8mm-cl-iot-gate: Add support for the Realtek RTL8211E PHY Newer imx8mm-cl-iot-gate versions are populated with a Realtek RTL8211E PHY instead of the Atheros AR8033. Adapted Compulab's patch from: https://github.com/compulab-yokneam/meta-bsp-imx8mm/blob/iot-gate-imx8_5.10.72/recipes-bsp/u-boot/compulab/imx8mm/0125-imx8mm-net-enable-phy-Realtek-RTL8211E.patch to support both PHYs in U-Boot. Signed-off-by: Fabio Estevam --- include/configs/imx8mm-cl-iot-gate.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 09d87cf214b..0c547027ba6 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -136,7 +136,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CFG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */ /* USB Configs */ #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -- cgit v1.2.3