From 26f32c32b2506172130255ee2a136d66bc28905c Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:38 +0530 Subject: configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For USB DFU boot mode there is a limitation on the load address of boot images that they have to be less than 0x70001000. Therefore, move the SPL_TEXT_BASE address to 0x70000000. Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at 0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move the location of ATF to a latter location in SRAM, past the SPL image. Also rearrange the EEPROM and BSS data on top of ATF. Given below is the placement of various data sections in SRAM ┌──────────────────────────────────────┐0x70000000 │ │ │ │ │ │ │ SPL IMAGE (Max size 1.5 MB) │ │ │ │ │ │ │ ├──────────────────────────────────────┤0x7017FFFF │ │ │ SPL STACK │ │ │ ├──────────────────────────────────────┤0x70192727 │ GLOBAL DATA(216 B) │ ├──────────────────────────────────────┤0x701927FF │ │ │ INITIAL HEAP (32 KB) │ │ │ ├──────────────────────────────────────┤0x7019A7FF │ │ │ BSS (20 KB) │ ├──────────────────────────────────────┤0x7019F7FF │ EEPROM DATA (2 KB) │ ├──────────────────────────────────────┤0x7019FFFF │ │ │ │ │ ATF (123 KB) │ │ │ │ │ ├──────────────────────────────────────┤0x701BEBFB │ BOOT PARAMETER INDEX TABLE (5124 B)│ ├──────────────────────────────────────┤0x701BFFFF │ │ │SYSFW FIREWALLED DUE TO A BUG (128 KB)│ │ │ ├──────────────────────────────────────┤0x701DFFFF │ │ │ DMSC CODE AREA (128 KB) │ │ │ └──────────────────────────────────────┘0x701FFFFF Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-9-a-govindraju@ti.com --- include/configs/am64x_evm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 7c30e50c5f1..7c9bdc2d7d3 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -12,6 +12,7 @@ #include #include #include +#include /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 @@ -43,7 +44,7 @@ * location filled in by the boot ROM that we want to read out without any * interference from the C context. */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ +#define CONFIG_SPL_BSS_START_ADDR (TI_SRAM_SCRATCH_BOARD_EEPROM_START -\ CONFIG_SPL_BSS_MAX_SIZE) /* Set the stack right below the SPL BSS section */ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -- cgit v1.3.1 From ce7ad5739054a9b3a766e49e574905590753c329 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:40 +0530 Subject: configs: am64: Enable configs to support USB host and device modes Enable config options required to add support for USB Mass storage boot, USB DFU boot, host and device modes in U-Boot. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-11-a-govindraju@ti.com --- configs/am64x_evm_a53_defconfig | 39 +++++++++++++++++++++++++++++++++++++++ configs/am64x_evm_r5_defconfig | 36 ++++++++++++++++++++++++++++++++++-- include/configs/am64x_evm.h | 12 +++++++++++- 3 files changed, 84 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 8894ac1702d..fbce9e96748 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -23,6 +23,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm" CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -30,12 +31,17 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y @@ -102,3 +108,36 @@ CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_USB=y +CONFIG_DFU=y +CONFIG_DFU_OVER_USB=y +# CONFIG_DFU_TFTP is not set +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +# CONFIG_DFU_VIRT is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_TI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index de0c814222c..3e9b5650c60 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm" CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y @@ -31,19 +32,30 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -52,8 +64,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_IS_IN_FAT=y -CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y @@ -64,6 +74,10 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y @@ -101,4 +115,22 @@ CONFIG_CADENCE_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_TI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 7c9bdc2d7d3..c2c2bf06777 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -13,6 +13,7 @@ #include #include #include +#include /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 @@ -95,16 +96,25 @@ "${bootdir}/${name_fit}\0" \ "partitions=" PARTS_DEFAULT +#define EXTRA_ENV_DFUARGS \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_OSPI + /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM642_BOARD_SETTINGS \ - EXTRA_ENV_AM642_BOARD_SETTINGS_MMC + EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \ + EXTRA_ENV_DFUARGS /* Now for the remaining common defines */ #include +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 + /* MMC ENV related defines */ #ifdef CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -- cgit v1.3.1 From e61a4ff13f36a9952b4ecdfaa209963d411d2884 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 9 Mar 2021 21:19:15 +0100 Subject: Nokia RX-51: Enable CONFIG_WDT to remove deprecation warning Also convert CONFIG_HW_WATCHDOG to CONFIG_WATCHDOG. Signed-off-by: Pali Roh?r Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210309201915.16586-1-pali@kernel.org --- board/nokia/rx51/rx51.c | 37 +++++++++++++++++++++++++++++++++---- configs/nokia_rx51_defconfig | 2 ++ include/configs/nokia_rx51.h | 3 --- 3 files changed, 35 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 7bd5fbd7152..fd3cec8358a 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -487,20 +488,20 @@ static unsigned long int twl_wd_time; /* last time of watchdog reset */ static unsigned long int twl_i2c_lock; /* - * Routine: hw_watchdog_reset + * Routine: rx51_watchdog_reset * Description: Reset timeout of twl4030 watchdog. */ -void hw_watchdog_reset(void) +static int rx51_watchdog_reset(struct udevice *dev) { u8 timeout = 0; /* do not reset watchdog too often - max every 4s */ if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ) - return; + return 0; /* localy lock twl4030 i2c bus */ if (test_and_set_bit(0, &twl_i2c_lock)) - return; + return 0; /* read actual watchdog timeout */ twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, @@ -517,8 +518,32 @@ void hw_watchdog_reset(void) /* localy unlock twl4030 i2c bus */ test_and_clear_bit(0, &twl_i2c_lock); + + return 0; +} + +static int rx51_watchdog_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + return 0; } +static int rx51_watchdog_probe(struct udevice *dev) +{ + return 0; +} + +static const struct wdt_ops rx51_watchdog_ops = { + .start = rx51_watchdog_start, + .reset = rx51_watchdog_reset, +}; + +U_BOOT_DRIVER(rx51_watchdog) = { + .name = "rx51_watchdog", + .id = UCLASS_WDT, + .ops = &rx51_watchdog_ops, + .probe = rx51_watchdog_probe, +}; + /* * TWL4030 keypad handler for cfb_console */ @@ -722,3 +747,7 @@ U_BOOT_DRVINFOS(rx51_i2c) = { { "i2c_omap", &rx51_i2c[1] }, { "i2c_omap", &rx51_i2c[2] }, }; + +U_BOOT_DRVINFOS(rx51_watchdog) = { + { "rx51_watchdog" }, +}; diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 3548aab0e16..061f5c357c4 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -67,4 +67,6 @@ CONFIG_CFB_CONSOLE=y CONFIG_CFB_CONSOLE_ANSI=y # CONFIG_VGA_AS_SINGLE_DEVICE is not set CONFIG_SPLASH_SCREEN=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=31000 +CONFIG_WDT=y # CONFIG_GZIP is not set diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 23368de624e..fe991ea0399 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -85,9 +85,6 @@ #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -/* Watchdog support */ -#define CONFIG_HW_WATCHDOG - /* * Framebuffer */ -- cgit v1.3.1 From 7d0f3fbb93cfebd7b5dc5635166e48ab998c4f82 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:02 +0300 Subject: lib: rational: copy the rational fraction lib routines from Linux Copy the best rational approximation calculation routines from Linux. Typical usecase for these routines is to calculate the M/N divider values for PLLs to reach a specific clock rate. This is based on linux kernel commit: "lib/math/rational.c: fix possible incorrect result from rational fractions helper" (sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881) Signed-off-by: Tero Kristo Reviewed-by: Tom Rini Signed-off-by: Tero Kristo --- include/linux/rational.h | 20 ++++++++++ lib/Kconfig | 7 ++++ lib/Makefile | 2 + lib/rational.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 128 insertions(+) create mode 100644 include/linux/rational.h create mode 100644 lib/rational.c (limited to 'include') diff --git a/include/linux/rational.h b/include/linux/rational.h new file mode 100644 index 00000000000..33f5f5fc3e3 --- /dev/null +++ b/include/linux/rational.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer + * + * helper functions when coping with rational numbers, + * e.g. when calculating optimum numerator/denominator pairs for + * pll configuration taking into account restricted register size + */ + +#ifndef _LINUX_RATIONAL_H +#define _LINUX_RATIONAL_H + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator); + +#endif /* _LINUX_RATIONAL_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 15019d2c658..ad0cd52edd8 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -674,6 +674,13 @@ config GENERATE_SMBIOS_TABLE See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in the devicetree. +config LIB_RATIONAL + bool "enable continued fraction calculation routines" + +config SPL_LIB_RATIONAL + bool "enable continued fraction calculation routines for SPL" + depends on SPL + endmenu config ASN1_COMPILER diff --git a/lib/Makefile b/lib/Makefile index b4795a62a0d..881034f4ae3 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/ obj-$(CONFIG_$(SPL_)LZMA) += lzma/ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o +obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o + obj-$(CONFIG_LIBAVB) += libavb/ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ diff --git a/lib/rational.c b/lib/rational.c new file mode 100644 index 00000000000..316db3b5901 --- /dev/null +++ b/lib/rational.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer + * Copyright (C) 2019 Trent Piepho + * + * helper functions when coping with rational numbers + */ + +#include +#include +#include + +/* + * calculate best rational approximation for a given fraction + * taking into account restricted register size, e.g. to find + * appropriate values for a pll with 5 bit denominator and + * 8 bit numerator register fields, trying to set up with a + * frequency ratio of 3.1415, one would say: + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator) +{ + /* n/d is the starting rational, which is continually + * decreased each iteration using the Euclidean algorithm. + * + * dp is the value of d from the prior iteration. + * + * n2/d2, n1/d1, and n0/d0 are our successively more accurate + * approximations of the rational. They are, respectively, + * the current, previous, and two prior iterations of it. + * + * a is current term of the continued fraction. + */ + unsigned long n, d, n0, d0, n1, d1, n2, d2; + n = given_numerator; + d = given_denominator; + n0 = d1 = 0; + n1 = d0 = 1; + + for (;;) { + unsigned long dp, a; + + if (d == 0) + break; + /* Find next term in continued fraction, 'a', via + * Euclidean algorithm. + */ + dp = d; + a = n / d; + d = n % d; + n = dp; + + /* Calculate the current rational approximation (aka + * convergent), n2/d2, using the term just found and + * the two prior approximations. + */ + n2 = n0 + a * n1; + d2 = d0 + a * d1; + + /* If the current convergent exceeds the maxes, then + * return either the previous convergent or the + * largest semi-convergent, the final term of which is + * found below as 't'. + */ + if ((n2 > max_numerator) || (d2 > max_denominator)) { + unsigned long t = min((max_numerator - n0) / n1, + (max_denominator - d0) / d1); + + /* This tests if the semi-convergent is closer + * than the previous convergent. + */ + if (2u * t > a || (2u * t == a && d0 * dp > d1 * d)) { + n1 = n0 + t * n1; + d1 = d0 + t * d1; + } + break; + } + n0 = n1; + n1 = n2; + d0 = d1; + d1 = d2; + } + *best_numerator = n1; + *best_denominator = d1; +} -- cgit v1.3.1 From 481d394e77915201e4ecc2d98e9cc2fbc3224991 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 11 Jun 2021 11:45:05 +0300 Subject: common: fit: Update board_fit_image_post_process() to pass fit and node_offset board_fit_image_post_process() passes only start and size of the image, but type of the image is not passed. So pass fit and node_offset, to derive information about image to be processed. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Signed-off-by: Tero Kristo --- arch/arm/mach-k3/security.c | 3 ++- arch/arm/mach-keystone/mon.c | 3 ++- arch/arm/mach-socfpga/board.c | 3 ++- board/ti/am335x/board.c | 3 ++- board/ti/am43xx/board.c | 3 ++- board/ti/am57xx/board.c | 3 ++- board/ti/dra7xx/evm.c | 3 ++- common/image-fit.c | 2 +- common/spl/spl_fit.c | 2 +- include/image.h | 5 ++++- 10 files changed, 20 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 66f90a5a34d..5b5ff9ba7b3 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -18,7 +18,8 @@ #include #include -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { struct ti_sci_handle *ti_sci = get_ti_sci_handle(); struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index 58995d73ac8..b863bab1969 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1) return result; } -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { int result = 0; void *image = *p_image; diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 650122fcd4f..36eecdc0577 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -103,7 +103,8 @@ __weak int board_fit_config_name_match(const char *name) #endif #if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS) -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) { if (socfpga_vendor_authentication(p_image, p_size)) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 5959ff73dc4..5c156a5d1d8 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -960,7 +960,8 @@ int board_fit_config_name_match(const char *name) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index e9febb95921..a71b588efcb 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -896,7 +896,8 @@ int embedded_dtb_select(void) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 05c26c74d9d..399a2e5d913 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -1199,7 +1199,8 @@ static int board_bootmode_has_emmc(void) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 05f251f7782..23e80059915 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/common/image-fit.c b/common/image-fit.c index e614643fe39..0c5a05948d1 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, /* perform any post-processing on the image data */ if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)) - board_fit_image_post_process(&buf, &size); + board_fit_image_post_process(fit, noffset, &buf, &size); len = (ulong)size; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index caddf511967..57d621d5b3c 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -320,7 +320,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, } if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)) - board_fit_image_post_process(&src, &length); + board_fit_image_post_process(fit, node, &src, &length); load_ptr = map_sysmem(load_addr, length); if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) { diff --git a/include/image.h b/include/image.h index 459685d4d43..0c24bf6f35f 100644 --- a/include/image.h +++ b/include/image.h @@ -1581,11 +1581,14 @@ int board_fit_config_name_match(const char *name); * into the FIT creation (i.e. the binary blobs would have been pre-processed * before being added to the FIT image). * + * @fit: pointer to fit image + * @node: offset of image node * @image: pointer to the image start pointer * @size: pointer to the image size * @return no return value (failure should be handled internally) */ -void board_fit_image_post_process(void **p_image, size_t *p_size); +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size); #define FDT_ERROR ((ulong)(-1)) -- cgit v1.3.1 From fc960cb6fb94c77d1245e7f39b49d7278f480d62 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:06 +0300 Subject: clk: fixed_rate: add API for directly registering fixed rate clocks Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by: Peng Fan Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk_fixed_rate.c | 45 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 48 insertions(+) (limited to 'include') diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 09f9ef26a42..325a9b2dcfb 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -9,6 +9,9 @@ #include #include +#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock" +#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock" + static ulong clk_fixed_rate_get_rate(struct clk *clk) { return to_clk_fixed_rate(clk->dev)->fixed_rate; @@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, clk->enable_count = 0; } +static ulong clk_fixed_rate_raw_get_rate(struct clk *clk) +{ + return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate; +} + +const struct clk_ops clk_fixed_rate_raw_ops = { + .get_rate = clk_fixed_rate_raw_get_rate, +}; + static int clk_fixed_rate_of_to_plat(struct udevice *dev) { clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev)); @@ -47,6 +59,32 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev) return 0; } +#if CONFIG_IS_ENABLED(CLK_CCF) +struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + ulong rate) +{ + struct clk *clk; + struct clk_fixed_rate *fixed; + int ret; + + fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return ERR_PTR(-ENOMEM); + + fixed->fixed_rate = rate; + + clk = &fixed->clk; + + ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL); + if (ret) { + kfree(fixed); + return ERR_PTR(ret); + } + + return clk; +} +#endif + static const struct udevice_id clk_fixed_rate_match[] = { { .compatible = "fixed-clock", @@ -63,3 +101,10 @@ U_BOOT_DRIVER(fixed_clock) = { .ops = &clk_fixed_rate_ops, .flags = DM_FLAG_PRE_RELOC, }; + +U_BOOT_DRIVER(clk_fixed_rate_raw) = { + .name = UBOOT_DM_CLK_FIXED_RATE_RAW, + .id = UCLASS_CLK, + .ops = &clk_fixed_rate_raw_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 6fda14f5fe6..9d296f240a4 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags); +struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + ulong rate); + const char *clk_hw_get_name(const struct clk *hw); ulong clk_generic_get_rate(struct clk *clk); -- cgit v1.3.1 From 0aa2930ca192a8738d1da8222fc6ac21d7c19182 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:13 +0300 Subject: clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/ti/Kconfig | 12 ++ drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-k3-pll.c | 283 ++++++++++++++++++++++++++++++++++++++++++++ include/k3-clk.h | 15 +++ 4 files changed, 311 insertions(+) create mode 100644 drivers/clk/ti/clk-k3-pll.c create mode 100644 include/k3-clk.h (limited to 'include') diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig index 2dc86d44a98..a8ec4f541a4 100644 --- a/drivers/clk/ti/Kconfig +++ b/drivers/clk/ti/Kconfig @@ -41,3 +41,15 @@ config CLK_TI_SCI This enables the clock driver support over TI System Control Interface available on some new TI's SoCs. If you wish to use clock resources managed by the TI System Controller, say Y here. Otherwise, say N. + +config CLK_K3_PLL + bool "PLL clock support for K3 SoC family of devices" + depends on CLK && LIB_RATIONAL + help + Enables PLL clock support for K3 SoC family of devices. + +config SPL_CLK_K3_PLL + bool "PLL clock support for K3 SoC family of devices" + depends on CLK && LIB_RATIONAL && SPL + help + Enables PLL clock support for K3 SoC family of devices. diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 9f56b477360..47839213e58 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o +obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c new file mode 100644 index 00000000000..bf2407a020a --- /dev/null +++ b/drivers/clk/ti/clk-k3-pll.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 SoC PLL clock driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include "k3-clk.h" +#include + +/* 16FFT register offsets */ +#define PLL_16FFT_CFG 0x08 +#define PLL_KICK0 0x10 +#define PLL_KICK1 0x14 +#define PLL_16FFT_CTRL 0x20 +#define PLL_16FFT_STAT 0x24 +#define PLL_16FFT_FREQ_CTRL0 0x30 +#define PLL_16FFT_FREQ_CTRL1 0x34 +#define PLL_16FFT_DIV_CTRL 0x38 + +/* CTRL register bits */ +#define PLL_16FFT_CTRL_BYPASS_EN BIT(31) +#define PLL_16FFT_CTRL_PLL_EN BIT(15) +#define PLL_16FFT_CTRL_DSM_EN BIT(1) + +/* STAT register bits */ +#define PLL_16FFT_STAT_LOCK BIT(0) + +/* FREQ_CTRL0 bits */ +#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff + +/* DIV CTRL register bits */ +#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f + +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 +#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15) + +/* KICK register magic values */ +#define PLL_KICK0_VALUE 0x68ef3490 +#define PLL_KICK1_VALUE 0xd172bc5a + +/** + * struct ti_pll_clk - TI PLL clock data info structure + * @clk: core clock structure + * @reg: memory address of the PLL controller + */ +struct ti_pll_clk { + struct clk clk; + void __iomem *reg; +}; + +#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk) + +static int ti_pll_wait_for_lock(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 stat; + int i; + + for (i = 0; i < 100000; i++) { + stat = readl(pll->reg + PLL_16FFT_STAT); + if (stat & PLL_16FFT_STAT_LOCK) + return 0; + } + + printf("%s: pll (%s) failed to lock\n", __func__, + clk->dev->name); + + return -EBUSY; +} + +static ulong ti_pll_clk_get_rate(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u64 current_freq; + u64 parent_freq = clk_get_parent_rate(clk); + u32 pllm; + u32 plld; + u32 pllfm; + u32 ctrl; + + /* Check if we are in bypass */ + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + if (ctrl & PLL_16FFT_CTRL_BYPASS_EN) + return parent_freq; + + pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0); + pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1); + + plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) & + PLL_16FFT_DIV_CTRL_REF_DIV_MASK; + + current_freq = parent_freq * pllm / plld; + + if (pllfm) { + u64 tmp; + + tmp = parent_freq * pllfm; + do_div(tmp, plld); + tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS; + current_freq += tmp; + } + + return current_freq; +} + +static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u64 current_freq; + u64 parent_freq = clk_get_parent_rate(clk); + int ret; + u32 ctrl; + unsigned long pllm; + u32 pllfm = 0; + unsigned long plld; + u32 rem; + int shift; + + debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate); + + if (ti_pll_clk_get_rate(clk) == rate) + return rate; + + if (rate != parent_freq) + /* + * Attempt with higher max multiplier value first to give + * some space for fractional divider to kick in. + */ + for (shift = 8; shift >= 0; shift -= 8) { + rational_best_approximation(rate, parent_freq, + ((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1, + PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld); + if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK) + break; + } + + /* Put PLL to bypass mode */ + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl |= PLL_16FFT_CTRL_BYPASS_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + if (rate == parent_freq) { + debug("%s: put %s to bypass\n", __func__, clk->dev->name); + return rate; + } + + debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n", + __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm); + + /* Check if we need fractional config */ + if (plld > 1) { + pllfm = pllm % plld; + pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS; + rem = pllfm % plld; + pllfm /= plld; + if (rem) + pllfm++; + pllm /= plld; + plld = 1; + } + + if (pllfm) + ctrl |= PLL_16FFT_CTRL_DSM_EN; + else + ctrl &= ~PLL_16FFT_CTRL_DSM_EN; + + writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0); + writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1); + writel(plld, pll->reg + PLL_16FFT_DIV_CTRL); + + ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; + ctrl |= PLL_16FFT_CTRL_PLL_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + ret = ti_pll_wait_for_lock(clk); + if (ret) + return ret; + + debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n", + __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq); + + current_freq = parent_freq * pllm / plld; + + if (pllfm) { + u64 tmp; + + tmp = parent_freq * pllfm; + do_div(tmp, plld); + tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS; + current_freq += tmp; + } + + return current_freq; +} + +static int ti_pll_clk_enable(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 ctrl; + + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; + ctrl |= PLL_16FFT_CTRL_PLL_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + return ti_pll_wait_for_lock(clk); +} + +static int ti_pll_clk_disable(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 ctrl; + + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl |= PLL_16FFT_CTRL_BYPASS_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + return 0; +} + +static const struct clk_ops ti_pll_clk_ops = { + .get_rate = ti_pll_clk_get_rate, + .set_rate = ti_pll_clk_set_rate, + .enable = ti_pll_clk_enable, + .disable = ti_pll_clk_disable, +}; + +struct clk *clk_register_ti_pll(const char *name, const char *parent_name, + void __iomem *reg) +{ + struct ti_pll_clk *pll; + int ret; + int i; + u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->reg = reg; + + ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name); + if (ret) { + printf("%s: failed to register: %d\n", __func__, ret); + kfree(pll); + return ERR_PTR(ret); + } + + /* Unlock the PLL registers */ + writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0); + writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1); + + /* Enable all HSDIV outputs */ + cfg = readl(pll->reg + PLL_16FFT_CFG); + for (i = 0; i < 16; i++) { + hsdiv_presence_bit = BIT(16 + i); + hsdiv_ctrl_offs = 0x80 + (i * 4); + /* Enable HSDIV output if present */ + if ((hsdiv_presence_bit & cfg) != 0UL) { + ctrl = readl(pll->reg + hsdiv_ctrl_offs); + ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN; + writel(ctrl, pll->reg + hsdiv_ctrl_offs); + } + } + + return &pll->clk; +} + +U_BOOT_DRIVER(ti_pll_clk) = { + .name = "ti-pll-clk", + .id = UCLASS_CLK, + .ops = &ti_pll_clk_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/k3-clk.h b/include/k3-clk.h new file mode 100644 index 00000000000..fc84378d03f --- /dev/null +++ b/include/k3-clk.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com + * Tero Kristo + */ + +#ifndef __K3_CLK_H__ +#define __K3_CLK_H__ + +#include + +struct clk *clk_register_ti_pll(const char *name, const char *parent_name, + void __iomem *reg); + +#endif /* __K3_CLK_H__ */ -- cgit v1.3.1 From b4a72a9f5b805b438312fd239fc8bfffd8f7b771 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:14 +0300 Subject: clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/ti/Kconfig | 12 ++ drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-k3.c | 374 ++++++++++++++++++++++++++++++++++++++++++++++++ include/k3-clk.h | 161 +++++++++++++++++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/clk/ti/clk-k3.c (limited to 'include') diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig index a8ec4f541a4..fbcdefd889a 100644 --- a/drivers/clk/ti/Kconfig +++ b/drivers/clk/ti/Kconfig @@ -53,3 +53,15 @@ config SPL_CLK_K3_PLL depends on CLK && LIB_RATIONAL && SPL help Enables PLL clock support for K3 SoC family of devices. + +config CLK_K3 + bool "Clock support for K3 SoC family of devices" + depends on CLK + help + Enables the clock translation layer from DT to device clocks. + +config SPL_CLK_K3 + bool "Clock support for K3 SoC family of devices" + depends on CLK && SPL + help + Enables the clock translation layer from DT to device clocks. diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 47839213e58..07aa9a53e08 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o +obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c new file mode 100644 index 00000000000..e921894e7a2 --- /dev/null +++ b/drivers/clk/ti/clk-k3.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 clock driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include "k3-clk.h" + +#define PLL_MIN_FREQ 800000000 +#define PLL_MAX_FREQ 3200000000UL +#define PLL_MAX_DIV 127 + +/** + * struct clk_map - mapping from dev/clk id tuples towards physical clocks + * @dev_id: device ID for the clock + * @clk_id: clock ID for the clock + * @clk: pointer to the registered clock entry for the mapping + */ +struct clk_map { + u16 dev_id; + u32 clk_id; + struct clk *clk; +}; + +/** + * struct ti_clk_data - clock controller information structure + * @map: mapping from dev/clk id tuples to physical clock entries + * @size: number of entries in the map + */ +struct ti_clk_data { + struct clk_map *map; + int size; +}; + +static ulong osc_freq; + +static void clk_add_map(struct ti_clk_data *data, struct clk *clk, + u32 dev_id, u32 clk_id) +{ + struct clk_map *map; + + debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__, + clk, data, dev_id, clk_id); + if (!clk) + return; + + map = data->map + data->size++; + + map->dev_id = dev_id; + map->clk_id = clk_id; + map->clk = clk; +} + +static const struct soc_attr ti_k3_soc_clk_data[] = { +#if IS_ENABLED(CONFIG_SOC_K3_J721E) + { + .family = "J721E", + .data = &j721e_clk_platdata, + }, + { + .family = "J7200", + .data = &j7200_clk_platdata, + }, +#endif + { /* sentinel */ } +}; + +static int ti_clk_probe(struct udevice *dev) +{ + struct ti_clk_data *data = dev_get_priv(dev); + struct clk *clk; + const char *name; + const struct clk_data *ti_clk_data; + int i, j; + const struct soc_attr *soc_match_data; + const struct ti_k3_clk_platdata *pdata; + + debug("%s(dev=%p)\n", __func__, dev); + + soc_match_data = soc_device_match(ti_k3_soc_clk_data); + if (!soc_match_data) + return -ENODEV; + + pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data; + + data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map), + GFP_KERNEL); + data->size = 0; + + for (i = 0; i < pdata->clk_list_cnt; i++) { + ti_clk_data = &pdata->clk_list[i]; + + switch (ti_clk_data->type) { + case CLK_TYPE_FIXED_RATE: + name = ti_clk_data->clk.fixed_rate.name; + clk = clk_register_fixed_rate(NULL, + name, + ti_clk_data->clk.fixed_rate.rate); + break; + case CLK_TYPE_DIV: + name = ti_clk_data->clk.div.name; + clk = clk_register_divider(NULL, name, + ti_clk_data->clk.div.parent, + ti_clk_data->clk.div.flags, + map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE), + ti_clk_data->clk.div.shift, + ti_clk_data->clk.div.width, + 0); + break; + case CLK_TYPE_MUX: + name = ti_clk_data->clk.mux.name; + clk = clk_register_mux(NULL, name, + ti_clk_data->clk.mux.parents, + ti_clk_data->clk.mux.num_parents, + ti_clk_data->clk.mux.flags, + map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE), + ti_clk_data->clk.mux.shift, + ti_clk_data->clk.mux.width, + 0); + break; + case CLK_TYPE_PLL: + name = ti_clk_data->clk.pll.name; + clk = clk_register_ti_pll(name, + ti_clk_data->clk.pll.parent, + map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE)); + + if (!osc_freq) + osc_freq = clk_get_rate(clk_get_parent(clk)); + break; + default: + name = NULL; + clk = NULL; + printf("WARNING: %s has encountered unknown clk type %d\n", + __func__, ti_clk_data->type); + } + + if (clk && ti_clk_data->default_freq) + clk_set_rate(clk, ti_clk_data->default_freq); + + if (clk && name) { + for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) { + if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) { + clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id, + pdata->soc_dev_clk_data[j].clk_id); + } + } + } + } + + return 0; +} + +static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map) +{ + if (map->dev_id == dev_id && map->clk_id == clk_id) + return 0; + if (map->dev_id > dev_id || + (map->dev_id == dev_id && map->clk_id > clk_id)) + return -1; + return 1; +} + +static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num) +{ + int result; + int idx; + + for (idx = 0; idx < num; idx++) { + result = _clk_cmp(dev_id, clk_id, &map[idx]); + + if (result == 0) + return idx; + } + + return -ENOENT; +} + +static int ti_clk_of_xlate(struct clk *clk, + struct ofnode_phandle_args *args) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + int idx; + + debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk, + args->args_count, args->args[0], args->args[1]); + + if (args->args_count != 2) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (!data->size) + return -EPROBE_DEFER; + + idx = bsearch(args->args[0], args->args[1], data->map, data->size); + if (idx < 0) + return idx; + + clk->id = idx; + + return 0; +} + +static ulong ti_clk_get_rate(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_get_rate(clkp); +} + +static ulong ti_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + int div = 1; + ulong child_rate; + const struct clk_ops *ops; + ulong new_rate, rem; + ulong diff, new_diff; + + /* + * We must propagate rate change to parent if current clock type + * does not allow setting it. + */ + while (clkp) { + ops = clkp->dev->driver->ops; + if (ops->set_rate) + break; + + /* + * Store child rate so we can calculate the clock rate + * that must be passed to parent + */ + child_rate = clk_get_rate(clkp); + clkp = clk_get_parent(clkp); + if (clkp) { + debug("%s: propagating rate change to parent %s, rate=%u.\n", + __func__, clkp->dev->name, (u32)rate / div); + div *= clk_get_rate(clkp) / child_rate; + } + } + + if (!clkp) + return -ENOSYS; + + child_rate = clk_get_rate(clkp); + + new_rate = clk_set_rate(clkp, rate / div); + + diff = abs(new_rate - rate / div); + + debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__, + clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff); + + /* + * If the new rate differs by 50% of the target, + * modify parent. This handles typical cases where we have a hsdiv + * following directly a PLL + */ + + if (diff > rate / div / 2) { + ulong pll_tgt; + int pll_div = 0; + + clk = clkp; + + debug("%s: propagating rate change to parent, rate=%u.\n", + __func__, (u32)rate / div); + + clkp = clk_get_parent(clkp); + + if (rate > osc_freq) { + if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) { + pll_tgt = rate; + pll_div = 1; + } else { + for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) { + pll_tgt = rate / div * pll_div; + if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ) + break; + } + } + } else { + pll_tgt = osc_freq; + pll_div = rate / div / osc_freq; + } + + debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__, + (u32)pll_tgt, (u32)rate, pll_div); + + clk_set_rate(clkp, pll_tgt); + + return clk_set_rate(clk, rate / div) * div; + } + + /* + * If the new rate differs by at least 5% of the target, + * we must check for rounding error in a divider, so try + * set rate with rate + (parent_freq % rate). + */ + + if (diff > rate / div / 20) { + u64 parent_freq = clk_get_parent_rate(clkp); + + rem = parent_freq % rate; + new_rate = clk_set_rate(clkp, (rate / div) + rem); + new_diff = abs(new_rate - rate / div); + + if (new_diff > diff) { + new_rate = clk_set_rate(clkp, rate / div); + } else { + debug("%s: Using better rate %lu that gives diff %lu\n", + __func__, new_rate, new_diff); + } + } + + return new_rate; +} + +static int ti_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + struct clk *parentp = data->map[parent->id].clk; + + return clk_set_parent(clkp, parentp); +} + +static int ti_clk_enable(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_enable(clkp); +} + +static int ti_clk_disable(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_disable(clkp); +} + +static const struct udevice_id ti_clk_of_match[] = { + { .compatible = "ti,k2g-sci-clk" }, + { /* sentinel */ }, +}; + +static const struct clk_ops ti_clk_ops = { + .of_xlate = ti_clk_of_xlate, + .set_rate = ti_clk_set_rate, + .get_rate = ti_clk_get_rate, + .enable = ti_clk_enable, + .disable = ti_clk_disable, + .set_parent = ti_clk_set_parent, +}; + +U_BOOT_DRIVER(ti_clk) = { + .name = "ti-clk", + .id = UCLASS_CLK, + .of_match = ti_clk_of_match, + .probe = ti_clk_probe, + .priv_auto = sizeof(struct ti_clk_data), + .ops = &ti_clk_ops, +}; diff --git a/include/k3-clk.h b/include/k3-clk.h index fc84378d03f..07352285798 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -7,7 +7,168 @@ #ifndef __K3_CLK_H__ #define __K3_CLK_H__ +#include +#include #include +#include +#include + +struct dev_clk { + int dev_id; + int clk_id; + const char *clk_name; +}; + +#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \ + .clk_id = _clk_id, .clk_name = _clk_name, } + +#define CLK_TYPE_MUX 0x01 +#define CLK_TYPE_DIV 0x02 +#define CLK_TYPE_PLL 0x03 +#define CLK_TYPE_HFOSC 0x04 +#define CLK_TYPE_POSTDIV 0x05 +#define CLK_TYPE_MUX_PLLCTRL 0x06 +#define CLK_TYPE_FIXED_RATE 0x07 + +struct pll_data { + u32 reg; + const char *name; + const char *parent; + u32 flags; +}; + +struct mux_data { + u32 reg; + const char *name; + const char * const *parents; + int num_parents; + u32 flags; + int shift; + int width; +}; + +struct div_data { + u32 reg; + const char *name; + const char *parent; + u32 flags; + int shift; + int width; +}; + +struct hfosc_data { + const char *name; + u32 flags; +}; + +struct fixed_rate_data { + const char *name; + u64 rate; + u32 flags; +}; + +struct postdiv_data { + const char *name; + const char *parent; + int width; + u32 flags; +}; + +struct mux_pllctrl_data { + u32 reg; + const char *name; + const char * const *parents; + int num_parents; + u32 flags; +}; + +struct clk_data { + int type; + u32 default_freq; + union { + struct pll_data pll; + struct mux_data mux; + struct div_data div; + struct hfosc_data hfosc; + struct postdiv_data postdiv; + struct mux_pllctrl_data mux_pllctrl; + struct fixed_rate_data fixed_rate; + } clk; +}; + +#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \ + { \ + .type = CLK_TYPE_MUX, \ + .clk.mux = { .name = _name, .parents = _parents, \ + .reg = _reg, \ + .num_parents = _num_parents, .shift = _shift, \ + .width = _width, .flags = _flags } \ + } + +#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \ + { \ + .type = CLK_TYPE_DIV, \ + .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \ + } + +#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \ + { \ + .type = CLK_TYPE_DIV, \ + .default_freq = _freq, \ + .clk.div = { \ + .name = _name, .parent = _parent, \ + .reg = _reg, .shift = _shift, \ + .width = _width, .flags = _flags } \ + } + +#define CLK_PLL(_name, _parent, _reg, _flags) \ + { \ + .type = CLK_TYPE_PLL, \ + .clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \ + } + +#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \ + { \ + .type = CLK_TYPE_PLL, \ + .default_freq = _freq, \ + .clk.pll = { .name = _name, .parent = _parent, \ + .reg = _reg, .flags = _flags } \ + } + +#define CLK_HFOSC(_name, _flags) \ + { \ + .type = CLK_TYPE_HFOSC, \ + .clk.hfosc = { .name = _name, .flags = _flags } \ + } + +#define CLK_FIXED_RATE(_name, _rate, _flags) \ + { \ + .type = CLK_TYPE_FIXED_RATE, \ + .clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \ + } + +#define CLK_POSTDIV(_name, _parent, _width, _flags) \ + { \ + .type = CLK_TYPE_POSTDIV, \ + .clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \ + } + +#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \ + { \ + .type = CLK_TYPE_MUX, \ + .clk.mux_pllctrl = { .name = _name, .parents = _parents,\ + .num_parents = _num_parents, .flags = _flags } \ + } + +struct ti_k3_clk_platdata { + const struct clk_data *clk_list; + int clk_list_cnt; + const struct dev_clk *soc_dev_clk_data; + int soc_dev_clk_data_cnt; +}; + +extern const struct ti_k3_clk_platdata j721e_clk_platdata; +extern const struct ti_k3_clk_platdata j7200_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); -- cgit v1.3.1 From 144464bd2c67a1f11e8dd4fb4a18b45b666dc1c4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:15 +0300 Subject: power: domain: Introduce driver for raw TI K3 PDs Normally, power domains are handled via TI-SCI in K3 SoCs. However, SPL is not going to have access to sysfw resources, so it must control them directly. Add driver for supporting this. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo Reviewed-by: Jaehoon Chung --- drivers/power/domain/Kconfig | 7 + drivers/power/domain/Makefile | 1 + drivers/power/domain/ti-power-domain.c | 368 +++++++++++++++++++++++++++++++++ include/k3-dev.h | 76 +++++++ 4 files changed, 452 insertions(+) create mode 100644 drivers/power/domain/ti-power-domain.c create mode 100644 include/k3-dev.h (limited to 'include') diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index a0fd9807529..99b3f9ae71b 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN help Generic power domain implementation for TI devices implementing the TI SCI protocol. + +config TI_POWER_DOMAIN + bool "Enable the TI K3 Power domain driver" + depends on POWER_DOMAIN && ARCH_K3 + help + Generic power domain implementation for TI K3 devices. + endmenu diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 45bf9f63834..3d1e5f073cb 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o +obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c new file mode 100644 index 00000000000..56bc6fc31c5 --- /dev/null +++ b/drivers/power/domain/ti-power-domain.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments power domain driver + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PSC_PTCMD 0x120 +#define PSC_PTSTAT 0x128 +#define PSC_PDSTAT 0x200 +#define PSC_PDCTL 0x300 +#define PSC_MDSTAT 0x800 +#define PSC_MDCTL 0xa00 + +#define PDCTL_STATE_MASK 0x1 +#define PDCTL_STATE_OFF 0x0 +#define PDCTL_STATE_ON 0x1 + +#define MDSTAT_STATE_MASK 0x3f +#define MDSTAT_BUSY_MASK 0x30 +#define MDSTAT_STATE_SWRSTDISABLE 0x0 +#define MDSTAT_STATE_ENABLE 0x3 + +#define LPSC_TIMEOUT 1000 +#define PD_TIMEOUT 1000 + +static u32 psc_read(struct ti_psc *psc, u32 reg) +{ + u32 val; + + val = readl(psc->base + reg); + debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg); + return val; +} + +static void psc_write(u32 val, struct ti_psc *psc, u32 reg) +{ + debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg); + writel(val, psc->base + reg); +} + +static u32 pd_read(struct ti_pd *pd, u32 reg) +{ + return psc_read(pd->psc, reg + 4 * pd->id); +} + +static void pd_write(u32 val, struct ti_pd *pd, u32 reg) +{ + psc_write(val, pd->psc, reg + 4 * pd->id); +} + +static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg) +{ + return psc_read(lpsc->psc, reg + 4 * lpsc->id); +} + +static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg) +{ + psc_write(val, lpsc->psc, reg + 4 * lpsc->id); +} + +static const struct soc_attr ti_k3_soc_pd_data[] = { +#if IS_ENABLED(CONFIG_SOC_K3_J721E) + { + .family = "J721E", + .data = &j721e_pd_platdata, + }, + { + .family = "J7200", + .data = &j7200_pd_platdata, + }, +#endif + { /* sentinel */ } +}; + +static int ti_power_domain_probe(struct udevice *dev) +{ + struct ti_k3_pd_platdata *data = dev_get_priv(dev); + const struct soc_attr *soc_match_data; + const struct ti_k3_pd_platdata *pdata; + + printf("%s(dev=%p)\n", __func__, dev); + + if (!data) + return -ENOMEM; + + soc_match_data = soc_device_match(ti_k3_soc_pd_data); + if (!soc_match_data) + return -ENODEV; + + pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data; + + data->psc = pdata->psc; + data->pd = pdata->pd; + data->lpsc = pdata->lpsc; + data->devs = pdata->devs; + data->num_psc = pdata->num_psc; + data->num_pd = pdata->num_pd; + data->num_lpsc = pdata->num_lpsc; + data->num_devs = pdata->num_devs; + + return 0; +} + +static int ti_pd_wait(struct ti_pd *pd) +{ + u32 ptstat; + int ret; + + ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat, + !(ptstat & BIT(pd->id)), PD_TIMEOUT); + + if (ret) + printf("%s: psc%d, pd%d failed to transition.\n", __func__, + pd->psc->id, pd->id); + + return ret; +} + +static void ti_pd_transition(struct ti_pd *pd) +{ + psc_write(BIT(pd->id), pd->psc, PSC_PTCMD); +} + +static u8 ti_pd_state(struct ti_pd *pd) +{ + return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK; +} + +static int ti_pd_get(struct ti_pd *pd) +{ + u32 pdctl; + int ret; + + pd->usecount++; + + if (pd->usecount > 1) + return 0; + + if (pd->depend) { + ret = ti_pd_get(pd->depend); + if (ret) + return ret; + ti_pd_transition(pd->depend); + ret = ti_pd_wait(pd->depend); + if (ret) + return ret; + } + + pdctl = pd_read(pd, PSC_PDCTL); + + if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON) + return 0; + + debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id); + + pdctl &= ~PDCTL_STATE_MASK; + pdctl |= PDCTL_STATE_ON; + + pd_write(pdctl, pd, PSC_PDCTL); + + return 0; +} + +static int ti_pd_put(struct ti_pd *pd) +{ + u32 pdctl; + int ret; + + pd->usecount--; + + if (pd->usecount > 0) + return 0; + + pdctl = pd_read(pd, PSC_PDCTL); + if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF) + return 0; + + pdctl &= ~PDCTL_STATE_MASK; + pdctl |= PDCTL_STATE_OFF; + + debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id); + + pd_write(pdctl, pd, PSC_PDCTL); + + if (pd->depend) { + ti_pd_transition(pd); + ret = ti_pd_wait(pd); + if (ret) + return ret; + + ret = ti_pd_put(pd->depend); + if (ret) + return ret; + ti_pd_transition(pd->depend); + ret = ti_pd_wait(pd->depend); + if (ret) + return ret; + } + + return 0; +} + +static int ti_lpsc_wait(struct ti_lpsc *lpsc) +{ + u32 mdstat; + int ret; + + ret = readl_poll_timeout(lpsc->psc->base + PSC_MDSTAT + lpsc->id * 4, + mdstat, + !(mdstat & MDSTAT_BUSY_MASK), LPSC_TIMEOUT); + + if (ret) + printf("%s: module %d failed to transition.\n", __func__, + lpsc->id); + + return ret; +} + +static u8 lpsc_get_state(struct ti_lpsc *lpsc) +{ + return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK; +} + +static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) +{ + struct ti_pd *psc_pd; + int ret; + u32 mdctl; + + psc_pd = lpsc->pd; + + if (state == MDSTAT_STATE_ENABLE) { + lpsc->usecount++; + if (lpsc->usecount > 1) + return 0; + } else { + lpsc->usecount--; + if (lpsc->usecount >= 1) + return 0; + } + + debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__, + lpsc->psc->id, lpsc->id, state); + + if (lpsc->depend) + ti_lpsc_transition(lpsc->depend, state); + + mdctl = lpsc_read(lpsc, PSC_MDCTL); + if ((mdctl & MDSTAT_STATE_MASK) == state) + return 0; + + if (state == MDSTAT_STATE_ENABLE) + ti_pd_get(psc_pd); + else + ti_pd_put(psc_pd); + + mdctl &= ~MDSTAT_STATE_MASK; + mdctl |= state; + + lpsc_write(mdctl, lpsc, PSC_MDCTL); + + ti_pd_transition(psc_pd); + ret = ti_pd_wait(psc_pd); + if (ret) + return ret; + + return ti_lpsc_wait(lpsc); +} + +static int ti_power_domain_transition(struct power_domain *pd, u8 state) +{ + struct ti_lpsc *lpsc = pd->priv; + + return ti_lpsc_transition(lpsc, state); +} + +static int ti_power_domain_on(struct power_domain *pd) +{ + debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id); + + return ti_power_domain_transition(pd, MDSTAT_STATE_ENABLE); +} + +static int ti_power_domain_off(struct power_domain *pd) +{ + debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id); + + return ti_power_domain_transition(pd, MDSTAT_STATE_SWRSTDISABLE); +} + +static struct ti_lpsc *lpsc_lookup(struct ti_k3_pd_platdata *data, int id) +{ + int idx; + + for (idx = 0; idx < data->num_devs; idx++) + if (data->devs[idx].id == id) + return data->devs[idx].lpsc; + + return NULL; +} + +static int ti_power_domain_of_xlate(struct power_domain *pd, + struct ofnode_phandle_args *args) +{ + struct ti_k3_pd_platdata *data = dev_get_priv(pd->dev); + struct ti_lpsc *lpsc; + + debug("%s(power_domain=%p, id=%d)\n", __func__, pd, args->args[0]); + + if (args->args_count < 1) { + printf("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + lpsc = lpsc_lookup(data, args->args[0]); + if (!lpsc) { + printf("%s: invalid dev-id: %d\n", __func__, args->args[0]); + return -ENOENT; + } + + pd->id = lpsc->id; + pd->priv = lpsc; + + return 0; +} + +static int ti_power_domain_request(struct power_domain *pd) +{ + return 0; +} + +static int ti_power_domain_free(struct power_domain *pd) +{ + return 0; +} + +static const struct udevice_id ti_power_domain_of_match[] = { + { .compatible = "ti,sci-pm-domain" }, + { /* sentinel */ } +}; + +static struct power_domain_ops ti_power_domain_ops = { + .on = ti_power_domain_on, + .off = ti_power_domain_off, + .of_xlate = ti_power_domain_of_xlate, + .request = ti_power_domain_request, + .rfree = ti_power_domain_free, +}; + +U_BOOT_DRIVER(ti_pm_domains) = { + .name = "ti-pm-domains", + .id = UCLASS_POWER_DOMAIN, + .of_match = ti_power_domain_of_match, + .probe = ti_power_domain_probe, + .priv_auto = sizeof(struct ti_k3_pd_platdata), + .ops = &ti_power_domain_ops, +}; diff --git a/include/k3-dev.h b/include/k3-dev.h new file mode 100644 index 00000000000..de3a8bdf9eb --- /dev/null +++ b/include/k3-dev.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments K3 Device Platform Data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef __K3_DEV_H__ +#define __K3_DEV_H__ + +#include +#include +#include + +#define LPSC_MODULE_EXISTS BIT(0) +#define LPSC_NO_CLOCK_GATING BIT(1) +#define LPSC_DEPENDS BIT(2) +#define LPSC_HAS_RESET_ISO BIT(3) +#define LPSC_HAS_LOCAL_RESET BIT(4) +#define LPSC_NO_MODULE_RESET BIT(5) + +#define PSC_PD_EXISTS BIT(0) +#define PSC_PD_ALWAYSON BIT(1) +#define PSC_PD_DEPENDS BIT(2) + +struct ti_psc { + int id; + void __iomem *base; +}; + +struct ti_pd; + +struct ti_pd { + int id; + int usecount; + struct ti_psc *psc; + struct ti_pd *depend; +}; + +struct ti_lpsc; + +struct ti_lpsc { + int id; + int usecount; + struct ti_psc *psc; + struct ti_pd *pd; + struct ti_lpsc *depend; +}; + +struct ti_dev { + struct ti_lpsc *lpsc; + int id; +}; + +/** + * struct ti_k3_pd_platdata - pm domain controller information structure + */ +struct ti_k3_pd_platdata { + struct ti_psc *psc; + struct ti_pd *pd; + struct ti_lpsc *lpsc; + struct ti_dev *devs; + int num_psc; + int num_pd; + int num_lpsc; + int num_devs; +}; + +#define PSC(_id, _base) { .id = _id, .base = (void *)_base, } +#define PSC_PD(_id, _psc, _depend) { .id = _id, .psc = _psc, .depend = _depend } +#define PSC_LPSC(_id, _psc, _pd, _depend) { .id = _id, .psc = _psc, .pd = _pd, .depend = _depend } +#define PSC_DEV(_id, _lpsc) { .id = _id, .lpsc = _lpsc } + +extern const struct ti_k3_pd_platdata j721e_pd_platdata; +extern const struct ti_k3_pd_platdata j7200_pd_platdata; + +#endif -- cgit v1.3.1 From f79753c3defb15c037e4e8be6235b2a37a8b56d4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:16 +0300 Subject: cmd: ti: pd: Add debug command for K3 power domains Add support command for debugging K3 power domains. This is useful with the HSM rearch setup, where power domains are directly controlled by SPL instead of going through the TI SCI layer. The debugging support is only available in the u-boot codebase though, so the raw register access power domain layer must be enabled on u-boot side for this to work. By default, u-boot side uses the TI SCI layer, and R5 SPL only uses the direct access methods. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo Reviewed-by: Jaehoon Chung --- cmd/ti/Kconfig | 8 ++ cmd/ti/Makefile | 1 + cmd/ti/pd.c | 185 +++++++++++++++++++++++++++++++++ drivers/power/domain/ti-power-domain.c | 6 +- include/k3-dev.h | 9 ++ 5 files changed, 206 insertions(+), 3 deletions(-) create mode 100644 cmd/ti/pd.c (limited to 'include') diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig index efeff0d4823..db557445a89 100644 --- a/cmd/ti/Kconfig +++ b/cmd/ti/Kconfig @@ -7,4 +7,12 @@ config CMD_DDR3 supports memory verification, memory comapre and ecc verification if supported. +config CMD_PD + bool "command for verifying power domains" + depends on TI_POWER_DOMAIN + help + Debug command for K3 power domains. For this to work, the + K3 power domain driver must be enabled for the u-boot; by + default it is only enabled for SPL. + endmenu diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile index 16fbade9edd..045593396b7 100644 --- a/cmd/ti/Makefile +++ b/cmd/ti/Makefile @@ -5,4 +5,5 @@ obj- += dummy.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_DDR3) += ddr3.o +obj-$(CONFIG_CMD_PD) += pd.o endif diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c new file mode 100644 index 00000000000..9e820b84ca3 --- /dev/null +++ b/cmd/ti/pd.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Power Domain test commands + * + * Copyright (C) 2020 Texas Instruments Incorporated, + */ + +#include +#include +#include +#include + +static const struct udevice_id ti_pd_of_match[] = { + { .compatible = "ti,sci-pm-domain" }, + { /* sentinel */ } +}; + +static struct ti_k3_pd_platdata *ti_pd_find_data(void) +{ + struct udevice *dev; + int i = 0; + + while (1) { + uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev); + if (!dev) + return NULL; + + if (device_is_compatible(dev, + ti_pd_of_match[0].compatible)) + return dev_get_priv(dev); + } + + return NULL; +} + +static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd) +{ + int i; + struct ti_lpsc *lpsc; + u8 state; + static const char * const lpsc_states[] = { + "swrstdis", "syncrst", "disable", "enable", "autosleep", + "autowake", "unknown", + }; + + for (i = 0; i < data->num_lpsc; i++) { + lpsc = &data->lpsc[i]; + if (lpsc->pd != pd) + continue; + state = lpsc_get_state(lpsc); + if (state > ARRAY_SIZE(lpsc_states)) + state = ARRAY_SIZE(lpsc_states) - 1; + printf(" LPSC%d: state=%s, usecount=%d\n", + lpsc->id, lpsc_states[state], lpsc->usecount); + } +} + +static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc) +{ + int i; + struct ti_pd *pd; + u8 state; + static const char * const pd_states[] = { + "off", "on", "unknown" + }; + + for (i = 0; i < data->num_pd; i++) { + pd = &data->pd[i]; + if (pd->psc != psc) + continue; + state = ti_pd_state(pd); + if (state > ARRAY_SIZE(pd_states)) + state = ARRAY_SIZE(pd_states) - 1; + printf(" PD%d: state=%s, usecount=%d:\n", + pd->id, pd_states[state], pd->usecount); + dump_lpsc(data, pd); + } +} + +static void dump_psc(struct ti_k3_pd_platdata *data) +{ + int i; + struct ti_psc *psc; + + for (i = 0; i < data->num_psc; i++) { + psc = &data->psc[i]; + printf("PSC%d [%p]:\n", psc->id, psc->base); + dump_pd(data, psc); + } +} + +static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct ti_k3_pd_platdata *data; + + data = ti_pd_find_data(); + if (!data) + return CMD_RET_FAILURE; + + dump_psc(data); + + return 0; +} + +static int do_pd_endis(int argc, char *const argv[], u8 state) +{ + u32 psc_id; + u32 lpsc_id; + int i; + struct ti_k3_pd_platdata *data; + struct ti_lpsc *lpsc; + int ret; + + if (argc < 3) + return CMD_RET_FAILURE; + + data = ti_pd_find_data(); + if (!data) + return CMD_RET_FAILURE; + + psc_id = simple_strtoul(argv[1], NULL, 10); + lpsc_id = simple_strtoul(argv[2], NULL, 10); + + for (i = 0; i < data->num_lpsc; i++) { + lpsc = &data->lpsc[i]; + if (lpsc->pd->psc->id != psc_id) + continue; + if (lpsc->id != lpsc_id) + continue; + printf("%s pd [PSC:%d,LPSC:%d]...\n", + state == MDSTAT_STATE_ENABLE ? "Enabling" : "Disabling", + psc_id, lpsc_id); + ret = ti_lpsc_transition(lpsc, state); + if (ret) + return CMD_RET_FAILURE; + else + return 0; + } + + printf("No matching psc/lpsc found.\n"); + + return CMD_RET_FAILURE; +} + +static int do_pd_enable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_pd_endis(argc, argv, MDSTAT_STATE_ENABLE); +} + +static int do_pd_disable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_pd_endis(argc, argv, MDSTAT_STATE_SWRSTDISABLE); +} + +static struct cmd_tbl cmd_pd[] = { + U_BOOT_CMD_MKENT(dump, 1, 0, do_pd_dump, "", ""), + U_BOOT_CMD_MKENT(enable, 3, 0, do_pd_enable, "", ""), + U_BOOT_CMD_MKENT(disable, 3, 0, do_pd_disable, "", ""), +}; + +static int ti_do_pd(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_pd, ARRAY_SIZE(cmd_pd)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD(pd, 4, 1, ti_do_pd, + "TI power domain control", +#if CONFIG_IS_ENABLED(SYS_LONGHELP) + "dump - show power domain status\n" + "enable [psc] [lpsc] - enable power domain\n" + "disable [psc] [lpsc] - disable power domain\n" +#endif +); diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 56bc6fc31c5..b45e9b82453 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -132,7 +132,7 @@ static void ti_pd_transition(struct ti_pd *pd) psc_write(BIT(pd->id), pd->psc, PSC_PTCMD); } -static u8 ti_pd_state(struct ti_pd *pd) +u8 ti_pd_state(struct ti_pd *pd) { return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK; } @@ -227,12 +227,12 @@ static int ti_lpsc_wait(struct ti_lpsc *lpsc) return ret; } -static u8 lpsc_get_state(struct ti_lpsc *lpsc) +u8 lpsc_get_state(struct ti_lpsc *lpsc) { return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK; } -static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) +int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) { struct ti_pd *psc_pd; int ret; diff --git a/include/k3-dev.h b/include/k3-dev.h index de3a8bdf9eb..55c5057db35 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -22,6 +22,11 @@ #define PSC_PD_ALWAYSON BIT(1) #define PSC_PD_DEPENDS BIT(2) +#define MDSTAT_STATE_MASK 0x3f +#define MDSTAT_BUSY_MASK 0x30 +#define MDSTAT_STATE_SWRSTDISABLE 0x0 +#define MDSTAT_STATE_ENABLE 0x3 + struct ti_psc { int id; void __iomem *base; @@ -73,4 +78,8 @@ struct ti_k3_pd_platdata { extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata; +u8 ti_pd_state(struct ti_pd *pd); +u8 lpsc_get_state(struct ti_lpsc *lpsc); +int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state); + #endif -- cgit v1.3.1