From a3055c587d69603ff2a3e183ce0daffaf4600910 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Tue, 5 Apr 2011 14:39:33 -0500 Subject: powerpc/85xx: rename NAND prefixes to CONFIG_SYS renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more appropriate CONFIG_SYS prefix as well as be consistent with 83xx. Signed-off-by: Matthew McClintock cc: Scott Wood Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 18 +++++++++--------- include/configs/MPC8569MDS.h | 12 ++++++------ include/configs/MPC8572DS.h | 18 +++++++++--------- include/configs/P1_P2_RDB.h | 12 ++++++------ include/configs/P2020DS.h | 14 +++++++------- 5 files changed, 37 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 333a1ea6ce3..9b3e0329243 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -361,13 +361,13 @@ #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM \ +#define CONFIG_SYS_NAND_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< Date: Fri, 8 Apr 2011 02:46:39 -0500 Subject: powerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boards We don't really ever use Video cards on corenet_ds style boards and its bloating our image which is close the its max size. Drop support and also kill some defines for non-PNP PCI which we never use. Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 23 ----------------------- 1 file changed, 23 deletions(-) (limited to 'include') diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7bafa05b199..6f01211e7e8 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -390,33 +390,10 @@ #endif #ifdef CONFIG_PCI - -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT - -/* video */ -#define CONFIG_VIDEO - -#ifdef CONFIG_VIDEO -#define CONFIG_BIOSEMU -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET -#endif - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ -- cgit v1.3.1 From 218a758fb96f3a0e5c18b4bbef8aa2a2f9eb0e35 Mon Sep 17 00:00:00 2001 From: Jiang Yutang Date: Mon, 24 Jan 2011 18:21:19 +0800 Subject: powerpc/85xx: Enable support for ATI graphics cards on P1022DS Make the support for ATI graphics cards mutually exclusive with DIU. Signed-off-by: Jiang Yutang Signed-off-by: Kumar Gala --- include/configs/P1022DS.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index e78bcc54c58..f91f8477e54 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -219,6 +219,22 @@ #undef CONFIG_SYS_FLASH_EMPTY_INFO #endif +#ifndef CONFIG_DIU +#define CONFIG_ATI +#endif + +#ifdef CONFIG_ATI +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT +#define CONFIG_VIDEO +#define CONFIG_BIOSEMU +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + /* * Pass open firmware flat tree */ -- cgit v1.3.1 From f378017ffa53fbf8bf3530b25a589fba771a2ffb Mon Sep 17 00:00:00 2001 From: Jiang Yutang Date: Thu, 24 Feb 2011 16:11:55 +0800 Subject: powerpc/85xx: Update default hwconfig on P1022DS Set default configuration to have SDHC controller enabled, AUDIO enabled(codec clock sources is 12MHz) and disable TDM. Signed-off-by: Jiang Yutang Signed-off-by: Kumar Gala --- include/configs/P1022DS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index f91f8477e54..fb2a41ce240 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -508,6 +508,7 @@ "dium=mw e002c01c\0" \ "diuerr=md e002c014 1\0" \ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ + "hwconfig=esdhc;audclk:12\0" \ "monitor=0-DVI\0" #define CONFIG_HDBOOT \ -- cgit v1.3.1 From 2a9fab82b74d59aa9150e905aa06a6bff32c5059 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 16 Mar 2011 10:10:32 +0800 Subject: powerpc/85xx: Add PBL boot from SPI flash support on P4080DS PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan Signed-off-by: Mingkai Hu Signed-off-by: Shaohui Xie Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +++++++++++++++++++ board/freescale/corenet_ds/tlb.c | 12 +++++++++++- boards.cfg | 1 + include/configs/corenet_ds.h | 27 ++++++++++++++++++++++++++- 4 files changed, 57 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 5642cd7b051..6f256cf7a7b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -145,6 +145,22 @@ static void enable_cpc(void) for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_RAMBOOT_PBL + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); @@ -168,6 +184,9 @@ void invalidate_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; /* Flash invalidate the CPC and clear all the locks */ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index 1ae0416248c..fe77e798a8c 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -51,9 +51,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, diff --git a/boards.cfg b/boards.cfg index d25f3f23927..c9c12785fae 100644 --- a/boards.cfg +++ b/boards.cfg @@ -542,6 +542,7 @@ P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH P4080DS powerpc mpc85xx corenet_ds freescale +P4080DS_RAMBOOT_PBL powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000 mpq101 powerpc mpc85xx mpq101 mercury - mpq101 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 6f01211e7e8..4e2b3fb983d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -28,6 +28,11 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -63,12 +68,17 @@ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_RAMBOOT_PBL) + #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */ +#endif + #ifdef CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_NOWHERE #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ @@ -99,6 +109,18 @@ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */ +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -192,6 +214,10 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -439,7 +465,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -- cgit v1.3.1 From 32c8cfb23cd8beb814edd217c02e6aa5c7a64acf Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 9 Feb 2011 09:24:10 +0530 Subject: fsl_esdhc: Deal with watermark level register related changes P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Tested-by: Stefano Babic Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ drivers/mmc/fsl_esdhc.c | 8 ++++---- include/fsl_esdhc.h | 15 ++++++++++++++- 3 files changed, 20 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 59aeb31087f..41fd86c4e22 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -88,6 +88,7 @@ #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -131,6 +132,7 @@ #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0962ac4476a..4f1b5150c94 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -178,14 +178,14 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = data->blocksize/4; if (data->flags & MMC_DATA_READ) { - if (wml_value > 0x10) - wml_value = 0x10; + if (wml_value > WML_RD_WML_MAX) + wml_value = WML_RD_WML_MAX_VAL; esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); esdhc_write32(®s->dsaddr, (u32)data->dest); } else { - if (wml_value > 0x80) - wml_value = 0x80; + if (wml_value > WML_WR_WML_MAX) + wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return TIMEOUT; diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 477bbd792e8..8418bf7f47a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008,2010 Freescale Semiconductor, Inc + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -135,8 +135,21 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#ifdef CONFIG_FSL_SDHC_V2_3 +#define WML_RD_WML_MAX 0x80 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x0 +#define WML_WR_WML_MAX_VAL 0x0 +#define WML_RD_WML_MASK 0x7f +#define WML_WR_WML_MASK 0x7f0000 +#else +#define WML_RD_WML_MAX 0x10 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x10 +#define WML_WR_WML_MAX_VAL 0x80 #define WML_RD_WML_MASK 0xff #define WML_WR_WML_MASK 0xff0000 +#endif #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) -- cgit v1.3.1