From dc3e30bab7c5ef87bd24ebcbb7cdfc3fb2b44555 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 4 Sep 2012 23:22:55 +0000 Subject: Atmel: sam9g10/9m10/9x5: Add support to boot DT kernel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mainline linux kernel is moving to flatten device tree support Add the CONFIG_OF_LIBFDT option to support booting DT linux kernel Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/at91sam9261ek.h | 2 ++ include/configs/at91sam9m10g45ek.h | 2 ++ include/configs/at91sam9x5ek.h | 2 ++ 3 files changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 1e1fbe56d71..611e3e25329 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -48,6 +48,8 @@ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + #define CONFIG_ATMEL_LEGACY #define CONFIG_SYS_TEXT_BASE 0x21f00000 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 4ca280a7fff..e988d814107 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -47,6 +47,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 1ceb31a0f4e..cbdc3e93cbf 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -42,6 +42,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO -- cgit v1.3.1 From 362635bd50e386770ebaa2d5d090eb8cbf96430b Mon Sep 17 00:00:00 2001 From: Benoît Thébaudeau Date: Tue, 18 Sep 2012 04:48:42 +0000 Subject: mx51evk: Add CONFIG_REVISION_TAG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Fabio Estevam Acked-by: Fabio Estevam --- arch/arm/include/asm/arch-mx5/imx-regs.h | 2 ++ board/freescale/mx51evk/mx51evk.c | 8 ++++++++ include/configs/mx51evk.h | 1 + 3 files changed, 11 insertions(+) (limited to 'include') diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d1ef15d043d..46017f4ad06 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -321,6 +321,8 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 +#define BOARD_VER_OFFSET 0x8 + #define IMX_IIM_BASE (IIM_BASE_ADDR) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 7a0682a7e96..a94701cbf17 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -60,6 +60,14 @@ int dram_init(void) return 0; } +u32 get_board_rev(void) +{ + u32 rev = get_cpu_rev(); + if (!gpio_get_value(IMX_GPIO_NR(1, 22))) + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; +} + static void setup_iomux_uart(void) { unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ba4a4a623c1..7b027b42acd 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -44,6 +44,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG #define CONFIG_OF_LIBFDT -- cgit v1.3.1 From 5f8e17ce158894b46acb25b975c579fae2350523 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 23 Sep 2012 07:30:54 +0000 Subject: i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU frame buffer Signed-off-by: Eric Nelson Tested-by: Fabio Estevam --- drivers/video/mxc_ipuv3_fb.c | 20 ++++++++++++++++++++ include/ipu_pixfmt.h | 1 + 2 files changed, 21 insertions(+) (limited to 'include') diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c index c38e22de1f3..47b336e7aa4 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@ -38,6 +38,7 @@ #include "videomodes.h" #include "ipu.h" #include "mxcfb.h" +#include "ipu_regs.h" static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); @@ -576,6 +577,25 @@ err0: return ret; } +void ipuv3_fb_shutdown(void) +{ + int i; + struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT; + + for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) { + struct fb_info *fbi = mxcfb_info[i]; + if (fbi) { + struct mxcfb_info *mxc_fbi = fbi->par; + ipu_disable_channel(mxc_fbi->ipu_ch); + ipu_uninit_channel(mxc_fbi->ipu_ch); + } + } + for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) { + __raw_writel(__raw_readl(&stat->int_stat[i]), + &stat->int_stat[i]); + } +} + void *video_hw_init(void) { int ret; diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h index 0019898d510..4baa71187d9 100644 --- a/include/ipu_pixfmt.h +++ b/include/ipu_pixfmt.h @@ -77,5 +77,6 @@ #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */ int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt); +void ipuv3_fb_shutdown(void); #endif -- cgit v1.3.1 From 7577a4b3c27af9ad21a4aedf732754ae96225448 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 21 Sep 2012 03:02:03 +0000 Subject: mx28evk: Add missing 'setexpr' command The environment now uses expressions but we missed the setexpr command was not being include. This patch adds it. Signed-off-by: Otavio Salvador --- include/configs/mx28evk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index dffb744c3dc..7cdbec68dea 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -63,6 +63,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_USB -- cgit v1.3.1 From b72db2080bc6d34be8011f1a7f38d9300fdb56be Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Thu, 30 Aug 2012 23:53:32 +0000 Subject: devkit8000: add rootwait to mmcboot option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann cc: Thomas Weber --- include/configs/devkit8000.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 2d2ee5f1a1a..1e658067e04 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -198,6 +198,7 @@ "run commonargs; " \ "setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 " \ + "rootwait " \ "${kernelopts}\0" \ "nandargs=" \ "run commonargs; " \ -- cgit v1.3.1 From 39e133d1962bd90c136460f0053dcd184feb053c Mon Sep 17 00:00:00 2001 From: Bastian Ruppert Date: Thu, 13 Sep 2012 22:29:00 +0000 Subject: davinci: ea20: the console is always set to the serial line Do not allow to overwrite it when video is enabled. Signed-off-by: Bastian Ruppert CC: Tom Rini Acked-by: Stefano Babic --- board/davinci/ea20/ea20.c | 11 +++++++++-- include/configs/ea20.h | 2 ++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 69307e459d4..0edd9102106 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -254,6 +254,15 @@ int board_early_init_f(void) return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_init(void) { /* arch number of the board */ @@ -281,8 +290,6 @@ int board_late_init(void) /* Set HALTEN to high */ gpio_direction_output(134, 1); - setenv("stdout", "serial"); - /* Set fixed contrast settings for LCD via I2C potentiometer */ buf[0] = 0x00; buf[1] = 0xd7; diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 337d504923b..21aa4172497 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -124,6 +124,8 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_CMD_BMP +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #endif /* -- cgit v1.3.1 From a64f0241dc3d2705b065d9546711f22db7dcf712 Mon Sep 17 00:00:00 2001 From: Bastian Ruppert Date: Thu, 13 Sep 2012 22:29:04 +0000 Subject: davinci: ea20: add some configs and default environmet variables Signed-off-by: Bastian Ruppert CC: Tom Rini Acked-by: Stefano Babic --- include/configs/ea20.h | 106 ++++++++++++++++++++++++++++++------------------- 1 file changed, 66 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 21aa4172497..c82b5b68a1d 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -30,6 +30,7 @@ #define CONFIG_USE_SPIFLASH #define CONFIG_SYS_USE_NAND #define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT #define CONFIG_VIDEO @@ -97,6 +98,7 @@ * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 0 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS @@ -120,9 +122,11 @@ #define CONFIG_VIDEO_DA8XX #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO #define CONFIG_CMD_BMP #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE @@ -196,6 +200,7 @@ #define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_NO_SUBPAGE #define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #undef CONFIG_SYS_NAND_HW_ECC @@ -234,31 +239,39 @@ #define xstr(s) str(s) #define str(s) #s - #define CONFIG_HOSTNAME ea20 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "as=3\0" \ - "netdev=eth0\0" \ + "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "rfsbargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rfsbpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdids=nand0=davinci_nand.0\0" \ - "mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel)," \ - "8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0" \ + "testrfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${testrfspath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw initrd=" \ + "0x${ramdisk_addr_r},4M\0" \ + "mtdids=nand0=davinci_nand.0\0" \ + "serverip=192.168.5.249\0" \ + "ipaddr=192.168.5.248\0" \ + "rootpath=/opt/eldk/arm\0" \ + "splashpos=230,180\0" \ + "testrfspath=/opt/eldk/test_arm\0" \ + "tempmac=setenv ethaddr 02:ea:20:ff:ff:ff\0" \ "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \ "ubi.mtd=${as} root=ubi0:rootfs\0" \ + "nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \ + "ubi.mtd=${as} root=ubi0:rootfs\0" \ "addip_sta=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ "else run addip_sta;fi\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addtty=setenv bootargs ${bootargs}" \ " console=${consoledev},${baudrate}n8\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \ "consoledev=ttyS0\0" \ "loadaddr=c0000014\0" \ @@ -266,44 +279,57 @@ "kernel_addr_r=c0700000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ - "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/image.ext2\0" \ "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "bootm ${kernel_addr_r}\0" \ "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \ "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ "run nfsargs addip addtty addmtd addmisc addmem;" \ - "bootm ${kernel_addr_r}\0" \ - "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \ - "run rfsbargs addip addtty addmtd addmisc addmem; " \ - "bootm ${kernel_addr_r}\0" \ + "bootm ${kernel_addr_r}\0" \ + "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \ + "run rfsbargs addip addtty addmtd addmisc addmem; " \ + "bootm ${kernel_addr_r}\0" \ + "net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run testrfsargs addip addtty addmtd addmisc addmem; " \ + "bootm ${kernel_addr_r}\0" \ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \ - "ubifsload ${kernel_addr_r} /boot/uImage;" \ - "ubifsumount; run nandargs addip addtty " \ - "addmtd addmisc addmem;bootm ${kernel_addr_r}\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ - "load_magic=if sf probe 0;then sf " \ - "read c0000000 0x10000 0x60000;fi\0" \ - "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \ - "if ubifsload c0000014 /boot/u-boot.bin;" \ - "then mw c0000008 ${filesize};else echo Error reading " \ - "u-boot from nand!;fi\0" \ - "load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;" \ - "tftp c0000014 ${u-boot};" \ - "mw c0000008 ${filesize};" \ - "fi\0" \ - "upd=if sf probe 0;then sf erase 10000 60000;" \ - "sf write c0000000 10000 60000;" \ - "fi\0" \ - "ubootupd_net=if run load_net;then echo Updating u-boot;" \ - "if run upd; then echo U-Boot updated;" \ + "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \ + "ubifsload ${kernel_addr_r} /boot/uImage;" \ + "ubifsumount; run nandargs addip addtty " \ + "addmtd addmisc addmem;clrlogo;" \ + "bootm ${kernel_addr_r}\0" \ + "nand_nandrw=ubi part nand0,${as};ubifsmount rootfs;" \ + "ubifsload ${kernel_addr_r} /boot/uImage;" \ + "ubifsumount; run nandrwargs addip addtty " \ + "addmtd addmisc addmem;clrlogo;" \ + "bootm ${kernel_addr_r}\0" \ + "net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \ + " addip addtty addmtd addmisc addmem;" \ + "clrlogo;bootm ${kernel_addr_r}\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load_magic=if sf probe 0;then sf " \ + "read c0000000 0x10000 0x60000;fi\0" \ + "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \ + "if ubifsload c0000014 /boot/u-boot.bin;" \ + "then mw c0000008 ${filesize};else echo Error reading" \ + " u-boot from nand!;fi\0" \ + "load_net=if sf probe 0;then sf read c0000000 0x10000 " \ + "0x60000;tftp c0000014 ${u-boot};" \ + "mw c0000008 ${filesize};fi\0" \ + "upd=if sf probe 0;then sf erase 10000 60000;" \ + "sf write c0000000 10000 60000;fi\0" \ + "ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \ + "sf erase 0 10000;" \ + "sf write 0xc0700000 0 ${filesize};fi\0" \ + "ubootupd_net=if run load_net;then echo Updating u-boot;" \ + "if run upd; then echo U-Boot updated;" \ "else echo Error updating u-boot !;" \ "echo Board without bootloader !!;" \ "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \ - "bootcmd=run net_nfs\0" + "else echo U-Boot not downloaded..exiting;fi\0" \ + "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \ + "bootcmd=run tempmac;run net_testrfs\0" #endif /* __CONFIG_H */ -- cgit v1.3.1 From 6feb4e9db10990ed56655602de8dd08564b7c245 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 17 Sep 2012 10:26:28 +0000 Subject: am335x_evm: enable networking in SPL This patch adds support for networking in SPL on TI AM335x based boards. Vendor Class Identifier used by SPL during BOOTP is "AM335x U-Boot SPL". Signed-off-by: Ilya Yanok --- include/configs/am335x_evm.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 263a5adb353..c5475421c0f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -195,7 +195,7 @@ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (46 * 1024) +#define CONFIG_SPL_MAX_SIZE (101 * 1024) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 @@ -215,6 +215,9 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +#define CONFIG_SPL_ETH_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* -- cgit v1.3.1 From 7ac2fe2da21d292aeaf3af74e5c80de9ce9dab56 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Tue, 18 Sep 2012 00:22:50 +0000 Subject: OMAP: networking support for SPL This patch adds support for networking in SPL. Some devices are capable of loading SPL via network so it makes sense to load the main U-Boot binary via network too. This patch tries to use existing network code as much as possible. Unfortunately, it depends on environment which in turn depends on other code so SPL size is increased significantly. No effort was done to decouple network code and environment so far. Signed-off-by: Ilya Yanok Acked-by: Joe Hershberger Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/spl.h | 1 + board/ti/beagle/beagle.c | 2 +- common/Makefile | 4 +++ common/cmd_nvedit.c | 8 ++++++ common/env_common.c | 7 +++-- common/spl/Makefile | 1 + common/spl/spl.c | 9 ++++++ common/spl/spl_net.c | 52 ++++++++++++++++++++++++++++++++++ include/bootstage.h | 6 +++- include/config_uncmd_spl.h | 44 ++++++++++++++++++++++++++++ include/spl.h | 3 ++ lib/Makefile | 9 ++++-- lib/hashtable.c | 2 ++ mkconfig | 1 + net/bootp.c | 7 ++++- spl/Makefile | 3 ++ 16 files changed, 152 insertions(+), 7 deletions(-) create mode 100644 common/spl/spl_net.c create mode 100644 include/config_uncmd_spl.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 70f521d2697..dc838823d32 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -27,5 +27,6 @@ #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 99f833f0410..49544755532 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -488,7 +488,7 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_USB_EHCI +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { diff --git a/common/Makefile b/common/Makefile index 125b2be3155..5442fbbc99d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -198,6 +198,10 @@ endif ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o endif COBJS-y += console.o COBJS-y += dlmalloc.o diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 3474bc60940..8ecc4982309 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -103,6 +103,7 @@ int get_env_id(void) return env_id; } +#ifndef CONFIG_SPL_BUILD /* * Command interface: print one or all environment variables * @@ -196,6 +197,7 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag, return rcode; } #endif +#endif /* CONFIG_SPL_BUILD */ /* * Perform consistency checking before setting, replacing, or deleting an @@ -437,6 +439,7 @@ int setenv_addr(const char *varname, const void *addr) return setenv(varname, str); } +#ifndef CONFIG_SPL_BUILD int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) @@ -536,6 +539,7 @@ int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return setenv(argv[1], buffer); } #endif /* CONFIG_CMD_EDITENV */ +#endif /* CONFIG_SPL_BUILD */ /* * Look up variable from environment, @@ -621,6 +625,7 @@ ulong getenv_ulong(const char *name, int base, ulong default_val) return str ? simple_strtoul(str, NULL, base) : default_val; } +#ifndef CONFIG_SPL_BUILD #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -635,6 +640,7 @@ U_BOOT_CMD( "" ); #endif +#endif /* CONFIG_SPL_BUILD */ /* @@ -656,6 +662,7 @@ int envmatch(uchar *s1, int i2) return -1; } +#ifndef CONFIG_SPL_BUILD static int do_env_default(cmd_tbl_t *cmdtp, int __flag, int argc, char * const argv[]) { @@ -1114,3 +1121,4 @@ U_BOOT_CMD_COMPLETE( var_complete ); #endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/common/env_common.c b/common/env_common.c index 3e46c260df8..57221efe01f 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -231,6 +231,7 @@ int set_default_vars(int nvars, char * const vars[]) nvars, vars, 1 /* do_apply */); } +#ifndef CONFIG_SPL_BUILD /* * Check if CRC is valid and (if yes) import the environment. * Note that "buf" may or may not be aligned. @@ -262,6 +263,7 @@ int env_import(const char *buf, int check) return 0; } +#endif void env_relocate(void) { @@ -269,7 +271,8 @@ void env_relocate(void) env_reloc(); #endif if (gd->env_valid == 0) { -#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */ +#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD) + /* Environment not changable */ set_default_env(NULL); #else bootstage_error(BOOTSTAGE_ID_NET_CHECKSUM); @@ -280,7 +283,7 @@ void env_relocate(void) } } -#ifdef CONFIG_AUTO_COMPLETE +#if defined(CONFIG_AUTO_COMPLETE) && !defined(CONFIG_SPL_BUILD) int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) { ENTRY *match; diff --git a/common/spl/Makefile b/common/spl/Makefile index 7cf01ad72d0..5698a2335a9 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -18,6 +18,7 @@ COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o endif COBJS := $(sort $(COBJS-y)) diff --git a/common/spl/spl.c b/common/spl/spl.c index 29cbb9335a3..40a7acaeaf5 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -195,6 +195,15 @@ void board_init_r(gd_t *dummy1, ulong dummy2) case BOOT_DEVICE_SPI: spl_spi_load_image(); break; +#endif +#ifdef CONFIG_SPL_ETH_SUPPORT + case BOOT_DEVICE_CPGMAC: +#ifdef CONFIG_SPL_ETH_DEVICE + spl_net_load_image(CONFIG_SPL_ETH_DEVICE); +#else + spl_net_load_image(NULL); +#endif + break; #endif default: debug("SPL: Un-supported Boot Device\n"); diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c new file mode 100644 index 00000000000..e1596fee274 --- /dev/null +++ b/common/spl/spl_net.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2012 + * Ilya Yanok + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_net_load_image(const char *device) +{ + int rv; + + env_init(); + env_relocate(); + setenv("autoload", "yes"); + load_addr = CONFIG_SYS_TEXT_BASE - sizeof(struct image_header); + rv = eth_initialize(gd->bd); + if (rv == 0) { + printf("No Ethernet devices found\n"); + hang(); + } + if (device) + setenv("ethact", device); + rv = NetLoop(BOOTP); + if (rv < 0) { + printf("Problem booting with BOOTP\n"); + hang(); + } + spl_parse_image_header((struct image_header *)load_addr); +} diff --git a/include/bootstage.h b/include/bootstage.h index a00053888f6..db94a957e6e 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -210,6 +210,7 @@ enum bootstage_id { */ ulong timer_get_boot_us(void); +#ifndef CONFIG_SPL_BUILD /* * Board code can implement show_boot_progress() if needed. * @@ -217,8 +218,11 @@ ulong timer_get_boot_us(void); * has occurred. */ void show_boot_progress(int val); +#else +#define show_boot_progress(val) do {} while (0) +#endif -#ifdef CONFIG_BOOTSTAGE +#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) /* This is the full bootstage implementation */ /* diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h new file mode 100644 index 00000000000..bab3ddf4af3 --- /dev/null +++ b/include/config_uncmd_spl.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2012 + * Ilya Yanok, ilya.yanok@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + * + * We don't use any commands in SPL, but generic networking code + * has some features enabled/disabled based on CONFIG_CMD_* + * options. As we want a minimal set of features included + * into network SPL image, we undefine some config options here. + */ + +#ifndef __CONFIG_UNCMD_SPL_H__ +#define __CONFIG_UNCMD_SPL_H__ + +#ifdef CONFIG_SPL_BUILD +/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */ +#undef CONFIG_CMD_CDP +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DNS +#undef CONFIG_CMD_LINK_LOCAL +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_RARP +#undef CONFIG_CMD_SNTP +#undef CONFIG_CMD_TFTPPUT +#undef CONFIG_CMD_TFTPSRV +#endif /* CONFIG_SPL_BUILD */ +#endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/include/spl.h b/include/spl.h index af94a8238f1..b02f36fa941 100644 --- a/include/spl.h +++ b/include/spl.h @@ -71,6 +71,9 @@ void spl_ymodem_load_image(void); /* SPI SPL functions */ void spl_spi_load_image(void); +/* Ethernet SPL functions */ +void spl_net_load_image(const char *device); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/lib/Makefile b/lib/Makefile index 45798de8a14..a099885f7b6 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -53,12 +53,17 @@ COBJS-$(CONFIG_SHA1) += sha1.o COBJS-$(CONFIG_SHA256) += sha256.o COBJS-y += strmhz.o COBJS-$(CONFIG_RBTREE) += rbtree.o -else -COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o endif ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += crc32.o +ifneq ($(CONFIG_SPL_SPI_FLASH_SUPPORT)$(CONFIG_SPL_NET_SUPPORT),) +COBJS-y += display_options.o +endif +COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o +COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o endif COBJS-y += crc32.o COBJS-y += ctype.o diff --git a/lib/hashtable.c b/lib/hashtable.c index 670a704a418..94a7b61717a 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -435,6 +435,7 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int do_apply) * hexport() */ +#ifndef CONFIG_SPL_BUILD /* * Export the data stored in the hash table in linearized form. * @@ -601,6 +602,7 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, return size; } +#endif /* diff --git a/mkconfig b/mkconfig index d3363c6df37..7c9aa74eb27 100755 --- a/mkconfig +++ b/mkconfig @@ -185,6 +185,7 @@ cat << EOF >> config.h #include #include #include +#include EOF exit 0 diff --git a/net/bootp.c b/net/bootp.c index ccf9ee66758..cd5c5dd1d74 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -535,9 +535,14 @@ static int BootpExtended(u8 *e) *e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff; #endif -#ifdef CONFIG_BOOTP_VCI_STRING +#if defined(CONFIG_BOOTP_VCI_STRING) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)) +#ifdef CONFIG_SPL_BUILD + put_vci(e, CONFIG_SPL_NET_VCI_STRING); +#else put_vci(e, CONFIG_BOOTP_VCI_STRING); #endif +#endif #if defined(CONFIG_BOOTP_SUBNETMASK) *e++ = 1; /* Subnet mask request */ diff --git a/spl/Makefile b/spl/Makefile index d9b1c2ff8ec..e9d0ec4c9a3 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -57,6 +57,9 @@ LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o +LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o +LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o +LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -- cgit v1.3.1 From 3580777b62060b6ec32b37905869baaeac22345f Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Wed, 26 Sep 2012 07:19:43 +0000 Subject: am335x-evm config: decrease bootdelay to 1s and mount rootfs RO A fast boot is important to the beaglebone, so save 2 seconds here by decreasing bootdelay. This is still plenty time to break into the prompt, I do that at least once a day. Mount the rootfs RO by default, this is needed to make fsck succeed without resorting to an initramfs. Signed-off-by: Koen Kooi --- include/configs/am335x_evm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c5475421c0f..339d4bdb631 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -45,7 +45,7 @@ #define CONFIG_VERSION_VARIABLE /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ @@ -54,7 +54,7 @@ "console=ttyO0,115200n8\0" \ "optargs=\0" \ "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ "ramrootfstype=ext2\0" \ -- cgit v1.3.1 From 3c2e616f4b20e6e23d8268e99beec91b95ce9e70 Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Thu, 27 Sep 2012 23:19:14 +0000 Subject: omap4_panda: remove CONFIG_PANDA, not used Signed-off-by: Peter Meerwald --- include/configs/omap4_panda.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index b4756be5287..eacb5f5c3b7 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -31,7 +31,6 @@ /* * High Level Configuration Options */ -#define CONFIG_PANDA /* working with Panda */ /* USB UHH support options */ #define CONFIG_CMD_USB -- cgit v1.3.1 From 8d811ca36a2a4096dd3ed0d64f2a22a247400737 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Jun 2012 14:55:07 +0900 Subject: arm: rmobile: Add supoprt for KMC KZM-A9-GT board The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 512MB DDR2-SDRAM - 16MB NOR Flash memory - Serial console (SCIF) - Ethernet (SMSC) - I2C Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- MAINTAINERS | 4 + arch/arm/include/asm/mach-types.h | 13 ++ board/kmc/kzm9g/Makefile | 50 +++++ board/kmc/kzm9g/kzm9g.c | 372 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/kzm9g.h | 168 +++++++++++++++++ 6 files changed, 608 insertions(+) create mode 100644 board/kmc/kzm9g/Makefile create mode 100644 board/kmc/kzm9g/kzm9g.c create mode 100644 include/configs/kzm9g.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index aa54fe11ee5..7c925d4e405 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -990,6 +990,10 @@ Zhong Hongbo SMDK6400 ARM1176 (S3C6400 SoC) +Nobuhiro Iwamatsu + + kzm9g SH73A0 (RMOBILE SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 2d5c3bc376b..5f9994ec901 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_KZM9G 4140 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14222,6 +14223,18 @@ extern unsigned int __machine_arch_type; # define machine_is_omap5_sevm() (0) #endif +#ifdef CONFIG_MACH_KZM9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KZM9G +# endif +# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G) +#else +# define machine_is_kzm9g() (0) +#endif + /* * These have not yet been registered */ diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile new file mode 100644 index 00000000000..bae79f50881 --- /dev/null +++ b/board/kmc/kzm9g/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2012 Nobuhiro Iwamatsu +# (C) Copyright 2012 Renesas Solutions Corp. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := kzm9g.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj) .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c new file mode 100644 index 00000000000..ad72c8daf3e --- /dev/null +++ b/board/kmc/kzm9g/kzm9g.c @@ -0,0 +1,372 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CS0BCR_D (0x06C00400) +#define CS4BCR_D (0x06C00400) +#define CS0WCR_D (0x55062C42) +#define CS4WCR_D (0x19051443) +#define CMNCR_BROMMD0 (1 << 21) +#define CMNCR_BROMMD1 (1 << 22) +#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) +#define VCLKCR1_D (0x27) + +#define SMSTPCR1_CMT0 (1 << 24) +#define SMSTPCR1_I2C0 (1 << 16) +#define SMSTPCR3_USB (1 << 22) + +#define PORT32CR (0xE6051020) +#define PORT33CR (0xE6051021) +#define PORT34CR (0xE6051022) +#define PORT35CR (0xE6051023) + +static int cmp_loop(u32 *addr, u32 data, u32 cmp) +{ + int err = -1; + int timeout = 100; + u32 value; + + while (timeout > 0) { + value = readl(addr); + if ((value & data) == cmp) { + err = 0; + break; + } + timeout--; + } + + return err; +} + +/* SBSC Init function */ +static void sbsc_init(struct sh73a0_sbsc *sbsc) +{ + writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); + writel(0x5, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + writel(0xacc90159, &sbsc->sdcr0); + writel(0x00010059, &sbsc->sdcr1); + writel(0x50874114, &sbsc->sdwcrc0); + writel(0x33199b37, &sbsc->sdwcrc1); + writel(0x008f2313, &sbsc->sdwcrc2); + writel(0x31020707, &sbsc->sdwcr00); + writel(0x0017040a, &sbsc->sdwcr01); + writel(0x31020707, &sbsc->sdwcr10); + writel(0x0017040a, &sbsc->sdwcr11); + writel(0x05555555, &sbsc->sddrvcr0); + writel(0x30000000, &sbsc->sdwcr2); + + writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); + cmp_loop(&sbsc->sdpcr, 0x80, 0x80); + + writel(0x00002710, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + writel(0x0000003f, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x000001f4, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + writel(0x0000ff0a, &sbsc->sdmracr0); + if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) + writel(0x0, SDMRA3A); + else + writel(0x0, SDMRA3B); + + writel(0x00000032, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { + writel(0x00002201, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x00000402, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x00000403, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x0, SDMRA2A); + } else { + writel(0x00002201, &sbsc->sdmracr0); + writel(0x0, SDMRA1B); + writel(0x00000402, &sbsc->sdmracr0); + writel(0x0, SDMRA1B); + writel(0x00000403, &sbsc->sdmracr0); + writel(0x0, SDMRA1B); + writel(0x0, SDMRA2B); + } + + writel(0x88800004, &sbsc->sdmrtmpcr); + writel(0x00000004, &sbsc->sdmrtmpmsk); + writel(0xa55a0032, &sbsc->rtcor); + writel(0xa55a000c, &sbsc->rtcorh); + writel(0xa55a2048, &sbsc->rtcsr); + writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); + writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); + writel(0xfff20000, &sbsc->zqccr); + + /* SCBS2 only */ + if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { + writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); + writel(0xa5390000, &sbsc->dphycnt1); + writel(0x00001200, &sbsc->dphycnt0); + writel(0x07ce0000, &sbsc->dphycnt1); + writel(0x00001247, &sbsc->dphycnt0); + cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); + writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); + } +} + +void s_init(void) +{ + struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; + struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; + struct sh73a0_sbsc_cpg_srcr *cpg_srcr = + (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; + struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; + struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + struct sh73a0_hpb_bscr *hpb_bscr = + (struct sh73a0_hpb_bscr *)HPBSCR_BASE; + + /* Watchdog init */ + writew(0xA507, &rwdt->rwtcsra0); + + /* Secure control register Init */ + #define LIFEC_SEC_SRC_BIT (1 << 15) + writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); + + clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); + clrbits_le32(&cpg->smstpcr2, (1 << 18)); + clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); + writel(0x0, &cpg->pllecr); + + cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); + cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); + + writel(0x2D000000, &cpg->pll0cr); + writel(0x17100000, &cpg->pll1cr); + writel(0x96235880, &cpg->frqcrb); + cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); + + writel(0xB, &cpg->flckcr); + clrbits_le32(&cpg->smstpcr0, (1 << 1)); + + clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); + writel(0x0514, &hpb_bscr->smgpiotime); + writel(0x0514, &hpb_bscr->smcmt2time); + writel(0x0514, &hpb_bscr->smcpgtime); + writel(0x0514, &hpb_bscr->smsysctime); + + writel(0x00092000, &cpg->dvfscr4); + writel(0x000000DC, &cpg->dvfscr5); + writel(0x0, &cpg->pllecr); + cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); + + /* FRQCR Init */ + writel(0x0012453C, &cpg->frqcra); + writel(0x80331350, &cpg->frqcrb); + cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); + writel(0x00000B0B, &cpg->frqcrd); + cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); + + /* Clock Init */ + writel(0x00000003, PCLKCR); + writel(0x0000012F, &cpg->vclkcr1); + writel(0x00000119, &cpg->vclkcr2); + writel(0x00000119, &cpg->vclkcr3); + writel(0x00000002, &cpg->zbckcr); + writel(0x00000005, &cpg->flckcr); + writel(0x00000080, &cpg->sd0ckcr); + writel(0x00000080, &cpg->sd1ckcr); + writel(0x00000080, &cpg->sd2ckcr); + writel(0x0000003F, &cpg->fsiackcr); + writel(0x0000003F, &cpg->fsibckcr); + writel(0x00000080, &cpg->subckcr); + writel(0x0000000B, &cpg->spuackcr); + writel(0x0000000B, &cpg->spuvckcr); + writel(0x0000013F, &cpg->msuckcr); + writel(0x00000080, &cpg->hsickcr); + writel(0x0000003F, &cpg->mfck1cr); + writel(0x0000003F, &cpg->mfck2cr); + writel(0x00000107, &cpg->dsitckcr); + writel(0x00000313, &cpg->dsi0pckcr); + writel(0x0000130D, &cpg->dsi1pckcr); + writel(0x2A800E0E, &cpg->dsi0phycr); + writel(0x1E000000, &cpg->pll0cr); + writel(0x2D000000, &cpg->pll0cr); + writel(0x17100000, &cpg->pll1cr); + writel(0x27000080, &cpg->pll2cr); + writel(0x1D000000, &cpg->pll3cr); + writel(0x00080000, &cpg->pll0stpcr); + writel(0x000120C0, &cpg->pll1stpcr); + writel(0x00012000, &cpg->pll2stpcr); + writel(0x00000030, &cpg->pll3stpcr); + + writel(0x0000000B, &cpg->pllecr); + cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); + + writel(0x000120F0, &cpg->dvfscr3); + writel(0x00000020, &cpg->mpmode); + writel(0x0000028A, &cpg->vrefcr); + writel(0xE4628087, &cpg->rmstpcr0); + writel(0xFFFFFFFF, &cpg->rmstpcr1); + writel(0x53FFFFFF, &cpg->rmstpcr2); + writel(0xFFFFFFFF, &cpg->rmstpcr3); + writel(0x00800D3D, &cpg->rmstpcr4); + writel(0xFFFFF3FF, &cpg->rmstpcr5); + writel(0x00000000, &cpg->smstpcr2); + writel(0x00040000, &cpg_srcr->srcr2); + + clrbits_le32(&cpg->pllecr, (1 << 3)); + cmp_loop(&cpg->pllecr, 0x00000800, 0x0); + + writel(0x00000001, &hpb->hpbctrl6); + cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); + + writel(0x00001414, &cpg->frqcrd); + cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); + + writel(0x1d000000, &cpg->pll3cr); + setbits_le32(&cpg->pllecr, (1 << 3)); + cmp_loop(&cpg->pllecr, 0x800, 0x800); + + /* SBSC1 Init*/ + sbsc_init(sbsc1); + + /* SBSC2 Init*/ + sbsc_init(sbsc2); + + writel(0x00000b0b, &cpg->frqcrd); + cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); +} + +int board_early_init_f(void) +{ + struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; + struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; + struct sh73a0_sbsc_cpg_srcr *cpg_srcr = + (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; + + writel(CS0BCR_D, &bsc->cs0bcr); + writel(CS4BCR_D, &bsc->cs4bcr); + writel(CS0WCR_D, &bsc->cs0wcr); + writel(CS4WCR_D, &bsc->cs4wcr); + + clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); + + clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); + clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); + clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); + clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); + writel(VCLKCR1_D, &cpg->vclkcr1); + + /* Setup SCIF4 / workaround */ + writeb(0x12, PORT32CR); + writeb(0x22, PORT33CR); + writeb(0x12, PORT34CR); + writeb(0x22, PORT35CR); + + return 0; +} + +int board_init(void) +{ + sh73a0_pinmux_init(); + + /* SCIFA 4 */ + gpio_request(GPIO_FN_SCIFA4_TXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); + gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); + + /* Ethernet/SMSC */ + gpio_request(GPIO_PORT224, NULL); + gpio_direction_input(GPIO_PORT224); + + /* SMSC/USB */ + gpio_request(GPIO_FN_CS4_, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCCMD0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_1_PU, NULL); + gpio_request(GPIO_FN_MMCD0_2_PU, NULL); + gpio_request(GPIO_FN_MMCD0_3_PU, NULL); + gpio_request(GPIO_FN_MMCD0_4_PU, NULL); + gpio_request(GPIO_FN_MMCD0_5_PU, NULL); + gpio_request(GPIO_FN_MMCD0_6_PU, NULL); + gpio_request(GPIO_FN_MMCD0_7_PU, NULL); + + /* SDHI */ + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); + gpio_request(GPIO_PORT15, NULL); + gpio_direction_output(GPIO_PORT15, 1); + + /* I2C */ + gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); + gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); + + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#ifdef CONFIG_SMC911X + ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return ret; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/boards.cfg b/boards.cfg index f789539e858..9599f8e7eed 100644 --- a/boards.cfg +++ b/boards.cfg @@ -272,6 +272,7 @@ ventana arm armv7:arm720t ventana nvidia whistler arm armv7:arm720t whistler nvidia tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 snowball arm armv7 snowball st-ericsson u8500 +kzm9g arm armv7 kzm9g kmc rmobile actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h new file mode 100644 index 00000000000..7567d46c76b --- /dev/null +++ b/include/configs/kzm9g.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2012 Nobuhiro Iwamatsu + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KZM9G_H +#define __KZM9G_H + +#undef DEBUG + +#define CONFIG_ARM_CORTEXA9 +#define CONFIG_RMOBILE +#define CONFIG_SH73A0 +#define CONFIG_KZM_A9_GT +#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" +#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G + +#include + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_L2_OFF + +#include +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_BAUDRATE (115200) +#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" +#define CONFIG_INTEGRATOR +#define CONFIG_ARCH_CINTEGRATOR +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* MEMORY */ +#define KZM_SDRAM_BASE (0x40000000) +#define PHYS_SDRAM KZM_SDRAM_BASE +#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) +#define CONFIG_NR_DRAM_BANKS (1) + +/* NOR Flash */ +#define KZM_FLASH_BASE (0x00000000) +#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) +#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) +#define CONFIG_SYS_MAX_FLASH_BANKS (1) +#define CONFIG_SYS_MAX_FLASH_SECT (512) + +/* prompt */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF4 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) +#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000) +#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_SDRAM_BASE KZM_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) + +#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE (256) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 + +/* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#undef CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ +#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE +#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) + +/* Timeout for Flash erase operations (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) + +#undef CONFIG_SYS_FLASH_PROTECTION +#undef CONFIG_SYS_DIRECT_FLASH_TFTP +#define CONFIG_ENV_IS_IN_FLASH + +/* GPIO / PFC */ +#define CONFIG_SH_GPIO_PFC + +/* Clock */ +#define CONFIG_SYS_CLK_FREQ (48000000) +#define CONFIG_SYS_CPU_CLK (1196000000) +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (1000) +#define CONFIG_SYS_HZ CFG_HZ + +/* Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE (0x10000000) +#define CONFIG_SMC911X_32_BIT + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SH_I2C 1 +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_I2C_MODULE +#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE (0x7F) +#define CONFIG_SH_I2C_DATA_HIGH (4) +#define CONFIG_SH_I2C_DATA_LOW (5) +#define CONFIG_SH_I2C_CLOCK (41666666) +#define CONFIG_SH_I2C_BASE0 (0xE6820000) +#define CONFIG_SH_I2C_BASE1 (0xE6822000) + +#endif /* __KZM9G_H */ -- cgit v1.3.1 From 9415cf93bc5ded82c6b915d5ab3b8c8f61a75c46 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 5 Jul 2012 01:43:44 +0000 Subject: arm: rmobile: kzm9g: Modify sdram area Reserve first 16MB for RT-CPU (as same as kernel config). Signed-off-by: Tetsuyuki Kobayashi Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 7567d46c76b..bcf2cd88c14 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -97,8 +97,9 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_SDRAM_BASE KZM_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) +#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) -- cgit v1.3.1 From 087a277b1add0d32087da2b99743c0af53c5589b Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 5 Jul 2012 01:43:52 +0000 Subject: arm: rmobile: kzm9g: change prompt to board specific Change U-Boot prompt to board specific one. Signed-off-by: Tetsuyuki Kobayashi Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index bcf2cd88c14..bd157d9b0f0 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -70,7 +70,7 @@ /* prompt */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_PROMPT "KZM-A9-GT# " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 -- cgit v1.3.1 From 18a65af408c77851c267cd8a071b5c7f6a2ef03b Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 19 Jul 2012 16:16:08 +0000 Subject: arm: rmobile: kzm9g: Fix CONFIG_BAUDRATE setting The value of CONFIG_BAUDRATE is treated as string and put as initial value of environment variable. If it begin with '(', it is wrongly parsed to 0 in number. So I removed '(' and ')'. Signed-off-by: Tetsuyuki Kobayashi Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index bd157d9b0f0..14f088fd086 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -46,7 +46,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_BOOTZ -#define CONFIG_BAUDRATE (115200) +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" #define CONFIG_INTEGRATOR #define CONFIG_ARCH_CINTEGRATOR -- cgit v1.3.1 From 38263df864b9414121742318351abff622e90057 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Wed, 25 Jul 2012 18:24:18 +0000 Subject: arm: rmobile: kzm9g: add NFS_TIMEOUT in config file Set NFS_TIMEOUT to 10,000 msec. Signed-off-by: Tetsuyuki Kobayashi Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 14f088fd086..a4d2c374b31 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -150,6 +150,7 @@ #define CONFIG_SMC911X #define CONFIG_SMC911X_BASE (0x10000000) #define CONFIG_SMC911X_32_BIT +#define CONFIG_NFS_TIMEOUT 10000UL /* I2C */ #define CONFIG_CMD_I2C -- cgit v1.3.1 From 67d4d26a0bf2b73d19c32baa54049309a2671225 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Wed, 25 Jul 2012 18:24:19 +0000 Subject: arm: rmobile: kzm9g: remove unrelated config Remove CONFIG_INTEGRATOR and CONFIG_ARCH_CINTEGRATOR. These are not for kzm9g. Signed-off-by: Tetsuyuki Kobayashi Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index a4d2c374b31..bc6dc72de1b 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -48,8 +48,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" -#define CONFIG_INTEGRATOR -#define CONFIG_ARCH_CINTEGRATOR #define CONFIG_BOOTDELAY 3 #define CONFIG_VERSION_VARIABLE -- cgit v1.3.1 From 15f2aa79801c545a3b96f92fadc731e5be0718fd Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 27 Jul 2012 11:40:13 +0900 Subject: arm: rmobile: kzm9g: Add LIBFDT support Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index bc6dc72de1b..15c03c70753 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -36,7 +36,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_L2_OFF +#define CONFIG_L2_OFF +#define CONFIG_OF_LIBFDT #include #define CONFIG_CMDLINE_TAG -- cgit v1.3.1 From af0dd19c2e864bb799e55e42133ebdfc631543c3 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 27 Jul 2012 11:45:14 +0900 Subject: arm: rmobile: kzm9g: remove unrelated config Remove CONFIG_ARM_CORTEXA9. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 15c03c70753..1950f451cf1 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -23,7 +23,6 @@ #undef DEBUG -#define CONFIG_ARM_CORTEXA9 #define CONFIG_RMOBILE #define CONFIG_SH73A0 #define CONFIG_KZM_A9_GT -- cgit v1.3.1 From 2c541df90110e87bb9b241a04089336b06d45716 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 3 Aug 2012 14:21:05 +0900 Subject: arm: rmobile: Add support TMU base timer function Some rmobile SoC has TMU base timer function. This supports TMU. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/Makefile | 3 ++- include/sh_tmu.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index a5228726158..dd0aede92d5 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -27,11 +27,12 @@ LIB = $(obj)lib$(SOC).o SOBJS = lowlevel_init.o COBJS-y += cpu_info.o -COBJS-y += timer.o COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o +COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o +COBJS-$(CONFIG_TMU_TIMER) += $(TOPDIR)/arch/sh/lib/time.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/include/sh_tmu.h b/include/sh_tmu.h index a55d14181d0..96c589da505 100644 --- a/include/sh_tmu.h +++ b/include/sh_tmu.h @@ -47,7 +47,7 @@ struct tmu_regs { }; #endif /* CONFIG_SH3 */ -#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) +#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE) struct tmu_regs { u32 reserved; u8 tstr; -- cgit v1.3.1 From eae6c8abd285ea81cb3c75255c231dce77346f78 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 3 Aug 2012 13:56:52 +0900 Subject: arm: rmobile: kzm9g: Add CONFIG_GLOBAL_TIMER to board config file kzm9g board use global timer. But by commit 813ffda31, timer function of rmobile was changed that global timer might be used, when CONFIG_GLOBAL_TIMER was defined. This add CONFIG_GLOBAL_TIMER to board config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/kzm9g.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 1950f451cf1..3a882e396b2 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -135,6 +135,7 @@ #define CONFIG_SH_GPIO_PFC /* Clock */ +#define CONFIG_GLOBAL_TIMER #define CONFIG_SYS_CLK_FREQ (48000000) #define CONFIG_SYS_CPU_CLK (1196000000) #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ -- cgit v1.3.1 From 1a31ca4a788ca197bad26f64a2c96350478cc9ba Mon Sep 17 00:00:00 2001 From: Hideyuki Sano Date: Wed, 27 Jun 2012 10:35:35 +0900 Subject: arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA board The Armadillo-800EVA board has Renesas R-Mobile R8A7740, 512MB DDR3-SDRAM, Ethernet, and more. This patch supports the following functions: - 512MB DDR3-SDRAM - Serial console (SCIF) - Ethernet MAC(MII) & PHY(SMSC) Signed-off-by: Hideyuki Sano Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- MAINTAINERS | 4 + arch/arm/include/asm/mach-types.h | 13 + board/atmark-techno/armadillo-800eva/Makefile | 46 +++ .../armadillo-800eva/armadillo-800eva.c | 331 +++++++++++++++++++++ boards.cfg | 1 + include/configs/armadillo-800eva.h | 157 ++++++++++ 6 files changed, 552 insertions(+) create mode 100644 board/atmark-techno/armadillo-800eva/Makefile create mode 100644 board/atmark-techno/armadillo-800eva/armadillo-800eva.c create mode 100644 include/configs/armadillo-800eva.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 7c925d4e405..ed854064671 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -994,6 +994,10 @@ Nobuhiro Iwamatsu kzm9g SH73A0 (RMOBILE SoC) +Nobuhiro Iwamatsu + + armadillo-800eva R8A7740 (RMOBILE SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 5f9994ec901..a676b6d9055 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 #ifdef CONFIG_ARCH_EBSA110 @@ -14223,6 +14224,18 @@ extern unsigned int __machine_arch_type; # define machine_is_omap5_sevm() (0) #endif +#ifdef CONFIG_MACH_ARMADILLO800EVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO800EVA +# endif +# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA) +#else +# define machine_is_armadillo800eva() (0) +#endif + #ifdef CONFIG_MACH_KZM9G # ifdef machine_arch_type # undef machine_arch_type diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile new file mode 100644 index 00000000000..9f9618b518b --- /dev/null +++ b/board/atmark-techno/armadillo-800eva/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2012 Nobuhiro Iwamatsu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += armadillo-800eva.o +COBJS := $(COBJS-y) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c new file mode 100644 index 00000000000..2f91666a786 --- /dev/null +++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define s_init_wait(cnt) \ + ({ \ + volatile u32 i = 0x10000 * cnt; \ + while (i > 0) \ + i--; \ + }) + +#define USBCR1 0xE605810A + +void s_init(void) +{ + struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE; + struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE; + struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE; + struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE; + struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE; + struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE; + + /* Watchdog init */ + writew(0xA500, &rwdt0->rwtcsra0); + writew(0xA500, &rwdt1->rwtcsra0); + + /* CPG */ + writel(0xFF800080, &cpg->rmstpcr4); + writel(0xFF800080, &cpg->smstpcr4); + + /* USB clock */ + writel(0x00000080, &cpg->usbckcr); + s_init_wait(1); + + /* USBCR1 */ + writew(0x0710, USBCR1); + + /* FRQCR */ + writel(0x00000000, &cpg->frqcrb); + writel(0x62030533, &cpg->frqcra); + writel(0x208A354E, &cpg->frqcrc); + writel(0x80331050, &cpg->frqcrb); + s_init_wait(1); + + writel(0x00000000, &cpg->frqcrd); + s_init_wait(1); + + /* SUBClk */ + writel(0x0000010B, &cpg->subckcr); + + /* PLL */ + writel(0x00004004, &cpg->pllc01cr); + s_init_wait(1); + + writel(0xa0000000, &cpg->pllc2cr); + s_init_wait(2); + + /* BSC */ + writel(0x0000001B, &bsc->cmncr); + + writel(0x20000000, &dbsc->dbcmd); + writel(0x10009C40, &dbsc->dbcmd); + s_init_wait(1); + + writel(0x00000007, &dbsc->dbkind); + writel(0x0E030A02, &dbsc->dbconf0); + writel(0x00000001, &dbsc->dbphytype); + writel(0x00000000, &dbsc->dbbl); + writel(0x00000006, &dbsc->dbtr0); + writel(0x00000005, &dbsc->dbtr1); + writel(0x00000000, &dbsc->dbtr2); + writel(0x00000006, &dbsc->dbtr3); + writel(0x00080006, &dbsc->dbtr4); + writel(0x00000015, &dbsc->dbtr5); + writel(0x0000000f, &dbsc->dbtr6); + writel(0x00000004, &dbsc->dbtr7); + writel(0x00000018, &dbsc->dbtr8); + writel(0x00000006, &dbsc->dbtr9); + writel(0x00000006, &dbsc->dbtr10); + writel(0x0000000F, &dbsc->dbtr11); + writel(0x0000000D, &dbsc->dbtr12); + writel(0x000000A0, &dbsc->dbtr13); + writel(0x000A0003, &dbsc->dbtr14); + writel(0x00000003, &dbsc->dbtr15); + writel(0x40005005, &dbsc->dbtr16); + writel(0x0C0C0000, &dbsc->dbtr17); + writel(0x00000200, &dbsc->dbtr18); + writel(0x00000040, &dbsc->dbtr19); + writel(0x00000001, &dbsc->dbrnk0); + writel(0x00000110, &dbsc->dbdficnt); + writel(0x00000101, &ddrp->funcctrl); + writel(0x00000001, &ddrp->dllctrl); + writel(0x00000186, &ddrp->zqcalctrl); + writel(0xB3440051, &ddrp->zqodtctrl); + writel(0x94449443, &ddrp->rdctrl); + writel(0x000000C0, &ddrp->rdtmg); + writel(0x00000101, &ddrp->fifoinit); + writel(0x02060506, &ddrp->outctrl); + writel(0x00004646, &ddrp->dqcalofs1); + writel(0x00004646, &ddrp->dqcalofs2); + writel(0x800000aa, &ddrp->dqcalexp); + writel(0x00000000, &ddrp->dllctrl); + writel(0x00000000, DDRPNCNT); + + writel(0x0000000C, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00000002, DDRPNCNT); + + writel(0x0000000C, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00000187, &ddrp->zqcalctrl); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00000010, &dbsc->dbdficnt); + writel(0x02060507, &ddrp->outctrl); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x21009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x11000044, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x2A000000, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x2B000000, &dbsc->dbcmd); + readl(&dbsc->dbwait); + + writel(0x29000004, &dbsc->dbcmd); + readl(&dbsc->dbwait); + + writel(0x28001520, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x03000200, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x000001FF, &dbsc->dbrfcnf0); + writel(0x00010C30, &dbsc->dbrfcnf1); + writel(0x00000000, &dbsc->dbrfcnf2); + + writel(0x00000001, &dbsc->dbrfen); + writel(0x00000001, &dbsc->dbacen); + + /* BSC */ + writel(0x00410400, &bsc->cs0bcr); + writel(0x00410400, &bsc->cs2bcr); + writel(0x00410400, &bsc->cs5bbcr); + writel(0x02CB0400, &bsc->cs6abcr); + + writel(0x00000440, &bsc->cs0wcr); + writel(0x00000440, &bsc->cs2wcr); + writel(0x00000240, &bsc->cs5bwcr); + writel(0x00000240, &bsc->cs6awcr); + + writel(0x00000005, &bsc->rbwtcnt); + writel(0x00000002, &bsc->cs0wcr2); + writel(0x00000002, &bsc->cs2wcr2); + writel(0x00000002, &bsc->cs4wcr2); +} + +#define GPIO_ICCR (0xE60581A0) +#define ICCR_15BIT (1 << 15) /* any time 1 */ +#define IIC0_CONTA (1 << 7) +#define IIC0_CONTB (1 << 6) +#define IIC1_CONTA (1 << 5) +#define IIC1_CONTB (1 << 4) +#define IIC0_PS33E (1 << 1) +#define IIC1_PS33E (1 << 0) +#define GPIO_ICCR_DATA \ + (ICCR_15BIT | \ + IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \ + IIC1_CONTB | IIC0_PS33E | IIC1_PS33E) + +#define MSTPCR1 0xE6150134 +#define TMU0_MSTP125 (1 << 25) +#define I2C0_MSTP116 (1 << 16) + +#define MSTPCR3 0xE615013C +#define I2C1_MSTP323 (1 << 23) +#define GETHER_MSTP309 (1 << 9) + +int board_early_init_f(void) +{ + /* TMU */ + clrbits_le32(MSTPCR1, TMU0_MSTP125); + + /* GETHER */ + clrbits_le32(MSTPCR3, GETHER_MSTP309); + + /* I2C 0/1 */ + clrbits_le32(MSTPCR1, I2C0_MSTP116); + clrbits_le32(MSTPCR3, I2C1_MSTP323); + + /* SCIFA1 */ + r8a7740_pinmux_init(); + gpio_request(GPIO_FN_SCIFA1_RXD, NULL); + gpio_request(GPIO_FN_SCIFA1_TXD, NULL); + + /* IICCR */ + writew(GPIO_ICCR_DATA, GPIO_ICCR); + + return 0; +} + +DECLARE_GLOBAL_DATA_PTR; +int board_init(void) +{ + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA; + /* adress of boot parameters */ + gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7740_pinmux_init(); + + /* GETHER Enable */ + gpio_request(GPIO_FN_ET_CRS, NULL); + gpio_request(GPIO_FN_ET_MDC, NULL); + gpio_request(GPIO_FN_ET_MDIO, NULL); + gpio_request(GPIO_FN_ET_TX_ER, NULL); + gpio_request(GPIO_FN_ET_RX_ER, NULL); + gpio_request(GPIO_FN_ET_ERXD0, NULL); + gpio_request(GPIO_FN_ET_ERXD1, NULL); + gpio_request(GPIO_FN_ET_ERXD2, NULL); + gpio_request(GPIO_FN_ET_ERXD3, NULL); + gpio_request(GPIO_FN_ET_TX_CLK, NULL); + gpio_request(GPIO_FN_ET_TX_EN, NULL); + gpio_request(GPIO_FN_ET_ETXD0, NULL); + gpio_request(GPIO_FN_ET_ETXD1, NULL); + gpio_request(GPIO_FN_ET_ETXD2, NULL); + gpio_request(GPIO_FN_ET_ETXD3, NULL); + gpio_request(GPIO_FN_ET_PHY_INT, NULL); + gpio_request(GPIO_FN_ET_COL, NULL); + gpio_request(GPIO_FN_ET_RX_DV, NULL); + gpio_request(GPIO_FN_ET_RX_CLK, NULL); + + gpio_request(GPIO_PORT18, NULL); /* PHY_RST */ + gpio_direction_output(GPIO_PORT18, 1); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return sh_eth_initialize(bis); +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +int board_late_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/boards.cfg b/boards.cfg index 9599f8e7eed..4f6ae2cdf68 100644 --- a/boards.cfg +++ b/boards.cfg @@ -273,6 +273,7 @@ whistler arm armv7:arm720t whistler nvidia u8500_href arm armv7 u8500 st-ericsson u8500 snowball arm armv7 snowball st-ericsson u8500 kzm9g arm armv7 kzm9g kmc rmobile +armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h new file mode 100644 index 00000000000..2f750999974 --- /dev/null +++ b/include/configs/armadillo-800eva.h @@ -0,0 +1,157 @@ +/* + * Configuation settings for the bonito board + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARMADILLO_800EVA_H +#define __ARMADILLO_800EVA_H + +#undef DEBUG +#define CONFIG_ARMV7 +#define CONFIG_R8A7740 +#define CONFIG_RMOBILE +#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n" +#define CONFIG_SH_GPIO_PFC + +#include + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define BOARD_LATE_INIT + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_NO_L2CACHE +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_USE_ARCH_MEMSET +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_TMU_TIMER +#define CONFIG_SYS_DCACHE_OFF + +/* STACK */ +#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 +#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF1 +#define SCIF0_BASE 0xe6c40000 +#define SCIF1_BASE 0xe6c50000 +#define SCIF2_BASE 0xe6c60000 +#define SCIF4_BASE 0xe6c80000 +#define CONFIG_SCIF_A +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 504 * 1024 * 1024) +#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ + 64 * 1024 * 1024) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE (256) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CONFIG_SYS_TEXT_BASE 0xE80C0000 + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } + +#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x0 +#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000 +#define CONFIG_SH_ETHER_SH7734_MII (0x01) +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 50000000 +#define CONFIG_SYS_TMU_CLK_DIV 4 +#define CONFIG_SYS_HZ 1000 + +#endif /* __ARMADILLO_800EVA_H */ -- cgit v1.3.1 From 09a3be080f04e62659612be26772af34b6126867 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 9 Aug 2012 15:38:47 +0900 Subject: rmobile: armadillo-800eva: Add Support CONFIG_OF_LIBFDT Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/armadillo-800eva.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 2f750999974..5b634fd337b 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -43,6 +43,8 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP + +#define CONFIG_OF_LIBFDT #define BOARD_LATE_INIT #define CONFIG_BAUDRATE 115200 -- cgit v1.3.1 From ca2fbeaaf5143ad7a358c90aec437648b00a4a1a Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 9 Aug 2012 15:39:33 +0900 Subject: rmobile: armadillo-800eva: Add Support NFS and BOOTZ command Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/armadillo-800eva.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 5b634fd337b..d1a0b628f1a 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -43,6 +43,8 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT #define BOARD_LATE_INIT -- cgit v1.3.1 From a085ba6fa631664b203cb444a8c240e90bf38c53 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 9 Aug 2012 15:41:49 +0900 Subject: rmobile: armadillo-800eva: Remove CONFIG_SYS_NO_L2CACHE armadillo-800eva needs this config. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/armadillo-800eva.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index d1a0b628f1a..b4402dd6bb9 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -58,7 +58,6 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_SYS_NO_L2CACHE #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_USE_ARCH_MEMSET -- cgit v1.3.1 From b77026225a319066eaaa11839121a273469a2cf4 Mon Sep 17 00:00:00 2001 From: Gabriel Huau Date: Wed, 2 May 2012 10:48:37 +0000 Subject: ARM : Add support for MINI2440 (s3c2440). Support of the MINI2440 board from FriendlyARM from an old version of u-boot : http://repo.or.cz/r/u-boot-openmoko/mini2440.git Currently, supporting only boot from NOR. Signed-off-by: Gabriel Huau --- MAINTAINERS | 4 + board/friendlyarm/mini2440/Makefile | 44 ++++++++ board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++ board/friendlyarm/mini2440/mini2440.h | 144 ++++++++++++++++++++++++++ boards.cfg | 1 + doc/README.mini2440 | 28 +++++ include/configs/mini2440.h | 186 ++++++++++++++++++++++++++++++++++ 7 files changed, 541 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index ed854064671..110a6c28c95 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -255,6 +255,10 @@ Klaus Heydeck KUP4K MPC855 KUP4X MPC859 +Gabriel Huau + + mini2440 s3c2440 + Gary Jennejohn quad100hd PPC405EP diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 00000000000..b88e5690749 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 00000000000..e97d981cab1 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2009 + * Michel Pollet + * + * (C) Copyright 2012 + * Gabriel Huau + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "mini2440.h" + +DECLARE_GLOBAL_DATA_PTR; + +static inline void pll_delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_early_init_f(void) +{ + struct s3c24x0_clock_power * const clk_power = + s3c24x0_get_base_clock_power(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ + clk_power->clkdivn = CLKDIVN_VAL; + + /* configure UPLL */ + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + /* some delay between MPLL and UPLL */ + pll_delay(100); + + /* configure MPLL */ + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + pll_delay(10000); + + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); + + /* IOMUX Port H : UART Configuration */ + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; + + gpio_direction_output(GPH8, 0); + gpio_direction_output(GPH9, 0); + gpio_direction_output(GPH10, 0); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; + + return 0; +} + +int dram_init(void) +{ + struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); + + /* + * Configuring bus width and timing + * Initialize clocks for each bank 0..5 + * Bank 3 and 4 are used for DM9000 + */ + writel(BANK_CONF, &memctl->bwscon); + writel(B0_CONF, &memctl->bankcon[0]); + writel(B1_CONF, &memctl->bankcon[1]); + writel(B2_CONF, &memctl->bankcon[2]); + writel(B3_CONF, &memctl->bankcon[3]); + writel(B4_CONF, &memctl->bankcon[4]); + writel(B5_CONF, &memctl->bankcon[5]); + + /* Bank 6 and 7 are used for DRAM */ + writel(SDRAM_64MB, &memctl->bankcon[6]); + writel(SDRAM_64MB, &memctl->bankcon[7]); + + writel(MEM_TIMING, &memctl->refresh); + writel(BANKSIZE_CONF, &memctl->banksize); + writel(B6_MRSR, &memctl->mrsrb6); + writel(B7_MRSR, &memctl->mrsrb7); + + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_DM9000 + return dm9000_initialize(bis); +#else + return 0; +#endif +} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h new file mode 100644 index 00000000000..db386eac01f --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.h @@ -0,0 +1,144 @@ +#ifndef __MINI2440_BOARD_CONF_H__ +#define __MINI2440_BOARD_CONF_H__ + +/* PLL Parameters */ +#define CLKDIVN_VAL 7 +#define M_MDIV 0x7f +#define M_PDIV 0x2 +#define M_SDIV 0x1 + +#define U_M_MDIV 0x38 +#define U_M_PDIV 0x2 +#define U_M_SDIV 0x2 + +/* BWSCON */ +#define DW8 0x0 +#define DW16 0x1 +#define DW32 0x2 +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16 + WAIT + UBLB) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* + * Bank Configuration + */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 /* 0clk */ +#define B0_PMC 0x0 /* normal */ + +#define B1_Tacs 0x0 +#define B1_Tcos 0x0 +#define B1_Tacc 0x7 +#define B1_Tcoh 0x0 +#define B1_Tah 0x0 +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x3 /* 4clk */ +#define B3_Tacp 0x0 +#define B3_PMC 0x0 + +#define B4_Tacs 0x0 +#define B4_Tcos 0x3 +#define B4_Tacc 0x7 +#define B4_Tcoh 0x1 +#define B4_Tah 0x3 +#define B4_Tacp 0x0 +#define B4_PMC 0x0 + +#define B5_Tacs 0x0 +#define B5_Tcos 0x0 +#define B5_Tacc 0x7 +#define B5_Tcoh 0x0 +#define B5_Tah 0x0 +#define B5_Tacp 0x0 +#define B5_PMC 0x0 + +/* + * SDRAM Configuration + */ +#define SDRAM_MT 0x3 /* SDRAM */ +#define SDRAM_Trcd 0x0 /* 2clk */ +#define SDRAM_SCAN_9 0x1 /* 9bit */ +#define SDRAM_SCAN_10 0x2 /* 10bit */ + +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) + +/* + * Refresh Parameter + */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x1 /* 3clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x0 /* unused */ +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ + +/* + * MRSR Parameter + */ +#define BL 0x0 +#define BT 0x0 +#define CL 0x3 /* 3 clocks */ +#define TM 0x0 +#define WBL 0x0 + +/* + * BankSize Parameter + */ +#define BK76MAP 0x2 /* 128MB/128MB */ +#define SCLK_EN 0x1 /* SCLK active */ +#define SCKE_EN 0x1 /* SDRAM power down mode enable */ +#define BURST_EN 0x1 /* Burst enable */ + +/* + * Register values + */ +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \ + (B7_BWSCON<<28))) + +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ + (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ + (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ + (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ + (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ + (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ + (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) + +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ + (Trc<<18) + (Tchr<<16) + REFCNT + +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) +#define B6_MRSR (CL<<4) +#define B7_MRSR (CL<<4) + +#endif diff --git a/boards.cfg b/boards.cfg index 4f6ae2cdf68..4e873d6898d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -67,6 +67,7 @@ mx1ads arm arm920t - - scb9328 arm arm920t - - imx cm4008 arm arm920t - - ks8695 cm41xx arm arm920t - - ks8695 +mini2440 arm arm920t mini2440 friendlyarm s3c24x0 VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 omap1510inn arm arm925t - ti diff --git a/doc/README.mini2440 b/doc/README.mini2440 new file mode 100644 index 00000000000..311ca52862a --- /dev/null +++ b/doc/README.mini2440 @@ -0,0 +1,28 @@ +U-Boot for FriendlyARM Mini2440 (s3c2440) + +This file contains information for the port of U-Boot to FriendlyARM +mini2440 + +All information about the board can be found on : +http://www.friendlyarm.net/products/mini2440 + +To build u-boot : ./MAKEALL mini2440 + +Overview : +-------- +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 +systems. It's a low cost board. + +Boot Methods : +------------ +Mini2440 can boot from NOR or NAND. + +Build : +----- +./MAKEALL mini2440 + +or + +make mini2440_config +make diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h new file mode 100644 index 00000000000..980b4a5746b --- /dev/null +++ b/include/configs/mini2440.h @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Gary Jennejohn + * David Mueller + * + * (C) Copyright 2009-2010 + * Michel Pollet + * + * (C) Copyright 2012 + * Gabriel Huau + * + * Configuation settings for the MINI2440 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_S3C2440_GPIO + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_MINI2440 /* on a MIN2440 Board */ + +#define MACH_TYPE_MINI2440 1999 +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 + +/* + * We don't use lowlevel_init + */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * input clock of PLL + */ +/* MINI2440 has 12.0000MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_DM9000 +#define CONFIG_DRIVER_DM9000_NO_EEPROM +#define CONFIG_DM9000_BASE 0x20000300 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) + +/* + * select serial console configuration + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 + +/* + * allow to overwrite serial and ethaddr + */ +#define CONFIG_ENV_OVERWRITE + +/* + * Command definition + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PORTIO +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SAVES + +/* + * Miscellaneous configurable options + */ +#define CONFIG_LONGHELP +#define CONFIG_SYS_PROMPT "MINI2440 => " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x30000000 +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x32000000 + +/* boot parameters address */ +#define CONFIG_BOOT_PARAM_ADDR 0x30000100 + +/* + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need + * it to wrap 100 times (total 1562500) to get 1 sec. + */ +#define CONFIG_SYS_HZ 1562500 + +/* + * valid baudrates + */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CONFIG_SYS_FLASH_BASE 0x0 + +/* + * Stack should be on the SRAM because + * DRAM is not init + */ +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) + +/* + * NOR FLASH organization + * Now uses the standard CFI interface + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE 0x0 +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* 512 * 4096 sectors, or 32 * 64k blocks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_FLASH_SHOW_PROGRESS 1 + +/* + * Config for NOR flash + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_MY_ENV_OFFSET 0x40000 +/* addr of environment */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) +/* 16k Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000 + +/* ATAG configuration */ +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 8e6224364e85950cc308f6ab19eacf957abd94de Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Thu, 6 Sep 2012 10:51:41 +0000 Subject: lacie_kw: add support for EFI partitions Defines CONFIG_EFI_PARTITION for LaCie boards. Additionally this patch defines CONFIG_DOS_PARTITION. Note that this definition is implicit in mv_common.h when CONFIG_CMD_USB is enabled. Signed-off-by: Simon Guinot --- include/configs/lacie_kw.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index c35c2db30c9..08aec042c37 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -129,6 +129,12 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ #endif /* CONFIG_CMD_I2C */ +/* + * Partition support + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + /* * File systems support */ -- cgit v1.3.1 From 37235496950360eb695214683f02f5975b010bd1 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Thu, 6 Sep 2012 10:51:42 +0000 Subject: ARM: add support for Network Space v2 Lite and Mini This patch adds support for the LaCie boards Network Space v2 (Lite and Mini). This two boards are derived from the Network Space v2 and a lot of hardware caracteristics are shared. - CPU: Marvell 88F6192 800Mhz - SDRAM memory: 128MB DDR2 200Mhz - 1 SATA port: internal - Gigabit ethernet: PHY Marvell 88E1318 - Flash memory: SPI NOR 512KB (Macronix MX25L4005A) - i2c EEPROM: 512 bytes (24C04 type) - 2 USB2 ports (Lite only): host and host/device - 1 push button - 1 SATA LED (bi-color, blue and red) Signed-off-by: Simon Guinot --- board/LaCie/common/common.c | 36 ++++++- board/LaCie/common/common.h | 1 + board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 162 ++++++++++++++++++++++++++++++ board/LaCie/netspace_v2/netspace_v2.c | 4 + boards.cfg | 2 + include/configs/lacie_kw.h | 28 +++++- 6 files changed, 226 insertions(+), 7 deletions(-) create mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg (limited to 'include') diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index 78d0edc66d8..a62bf9f1896 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -13,10 +13,11 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +#define MII_MARVELL_PHY_PAGE 22 + #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5) @@ -31,15 +32,44 @@ void mv_phy_88e1116_init(const char *name, u16 phyaddr) * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); if (miiphy_reset(name, phyaddr) == 0) printf("88E1116 Initialized on %s\n", name); } + +void mv_phy_88e1318_init(const char *name, u16 phyaddr) +{ + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* + * Set control mode 4 for LED[0]. + */ + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); + miiphy_read(name, phyaddr, 16, ®); + reg |= 0xf; + miiphy_write(name, phyaddr, 16, reg); + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); + + if (miiphy_reset(name, phyaddr) == 0) + printf("88E1318 Initialized on %s\n", name); +} #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h index 2edd5abbcd0..85e433c9316 100644 --- a/board/LaCie/common/common.h +++ b/board/LaCie/common/common.h @@ -12,6 +12,7 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) void mv_phy_88e1116_init(const char *name, u16 phyaddr); +void mv_phy_88e1318_init(const char *name, u16 phyaddr); #endif #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) int lacie_read_mac_address(uchar *mac); diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg new file mode 100644 index 00000000000..d008eb0ab0b --- /dev/null +++ b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x34143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000DDDD # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 68e8a770c79..101a80a70ab 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -107,7 +107,11 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { +#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) + mv_phy_88e1318_init("egiga0", 0); +#else mv_phy_88e1116_init("egiga0", 8); +#endif } #endif diff --git a/boards.cfg b/boards.cfg index 4f6ae2cdf68..d6813677e23 100644 --- a/boards.cfg +++ b/boards.cfg @@ -161,7 +161,9 @@ kmcoge5un arm arm926ejs km_arm keymile portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 +netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2 netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 +netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2 netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 08aec042c37..878d2a32a10 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -27,6 +27,14 @@ #elif defined(CONFIG_NETSPACE_V2) #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 #define CONFIG_IDENT_STRING " NS v2" +#elif defined(CONFIG_NETSPACE_LITE_V2) +#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 +#define CONFIG_IDENT_STRING " NS v2 Lite" +#elif defined(CONFIG_NETSPACE_MINI_V2) +#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 +#define CONFIG_IDENT_STRING " NS v2 Mini" #elif defined(CONFIG_NETSPACE_MAX_V2) #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 #define CONFIG_IDENT_STRING " NS Max v2" @@ -41,8 +49,13 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ -#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_KIRKWOOD /* SoC Family Name */ +/* SoC name */ +#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) +#define CONFIG_KW88F6192 +#else +#define CONFIG_KW88F6281 +#endif #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* @@ -56,7 +69,9 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE +#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */ #define CONFIG_CMD_USB +#endif /* * Core clock definition @@ -68,9 +83,14 @@ */ #define CONFIG_NR_DRAM_BANKS 1 -#ifdef CONFIG_INETSPACE_V2 -/* Different SDRAM configuration and size for Internet Space v2 */ +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ +#if defined(CONFIG_INETSPACE_V2) #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg +#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg #endif /* -- cgit v1.3.1 From ee8f6d2370744e07a06ed1bba245258015153049 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Thu, 6 Sep 2012 10:51:43 +0000 Subject: ARM: add support for d2 Network v2 This patch adds support for the LaCie board d2 Network v2 which share a lot of hardware caracteristics with the 2Big Network v2. - CPU: Marvell 88F6281 1200Mhz - SDRAM memory: 256MB DDR2 400Mhz - 2 SATA ports: internal and eSATA - Gigabit ethernet: PHY Marvell 88E1116R - Flash memory: SPI NOR 512KB (Macronix MX25L4005A) - i2c EEPROM: 512 bytes (24C04 type) - 2 USB2 ports: host and host/device - 1 push button - 1 power switch - 1 SATA LED (bi-color, blue and red) Signed-off-by: Simon Guinot --- boards.cfg | 1 + include/configs/lacie_kw.h | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index d6813677e23..5890d6b8e3d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -159,6 +159,7 @@ kmnusa arm arm926ejs km_arm keymile mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 +d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2 diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 878d2a32a10..09b5798d578 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -38,6 +38,9 @@ #elif defined(CONFIG_NETSPACE_MAX_V2) #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 #define CONFIG_IDENT_STRING " NS Max v2" +#elif defined(CONFIG_D2NET_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 +#define CONFIG_IDENT_STRING " D2 v2" #elif defined(CONFIG_NET2BIG_V2) #define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 #define CONFIG_IDENT_STRING " 2Big v2" @@ -108,7 +111,9 @@ #define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_IDE_MAXDEVICE 1 -#if defined(CONFIG_NET2BIG_V2) +#if defined(CONFIG_D2NET_V2) +#define CONFIG_SYS_PROMPT "d2v2> " +#elif defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_PROMPT "2big2> " #else #define CONFIG_SYS_PROMPT "ns2> " @@ -128,7 +133,8 @@ */ #ifdef CONFIG_MVSATA_IDE #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2) +#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ + defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif #endif /* CONFIG_MVSATA_IDE */ -- cgit v1.3.1 From 9b914727ce5c9016ad93d4bcdaef48be761a4cef Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Wed, 5 Sep 2012 08:01:25 +0000 Subject: kirkwood: add support for Iomega iConnect board Add support for new board iConnect from Iomega. More information about the device can be found here: http://go.iomega.com/en/products/network-storage-desktop/wireless-data-station/network-hard-drive-iconnect/?partner=4735 Signed-off-by: Luka Perkov Tested-by: Wojciech Dubowik Tested-by: Tim Fletcher --- MAINTAINERS | 1 + board/iomega/iconnect/Makefile | 43 ++++++++++ board/iomega/iconnect/iconnect.c | 107 ++++++++++++++++++++++++ board/iomega/iconnect/iconnect.h | 39 +++++++++ board/iomega/iconnect/kwbimage.cfg | 165 +++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/iconnect.h | 129 +++++++++++++++++++++++++++++ 7 files changed, 485 insertions(+) create mode 100644 board/iomega/iconnect/Makefile create mode 100644 board/iomega/iconnect/iconnect.c create mode 100644 board/iomega/iconnect/iconnect.h create mode 100644 board/iomega/iconnect/kwbimage.cfg create mode 100644 include/configs/iconnect.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index ed854064671..2885dbe7ea1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -799,6 +799,7 @@ Veli-Pekka Peltola Luka Perkov ib62x0 ARM926EJS + iconnect ARM926EJS Dave Peverley diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile new file mode 100644 index 00000000000..f77fcfb9901 --- /dev/null +++ b/board/iomega/iconnect/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := iconnect.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c new file mode 100644 index 00000000000..6ee2128aab8 --- /dev/null +++ b/board/iomega/iconnect/iconnect.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik + * Luka Perkov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include "iconnect.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, /* Reset signal */ + MPP7_GPO, + MPP8_TW_SDA, /* I2C */ + MPP9_TW_SCK, /* I2C */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* Reset button */ + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GPIO, /* OTB button */ + MPP36_AUDIO_SPDIFI, + MPP37_AUDIO_SPDIFO, + MPP38_GPIO, + MPP39_TDM_SPI_CS0, + MPP40_TDM_SPI_SCK, + MPP41_GPIO, /* LED brightness */ + MPP42_GPIO, /* LED power (blue) */ + MPP43_GPIO, /* LED power (red) */ + MPP44_GPIO, /* LED USB 1 */ + MPP45_GPIO, /* LED USB 2 */ + MPP46_GPIO, /* LED USB 3 */ + MPP47_GPIO, /* LED USB 4 */ + MPP48_GPIO, /* LED OTB */ + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h new file mode 100644 index 00000000000..2fb3e5ed8f2 --- /dev/null +++ b/board/iomega/iconnect/iconnect.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik + * Luka Perkov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ICONNECT_H +#define __ICONNECT_H + +#define ICONNECT_OE_LOW (~(1 << 7)) +#define ICONNECT_OE_HIGH (~(1 << 10)) +#define ICONNECT_OE_VAL_LOW (0) +#define ICONNECT_OE_VAL_HIGH (1 << 10) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __ICONNECT_H */ diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg new file mode 100644 index 00000000000..6c9dfe3d31d --- /dev/null +++ b/board/iomega/iconnect/kwbimage.cfg @@ -0,0 +1,165 @@ +# +# (C) Copyright 2009-2012 +# Wojciech Dubowik +# Luka Perkov +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) +# bit23-14: 0x0, +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required +# bit29-26: 0x0, +# bit31-30: 0x1, + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit4: 0x0, addr/cmd in smame cycle +# bit5: 0x0, clk is driven during self refresh, we don't care for APX +# bit6: 0x0, use recommended falling edge of clk for addr/cmd +# bit14: 0x0, input buffer always powered up +# bit18: 0x1, cpu lock transaction enabled +# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 0x3, required +# bit31: 0x0, no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11-8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: 0x0, required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width (x8) +# bit3-2: 11, Cs0size (1Gb) +# bit5-4: 00, Cs1width (x8) +# bit7-6: 11, Cs1size (1Gb) +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0x0, required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0x0, required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0x0, required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 0x2, BurstLen=2 required +# bit3: 0x0, BurstType=0 required +# bit6-4: 0x4, CL=5 +# bit7: 0x0, TestMode=0 normal +# bit8: 0x0, DLL reset=0 normal +# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit12: 0x0, PD must be zero +# bit31-13: 0x0, required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 0x0, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 0x0, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0x0, required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 0x7, required +# bit3: 0x1, MBUS Burst Chop disabled +# bit6-4: 0x7, required +# bit7: 0x0, +# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0x0, no half clock cycle addition to dataout +# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf, required +# bit31-16: 0x0, required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 0x1, Window enabled +# bit1: 0x0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above +# bit3-2: 0x1, ODT1 active NEVER! +# bit31-4: 0x0, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +# bit0: 0x1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 5890d6b8e3d..6f1c7ba0786 100644 --- a/boards.cfg +++ b/boards.cfg @@ -151,6 +151,7 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood +iconnect arm arm926ejs - iomega kirkwood lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h new file mode 100644 index 00000000000..2b523c9fc97 --- /dev/null +++ b/include/configs/iconnect.h @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2009-2012 + * Wojciech Dubowik + * Luka Perkov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _CONFIG_ICONNECT_H +#define _CONFIG_ICONNECT_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING " Iomega iConnect" + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Machine type + */ +#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "iconnect => " + +/* + * Environment variables configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part rootfs; " \ + "ubifsmount rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "bootm 0x800000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(rootfs)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 11 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_ICONNECT_H */ -- cgit v1.3.1 From 84fb04b686672cc655cd8f6dee7fc3a9d56e7de5 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 21 Sep 2012 14:57:12 +0000 Subject: edminiv2: increase malloc len to 256K Malloc len of 128K caused a warning from ehci_hcd asking for more. Signed-off-by: Albert ARIBAUD Acked-by: Prafulla Wadaskar --- include/configs/edminiv2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index f2cfaf8350e..adb505e1346 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -222,7 +222,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ /* * Other required minimal configurations -- cgit v1.3.1 From be3e8be0a7cd07c14647bd30ad87ce2540f3e4c7 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Thu, 16 Aug 2012 01:25:20 +0000 Subject: km_kirkwood: enable MV88E6352_SWITCH support for kmnusa This is required to configure the external 88e6352 switch on nusa. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar Acked-by: Prafulla Wadaskar --- include/configs/km_kirkwood.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index fba181fffa1..762cc10b885 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -62,6 +62,8 @@ #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352 +#define CONFIG_MV88E6352_SWITCH +#define CONFIG_KM_MVEXTSW_ADDR 0x10 /* KM_MGCOGE3UN */ #elif defined(CONFIG_KM_MGCOGE3UN) -- cgit v1.3.1 From 995b72ddda77ffa471930fdc1c3e587d5a6b4aa8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 30 May 2012 22:59:08 +0000 Subject: ARM: Add X600 board support (SPEAr600 based) This patch adds support for the X600 SPEAr600 based board. Its also the first SPEAr600 board that uses the newly introduced SPEAr600 SPL support. Xloader is not necessary any more. By using the new "u-boot.spr" make target, one image will generated containing both, U-Boot SPL (with mkimage header as needed by the SPEAr BootROM, and the main U-Boot with mkimage header. Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar --- MAINTAINERS | 2 + board/spear/x600/Makefile | 47 +++++++ board/spear/x600/fpga.c | 280 ++++++++++++++++++++++++++++++++++++++ board/spear/x600/fpga.h | 23 ++++ board/spear/x600/x600.c | 124 +++++++++++++++++ boards.cfg | 1 + include/configs/x600.h | 339 ++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 816 insertions(+) create mode 100644 board/spear/x600/Makefile create mode 100644 board/spear/x600/fpga.c create mode 100644 board/spear/x600/fpga.h create mode 100644 board/spear/x600/x600.c create mode 100644 include/configs/x600.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 842ff57ea5c..45351cc23e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -857,6 +857,8 @@ John Rigby Stefan Roese + x600 ARM926EJS (spear600 Soc) + pdnb3 xscale/ixp scpu xscale/ixp diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile new file mode 100644 index 00000000000..8c4e7e2987c --- /dev/null +++ b/board/spear/x600/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifndef CONFIG_SPL_BUILD +COBJS := fpga.o $(BOARD).o +endif +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c new file mode 100644 index 00000000000..85eb31be7bc --- /dev/null +++ b/board/spear/x600/fpga.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * FPGA program pin configuration on X600: + * + * Only PROG and DONE are connected to GPIOs. INIT is not connected to the + * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use + * 16bit serial writes via this SSP port to write the data bits into the + * FPGA. + */ +#define CONFIG_SYS_FPGA_PROG 2 +#define CONFIG_SYS_FPGA_DONE 3 + +/* + * Set the active-low FPGA reset signal. + */ +static void fpga_reset(int assert) +{ + /* + * On x600 we have no means to toggle the FPGA reset signal + */ + debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert); +} + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +static int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); + + gpio_set_value(CONFIG_SYS_FPGA_PROG, assert); + + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +static int fpga_init_fn(int cookie) +{ + static int state; + + debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state); + + /* + * On x600, the FPGA INIT signal is not connected to the SoC. + * We can't read the INIT status. Let's return the "correct" + * INIT signal state generated via a local state-machine. + */ + if (++state == 1) { + return 1; + } else { + state = 0; + return 0; + } +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +static int fpga_done_fn(int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + + /* + * Wait for Tx-FIFO to become empty before looking for DONE + */ + while (!(readl(&ssp->sspsr) & SSPSR_TFE)) + ; + + if (gpio_get_value(CONFIG_SYS_FPGA_DONE)) + return 1; + else + return 0; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +static int fpga_pre_config_fn(int cookie) +{ + debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); + fpga_reset(TRUE); + + return 0; +} + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +static int fpga_post_config_fn(int cookie) +{ + int rc = 0; + + debug("%s:%d: FPGA post configuration\n", __func__, __LINE__); + + fpga_reset(TRUE); + udelay(100); + fpga_reset(FALSE); + udelay(100); + + return rc; +} + +static int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + /* + * No dedicated clock signal on x600 (data & clock generated) + * in SSP interface. So we don't have to do anything here. + */ + return assert_clk; +} + +static int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + static int count; + static u16 data; + + /* + * First collect 16 bits of data + */ + data = data << 1; + if (assert_write) + data |= 1; + + /* + * If 16 bits are not available, return for more bits + */ + count++; + if (count != 16) + return assert_write; + + count = 0; + + /* + * Wait for Tx-FIFO to become ready + */ + while (!(readl(&ssp->sspsr) & SSPSR_TNF)) + ; + + /* Send 16 bits to FPGA via SSP bus */ + writel(data, &ssp->sspdr); + + return assert_write; +} + +static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_post_config_fn, +}; + +static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) +}; + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +static void fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__); + fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ +} + +static int expi_setup(int freq) +{ + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + int pll2_m, pll2_n, pll2_p, expi_x, expi_y; + + pll2_m = (freq * 2) / 1000; + pll2_n = 15; + pll2_p = 1; + expi_x = 1; + expi_y = 2; + + /* + * Disable reset, Low compression, Disable retiming, Enable Expi, + * Enable soft reset, DMA, PLL2, Internal + */ + writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST | + EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 | + EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24), + &misc->expi_clk_cfg); + + /* + * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters, + * Enable PLL2, Disable reset + */ + writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq); + writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE | + PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl); + + /* + * Disable soft reset + */ + clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST); + + return 0; +} + +/* + * Initialize the fpga + */ +int x600_init_fpga(void) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Enable SSP2 clock */ + writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB, + &misc->periph1_clken); + + /* Set EXPI clock to 45 MHz */ + expi_setup(45000); + + /* Configure GPIO directions */ + gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0); + gpio_direction_input(CONFIG_SYS_FPGA_DONE); + + writel(SSPCR0_DSS_16BITS, &ssp->sspcr0); + writel(SSPCR1_SSE, &ssp->sspcr1); + + /* + * Set lowest prescale divisor value (CPSDVSR) of 2 for max download + * speed. + * + * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1)) + * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz. + */ + writel(2, &ssp->sspcpsr); + + fpga_init(); + fpga_serialslave_init(); + + debug("%s:%d: Adding fpga 0\n", __func__, __LINE__); + fpga_add(fpga_xilinx, &fpga[0]); + + return 0; +} diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h new file mode 100644 index 00000000000..2b1855716bd --- /dev/null +++ b/board/spear/x600/fpga.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +int x600_init_fpga(void); diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c new file mode 100644 index 00000000000..96ec0ad8a5d --- /dev/null +++ b/board/spear/x600/x600.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fpga.h" + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +int board_init(void) +{ + /* + * X600 is equipped with an M41T82 RTC. This RTC has the + * HT bit (Halt Update), which needs to be cleared upon + * power-up. Otherwise the RTC is halted. + */ + rtc_reset(); + + return spear_board_init(MACH_TYPE_SPEAR600); +} + +int board_late_init(void) +{ + /* + * Monitor and env protection on by default + */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + + CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* Init FPGA subsystem */ + x600_init_fpga(); + + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +void board_nand_init(void) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) + fsmc_nand_init(nand); +} + +int designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + /* Extended PHY control 1, select GMII */ + mii_write(dev, phy_addr, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + dw_reset_phy(dev); + + /* Enable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + mii_write(dev, phy_addr, 17, 0x09ff); + mii_write(dev, phy_addr, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + mii_write(dev, phy_addr, 16, 0xe0ea); + + /* Disable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0000); + + /* Enable clock output pin */ + mii_write(dev, phy_addr, 18, 0x0049); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + PHY_INTERFACE_MODE_GMII) >= 0) + ret++; + + return ret; +} diff --git a/boards.cfg b/boards.cfg index f9df74b2652..5eb35c95940 100644 --- a/boards.cfg +++ b/boards.cfg @@ -218,6 +218,7 @@ spear600 arm arm926ejs spear600 spear spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand +x600 arm arm926ejs - spear spear x600 versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB diff --git a/include/configs/x600.h b/include/configs/x600.h new file mode 100644 index 00000000000..3082aaa1e63 --- /dev/null +++ b/include/configs/x600.h @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 /* SPEAr600 SoC */ +#define CONFIG_X600 /* on X600 board */ + +#include + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK 8300000 + +#define CONFIG_SYS_TEXT_BASE 0x00800040 +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +/* Reserve 8KiB for SPL */ +#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x60000 + +#define CONFIG_ENV_IS_IN_FLASH + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* NOR FLASH config options */ +#define CONFIG_ST_SMI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* NAND FLASH config options */ +#define CONFIG_NAND_FSMC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE +#define CONFIG_MTD_ECC_SOFT +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* UBI/UBI config options */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE + +/* Ethernet config options */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#define CONFIG_SPEAR_GPIO + +/* I2C config options */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_I2C_CHIPADDRESS 0x50 + +#define CONFIG_RTC_M41T62 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* FPGA config options */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 + +/* + * Command support defines + */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_LZO + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * U-Boot Environment placing definitions. + */ +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x02000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "X600> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_64BIT_VSPRINTF + +/* Use last 2 lwords in internal SRAM for bootcounter */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 + +#define CONFIG_HOSTNAME x600 +#define CONFIG_UBI_PART ubi0 +#define CONFIG_UBIFS_VOLUME rootfs + +#define xstr(s) str(s) +#define str(s) #s + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr=1000000\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ + "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ + " ${filesize};" \ + "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "upd=run load update\0" \ + "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ + "part=" xstr(CONFIG_UBI_PART) "\0" \ + "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ + "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ + "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ + " ${filesize}\0" \ + "upd_ubifs=run load_ubifs update_ubifs\0" \ + "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ + "ubi create ${vol} 4000000\0" \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk-4.2/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "boot_part=0\0" \ + "altbootcmd=if test $boot_part -eq 0;then " \ + "echo Switching to partition 1!;" \ + "setenv boot_part 1;" \ + "else; " \ + "echo Switching to partition 0!;" \ + "setenv boot_part 0;" \ + "fi;" \ + "saveenv;boot\0" \ + "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ + "root=ubi0:rootfs rootfstype=ubifs\0" \ + "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel_fs=/boot/uImage \0" \ + "kernel_addr=1000000\0" \ + "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_addr=1800000\0" \ + "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ + "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ + "${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "net_nfs=run load_dtb load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ + " addcon addmisc addmtd;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \ + "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ + "ubifsload ${dtb_addr} ${dtb_fs};\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ + "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ + "bootcmd=run nand_ubifs\0" \ + "\0" + +/* Stack sizes */ +#define CONFIG_STACKSIZE (512 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * SPL related defines + */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0xd2800b00 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ +#define CONFIG_SPL_NO_PRINTF + +/* + * Please select/define only one of the following + * Each definition corresponds to a supported DDR chip. + * DDR configuration is based on the following selection + */ +#define CONFIG_DDR_MT47H64M16 1 +#define CONFIG_DDR_MT47H32M16 0 +#define CONFIG_DDR_MT47H128M8 0 + +/* + * Synchronous/Asynchronous operation of DDR + * + * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation + * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation + * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation + */ +#define CONFIG_DDR_2HCLK 1 +#define CONFIG_DDR_HCLK 0 +#define CONFIG_DDR_PLL2 0 + +/* + * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported + * or not. Modify/Add to only these macros to define new boot types + */ +#define USB_BOOT_SUPPORTED 0 +#define PCIE_BOOT_SUPPORTED 0 +#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 0 +#define TFTP_BOOT_SUPPORTED 0 +#define UART_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 +#define MMC_BOOT_SUPPORTED 0 + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 194846f398ef38d5e24c239d264a3f637c685e53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Sep 2012 00:55:24 +0000 Subject: serial: Add Zynq serial driver The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek CC: Joe Hershberger CC: Marek Vasut Acked-by: Marek Vasut --- common/serial.c | 8 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_zynq.c | 247 +++++++++++++++++++++++++++++++++++++++++++ include/serial.h | 5 + 4 files changed, 261 insertions(+) create mode 100644 drivers/serial/serial_zynq.c (limited to 'include') diff --git a/common/serial.c b/common/serial.c index 75cc1bb71c2..4f2bc7ffb9d 100644 --- a/common/serial.c +++ b/common/serial.c @@ -122,6 +122,14 @@ void serial_initialize(void) serial_register(&uartlite_serial3_device); # endif /* XILINX_UARTLITE_BASEADDR3 */ #endif /* CONFIG_XILINX_UARTLITE */ +#if defined(CONFIG_ZYNQ_SERIAL) +# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + serial_register(&uart_zynq_serial0_device); +# endif +# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + serial_register(&uart_zynq_serial1_device); +# endif +#endif serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 65d0f234e7e..dfc22a4b36c 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c new file mode 100644 index 00000000000..38322367b42 --- /dev/null +++ b/drivers/serial/serial_zynq.c @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2012 Michal Simek + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ + +#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ +#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ +#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ +#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ + +#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ + +/* Some clock/baud constants */ +#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ +#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ + +struct uart_zynq { + u32 control; /* Control Register [8:0] */ + u32 mode; /* Mode Register [10:0] */ + u32 reserved1[4]; + u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 reserved2[4]; + u32 channel_sts; /* Channel Status [11:0] */ + u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ +}; + +static struct uart_zynq *uart_zynq_ports[2] = { +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, +#endif +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#endif +}; + +struct uart_zynq_params { + u32 baudrate; + u32 clock; +}; + +static struct uart_zynq_params uart_zynq_ports_param[2] = { +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) + [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, + [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, +#endif +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) + [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, + [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, +#endif +}; + +/* Set up the baud rate in gd struct */ +static void uart_zynq_serial_setbrg(const int port) +{ + /* Calculation results. */ + unsigned int calc_bauderror, bdiv, bgen; + unsigned long calc_baud = 0; + unsigned long baud = uart_zynq_ports_param[port].baudrate; + unsigned long clock = uart_zynq_ports_param[port].clock; + struct uart_zynq *regs = uart_zynq_ports[port]; + + /* master clock + * Baud rate = ------------------ + * bgen * (bdiv + 1) + * + * Find acceptable values for baud generation. + */ + for (bdiv = 4; bdiv < 255; bdiv++) { + bgen = clock / (baud * (bdiv + 1)); + if (bgen < 2 || bgen > 65535) + continue; + + calc_baud = clock / (bgen * (bdiv + 1)); + + /* + * Use first calculated baudrate with + * an acceptable (<3%) error + */ + if (baud > calc_baud) + calc_bauderror = baud - calc_baud; + else + calc_bauderror = calc_baud - baud; + if (((calc_bauderror * 100) / baud) < 3) + break; + } + + writel(bdiv, ®s->baud_rate_divider); + writel(bgen, ®s->baud_rate_gen); +} + +/* Initialize the UART, with...some settings. */ +static int uart_zynq_serial_init(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + if (!regs) + return -1; + + /* RX/TX enabled & reset */ + writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ + ZYNQ_UART_CR_RXRST, ®s->control); + writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ + uart_zynq_serial_setbrg(port); + + return 0; +} + +static void uart_zynq_serial_putc(const char c, const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + + if (c == '\n') { + writel('\r', ®s->tx_rx_fifo); + while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + } + writel(c, ®s->tx_rx_fifo); +} + +static void uart_zynq_serial_puts(const char *s, const int port) +{ + while (*s) + uart_zynq_serial_putc(*s++, port); +} + +static int uart_zynq_serial_tstc(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; +} + +static int uart_zynq_serial_getc(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + while (!uart_zynq_serial_tstc(port)) + WATCHDOG_RESET(); + return readl(®s->tx_rx_fifo); +} + +#if !defined(CONFIG_SERIAL_MULTI) +int serial_init(void) +{ + return uart_zynq_serial_init(0); +} + +void serial_setbrg(void) +{ + uart_zynq_serial_setbrg(0); +} + +void serial_putc(const char c) +{ + uart_zynq_serial_putc(c, 0); +} + +void serial_puts(const char *s) +{ + uart_zynq_serial_puts(s, 0); +} + +int serial_getc(void) +{ + return uart_zynq_serial_getc(0); +} + +int serial_tstc(void) +{ + return uart_zynq_serial_tstc(0); +} +#else +/* Multi serial device functions */ +#define DECLARE_PSSERIAL_FUNCTIONS(port) \ + int uart_zynq##port##_init(void) \ + { return uart_zynq_serial_init(port); } \ + void uart_zynq##port##_setbrg(void) \ + { return uart_zynq_serial_setbrg(port); } \ + int uart_zynq##port##_getc(void) \ + { return uart_zynq_serial_getc(port); } \ + int uart_zynq##port##_tstc(void) \ + { return uart_zynq_serial_tstc(port); } \ + void uart_zynq##port##_putc(const char c) \ + { uart_zynq_serial_putc(c, port); } \ + void uart_zynq##port##_puts(const char *s) \ + { uart_zynq_serial_puts(s, port); } + +/* Serial device descriptor */ +#define INIT_PSSERIAL_STRUCTURE(port, __name) { \ + .name = __name, \ + .init = uart_zynq##port##_init, \ + .uninit = NULL, \ + .setbrg = uart_zynq##port##_setbrg, \ + .getc = uart_zynq##port##_getc, \ + .tstc = uart_zynq##port##_tstc, \ + .putc = uart_zynq##port##_putc, \ + .puts = uart_zynq##port##_puts, \ +} + +DECLARE_PSSERIAL_FUNCTIONS(0); +struct serial_device uart_zynq_serial0_device = + INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); +DECLARE_PSSERIAL_FUNCTIONS(1); +struct serial_device uart_zynq_serial1_device = + INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + +__weak struct serial_device *default_serial_console(void) +{ + if (uart_zynq_ports[0]) + return &uart_zynq_serial0_device; + if (uart_zynq_ports[1]) + return &uart_zynq_serial1_device; + + return NULL; +} +#endif diff --git a/include/serial.h b/include/serial.h index d76d6dfb6d4..826b4884963 100644 --- a/include/serial.h +++ b/include/serial.h @@ -90,6 +90,11 @@ extern struct serial_device bfin_serial2_device; extern struct serial_device bfin_serial3_device; #endif +#if defined(CONFIG_ZYNQ_SERIAL) +extern struct serial_device uart_zynq_serial0_device; +extern struct serial_device uart_zynq_serial1_device; +#endif + extern void serial_register(struct serial_device *); extern void serial_initialize(void); extern void serial_stdio_init(void); -- cgit v1.3.1 From f22651cfc422a51253f2d475343373f82cf7f929 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 28 Sep 2012 09:56:37 +0000 Subject: xilinx: Add new Zynq board Add support for Xilinx Zynq board. Signed-off-by: Michal Simek Acked-by: Marek Vasut CC: Joe Hershberger --- MAINTAINERS | 4 ++ board/xilinx/zynq/Makefile | 54 ++++++++++++++++++++++ board/xilinx/zynq/board.c | 54 ++++++++++++++++++++++ boards.cfg | 1 + include/configs/zynq.h | 112 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 225 insertions(+) create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 include/configs/zynq.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 45351cc23e0..7004716e416 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -897,6 +897,10 @@ Matt Sealey Bo Shen at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC) +Michal Simek + + zynq ARM ARMV7 (Zynq SoC) + Nick Thompson da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile new file mode 100644 index 00000000000..ef4faa125ed --- /dev/null +++ b/board/xilinx/zynq/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := board.o + +COBJS := $(sort $(COBJS-y)) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c new file mode 100644 index 00000000000..8ed75c3d383 --- /dev/null +++ b/board/xilinx/zynq/board.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2012 Michal Simek + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + icache_enable(); + + return 0; +} + + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0) + ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0); +#endif + + return ret; +} +#endif + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 5eb35c95940..3a2cf324e29 100644 --- a/boards.cfg +++ b/boards.cfg @@ -280,6 +280,7 @@ u8500_href arm armv7 u8500 st-eric snowball arm armv7 snowball st-ericsson u8500 kzm9g arm armv7 kzm9g kmc rmobile armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile +zynq arm armv7 zynq xilinx zynq actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/configs/zynq.h b/include/configs/zynq.h new file mode 100644 index 00000000000..34ac3ef3d1f --- /dev/null +++ b/include/configs/zynq.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2012 Michal Simek + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_ZYNQ_H +#define __CONFIG_ZYNQ_H + +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_ZYNQ + +/* CPU clock */ +#define CONFIG_CPU_FREQ_HZ 800000000 +#define CONFIG_SYS_HZ 1000 + +/* Ram */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CONFIG_BAUDRATE 115200 + +/* XPSS Serial driver */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_ZYNQ_SERIAL +#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 +#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 + +/* SCU timer address is hardcoded */ +#define CONFIG_SCUTIMER_BASEADDR 0xF8F00600 + +/* Ethernet driver */ +#define CONFIG_NET_MULTI +#define CONFIG_ZYNQ_GEM +#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000 + +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL + +/* MII and Phylib */ +#define CONFIG_MII +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL + +/* Environment */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SYS_LOAD_ADDR 0 +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* OF */ +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT + +/* Commands */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII + +#endif /* __CONFIG_ZYNQ_H */ -- cgit v1.3.1 From 777544085d2b417a36df50eb564bf037a044e60e Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 4 Oct 2012 06:46:02 +0000 Subject: ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen Signed-off-by: Chin Liang See Signed-off-by: Pavel Machek Reviewed-by: Marek Vasut Acked-by: Tom Trini Cc: Wolfgang Denx Cc: Albert Aribaud Cc: Stefan Roese ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2 --- MAINTAINERS | 5 + arch/arm/cpu/armv7/socfpga/Makefile | 51 +++++ arch/arm/cpu/armv7/socfpga/config.mk | 16 ++ arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 77 +++++++ arch/arm/cpu/armv7/socfpga/misc.c | 54 +++++ arch/arm/cpu/armv7/socfpga/spl.c | 48 +++++ arch/arm/cpu/armv7/socfpga/timer.c | 104 +++++++++ arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 60 ++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 37 ++++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 27 +++ arch/arm/include/asm/arch-socfpga/spl.h | 26 +++ arch/arm/include/asm/arch-socfpga/timer.h | 29 +++ board/altera/socfpga_cyclone5/Makefile | 50 +++++ board/altera/socfpga_cyclone5/socfpga_cyclone5.c | 80 +++++++ boards.cfg | 1 + include/configs/socfpga_cyclone5.h | 236 +++++++++++++++++++++ 16 files changed, 901 insertions(+) create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile create mode 100644 arch/arm/cpu/armv7/socfpga/config.mk create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/socfpga/misc.c create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h create mode 100644 arch/arm/include/asm/arch-socfpga/spl.h create mode 100644 arch/arm/include/asm/arch-socfpga/timer.h create mode 100644 board/altera/socfpga_cyclone5/Makefile create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c create mode 100644 include/configs/socfpga_cyclone5.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 7004716e416..200426e8eaa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -781,6 +781,11 @@ Nagendra T S am3517_crane ARM ARMV7 (AM35x SoC) +Dinh Nguyen +Chin Liang See + + socfpga socfpga_cyclone5 + Sandeep Paulraj davinci_dm355evm ARM926EJS diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644 index 00000000000..376a4bddee8 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2012 Altera Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS-y := misc.o timer.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644 index 00000000000..b72ed1e40d6 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644 index 00000000000..001b37d42d8 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Save the parameter pass in by previous boot loader */ +.global save_boot_params +save_boot_params: + /* save the parameter here */ + + /* + * Setup stack for exception, which is located + * at the end of on-chip RAM. We don't expect exception prior to + * relocation and if that happens, we won't worry -- it will overide + * global data region as the code will goto reset. After relocation, + * this region won't be used by other part of program. + * Hence it is safe. + */ + ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + ldr r1, =IRQ_STACK_START_IN + str r0, [r1] + + bx lr + + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* Remap */ +#ifdef CONFIG_SPL_BUILD + /* + * SPL : configure the remap (L3 NIC-301 GPV) + * so the on-chip RAM at lower memory instead ROM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x19 + str r1, [r0] +#else + /* + * U-Boot : configure the remap (L3 NIC-301 GPV) + * so the SDRAM at lower memory instead on-chip RAM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x2 + str r1, [r0] + + /* Private components security */ + + /* + * U-Boot : configure private timer, global timer and cpu + * component access as non secure for kernel stage (as required + * by kernel) + */ + mrc p15,4,r0,c15,c0,0 + add r1, r0, #0x54 + ldr r2, [r1] + orr r2, r2, #0xff + orr r2, r2, #0xf00 + str r2, [r1] +#endif /* #ifdef CONFIG_SPL_BUILD */ + mov pc, lr diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c new file mode 100644 index 00000000000..fa16424b6f0 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644 index 00000000000..944238bad15 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +/* + * Board initialization after bss clearance + */ +void spl_board_init(void) +{ + /* init timer for enabling delay function */ + timer_init(); + + /* de-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + + /* enable console uart printing */ + preloader_console_init(); +} diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c new file mode 100644 index 00000000000..321e9b41813 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; + +/* + * Timer initialization + */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->load_val); + writel(TIMER_LOAD_VAL, &timer_base->curr_val); + writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); + return 0; +} + +static u32 read_timer(void) +{ + return readl(&timer_base->curr_val); +} + +/* + * Delay x useconds + */ +void __udelay(unsigned long usec) +{ + unsigned long now, last; + /* + * get the tmo value based on timer clock speed + * tmo = delay required / period of timer clock + */ + long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; + + last = read_timer(); + while (tmo > 0) { + now = read_timer(); + if (last >= now) + /* normal mode (non roll) */ + tmo -= last - now; + else + /* we have overflow of the count down timer */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * Get the timer value + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * Timer : get the time difference + * Unit of tick is based on the CONFIG_SYS_HZ + */ +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + if (gd->lastinc >= now) { + /* normal mode (non roll) */ + /* move stamp forward with absolute diff ticks */ + gd->tbl += gd->lastinc - now; + } else { + /* we have overflow of the count down timer */ + gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; + } + gd->lastinc = now; + return gd->tbl; +} + +/* + * Reset the timer + */ +void reset_timer(void) +{ + /* capture current decrementer value time */ + gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + /* start "advancing" time stamp from 0 */ + gd->tbl = 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds new file mode 100644 index 00000000000..7cd409cca20 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sdram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram + + . = ALIGN(8); + __malloc_start = .; + . = . + CONFIG_SPL_MALLOC_SIZE; + __malloc_end = .; + + . = . + CONFIG_SPL_STACK_SIZE; + . = ALIGN(8); + __stack_start = .; +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 00000000000..d9d2c1c56ff --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file mode 100644 index 00000000000..f353eb261c5 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h new file mode 100644 index 00000000000..efd0c060ce0 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/spl.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012 Pavel Machek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _SOCFPGA_SPL_H_ +#define _SOCFPGA_SPL_H_ + +/* Symbols from linker script */ +extern char __malloc_start, __malloc_end, __stack_start; + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h new file mode 100644 index 00000000000..830c94a2755 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/timer.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile new file mode 100644 index 00000000000..43bbc3785f4 --- /dev/null +++ b/board/altera/socfpga_cyclone5/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := socfpga_cyclone5.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file mode 100644 index 00000000000..7725be12f4e --- /dev/null +++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Platform\n"); + return 0; +} + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +/* + * DesignWare Ethernet initialization + */ +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/boards.cfg b/boards.cfg index 3a2cf324e29..fe201c26693 100644 --- a/boards.cfg +++ b/boards.cfg @@ -281,6 +281,7 @@ snowball arm armv7 snowball st-e kzm9g arm armv7 kzm9g kmc rmobile armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile zynq arm armv7 zynq xilinx zynq +socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h new file mode 100644 index 00000000000..d9eb5d99055 --- /dev/null +++ b/include/configs/socfpga_cyclone5.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High level configuration + */ + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define V_NS16550_CLK 1000000 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_STACK (&__stack_start) +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE + +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS + +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_H */ -- cgit v1.3.1