From 7544ad0303013e625c9500a4d87d4e5bfe369ee4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 8 May 2018 20:32:01 +0200 Subject: ARM: socfpga: Disable D cache in SPL The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_arria10_socdk.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 58e446b60a9..0f116fbf2d9 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -15,8 +15,6 @@ /* * U-Boot general configurations */ -/* Cache options */ -#define CONFIG_SYS_DCACHE_OFF /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 -- cgit v1.3.1 From 60082d3b3ff17fc0c5ae6c1cdd176219554ed61f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 8 May 2018 18:44:00 +0200 Subject: ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS This is not used anywhere, so drop it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e37..f182e9e71b4 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -280,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #endif -- cgit v1.3.1 From bd6363a7b77f0a5737b736f80179b6f53ef2cf7c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 8 May 2018 18:44:43 +0200 Subject: ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f182e9e71b4..181af9b646a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -275,12 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif #endif /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif #endif /* -- cgit v1.3.1