From 8475c869c30cbeef1695396b43bc240cc0d35f5a Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:10 +0100 Subject: s5p: gpio: change gpio coding method for s5p gpio. Old s5p gpio coding method was not clean and was not working properly for all parts and banks. New method is clean and easy to extend. Gpio coding mask: 0x000000ff - pin number 0x00ffff00 - bank offset 0xff000000 - part number Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- include/configs/s5p_goni.h | 4 ++-- include/configs/s5pc210_universal.h | 12 ++++++------ include/configs/trats.h | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 0590d201cea..4cdf937a60c 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -208,8 +208,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) +#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index d9e4c5683f8..02a1c99a831 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -229,8 +229,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ @@ -253,10 +253,10 @@ */ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) +#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) +#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) +#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) #define SPI_DELAY udelay(1) #undef SPI_INIT diff --git a/include/configs/trats.h b/include/configs/trats.h index fdd8b460b0d..9a927837963 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -287,8 +287,8 @@ #include /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) #define CONFIG_POWER #define CONFIG_POWER_I2C -- cgit v1.3.1 From 7f39b0678275c773301da15d3a7cc1ea7ca87171 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:11 +0100 Subject: trats2: Code cleanup. Remove wrong and unused env variables Trats2 is not as GT-I8800. Signed-off-by: Przemyslaw Marczak Acked-by: Jaehoon Chung Cc: Piotr Wilczek Signed-off-by: Minkyu Kang --- board/samsung/trats2/trats2.c | 12 ++---------- drivers/power/battery/bat_trats2.c | 2 +- include/power/max77686_pmic.h | 2 ++ 3 files changed, 5 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 1e96fdc6af9..feb6c4cccd2 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -72,15 +72,12 @@ static void check_hw_revision(void) int checkboard(void) { puts("Board:\tTRATS2\n"); + printf("HW Revision:\t0x%04x\n", board_rev); + return 0; } #endif -static void show_hw_revision(void) -{ - printf("HW Revision:\t0x%04x\n", board_rev); -} - u32 get_board_rev(void) { return board_rev; @@ -618,11 +615,6 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - setenv("model", "GT-I8800"); - setenv("board", "TRATS2"); - - show_hw_revision(); - return 0; } #endif diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c index f2648329d4d..94015aa41a1 100644 --- a/drivers/power/battery/bat_trats2.c +++ b/drivers/power/battery/bat_trats2.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include static struct battery battery_trats; diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index 16e90160894..c2a772a8951 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -8,6 +8,8 @@ #ifndef __MAX77686_H_ #define __MAX77686_H_ +#include + enum { MAX77686_REG_PMIC_ID = 0x0, MAX77686_REG_PMIC_INTSRC, -- cgit v1.3.1 From 679549d1802f0ee8e66576ecfc766d30b4040983 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:12 +0100 Subject: samsung: common: Add file for common functions, draw_logo() cleanup. Changes: new file: - board/samsung/common/misc.c depends on: CONFIG_MISC_COMMON - move draw_logo() to misc.c configs: trats, trats2, universal: - enable CONFIG_MISC_COMMON, - enable CONFIG_MISC_INIT_R, - add misc_init_r() and call draw_logo() in it. Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/common/Makefile | 1 + board/samsung/common/misc.c | 41 ++++++++++++++++++++++++++++++++ board/samsung/trats/trats.c | 11 +++++++++ board/samsung/trats2/trats2.c | 4 ++++ board/samsung/universal_c210/universal.c | 11 +++++++++ drivers/video/exynos_fb.c | 28 ---------------------- include/configs/s5pc210_universal.h | 5 ++++ include/configs/trats.h | 5 ++++ include/configs/trats2.h | 6 ++++- include/samsung/misc.h | 8 +++++++ 10 files changed, 91 insertions(+), 29 deletions(-) create mode 100644 board/samsung/common/misc.c create mode 100644 include/samsung/misc.h (limited to 'include') diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 22bd6b197e5..7d2bb8c4a2f 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o obj-$(CONFIG_THOR_FUNCTION) += thor.o obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o +obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_BOARD_COMMON) += board.o diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c new file mode 100644 index 00000000000..f6be8917928 --- /dev/null +++ b/board/samsung/common/misc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_CMD_BMP +void draw_logo(void) +{ + int x, y; + ulong addr; + + addr = panel_info.logo_addr; + if (!addr) { + error("There is no logo data."); + return; + } + + if (panel_info.vl_width >= panel_info.logo_width) { + x = ((panel_info.vl_width - panel_info.logo_width) >> 1); + } else { + x = 0; + printf("Warning: image width is bigger than display width\n"); + } + + if (panel_info.vl_height >= panel_info.logo_height) { + y = ((panel_info.vl_height - panel_info.logo_height) >> 1); + } else { + y = 0; + printf("Warning: image height is bigger than display height\n"); + } + + bmp_display(addr, x, y); +} +#endif /* CONFIG_CMD_BMP */ diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 640a193dc21..a644b608cdb 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -786,3 +786,14 @@ void init_panel_info(vidinfo_t *vid) setenv("lcdinfo", "lcd=s6e8ax0"); } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index feb6c4cccd2..4834f9010d7 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -615,6 +615,10 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif return 0; } #endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 3feef3f7777..2b8c69be1d0 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -511,3 +511,14 @@ int board_init(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 7d4c6e092df..00a0a11ed4e 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -62,31 +62,6 @@ static void exynos_lcd_init(vidinfo_t *vid) lcd_set_flush_dcache(1); } -#ifdef CONFIG_CMD_BMP -static void draw_logo(void) -{ - int x, y; - ulong addr; - - if (panel_width >= panel_info.logo_width) { - x = ((panel_width - panel_info.logo_width) >> 1); - } else { - x = 0; - printf("Warning: image width is bigger than display width\n"); - } - - if (panel_height >= panel_info.logo_height) { - y = ((panel_height - panel_info.logo_height) >> 1) - 4; - } else { - y = 0; - printf("Warning: image height is bigger than display height\n"); - } - - addr = panel_info.logo_addr; - bmp_display(addr, x, y); -} -#endif - void __exynos_cfg_lcd_gpio(void) { } @@ -323,9 +298,6 @@ void lcd_enable(void) if (panel_info.logo_on) { memset((void *) gd->fb_base, 0, panel_width * panel_height * (NBITS(panel_info.vl_bpix) >> 3)); -#ifdef CONFIG_CMD_BMP - draw_logo(); -#endif } lcd_panel_on(&panel_info); diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 02a1c99a831..6b98bed7b4f 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -269,6 +269,11 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + /* * LCD Settings */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 9a927837963..7a9c60b3491 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -306,6 +306,11 @@ #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_CABLE_CHECK +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 83633b074d5..b4ca1ff8570 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -277,7 +277,6 @@ #define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS -#define CONFIG_MISC_INIT_R #define CONFIG_BOARD_EARLY_INIT_F /* I2C */ @@ -318,6 +317,11 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_CABLE_CHECK +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD diff --git a/include/samsung/misc.h b/include/samsung/misc.h new file mode 100644 index 00000000000..8ea92236f9b --- /dev/null +++ b/include/samsung/misc.h @@ -0,0 +1,8 @@ +#ifndef __SAMSUNG_MISC_COMMON_H__ +#define __SAMSUNG_MISC_COMMON_H__ + +#ifdef CONFIG_CMD_BMP +void draw_logo(void); +#endif + +#endif /* __SAMSUNG_MISC_COMMON_H__ */ -- cgit v1.3.1 From 903afe18bb272d6d5c12e0be22b0f8fd35fa6f1b Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Fri, 29 Nov 2013 18:30:43 +0100 Subject: lib: tizen: change Tizen logo with the new one. Changes: - check image bpp instead of resolution when returns logo address - remove 32bpp logo - add 16bpp logo in two formats: bmp and gzipped bmp - init logo address with "0" for unsupported bpp mode - update boards configs with proper image size for gunzip - extend structure vidinfo by two fields: logo_x_offset and logo_y_offset. Signed-off-by: Przemyslaw Marczak Tested-by: Hyungwon Hwang Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 2 + include/configs/s5pc210_universal.h | 2 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- include/lcd.h | 2 + lib/tizen/tizen.c | 21 +- lib/tizen/tizen_hd_logo.h | 5057 ----------------- lib/tizen/tizen_hd_logo_data.h | 15 - lib/tizen/tizen_logo_16bpp.h | 10025 ++++++++++++++++++++++++++++++++++ lib/tizen/tizen_logo_16bpp_gzip.h | 727 +++ 10 files changed, 10773 insertions(+), 5082 deletions(-) delete mode 100644 lib/tizen/tizen_hd_logo.h delete mode 100644 lib/tizen/tizen_hd_logo_data.h create mode 100644 lib/tizen/tizen_logo_16bpp.h create mode 100644 lib/tizen/tizen_logo_16bpp_gzip.h (limited to 'include') diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index f6be8917928..15775e35dfa 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -24,6 +24,7 @@ void draw_logo(void) if (panel_info.vl_width >= panel_info.logo_width) { x = ((panel_info.vl_width - panel_info.logo_width) >> 1); + x += panel_info.logo_x_offset; /* For X center align */ } else { x = 0; printf("Warning: image width is bigger than display width\n"); @@ -31,6 +32,7 @@ void draw_logo(void) if (panel_info.vl_height >= panel_info.logo_height) { y = ((panel_info.vl_height - panel_info.logo_height) >> 1); + y += panel_info.logo_y_offset; /* For Y center align */ } else { y = 0; printf("Warning: image height is bigger than display height\n"); diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 6b98bed7b4f..67b08fc7d3b 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -284,6 +284,6 @@ int universal_spi_read(void); #define CONFIG_LD9040 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 7a9c60b3491..7babc0fcfcd 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -320,7 +320,7 @@ #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE diff --git a/include/configs/trats2.h b/include/configs/trats2.h index b4ca1ff8570..a66358bb1cf 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -331,7 +331,7 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE diff --git a/include/lcd.h b/include/lcd.h index 40e8d2a86b5..d06d6f10720 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -223,6 +223,8 @@ typedef struct vidinfo { unsigned int logo_on; unsigned int logo_width; unsigned int logo_height; + int logo_x_offset; + int logo_y_offset; unsigned long logo_addr; unsigned int rgb_mode; unsigned int resolution; diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c index e872591cd18..814ed18329e 100644 --- a/lib/tizen/tizen.c +++ b/lib/tizen/tizen.c @@ -9,18 +9,25 @@ #include #include -#include "tizen_hd_logo.h" -#include "tizen_hd_logo_data.h" +#include "tizen_logo_16bpp.h" +#include "tizen_logo_16bpp_gzip.h" void get_tizen_logo_info(vidinfo_t *vid) { - switch (vid->resolution) { - case HD_RESOLUTION: - vid->logo_width = TIZEN_HD_LOGO_WIDTH; - vid->logo_height = TIZEN_HD_LOGO_HEIGHT; - vid->logo_addr = (ulong)tizen_hd_logo; + switch (vid->vl_bpix) { + case 4: + vid->logo_width = TIZEN_LOGO_16BPP_WIDTH; + vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT; + vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET; + vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET; +#if defined(CONFIG_VIDEO_BMP_GZIP) + vid->logo_addr = (ulong)tizen_logo_16bpp_gzip; +#else + vid->logo_addr = (ulong)tizen_logo_16bpp; +#endif break; default: + vid->logo_addr = 0; break; } } diff --git a/lib/tizen/tizen_hd_logo.h b/lib/tizen/tizen_hd_logo.h deleted file mode 100644 index 28377b75c9a..00000000000 --- a/lib/tizen/tizen_hd_logo.h +++ /dev/null @@ -1,5057 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TIZEN_HD_LOGO_H_ -#define _TIZEN_HD_LOGO_H_ - -unsigned char tizen_hd_logo[]={ -0x1f,0x8b,0x08,0x08,0xe0,0x6f,0x8f,0x4f,0x00,0x03,0x74,0x72,0x61,0x74,0x73,0x2e, -0x62,0x6d,0x70,0x00,0xbc,0x5c,0xe9,0x53,0x1c,0x57,0x92,0xaf,0x6a,0xa0,0x81,0xa6, -0xb9,0x1b,0x04,0x48,0x02,0x04,0x7d,0xd0,0xdd,0x1c,0x12,0xba,0xd1,0x61,0x59,0x48, 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a/lib/tizen/tizen_hd_logo_data.h b/lib/tizen/tizen_hd_logo_data.h deleted file mode 100644 index 95e5f827ebb..00000000000 --- a/lib/tizen/tizen_hd_logo_data.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TIZEN_HD_LOGO_DATA_H_ -#define _TIZEN_HD_LOGO_DATA_H_ - -#define TIZEN_HD_LOGO_WIDTH 520 -#define TIZEN_HD_LOGO_HEIGHT 120 -#define TIZEN_HD_LOGO_BPP 32 - -#endif /* _TIZEN_HD_LOGO_DATA_H_ */ diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h new file mode 100644 index 00000000000..9a0b6fa3544 --- /dev/null +++ b/lib/tizen/tizen_logo_16bpp.h @@ -0,0 +1,10025 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __TIZEN_LOGO_16BPP__ +#define __TIZEN_LOGO_16BPP__ + +#define TIZEN_LOGO_16BPP_WIDTH 500 +#define TIZEN_LOGO_16BPP_HEIGHT 160 + +/* Center align offsets for word "TIZEN" */ +#define TIZEN_LOGO_16BPP_X_OFFSET (30) +#define TIZEN_LOGO_16BPP_Y_OFFSET (-26) + +/* Format: BMP RGB565 16BPP 500x160 */ +unsigned char tizen_logo_16bpp[] = { +0x42,0x4d,0x46,0x71,0x02,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, +0x00,0x00,0xf4,0x01,0x00,0x00,0xa0,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, +0x00,0x00,0x00,0x71,0x02,0x00,0x13,0x0b,0x00,0x00,0x13,0x0b,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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/dev/null +++ b/lib/tizen/tizen_logo_16bpp_gzip.h @@ -0,0 +1,727 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __TIZEN_LOGO_16BPP_GZIP__ +#define __TIZEN_LOGO_16BPP_GZIP__ + +/* Format: GZIP: BMP RGB565 16BPP 500x160 */ +unsigned char tizen_logo_16bpp_gzip[] = { +0x1f,0x8b,0x08,0x08,0xff,0xf7,0xb3,0x52,0x00,0x03,0x54,0x69,0x7a,0x65,0x6e,0x2d, +0x4c,0x6f,0x63,0x6b,0x75,0x70,0x2d,0x4f,0x6e,0x2d,0x44,0x61,0x72,0x6b,0x2d,0x52, +0x47,0x42,0x5f,0x35,0x30,0x30,0x78,0x31,0x36,0x30,0x2e,0x62,0x6d,0x70,0x00,0xed, +0x9d,0x7f,0x6c,0x5b,0xe7,0x79,0xef,0x29,0xf1,0x47,0xd8,0x59,0x86,0xd9,0xda,0x85, +0x95,0x50,0x89,0xc9,0x56,0xe9,0xa2,0x44,0xc5,0xec,0x55,0xbb,0x91,0x22,0xba,0xbe, +0x32,0xe6,0xdc,0x6b,0xad,0xc6,0x1c,0x55,0x1e,0x24,0x99,0x4e,0x60,0x0b,0xce,0x20, +0xa8,0xee,0xbd,0x86,0xae,0x50,0x2b,0x92,0x62,0x5c,0x55,0xf3,0x6e,0x32,0x25,0x80, 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+0100 Subject: samsung: boards: update display configs with 16bpp mode. 16 bpp mode is required by LCD console mode. This change updates exynos board files. Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 2 +- board/samsung/trats2/trats2.c | 2 +- board/samsung/universal_c210/universal.c | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a644b608cdb..32a6cee1ecf 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -742,7 +742,7 @@ vidinfo_t panel_info = { .vl_hsp = CONFIG_SYS_LOW, .vl_vsp = CONFIG_SYS_LOW, .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ + .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ /* s6e8ax0 Panel infomation */ .vl_hspw = 5, diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 4834f9010d7..b60a2da5558 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -565,7 +565,7 @@ vidinfo_t panel_info = { .vl_hsp = CONFIG_SYS_LOW, .vl_vsp = CONFIG_SYS_LOW, .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ + .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ /* s6e8ax0 Panel infomation */ .vl_hspw = 5, diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 2b8c69be1d0..7278a2c1aa2 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -446,7 +446,7 @@ vidinfo_t panel_info = { .vl_vsp = CONFIG_SYS_HIGH, .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = 5, /* Bits per pixel */ + .vl_bpix = 4, /* Bits per pixel */ /* LD9040 LCD Panel */ .vl_hspw = 2, diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 67b08fc7d3b..93b9dfb0f96 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -280,7 +280,7 @@ int universal_spi_read(void); #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_LD9040 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP diff --git a/include/configs/trats.h b/include/configs/trats.h index 7babc0fcfcd..5022f400292 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -315,7 +315,7 @@ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM diff --git a/include/configs/trats2.h b/include/configs/trats2.h index a66358bb1cf..a97ecb2d6ac 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -326,7 +326,7 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM -- cgit v1.3.1 From 9d29a682a8dbe40b8d1af45197a87d49472fc105 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:17 +0100 Subject: samsung: misc: Add LCD download menu. This simple LCD menu allows run one of download mode on device without writing on console or for fast and easy upgrade. This feature check user keys combination at boot: - power key + volume up - download menu - power key + volume down - thor mode (without menu) New configs: - CONFIG_LCD_MENU - CONFIG_LCD_MENU_BOARD For proper effect this feature needs following definitions: Power key: - KEY_PWR_PMIC_NAME - (string) pmic which supports power key check Register address: - KEY_PWR_STATUS_REG - KEY_PWR_INTERRUPT_REG Register power key mask: - KEY_PWR_STATUS_MASK - KEY_PWR_INTERRUPT_MASK Gpio numbers: - KEY_PWR_INTERRUPT_MASK - KEY_VOL_DOWN_GPIO Functions needs to be called: - keys_init() - for set proper gpio direction - check_boot_mode() - menu - main function Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 344 ++++++++++++++++++++++++++++++++++++++++++++ include/samsung/misc.h | 17 +++ 2 files changed, 361 insertions(+) (limited to 'include') diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 15775e35dfa..643f957a543 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -9,6 +9,350 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_LCD_MENU +static int power_key_pressed(u32 reg) +{ + struct pmic *pmic; + u32 status; + u32 mask; + + pmic = pmic_get(KEY_PWR_PMIC_NAME); + if (!pmic) { + printf("%s: Not found\n", KEY_PWR_PMIC_NAME); + return 0; + } + + if (pmic_probe(pmic)) + return 0; + + if (reg == KEY_PWR_STATUS_REG) + mask = KEY_PWR_STATUS_MASK; + else + mask = KEY_PWR_INTERRUPT_MASK; + + if (pmic_reg_read(pmic, reg, &status)) + return 0; + + return !!(status & mask); +} + +static int key_pressed(int key) +{ + int value; + + switch (key) { + case KEY_POWER: + value = power_key_pressed(KEY_PWR_INTERRUPT_REG); + break; + case KEY_VOLUMEUP: + value = !gpio_get_value(KEY_VOL_UP_GPIO); + break; + case KEY_VOLUMEDOWN: + value = !gpio_get_value(KEY_VOL_DOWN_GPIO); + break; + default: + value = 0; + break; + } + + return value; +} + +static int check_keys(void) +{ + int keys = 0; + + if (key_pressed(KEY_POWER)) + keys += KEY_POWER; + if (key_pressed(KEY_VOLUMEUP)) + keys += KEY_VOLUMEUP; + if (key_pressed(KEY_VOLUMEDOWN)) + keys += KEY_VOLUMEDOWN; + + return keys; +} + +/* + * 0 BOOT_MODE_INFO + * 1 BOOT_MODE_THOR + * 2 BOOT_MODE_UMS + * 3 BOOT_MODE_DFU + * 4 BOOT_MODE_EXIT + */ +static char * +mode_name[BOOT_MODE_EXIT + 1] = { + "DEVICE", + "THOR", + "UMS", + "DFU", + "EXIT" +}; + +static char * +mode_info[BOOT_MODE_EXIT + 1] = { + "info", + "downloader", + "mass storage", + "firmware update", + "and run normal boot" +}; + +#define MODE_CMD_ARGC 4 + +static char * +mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = { + {"", "", "", ""}, + {"thor", "0", "mmc", "0"}, + {"ums", "0", "mmc", "0"}, + {"dfu", "0", "mmc", "0"}, + {"", "", "", ""}, +}; + +static void display_board_info(void) +{ +#ifdef CONFIG_GENERIC_MMC + struct mmc *mmc = find_mmc_device(0); +#endif + vidinfo_t *vid = &panel_info; + + lcd_position_cursor(4, 4); + + lcd_printf("%s\n\t", U_BOOT_VERSION); + lcd_puts("\n\t\tBoard Info:\n"); +#ifdef CONFIG_SYS_BOARD + lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD); +#endif +#ifdef CONFIG_REVISION_TAG + lcd_printf("\tBoard rev: %u\n", get_board_rev()); +#endif + lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS); + lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M); + +#ifdef CONFIG_GENERIC_MMC + if (mmc) { + if (!mmc->capacity) + mmc_init(mmc); + + lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M); + } +#endif + if (vid) + lcd_printf("\tDisplay resolution: %u x % u\n", + vid->vl_col, vid->vl_row); + + lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix); +} + +static int mode_leave_menu(int mode) +{ + char *exit_option; + char *exit_boot = "boot"; + char *exit_back = "back"; + cmd_tbl_t *cmd; + int cmd_result; + int cmd_repeatable; + int leave; + + lcd_clear(); + + switch (mode) { + case BOOT_MODE_EXIT: + return 1; + case BOOT_MODE_INFO: + display_board_info(); + exit_option = exit_back; + leave = 0; + break; + default: + cmd = find_cmd(mode_cmd[mode][0]); + if (cmd) { + printf("Enter: %s %s\n", mode_name[mode], + mode_info[mode]); + lcd_printf("\n\n\t%s %s\n", mode_name[mode], + mode_info[mode]); + lcd_puts("\n\tDo not turn off device before finish!\n"); + + cmd_result = cmd_process(0, MODE_CMD_ARGC, + *(mode_cmd + mode), + &cmd_repeatable, NULL); + + if (cmd_result == CMD_RET_SUCCESS) { + printf("Command finished\n"); + lcd_clear(); + lcd_printf("\n\n\t%s finished\n", + mode_name[mode]); + + exit_option = exit_boot; + leave = 1; + } else { + printf("Command error\n"); + lcd_clear(); + lcd_printf("\n\n\t%s command error\n", + mode_name[mode]); + + exit_option = exit_back; + leave = 0; + } + } else { + lcd_puts("\n\n\tThis mode is not supported.\n"); + exit_option = exit_back; + leave = 0; + } + } + + lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option); + + /* Clear PWR button Rising edge interrupt status flag */ + power_key_pressed(KEY_PWR_INTERRUPT_REG); + + /* Wait for PWR key */ + while (!key_pressed(KEY_POWER)) + mdelay(1); + + lcd_clear(); + return leave; +} + +static void display_download_menu(int mode) +{ + char *selection[BOOT_MODE_EXIT + 1]; + int i; + + for (i = 0; i <= BOOT_MODE_EXIT; i++) + selection[i] = "[ ]"; + + selection[mode] = "[=>]"; + + lcd_clear(); + lcd_printf("\n\t\tDownload Mode Menu\n"); + + for (i = 0; i <= BOOT_MODE_EXIT; i++) + lcd_printf("\t%s %s - %s\n\n", selection[i], + mode_name[i], + mode_info[i]); +} + +static void download_menu(void) +{ + int mode = 0; + int last_mode = 0; + int run; + int key; + + display_download_menu(mode); + + while (1) { + run = 0; + + if (mode != last_mode) + display_download_menu(mode); + + last_mode = mode; + mdelay(100); + + key = check_keys(); + switch (key) { + case KEY_POWER: + run = 1; + break; + case KEY_VOLUMEUP: + if (mode > 0) + mode--; + break; + case KEY_VOLUMEDOWN: + if (mode < BOOT_MODE_EXIT) + mode++; + break; + default: + break; + } + + if (run) { + if (mode_leave_menu(mode)) + break; + + display_download_menu(mode); + } + } + + lcd_clear(); +} + +static void display_mode_info(void) +{ + lcd_position_cursor(4, 4); + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_puts("\nDownload Mode Menu\n"); +#ifdef CONFIG_SYS_BOARD + lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD); +#endif + lcd_printf("Press POWER KEY to display MENU options."); +} + +static int boot_menu(void) +{ + int key = 0; + int timeout = 10; + + display_mode_info(); + + while (timeout--) { + lcd_printf("\rNormal boot will start in: %d seconds.", timeout); + mdelay(1000); + + key = key_pressed(KEY_POWER); + if (key) + break; + } + + lcd_clear(); + + /* If PWR pressed - show download menu */ + if (key) { + printf("Power pressed - go to download menu\n"); + download_menu(); + printf("Download mode exit.\n"); + } + + return 0; +} + +void check_boot_mode(void) +{ + int pwr_key; + + pwr_key = power_key_pressed(KEY_PWR_STATUS_REG); + if (!pwr_key) + return; + + /* Clear PWR button Rising edge interrupt status flag */ + power_key_pressed(KEY_PWR_INTERRUPT_REG); + + if (key_pressed(KEY_VOLUMEUP)) + boot_menu(); + else if (key_pressed(KEY_VOLUMEDOWN)) + mode_leave_menu(BOOT_MODE_THOR); +} + +void keys_init(void) +{ + /* Set direction to input */ + gpio_direction_input(KEY_VOL_UP_GPIO); + gpio_direction_input(KEY_VOL_DOWN_GPIO); +} +#endif /* CONFIG_LCD_MENU */ #ifdef CONFIG_CMD_BMP void draw_logo(void) diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 8ea92236f9b..1a6d47f4ca6 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -1,6 +1,23 @@ #ifndef __SAMSUNG_MISC_COMMON_H__ #define __SAMSUNG_MISC_COMMON_H__ +#ifdef CONFIG_LCD_MENU +enum { + BOOT_MODE_INFO, + BOOT_MODE_THOR, + BOOT_MODE_UMS, + BOOT_MODE_DFU, + BOOT_MODE_EXIT, +}; + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void); +#endif + +void keys_init(void); +void check_boot_mode(void); +#endif /* CONFIG_LCD_MENU */ + #ifdef CONFIG_CMD_BMP void draw_logo(void); #endif -- cgit v1.3.1 From 00e64ab6471e154a06d89bbfffba2bbe6e2150ad Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:18 +0100 Subject: trats: add LCD download menu support Signed-off-by: Przemyslaw Marczak Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 5 +++++ include/configs/trats.h | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'include') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 32a6cee1ecf..c6664e7a123 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "setup.h" @@ -790,6 +791,10 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif #ifdef CONFIG_CMD_BMP if (panel_info.logo_on) draw_logo(); diff --git a/include/configs/trats.h b/include/configs/trats.h index 5022f400292..a623371cd17 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -311,6 +311,28 @@ #define CONFIG_MISC_INIT_R +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX8997_PMIC" +#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 0) + +#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) +#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD -- cgit v1.3.1 From f64236a907acf852f9b0421497aa6563e10e1d37 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:19 +0100 Subject: trats2: add LCD download menu support Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/trats2/trats2.c | 5 +++++ include/configs/trats2.h | 22 ++++++++++++++++++++++ include/power/pmic.h | 1 - 3 files changed, 27 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index b60a2da5558..62e7fd22242 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -615,6 +616,10 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif #ifdef CONFIG_CMD_BMP if (panel_info.logo_on) draw_logo(); diff --git a/include/configs/trats2.h b/include/configs/trats2.h index a97ecb2d6ac..095f253c26a 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -322,6 +322,28 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_MISC_INIT_R +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" +#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 1) + +#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) +#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD diff --git a/include/power/pmic.h b/include/power/pmic.h index 0e7aa314927..8f282dd2f29 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -8,7 +8,6 @@ #ifndef __CORE_PMIC_H_ #define __CORE_PMIC_H_ -#include #include #include #include -- cgit v1.3.1 From 82b0a0556172a17aca23cd07cf1dc3bd86248b97 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:20 +0100 Subject: universal: add LCD download menu support Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/universal_c210/universal.c | 5 +++++ include/configs/s5pc210_universal.h | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'include') diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 7278a2c1aa2..ced4caa86fd 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -515,6 +516,10 @@ int board_init(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif #ifdef CONFIG_CMD_BMP if (panel_info.logo_on) draw_logo(); diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 93b9dfb0f96..bfb044b087b 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -274,6 +274,28 @@ int universal_spi_read(void); #define CONFIG_MISC_INIT_R +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX8998_PMIC" +#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 7) +#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 +#define KEY_PWR_INTERRUPT_MASK (1 << 7) + +#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) +#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* * LCD Settings */ -- cgit v1.3.1 From a0afc6f37851fe324418fff9655abedfe2d975a2 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 12:02:47 +0100 Subject: config: trats: trats2: extend dfu_alt_info by env update settings This change allows updating environment stored on MMC by dfu or thor. New setting: - "params.bin mmc 0x38 0x8" File params.bin can be generated by: tools/mkenvimage. e.g. ./mkenvimage -s 4096 -o params.bin Every new env variable in text file should start with a new line. Sample env text file: - board/samsung/common/dfu_sample_env.txt Requirements: - file name: "params.bin" - file size: 4096 Bytes - the same as CONFIG_ENV_SIZE. Other size will cause CRC miscalculation at boot. Signed-off-by: Przemyslaw Marczak CC: Piotr Wilczek CC: Lukasz Majewski Acked-by: Lukasz Majewski Acked-by: Jaehoon Chung Signed-off-by: Minkyu Kang --- board/samsung/common/dfu_sample_env.txt | 9 +++++++++ include/configs/trats.h | 3 ++- include/configs/trats2.h | 3 ++- 3 files changed, 13 insertions(+), 2 deletions(-) create mode 100644 board/samsung/common/dfu_sample_env.txt (limited to 'include') diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt new file mode 100644 index 00000000000..d6ee8a228a8 --- /dev/null +++ b/board/samsung/common/dfu_sample_env.txt @@ -0,0 +1,9 @@ +mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0 +rootfstype=ext4 +loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage +mmcdev=0 +mmcbootpart=2 +mmcrootpart=5 +console=console=ttySAC2,115200n8 +bootcmd=run mmcboot +dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2 diff --git a/include/configs/trats.h b/include/configs/trats.h index a623371cd17..41de414485a 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -147,7 +147,8 @@ ""PARTS_BOOT" part 0 2;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7\0" + ""PARTS_UMS" part 0 7;" \ + "params.bin mmc 0x38 0x8\0" #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_INFO_QUIET diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 095f253c26a..b72f4920d90 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -178,7 +178,8 @@ ""PARTS_BOOT" part 0 2;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7\0" + ""PARTS_UMS" part 0 7;" \ + "params.bin mmc 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ -- cgit v1.3.1 From 5b7672fc49af1b771a7e318522b010fd5b11c4ab Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 27 Jan 2014 15:55:20 +0530 Subject: boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel Signed-off-by: Bhupesh Sharma Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Prabhakar Kushwaha [York Sun: remove dash from commit message] Signed-off-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 11 + board/freescale/t1040qds/Makefile | 1 + board/freescale/t1040qds/eth.c | 492 ++++++++++++++++++++++++++++++++++ board/freescale/t1040qds/t1040qds.c | 1 + drivers/net/fm/t1040.c | 56 ++++ include/configs/T1040QDS.h | 5 +- 6 files changed, 563 insertions(+), 3 deletions(-) create mode 100644 board/freescale/t1040qds/eth.c (limited to 'include') diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 68c3c824533..9d08321f5d3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,6 +1759,17 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 93af9eb6a06..c7470d7cbb2 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -9,3 +9,4 @@ obj-y += ddr.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o +obj-y += eth.o diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c new file mode 100644 index 00000000000..3077b4ae2c5 --- /dev/null +++ b/board/freescale/t1040qds/eth.c @@ -0,0 +1,492 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY connected to + * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board + * PHY or by the standard four-port SGMII riser card (VSC). + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "../common/qixis.h" + +#include "t1040qds_qixis.h" + +#ifdef CONFIG_FMAN_ENET + /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks. + * Bank 1 -> Lanes A, B, C, D + * Bank 2 -> Lanes E, F, G, H + */ + + /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here + * means that the mapping must be determined dynamically, or that the lane + * maps to something other than a board slot. + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs + * housed. + */ +static int riser_phy_addr[] = { + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* Slot2 does not have EMI connections */ +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII0 0 +#define EMI1_RGMII1 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1040_QDS_MDIO0", + "T1040_QDS_MDIO1", + "T1040_QDS_MDIO2", + "T1040_QDS_MDIO3", + "T1040_QDS_MDIO4", + "T1040_QDS_MDIO5", + "T1040_QDS_MDIO6", + "T1040_QDS_MDIO7", +}; + +struct t1040_qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static const char *t1040_qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t1040_qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +static void t1040_qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval <= 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1040_qds_mdio_reset(struct mii_dev *bus) +{ + struct t1040_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1040_qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1040_qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1040_qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1040_qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1040_qds_mdio_read; + bus->write = t1040_qds_mdio_write; + bus->reset = t1040_qds_mdio_reset; + sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Initialize the lane_to_slot[] array. + * + * On the T1040QDS board the mapping is controlled by ?? register. + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL) + >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + QIXIS_WRITE(cms[0], 0x07); + + switch (serdes1_prtcl) { + case 0x60: + case 0x66: + case 0x67: + case 0x69: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + break; + case 0x86: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + case 0x87: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x89: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x8d: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0x8F: + case 0x85: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA5: + lane_to_slot[1] = 7; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA7: + lane_to_slot[1] = 7; + lane_to_slot[7] = 7; + break; + case 0xAA: + lane_to_slot[1] = 7; + lane_to_slot[6] = 7; + lane_to_slot[7] = 7; + break; + case 0x40: + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + default: + printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + + /* The RGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_RGMII) { + sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* The SGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_SGMII) { + int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + + port); + u8 slot; + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + /* Slot housing a SGMII riser card */ + sprintf(phy, "phy_s%x_%02x", slot, + (fm_info_get_phy_address(port - FM1_DTSEC1)- + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT5: + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + break; + case EMI1_SLOT6: + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + break; + case EMI1_SLOT7: + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC4) + fdt_status_okay_by_alias(fdt, "emi1_rgmii0"); + + if (i == FM1_DTSEC5) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + break; + default: + break; + } + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +static void set_brdcfg9_for_gtx_clk(void) +{ + u8 brdcfg9; + brdcfg9 = QIXIS_READ(brdcfg[9]); + brdcfg9 |= (1 << 5); + QIXIS_WRITE(brdcfg[9], brdcfg9); +} + +void t1040_handle_phy_interface_sgmii(int i) +{ + int lane, idx, slot; + idx = i - FM1_DTSEC1; + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + + if (lane < 0) + return; + slot = lane_to_slot[lane]; + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + if (FM1_DTSEC4 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC5 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + + mdio_mux[i] = EMI1_SLOT3; + + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 5: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 6: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 7: + if (FM1_DTSEC1 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC2 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + if (FM1_DTSEC3 == i) + fm_info_set_phy_address(i, riser_phy_addr[2]); + + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} +void t1040_handle_phy_interface_rgmii(int i) +{ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 : + EMI1_RGMII0; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + + printf("Initializing Fman\n"); + set_brdcfg9_for_gtx_clk(); + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + + /* + * Program on board RGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + break; + case PHY_INTERFACE_MODE_SGMII: + t1040_handle_phy_interface_sgmii(i); + break; + + case PHY_INTERFACE_MODE_RGMII: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + t1040_handle_phy_interface_rgmii(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index de3ea5c2aa2..3dec4473e52 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -223,6 +223,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); #endif } diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 83cf081f3d3..bcc871d8420 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -12,5 +12,61 @@ phy_interface_t fman_port_enet_if(enum fm_port port) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + return PHY_INTERFACE_MODE_NONE; } diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8234a828dda..75ea125f539 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -611,9 +611,8 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -- cgit v1.3.1 From 9b444be32230160ee6b3e4dbf625b4201ac3897d Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 27 Jan 2014 14:07:11 +0530 Subject: powerpc/t104xrdb: Update T1040RDB.h in config folder Add usb2 node entry in "hwconfig string" Remove controller interleaving from hwconfig string as T1040 has only one DDR conroller SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH are move outside so that they are defined for all cases as these macros are also used by other u-boot code Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain [York Sun: Minor change to commit message] Signed-off-by: York Sun --- include/configs/T1040RDB.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 5e988c254c7..611b95c4478 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -386,6 +383,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -627,9 +628,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ -- cgit v1.3.1 From 48aee3913d1e99b9f0b91ff0eb52700b4dd24d25 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 27 Jan 2014 14:41:55 +0530 Subject: powerpc/t104xrdb: Update T1042RDB.h in config folder Add usb2 node entry to hwconfig default Remove DDR controller interleaving from hwconfig Move SPI related macros out of "#ifdef CONFIG_SPIFLASH" Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot Signed-off-by: Prabhakar Kushwaha [York Sun: Fix commit message] Signed-off-by: York Sun --- include/configs/T1042RDB_PI.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index aafa8139b1a..1cbc375b047 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -394,6 +391,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -631,9 +632,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ -- cgit v1.3.1 From 714fd406daab6a98b2ee8d301c4888c113fdd818 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 30 Jan 2014 11:30:04 +0530 Subject: powerpc/t104xrdb: Add basic ethernet support This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain [York Sun: Minor change in commit message] Signed-off-by: York Sun --- board/freescale/t104xrdb/Makefile | 1 + board/freescale/t104xrdb/eth.c | 72 +++++++++++++++++++++++++++++++++++++++ include/configs/T1040RDB.h | 9 +++-- include/configs/T1042RDB_PI.h | 5 ++- 4 files changed, 81 insertions(+), 6 deletions(-) create mode 100644 board/freescale/t104xrdb/eth.c (limited to 'include') diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 76c0c94b0e1..e51fb7a7f45 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -7,6 +7,7 @@ obj-y += t104xrdb.o obj-y += ddr.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c new file mode 100644 index 00000000000..0188fd4090b --- /dev/null +++ b/board/freescale/t104xrdb/eth.c @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + int phy_addr = 0; + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { +#ifdef CONFIG_T1040RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1040RDB only supports SGMII on DTSEC3 */ + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_SGMII1_PHY_ADDR); +#endif + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 611b95c4478..7cfda50c8cd 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -544,13 +544,12 @@ #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 1cbc375b047..ed9ca8a3e19 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -552,8 +552,11 @@ #endif #ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 + #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif -- cgit v1.3.1 From dd21f09669ee65500f1f9bce5c4024cf817f3c79 Mon Sep 17 00:00:00 2001 From: Rainer Boschung Date: Mon, 27 Jan 2014 11:49:04 +0100 Subject: kmp204x: support for QRIO1 bootcounter Make use of the QRIO1 32bit register at 0x20 as bootcounter register Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read Signed-off-by: Rainer Boschung Signed-off-by: Valentin Longchamp [York Sun: Minor change to commit message] Signed-off-by: York Sun --- board/keymile/kmp204x/kmp204x.c | 20 -------------------- include/configs/km/kmp204x-common.h | 6 ++++-- 2 files changed, 4 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index f02642aecec..20a32642bbc 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -133,26 +133,6 @@ void qrio_prstcfg(u8 bit, u8 mode) out_be32(qrio_base + PRSTCFG_OFF, prstcfg); } - -#define BOOTCOUNT_OFF 0x12 - -void bootcount_store(ulong counter) -{ - u8 val; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - val = (counter <= 255) ? (u8)counter : 255; - out_8(qrio_base + BOOTCOUNT_OFF, val); -} - -ulong bootcount_load(void) -{ - u8 val; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - val = in_8(qrio_base + BOOTCOUNT_OFF); - return val; -} - #define NUM_SRDS_BANKS 2 #define PHY_RST 15 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 2466649b15c..0461815ca13 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -148,8 +148,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ -#define CONFIG_BOOTCOUNT_LIMIT - /* * Local Bus Definitions */ @@ -206,6 +204,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ +/* bootcounter in QRIO */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R -- cgit v1.3.1 From f3e74d0a9fd8cdcbdc59b7c5a702aacc51908dca Mon Sep 17 00:00:00 2001 From: Rainer Boschung Date: Mon, 3 Feb 2014 08:45:40 +0100 Subject: kmp204x: I2C deblocking support This patch adds support for using some GPIOs that are connected to the I2C bus to force the bus lines state and perform some bus deblocking sequences. The KM common deblocking algorithm from board/keymile/common/common.c is used. The GPIO lines used for deblocking the I2C bus are some external GPIOs provided by the QRIO CPLD: - SCL = GPIOA_20 - SDA = GPIOA_21 The QRIO GPIOs act in an open-drain-like manner, for 0 the line is driven low and for 1 the GPIO is set as input and the line gets pulled-up. Signed-off-by: Rainer Boschung Signed-off-by: Valentin Longchamp Reviewed-by: York Sun --- board/keymile/kmp204x/kmp204x.c | 53 ++++++++++++++++++++++++++++++++++--- include/configs/km/kmp204x-common.h | 10 +++++++ 2 files changed, 60 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index bbb24531557..a6c23a2c358 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -33,12 +33,51 @@ int checkboard(void) return 0; } -/* TODO: implement the I2C deblocking function */ -int i2c_make_abort(void) +/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c + * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines + * For I2C only the low state is activly driven and high state is pulled-up + * by a resistor. Therefore the deblock GPIOs are used + * -> as an active output to drive a low state + * -> as an open-drain input to have a pulled-up high state + */ + +/* QRIO GPIOs used for deblocking */ +#define DEBLOCK_PORT1 GPIO_A +#define DEBLOCK_SCL1 20 +#define DEBLOCK_SDA1 21 + +/* By default deblock GPIOs are floating */ +static void i2c_deblock_gpio_cfg(void) +{ + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); + + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); +} + +void set_sda(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); +} + +void set_scl(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); +} + +int get_sda(void) +{ + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); +} + +int get_scl(void) { - return 1; + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); } + #define ZL30158_RST 8 #define ZL30343_RST 9 @@ -77,6 +116,14 @@ unsigned long get_board_sys_clk(unsigned long dummy) return 66666666; } +int misc_init_f(void) +{ + /* configure QRIO pis for i2c deblocking */ + i2c_deblock_gpio_cfg(); + + return 0; +} + #define NUM_SRDS_BANKS 2 #define PHY_RST 15 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 0461815ca13..afb22462472 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -210,6 +210,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT @@ -265,7 +266,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ /* I2C */ + #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ #define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ @@ -278,6 +282,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ -- cgit v1.3.1 From e95bbc8bac38918d2533b987a5c1b44e5bafe2d6 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 27 Jan 2014 11:49:08 +0100 Subject: kmp204x: add support for the kmcoge4 board The kmcoge4 board is the product board derived from the kmlion1 prototype. The main difference between the 2 boards is that the kmcoge4 does not configure the Local Bus controller for LCS2. Signed-off-by: Valentin Longchamp [York Sun: Minor change to boards.cfg to keep targets in order] Signed-off-by: York Sun --- boards.cfg | 1 + include/configs/kmp204x.h | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index 2dfd2b479c5..706ec96585a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -990,6 +990,7 @@ Active powerpc mpc85xx - gdsys p1022 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach +Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index 4158c8dd0f9..8bb35716912 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -13,6 +13,11 @@ #define CONFIG_HOSTNAME kmlion1 #define CONFIG_KM_BOARD_NAME "kmlion1" +/* KMCOGE4 */ +#elif defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME kmcoge4 +#define CONFIG_KM_BOARD_NAME "kmcoge4" + #else #error ("Board not supported") #endif @@ -42,6 +47,7 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM /* Local bus app1 Options */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM +#endif /* App2 Local bus */ #define CONFIG_SYS_LBAPP2_BASE 0xE0000000 @@ -63,6 +69,5 @@ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM /* Local bus app2 Options */ #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM -#endif #endif /* __CONFIG_H */ -- cgit v1.3.1 From cf7707a1df14e644d378c6d36f27e17dd666ac34 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 27 Jan 2014 11:49:10 +0100 Subject: KM: add the KM_UBI_PART_BOOT_OPTS #define This define can be used if the ubi boot partition (defined for all Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs some additionnal boot options. This is the case for the kmp204x boards since u-boot does not support NAND Flash subpage accesses on this platform, an additionnal argument that defines the VID offstet must be given to the kernel. The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this platform. Signed-off-by: Valentin Longchamp Reviewed-by: York Sun --- include/configs/km/keymile-common.h | 10 ++++++++-- include/configs/km/kmp204x-common.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 2a15ad469b1..a4e0f7cf686 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -99,11 +99,16 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP /* one flash chip only called boot */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ @@ -111,7 +116,8 @@ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=if test ${boot_bank} -eq 0; then; " \ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index afb22462472..e55b7220d90 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -15,6 +15,10 @@ #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" +/* an additionnal option is required for UBI as subpage access is + * supported in u-boot */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + #define CONFIG_NAND_ECC_BCH /* common KM defines */ -- cgit v1.3.1 From 47c1180c022bf67615349257dc3de98388bac398 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 27 Jan 2014 11:49:11 +0100 Subject: kmp204x: enable support for SPANSION SPI NOR The new prototype and the final series was moved from Micron to Spansion to have a better reset sequence that is easier to support. Signed-off-by: Valentin Longchamp Reviewed-by: York Sun --- include/configs/km/kmp204x-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index e55b7220d90..b9e1bacfa72 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -302,6 +302,7 @@ int get_scl(void); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE 0 -- cgit v1.3.1 From 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Sat, 18 Jan 2014 12:28:30 +0530 Subject: driver/ifc:Change accessor function to take care of endianness IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha Acked-by: York Sun --- README | 6 + arch/powerpc/include/asm/config_mpc85xx.h | 3 + drivers/mtd/nand/fsl_ifc_nand.c | 243 +++++++++++++++--------------- drivers/mtd/nand/fsl_ifc_spl.c | 60 ++++---- include/fsl_ifc.h | 42 ++++-- 5 files changed, 190 insertions(+), 164 deletions(-) (limited to 'include') diff --git a/README b/README index 176de61a331..6cdf355446f 100644 --- a/README +++ b/README @@ -472,6 +472,12 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 32e19be82fa..56587aebc0b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -22,6 +22,9 @@ #define FSL_DDR_VER_4_7 47 #define FSL_DDR_VER_5_0 50 +/* IP endianness */ +#define CONFIG_SYS_FSL_IFC_BE + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 1808a7ffba8..be5a16a1ba9 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -230,8 +230,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->page = page_addr; /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, page_addr); - out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); + ifc_out32(&ifc->ifc_nand.row0, page_addr); + ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); buf_num = page_addr & priv->bufnum_mask; @@ -294,23 +294,23 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int i; /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read/write seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) printf("%s: Flash Time Out Error\n", __func__); @@ -324,7 +324,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int sector_end = sector + chip->ecc.steps - 1; for (i = sector / 4; i <= sector_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i); @@ -364,30 +364,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip, /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ if (mtd->writesize > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); if (oob) - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); else - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } } @@ -408,7 +408,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, switch (command) { /* READ0 read the entire buffer to use hardware ECC. */ case NAND_CMD_READ0: { - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); set_addr(mtd, 0, page_addr, 0); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -424,7 +424,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: - out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); set_addr(mtd, column, page_addr, 1); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -441,19 +441,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_PARAM) timing = IFC_FIR_OP_RBCD; - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (timing << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - command << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, column); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (timing << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + command << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, column); /* * although currently it's 8 bytes for READID, we always read * the maximum 256 bytes(for PARAM) */ - out_be32(&ifc->ifc_nand.nand_fbcr, 256); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 256); ctrl->read_bytes = 256; set_addr(mtd, 0, 0, 0); @@ -468,16 +468,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* ERASE2 uses the block and page address from ERASE1 */ case NAND_CMD_ERASE2: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); ctrl->read_bytes = 0; fsl_ifc_run_command(mtd); return; @@ -494,17 +494,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_WBCD << + IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | @@ -513,18 +514,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= @@ -539,7 +540,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, column -= mtd->writesize; ctrl->oob = 1; } - out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); + ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); set_addr(mtd, column, page_addr, ctrl->oob); return; } @@ -547,21 +548,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ case NAND_CMD_PAGEPROG: if (ctrl->oob) - out_be32(&ifc->ifc_nand.nand_fbcr, - ctrl->index - ctrl->column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, + ctrl->index - ctrl->column); else - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); fsl_ifc_run_command(mtd); return; case NAND_CMD_STATUS: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -572,10 +573,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, return; case NAND_CMD_RESET: - out_be32(&ifc->ifc_nand.nand_fir0, - IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); fsl_ifc_run_command(mtd); return; @@ -647,8 +648,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ctrl->index < ctrl->read_bytes) { - data = in_be16((uint16_t *)&ctrl-> - addr[ctrl->index]); + data = ifc_in16((uint16_t *)&ctrl-> + addr[ctrl->index]); ctrl->index += 2; return (uint8_t)data; } @@ -727,12 +728,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return NAND_STATUS_FAIL; /* Use READ_STATUS command, but wait for the device to be ready */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << - IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -741,7 +742,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) return NAND_STATUS_FAIL; - nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); /* Chip sometimes reporting write protect even when it's not */ nand_fsr = nand_fsr | NAND_STATUS_WP; @@ -784,17 +785,17 @@ static void fsl_ifc_ctrl_init(void) ifc_ctrl->regs = IFC_BASE_ADDR; /* clear event registers */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); - out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); /* Enable error and event for any detected errors */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, - IFC_NAND_EVTER_EN_OPC_EN | - IFC_NAND_EVTER_EN_PGRDCMPL_EN | - IFC_NAND_EVTER_EN_FTOER_EN | - IFC_NAND_EVTER_EN_WPER_EN); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); - out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); } static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) @@ -810,50 +811,50 @@ static void fsl_ifc_sram_init(void) cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ - csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); - csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); /* chage PageSize 8K and SpareSize 1K*/ csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); /* READID */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, 0x0); - out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0); /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, 0x0); - out_be32(&ifc->ifc_nand.col0, 0x0); + ifc_out32(&ifc->ifc_nand.row0, 0x0); + ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -883,8 +884,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { phys_addr_t phys_addr = virt_to_phys(addr); - cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); - csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); + cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { @@ -1004,7 +1005,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->ecc.mode = NAND_ECC_SOFT; } - ver = in_be32(&ifc_ctrl->regs->ifc_rev); + ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); if (ver == FSL_IFC_V1_1_0) fsl_ifc_sram_init(); diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 6b43496f0ed..2f82f7c5c61 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) bufnum_end = bufnum + bufperpage - 1; do { - status = in_be32(&ifc->ifc_nand.nand_evter_stat); + status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); } while (!(status & IFC_NAND_EVTER_STAT_OPC)); if (status & IFC_NAND_EVTER_STAT_FTOER) { @@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) } for (i = bufnum / 4; i <= bufnum_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = bufnum; i <= bufnum_end; i++) { if (check_read_ecc(buf, eccstat, i, page_size)) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); } static inline int bad_block(uchar *marker, int port_size) @@ -140,38 +140,38 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) blk_size = pages_per_blk * page_size; /* Open Full SRAM mapping for spare are access */ - out_be32(&ifc->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc->ifc_nand.ncfgr, 0x0); /* Clear Boot events */ - out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); /* Program FIR/FCR for Large/Small page */ if (page_size > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } /* Program FBCR = 0 for full page read */ - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); /* Read and copy u-boot on SDRAM from NAND device, In parallel * check for Bad block if found skip it and read continue to @@ -184,11 +184,11 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) bufnum = pg_no & bufnum_mask; sram_addr = bufnum * page_size * 2; - out_be32(&ifc->ifc_nand.row0, pg_no); - out_be32(&ifc->ifc_nand.col0, 0); + ifc_out32(&ifc->ifc_nand.row0, pg_no); + ifc_out32(&ifc->ifc_nand.col0, 0); /* start read */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for read to complete */ nand_wait(&buf[sram_addr], bufnum, page_size); diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index be6c10715b1..58a6efdfe05 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,6 +12,20 @@ #include #include + +#ifdef CONFIG_SYS_FSL_IFC_LE +#define ifc_in32(a) in_le32(a) +#define ifc_out32(a, v) out_le32(a, v) +#define ifc_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_IFC_BE) +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined +#endif + + /* * CSPR - Chip Select Property Register */ @@ -773,20 +787,22 @@ extern void init_early_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) #define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) enum ifc_chip_sel { IFC_CS0, -- cgit v1.3.1 From b9b53a60ae1148fa478c21f19fe89b8991ef0692 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 23 Jan 2014 13:17:01 -0700 Subject: ARM: tegra: set env vars to indicate Cardhu A04 support The U-Boot "cardhu" build supports only revision 4 of the Cardhu board and later compatible revisions. Hence, set $board_name in the default environment to "cardhu-a04" rather than just "cardhu". The Linux kernel has separate DTs for Cardhu A02 and A04, although the former isn't really supported any more. Consequently, the kernel DT file that matches the U-Boot cardhu build is "tegra30-cardhu-a04.dtb" rather than "tegra30-cardhu.dtb". Set the $fdtfile default environment variable to reflect this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/cardhu.h | 4 ++++ include/configs/tegra-common-post.h | 7 ++++++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 4abb03ea56d..e80d1a6fa3a 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -30,6 +30,10 @@ #define V_PROMPT "Tegra30 (Cardhu) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" +#define BOARD_EXTRA_ENV_SETTINGS \ + "board_name=cardhu-a04\0" \ + "fdtfile=tegra30-cardhu-a04.dtb\0" + /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index a3242fe6129..020b9b17b1d 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -129,10 +129,15 @@ "stderr=serial" STDOUT_LCD "\0" \ "" +#ifndef BOARD_EXTRA_ENV_SETTINGS +#define BOARD_EXTRA_ENV_SETTINGS +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - BOOTCMDS_COMMON + BOOTCMDS_COMMON \ + BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) #define CONFIG_FDT_SPI -- cgit v1.3.1 From 09266b270fb8bba934317d2d5a22063ac45bf960 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 23 Jan 2014 13:17:05 -0700 Subject: ARM: tegra: clear $usb_need_init each boot $usb_need_init prevents "usb start" from being run multiple times for each boot attempt, i.e. once for USB storage, another for PXE, and another for DHCP. However, the flag that's used to determine when to run "usb start" is never cleared, so a subsequent "boot" command will never probe for a freshly plugged in USB device. Fix this so that new USB devices will be probed once per boot attempt. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 020b9b17b1d..e1a3bbc6263 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -99,6 +99,7 @@ BOOTCMDS_DHCP #define CONFIG_BOOTCOMMAND \ + "set usb_need_init; " \ "for target in ${boot_targets}; do run bootcmd_${target}; done" #endif -- cgit v1.3.1 From a73ca4789fddce35936dd8decb1522f08b6cb620 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 24 Jan 2014 12:46:06 -0700 Subject: mmc: tegra: support Tegra124 Tegra124's MMC controller is very similar to earlier SoC generations, and can be supported by the same driver. However, there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. This patch updates the driver to support that new compatible value. That said, the HW differences are only relevant when enabling certain high-performance transfer modes. Since the driver is currently very simple and doesn't enable those modes, we don't actually need to address any of these HW differences in the code yet, hence the simple nature of this patch. Signed-off-by: Stephen Warren Acked-by: Pantelis Antoniou Tested-by: Thierry Reding Acked-by: Simon Glass Signed-off-by: Tom Warren --- drivers/mmc/tegra_mmc.c | 9 +++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 3 files changed, 11 insertions(+) (limited to 'include') diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index e1817e24f6d..3d1ce1263c8 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -668,6 +668,15 @@ void tegra_mmc_init(void) const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra124 MMC controllers are present */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS); + debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T30 mmc node(s)!\n", __func__); + return; + } + /* See if any Tegra30 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); diff --git a/include/fdtdec.h b/include/fdtdec.h index 433d6a7c025..19bab794481 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -59,6 +59,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 207314fa72f..1fecab3fbc3 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -32,6 +32,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), -- cgit v1.3.1 From f7dc4ac37c8e2448aa88209e5d00fa377ca98ced Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 24 Jan 2014 12:46:18 -0700 Subject: ARM: tegra: add Venice2 (Tegra124) board These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC files. PMIC init will be moved to pmic_common_init later. This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display and WB/LP0 are not supported yet. Signed-off-by: Tom Warren Signed-off-by: Stephen Warren Tested-by: Thierry Reding Signed-off-by: Tom Warren --- board/nvidia/venice2/Makefile | 9 + board/nvidia/venice2/as3722_init.c | 91 +++++++ board/nvidia/venice2/as3722_init.h | 38 +++ board/nvidia/venice2/pinmux-config-venice2.h | 339 +++++++++++++++++++++++++++ board/nvidia/venice2/venice2.c | 33 +++ boards.cfg | 1 + include/configs/tegra124-common.h | 82 +++++++ include/configs/venice2.h | 79 +++++++ 8 files changed, 672 insertions(+) create mode 100644 board/nvidia/venice2/Makefile create mode 100644 board/nvidia/venice2/as3722_init.c create mode 100644 board/nvidia/venice2/as3722_init.h create mode 100644 board/nvidia/venice2/pinmux-config-venice2.h create mode 100644 board/nvidia/venice2/venice2.c create mode 100644 include/configs/tegra124-common.h create mode 100644 include/configs/venice2.h (limited to 'include') diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile new file mode 100644 index 00000000000..5fac5ab1f81 --- /dev/null +++ b/board/nvidia/venice2/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += as3722_init.o +obj-y += venice2.o diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c new file mode 100644 index 00000000000..960fea7ee7e --- /dev/null +++ b/board/nvidia/venice2/as3722_init.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "as3722_init.h" + +/* AS3722-PMIC-specific early init code - get CPU rails up, etc */ + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} + +void pmic_enable_cpu_vdd(void) +{ + debug("%s entry\n", __func__); + + /* Don't need to set up VDD_CORE - already done - by OTP */ + + debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); + /* + * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); + /* + * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); + /* + * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.2V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__); + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +} diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h new file mode 100644 index 00000000000..2a9e7cdf872 --- /dev/null +++ b/board/nvidia/venice2/as3722_init.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* AS3722-PMIC-specific early init regs */ + +#define AS3722_I2C_ADDR 0x80 + +#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ +#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ +#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ +#define AS3722_SDCONTROL_REG 0x4D + +#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ +#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ +#define AS3722_LDCONTROL_REG 0x4E + +#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) +#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) + +#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) +#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) + +#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) +#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) + +#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) +#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) + +#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) +#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) + +#define I2C_SEND_2_BYTES 0x0A02 + +void pmic_enable_cpu_vdd(void); diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h new file mode 100644 index 00000000000..50868e6488d --- /dev/null +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_VENICE2_H_ +#define _PINMUX_CONFIG_VENICE2_H_ + +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define USB_PINMUX CEC_PINMUX + +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + +static struct pingroup_config tegra124_pinmux_common[] = { + /* EXTPERIPH1 pinmux */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + + /* I2S0 pinmux */ + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + + /* I2S1 pinmux */ + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 pinmux */ + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* CLDVFS pinmux */ + DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), + + /* EC KBC/SPI */ + DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT), + + /* I2C3 (TPM) pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* UARTD pinmux (UART4 on Servo board, unused) */ + DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + + /* SPI4 (Winbond 'boot ROM') */ + DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT), + + /* Touch IRQ */ + DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT), + + /* PWM1 pinmux */ + DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT), + + /* BLINK pinmux */ + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), + + /* KBC pinmux */ + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), + + /* Misc */ + DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT), + + /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */ + DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT), + + /* I2CPWR pinmux (I2C5) */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* RTCK pinmux */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), + + /* CLK pinmux */ + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), + + /* PWRON pinmux */ + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), + + /* CPU pinmux */ + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), + + /* PMI pinmux */ + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), + + /* RESET_OUT_N pinmux */ + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), + + /* EXTPERIPH3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* UARTB, GPS */ + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UARTC (WIFI/BT) */ + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + + /* CEC pinmux */ + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* I2C4 (HDMI_DDC) pinmux */ + DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + + /* USB pinmux */ + USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* Unused, marked SNN_ on schematic, TRISTATE 'em */ + DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT), +}; + +static struct pingroup_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT), +}; + +/* Initially setting all used GPIO's to non-TRISTATE */ +static struct pingroup_config tegra124_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT), + + /* EN_VDD_BL */ + DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT), + + /* MODEM */ + DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), + + /* BOOT_SEL0-3 */ + DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), + + /* TS_SHDN_L */ + DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT), +}; + +static struct padctrl_config venice2_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), +}; +#endif /* PINMUX_CONFIG_VENICE2_H */ diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c new file mode 100644 index 00000000000..1ed2fd788ec --- /dev/null +++ b/board/nvidia/venice2/venice2.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "pinmux-config-venice2.h" +#include + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_table(tegra124_pinmux_set_nontristate, + ARRAY_SIZE(tegra124_pinmux_set_nontristate)); + + pinmux_config_table(tegra124_pinmux_common, + ARRAY_SIZE(tegra124_pinmux_common)); + + pinmux_config_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl)); +} diff --git a/boards.cfg b/boards.cfg index 2dfd2b479c5..a5165c8f53a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -364,6 +364,7 @@ Active arm armv7 zynq xilinx zynq Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren +Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h new file mode 100644 index 00000000000..32d5bc9c950 --- /dev/null +++ b/include/configs/tegra124-common.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_COMMON_H_ +#define _TEGRA124_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * High Level Configuration Options + */ +#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */ + +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* Total I2C ports on Tegra124 */ +#define TEGRA_I2C_NUM_CONTROLLERS 5 + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + +#endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h new file mode 100644 index 00000000000..91808e92038 --- /dev/null +++ b/include/configs/venice2.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Venice2) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 7bc5c8c93032a7b86e268a172955e15b84f1aac3 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 24 Jan 2014 12:46:19 -0700 Subject: ARM: tegra: fix "bootp" issue for Tegra124 too Fix the timeout issue after running "bootp" command in U-Boot console. TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a controller reset and before RUN bit is set (per technical reference manual). Signed-off-by: Jim Lin Signed-off-by: Stephen Warren Tested-by: Thierry Reding Signed-off-by: Tom Warren --- include/configs/tegra124-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 32d5bc9c950..0a4541bd20e 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -78,5 +78,6 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA124_COMMON_H_ */ -- cgit v1.3.1 From 08d0d6f32ecf75a6c5dede5fc9ee84b84d8b90e7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Nov 2013 13:39:02 -0800 Subject: common: Add new clk command Command provides just dump subcommand for showing clock frequencies in a soc. Signed-off-by: Michal Simek Acked-by: Stefano Babic --- README | 1 + common/Makefile | 1 + common/cmd_clk.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++ include/clk.h | 6 ++++++ include/config_cmd_all.h | 1 + 5 files changed, 60 insertions(+) create mode 100644 common/cmd_clk.c create mode 100644 include/clk.h (limited to 'include') diff --git a/README b/README index 176de61a331..ba4be660be9 100644 --- a/README +++ b/README @@ -896,6 +896,7 @@ The following options need to be configured: CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... diff --git a/common/Makefile b/common/Makefile index 4d99ecd6168..a83246ee27b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 00000000000..6d3d46a1844 --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +int __weak soc_clk_dump(void) +{ + puts("Not implemented\n"); + return 1; +} + +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return soc_clk_dump(); +} + +static cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +}; + +static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'clk' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +#ifdef CONFIG_SYS_LONGHELP +static char clk_help_text[] = + "dump - Print clock frequencies"; +#endif + +U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); diff --git a/include/clk.h b/include/clk.h new file mode 100644 index 00000000000..df4570c6f54 --- /dev/null +++ b/include/clk.h @@ -0,0 +1,6 @@ +#ifndef _CLK_H_ +#define _CLK_H_ + +int soc_clk_dump(void); + +#endif /* _CLK_H_ */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d84706969d1..3e8983f2443 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CLK /* Clock support */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ -- cgit v1.3.1 From 22ff7f4d195b49ca7db5b2a0c3aa2c987ab88c34 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 21 Jan 2014 07:26:58 +0100 Subject: microblaze: Enable buffer write for NOR flashes It speeds up writing a lot. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index aa8d59d6e91..35e5a4acfab 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -200,7 +200,8 @@ # define CONFIG_SYS_MAX_FLASH_SECT 512 /* hardware flash protection */ # define CONFIG_SYS_FLASH_PROTECTION - +/* use buffered writes (20x faster) */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # ifdef RAMENV # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 -- cgit v1.3.1 From 9d24274509cdd463992dc1fb1a2820d6a4b6d21d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 21 Jan 2014 07:30:37 +0100 Subject: microblaze: Add SPL support Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek --- arch/microblaze/cpu/Makefile | 1 + arch/microblaze/cpu/spl.c | 55 +++++++++++++++++++++++++++++++++ arch/microblaze/cpu/start.S | 12 ++++++++ arch/microblaze/cpu/timer.c | 8 ++++- arch/microblaze/cpu/u-boot-spl.lds | 57 ++++++++++++++++++++++++++++++++++ arch/microblaze/include/asm/spl.h | 16 ++++++++++ arch/microblaze/include/asm/u-boot.h | 1 + arch/microblaze/lib/board.c | 11 ++++++- include/configs/microblaze-generic.h | 60 ++++++++++++++++++++++++++++++++++++ 9 files changed, 219 insertions(+), 2 deletions(-) create mode 100644 arch/microblaze/cpu/spl.c create mode 100644 arch/microblaze/cpu/u-boot-spl.lds create mode 100644 arch/microblaze/include/asm/spl.h (limited to 'include') diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 6e201f2d540..4955e812360 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -8,3 +8,4 @@ extra-y = start.o obj-y = irq.o obj-y += cpu.o interrupts.o cache.o exception.o timer.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c new file mode 100644 index 00000000000..091226133e4 --- /dev/null +++ b/arch/microblaze/cpu/spl.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +bool boot_linux; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NOR; +} + +/* Board initialization after bss clearance */ +void spl_board_init(void) +{ + gd = (gd_t *)CONFIG_SPL_STACK_ADDR; + + /* enable console uart printing */ + preloader_console_init(); +} + +#ifdef CONFIG_SPL_OS_BOOT +void __noreturn jump_to_image_linux(void *arg) +{ + debug("Entering kernel arg pointer: 0x%p\n", arg); + typedef void (*image_entry_arg_t)(char *, ulong, ulong) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t)spl_image.entry_point; + + image_entry(NULL, 0, (ulong)arg); +} +#endif /* CONFIG_SPL_OS_BOOT */ + +int spl_start_uboot(void) +{ +#ifdef CONFIG_SPL_OS_BOOT + if (boot_linux) + return 0; +#endif + + return 1; +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 89280248387..1757bbfa94b 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -22,6 +22,11 @@ _start: */ mts rmsr, r0 /* disable cache */ + +#if defined(CONFIG_SPL_BUILD) + addi r1, r0, CONFIG_SPL_STACK_ADDR + addi r1, r1, -4 /* Decrement SP to top of memory */ +#else addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET addi r1, r1, -4 /* Decrement SP to top of memory */ @@ -115,6 +120,7 @@ _start: sh r7, r0, r8 rsubi r8, r10, 0x26 sh r6, r0, r8 +#endif /* BUILD_SPL */ /* Flush cache before enable cache */ addik r5, r0, 0 @@ -139,9 +145,14 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ +#ifndef CONFIG_SPL_BUILD brai board_init_f +#else + brai board_init_r +#endif 1: bri 1b +#ifndef CONFIG_SPL_BUILD /* * Read 16bit little endian */ @@ -174,3 +185,4 @@ out16: bslli r3, r6, 8 rtsd r15, 8 or r0, r0, r0 .end out16 +#endif diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index 69ae6d4d873..3960bbb08a8 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -34,6 +34,7 @@ void __udelay(unsigned long usec) } } +#ifndef CONFIG_SPL_BUILD static void timer_isr(void *arg) { timestamp++; @@ -62,10 +63,15 @@ int timer_init (void) if (ret) tmr = NULL; } - /* No problem if timer is not found/initialized */ return 0; } +#else +int timer_init(void) +{ + return 0; +} +#endif /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds new file mode 100644 index 00000000000..96353cd96ca --- /dev/null +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + arch/microblaze/cpu/start.o (.text) + *(.text) + *(.text.*) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + *(.data.*) + __data_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.sbss) + *(.scommon) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + } + __end = . ; +} + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h new file mode 100644 index 00000000000..c1cae6cf0fe --- /dev/null +++ b/arch/microblaze/include/asm/spl.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_MICROBLAZE_SPL_H_ +#define _ASM_MICROBLAZE_SPL_H_ + +#define BOOT_DEVICE_RAM 1 +#define BOOT_DEVICE_NOR 2 +#define BOOT_DEVICE_SPI 3 + +#endif diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index 31b014c77d2..ab3f23202d6 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -25,6 +25,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ unsigned int bi_baudrate; /* Console Baudrate */ + ulong bi_boot_params; /* where this board expects params */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index d22aa85c24a..59956a8673d 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -50,10 +50,14 @@ init_fnc_t *init_sequence[] = { fdtdec_check_fdt, #endif serial_init, +#ifndef CONFIG_SPL_BUILD console_init_f, +#endif display_banner, +#ifndef CONFIG_SPL_BUILD interrupts_init, timer_init, +#endif NULL, }; @@ -66,7 +70,7 @@ void board_init_f(ulong not_used) gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET); bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - GENERATED_BD_INFO_SIZE); -#if defined(CONFIG_CMD_FLASH) +#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD) ulong flash_size = 0; #endif asm ("nop"); /* FIXME gd is not initialize - wait */ @@ -88,9 +92,12 @@ void board_init_f(ulong not_used) /* FDT is at end of image */ gd->fdt_blob = (void *)__end; #endif + +#ifndef CONFIG_SPL_BUILD /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, (uintptr_t)gd->fdt_blob); +#endif /* * The Malloc area is immediately below the monitor copy in DRAM @@ -110,6 +117,7 @@ void board_init_f(ulong not_used) hang(); } +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_OF_CONTROL /* For now, put this check after the console is ready */ if (fdtdec_prepare_fdt()) @@ -190,4 +198,5 @@ void board_init_f(ulong not_used) WATCHDOG_RESET(); main_loop(); } +#endif /* CONFIG_SPL_BUILD */ } diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 35e5a4acfab..486787e1479 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -447,4 +447,64 @@ # undef CONFIG_PHYLIB #endif +/* SPL part */ +#define CONFIG_SPL +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_NOR_SUPPORT + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x60000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x40000) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ + 0x1000000) + +/* SP location before relocation, must use scratch RAM */ +/* BRAM start */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +/* BRAM size - will be generated */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100 + +/* + * The main reason to do it in this way is that MALLOC_START + * can't be defined - common/spl/spl.c + */ +#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0) +# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \ + CONFIG_SYS_SPL_MALLOC_SIZE) +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START +#else +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END +#endif + +/* Just for sure that there is a space for stack */ +#define CONFIG_SPL_STACK_SIZE 0x100 + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_INIT_RAM_ADDR - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE - \ + CONFIG_SPL_STACK_SIZE) + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 13a49c3a739bec2414c2833e0393469aab93e870 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Tue, 4 Feb 2014 05:25:47 -0600 Subject: config: add config_distro_defaults.h describe a set of default features that distros can rely on being available. having this common definition means that distros can easily support systems implementing them. Signed-off-by: Dennis Gilmore --- include/config_distro_defaults.h | 55 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 include/config_distro_defaults.h (limited to 'include') diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h new file mode 100644 index 00000000000..11b5b793046 --- /dev/null +++ b/include/config_distro_defaults.h @@ -0,0 +1,55 @@ +/* + * Copyright 2013-2014 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H +#define _CONFIG_CMD_DISTRO_DEFAULTS_H + +/* + * List of all commands and options that when defined enables support for features + * required by distros to support boards in a standardised and consitant manner. + */ + +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_SUBNETMASK + +#if defined(__arm__) +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7" +#else +#define CONFIG_BOOTP_VCI_STRING "U-boot.arm" +#endif +#endif + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_PXE + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_BOOTDELAY 2 +#define CONFIG_SYS_LONGHELP +#define CONFIG_MENU +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SYS_HUSH_PARSER + +#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */ -- cgit v1.3.1 From e141652b9cd0cb4f899f7a0fd71c8a438300e365 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 08:04:38 -0500 Subject: config: Fix line lengths in include/config_distro_defaults.h Signed-off-by: Tom Rini --- include/config_distro_defaults.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index 11b5b793046..5d18a4b903a 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -8,8 +8,9 @@ #define _CONFIG_CMD_DISTRO_DEFAULTS_H /* - * List of all commands and options that when defined enables support for features - * required by distros to support boards in a standardised and consitant manner. + * List of all commands and options that when defined enables support for + * features required by distros to support boards in a standardised and + * consitant manner. */ #define CONFIG_BOOTP_BOOTPATH -- cgit v1.3.1 From e0059eaef18dbdc65ee420a337aecfa555e8d493 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:44 +0100 Subject: usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driver The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/s3c_udc_otg.c | 19 +++++----- drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 63 ++++++++++++++++--------------- include/usb/s3c_udc.h | 5 +-- 3 files changed, 43 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index ba17a04265e..63d4487a9bb 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -843,7 +843,7 @@ static struct s3c_udc memory = { int s3c_udc_probe(struct s3c_plat_otg_data *pdata) { struct s3c_udc *dev = &memory; - int retval = 0, i; + int retval = 0; debug("%s: %p\n", __func__, pdata); @@ -864,16 +864,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) the_controller = dev; - for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) { - dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE, - DMA_BUFFER_SIZE); - dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i]; - invalidate_dcache_range((unsigned long) dev->dma_buf[i], - (unsigned long) (dev->dma_buf[i] - + DMA_BUFFER_SIZE)); + usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, + ROUND(sizeof(struct usb_ctrlrequest), + CONFIG_SYS_CACHELINE_SIZE)); + if (!usb_ctrl) { + error("No memory available for UDC!\n"); + return -ENOMEM; } - usb_ctrl = dev->dma_buf[0]; - usb_ctrl_dma_addr = dev->dma_addr[0]; + + usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; udc_reinit(dev); diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 7c7176bfd3c..06dfeed9051 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -110,8 +110,7 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) ctrl = readl(®->out_endp[ep_num].doepctl); - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->out_endp[ep_num].doepdma); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); @@ -134,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) u32 *buf, ctrl = 0; u32 length, pktcnt; u32 ep_num = ep_index(ep); - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; buf = req->req.buf + req->req.actual; length = req->req.length - req->req.actual; @@ -144,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) ep->len = length; ep->dma_buf = buf; - memcpy(p, ep->dma_buf, length); - flush_dcache_range((unsigned long) p , - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); if (length == 0) pktcnt = 1; @@ -160,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) while (readl(®->grstctl) & TX_FIFO_FLUSH) ; - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->in_endp[ep_num].diepdma); + writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), ®->in_endp[ep_num].dieptsiz); @@ -194,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) struct s3c_ep *ep = &dev->ep[ep_num]; struct s3c_request *req = NULL; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; if (list_empty(&ep->queue)) { debug_cond(DEBUG_OUT_EP != 0, @@ -214,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) xfer_size = ep->len - xfer_size; - invalidate_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); - - memcpy(ep->dma_buf, p, ep->len); + /* + * NOTE: + * + * Please be careful with proper buffer allocation for USB request, + * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only + * with starting address, but also its size shall be a cache line + * multiplication. + * + * This will prevent from corruption of data allocated immediatelly + * before or after the buffer. + * + * For armv7, the cache_v7.c provides proper code to emit "ERROR" + * message to warn users. + */ + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); req->req.actual += min(xfer_size, req->req.length - req->req.actual); is_short = (xfer_size < ep->ep.maxpacket); @@ -711,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) { - u32 bytes; - - bytes = sizeof(struct usb_ctrlrequest); - - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)], - (unsigned long) ep->dev->dma_buf[ep_index(ep)] - + DMA_BUFFER_SIZE); + invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + + ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); debug_cond(DEBUG_EP0 != 0, - "%s: bytes=%d, ep_index=%d %p\n", __func__, - bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]); + "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, + max, ep_index(ep), cp); - return bytes; + return max; } /** @@ -855,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev) return 1; } -u16 g_status; - int s3c_udc_get_status(struct s3c_udc *dev, struct usb_ctrlrequest *crq) { u8 ep_num = crq->wIndex & 0x7F; + u16 g_status = 0; u32 ep_ctrl; - u32 *p = the_controller->dma_buf[1]; debug_cond(DEBUG_SETUP != 0, "%s: *** USB_REQ_GET_STATUS\n", __func__); @@ -900,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev, return 1; } - memcpy(p, &g_status, sizeof(g_status)); + memcpy(usb_ctrl, &g_status, sizeof(g_status)); - flush_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) usb_ctrl, + (unsigned long) usb_ctrl + + ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); - writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma); + writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), ®->in_endp[EP0_CON].dieptsiz); diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 734c6cd2f7c..6dead2fb46d 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -19,7 +19,7 @@ /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ -#define DMA_BUFFER_SIZE (4096*4) +#define DMA_BUFFER_SIZE (16*SZ_1K) #define EP0_FIFO_SIZE 64 #define EP_FIFO_SIZE 512 @@ -81,9 +81,6 @@ struct s3c_udc { struct s3c_plat_otg_data *pdata; - void *dma_buf[S3C_MAX_ENDPOINTS+1]; - dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1]; - int ep0state; struct s3c_ep ep[S3C_MAX_ENDPOINTS]; -- cgit v1.3.1 From 373ee048a8bdc3291aa88b93da183a0bc3b34a22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:04:58 +0100 Subject: ARM: IXP: Remove actux1 board The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- board/actux1/Makefile | 8 -- board/actux1/actux1.c | 148 ------------------------------- board/actux1/actux1_hw.h | 41 --------- board/actux1/u-boot.lds | 99 --------------------- boards.cfg | 4 - doc/README.scrapyard | 1 + include/configs/actux1.h | 226 ----------------------------------------------- 7 files changed, 1 insertion(+), 526 deletions(-) delete mode 100644 board/actux1/Makefile delete mode 100644 board/actux1/actux1.c delete mode 100644 board/actux1/actux1_hw.h delete mode 100644 board/actux1/u-boot.lds delete mode 100644 include/configs/actux1.h (limited to 'include') diff --git a/board/actux1/Makefile b/board/actux1/Makefile deleted file mode 100644 index 05a8669113c..00000000000 --- a/board/actux1/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux1.o diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c deleted file mode 100644 index 03ccd936b43..00000000000 --- a/board/actux1/actux1.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "actux1_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HwRel */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* Setup GPIOs for PCI INTA */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - ACTUX1_LED1(2); - ACTUX1_LED2(2); - ACTUX1_LED3(0); - ACTUX1_LED4(0); - ACTUX1_LED5(0); - ACTUX1_LED6(0); - ACTUX1_LED7(0); - - ACTUX1_HS(ACTUX1_HS_DCD); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-1 rev."); - putc(ACTUX1_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX1_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - u16 id1, id2; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); - - id2 &= 0xFFF0; /* mask out revision bits */ - - if (id1 == 0x13 && id2 == 0x78e0) { - /* - * LXT971/LXT972 PHY: set LED outputs: - * LED1(green) = Link/ACT, - * LED2 (unused) = LINK, - * LED3(red) = Coll - */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); - } else if (id1 == 0x143 && id2 == 0xbc30) { - /* BCM5241: default values are OK */ - } else - printf("unknown ethernet PHY ID: %x %x\n", id1, id2); -} diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h deleted file mode 100644 index 5627f247960..00000000000 --- a/board/actux1/actux1_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX1_HW_H -#define _ACTUX1_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) -#define ACTUX1_HS_DCD 0x01 -#define ACTUX1_HS_DSR 0x02 - -#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_PCI1_INTA 2 -#define CONFIG_SYS_GPIO_PCI2_INTA 3 -#define CONFIG_SYS_GPIO_I2C_SDA 4 -#define CONFIG_SYS_GPIO_I2C_SCL 5 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds deleted file mode 100644 index 4716e4f0e03..00000000000 --- a/board/actux1/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux1/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/boards.cfg b/boards.cfg index 2dfd2b479c5..b3faeb4c455 100644 --- a/boards.cfg +++ b/boards.cfg @@ -381,10 +381,6 @@ Active arm ixp - - - Active arm ixp - - - actux3 - Michael Schwingen Active arm ixp - - - actux4 - Michael Schwingen Active arm ixp - - - dvlhost - Michael Schwingen -Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen -Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen -Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen -Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen Active arm pxa - - - balloon3 - Marek Vasut Active arm pxa - - - h2200 - Lukasz Dalek Active arm pxa - - - palmld - Marek Vasut diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2aed8559939..0ae5e4de3f8 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +actux1 arm ixp - 2014-01-28 Michael Schwingen mx1ads arm arm920t - 2014-01-13 mini2440 arm arm920t - 2014-01-13 Gabriel Huau omap730p2 arm arm926ejs 79c5c08d 2013-11-11 diff --git a/include/configs/actux1.h b/include/configs/actux1.h deleted file mode 100644 index 9b8bd78943f..00000000000 --- a/include/configs/actux1.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX1 1 - -#define CONFIG_MACH_TYPE 1479 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113842 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#ifdef CONFIG_RAM_32MB -# define CONFIG_SYS_SDR_CONFIG 0x18 -# define PHYS_SDRAM_1_SIZE 0x02000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x02000000 -#else /* 16MB SDRAM */ -# define CONFIG_SYS_SDR_CONFIG 0x3A -# define PHYS_SDRAM_1_SIZE 0x01000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x01000000 -#endif - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#ifdef CONFIG_FLASH2X2 -# define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 40 -# define PHYS_FLASH_1 0x50000000 -# define PHYS_FLASH_2 0x50200000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } -#endif -#ifdef CONFIG_FLASH1X8 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 140 -# define PHYS_FLASH_1 0x50000000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#endif - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0 -/* NPE1 PHY address (HW Release E only) */ -#define CONFIG_PHY1_ADDR 1 -/* MII PHY management */ -#define CONFIG_MII 1 -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 - -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux1/uImage\0" \ - "rootfile=actux1/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux1/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 13e0ee7f9acf6f1af0db7147ea8d157668f45ca6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:06:45 +0100 Subject: ARM: IXP: Remove actux2 board The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- board/actux2/Makefile | 8 -- board/actux2/actux2.c | 122 ---------------------------- board/actux2/actux2_hw.h | 43 ---------- board/actux2/u-boot.lds | 99 ----------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/actux2.h | 206 ----------------------------------------------- 7 files changed, 1 insertion(+), 479 deletions(-) delete mode 100644 board/actux2/Makefile delete mode 100644 board/actux2/actux2.c delete mode 100644 board/actux2/actux2_hw.h delete mode 100644 board/actux2/u-boot.lds delete mode 100644 include/configs/actux2.h (limited to 'include') diff --git a/board/actux2/Makefile b/board/actux2/Makefile deleted file mode 100644 index 24cbff1b473..00000000000 --- a/board/actux2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux2.o diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c deleted file mode 100644 index e578cd09964..00000000000 --- a/board/actux2/actux2.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include - -#include "actux2_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: IPAC-X */ - writel(0x94d10013, IXP425_EXP_CS1); - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HW release register */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - - /* Setup GPIOs for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - - ACTUX2_LED1(1); - ACTUX2_LED2(0); - ACTUX2_LED3(0); - ACTUX2_LED4(0); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-2 rev."); - putc(ACTUX2_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX2_BOARDREL; -} - -void reset_phy(void) -{ - /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write("NPE0", 29, 31, 0x175C); -} diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h deleted file mode 100644 index 57c6fa7076e..00000000000 --- a/board/actux2/actux2_hw.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX2_HW_H -#define _ACTUX2_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) - -#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) -#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_DBGINT 0 -#define CONFIG_SYS_GPIO_ETHINT 1 -#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ -#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ -#define CONFIG_SYS_GPIO_UNUSED4 4 -#define CONFIG_SYS_GPIO_UNUSED5 5 -#define CONFIG_SYS_GPIO_DSR 6 /* Out */ -#define CONFIG_SYS_GPIO_DCD 7 /* Out */ -#define CONFIG_SYS_GPIO_IPAC_INT 8 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds deleted file mode 100644 index f00d7c72b1f..00000000000 --- a/board/actux2/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux2/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/boards.cfg b/boards.cfg index b3faeb4c455..d3ebb4f58b5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,7 +377,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren -Active arm ixp - - - actux2 - Michael Schwingen Active arm ixp - - - actux3 - Michael Schwingen Active arm ixp - - - actux4 - Michael Schwingen Active arm ixp - - - dvlhost - Michael Schwingen diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0ae5e4de3f8..0ac90a97bac 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +actux2 arm ixp - 2014-01-28 Michael Schwingen actux1 arm ixp - 2014-01-28 Michael Schwingen mx1ads arm arm920t - 2014-01-13 mini2440 arm arm920t - 2014-01-13 Gabriel Huau diff --git a/include/configs/actux2.h b/include/configs/actux2.h deleted file mode 100644 index f0cbff79cae..00000000000 --- a/include/configs/actux2.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX2 1 - -#define CONFIG_MACH_TYPE 1480 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#undef CONFIG_CMD_PCI -#undef CONFIG_PCI - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113042 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 16MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x3A -#define PHYS_SDRAM_1_SIZE 0x01000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x00 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux2/uImage\0" \ - "rootfile=actux2/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux2/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 38da33f3c1fabeb0350c1bd0ed28556802cc7c12 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:08:10 +0100 Subject: ARM: IXP: Remove actux3 board The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- board/actux3/Makefile | 8 -- board/actux3/actux3.c | 149 ---------------------------------- board/actux3/actux3_hw.h | 44 ---------- board/actux3/u-boot.lds | 99 ----------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/actux3.h | 205 ----------------------------------------------- 7 files changed, 1 insertion(+), 506 deletions(-) delete mode 100644 board/actux3/Makefile delete mode 100644 board/actux3/actux3.c delete mode 100644 board/actux3/actux3_hw.h delete mode 100644 board/actux3/u-boot.lds delete mode 100644 include/configs/actux3.h (limited to 'include') diff --git a/board/actux3/Makefile b/board/actux3/Makefile deleted file mode 100644 index f628f264495..00000000000 --- a/board/actux3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux3.o diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c deleted file mode 100644 index 09c803ccd4e..00000000000 --- a/board/actux3/actux3.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "actux3_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: IPAC-X */ - writel(0x94d10013, IXP425_EXP_CS1); - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: Release/Option register */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN); - - /* - * Setup GPIO's for Interrupt inputs - */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - - /* - * Setup GPIO's for 33MHz clock output - */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - /* we need a minimum PCI reset pulse width after enabling the clock */ - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - - ACTUX3_LED1_RT(1); - ACTUX3_LED1_GN(0); - ACTUX3_LED2_RT(0); - ACTUX3_LED2_GN(0); - ACTUX3_LED3_RT(0); - ACTUX3_LED3_GN(0); - ACTUX3_LED4_GN(0); - ACTUX3_LED5_RT(0); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-3 rev."); - putc(ACTUX3_BOARDREL + 'A' - 1); - - if (i > 0) { - puts (", serial# "); - puts (buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX3_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -void reset_phy(void) -{ - int i; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - /* all LED outputs = Link/Act */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); - - /* - * The Marvell 88E6060 switch comes up with all ports disabled. - * set all ethernet switch ports to forwarding state - */ - for (i = 1; i <= 5; i++) - miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); - -} diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h deleted file mode 100644 index f8acb4d0604..00000000000 --- a/board/actux3/actux3_hw.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX3_HW_H -#define _ACTUX3_HW_H - -/* 0 = LED off,1 = ON */ -#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) - -#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) -#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_DBGINT 0 -#define CONFIG_SYS_GPIO_ETHINT 1 -#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ -#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ -#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */ -#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */ -#define CONFIG_SYS_GPIO_DSR 6 /* Out */ -#define CONFIG_SYS_GPIO_DCD 7 /* Out */ -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds deleted file mode 100644 index 2de3ca60b58..00000000000 --- a/board/actux3/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux3/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/boards.cfg b/boards.cfg index d3ebb4f58b5..ab94887666e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,7 +377,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren -Active arm ixp - - - actux3 - Michael Schwingen Active arm ixp - - - actux4 - Michael Schwingen Active arm ixp - - - dvlhost - Michael Schwingen Active arm pxa - - - balloon3 - Marek Vasut diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0ac90a97bac..2e64278da0a 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +actux3 arm ixp - 2014-01-28 Michael Schwingen actux2 arm ixp - 2014-01-28 Michael Schwingen actux1 arm ixp - 2014-01-28 Michael Schwingen mx1ads arm arm920t - 2014-01-13 diff --git a/include/configs/actux3.h b/include/configs/actux3.h deleted file mode 100644 index 763910745ce..00000000000 --- a/include/configs/actux3.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX3 1 - -#define CONFIG_MACH_TYPE 1481 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113442 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 16MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x3A -#define PHYS_SDRAM_1_SIZE 0x01000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x10 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux3/uImage\0" \ - "rootfile=actux3/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux3/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 6ff7aafa4b1f3a3f3808c9a9d9257f13e880689b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:09:01 +0100 Subject: ARM: IXP: Remove actux4 board The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- board/actux4/Makefile | 8 -- board/actux4/actux4.c | 129 ------------------------------ board/actux4/actux4_hw.h | 33 -------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/actux4.h | 204 ----------------------------------------------- 6 files changed, 1 insertion(+), 375 deletions(-) delete mode 100644 board/actux4/Makefile delete mode 100644 board/actux4/actux4.c delete mode 100644 board/actux4/actux4_hw.h delete mode 100644 include/configs/actux4.h (limited to 'include') diff --git a/board/actux4/Makefile b/board/actux4/Makefile deleted file mode 100644 index b949b608c66..00000000000 --- a/board/actux4/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux4.o diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c deleted file mode 100644 index 81c545884eb..00000000000 --- a/board/actux4/actux4.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "actux4_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - writel(0xbd113c42, IXP425_EXP_CS1); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* led not populated on board*/ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3); - - /* middle LED */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2); - - /* right LED */ - /* weak pulldown = LED weak on */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1); - - /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); - - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); - - /* Setup GPIO's for 33MHz clock output */ - writel(0x011001FF, IXP425_GPIO_GPCLKR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - - udelay(10000); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - udelay(10000); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - udelay(10000); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - return 0; -} - -/* Check Board Identity */ -int checkboard(void) -{ - puts("Board: AcTux-4\n"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus. - * Flash 1 is an Intel *16 flash using the CFI driver. - */ -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = 1; - info->chipwidth = 1; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h deleted file mode 100644 index b936376de9d..00000000000 --- a/board/actux4/actux4_hw.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-4 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX4_HW_H -#define _ACTUX4_HW_H - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_USBINTA 0 -#define CONFIG_SYS_GPIO_USBINTB 1 -#define CONFIG_SYS_GPIO_USBINTC 2 -#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */ -#define CONFIG_SYS_GPIO_I2C_SCL 4 -#define CONFIG_SYS_GPIO_I2C_SDA 5 -#define CONFIG_SYS_GPIO_PCI_INTB 6 -#define CONFIG_SYS_GPIO_BUTTON1 7 -#define CONFIG_SYS_GPIO_LED1 8 /* Out */ -#define CONFIG_SYS_GPIO_RTCINT 9 -#define CONFIG_SYS_GPIO_LED2 10 /* Out */ -#define CONFIG_SYS_GPIO_PCI_INTA 11 -#define CONFIG_SYS_GPIO_IORST 12 /* Out */ -#define CONFIG_SYS_GPIO_LED3 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/boards.cfg b/boards.cfg index ab94887666e..2d810eefe08 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,7 +377,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren -Active arm ixp - - - actux4 - Michael Schwingen Active arm ixp - - - dvlhost - Michael Schwingen Active arm pxa - - - balloon3 - Marek Vasut Active arm pxa - - - h2200 - Lukasz Dalek diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2e64278da0a..2ec2ad4bdb0 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +actux4 arm ixp - 2014-01-28 Michael Schwingen actux3 arm ixp - 2014-01-28 Michael Schwingen actux2 arm ixp - 2014-01-28 Michael Schwingen actux1 arm ixp - 2014-01-28 Michael Schwingen diff --git a/include/configs/actux4.h b/include/configs/actux4.h deleted file mode 100644 index 12bd98a7e18..00000000000 --- a/include/configs/actux4.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-4 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX4 1 - -#define CONFIG_MACH_TYPE 1532 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66000000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113003 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 32MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x02000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max # of sectors per chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 70 -#define PHYS_FLASH_1 0x50000000 -#define PHYS_FLASH_2 0x51000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (252 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 258048 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* board provides its own flash_init code */ -#define CONFIG_FLASH_CFI_LEGACY 1 -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* SST 39VF020 etc. support */ -#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1 - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x1C -/* MII PHY management */ -#define CONFIG_MII 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* environment organization: one complete 4k flash sector */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=51000000\0" \ - "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ - "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ - "kerneladdr=51020000\0" \ - "kernelfile=actux4/uImage\0" \ - "rootfile=actux4/rootfs\0" \ - "rootaddr=51160000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux4/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 5003efff;" \ - " erase 50000000 +${filesize}\0" \ - "writeboot=cp.b 10000 50000000 ${filesize}\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From e317de6b083adee81187fe1bba8b2fdf0ac983e7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:10:46 +0100 Subject: ARM: IXP: Remove dvl_host board The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- board/dvlhost/Makefile | 8 -- board/dvlhost/dvlhost.c | 112 ----------------------- board/dvlhost/dvlhost_hw.h | 31 ------- board/dvlhost/u-boot.lds | 99 -------------------- board/dvlhost/watchdog.c | 27 ------ boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/dvlhost.h | 222 --------------------------------------------- 8 files changed, 1 insertion(+), 500 deletions(-) delete mode 100644 board/dvlhost/Makefile delete mode 100644 board/dvlhost/dvlhost.c delete mode 100644 board/dvlhost/dvlhost_hw.h delete mode 100644 board/dvlhost/u-boot.lds delete mode 100644 board/dvlhost/watchdog.c delete mode 100644 include/configs/dvlhost.h (limited to 'include') diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile deleted file mode 100644 index 8b489362cea..00000000000 --- a/board/dvlhost/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dvlhost.o watchdog.o diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c deleted file mode 100644 index 087070f40d1..00000000000 --- a/board/dvlhost/dvlhost.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "dvlhost_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: LED Latch */ - writel(0xBFFF0002, IXP425_EXP_CS1); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* Setup GPIOs used as output */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST); - - /* - * LED latch enable and watchdog enable are tied to the same GPIO, - * so we need to trigger the watchdog if we want to enable the LEDs. - */ -#ifdef CONFIG_HW_WATCHDOG - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN); -#else - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN); -#endif - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST); - - /* Setup GPIOs for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB); - - /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x01FF01FF, IXP425_GPIO_GPCLKR); - - /* turn off all LEDs */ - writew(0x0000, DVLHOST_LED_LATCH); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST); - - return 0; -} - -/* Check Board Identity */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: dLAN 200AV (dvlhost)"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write("NPE1", 29, 31, 0x175C); -} diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h deleted file mode 100644 index 545099e9ea6..00000000000 --- a/board/dvlhost/dvlhost_hw.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the - * dLAN200 AV Wireless G ("dvlhost") board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DVLHOST_HW_H -#define _DVLHOST_HW_H - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_WDGTRIGGER 0 /* Out */ -#define CONFIG_SYS_GPIO_BTN_WLAN 1 -#define CONFIG_SYS_GPIO_BTN_PAIRING 6 -#define CONFIG_SYS_GPIO_DLAN_PAIRING 7 /* Out */ -#define CONFIG_SYS_GPIO_BTN_RESET 9 -#define CONFIG_SYS_GPIO_IRQB 10 -#define CONFIG_SYS_GPIO_IRQA 11 -#define CONFIG_SYS_GPIO_WDG_LED_EN 12 /* Out */ -#define CONFIG_SYS_GPIO_PCIRST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#define DVLHOST_LED_LATCH IXP425_EXP_BUS_CS1_BASE_PHYS - -#endif diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds deleted file mode 100644 index ebcaf447b83..00000000000 --- a/board/dvlhost/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/dvlhost/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/serial/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN (4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN (4); - .data : { - *(.data*) - } - . = ALIGN (4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c deleted file mode 100644 index 02ec35eb1a9..00000000000 --- a/board/dvlhost/watchdog.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "dvlhost_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_HW_WATCHDOG -#include -#include - -void hw_watchdog_reset(void) -{ - unsigned int x; - x = readl(IXP425_GPIO_GPOUTR); - x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER)); - writel(x, IXP425_GPIO_GPOUTR); -} - -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/boards.cfg b/boards.cfg index 2d810eefe08..de11dfe2938 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,7 +377,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren -Active arm ixp - - - dvlhost - Michael Schwingen Active arm pxa - - - balloon3 - Marek Vasut Active arm pxa - - - h2200 - Lukasz Dalek Active arm pxa - - - palmld - Marek Vasut diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2ec2ad4bdb0..6b41445faa0 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +dvl_host arm ixp - 2014-01-28 Michael Schwingen actux4 arm ixp - 2014-01-28 Michael Schwingen actux3 arm ixp - 2014-01-28 Michael Schwingen actux2 arm ixp - 2014-01-28 Michael Schwingen diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h deleted file mode 100644 index 1af7f169893..00000000000 --- a/include/configs/dvlhost.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the - * dLAN200 AV Wireless G ("dvlhost") board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_DVLHOST 1 - -#define CONFIG_MACH_TYPE 1343 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x01D80000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113442 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 32MB SDRAM: 2* 8Mx16, CL3 */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800 -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE - -/* FLASH organization: one Spansion S29AL032D-04 Flash */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */ -#define CONFIG_PHY_ADDR 0x18 -/* NPE1 PHY: MII IP175 switch, port 5 is host port */ -#define CONFIG_PHY1_ADDR 0x05 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed powerline modem without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE1_FIXEDLINK 1 -#define CONFIG_MII_NPE1_SPEED 100 -#define CONFIG_MII_NPE1_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "ethprime=NPE1\0" \ - "ethrotate=no\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=dvlhost/uImage\0" \ - "rootfile=dvlhost/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} dvlhost/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From f016f8ca3d503af004a649de1c704d5ddf3def22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Feb 2014 02:43:45 +0100 Subject: usb: mv_udc: Rename to ci_udc The mv_udc is not marvell-specific anymore. The mv_udc is used to drive generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc instead. Signed-off-by: Marek Vasut Cc: Eric Nelson Cc: Stefano Babic --- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 2 +- drivers/usb/gadget/ci_udc.c | 737 +++++++++++++++++++++++++++++++++ drivers/usb/gadget/ci_udc.h | 115 +++++ drivers/usb/gadget/gadget_chips.h | 8 +- drivers/usb/gadget/mv_udc.c | 737 --------------------------------- drivers/usb/gadget/mv_udc.h | 115 ----- include/configs/nitrogen6x.h | 2 +- include/configs/sansa_fuze_plus.h | 2 +- include/configs/xfi3.h | 2 +- include/usb/ci_udc.h | 14 + include/usb/mv_udc.h | 14 - 13 files changed, 877 insertions(+), 877 deletions(-) create mode 100644 drivers/usb/gadget/ci_udc.c create mode 100644 drivers/usb/gadget/ci_udc.h delete mode 100644 drivers/usb/gadget/mv_udc.c delete mode 100644 drivers/usb/gadget/mv_udc.h create mode 100644 include/usb/ci_udc.h delete mode 100644 include/usb/mv_udc.h (limited to 'include') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 3f4cfa1a29a..d9c05b07bfa 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -389,7 +389,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_MV_UDC +#ifdef CONFIG_CI_UDC /* For otg ethernet*/ usb_eth_initialize(bis); #endif diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 819dec663f4..21a3ef4d97e 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -20,8 +20,8 @@ #include #elif defined(CONFIG_DW_UDC) #include -#elif defined(CONFIG_MV_UDC) -#include +#elif defined(CONFIG_CI_UDC) +#include #endif #include diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index f13b172a667..804a2bd412d 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -21,7 +21,7 @@ endif ifdef CONFIG_USB_ETHER obj-y += ether.o obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o -obj-$(CONFIG_MV_UDC) += mv_udc.o +obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o else # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c new file mode 100644 index 00000000000..14b1e9b8bf1 --- /dev/null +++ b/drivers/usb/gadget/ci_udc.c @@ -0,0 +1,737 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../host/ehci.h" +#include "ci_udc.h" + +/* + * Check if the system has too long cachelines. If the cachelines are + * longer then 128b, the driver will not be able flush/invalidate data + * cache over separate QH entries. We use 128b because one QH entry is + * 64b long and there are always two QH list entries for each endpoint. + */ +#if ARCH_DMA_MINALIGN > 128 +#error This driver can not work on systems with caches longer than 128b +#endif + +#ifndef DEBUG +#define DBG(x...) do {} while (0) +#else +#define DBG(x...) printf(x) +static const char *reqname(unsigned r) +{ + switch (r) { + case USB_REQ_GET_STATUS: return "GET_STATUS"; + case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; + case USB_REQ_SET_FEATURE: return "SET_FEATURE"; + case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; + case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; + case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; + case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; + case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; + case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; + case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; + default: return "*UNKNOWN*"; + } +} +#endif + +static struct usb_endpoint_descriptor ep0_out_desc = { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; + +static struct usb_endpoint_descriptor ep0_in_desc = { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; + +static int ci_pullup(struct usb_gadget *gadget, int is_on); +static int ci_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); +static int ci_ep_disable(struct usb_ep *ep); +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags); +static struct usb_request * +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); + +static struct usb_gadget_ops ci_udc_ops = { + .pullup = ci_pullup, +}; + +static struct usb_ep_ops ci_ep_ops = { + .enable = ci_ep_enable, + .disable = ci_ep_disable, + .queue = ci_ep_queue, + .alloc_request = ci_ep_alloc_request, + .free_request = ci_ep_free_request, +}; + +/* Init values for USB endpoints. */ +static const struct usb_ep ci_ep_init[2] = { + [0] = { /* EP 0 */ + .maxpacket = 64, + .name = "ep0", + .ops = &ci_ep_ops, + }, + [1] = { /* EP 1..n */ + .maxpacket = 512, + .name = "ep-", + .ops = &ci_ep_ops, + }, +}; + +static struct ci_drv controller = { + .gadget = { + .name = "ci_udc", + .ops = &ci_udc_ops, + .is_dualspeed = 1, + }, +}; + +/** + * ci_get_qh() - return queue head for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) +{ + return &controller.epts[(ep_num * 2) + dir_in]; +} + +/** + * ci_get_qtd() - return queue item for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) +{ + return controller.items[(ep_num * 2) + dir_in]; +} + +/** + * ci_flush_qh - flush cache over queue head + * @ep_num: Endpoint number + * + * This function flushes cache over QH for particular endpoint. + */ +static void ci_flush_qh(int ep_num) +{ + struct ept_queue_head *head = ci_get_qh(ep_num, 0); + const uint32_t start = (uint32_t)head; + const uint32_t end = start + 2 * sizeof(*head); + + flush_dcache_range(start, end); +} + +/** + * ci_invalidate_qh - invalidate cache over queue head + * @ep_num: Endpoint number + * + * This function invalidates cache over QH for particular endpoint. + */ +static void ci_invalidate_qh(int ep_num) +{ + struct ept_queue_head *head = ci_get_qh(ep_num, 0); + uint32_t start = (uint32_t)head; + uint32_t end = start + 2 * sizeof(*head); + + invalidate_dcache_range(start, end); +} + +/** + * ci_flush_qtd - flush cache over queue item + * @ep_num: Endpoint number + * + * This function flushes cache over qTD pair for particular endpoint. + */ +static void ci_flush_qtd(int ep_num) +{ + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end_raw = start + 2 * sizeof(*item); + const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +/** + * ci_invalidate_qtd - invalidate cache over queue item + * @ep_num: Endpoint number + * + * This function invalidates cache over qTD pair for particular endpoint. + */ +static void ci_invalidate_qtd(int ep_num) +{ + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end_raw = start + 2 * sizeof(*item); + const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static struct usb_request * +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + return &ci_ep->req; +} + +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req) +{ + return; +} + +static void ep_enable(int num, int in, int maxpacket) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n; + + n = readl(&udc->epctrl[num]); + if (in) + n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); + else + n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); + + if (num != 0) { + struct ept_queue_head *head = ci_get_qh(num, in); + + head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; + ci_flush_qh(num); + } + writel(n, &udc->epctrl[num]); +} + +static int ci_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + int num, in; + num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (desc->bEndpointAddress & USB_DIR_IN) != 0; + ci_ep->desc = desc; + + if (num) { + int max = get_unaligned_le16(&desc->wMaxPacketSize); + + if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) + max = 64; + if (ep->maxpacket != max) { + DBG("%s: from %d to %d\n", __func__, + ep->maxpacket, max); + ep->maxpacket = max; + } + } + ep_enable(num, in, ep->maxpacket); + DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); + return 0; +} + +static int ci_ep_disable(struct usb_ep *ep) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + + ci_ep->desc = NULL; + return 0; +} + +static int ci_bounce(struct ci_ep *ep, int in) +{ + uint32_t addr = (uint32_t)ep->req.buf; + uint32_t ba; + + /* Input buffer address is not aligned. */ + if (addr & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* Input buffer length is not aligned. */ + if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* The buffer is well aligned, only flush cache. */ + ep->b_len = ep->req.length; + ep->b_buf = ep->req.buf; + goto flush; + +align: + /* Use internal buffer for small payloads. */ + if (ep->req.length <= 64) { + ep->b_len = 64; + ep->b_buf = ep->b_fast; + } else { + ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); + ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); + if (!ep->b_buf) + return -ENOMEM; + } + if (in) + memcpy(ep->b_buf, ep->req.buf, ep->req.length); + +flush: + ba = (uint32_t)ep->b_buf; + flush_dcache_range(ba, ba + ep->b_len); + + return 0; +} + +static void ci_debounce(struct ci_ep *ep, int in) +{ + uint32_t addr = (uint32_t)ep->req.buf; + uint32_t ba = (uint32_t)ep->b_buf; + + if (in) { + if (addr == ba) + return; /* not a bounce */ + goto free; + } + invalidate_dcache_range(ba, ba + ep->b_len); + + if (addr == ba) + return; /* not a bounce */ + + memcpy(ep->req.buf, ep->b_buf, ep->req.length); +free: + /* Large payloads use allocated buffer, free it. */ + if (ep->b_buf != ep->b_fast) + free(ep->b_buf); +} + +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + struct ept_queue_item *item; + struct ept_queue_head *head; + int bit, num, len, in, ret; + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + item = ci_get_qtd(num, in); + head = ci_get_qh(num, in); + len = req->length; + + ret = ci_bounce(ci_ep, in); + if (ret) + return ret; + + item->next = TERMINATE; + item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; + item->page0 = (uint32_t)ci_ep->b_buf; + item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; + ci_flush_qtd(num); + + head->next = (unsigned) item; + head->info = 0; + + DBG("ept%d %s queue len %x, buffer %p\n", + num, in ? "in" : "out", len, ci_ep->b_buf); + ci_flush_qh(num); + + if (in) + bit = EPT_TX(num); + else + bit = EPT_RX(num); + + writel(bit, &udc->epprime); + + return 0; +} + +static void handle_ep_complete(struct ci_ep *ep) +{ + struct ept_queue_item *item; + int num, in, len; + num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + if (num == 0) + ep->desc = &ep0_out_desc; + item = ci_get_qtd(num, in); + ci_invalidate_qtd(num); + + if (item->info & 0xff) + printf("EP%d/%s FAIL info=%x pg0=%x\n", + num, in ? "in" : "out", item->info, item->page0); + + len = (item->info >> 16) & 0x7fff; + ep->req.length -= len; + ci_debounce(ep, in); + + DBG("ept%d %s complete %x\n", + num, in ? "in" : "out", len); + ep->req.complete(&ep->ep, &ep->req); + if (num == 0) { + ep->req.length = 0; + usb_ep_queue(&ep->ep, &ep->req, 0); + ep->desc = &ep0_in_desc; + } +} + +#define SETUP(type, request) (((type) << 8) | (request)) + +static void handle_setup(void) +{ + struct usb_request *req = &controller.ep[0].req; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + struct ept_queue_head *head; + struct usb_ctrlrequest r; + int status = 0; + int num, in, _num, _in, i; + char *buf; + head = ci_get_qh(0, 0); /* EP0 OUT */ + + ci_invalidate_qh(0); + memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); + writel(EPT_RX(0), &udc->epstat); + DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), + r.bRequestType, r.bRequest, r.wIndex, r.wValue); + + switch (SETUP(r.bRequestType, r.bRequest)) { + case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): + _num = r.wIndex & 15; + _in = !!(r.wIndex & 0x80); + + if ((r.wValue == 0) && (r.wLength == 0)) { + req->length = 0; + for (i = 0; i < NUM_ENDPOINTS; i++) { + struct ci_ep *ep = &controller.ep[i]; + + if (!ep->desc) + continue; + num = ep->desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (ep->desc->bEndpointAddress + & USB_DIR_IN) != 0; + if ((num == _num) && (in == _in)) { + ep_enable(num, in, ep->ep.maxpacket); + usb_ep_queue(controller.gadget.ep0, + req, 0); + break; + } + } + } + return; + + case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): + /* + * write address delayed (will take effect + * after the next IN txn) + */ + writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + req->length = 0; + usb_ep_queue(controller.gadget.ep0, req, 0); + return; + + case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): + req->length = 2; + buf = (char *)req->buf; + buf[0] = 1 << USB_DEVICE_SELF_POWERED; + buf[1] = 0; + usb_ep_queue(controller.gadget.ep0, req, 0); + return; + } + /* pass request up to the gadget driver */ + if (controller.driver) + status = controller.driver->setup(&controller.gadget, &r); + else + status = -ENODEV; + + if (!status) + return; + DBG("STALL reqname %s type %x value %x, index %x\n", + reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); + writel((1<<16) | (1 << 0), &udc->epctrl[0]); +} + +static void stop_activity(void) +{ + int i, num, in; + struct ept_queue_head *head; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + writel(readl(&udc->epcomp), &udc->epcomp); + writel(readl(&udc->epstat), &udc->epstat); + writel(0xffffffff, &udc->epflush); + + /* error out any pending reqs */ + for (i = 0; i < NUM_ENDPOINTS; i++) { + if (i != 0) + writel(0, &udc->epctrl[i]); + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + head = ci_get_qh(num, in); + head->info = INFO_ACTIVE; + ci_flush_qh(num); + } + } +} + +void udc_irq(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n = readl(&udc->usbsts); + writel(n, &udc->usbsts); + int bit, i, num, in; + + n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); + if (n == 0) + return; + + if (n & STS_URI) { + DBG("-- reset --\n"); + stop_activity(); + } + if (n & STS_SLI) + DBG("-- suspend --\n"); + + if (n & STS_PCI) { + int max = 64; + int speed = USB_SPEED_FULL; + + bit = (readl(&udc->portsc) >> 26) & 3; + DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); + if (bit == 2) { + speed = USB_SPEED_HIGH; + max = 512; + } + controller.gadget.speed = speed; + for (i = 1; i < NUM_ENDPOINTS; i++) { + if (controller.ep[i].ep.maxpacket > max) + controller.ep[i].ep.maxpacket = max; + } + } + + if (n & STS_UEI) + printf("\n", readl(&udc->epcomp)); + + if ((n & STS_UI) || (n & STS_UEI)) { + n = readl(&udc->epstat); + if (n & EPT_RX(0)) + handle_setup(); + + n = readl(&udc->epcomp); + if (n != 0) + writel(n, &udc->epcomp); + + for (i = 0; i < NUM_ENDPOINTS && n; i++) { + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + bit = (in) ? EPT_TX(num) : EPT_RX(num); + if (n & bit) + handle_ep_complete(&controller.ep[i]); + } + } + } +} + +int usb_gadget_handle_interrupts(void) +{ + u32 value; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + value = readl(&udc->usbsts); + if (value) + udc_irq(); + + return value; +} + +static int ci_pullup(struct usb_gadget *gadget, int is_on) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + if (is_on) { + /* RESET */ + writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); + udelay(200); + + writel((unsigned)controller.epts, &udc->epinitaddr); + + /* select DEVICE mode */ + writel(USBMODE_DEVICE, &udc->usbmode); + + writel(0xffffffff, &udc->epflush); + + /* Turn on the USB connection by enabling the pullup resistor */ + writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); + } else { + stop_activity(); + writel(USBCMD_FS2, &udc->usbcmd); + udelay(800); + if (controller.driver) + controller.driver->disconnect(gadget); + } + + return 0; +} + +void udc_disconnect(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + /* disable pullup */ + stop_activity(); + writel(USBCMD_FS2, &udc->usbcmd); + udelay(800); + if (controller.driver) + controller.driver->disconnect(&controller.gadget); +} + +static int ci_udc_probe(void) +{ + struct ept_queue_head *head; + uint8_t *imem; + int i; + + const int num = 2 * NUM_ENDPOINTS; + + const int eplist_min_align = 4096; + const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); + const int eplist_raw_sz = num * sizeof(struct ept_queue_head); + const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); + + const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); + const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); + const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); + const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; + + /* The QH list must be aligned to 4096 bytes. */ + controller.epts = memalign(eplist_align, eplist_sz); + if (!controller.epts) + return -ENOMEM; + memset(controller.epts, 0, eplist_sz); + + /* + * Each qTD item must be 32-byte aligned, each qTD touple must be + * cacheline aligned. There are two qTD items for each endpoint and + * only one of them is used for the endpoint at time, so we can group + * them together. + */ + controller.items_mem = memalign(ilist_align, ilist_sz); + if (!controller.items_mem) { + free(controller.epts); + return -ENOMEM; + } + memset(controller.items_mem, 0, ilist_sz); + + for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { + /* + * Configure QH for each endpoint. The structure of the QH list + * is such that each two subsequent fields, N and N+1 where N is + * even, in the QH list represent QH for one endpoint. The Nth + * entry represents OUT configuration and the N+1th entry does + * represent IN configuration of the endpoint. + */ + head = controller.epts + i; + if (i < 2) + head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) + | CONFIG_ZLT | CONFIG_IOS; + else + head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) + | CONFIG_ZLT; + head->next = TERMINATE; + head->info = 0; + + imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); + if (i & 1) + imem += sizeof(struct ept_queue_item); + + controller.items[i] = (struct ept_queue_item *)imem; + + if (i & 1) { + ci_flush_qh(i - 1); + ci_flush_qtd(i - 1); + } + } + + INIT_LIST_HEAD(&controller.gadget.ep_list); + + /* Init EP 0 */ + memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); + controller.ep[0].desc = &ep0_in_desc; + controller.gadget.ep0 = &controller.ep[0].ep; + INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); + + /* Init EP 1..n */ + for (i = 1; i < NUM_ENDPOINTS; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[1], + sizeof(*ci_ep_init)); + list_add_tail(&controller.ep[i].ep.ep_list, + &controller.gadget.ep_list); + } + + return 0; +} + +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + struct ci_udc *udc; + int ret; + + if (!driver) + return -EINVAL; + if (!driver->bind || !driver->setup || !driver->disconnect) + return -EINVAL; + if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) + return -EINVAL; + + ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); + if (ret) + return ret; + + ret = ci_udc_probe(); + if (!ret) { + udc = (struct ci_udc *)controller.ctrl->hcor; + + /* select ULPI phy */ + writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + } + + ret = driver->bind(&controller.gadget); + if (ret) { + DBG("driver->bind() returned %d\n", ret); + return ret; + } + controller.driver = driver; + + return 0; +} + +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + return 0; +} diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h new file mode 100644 index 00000000000..42f6ef4ab30 --- /dev/null +++ b/drivers/usb/gadget/ci_udc.h @@ -0,0 +1,115 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __GADGET__CI_UDC_H__ +#define __GADGET__CI_UDC_H__ + +#define NUM_ENDPOINTS 6 + +struct ci_udc { +#define MICRO_8FRAME 0x8 +#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) +#define USBCMD_FS2 (1 << 15) +#define USBCMD_RST (1 << 1) +#define USBCMD_RUN (1) + u32 usbcmd; /* 0x140 */ +#define STS_SLI (1 << 8) +#define STS_URI (1 << 6) +#define STS_PCI (1 << 2) +#define STS_UEI (1 << 1) +#define STS_UI (1 << 0) + u32 usbsts; /* 0x144 */ + u32 pad1[3]; + u32 devaddr; /* 0x154 */ + u32 epinitaddr; /* 0x158 */ + u32 pad2[10]; +#define PTS_ENABLE 2 +#define PTS(x) (((x) & 0x3) << 30) +#define PFSC (1 << 24) + u32 portsc; /* 0x184 */ + u32 pad3[8]; +#define USBMODE_DEVICE 2 + u32 usbmode; /* 0x1a8 */ + u32 epstat; /* 0x1ac */ +#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) +#define EPT_RX(x) (1 << ((x) & 0xffff)) + u32 epprime; /* 0x1b0 */ + u32 epflush; /* 0x1b4 */ + u32 pad4; + u32 epcomp; /* 0x1bc */ +#define CTRL_TXE (1 << 23) +#define CTRL_TXR (1 << 22) +#define CTRL_RXE (1 << 7) +#define CTRL_RXR (1 << 6) +#define CTRL_TXT_BULK (2 << 18) +#define CTRL_RXT_BULK (2 << 2) + u32 epctrl[16]; /* 0x1c0 */ +}; + +struct ci_ep { + struct usb_ep ep; + struct list_head queue; + const struct usb_endpoint_descriptor *desc; + + struct usb_request req; + uint8_t *b_buf; + uint32_t b_len; + uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); +}; + +struct ci_drv { + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct ehci_ctrl *ctrl; + struct ept_queue_head *epts; + struct ept_queue_item *items[2 * NUM_ENDPOINTS]; + uint8_t *items_mem; + struct ci_ep ep[NUM_ENDPOINTS]; +}; + +struct ept_queue_head { + unsigned config; + unsigned current; /* read-only */ + + unsigned next; + unsigned info; + unsigned page0; + unsigned page1; + unsigned page2; + unsigned page3; + unsigned page4; + unsigned reserved_0; + + unsigned char setup_data[8]; + + unsigned reserved_1; + unsigned reserved_2; + unsigned reserved_3; + unsigned reserved_4; +}; + +#define CONFIG_MAX_PKT(n) ((n) << 16) +#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ +#define CONFIG_IOS (1 << 15) /* IRQ on setup */ + +struct ept_queue_item { + unsigned next; + unsigned info; + unsigned page0; + unsigned page1; + unsigned page2; + unsigned page3; + unsigned page4; + unsigned reserved; +}; + +#define TERMINATE 1 +#define INFO_BYTES(n) ((n) << 16) +#define INFO_IOC (1 << 15) +#define INFO_ACTIVE (1 << 7) +#define INFO_HALTED (1 << 6) +#define INFO_BUFFER_ERROR (1 << 5) +#define INFO_TX_ERROR (1 << 3) +#endif diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index aa54b8547e7..cc94771e32f 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -144,10 +144,10 @@ #define gadget_is_m66592(g) 0 #endif -#ifdef CONFIG_MV_UDC -#define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name)) +#ifdef CONFIG_CI_UDC +#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name)) #else -#define gadget_is_mv(g) 0 +#define gadget_is_ci(g) 0 #endif #ifdef CONFIG_USB_GADGET_FOTG210 @@ -219,7 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x19; else if (gadget_is_m66592(gadget)) return 0x20; - else if (gadget_is_mv(gadget)) + else if (gadget_is_ci(gadget)) return 0x21; else if (gadget_is_fotg210(gadget)) return 0x22; diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c deleted file mode 100644 index da41738653e..00000000000 --- a/drivers/usb/gadget/mv_udc.c +++ /dev/null @@ -1,737 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../host/ehci.h" -#include "mv_udc.h" - -/* - * Check if the system has too long cachelines. If the cachelines are - * longer then 128b, the driver will not be able flush/invalidate data - * cache over separate QH entries. We use 128b because one QH entry is - * 64b long and there are always two QH list entries for each endpoint. - */ -#if ARCH_DMA_MINALIGN > 128 -#error This driver can not work on systems with caches longer than 128b -#endif - -#ifndef DEBUG -#define DBG(x...) do {} while (0) -#else -#define DBG(x...) printf(x) -static const char *reqname(unsigned r) -{ - switch (r) { - case USB_REQ_GET_STATUS: return "GET_STATUS"; - case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; - case USB_REQ_SET_FEATURE: return "SET_FEATURE"; - case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; - case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; - case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; - case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; - case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; - case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; - case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; - default: return "*UNKNOWN*"; - } -} -#endif - -static struct usb_endpoint_descriptor ep0_out_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static struct usb_endpoint_descriptor ep0_in_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_DIR_IN, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static int mv_pullup(struct usb_gadget *gadget, int is_on); -static int mv_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc); -static int mv_ep_disable(struct usb_ep *ep); -static int mv_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags); -static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req); - -static struct usb_gadget_ops mv_udc_ops = { - .pullup = mv_pullup, -}; - -static struct usb_ep_ops mv_ep_ops = { - .enable = mv_ep_enable, - .disable = mv_ep_disable, - .queue = mv_ep_queue, - .alloc_request = mv_ep_alloc_request, - .free_request = mv_ep_free_request, -}; - -/* Init values for USB endpoints. */ -static const struct usb_ep mv_ep_init[2] = { - [0] = { /* EP 0 */ - .maxpacket = 64, - .name = "ep0", - .ops = &mv_ep_ops, - }, - [1] = { /* EP 1..n */ - .maxpacket = 512, - .name = "ep-", - .ops = &mv_ep_ops, - }, -}; - -static struct mv_drv controller = { - .gadget = { - .name = "mv_udc", - .ops = &mv_udc_ops, - .is_dualspeed = 1, - }, -}; - -/** - * mv_get_qh() - return queue head for endpoint - * @ep_num: Endpoint number - * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) - * - * This function returns the QH associated with particular endpoint - * and it's direction. - */ -static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in) -{ - return &controller.epts[(ep_num * 2) + dir_in]; -} - -/** - * mv_get_qtd() - return queue item for endpoint - * @ep_num: Endpoint number - * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) - * - * This function returns the QH associated with particular endpoint - * and it's direction. - */ -static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in) -{ - return controller.items[(ep_num * 2) + dir_in]; -} - -/** - * mv_flush_qh - flush cache over queue head - * @ep_num: Endpoint number - * - * This function flushes cache over QH for particular endpoint. - */ -static void mv_flush_qh(int ep_num) -{ - struct ept_queue_head *head = mv_get_qh(ep_num, 0); - const uint32_t start = (uint32_t)head; - const uint32_t end = start + 2 * sizeof(*head); - - flush_dcache_range(start, end); -} - -/** - * mv_invalidate_qh - invalidate cache over queue head - * @ep_num: Endpoint number - * - * This function invalidates cache over QH for particular endpoint. - */ -static void mv_invalidate_qh(int ep_num) -{ - struct ept_queue_head *head = mv_get_qh(ep_num, 0); - uint32_t start = (uint32_t)head; - uint32_t end = start + 2 * sizeof(*head); - - invalidate_dcache_range(start, end); -} - -/** - * mv_flush_qtd - flush cache over queue item - * @ep_num: Endpoint number - * - * This function flushes cache over qTD pair for particular endpoint. - */ -static void mv_flush_qtd(int ep_num) -{ - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); - const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); - - flush_dcache_range(start, end); -} - -/** - * mv_invalidate_qtd - invalidate cache over queue item - * @ep_num: Endpoint number - * - * This function invalidates cache over qTD pair for particular endpoint. - */ -static void mv_invalidate_qtd(int ep_num) -{ - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); - const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); - - invalidate_dcache_range(start, end); -} - -static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - return &mv_ep->req; -} - -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req) -{ - return; -} - -static void ep_enable(int num, int in, int maxpacket) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - unsigned n; - - n = readl(&udc->epctrl[num]); - if (in) - n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); - else - n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); - - if (num != 0) { - struct ept_queue_head *head = mv_get_qh(num, in); - - head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; - mv_flush_qh(num); - } - writel(n, &udc->epctrl[num]); -} - -static int mv_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - int num, in; - num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (desc->bEndpointAddress & USB_DIR_IN) != 0; - mv_ep->desc = desc; - - if (num) { - int max = get_unaligned_le16(&desc->wMaxPacketSize); - - if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) - max = 64; - if (ep->maxpacket != max) { - DBG("%s: from %d to %d\n", __func__, - ep->maxpacket, max); - ep->maxpacket = max; - } - } - ep_enable(num, in, ep->maxpacket); - DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); - return 0; -} - -static int mv_ep_disable(struct usb_ep *ep) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - - mv_ep->desc = NULL; - return 0; -} - -static int mv_bounce(struct mv_ep *ep, int in) -{ - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba; - - /* Input buffer address is not aligned. */ - if (addr & (ARCH_DMA_MINALIGN - 1)) - goto align; - - /* Input buffer length is not aligned. */ - if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) - goto align; - - /* The buffer is well aligned, only flush cache. */ - ep->b_len = ep->req.length; - ep->b_buf = ep->req.buf; - goto flush; - -align: - /* Use internal buffer for small payloads. */ - if (ep->req.length <= 64) { - ep->b_len = 64; - ep->b_buf = ep->b_fast; - } else { - ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); - ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); - if (!ep->b_buf) - return -ENOMEM; - } - if (in) - memcpy(ep->b_buf, ep->req.buf, ep->req.length); - -flush: - ba = (uint32_t)ep->b_buf; - flush_dcache_range(ba, ba + ep->b_len); - - return 0; -} - -static void mv_debounce(struct mv_ep *ep, int in) -{ - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba = (uint32_t)ep->b_buf; - - if (in) { - if (addr == ba) - return; /* not a bounce */ - goto free; - } - invalidate_dcache_range(ba, ba + ep->b_len); - - if (addr == ba) - return; /* not a bounce */ - - memcpy(ep->req.buf, ep->b_buf, ep->req.length); -free: - /* Large payloads use allocated buffer, free it. */ - if (ep->b_buf != ep->b_fast) - free(ep->b_buf); -} - -static int mv_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - struct ept_queue_item *item; - struct ept_queue_head *head; - int bit, num, len, in, ret; - num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - item = mv_get_qtd(num, in); - head = mv_get_qh(num, in); - len = req->length; - - ret = mv_bounce(mv_ep, in); - if (ret) - return ret; - - item->next = TERMINATE; - item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)mv_ep->b_buf; - item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000; - mv_flush_qtd(num); - - head->next = (unsigned) item; - head->info = 0; - - DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, mv_ep->b_buf); - mv_flush_qh(num); - - if (in) - bit = EPT_TX(num); - else - bit = EPT_RX(num); - - writel(bit, &udc->epprime); - - return 0; -} - -static void handle_ep_complete(struct mv_ep *ep) -{ - struct ept_queue_item *item; - int num, in, len; - num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - if (num == 0) - ep->desc = &ep0_out_desc; - item = mv_get_qtd(num, in); - mv_invalidate_qtd(num); - - if (item->info & 0xff) - printf("EP%d/%s FAIL info=%x pg0=%x\n", - num, in ? "in" : "out", item->info, item->page0); - - len = (item->info >> 16) & 0x7fff; - ep->req.length -= len; - mv_debounce(ep, in); - - DBG("ept%d %s complete %x\n", - num, in ? "in" : "out", len); - ep->req.complete(&ep->ep, &ep->req); - if (num == 0) { - ep->req.length = 0; - usb_ep_queue(&ep->ep, &ep->req, 0); - ep->desc = &ep0_in_desc; - } -} - -#define SETUP(type, request) (((type) << 8) | (request)) - -static void handle_setup(void) -{ - struct usb_request *req = &controller.ep[0].req; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - struct ept_queue_head *head; - struct usb_ctrlrequest r; - int status = 0; - int num, in, _num, _in, i; - char *buf; - head = mv_get_qh(0, 0); /* EP0 OUT */ - - mv_invalidate_qh(0); - memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); - writel(EPT_RX(0), &udc->epstat); - DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), - r.bRequestType, r.bRequest, r.wIndex, r.wValue); - - switch (SETUP(r.bRequestType, r.bRequest)) { - case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): - _num = r.wIndex & 15; - _in = !!(r.wIndex & 0x80); - - if ((r.wValue == 0) && (r.wLength == 0)) { - req->length = 0; - for (i = 0; i < NUM_ENDPOINTS; i++) { - struct mv_ep *ep = &controller.ep[i]; - - if (!ep->desc) - continue; - num = ep->desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (ep->desc->bEndpointAddress - & USB_DIR_IN) != 0; - if ((num == _num) && (in == _in)) { - ep_enable(num, in, ep->ep.maxpacket); - usb_ep_queue(controller.gadget.ep0, - req, 0); - break; - } - } - } - return; - - case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): - /* - * write address delayed (will take effect - * after the next IN txn) - */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); - req->length = 0; - usb_ep_queue(controller.gadget.ep0, req, 0); - return; - - case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): - req->length = 2; - buf = (char *)req->buf; - buf[0] = 1 << USB_DEVICE_SELF_POWERED; - buf[1] = 0; - usb_ep_queue(controller.gadget.ep0, req, 0); - return; - } - /* pass request up to the gadget driver */ - if (controller.driver) - status = controller.driver->setup(&controller.gadget, &r); - else - status = -ENODEV; - - if (!status) - return; - DBG("STALL reqname %s type %x value %x, index %x\n", - reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); - writel((1<<16) | (1 << 0), &udc->epctrl[0]); -} - -static void stop_activity(void) -{ - int i, num, in; - struct ept_queue_head *head; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - writel(readl(&udc->epcomp), &udc->epcomp); - writel(readl(&udc->epstat), &udc->epstat); - writel(0xffffffff, &udc->epflush); - - /* error out any pending reqs */ - for (i = 0; i < NUM_ENDPOINTS; i++) { - if (i != 0) - writel(0, &udc->epctrl[i]); - if (controller.ep[i].desc) { - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - head = mv_get_qh(num, in); - head->info = INFO_ACTIVE; - mv_flush_qh(num); - } - } -} - -void udc_irq(void) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - unsigned n = readl(&udc->usbsts); - writel(n, &udc->usbsts); - int bit, i, num, in; - - n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); - if (n == 0) - return; - - if (n & STS_URI) { - DBG("-- reset --\n"); - stop_activity(); - } - if (n & STS_SLI) - DBG("-- suspend --\n"); - - if (n & STS_PCI) { - int max = 64; - int speed = USB_SPEED_FULL; - - bit = (readl(&udc->portsc) >> 26) & 3; - DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); - if (bit == 2) { - speed = USB_SPEED_HIGH; - max = 512; - } - controller.gadget.speed = speed; - for (i = 1; i < NUM_ENDPOINTS; i++) { - if (controller.ep[i].ep.maxpacket > max) - controller.ep[i].ep.maxpacket = max; - } - } - - if (n & STS_UEI) - printf("\n", readl(&udc->epcomp)); - - if ((n & STS_UI) || (n & STS_UEI)) { - n = readl(&udc->epstat); - if (n & EPT_RX(0)) - handle_setup(); - - n = readl(&udc->epcomp); - if (n != 0) - writel(n, &udc->epcomp); - - for (i = 0; i < NUM_ENDPOINTS && n; i++) { - if (controller.ep[i].desc) { - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - bit = (in) ? EPT_TX(num) : EPT_RX(num); - if (n & bit) - handle_ep_complete(&controller.ep[i]); - } - } - } -} - -int usb_gadget_handle_interrupts(void) -{ - u32 value; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - - value = readl(&udc->usbsts); - if (value) - udc_irq(); - - return value; -} - -static int mv_pullup(struct usb_gadget *gadget, int is_on) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - if (is_on) { - /* RESET */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); - udelay(200); - - writel((unsigned)controller.epts, &udc->epinitaddr); - - /* select DEVICE mode */ - writel(USBMODE_DEVICE, &udc->usbmode); - - writel(0xffffffff, &udc->epflush); - - /* Turn on the USB connection by enabling the pullup resistor */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); - } else { - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(gadget); - } - - return 0; -} - -void udc_disconnect(void) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - /* disable pullup */ - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(&controller.gadget); -} - -static int mvudc_probe(void) -{ - struct ept_queue_head *head; - uint8_t *imem; - int i; - - const int num = 2 * NUM_ENDPOINTS; - - const int eplist_min_align = 4096; - const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); - const int eplist_raw_sz = num * sizeof(struct ept_queue_head); - const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); - - const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); - const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); - const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); - const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; - - /* The QH list must be aligned to 4096 bytes. */ - controller.epts = memalign(eplist_align, eplist_sz); - if (!controller.epts) - return -ENOMEM; - memset(controller.epts, 0, eplist_sz); - - /* - * Each qTD item must be 32-byte aligned, each qTD touple must be - * cacheline aligned. There are two qTD items for each endpoint and - * only one of them is used for the endpoint at time, so we can group - * them together. - */ - controller.items_mem = memalign(ilist_align, ilist_sz); - if (!controller.items_mem) { - free(controller.epts); - return -ENOMEM; - } - memset(controller.items_mem, 0, ilist_sz); - - for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { - /* - * Configure QH for each endpoint. The structure of the QH list - * is such that each two subsequent fields, N and N+1 where N is - * even, in the QH list represent QH for one endpoint. The Nth - * entry represents OUT configuration and the N+1th entry does - * represent IN configuration of the endpoint. - */ - head = controller.epts + i; - if (i < 2) - head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) - | CONFIG_ZLT | CONFIG_IOS; - else - head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) - | CONFIG_ZLT; - head->next = TERMINATE; - head->info = 0; - - imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); - if (i & 1) - imem += sizeof(struct ept_queue_item); - - controller.items[i] = (struct ept_queue_item *)imem; - - if (i & 1) { - mv_flush_qh(i - 1); - mv_flush_qtd(i - 1); - } - } - - INIT_LIST_HEAD(&controller.gadget.ep_list); - - /* Init EP 0 */ - memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init)); - controller.ep[0].desc = &ep0_in_desc; - controller.gadget.ep0 = &controller.ep[0].ep; - INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); - - /* Init EP 1..n */ - for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &mv_ep_init[1], - sizeof(*mv_ep_init)); - list_add_tail(&controller.ep[i].ep.ep_list, - &controller.gadget.ep_list); - } - - return 0; -} - -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -{ - struct mv_udc *udc; - int ret; - - if (!driver) - return -EINVAL; - if (!driver->bind || !driver->setup || !driver->disconnect) - return -EINVAL; - if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) - return -EINVAL; - - ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); - if (ret) - return ret; - - ret = mvudc_probe(); - if (!ret) { - udc = (struct mv_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); - } - - ret = driver->bind(&controller.gadget); - if (ret) { - DBG("driver->bind() returned %d\n", ret); - return ret; - } - controller.driver = driver; - - return 0; -} - -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - return 0; -} diff --git a/drivers/usb/gadget/mv_udc.h b/drivers/usb/gadget/mv_udc.h deleted file mode 100644 index c7d8b33984c..00000000000 --- a/drivers/usb/gadget/mv_udc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * - * Licensed under the GPL-2 or later. - */ -#ifndef __GADGET__MV_UDC_H__ -#define __GADGET__MV_UDC_H__ - -#define NUM_ENDPOINTS 6 - -struct mv_udc { -#define MICRO_8FRAME 0x8 -#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) -#define USBCMD_FS2 (1 << 15) -#define USBCMD_RST (1 << 1) -#define USBCMD_RUN (1) - u32 usbcmd; /* 0x140 */ -#define STS_SLI (1 << 8) -#define STS_URI (1 << 6) -#define STS_PCI (1 << 2) -#define STS_UEI (1 << 1) -#define STS_UI (1 << 0) - u32 usbsts; /* 0x144 */ - u32 pad1[3]; - u32 devaddr; /* 0x154 */ - u32 epinitaddr; /* 0x158 */ - u32 pad2[10]; -#define PTS_ENABLE 2 -#define PTS(x) (((x) & 0x3) << 30) -#define PFSC (1 << 24) - u32 portsc; /* 0x184 */ - u32 pad3[8]; -#define USBMODE_DEVICE 2 - u32 usbmode; /* 0x1a8 */ - u32 epstat; /* 0x1ac */ -#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) -#define EPT_RX(x) (1 << ((x) & 0xffff)) - u32 epprime; /* 0x1b0 */ - u32 epflush; /* 0x1b4 */ - u32 pad4; - u32 epcomp; /* 0x1bc */ -#define CTRL_TXE (1 << 23) -#define CTRL_TXR (1 << 22) -#define CTRL_RXE (1 << 7) -#define CTRL_RXR (1 << 6) -#define CTRL_TXT_BULK (2 << 18) -#define CTRL_RXT_BULK (2 << 2) - u32 epctrl[16]; /* 0x1c0 */ -}; - -struct mv_ep { - struct usb_ep ep; - struct list_head queue; - const struct usb_endpoint_descriptor *desc; - - struct usb_request req; - uint8_t *b_buf; - uint32_t b_len; - uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); -}; - -struct mv_drv { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - struct ehci_ctrl *ctrl; - struct ept_queue_head *epts; - struct ept_queue_item *items[2 * NUM_ENDPOINTS]; - uint8_t *items_mem; - struct mv_ep ep[NUM_ENDPOINTS]; -}; - -struct ept_queue_head { - unsigned config; - unsigned current; /* read-only */ - - unsigned next; - unsigned info; - unsigned page0; - unsigned page1; - unsigned page2; - unsigned page3; - unsigned page4; - unsigned reserved_0; - - unsigned char setup_data[8]; - - unsigned reserved_1; - unsigned reserved_2; - unsigned reserved_3; - unsigned reserved_4; -}; - -#define CONFIG_MAX_PKT(n) ((n) << 16) -#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ -#define CONFIG_IOS (1 << 15) /* IRQ on setup */ - -struct ept_queue_item { - unsigned next; - unsigned info; - unsigned page0; - unsigned page1; - unsigned page2; - unsigned page3; - unsigned page4; - unsigned reserved; -}; - -#define TERMINATE 1 -#define INFO_BYTES(n) ((n) << 16) -#define INFO_IOC (1 << 15) -#define INFO_ACTIVE (1 << 7) -#define INFO_HALTED (1 << 6) -#define INFO_BUFFER_ERROR (1 << 5) -#define INFO_TX_ERROR (1 << 3) -#endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f4ff5cd1b5c..e44ec88f71b 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO -#define CONFIG_MV_UDC +#define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index a85eb1c3fc2..8cce34af763 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -56,7 +56,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 022bc95927b..8e6b3653644 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -55,7 +55,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/usb/ci_udc.h b/include/usb/ci_udc.h new file mode 100644 index 00000000000..0dee50461e8 --- /dev/null +++ b/include/usb/ci_udc.h @@ -0,0 +1,14 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CI_UDC_H__ +#define __CI_UDC_H__ + +#define EP_MAX_PACKET_SIZE 0x200 +#define EP0_MAX_PACKET_SIZE 64 +#endif /* __CI_UDC_H__ */ diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h deleted file mode 100644 index f6c7b5e8987..00000000000 --- a/include/usb/mv_udc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __MV_UDC_H__ -#define __MV_UDC_H__ - -#define EP_MAX_PACKET_SIZE 0x200 -#define EP0_MAX_PACKET_SIZE 64 -#endif /* __MV_UDC_H__ */ -- cgit v1.3.1 From 31993d6a3585d478d792fc70240129b0ca03f55f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Sep 2013 16:39:03 +0200 Subject: fpga: zynqpl: Add support for zc7015 device Just extend tables with this new device. Signed-off-by: Michal Simek --- board/xilinx/zynq/board.c | 4 ++++ include/zynqpl.h | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index a5b9bdef46a..5a47149902d 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -23,6 +23,7 @@ Xilinx_desc fpga; /* It can be done differently */ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); @@ -40,6 +41,9 @@ int board_init(void) case XILINX_ZYNQ_7010: fpga = fpga010; break; + case XILINX_ZYNQ_7015: + fpga = fpga015; + break; case XILINX_ZYNQ_7020: fpga = fpga020; break; diff --git a/include/zynqpl.h b/include/zynqpl.h index 6107cbf3a5a..c81446e9860 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -17,6 +17,7 @@ extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); extern int zynq_info(Xilinx_desc *desc); #define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc #define XILINX_ZYNQ_7045 0x11 @@ -24,6 +25,7 @@ extern int zynq_info(Xilinx_desc *desc); /* Device Image Sizes */ #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 #define XILINX_XC7Z045_SIZE 106571232/8 @@ -33,6 +35,9 @@ extern int zynq_info(Xilinx_desc *desc); #define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } +#define XILINX_XC7Z015_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" } + #define XILINX_XC7Z020_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } -- cgit v1.3.1 From dbf3de2dd26cae37d16b00b348828c883b658cc5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 6 Feb 2014 14:26:05 -0500 Subject: include/usb/s3c_udc.h: Add With e0059ea switching to using SZ_1K, we need to #include here for everyone to build still. Signed-off-by: Tom Rini --- include/usb/s3c_udc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 6dead2fb46d..ce3dd2c6bbe 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -10,6 +10,7 @@ #define __S3C_USB_GADGET #include +#include #include #include #include -- cgit v1.3.1 From eee2fab0bddb2c460a96a943d7ed6b0f3718f0fd Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 22 Jan 2014 15:54:32 +0100 Subject: board:samsung:common: set envs with board unified information This patch sets envs that describe board information. The following envs are set: soc_id, soc_rev, board_rev. Based on this information, if CONFIG_OF_LIBFDT is enabled, the 'fdtfile' env is set as: fdtfile=${soc_family}${soc_id}-${board}.dtb The generated envs are intenionally not saved to persistent storage. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 24 ++++++++++++++++++++++++ include/samsung/misc.h | 12 ++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 643f957a543..eb157394adb 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -21,6 +21,30 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +void set_board_info(void) +{ + char info[64]; + + snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f, + (s5p_cpu_rev & 0xf0) >> 0x04); + setenv("soc_rev", info); + + snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id); + setenv("soc_id", info); + +#ifdef CONFIG_REVISION_TAG + snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev()); + setenv("board_rev", info); +#endif +#ifdef CONFIG_OF_LIBFDT + snprintf(info, ARRAY_SIZE(info), "%s%x-%s.dtb", + CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD); + setenv("fdtfile", info); +#endif +} +#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ + #ifdef CONFIG_LCD_MENU static int power_key_pressed(u32 reg) { diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 1a6d47f4ca6..ede6c1583a9 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -1,6 +1,14 @@ #ifndef __SAMSUNG_MISC_COMMON_H__ #define __SAMSUNG_MISC_COMMON_H__ +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +void set_board_info(void); +#endif + #ifdef CONFIG_LCD_MENU enum { BOOT_MODE_INFO, @@ -10,10 +18,6 @@ enum { BOOT_MODE_EXIT, }; -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void); -#endif - void keys_init(void); void check_boot_mode(void); #endif /* CONFIG_LCD_MENU */ -- cgit v1.3.1 From 2ac9a35bcd441b06601b8fcfc1d39b6b3d9f0aef Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 22 Jan 2014 15:54:33 +0100 Subject: board:samsung:goni: add env variables describing platform This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Mateusz Zalega Signed-off-by: Minkyu Kang --- board/samsung/goni/goni.c | 17 +++++++++++++++++ include/configs/s5p_goni.h | 6 ++++++ 2 files changed, 23 insertions(+) (limited to 'include') diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 366f648d320..61b9ece0387 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -13,10 +13,17 @@ #include #include #include +#include + DECLARE_GLOBAL_DATA_PTR; static struct s5pc110_gpio *s5pc110_gpio; +u32 get_board_rev(void) +{ + return 0; +} + int board_init(void) { /* Set Initial global variables */ @@ -173,3 +180,13 @@ struct s3c_plat_otg_data s5pc110_otg_data = { .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL, }; #endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif + return 0; +} +#endif diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 4cdf937a60c..991c43e1cc2 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -34,6 +34,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING @@ -113,8 +114,13 @@ #define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc" +#define CONFIG_MISC_COMMON +#define CONFIG_MISC_INIT_R + #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_UPDATEB \ "updatek=" \ -- cgit v1.3.1 From 815a6072f06557ce776744ef2c3b57189a2abd3e Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 22 Jan 2014 15:54:34 +0100 Subject: board:samsung:universal: add env variables describing platform This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Przemyslaw Marczak Acked-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/universal_c210/universal.c | 3 +++ include/configs/s5pc210_universal.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index ced4caa86fd..96da7e0861e 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -516,6 +516,9 @@ int board_init(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif #ifdef CONFIG_LCD_MENU keys_init(); check_boot_mode(); diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index bfb044b087b..67921e900be 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -124,6 +124,9 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ -- cgit v1.3.1 From 943eacde686f50fc82d18af88825ff74d8d89967 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 22 Jan 2014 15:54:35 +0100 Subject: board:samsung:trats: add env variables describing platform This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Lukasz Majewski Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 3 +++ include/configs/trats.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index c6664e7a123..b72550538a9 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -791,6 +791,9 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif #ifdef CONFIG_LCD_MENU keys_init(); check_boot_mode(); diff --git a/include/configs/trats.h b/include/configs/trats.h index 41de414485a..6e14a59a074 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -154,6 +154,9 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ -- cgit v1.3.1 From 8c57fb7d9aa1c9d46d797a0926d755e95a5cb64e Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 22 Jan 2014 15:54:36 +0100 Subject: board:samsung:trats2: add env variables describing platform This patch adds variables describing platform (soc, board, vendor) to default environment. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- board/samsung/trats2/trats2.c | 3 +++ include/configs/trats2.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 62e7fd22242..c17c24d60a4 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -616,6 +616,9 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif #ifdef CONFIG_LCD_MENU keys_init(); check_boot_mode(); diff --git a/include/configs/trats2.h b/include/configs/trats2.h index b72f4920d90..087471752c6 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -152,6 +152,9 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Tizen - partitions definitions */ #define PARTS_CSA "csa" #define PARTS_BOOT "boot" -- cgit v1.3.1 From 425e26de292b9dc53a73ee5493d4eaf58c8d1c14 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 22 Jan 2014 15:54:37 +0100 Subject: board:samsung:trats/trats2: enable boot with appended and separated DTB This patch modifies envs to enable dual kernel boot - with separated DTB if the DTB file is loaded successfully; - with DTB apppended to uImage if DTB file is not found; This is neccesssary for backward compatibilty. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Lukasz Majewski Signed-off-by: Minkyu Kang --- include/configs/trats.h | 9 ++++++--- include/configs/trats2.h | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/trats.h b/include/configs/trats.h index 6e14a59a074..718107ac9f0 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -159,7 +159,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatemmc=" \ "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ "mmc boot 0 1 1 0\0" \ @@ -182,7 +186,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ @@ -221,7 +225,6 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4210-trats.dtb\0" /* Miscellaneous configurable options */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 087471752c6..e30c428a442 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -186,7 +186,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatemmc=" \ "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ "mmc boot 0 1 1 0\0" \ @@ -200,7 +204,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "verify=n\0" \ @@ -241,7 +245,6 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4412-trats2.dtb\0" /* * Miscellaneous configurable options -- cgit v1.3.1 From bc5d5428805c804cab67a0cc000bbf64e26acf71 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 4 Feb 2014 12:56:16 +0400 Subject: arc: bdinfo, image and arc-specific init functions declarations support Signed-off-by: Alexey Brodkin Cc: Vineet Gupta Cc: Francois Bedard Cc: Wolfgang Denk Cc: Heiko Schocher --- common/cmd_bdinfo.c | 18 ++++++++++++++++++ common/image.c | 1 + include/common.h | 3 +++ include/image.h | 1 + 4 files changed, 23 insertions(+) (limited to 'include') diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 713de1464c3..15119a775e5 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -517,6 +517,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_ARC700) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("mem start", bd->bi_memstart); + print_lnum("mem size", bd->bi_memsize); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf("ip_addr = %s\n", getenv("ipaddr")); +#endif + printf("baudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else #error "a case for this architecture does not exist!" #endif diff --git a/common/image.c b/common/image.c index ae95c3f18aa..9c6bec5b769 100644 --- a/common/image.c +++ b/common/image.c @@ -82,6 +82,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",}, { IH_ARCH_SANDBOX, "sandbox", "Sandbox", }, { IH_ARCH_ARM64, "arm64", "AArch64", }, + { IH_ARCH_ARC, "arc", "ARC", }, { -1, "", "", }, }; diff --git a/include/common.h b/include/common.h index d5ebb253906..221b7768c5b 100644 --- a/include/common.h +++ b/include/common.h @@ -408,6 +408,9 @@ static inline int setenv_addr(const char *varname, const void *addr) #ifdef CONFIG_MIPS # include #endif /* CONFIG_MIPS */ +#ifdef CONFIG_ARC +# include +#endif /* CONFIG_ARC */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); diff --git a/include/image.h b/include/image.h index 7de2bb2f81e..3ba8c2ea304 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,7 @@ struct lmb; #define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ #define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ #define IH_ARCH_ARM64 22 /* ARM64 */ +#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ /* * Image Types -- cgit v1.3.1 From 66712b8b460e9ba01374ca0df8aa8bcb3137e4bb Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 4 Feb 2014 12:56:18 +0400 Subject: arc: add Arcangel4 board support Arcangel4 is a FPGA-based development board that is used for prototyping and verificationof of both ARC hardware (CPUs) and software running upon CPU. This board avaialble in 2 flavours: * Little-endian (arcangel4) * Big-endian (arcangel4-be) Signed-off-by: Alexey Brodkin Cc: Vineet Gupta Cc: Francois Bedard Cc: Wolfgang Denk Cc: Heiko Schocher --- board/synopsys/arcangel4/Makefile | 11 +++++ boards.cfg | 2 + include/configs/arcangel4-be.h | 92 +++++++++++++++++++++++++++++++++++++++ include/configs/arcangel4.h | 91 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 196 insertions(+) create mode 100644 board/synopsys/arcangel4/Makefile create mode 100644 include/configs/arcangel4-be.h create mode 100644 include/configs/arcangel4.h (limited to 'include') diff --git a/board/synopsys/arcangel4/Makefile b/board/synopsys/arcangel4/Makefile new file mode 100644 index 00000000000..575e58fd960 --- /dev/null +++ b/board/synopsys/arcangel4/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# This board is mostly used for debugging U-Boot in simulation (ISS). +# The only peripheral which is used on this board is a serial port which +# requires no initialization except those in "include/configs/arcangel4.h". +# And now there's no specific initializations for this board. +# So this Makefile is only required for satisfaction of U-Boot build system. diff --git a/boards.cfg b/boards.cfg index 706ec96585a..de39bfaa0dc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1230,6 +1230,8 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +Active arc arc700 - synopsys - arcangel4 - Alexey Brodkin +Active arc arc700 - synopsys arcangel4 arcangel4-be - Alexey Brodkin Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski Orphan arm pxa - - - lubbock - (dead address) Kyle Harris diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h new file mode 100644 index 00000000000..88d27db08b6 --- /dev/null +++ b/include/configs/arcangel4-be.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_SYS_BIG_ENDIAN +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h new file mode 100644 index 00000000000..4579eb97c2c --- /dev/null +++ b/include/configs/arcangel4.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ -- cgit v1.3.1 From a7069ddfa9b369e8bed449806a4422ad751246ab Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 4 Feb 2014 12:56:19 +0400 Subject: arc: add AXS101 board support AXS101 is a new generation of devlopment boards from Synopsys that houses ASIC with ARC700 and lots of DesignWare peripherals: * DW APB UART * DW Mobile Storage (MMC/SD) * DW I2C * DW GMAC Signed-off-by: Alexey Brodkin Cc: Vineet Gupta Cc: Francois Bedard Cc: Wolfgang Denk Cc: Heiko Schocher --- board/synopsys/axs101/Makefile | 8 ++ board/synopsys/axs101/axs101.c | 44 ++++++++ board/synopsys/axs101/nand.c | 226 +++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/axs101.h | 181 +++++++++++++++++++++++++++++++++ 5 files changed, 460 insertions(+) create mode 100644 board/synopsys/axs101/Makefile create mode 100644 board/synopsys/axs101/axs101.c create mode 100644 board/synopsys/axs101/nand.c create mode 100644 include/configs/axs101.h (limited to 'include') diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile new file mode 100644 index 00000000000..f0965f78416 --- /dev/null +++ b/board/synopsys/axs101/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += axs101.o +obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c new file mode 100644 index 00000000000..4dbeaea1615 --- /dev/null +++ b/board/synopsys/axs101/axs101.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_mmc_init(bd_t *bis) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + memset(host, 0, sizeof(struct dwmci_host)); + host->name = "Synopsys Mobile storage"; + host->ioaddr = (void *)ARC_DWMMC_BASE; + host->buswidth = 4; + host->dev_index = 0; + host->bus_hz = 25000000; + + add_dwmci(host, 52000000, 400000); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(0, ARC_DWGMAC_BASE, 0, + PHY_INTERFACE_MODE_RGMII) >= 0) + return 1; + + return 0; +} diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c new file mode 100644 index 00000000000..8672803871d --- /dev/null +++ b/board/synopsys/axs101/nand.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define BUS_WIDTH 8 /* AXI data bus width in bytes */ + +/* DMA buffer descriptor bits & masks */ +#define BD_STAT_OWN (1 << 31) +#define BD_STAT_BD_FIRST (1 << 3) +#define BD_STAT_BD_LAST (1 << 2) +#define BD_SIZES_BUFFER1_MASK 0xfff + +#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST) + +/* Controller command flags */ +#define B_WFR (1 << 19) /* 1b - Wait for ready */ +#define B_LC (1 << 18) /* 1b - Last cycle */ +#define B_IWC (1 << 13) /* 1b - Interrupt when complete */ + +/* NAND cycle types */ +#define B_CT_ADDRESS (0x0 << 16) /* Address operation */ +#define B_CT_COMMAND (0x1 << 16) /* Command operation */ +#define B_CT_WRITE (0x2 << 16) /* Write operation */ +#define B_CT_READ (0x3 << 16) /* Write operation */ + +enum nand_isr_t { + NAND_ISR_DATAREQUIRED = 0, + NAND_ISR_TXUNDERFLOW, + NAND_ISR_TXOVERFLOW, + NAND_ISR_DATAAVAILABLE, + NAND_ISR_RXUNDERFLOW, + NAND_ISR_RXOVERFLOW, + NAND_ISR_TXDMACOMPLETE, + NAND_ISR_RXDMACOMPLETE, + NAND_ISR_DESCRIPTORUNAVAILABLE, + NAND_ISR_CMDDONE, + NAND_ISR_CMDAVAILABLE, + NAND_ISR_CMDERROR, + NAND_ISR_DATATRANSFEROVER, + NAND_ISR_NONE +}; + +enum nand_regs_t { + AC_FIFO = 0, /* address and command fifo */ + IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */ + INT_STATUS = 0x118, /* interrupt status register */ + INT_CLR_STATUS = 0x120, /* interrupt clear status register */ +}; + +struct nand_bd { + uint32_t status; /* DES0 */ + uint32_t sizes; /* DES1 */ + uint32_t buffer_ptr0; /* DES2 */ + uint32_t buffer_ptr1; /* DES3 */ +}; + +#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r) +#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r) + +static struct nand_bd *bd; /* DMA buffer descriptors */ + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static uint32_t nand_flag_is_set(uint32_t flag) +{ + uint32_t reg = NAND_REG_READ(INT_STATUS); + + if (reg & (1 << NAND_ISR_CMDERROR)) + return 0; + + if (reg & (1 << flag)) { + NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag); + return 1; + } + + return 0; +} + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Issue "write" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store data + * @len: number of bytes to read + */ +static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Issue "read" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char axs101_nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + + axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * axs101_nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 axs101_nand_read_word(struct mtd_info *mtd) +{ + u16 word; + + axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * axs101_nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, + unsigned int ctrl) +{ + if (cmd == NAND_CMD_NONE) + return; + + cmd = cmd & 0xff; + + switch (ctrl & (NAND_ALE | NAND_CLE)) { + /* Address */ + case NAND_ALE: + cmd |= B_CT_ADDRESS; + break; + + /* Command */ + case NAND_CLE: + cmd |= B_CT_COMMAND | B_WFR; + + break; + + default: + debug("%s: unknown ctrl %#x\n", __func__, ctrl); + } + + NAND_REG_WRITE(AC_FIFO, cmd | B_LC); + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; +} + +int board_nand_init(struct nand_chip *nand) +{ + bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN, + sizeof(struct nand_bd)); + + /* Set buffer descriptor address in IDMAC */ + NAND_REG_WRITE(IDMAC_BDADDR, bd); + + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = axs101_nand_hwcontrol; + nand->read_byte = axs101_nand_read_byte; + nand->read_word = axs101_nand_read_word; + nand->write_buf = axs101_nand_write_buf; + nand->read_buf = axs101_nand_read_buf; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index de39bfaa0dc..c97c4bdd5d5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1230,6 +1230,7 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +Active arc arc700 - synopsys - axs101 - Alexey Brodkin Active arc arc700 - synopsys - arcangel4 - Alexey Brodkin Active arc arc700 - synopsys arcangel4 arcangel4-be - Alexey Brodkin Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski diff --git a/include/configs/axs101.h b/include/configs/axs101.h new file mode 100644 index 00000000000..af2e63b4db7 --- /dev/null +++ b/include/configs/axs101.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_AXS101_H_ +#define _CONFIG_AXS101_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CLK_FREQ 750000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* dwgmac doesn't work with D$ enabled now */ +#define CONFIG_SYS_DCACHE_OFF + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 +#define ARC_APB_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) +#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * UART configuration + * + * CONFIG_CONS_INDEX = 1 - Debug UART + * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB + */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#if (CONFIG_CONS_INDEX == 1) + /* Debug UART */ +# define CONFIG_SYS_NS16550_CLK 33333000 +#else + /* FPGA UARTs use different clock */ +# define CONFIG_SYS_NS16550_CLK 33333333 +#endif +#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000) +#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000) +#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000) +#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_ENV_EEPROM_BUS 2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_BASE 0xE001D000 +#define CONFIG_SYS_I2C_BASE1 0xE001E000 +#define CONFIG_SYS_I2C_BASE2 0xE001F000 +#define CONFIG_SYS_I2C_BUS_MAX 3 +#define IC_CLK 50 + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32 + +/* + * SD/MMC configuration + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_DOS_PARTITION + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_MII +#define CONFIG_PHY_GIGE + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_AUTONEG +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS3,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "axs# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_AXS101_H_ */ -- cgit v1.3.1 From 92a190aaab3536d695c51e0739f925910eb49889 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 22 Jan 2014 20:54:06 +0400 Subject: net/designware - switch driver to phylib usage With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger Cc: Vipin Kumar Cc: Stefan Roese Cc: Mischa Jonker Cc: Shiraz Hashim Cc: Albert ARIBAUD Cc: Amit Virdi Cc: Sonic Zhang Signed-off-by: Alexey Brodkin --- board/bf609-ezkit/bf609-ezkit.c | 4 +- board/spear/spear300/spear300.c | 3 +- board/spear/spear310/spear310.c | 3 +- board/spear/spear320/spear320.c | 3 +- board/spear/spear600/spear600.c | 3 +- board/spear/x600/x600.c | 25 +-- doc/README.designware_eth | 25 --- drivers/net/designware.c | 460 +++++++++++++--------------------------- drivers/net/designware.h | 18 +- include/configs/bf609-ezkit.h | 3 +- include/configs/spear-common.h | 4 +- include/configs/spear6xx_evb.h | 3 + include/netdev.h | 2 +- 13 files changed, 177 insertions(+), 379 deletions(-) delete mode 100644 doc/README.designware_eth (limited to 'include') diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index cfc64fe51d6..43a43306bbc 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis) if (CONFIG_DW_PORTS & 1) { static const unsigned short pins[] = P_RMII0; if (!peripheral_request_list(pins, "emac0")) - ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); + ret += designware_initialize(EMAC0_MACCFG, 0); } if (CONFIG_DW_PORTS & 2) { static const unsigned short pins[] = P_RMII1; if (!peripheral_request_list(pins, "emac1")) - ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); + ret += designware_initialize(EMAC1_MACCFG, 0); } return ret; diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index e25aba2f287..6b6bd9f29d5 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 70f9aa16eaa..a4c6a8edb0d 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index f6b1fdd0e63..ab732a724c7 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index e996a0e381e..8472002f749 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DW_AUTONEG) interface = PHY_INTERFACE_MODE_GMII; #endif - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index 044d2049ef8..b8edfcd071f 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -67,31 +67,32 @@ void board_nand_init(void) fsmc_nand_init(nand); } -int designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) +int board_phy_config(struct phy_device *phydev) { /* Extended PHY control 1, select GMII */ - mii_write(dev, phy_addr, 23, 0x0020); + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); /* Software reset necessary after GMII mode selction */ - dw_reset_phy(dev); + phy_reset(phydev); /* Enable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0001); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); /* 17e: Enhanced LED behavior, needs to be written twice */ - mii_write(dev, phy_addr, 17, 0x09ff); - mii_write(dev, phy_addr, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); /* 16e: Enhanced LED method select */ - mii_write(dev, phy_addr, 16, 0xe0ea); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); /* Disable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); /* Enable clock output pin */ - mii_write(dev, phy_addr, 18, 0x0049); + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis) { int ret = 0; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + if (designware_initialize(CONFIG_SPEAR_ETHBASE, PHY_INTERFACE_MODE_GMII) >= 0) ret++; diff --git a/doc/README.designware_eth b/doc/README.designware_eth deleted file mode 100644 index 25ec6bd9699..00000000000 --- a/doc/README.designware_eth +++ /dev/null @@ -1,25 +0,0 @@ -This driver supports Designware Ethernet Controller provided by Synopsis. - -The driver is enabled by CONFIG_DESIGNWARE_ETH. - -The driver has been developed and tested on SPEAr platforms. By default, the -MDIO interface works at 100/Full. #defining the below options in board -configuration file changes this behavior. - -Call an subroutine from respective board/.../board.c -designware_initialize(u32 id, ulong base_addr, u32 phy_addr); - -The various options suported by the driver are -1. CONFIG_DW_ALTDESCRIPTOR - Define this to use the Alternate/Enhanced Descriptor configurations. -1. CONFIG_DW_AUTONEG - Define this to autonegotiate with the host before proceeding with mac - level configuration. This obviates the definitions of CONFIG_DW_SPEED10M - and CONFIG_DW_DUPLEXHALF. -2. CONFIG_DW_SPEED10M - Define this to change the default behavior from 100Mbps to 10Mbps. -3. CONFIG_DW_DUPLEXHALF - Define this to change the default behavior from Full Duplex to Half. -4. CONFIG_DW_SEARCH_PHY - Define this to search the phy address. This would overwrite the value - passed as 3rd arg from designware_initialize routine. diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 186808943ab..44c1e350ced 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -17,7 +17,75 @@ #include #include "designware.h" -static int configure_phy(struct eth_device *dev); +#if !defined(CONFIG_PHYLIB) +# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -1; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -1; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} static void tx_descs_init(struct eth_device *dev) { @@ -83,53 +151,59 @@ static void rx_descs_init(struct eth_device *dev) priv->rx_currdescnum = 0; } -static void descs_init(struct eth_device *dev) +static int dw_write_hwaddr(struct eth_device *dev) { - tx_descs_init(dev); - rx_descs_init(dev); + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; } -static int mac_reset(struct eth_device *dev) +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; - ulong start; - int timeout = CONFIG_MACRESET_TIMEOUT; + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } - writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; - if (priv->interface != PHY_INTERFACE_MODE_RGMII) - writel(MII_PORTSELECT, &mac_p->conf); + if (phydev->speed == 100) + conf |= FES_100; - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) - return 0; + if (phydev->duplex) + conf |= FULLDPLXMODE; - /* Try again after 10usec */ - udelay(10); - }; + writel(conf, &mac_p->conf); - return -1; + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } -static int dw_write_hwaddr(struct eth_device *dev) +static void dw_eth_halt(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 macid_lo, macid_hi; - u8 *mac_id = &dev->enetaddr[0]; + struct eth_dma_regs *dma_p = priv->dma_regs_p; - macid_lo = mac_id[0] + (mac_id[1] << 8) + \ - (mac_id[2] << 16) + (mac_id[3] << 24); - macid_hi = mac_id[4] + (mac_id[5] << 8); + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); - writel(macid_hi, &mac_p->macaddr0hi); - writel(macid_lo, &mac_p->macaddr0lo); - - return 0; + phy_shutdown(priv->phydev); } static int dw_eth_init(struct eth_device *dev, bd_t *bis) @@ -137,55 +211,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - u32 conf; + unsigned int start; - if (priv->phy_configured != 1) - configure_phy(dev); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) + return -1; - /* Reset ethernet hardware */ - if (mac_reset(dev) < 0) - return -1; + mdelay(100); + }; - /* Resore the HW MAC address as it has been lost during MAC reset */ + /* Soft reset above clears HW address registers. + * So we have to set it here once again */ dw_write_hwaddr(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, - &dma_p->busmode); - - writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | - TXSECONDFRAME, &dma_p->opmode); + rx_descs_init(dev); + tx_descs_init(dev); - conf = FRAMEBURSTENABLE | DISABLERXOWN; + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - if (priv->speed != 1000) - conf |= MII_PORTSELECT; + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); - if ((priv->interface != PHY_INTERFACE_MODE_MII) && - (priv->interface != PHY_INTERFACE_MODE_GMII)) { + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); - if (priv->speed == 100) - conf |= FES_100; + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; } - if (priv->duplex == FULL) - conf |= FULLDPLXMODE; - - writel(conf, &mac_p->conf); + dw_adjust_link(mac_p, priv->phydev); - descs_init(dev); - - /* - * Start/Enable xfer at dma as well as mac level - */ - writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); - writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + if (!priv->phydev->link) + return -1; writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); @@ -267,251 +329,30 @@ static int dw_eth_recv(struct eth_device *dev) return length; } -static void dw_eth_halt(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - - mac_reset(dev); - priv->tx_currdescnum = priv->rx_currdescnum = 0; -} - -static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +static int dw_phy_init(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; - - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK); - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - *val = readl(&mac_p->miidata); - return 0; - } + struct phy_device *phydev; + int mask = 0xffffffff; - /* Try again after 10usec */ - udelay(10); - }; - - return -1; -} - -static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - u16 value; - - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } - - /* Try again after 10usec */ - udelay(10); - }; - - /* Needed as a fix for ST-Phy */ - eth_mdio_read(dev, addr, reg, &value); - - return ret; -} - -#if defined(CONFIG_DW_SEARCH_PHY) -static int find_phy(struct eth_device *dev) -{ - int phy_addr = 0; - u16 ctrl, oldctrl; - - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - oldctrl = ctrl & BMCR_ANENABLE; - - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - ctrl &= BMCR_ANENABLE; - - if (ctrl == oldctrl) { - phy_addr++; - } else { - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - - return phy_addr; - } - } while (phy_addr < 32); - - return -1; -} +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; #endif -static int dw_reset_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - u16 ctrl; - ulong start; - int timeout = CONFIG_PHYRESET_TIMEOUT; - u32 phy_addr = priv->address; - - eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); - - start = get_timer(0); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - if (!(ctrl & BMCR_RESET)) - break; - - /* Try again after 10usec */ - udelay(10); - }; - - if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) return -1; -#ifdef CONFIG_PHY_RESET_DELAY - udelay(CONFIG_PHY_RESET_DELAY); -#endif - return 0; -} + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; -/* - * Add weak default function for board specific PHY configuration - */ -int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) -{ - return 0; -} + priv->phydev = phydev; + phy_config(phydev); -static int configure_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - int phy_addr; - u16 bmcr; -#if defined(CONFIG_DW_AUTONEG) - u16 bmsr; - u32 timeout; - ulong start; -#endif - -#if defined(CONFIG_DW_SEARCH_PHY) - phy_addr = find_phy(dev); - if (phy_addr >= 0) - priv->address = phy_addr; - else - return -1; -#else - phy_addr = priv->address; -#endif - - /* - * Some boards need board specific PHY initialization. This is - * after the main driver init code but before the auto negotiation - * is run. - */ - if (designware_board_phy_init(dev, phy_addr, - eth_mdio_write, dw_reset_phy) < 0) - return -1; - - if (dw_reset_phy(dev) < 0) - return -1; - -#if defined(CONFIG_DW_AUTONEG) - /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ - eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); - - bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -#else - bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; - -#if defined(CONFIG_DW_SPEED10M) - bmcr &= ~BMCR_SPEED100; -#endif -#if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~BMCR_FULLDPLX; -#endif -#endif - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - - /* Read the phy status register and populate priv structure */ -#if defined(CONFIG_DW_AUTONEG) - timeout = CONFIG_AUTONEG_TIMEOUT; - start = get_timer(0); - puts("Waiting for PHY auto negotiation to complete"); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) { - priv->phy_configured = 1; - break; - } - - /* Print dot all 1s to show progress */ - if ((get_timer(start) % 1000) == 0) - putc('.'); - - /* Try again after 1msec */ - udelay(1000); - }; - - if (!(bmsr & BMSR_ANEGCOMPLETE)) - puts(" TIMEOUT!\n"); - else - puts(" done\n"); -#else - priv->phy_configured = 1; -#endif - - priv->speed = miiphy_speed(dev->name, phy_addr); - priv->duplex = miiphy_duplex(dev->name, phy_addr); - - return 0; -} - -#if defined(CONFIG_MII) -static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_read(dev, addr, reg, val); - - return 0; -} - -static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_write(dev, addr, reg, val); - - return 0; + return 1; } -#endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) +int designware_initialize(ulong base_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -533,19 +374,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev)); - sprintf(dev->name, "mii%d", id); + sprintf(dev->name, "dwmac.%lx", base_addr); dev->iobase = (int)base_addr; dev->priv = priv; - eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); - priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); - priv->address = phy_addr; - priv->phy_configured = 0; - priv->interface = interface; dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -555,8 +391,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) eth_register(dev); -#if defined(CONFIG_MII) - miiphy_register(dev->name, dw_mii_read, dw_mii_write); -#endif - return 1; + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(dev); } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 5440c9215fb..afeaccec19a 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -16,8 +16,6 @@ #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) struct eth_mac_regs { u32 conf; /* 0x00 */ @@ -217,14 +215,9 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 address; u32 interface; - u32 speed; - u32 duplex; u32 tx_currdescnum; u32 rx_currdescnum; - u32 phy_configured; - u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -236,15 +229,8 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; }; -/* Speed specific definitions */ -#define SPEED_10M 1 -#define SPEED_100M 2 -#define SPEED_1000M 3 - -/* Duplex mode specific definitions */ -#define HALF_DUPLEX 1 -#define FULL_DUPLEX 2 - #endif diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b433e..12192ffb5d7 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,12 +72,13 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH +#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 -#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_BFIN_TWI_I2C diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 23f7ad77b61..e090a376d03 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,11 +17,9 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY -#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 7f4dc5801c2..28dddcc5b93 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,6 +37,9 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000 +/* Ethernet PHY configuration */ +#define CONFIG_PHY_NATSEMI + /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/netdev.h b/include/netdev.h index 47fa80d6fc4..37056291946 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); +int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); -- cgit v1.3.1 From 1a78d28d024d458f24e78bd469e2e428145397fc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 7 Feb 2014 08:52:06 -0500 Subject: x600: Switch to CONFIG_PHYLIB Now that the designware ethernet driver uses phylib we need to turn it on here. Acked-by: Stefan Roese Signed-off-by: Tom Rini --- include/configs/x600.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/x600.h b/include/configs/x600.h index 39540e38060..00b938a2160 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -74,10 +74,9 @@ /* Ethernet config options */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -- cgit v1.3.1 From d3e016cc28684cd32d826a9414a0e89ccf80861a Mon Sep 17 00:00:00 2001 From: Rajeshwari S Shinde Date: Wed, 5 Feb 2014 10:48:15 +0530 Subject: MMC: DWMMC: Correct the CLKDIV register value This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde Acked-by: Jaehoon Chung Signed-off-by: Pantelis Antoniou --- arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- include/dwmmc.h | 2 +- 4 files changed, 21 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739dfca9..a7ca12c477e 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aaa604..d45c15cfa4e 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host->dev_index); + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b3e5c5e5e09..de8cdcc42b3 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) diff --git a/include/dwmmc.h b/include/dwmmc.h index a02dd67c137..b64155851d6 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -142,7 +142,7 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(int dev_index); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); }; struct dwmci_idmac { -- cgit v1.3.1 From 7dbe63bc950bbd12d021f72bf04104688cd324a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:18 -0500 Subject: SPL: Add CONFIG_SUPPORT_EMMC_BOOT support to CONFIG_SPL_FRAMEWORK We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some additional features of the eMMC boot partitions. Add support for being told that we have booted from one of these partitions to the spl framework and implement this on TI OMAP/related. Cc: Pantelis Antoniou Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- arch/arm/cpu/armv7/omap-common/boot-common.c | 13 ++++++++++++- common/spl/spl_mmc.c | 24 ++++++++++++++++++++++++ include/spl.h | 1 + 3 files changed, 37 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 69fff323d36..52e0f4a6cf5 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -66,7 +66,18 @@ u32 spl_boot_device(void) u32 spl_boot_mode(void) { - return gd->arch.omap_boot_params.omap_bootmode; + u32 val = gd->arch.omap_boot_params.omap_bootmode; + + if (val == MMCSD_MODE_RAW) + return MMCSD_MODE_RAW; + else if (val == MMCSD_MODE_FAT) + return MMCSD_MODE_FAT; + else +#ifdef CONFIG_SUPPORT_EMMC_BOOT + return MMCSD_MODE_EMMCBOOT; +#else + return MMCSD_MODE_UNDEFINED; +#endif } void spl_board_init(void) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 13fbff082cf..fa6f891bc80 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -110,6 +110,30 @@ void spl_mmc_load_image(void) err = spl_load_image_fat(&mmc->block_dev, CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); +#endif +#ifdef CONFIG_SUPPORT_EMMC_BOOT + } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ + int part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; + + if (mmc_switch_part(0, part)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("MMC partition switch failed\n"); +#endif + hang(); + } +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) +#endif + err = mmc_load_image_raw(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #endif } else { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/spl.h b/include/spl.h index 5e248561f13..dad00c0075d 100644 --- a/include/spl.h +++ b/include/spl.h @@ -16,6 +16,7 @@ #define MMCSD_MODE_UNDEFINED 0 #define MMCSD_MODE_RAW 1 #define MMCSD_MODE_FAT 2 +#define MMCSD_MODE_EMMCBOOT 3 struct spl_image_info { const char *name; -- cgit v1.3.1 From 792970b0a344d905848fb98564ed469786af11b7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:21 -0500 Subject: cmd_mmc.c: Add 'partconf' command to mmc Add a partconf sub-command to the mmc command to allow for setting the boot_ack, boot_partition and partition_access fields of PARTITION_CONFIG (formerly BOOT_CONFIG, EXT_CSD[179]). Part of this requires changing the check for 'part' from an strncmp to a strcmp, like the rest of the sub-commands. Cc: Andy Fleming Cc: Pantelis Antoniou Acked-by: Jaehoon Chung Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- common/cmd_mmc.c | 30 +++++++++++++++++++++++++++++- drivers/mmc/mmc.c | 21 +++++++++++++++++++++ include/mmc.h | 2 ++ 3 files changed, 52 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a322063cf6a..5842e85de9f 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -195,7 +195,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; else return 0; - } else if (strncmp(argv[1], "part", 4) == 0) { + } else if (strcmp(argv[1], "part") == 0) { block_dev_desc_t *mmc_dev; struct mmc *mmc; @@ -311,7 +311,33 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* acknowledge to be sent during boot operation */ return boot_part_access(mmc, 1, part_num, access); + } else if (strcmp(argv[1], "partconf") == 0) { + int dev; + struct mmc *mmc; + u8 ack, part_num, access; + + if (argc == 6) { + dev = simple_strtoul(argv[2], NULL, 10); + ack = simple_strtoul(argv[3], NULL, 10); + part_num = simple_strtoul(argv[4], NULL, 10); + access = simple_strtoul(argv[5], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + if (IS_SD(mmc)) { + puts("PARTITION_CONFIG only exists on eMMC\n"); + return 1; + } + + /* acknowledge to be sent during boot operation */ + return mmc_set_part_conf(mmc, ack, part_num, access); } else if (strcmp(argv[1], "bootpart-resize") == 0) { int dev; struct mmc *mmc; @@ -451,6 +477,8 @@ U_BOOT_CMD( " - Enable boot_part for booting and disable access to boot_part\n" "mmc bootpart-resize \n" " - Change sizes of boot and RPMB partitions of specified device\n" + "mmc partconf dev boot_ack boot_partition partition_access\n" + " - Change the bits of the PARTITION_CONFIG field of the specified device\n" #endif "mmc setdsr - set DSR register value\n" ); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 7efc2bedbe1..907c4185ade 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1505,4 +1505,25 @@ int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) } return 0; } + +/* + * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + * + * Returns 0 on success. + */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)); + + if (err) + return err; + return 0; +} #endif diff --git a/include/mmc.h b/include/mmc.h index e1060b9ff27..7e026da4446 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -312,6 +312,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); /* Function to send commands to open/close the specified boot partition */ int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the PARTITION_CONFIG field of EXT_CSD */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /** * Start device initialization and return immediately; it does not block on -- cgit v1.3.1 From 5a99b9de1a845bf254292ae4730633e6ca8a29c7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:22 -0500 Subject: cmd_mmc.c: Add bootbus mmc sub-command Add a bootbus sub-command to the mmc command to allow for setting the boot_bus_width, reset_boot_bus_width and boot_mode fields of BOOT_BUS_WIDTH (EXT_CSD[177]). Acked-by: Jaehoon Chung Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- common/cmd_mmc.c | 29 +++++++++++++++++++++++++++++ drivers/mmc/mmc.c | 21 +++++++++++++++++++++ include/mmc.h | 5 +++++ 3 files changed, 55 insertions(+) (limited to 'include') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 5842e85de9f..a028149d906 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -338,6 +338,33 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* acknowledge to be sent during boot operation */ return mmc_set_part_conf(mmc, ack, part_num, access); + } else if (strcmp(argv[1], "bootbus") == 0) { + int dev; + struct mmc *mmc; + u8 width, reset, mode; + + if (argc == 6) { + dev = simple_strtoul(argv[2], NULL, 10); + width = simple_strtoul(argv[3], NULL, 10); + reset = simple_strtoul(argv[4], NULL, 10); + mode = simple_strtoul(argv[5], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + puts("BOOT_BUS_WIDTH only exists on eMMC\n"); + return 1; + } + + /* acknowledge to be sent during boot operation */ + return mmc_set_boot_bus_width(mmc, width, reset, mode); } else if (strcmp(argv[1], "bootpart-resize") == 0) { int dev; struct mmc *mmc; @@ -475,6 +502,8 @@ U_BOOT_CMD( " - Enable boot_part for booting and enable R/W access of boot_part\n" "mmc close \n" " - Enable boot_part for booting and disable access to boot_part\n" + "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" + " - Set the BOOT_BUS_WIDTH field of the specified device\n" "mmc bootpart-resize \n" " - Change sizes of boot and RPMB partitions of specified device\n" "mmc partconf dev boot_ack boot_partition partition_access\n" diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 907c4185ade..37719d26558 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1506,6 +1506,27 @@ int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) return 0; } +/* + * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH + * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH + * and BOOT_MODE. + * + * Returns 0 on success. + */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, + EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | + EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | + EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); + + if (err) + return err; + return 0; +} + /* * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and diff --git a/include/mmc.h b/include/mmc.h index 7e026da4446..3594286d42c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -187,6 +187,9 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -314,6 +317,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /** * Start device initialization and return immediately; it does not block on -- cgit v1.3.1 From 614b2bf1c9bf80dbad24f5e5ce1d115bf24a831d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:23 -0500 Subject: cmd_mmc.c: Drop open/close mmc sub-commands The open and close mmc sub-commands implement a hard-coded set of values specific to the SMDK5250 platform. Remove these commands as what they did can be done instead with a series of mmc dev / bootpart / bootbus commands instead now. Cc: Amar Cc: Minkyu Kang Acked-by: Jaehoon Chung Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- common/cmd_mmc.c | 72 ------------------------------------------------------- drivers/mmc/mmc.c | 65 ------------------------------------------------- include/mmc.h | 2 -- 3 files changed, 139 deletions(-) (limited to 'include') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a028149d906..2d519270602 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -131,36 +131,6 @@ U_BOOT_CMD( "- display info of the current MMC device" ); -#ifdef CONFIG_SUPPORT_EMMC_BOOT -static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - err = mmc_boot_part_access(mmc, ack, part_num, access); - - if ((err == 0) && (access != 0)) { - printf("\t\t\t!!!Notice!!!\n"); - - printf("!You must close EMMC boot Partition"); - printf("after all images are written\n"); - - printf("!EMMC boot partition has continuity"); - printf("at image writing time.\n"); - - printf("!So, do not close the boot partition"); - printf("before all images are written.\n"); - return 0; - } else if ((err == 0) && (access == 0)) - return 0; - else if ((err != 0) && (access != 0)) { - printf("EMMC boot partition-%d OPEN Failed.\n", part_num); - return 1; - } else { - printf("EMMC boot partition-%d CLOSE Failed.\n", part_num); - return 1; - } -} -#endif - static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -273,44 +243,6 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; #ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if ((strcmp(argv[1], "open") == 0) || - (strcmp(argv[1], "close") == 0)) { - int dev; - struct mmc *mmc; - u8 part_num, access = 0; - - if (argc == 4) { - dev = simple_strtoul(argv[2], NULL, 10); - part_num = simple_strtoul(argv[3], NULL, 10); - } else { - return CMD_RET_USAGE; - } - - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } - - if (IS_SD(mmc)) { - printf("SD device cannot be opened/closed\n"); - return 1; - } - - if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) { - printf("Invalid boot partition number:\n"); - printf("Boot partition number cannot be <= 0\n"); - printf("EMMC44 supports only 2 boot partitions\n"); - return 1; - } - - if (strcmp(argv[1], "open") == 0) - access = part_num; /* enable R/W access to boot part*/ - else - access = 0; /* No access to boot partition */ - - /* acknowledge to be sent during boot operation */ - return boot_part_access(mmc, 1, part_num, access); } else if (strcmp(argv[1], "partconf") == 0) { int dev; struct mmc *mmc; @@ -498,10 +430,6 @@ U_BOOT_CMD( "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" #ifdef CONFIG_SUPPORT_EMMC_BOOT - "mmc open \n" - " - Enable boot_part for booting and enable R/W access of boot_part\n" - "mmc close \n" - " - Enable boot_part for booting and disable access to boot_part\n" "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" " - Set the BOOT_BUS_WIDTH field of the specified device\n" "mmc bootpart-resize \n" diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 37719d26558..8ab0bc948f5 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1441,71 +1441,6 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, return 0; } -/* - * This function shall form and send the commands to open / close the - * boot partition specified by user. - * - * Input Parameters: - * ack: 0x0 - No boot acknowledge sent (default) - * 0x1 - Boot acknowledge sent during boot operation - * part_num: User selects boot data that will be sent to master - * 0x0 - Device not boot enabled (default) - * 0x1 - Boot partition 1 enabled for boot - * 0x2 - Boot partition 2 enabled for boot - * access: User selects partitions to access - * 0x0 : No access to boot partition (default) - * 0x1 : R/W boot partition 1 - * 0x2 : R/W boot partition 2 - * 0x3 : R/W Replay Protected Memory Block (RPMB) - * - * Returns 0 on success. - */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - struct mmc_cmd cmd; - - /* Boot ack enable, boot partition enable , boot partition access */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_PART_CONF << 16) | - ((EXT_CSD_BOOT_ACK(ack) | - EXT_CSD_BOOT_PART_NUM(part_num) | - EXT_CSD_PARTITION_ACCESS(access)) << 8); - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - if (access) { - debug("mmc boot partition#%d open fail:Error1 = %d\n", - part_num, err); - } else { - debug("mmc boot partition#%d close fail:Error = %d\n", - part_num, err); - } - return err; - } - - if (access) { - /* 4bit transfer mode at booting time. */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_BOOT_BUS_WIDTH << 16) | - ((1 << 0) << 8); - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc boot partition#%d open fail:Error2 = %d\n", - part_num, err); - return err; - } - } - return 0; -} - /* * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH diff --git a/include/mmc.h b/include/mmc.h index 3594286d42c..e95a2376d20 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -313,8 +313,6 @@ int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); -/* Function to send commands to open/close the specified boot partition */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ -- cgit v1.3.1 From 378ec0f8161d12df63016b7ad1e9415b4221b7dc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:24 -0500 Subject: omap5_uevm: Add CONFIG_SUPPORT_EMMC_BOOT, document usage Add a README to the board which lists the commands required to enable booting from the eMMC boot partitions found on the board. Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- board/ti/omap5_uevm/README | 25 +++++++++++++++++++++++++ include/configs/omap5_uevm.h | 1 + 2 files changed, 26 insertions(+) create mode 100644 board/ti/omap5_uevm/README (limited to 'include') diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README new file mode 100644 index 00000000000..970e2eceb77 --- /dev/null +++ b/board/ti/omap5_uevm/README @@ -0,0 +1,25 @@ +Summary +======= + +This document covers various features of the 'omap5_uevm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} omap5uevm/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 76c5106b45e..3df502eda02 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,6 +37,7 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART #define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X -- cgit v1.3.1 From b818d9ab8d96471c40ccbd4541a46dfa415eda73 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:25 -0500 Subject: dra7xx_evm: Add CONFIG_SUPPORT_EMMC_BOOT, document usage Add a README to the board which lists the commands required to enable booting from the eMMC boot partitions found on the board. Cc: Lokesh Vutla Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- board/ti/dra7xx/README | 25 +++++++++++++++++++++++++ include/configs/dra7xx_evm.h | 2 ++ 2 files changed, 27 insertions(+) create mode 100644 board/ti/dra7xx/README (limited to 'include') diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README new file mode 100644 index 00000000000..2fdaeac31ee --- /dev/null +++ b/board/ti/dra7xx/README @@ -0,0 +1,25 @@ +Summary +======= + +This document covers various features of the 'dra7xx_evm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} dra7xx/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} dra7xx/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f210ed8b924..3c53f0af10b 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -73,6 +73,8 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SUPPORT_EMMC_BOOT + /* USB xHCI HOST */ #define CONFIG_CMD_USB #define CONFIG_USB_HOST -- cgit v1.3.1 From bccaa476f69351c44f382668474896fb360d054f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 28 Jan 2014 22:41:50 -0700 Subject: ARM: rpi_b: set $fdtfile in default environment U-Boot names the Raspberry Pi board rpi_b. This means that the common expression for DTB filename ${soc}-${board}.dtb expands to bcm2835-rpi_b.dtb. However, the DTB generated by the Linux kernel is bcm2835-rpi-b.dtb. Set $fdtfile in U-Boot's environment so that scripts look for the correct DTB filename. An alternative would be to rename the U-Boot board to rpi-b. However, that change would be far more invasive, and end up affecting users (i.e they'd have to change their U-Boot build commands). Signed-off-by: Stephen Warren --- include/configs/rpi_b.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 0b7add7bea3..976ceaa9c1d 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -123,6 +123,7 @@ "scriptaddr=0x00000000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ + "fdtfile=bcm2835-rpi-b.dtb\0" \ "ramdisk_addr_r=0x02100000\0" \ "boot_targets=mmc0\0" \ \ -- cgit v1.3.1 From dfa94058f550e06405e80df4fb277fd306a77cbd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 5 Feb 2014 07:56:07 +0100 Subject: zynq: Use full tftpboot command instead of shortcut tftp The reason is enabling tftpput command where tftp shorcut stops to work for tftpboot. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e7a8e9fb11b..3b461e07a63 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -164,7 +164,7 @@ "fatload mmc 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "jtagboot=echo TFTPing FIT to RAM... && " \ - "tftp ${load_addr} ${fit_image} && " \ + "tftpboot ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ -- cgit v1.3.1 From 38716189d439c3ed8707e7bc1f430322ba7a810d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 5 Feb 2014 08:06:29 +0100 Subject: zynq: Fix elf header generation This patch is here because of: "arm: keep all sections in ELF file" (sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7) Our tools expect to have elf with only LOAD header. Without this fix also PHDR, INTERP and DYNAMIC headers are available in ELF. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/u-boot.lds | 99 ++++++++++++++++++++++++++++++++++++++ include/configs/zynq-common.h | 2 + 2 files changed, 101 insertions(+) create mode 100644 arch/arm/cpu/armv7/zynq/u-boot.lds (limited to 'include') diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds new file mode 100644 index 00000000000..a68b050f2bd --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /* + * Zynq needs to discard more sections because the user + * is expected to pass this image on to tools for boot.bin + * generation that require them to be dropped. + */ + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 3b461e07a63..9b6db043b57 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -228,6 +228,8 @@ # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif +#define CONFIG_SYS_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot.lds" + /* Commands */ #include -- cgit v1.3.1 From 2a4ebef267ffb615ff753f6ce804e0643110e5a4 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Mon, 27 Jan 2014 16:58:24 +0100 Subject: arm/km/suv31: switch to 256MB RAM We now use 256MB RAM instead of 128MB. We can use the same config file as kmnusa. Signed-off-by: Holger Brunck Acked-by: Valentin Longchamp --- include/configs/km_kirkwood.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 74c72325f65..2bd89b1e249 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -97,6 +97,9 @@ #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile SUV31" #define CONFIG_HOSTNAME kmsuv31 +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG -- cgit v1.3.1 From 56cde17760deacc45866cdc6a2248d0fc245026d Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Mon, 27 Jan 2014 16:58:25 +0100 Subject: arm/km: add CONFIG_KM_BOARD_EXTRA_ENV to default environment This is needed for board specific additional environment variables. E.g. the mgcoge3un has this additional "waitforne" variable. Signed-off-by: Holger Brunck Acked-by: Valentin Longchamp --- include/configs/km/km_arm.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index e74f85f6045..6278e76d9f8 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -289,10 +289,15 @@ int get_scl(void); " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" #endif +#ifndef CONFIG_KM_BOARD_EXTRA_ENV +#define CONFIG_KM_BOARD_EXTRA_ENV "" +#endif + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_BOARD_EXTRA_ENV \ CONFIG_KM_DEF_ENV \ CONFIG_KM_NEW_ENV \ "arch=arm\0" \ -- cgit v1.3.1 From 7b2268b88fb9a67b13563fa61b8ae282b9aa6e00 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Mon, 27 Jan 2014 16:58:27 +0100 Subject: arm/km: enable FDT for km_kirwkood This consists of: a) Defining the addresses, enabling fdtsupport [arm] b) Defining "cramfsloadfdt" [arm,powerpc => common] c) Adding the FDT address to bootm [arm,powerpc => common] d) Defining "tftpfdt" in ramfs-,develop- [arm,powerpc >= common] This should work with 3.10 kernels, whether loaded through TFTP (with rootfs either through NFS or TFTP-ramfs) or from the NAND. The machid was left unchanged, this should keep compatibility with both older and newer kernels. Signed-off-by: Valentin Longchamp Signed-off-by: Gerlando Falauto Signed-off-by: Holger Brunck Acked-by: Valentin Longchamp --- board/keymile/scripts/develop-arm.txt | 1 - board/keymile/scripts/develop-common.txt | 1 + board/keymile/scripts/develop-ppc_82xx.txt | 1 - board/keymile/scripts/develop-ppc_8xx.txt | 1 - board/keymile/scripts/ramfs-arm.txt | 1 - board/keymile/scripts/ramfs-common.txt | 1 + board/keymile/scripts/ramfs-ppc_82xx.txt | 1 - board/keymile/scripts/ramfs-ppc_8xx.txt | 1 - include/configs/km/keymile-common.h | 5 +++++ include/configs/km/km-powerpc.h | 5 ----- include/configs/km/km_arm.h | 8 +++++--- 11 files changed, 12 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt index 922afea2778..d3c974f1f91 100644 --- a/board/keymile/scripts/develop-arm.txt +++ b/board/keymile/scripts/develop-arm.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=true diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index a6bb1b1d4a9..f49b26a2330 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -3,6 +3,7 @@ bootcmd=run ${subbootcmds} configure=run set_uimage; km_setboardid && saveenv && reset subbootcmds=tftpfdt tftpkernel nfsargs add_default boot nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch} +tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} toolchain=/opt/eldk rootfssize=0 diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt index 909f6a3cee3..d3c974f1f91 100644 --- a/board/keymile/scripts/develop-ppc_82xx.txt +++ b/board/keymile/scripts/develop-ppc_82xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt index 909f6a3cee3..d3c974f1f91 100644 --- a/board/keymile/scripts/develop-ppc_8xx.txt +++ b/board/keymile/scripts/develop-ppc_8xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt index 79974f1b70e..87e984e179b 100644 --- a/board/keymile/scripts/ramfs-arm.txt +++ b/board/keymile/scripts/ramfs-arm.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=true diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index 502c8631f4f..0cfb36fba01 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -7,6 +7,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} configure=run set_uimage; km_setboardid && saveenv && reset rootfsfile=${hostname}/rootfsImage setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} +tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage set_uimage=printenv uimage || setenv uimage uImage diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt index 970927a2fad..87e984e179b 100644 --- a/board/keymile/scripts/ramfs-ppc_82xx.txt +++ b/board/keymile/scripts/ramfs-ppc_82xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt index 970927a2fad..87e984e179b 100644 --- a/board/keymile/scripts/ramfs-ppc_8xx.txt +++ b/board/keymile/scripts/ramfs-ppc_8xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 2a15ad469b1..cb53dbd768f 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -220,6 +220,7 @@ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ "bootcmd=km_checkbidhwk && " \ "setenv bootcmd \'if km_checktestboot; then; " \ "setenv boot_bank ${test_bank}; else; " \ @@ -229,6 +230,10 @@ "run ${subbootcmds}; reset\' && " \ "saveenv && saveenv && boot\0" \ "bootlimit=3\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \ "init=/sbin/init-overlay.sh\0" \ "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 2cebb2bb0cc..b03fdd9b66a 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -70,11 +70,6 @@ #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "update=" \ "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 6278e76d9f8..a5cc1c5126a 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -70,7 +70,8 @@ #define CONFIG_KM_PHRAM 0x17F000 #define CONFIG_KM_CRAMFS_ADDR 0x2400000 -#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */ +#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */ /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ @@ -78,8 +79,6 @@ " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - -\0" \ - "cramfsloadfdt=true\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ CONFIG_KM_UPDATE_UBOOT \ "" @@ -87,6 +86,9 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_MISC_INIT_R +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT + /* * NS16550 Configuration */ -- cgit v1.3.1 From b1c2a7ae32b6c5dd1dcb7cb29c862af01523ba36 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Mon, 27 Jan 2014 16:58:28 +0100 Subject: arm/km: define fdt_high env variable and allow backwards compatibility Add set_fdthigh subcommand to "subbootcmds" (release) so to set "fdt_high" This is necessary on Kirkwood so that the FDT does not get relocated above the memory limit that the kernel cannot access (that is the memory part reserved for the switch). This was tested on NUSA1, where it is necessary, and on ETER1, where it doesn't seem to hurt. We want the scripts to also work with older versions of u-boot, where: a) set_fdthigh is not defined (will be default env for newer u-boots) b) the fdt will not be available For this reason, we use "set_fdthigh" to tell whether we are running a newer (FDT-aware) u-boot or not. So if "set_fdthigh" runs successfully or arch != arm we try loading the fdt; otherwise we proceed normally. Notice how, contrary to release mode, set_fdthigh will _not_ be part of subbootcmds for develop and ramfs, but will be executed as part of "tftpfdt". Since this is only needed for kirkwood cards, and it prevents the kernel from booting on QorIQ (though it seemed to work on ETER1), we change its definition in the default env for powerpc so that the value is only set on ARM. Signed-off-by: Valentin Longchamp Signed-off-by: Gerlando Falauto Signed-off-by: Holger Brunck Acked-by: Valentin Longchamp --- board/keymile/scripts/develop-common.txt | 2 +- board/keymile/scripts/ramfs-common.txt | 2 +- include/configs/km/keymile-common.h | 4 ++-- include/configs/km/km-powerpc.h | 1 + include/configs/km/km_arm.h | 1 + include/configs/km/kmp204x-common.h | 1 + 6 files changed, 7 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index f49b26a2330..a80812a5d04 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -3,7 +3,7 @@ bootcmd=run ${subbootcmds} configure=run set_uimage; km_setboardid && saveenv && reset subbootcmds=tftpfdt tftpkernel nfsargs add_default boot nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch} -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb +tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} toolchain=/opt/eldk rootfssize=0 diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index 0cfb36fba01..d79ad2e21b2 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -7,7 +7,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} configure=run set_uimage; km_setboardid && saveenv && reset rootfsfile=${hostname}/rootfsImage setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb +tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage set_uimage=printenv uimage || setenv uimage uImage diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index cb53dbd768f..7361072c982 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -135,8 +135,8 @@ * - 'release': for a standalone system kernel/rootfs from flash */ #define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \ - "flashargs add_default addpanic boot\0" \ + "subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh " \ + "cramfsloadkernel flashargs add_default addpanic boot\0"\ "develop=" \ "tftp 200000 scripts/develop-${arch}.txt && " \ "env import -t 200000 ${filesize} && " \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index b03fdd9b66a..763c5bad82c 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -77,6 +77,7 @@ "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ " ${filesize} && " \ "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ + "set_fdthigh=true\0" \ "" #endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index a5cc1c5126a..6d77680c82a 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -81,6 +81,7 @@ #define CONFIG_KM_DEF_ENV_CPU \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ CONFIG_KM_UPDATE_UBOOT \ + "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ "" #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 2466649b15c..569b574a2b9 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -420,6 +420,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "update=" \ "sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};\0" \ + "set_fdthigh=true\0" \ "" #define CONFIG_HW_ENV_SETTINGS \ -- cgit v1.3.1 From 9c134e189a95c976dab94d4f28444a5398627188 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Thu, 13 Feb 2014 16:43:00 +0100 Subject: arm/km: introduce kmsugp1 target KMSUGP1 is from a u-boot perspective (almost) identical to KMNUSA. The only difference is that the PCIe reset is connected to Kirkwood pin MPP7_PEX_RST_OUTn, we use a dedicated config flag KM_PCIE_RESET_MPP7. Such pin should theoretically be handled by the PCIe subsystem automatically, but this turned out not to be the case. So simply configure this PIN as a GPIO and issue a pulse manually. Signed-off-by: Gerlando Falauto Cc: Karlheinz Jerg Cc: Valentin Longchamp Cc: Holger Brunck Acked-by: Valentin Longchamp --- board/keymile/km_arm/fpga_config.c | 26 ++++++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 4 ++++ boards.cfg | 1 + include/configs/km_kirkwood.h | 12 ++++++++++-- 4 files changed, 41 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index cbfc7d21759..51a3cfe6478 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -189,6 +189,31 @@ int wait_for_fpga_config(void) return 0; } +#if defined(KM_PCIE_RESET_MPP7) + +#define KM_PEX_RST_GPIO_PIN 7 +int fpga_reset(void) +{ + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe reset through GPIO7: "); + /* apply PCIe reset via GPIO */ + kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0); + udelay(1000*10); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1); + + printf(" done\n"); + + return 0; +} + +#else + #define PRST1 0x4 #define PCIE_RST 0x10 #define TRAFFIC_RST 0x04 @@ -219,6 +244,7 @@ int fpga_reset(void) return 0; } +#endif /* the FPGA was configured, we configure the BOCO2 so that the EEPROM * is available from the Bobcat SPI bus */ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5f32e70f10a..35402c800bd 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, +#if defined(KM_PCIE_RESET_MPP7) + MPP7_GPO, +#else MPP7_PEX_RST_OUTn, +#endif #if defined(CONFIG_SYS_I2C_SOFT) MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ diff --git a/boards.cfg b/boards.cfg index a5165c8f53a..f6a74880b9f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -173,6 +173,7 @@ Active arm arm926ejs kirkwood keymile km_arm Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp +Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 2bd89b1e249..2cde1770cdc 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -45,11 +45,19 @@ #define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -/* KM_NUSA */ -#elif defined(CONFIG_KM_NUSA) +/* KM_NUSA / KM_SUGP1 */ +#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ + +# if defined(CONFIG_KM_NUSA) #define CONFIG_IDENT_STRING "\nKeymile NUSA" #define CONFIG_HOSTNAME kmnusa +# elif defined(CONFIG_KM_SUGP1) +#define CONFIG_IDENT_STRING "\nKeymile SUGP1" +#define CONFIG_HOSTNAME kmsugp1 +#define KM_PCIE_RESET_MPP7 +#endif + #undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg -- cgit v1.3.1 From ea4c7a8321427dd9d579fd449e32b1dcb066dab7 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Sat, 21 Dec 2013 12:50:08 +0530 Subject: am437x_epos_evm: add SPL API, QSPI, and serial flash support Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki --- board/ti/am43xx/mux.c | 11 +++++++++++ include/configs/am43xx_evm.h | 20 ++++++++++++++++++++ 2 files changed, 31 insertions(+) (limited to 'include') diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 810b1941db9..f96c56f8865 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -38,6 +38,16 @@ static struct module_pin_mux gpio0_22_pin_mux[] = { {-1}, }; +static struct module_pin_mux qspi_pin_mux[] = { + {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ + {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ + {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ + {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ + {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ + {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -50,6 +60,7 @@ void enable_board_pin_mux(void) if (board_is_gpevm()) configure_module_pin_mux(gpio0_22_pin_mux); + configure_module_pin_mux(qspi_pin_mux); } void enable_i2c0_pin_mux(void) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index f45deeb351c..bef46bd14fb 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -84,6 +84,26 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_TI_SPI_MMAP +#define CONFIG_QSPI_SEL_GPIO 48 +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* SPI SPL */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ -- cgit v1.3.1 From c74a94415cd5cea211004f520aa5710510392a0e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Jan 2014 09:51:25 +0100 Subject: zynq: Fix incorrect header name Zynq common configuration is placed in zynq-common.h not zynq_common.h. Signed-off-by: Michal Simek --- include/configs/zynq_zc70x.h | 2 +- include/configs/zynq_zed.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 673660e6596..de0e24129c2 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -2,7 +2,7 @@ * (C) Copyright 2013 Xilinx, Inc. * * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards - * See zynq_common.h for Zynq common configs + * See zynq-common.h for Zynq common configs * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 412dede5331..274140cb3fa 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -2,7 +2,7 @@ * (C) Copyright 2013 Xilinx, Inc. * * Configuration for Zynq Evaluation and Development Board - ZedBoard - * See zynq_common.h for Zynq common configs + * See zynq-common.h for Zynq common configs * * SPDX-License-Identifier: GPL-2.0+ */ -- cgit v1.3.1 From ae9f489977c802d5209b05a4d78fc59aa41f89c4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 20 Jan 2014 11:29:06 +0100 Subject: zynq: Extend kernel image size to 20MB Extend max kernel image size. Gunzip is checking this value. If kernel is larger, message below is shown. Uncompressing Kernel Image ... Error: inflate() returned -5 GUNZIP: uncompress, out-of-mem or overwrite error - must RESET board to recover Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 9b6db043b57..3ada295fe0d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -221,6 +221,9 @@ #define CONFIG_FIT_SIGNATURE #define CONFIG_RSA +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024) + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- cgit v1.3.1 From 427b2d4e5afe149b0da012322530a363d01058fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 20 Jan 2014 14:40:26 +0100 Subject: zynq: Enable tftp put command For saving content of memory via tftp to file. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 3ada295fe0d..bafa01b2e34 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -239,5 +239,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII +#define CONFIG_CMD_TFTPPUT #endif /* __CONFIG_ZYNQ_COMMON_H */ -- cgit v1.3.1 From bf83495040fcf273eba534f7c2c0cb2325d2240c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 19 Dec 2013 23:38:58 +0530 Subject: zynq: serial: Simplify serial driver initialization Define both serial uarts in the driver and return default uart based on board configuration. - Move baseaddresses to hardware.h - Define default baudrate and clock values Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynq/hardware.h | 2 ++ drivers/serial/serial_zynq.c | 34 ++++++++++++++++++------------- include/configs/zynq-common.h | 19 ++--------------- 3 files changed, 24 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 1fe044801cf..d0fba642839 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 +#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index ff28f3c8019..9a1ee00e9c3 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -10,6 +10,7 @@ #include #include #include +#include #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -33,13 +34,23 @@ struct uart_zynq { }; static struct uart_zynq *uart_zynq_ports[2] = { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 - [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, + [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, + [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, +}; + +#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE #endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 - [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +#endif + +#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0) +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif +#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1) +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 #endif -}; struct uart_zynq_params { u32 baudrate; @@ -47,14 +58,10 @@ struct uart_zynq_params { }; static struct uart_zynq_params uart_zynq_ports_param[2] = { -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, -#endif -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, -#endif }; /* Set up the baud rate in gd struct */ @@ -186,20 +193,19 @@ struct serial_device uart_zynq_serial1_device = __weak struct serial_device *default_serial_console(void) { +#if defined(CONFIG_ZYNQ_SERIAL_UART0) if (uart_zynq_ports[0]) return &uart_zynq_serial0_device; +#endif +#if defined(CONFIG_ZYNQ_SERIAL_UART1) if (uart_zynq_ports[1]) return &uart_zynq_serial1_device; - +#endif return NULL; } void zynq_serial_initalize(void) { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 serial_register(&uart_zynq_serial0_device); -#endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 serial_register(&uart_zynq_serial1_device); -#endif } diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bafa01b2e34..b5bf7acadf2 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -35,27 +35,12 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -/* Zynq Serial driver */ -#ifdef CONFIG_ZYNQ_SERIAL_UART0 -# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 -#endif - -#ifdef CONFIG_ZYNQ_SERIAL_UART1 -# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE -# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 -#endif - -#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) -# define CONFIG_ZYNQ_SERIAL -#endif - /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) # define CONFIG_ARM_DCC # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#else +# define CONFIG_ZYNQ_SERIAL #endif /* Ethernet driver */ -- cgit v1.3.1 From 23d5c738664918b1cb11cfffe5fbd79940d68c49 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 21 Nov 2013 13:38:53 -0800 Subject: common: Provide DIV_ROUND_CLOSEST macro Provide the DIV_ROUND_CLOSEST macro - taken from the Linux kernel - in common.h Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- include/common.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/common.h b/include/common.h index 221b7768c5b..ea3e5ed69f1 100644 --- a/include/common.h +++ b/include/common.h @@ -964,6 +964,22 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +/* + * Divide positive or negative dividend by positive divisor and round + * to closest integer. Result is undefined for negative divisors and + * for negative dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) + #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) -- cgit v1.3.1 From 6c3e61de3c9e6fbc283c16269f2e86f8fe0e0a6c Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 21 Nov 2013 13:38:54 -0800 Subject: zynq: Provide a framework to read clock frequencies Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/Makefile | 1 + arch/arm/cpu/armv7/zynq/clk.c | 638 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/zynq/cpu.c | 2 + arch/arm/include/asm/arch-zynq/clk.h | 29 ++ arch/arm/include/asm/arch-zynq/hardware.h | 32 +- include/configs/zynq-common.h | 1 + 6 files changed, 701 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/clk.c create mode 100644 arch/arm/include/asm/arch-zynq/clk.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index d382d49eb0f..33747899051 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -12,3 +12,4 @@ obj-y := timer.o obj-y += cpu.o obj-y += ddrc.o obj-y += slcr.o +obj-y += clk.o diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c new file mode 100644 index 00000000000..0891a23526a --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/clk.c @@ -0,0 +1,638 @@ +/* + * Copyright (C) 2013 Soren Brinkmann + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +/* Board oscillator frequency */ +#ifndef CONFIG_ZYNQ_PS_CLK_FREQ +# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL +#endif + +/* Register bitfield defines */ +#define PLLCTRL_FBDIV_MASK 0x7f000 +#define PLLCTRL_FBDIV_SHIFT 12 +#define PLLCTRL_BPFORCE_MASK (1 << 4) +#define PLLCTRL_PWRDWN_MASK 2 +#define PLLCTRL_PWRDWN_SHIFT 1 +#define PLLCTRL_RESET_MASK 1 +#define PLLCTRL_RESET_SHIFT 0 + +#define ZYNQ_CLK_MAXDIV 0x3f +#define CLK_CTRL_DIV1_SHIFT 20 +#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) +#define CLK_CTRL_DIV0_SHIFT 8 +#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) +#define CLK_CTRL_SRCSEL_SHIFT 4 +#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) + +#define CLK_CTRL_DIV2X_SHIFT 26 +#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT) +#define CLK_CTRL_DIV3X_SHIFT 20 +#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT) + +#define ZYNQ_CLKMUX_SEL_0 0 +#define ZYNQ_CLKMUX_SEL_1 1 +#define ZYNQ_CLKMUX_SEL_2 2 +#define ZYNQ_CLKMUX_SEL_3 3 + +DECLARE_GLOBAL_DATA_PTR; + +struct clk; + +/** + * struct clk_ops: + * @set_rate: Function pointer to set_rate() implementation + * @get_rate: Function pointer to get_rate() implementation + */ +struct clk_ops { + int (*set_rate)(struct clk *clk, unsigned long rate); + unsigned long (*get_rate)(struct clk *clk); +}; + +/** + * struct clk: + * @name: Clock name + * @frequency: Currenct frequency + * @parent: Parent clock + * @flags: Clock flags + * @reg: Clock control register + * @ops: Clock operations + */ +struct clk { + char *name; + unsigned long frequency; + enum zynq_clk parent; + unsigned int flags; + u32 *reg; + struct clk_ops ops; +}; +#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1 + +static struct clk clks[clk_max]; + +/** + * __zynq_clk_cpu_get_parent() - Decode clock multiplexer + * @srcsel: Mux select value + * Returns the clock identifier associated with the selected mux input. + */ +static int __zynq_clk_cpu_get_parent(unsigned int srcsel) +{ + unsigned int ret; + + switch (srcsel) { + case ZYNQ_CLKMUX_SEL_0: + case ZYNQ_CLKMUX_SEL_1: + ret = armpll_clk; + break; + case ZYNQ_CLKMUX_SEL_2: + ret = ddrpll_clk; + break; + case ZYNQ_CLKMUX_SEL_3: + ret = iopll_clk; + break; + default: + ret = armpll_clk; + break; + } + + return ret; +} + +/** + * ddr2x_get_rate() - Get clock rate of DDR2x clock + * @clk: Clock handle + * Returns the current clock rate of @clk. + */ +static unsigned long ddr2x_get_rate(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div); +} + +/** + * ddr3x_get_rate() - Get clock rate of DDR3x clock + * @clk: Clock handle + * Returns the current clock rate of @clk. + */ +static unsigned long ddr3x_get_rate(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div); +} + +static void init_ddr_clocks(void) +{ + u32 div0, div1; + unsigned long prate = zynq_clk_get_rate(ddrpll_clk); + u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); + + /* DDR2x */ + clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl; + clks[ddr2x_clk].parent = ddrpll_clk; + clks[ddr2x_clk].name = "ddr_2x"; + clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]); + clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate; + + /* DDR3x */ + clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl; + clks[ddr3x_clk].parent = ddrpll_clk; + clks[ddr3x_clk].name = "ddr_3x"; + clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]); + clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate; + + /* DCI */ + clk_ctrl = readl(&slcr_base->dci_clk_ctrl); + div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + clks[dci_clk].reg = &slcr_base->dci_clk_ctrl; + clks[dci_clk].parent = ddrpll_clk; + clks[dci_clk].frequency = DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST(prate, div0), div1); + clks[dci_clk].name = "dci"; +} + +static void init_cpu_clocks(void) +{ + int clk_621; + u32 reg, div, srcsel; + enum zynq_clk parent; + + reg = readl(&slcr_base->arm_clk_ctrl); + clk_621 = readl(&slcr_base->clk_621_true) & 1; + div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + parent = __zynq_clk_cpu_get_parent(srcsel); + + /* cpu clocks */ + clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_6or4x_clk].parent = parent; + clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST( + zynq_clk_get_rate(parent), div); + clks[cpu_6or4x_clk].name = "cpu_6or4x"; + + clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_3or2x_clk].parent = cpu_6or4x_clk; + clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2; + clks[cpu_3or2x_clk].name = "cpu_3or2x"; + + clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_2x_clk].parent = cpu_6or4x_clk; + clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / + (2 + clk_621); + clks[cpu_2x_clk].name = "cpu_2x"; + + clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_1x_clk].parent = cpu_6or4x_clk; + clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / + (4 + 2 * clk_621); + clks[cpu_1x_clk].name = "cpu_1x"; +} + +/** + * periph_calc_two_divs() - Calculate clock dividers + * @cur_rate: Current clock rate + * @tgt_rate: Target clock rate + * @prate: Parent clock rate + * @div0: First divider (output) + * @div1: Second divider (output) + * Returns the actual clock rate possible. + * + * Calculates clock dividers for clocks with two 6-bit dividers. + */ +static unsigned long periph_calc_two_divs(unsigned long cur_rate, + unsigned long tgt_rate, unsigned long prate, u32 *div0, + u32 *div1) +{ + long err, best_err = (long)(~0UL >> 1); + unsigned long rate, best_rate = 0; + u32 d0, d1; + + for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { + for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { + rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0), + d1); + err = abs(rate - tgt_rate); + + if (err < best_err) { + *div0 = d0; + *div1 = d1; + best_err = err; + best_rate = rate; + } + } + } + + return best_rate; +} + +/** + * zynq_clk_periph_set_rate() - Set clock rate + * @clk: Handle of the peripheral clock + * @rate: New clock rate + * Sets the clock frequency of @clk to @rate. Returns zero on success. + */ +static int zynq_clk_periph_set_rate(struct clk *clk, + unsigned long rate) +{ + u32 ctrl, div0 = 0, div1 = 0; + unsigned long prate, new_rate, cur_rate = clk->frequency; + + ctrl = readl(clk->reg); + prate = zynq_clk_get_rate(clk->parent); + ctrl &= ~CLK_CTRL_DIV0_MASK; + + if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) { + ctrl &= ~CLK_CTRL_DIV1_MASK; + new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0, + &div1); + ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; + } else { + div0 = DIV_ROUND_CLOSEST(prate, rate); + div0 &= ZYNQ_CLK_MAXDIV; + new_rate = DIV_ROUND_CLOSEST(rate, div0); + } + + /* write new divs to hardware */ + ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; + writel(ctrl, clk->reg); + + /* update frequency in clk framework */ + clk->frequency = new_rate; + + return 0; +} + +/** + * zynq_clk_periph_get_rate() - Get clock rate + * @clk: Handle of the peripheral clock + * Returns the current clock rate of @clk. + */ +static unsigned long zynq_clk_periph_get_rate(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + u32 div1 = 1; + + if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + + /* a register value of zero == division by 1 */ + if (!div0) + div0 = 1; + if (!div1) + div1 = 1; + + return + DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0), + div1); +} + +/** + * __zynq_clk_periph_get_parent() - Decode clock multiplexer + * @srcsel: Mux select value + * Returns the clock identifier associated with the selected mux input. + */ +static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel) +{ + switch (srcsel) { + case ZYNQ_CLKMUX_SEL_0: + case ZYNQ_CLKMUX_SEL_1: + return iopll_clk; + case ZYNQ_CLKMUX_SEL_2: + return armpll_clk; + case ZYNQ_CLKMUX_SEL_3: + return ddrpll_clk; + default: + return 0; + } +} + +/** + * zynq_clk_periph_get_parent() - Decode clock multiplexer + * @clk: Clock handle + * Returns the clock identifier associated with the selected mux input. + */ +static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + + return __zynq_clk_periph_get_parent(srcsel); +} + +/** + * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework + * @clk: Pointer to struct clk for the clock + * @ctrl: Clock control register + * @name: PLL name + * @two_divs: Indicates whether the clock features one or two dividers + */ +static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name, + bool two_divs) +{ + clk->name = name; + clk->reg = ctrl; + if (two_divs) + clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS; + clk->parent = zynq_clk_periph_get_parent(clk); + clk->frequency = zynq_clk_periph_get_rate(clk); + clk->ops.get_rate = zynq_clk_periph_get_rate; + clk->ops.set_rate = zynq_clk_periph_set_rate; + + return 0; +} + +static void init_periph_clocks(void) +{ + zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl, + "gem0", 1); + zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl, + "gem1", 1); + + zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl, + "smc", 0); + + zynq_clk_register_periph_clk(&clks[lqspi_clk], + &slcr_base->lqspi_clk_ctrl, "lqspi", 0); + + zynq_clk_register_periph_clk(&clks[sdio0_clk], + &slcr_base->sdio_clk_ctrl, "sdio0", 0); + zynq_clk_register_periph_clk(&clks[sdio1_clk], + &slcr_base->sdio_clk_ctrl, "sdio1", 0); + + zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl, + "spi0", 0); + zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl, + "spi1", 0); + + zynq_clk_register_periph_clk(&clks[uart0_clk], + &slcr_base->uart_clk_ctrl, "uart0", 0); + zynq_clk_register_periph_clk(&clks[uart1_clk], + &slcr_base->uart_clk_ctrl, "uart1", 0); + + zynq_clk_register_periph_clk(&clks[dbg_trc_clk], + &slcr_base->dbg_clk_ctrl, "dbg_trc", 0); + zynq_clk_register_periph_clk(&clks[dbg_apb_clk], + &slcr_base->dbg_clk_ctrl, "dbg_apb", 0); + + zynq_clk_register_periph_clk(&clks[pcap_clk], + &slcr_base->pcap_clk_ctrl, "pcap", 0); + + zynq_clk_register_periph_clk(&clks[fclk0_clk], + &slcr_base->fpga0_clk_ctrl, "fclk0", 1); + zynq_clk_register_periph_clk(&clks[fclk1_clk], + &slcr_base->fpga1_clk_ctrl, "fclk1", 1); + zynq_clk_register_periph_clk(&clks[fclk2_clk], + &slcr_base->fpga2_clk_ctrl, "fclk2", 1); + zynq_clk_register_periph_clk(&clks[fclk3_clk], + &slcr_base->fpga3_clk_ctrl, "fclk3", 1); +} + +/** + * zynq_clk_register_aper_clk() - Set up a APER clock with the framework + * @clk: Pointer to struct clk for the clock + * @ctrl: Clock control register + * @name: PLL name + */ +static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name) +{ + clk->name = name; + clk->reg = ctrl; + clk->parent = cpu_1x_clk; + clk->frequency = zynq_clk_get_rate(clk->parent); +} + +static void init_aper_clocks(void) +{ + zynq_clk_register_aper_clk(&clks[usb0_aper_clk], + &slcr_base->aper_clk_ctrl, "usb0_aper"); + zynq_clk_register_aper_clk(&clks[usb1_aper_clk], + &slcr_base->aper_clk_ctrl, "usb1_aper"); + + zynq_clk_register_aper_clk(&clks[gem0_aper_clk], + &slcr_base->aper_clk_ctrl, "gem0_aper"); + zynq_clk_register_aper_clk(&clks[gem1_aper_clk], + &slcr_base->aper_clk_ctrl, "gem1_aper"); + + zynq_clk_register_aper_clk(&clks[sdio0_aper_clk], + &slcr_base->aper_clk_ctrl, "sdio0_aper"); + zynq_clk_register_aper_clk(&clks[sdio1_aper_clk], + &slcr_base->aper_clk_ctrl, "sdio1_aper"); + + zynq_clk_register_aper_clk(&clks[spi0_aper_clk], + &slcr_base->aper_clk_ctrl, "spi0_aper"); + zynq_clk_register_aper_clk(&clks[spi1_aper_clk], + &slcr_base->aper_clk_ctrl, "spi1_aper"); + + zynq_clk_register_aper_clk(&clks[can0_aper_clk], + &slcr_base->aper_clk_ctrl, "can0_aper"); + zynq_clk_register_aper_clk(&clks[can1_aper_clk], + &slcr_base->aper_clk_ctrl, "can1_aper"); + + zynq_clk_register_aper_clk(&clks[i2c0_aper_clk], + &slcr_base->aper_clk_ctrl, "i2c0_aper"); + zynq_clk_register_aper_clk(&clks[i2c1_aper_clk], + &slcr_base->aper_clk_ctrl, "i2c1_aper"); + + zynq_clk_register_aper_clk(&clks[uart0_aper_clk], + &slcr_base->aper_clk_ctrl, "uart0_aper"); + zynq_clk_register_aper_clk(&clks[uart1_aper_clk], + &slcr_base->aper_clk_ctrl, "uart1_aper"); + + zynq_clk_register_aper_clk(&clks[gpio_aper_clk], + &slcr_base->aper_clk_ctrl, "gpio_aper"); + + zynq_clk_register_aper_clk(&clks[lqspi_aper_clk], + &slcr_base->aper_clk_ctrl, "lqspi_aper"); + + zynq_clk_register_aper_clk(&clks[smc_aper_clk], + &slcr_base->aper_clk_ctrl, "smc_aper"); +} + +/** + * __zynq_clk_pll_get_rate() - Get PLL rate + * @addr: Address of the PLL's control register + * Returns the current PLL output rate. + */ +static unsigned long __zynq_clk_pll_get_rate(u32 *addr) +{ + u32 reg, mul, bypass; + + reg = readl(addr); + bypass = reg & PLLCTRL_BPFORCE_MASK; + if (bypass) + mul = 1; + else + mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; + + return CONFIG_ZYNQ_PS_CLK_FREQ * mul; +} + +/** + * zynq_clk_pll_get_rate() - Get PLL rate + * @pll: Handle of the PLL + * Returns the current clock rate of @pll. + */ +static unsigned long zynq_clk_pll_get_rate(struct clk *pll) +{ + return __zynq_clk_pll_get_rate(pll->reg); +} + +/** + * zynq_clk_register_pll() - Set up a PLL with the framework + * @clk: Pointer to struct clk for the PLL + * @ctrl: PLL control register + * @name: PLL name + * @prate: PLL input clock rate + */ +static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name, + unsigned long prate) +{ + clk->name = name; + clk->reg = ctrl; + clk->frequency = zynq_clk_pll_get_rate(clk); + clk->ops.get_rate = zynq_clk_pll_get_rate; +} + +/** + * clkid_2_register() - Get clock control register + * @id: Clock identifier of one of the PLLs + * Returns the address of the requested PLL's control register. + */ +static u32 *clkid_2_register(enum zynq_clk id) +{ + switch (id) { + case armpll_clk: + return &slcr_base->arm_pll_ctrl; + case ddrpll_clk: + return &slcr_base->ddr_pll_ctrl; + case iopll_clk: + return &slcr_base->io_pll_ctrl; + default: + return &slcr_base->io_pll_ctrl; + } +} + +/* API */ +/** + * zynq_clk_early_init() - Early init for the clock framework + * + * This function is called from before relocation and sets up the CPU clock + * frequency in the global data struct. + */ +void zynq_clk_early_init(void) +{ + u32 reg = readl(&slcr_base->arm_clk_ctrl); + u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel); + u32 *pllreg = clkid_2_register(parent); + unsigned long prate = __zynq_clk_pll_get_rate(pllreg); + + if (!div) + div = 1; + + gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div); +} + +/** + * get_uart_clk() - Get UART input frequency + * @dev_index: UART ID + * Returns UART input clock frequency in Hz. + * + * Compared to zynq_clk_get_rate() this function is designed to work before + * relocation and can be called when the serial UART is set up. + */ +unsigned long get_uart_clk(int dev_index) +{ + u32 reg = readl(&slcr_base->uart_clk_ctrl); + u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel); + u32 *pllreg = clkid_2_register(parent); + unsigned long prate = __zynq_clk_pll_get_rate(pllreg); + + if (!div) + div = 1; + + return DIV_ROUND_CLOSEST(prate, div); +} + +/** + * set_cpu_clk_info() - Initialize clock framework + * Always returns zero. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl, + "armpll", CONFIG_ZYNQ_PS_CLK_FREQ); + zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl, + "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ); + zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl, + "iopll", CONFIG_ZYNQ_PS_CLK_FREQ); + + init_ddr_clocks(); + init_cpu_clocks(); + init_periph_clocks(); + init_aper_clocks(); + + return 0; +} + +/** + * zynq_clk_get_rate() - Get clock rate + * @clk: Clock identifier + * Returns the current clock rate of @clk on success or zero for an invalid + * clock id. + */ +unsigned long zynq_clk_get_rate(enum zynq_clk clk) +{ + if (clk < 0 || clk >= clk_max) + return 0; + + return clks[clk].frequency; +} + +/** + * zynq_clk_set_rate() - Set clock rate + * @clk: Clock identifier + * @rate: Requested clock rate + * Passes on the return value from the clock's set_rate() function or negative + * errno. + */ +int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate) +{ + if (clk < 0 || clk >= clk_max) + return -ENODEV; + + if (clks[clk].ops.set_rate) + return clks[clk].ops.set_rate(&clks[clk], rate); + + return -ENXIO; +} + +/** + * zynq_clk_get_name() - Get clock name + * @clk: Clock identifier + * Returns the name of @clk. + */ +const char *zynq_clk_get_name(enum zynq_clk clk) +{ + return clks[clk].name; +} diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index c771759ab80..5d505dd4864 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include @@ -35,6 +36,7 @@ int arch_cpu_init(void) writel(0xC, &slcr_base->ddr_urgent); #endif + zynq_clk_early_init(); zynq_slcr_lock(); return 0; diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h new file mode 100644 index 00000000000..250c5bc07b1 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/clk.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_CLK_H_ +#define _ZYNQ_CLK_H_ + +enum zynq_clk { + armpll_clk, ddrpll_clk, iopll_clk, + cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, + ddr2x_clk, ddr3x_clk, dci_clk, + lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, + fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, + sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, + usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, + sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, + can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, + uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, + smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; + +void zynq_clk_early_init(void); +int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); +unsigned long zynq_clk_get_rate(enum zynq_clk clk); +const char *zynq_clk_get_name(enum zynq_clk clk); +unsigned long get_uart_clk(int dev_id); + +#endif diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index d0fba642839..39184da40ea 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -34,12 +34,40 @@ struct slcr_regs { u32 scl; /* 0x0 */ u32 slcr_lock; /* 0x4 */ u32 slcr_unlock; /* 0x8 */ - u32 reserved0[75]; + u32 reserved0_1[61]; + u32 arm_pll_ctrl; /* 0x100 */ + u32 ddr_pll_ctrl; /* 0x104 */ + u32 io_pll_ctrl; /* 0x108 */ + u32 reserved0_2[5]; + u32 arm_clk_ctrl; /* 0x120 */ + u32 ddr_clk_ctrl; /* 0x124 */ + u32 dci_clk_ctrl; /* 0x128 */ + u32 aper_clk_ctrl; /* 0x12c */ + u32 reserved0_3[2]; u32 gem0_rclk_ctrl; /* 0x138 */ u32 gem1_rclk_ctrl; /* 0x13c */ u32 gem0_clk_ctrl; /* 0x140 */ u32 gem1_clk_ctrl; /* 0x144 */ - u32 reserved1[46]; + u32 smc_clk_ctrl; /* 0x148 */ + u32 lqspi_clk_ctrl; /* 0x14c */ + u32 sdio_clk_ctrl; /* 0x150 */ + u32 uart_clk_ctrl; /* 0x154 */ + u32 spi_clk_ctrl; /* 0x158 */ + u32 can_clk_ctrl; /* 0x15c */ + u32 can_mioclk_ctrl; /* 0x160 */ + u32 dbg_clk_ctrl; /* 0x164 */ + u32 pcap_clk_ctrl; /* 0x168 */ + u32 reserved0_4[1]; + u32 fpga0_clk_ctrl; /* 0x170 */ + u32 reserved0_5[3]; + u32 fpga1_clk_ctrl; /* 0x180 */ + u32 reserved0_6[3]; + u32 fpga2_clk_ctrl; /* 0x190 */ + u32 reserved0_7[3]; + u32 fpga3_clk_ctrl; /* 0x1a0 */ + u32 reserved0_8[8]; + u32 clk_621_true; /* 0x1c4 */ + u32 reserved1[14]; u32 pss_rst_ctrl; /* 0x200 */ u32 reserved2[15]; u32 fpga_rst_ctrl; /* 0x240 */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b5bf7acadf2..406ccaf9df8 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -163,6 +163,7 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_LONGHELP +#define CONFIG_CLOCKS #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ -- cgit v1.3.1 From d6c9bbaad194b48e799ed84df67b629424a56508 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 21 Nov 2013 13:39:03 -0800 Subject: zynq: Implement dump clock command Enable and implement dump clock command which shows soc frequencies. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/clk.c | 21 +++++++++++++++++++++ include/configs/zynq-common.h | 1 + 2 files changed, 22 insertions(+) (limited to 'include') diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c index 0891a23526a..43071111c4d 100644 --- a/arch/arm/cpu/armv7/zynq/clk.c +++ b/arch/arm/cpu/armv7/zynq/clk.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -636,3 +637,23 @@ const char *zynq_clk_get_name(enum zynq_clk clk) { return clks[clk].name; } + +/** + * soc_clk_dump() - Print clock frequencies + * Returns zero on success + * + * Implementation for the clk dump command. + */ +int soc_clk_dump(void) +{ + int i; + + printf("clk\t\tfrequency\n"); + for (i = 0; i < clk_max; i++) { + const char *name = zynq_clk_get_name(i); + if (name) + printf("%10s%20lu\n", name, zynq_clk_get_rate(i)); + } + + return 0; +} diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 406ccaf9df8..d6dc74581e4 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -164,6 +164,7 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS +#define CONFIG_CMD_CLK #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ -- cgit v1.3.1 From d7e269cfbdd5fe0bbc0961bcf89845484bf28de7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 14 Jan 2014 14:21:52 +0100 Subject: zynq: Add support for U-BOOT SPL SPL is using ps7_init.c/h files which are generated from design tools which have to be copied to boards/xilinx/zynq folder before compilation. BSS section is moved to SDRAM because fat support requires more space than SRAM size. Added: - MMC and QSPI support - Boot OS directly from SPL - Enable SPL command Signed-off-by: Michal Simek Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/zynq/Makefile | 1 + arch/arm/cpu/armv7/zynq/cpu.c | 4 +- arch/arm/cpu/armv7/zynq/spl.c | 69 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/zynq/u-boot-spl.lds | 61 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynq/spl.h | 18 ++++++++ board/xilinx/zynq/Makefile | 1 + board/xilinx/zynq/ps7_init.c | 12 ++++++ include/configs/zynq-common.h | 77 ++++++++++++++++++++++++++++++++++ 8 files changed, 241 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/spl.c create mode 100644 arch/arm/cpu/armv7/zynq/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-zynq/spl.h create mode 100644 board/xilinx/zynq/ps7_init.c (limited to 'include') diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index 33747899051..3363a3c71b9 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -13,3 +13,4 @@ obj-y += cpu.o obj-y += ddrc.o obj-y += slcr.o obj-y += clk.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 5d505dd4864..7626b5c1a3b 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -17,7 +17,7 @@ void lowlevel_init(void) int arch_cpu_init(void) { zynq_slcr_unlock(); - +#ifndef CONFIG_SPL_BUILD /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); @@ -35,7 +35,7 @@ int arch_cpu_init(void) /* Urgent write, ports S2/S3 */ writel(0xC, &slcr_base->ddr_urgent); #endif - +#endif zynq_clk_early_init(); zynq_slcr_lock(); diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c new file mode 100644 index 00000000000..fcad762c030 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong dummy) +{ + ps7_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Set global data pointer. */ + gd = &gdata; + + preloader_console_init(); + arch_cpu_init(); + board_init_r(NULL, 0); +} + +u32 spl_boot_device(void) +{ + u32 mode; + + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { +#ifdef CONFIG_SPL_SPI_SUPPORT + case ZYNQ_BM_QSPI: + puts("qspi boot\n"); + mode = BOOT_DEVICE_SPI; + break; +#endif +#ifdef CONFIG_SPL_MMC_SUPPORT + case ZYNQ_BM_SD: + puts("mmc boot\n"); + mode = BOOT_DEVICE_MMC1; + break; +#endif + default: + puts("Unsupported boot mode selected\n"); + hang(); + } + + return mode; +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_FAT; +} +#endif + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* boot linux */ + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds new file mode 100644 index 00000000000..0c4501e5c77 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2014 Xilinx, Inc. Michal Simek + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text*) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } > .sram + + . = ALIGN(4); + .data : { + *(.data*) + } > .sram + + . = ALIGN(4); + + . = .; + + __image_copy_end = .; + + _end = .; + + /* Move BSS section to RAM because of FAT */ + .bss (NOLOAD) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/arch-zynq/spl.h b/arch/arm/include/asm/arch-zynq/spl.h new file mode 100644 index 00000000000..5789d28bb3e --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/spl.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +extern void ps7_init(void); + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_RAM 1 +#define BOOT_DEVICE_SPI 2 +#define BOOT_DEVICE_MMC1 3 +#define BOOT_DEVICE_MMC2 4 +#define BOOT_DEVICE_MMC2_2 5 + +#endif diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 6301a8c1496..3f19a1cd8b2 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -6,3 +6,4 @@ # obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += ps7_init.o diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c new file mode 100644 index 00000000000..c47da09b9e8 --- /dev/null +++ b/board/xilinx/zynq/ps7_init.c @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +__weak void ps7_init(void) +{ + puts("Please copy ps7_init.c/h from hw project\n"); +} diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d6dc74581e4..c7eee0abe5b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -228,4 +228,81 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_TFTPPUT +/* SPL part */ +#define CONFIG_SPL +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" + +/* Disable dcache for SPL just for sure */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_FPGA +#endif + +/* MMC support */ +#ifdef CONFIG_ZYNQ_SDHCI0 +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +/* Address in RAM where the parameters must be copied by SPL. */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 + +#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "system.dtb" +#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" + +/* Not using MMC raw mode - just for compilation purpose */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 + +/* qspi mode is working fine */ +#ifdef CONFIG_ZYNQ_QSPI +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#define CONFIG_SPL_SPI_CS 0 +#endif + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SPL_TEXT_BASE 0x0 + +/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ +#define CONFIG_SPL_MAX_SIZE 0x30000 + +/* The highest 64k OCM address */ +#define OCM_HIGH_ADDR 0xffff0000 + +/* Just define any reasonable size */ +#define CONFIG_SPL_STACK_SIZE 0x1000 + +/* SPL stack position - and stack goes down */ +#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE) + +/* On the top of OCM space */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000 + +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #endif /* __CONFIG_ZYNQ_COMMON_H */ -- cgit v1.3.1 From bd6fb31fab1523ecac1aaf7af574868a26169dc6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Feb 2014 13:20:59 -0700 Subject: fs: fix generic save command implementation Fix a few issues with the generic "save" shell command, and fs_write() function. 1) fstypes[].write wasn't filled in for some file-systems, and isn't checked when used, which could cause crashes/... if executing save on e.g. fat/ext filesystems. 2) fs_write() requires the length argument to be non-zero, since it needs to know exactly how many bytes to write. Adjust the comments and code according to this. 3) fs_write() wasn't prototyped in like other generic functions; other code should be able to call this directly rather than invoking the "save" shell command. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- fs/fs.c | 9 +++------ include/fs.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/fs/fs.c b/fs/fs.c index be1855d1291..9c2ef6b6597 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -75,6 +75,7 @@ static struct fstype_info fstypes[] = { .close = fat_close, .ls = file_fat_ls, .read = fat_read_file, + .write = fs_write_unsupported, }, #endif #ifdef CONFIG_FS_EXT4 @@ -84,6 +85,7 @@ static struct fstype_info fstypes[] = { .close = ext4fs_close, .ls = ext4fs_ls, .read = ext4_read_file, + .write = fs_write_unsupported, }, #endif #ifdef CONFIG_SANDBOX @@ -212,16 +214,11 @@ int fs_write(const char *filename, ulong addr, int offset, int len) void *buf; int ret; - /* - * We don't actually know how many bytes are being read, since len==0 - * means read the whole file. - */ buf = map_sysmem(addr, len); ret = info->write(filename, buf, offset, len); unmap_sysmem(buf); - /* If we requested a specific number of bytes, check we got it */ - if (ret >= 0 && len && ret != len) { + if (ret >= 0 && ret != len) { printf("** Unable to write file %s **\n", filename); ret = -1; } diff --git a/include/fs.h b/include/fs.h index 7d9403ed875..97b0094e954 100644 --- a/include/fs.h +++ b/include/fs.h @@ -54,6 +54,16 @@ int fs_ls(const char *dirname); */ int fs_read(const char *filename, ulong addr, int offset, int len); +/* + * Write file "filename" to the partition previously set by fs_set_blk_dev(), + * from address "addr", starting at byte offset "offset", and writing "len" + * bytes. "offset" may be 0 to write to the start of the file. Note that not + * all filesystem types support offset!=0. + * + * Returns number of bytes read on success. Returns <= 0 on error. + */ +int fs_write(const char *filename, ulong addr, int offset, int len); + /* * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. -- cgit v1.3.1 From 6152916a95af299e5b3061bbd43418e2b73295d0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Feb 2014 13:21:00 -0700 Subject: fs: implement infrastructure for an 'exists' function This could be used in scripts such as: if test -e mmc 0:1 /boot/boot.scr; then load mmc 0:1 ${scriptaddr} /boot/boot.scr source ${scriptaddr} fi rather than: if load mmc 0:1 ${scriptaddr} /boot/boot.scr; then source ${scriptaddr} fi This prevents errors being printed by attempts to load non-existent files, which can be important when checking for a large set of files, such as /boot/boot.scr.uimg, /boot/boot.scr, /boot/extlinux.conf, /boot.scr.uimg, /boot.scr, /extlinux.conf. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- fs/fs.c | 32 ++++++++++++++++++++++++++++++++ include/fs.h | 9 +++++++++ 2 files changed, 41 insertions(+) (limited to 'include') diff --git a/fs/fs.c b/fs/fs.c index 9c2ef6b6597..8fe2403a46a 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -41,6 +41,11 @@ static inline int fs_ls_unsupported(const char *dirname) return -1; } +static inline int fs_exists_unsupported(const char *filename) +{ + return 0; +} + static inline int fs_read_unsupported(const char *filename, void *buf, int offset, int len) { @@ -62,6 +67,7 @@ struct fstype_info { int (*probe)(block_dev_desc_t *fs_dev_desc, disk_partition_t *fs_partition); int (*ls)(const char *dirname); + int (*exists)(const char *filename); int (*read)(const char *filename, void *buf, int offset, int len); int (*write)(const char *filename, void *buf, int offset, int len); void (*close)(void); @@ -74,6 +80,7 @@ static struct fstype_info fstypes[] = { .probe = fat_set_blk_dev, .close = fat_close, .ls = file_fat_ls, + .exists = fs_exists_unsupported, .read = fat_read_file, .write = fs_write_unsupported, }, @@ -84,6 +91,7 @@ static struct fstype_info fstypes[] = { .probe = ext4fs_probe, .close = ext4fs_close, .ls = ext4fs_ls, + .exists = fs_exists_unsupported, .read = ext4_read_file, .write = fs_write_unsupported, }, @@ -94,6 +102,7 @@ static struct fstype_info fstypes[] = { .probe = sandbox_fs_set_blk_dev, .close = sandbox_fs_close, .ls = sandbox_fs_ls, + .exists = fs_exists_unsupported, .read = fs_read_sandbox, .write = fs_write_sandbox, }, @@ -103,6 +112,7 @@ static struct fstype_info fstypes[] = { .probe = fs_probe_unsupported, .close = fs_close_unsupported, .ls = fs_ls_unsupported, + .exists = fs_exists_unsupported, .read = fs_read_unsupported, .write = fs_write_unsupported, }, @@ -184,6 +194,19 @@ int fs_ls(const char *dirname) return ret; } +int fs_exists(const char *filename) +{ + int ret; + + struct fstype_info *info = fs_get_info(fs_type); + + ret = info->exists(filename); + + fs_close(); + + return ret; +} + int fs_read(const char *filename, ulong addr, int offset, int len) { struct fstype_info *info = fs_get_info(fs_type); @@ -309,6 +332,15 @@ int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], return 0; } +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype) +{ + if (fs_set_blk_dev(dev_type, dev_part, fstype)) + return 0; + + return fs_exists(file); +} + int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype) { diff --git a/include/fs.h b/include/fs.h index 97b0094e954..26de0539f7d 100644 --- a/include/fs.h +++ b/include/fs.h @@ -43,6 +43,13 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype); */ int fs_ls(const char *dirname); +/* + * Determine whether a file exists + * + * Returns 1 if the file exists, 0 if it doesn't exist. + */ +int fs_exists(const char *filename); + /* * Read file "filename" from the partition previously set by fs_set_blk_dev(), * to address "addr", starting at byte offset "offset", and reading "len" @@ -72,6 +79,8 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype); int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); -- cgit v1.3.1 From 0a30aa1e7e4e194ecc04c5970267bd6493db8eaf Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Feb 2014 13:21:07 -0700 Subject: sandbox: implement exists() function This hooks into the generic "file exists" support added in an earlier patch, and provides an implementation for the sandbox test environment. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- fs/fs.c | 2 +- fs/sandbox/sandboxfs.c | 8 ++++++++ include/sandboxfs.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/fs/fs.c b/fs/fs.c index aaa6732a879..2e60f57bc45 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -114,7 +114,7 @@ static struct fstype_info fstypes[] = { .probe = sandbox_fs_set_blk_dev, .close = sandbox_fs_close, .ls = sandbox_fs_ls, - .exists = fs_exists_unsupported, + .exists = sandbox_fs_exists, .read = fs_read_sandbox, .write = fs_write_sandbox, }, diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index dd028da8e32..85079788c99 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -72,6 +72,14 @@ int sandbox_fs_ls(const char *dirname) return 0; } +int sandbox_fs_exists(const char *filename) +{ + ssize_t sz; + + sz = os_get_filesize(filename); + return sz >= 0; +} + void sandbox_fs_close(void) { } diff --git a/include/sandboxfs.h b/include/sandboxfs.h index 8ea8cb7e2e6..a51ad13044e 100644 --- a/include/sandboxfs.h +++ b/include/sandboxfs.h @@ -25,6 +25,7 @@ long sandbox_fs_read_at(const char *filename, unsigned long pos, void sandbox_fs_close(void); int sandbox_fs_ls(const char *dirname); +int sandbox_fs_exists(const char *filename); int fs_read_sandbox(const char *filename, void *buf, int offset, int len); int fs_write_sandbox(const char *filename, void *buf, int offset, int len); -- cgit v1.3.1 From 89ba42d18303d06d49ca14de2d46c82bbdcad06c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Feb 2014 13:21:08 -0700 Subject: sandbox: enable CONFIG_CMD_FS_GENERIC Since the generic ls command no longer segfaults sandbox, enable it. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- include/configs/sandbox.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index a6d55822b82..e77d06bcd3e 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -42,6 +42,7 @@ #define CONFIG_CMD_PART #define CONFIG_DOS_PARTITION #define CONFIG_HOST_MAX_DEVICES 4 +#define CONFIG_CMD_FS_GENERIC #define CONFIG_SYS_VSNPRINTF -- cgit v1.3.1 From 55af5c9313607f3b6acba2fd915b263ef6a61dd4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Feb 2014 13:21:09 -0700 Subject: ext4: implement exists() for ext4fs This hooks into the generic "file exists" support added in an earlier patch, and provides an implementation for the ext4 filesystem. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- fs/ext4/ext4fs.c | 8 ++++++++ fs/fs.c | 2 +- include/ext4fs.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 735b2564175..417ce7b63bf 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -174,6 +174,14 @@ int ext4fs_ls(const char *dirname) return 0; } +int ext4fs_exists(const char *filename) +{ + int file_len; + + file_len = ext4fs_open(filename); + return file_len >= 0; +} + int ext4fs_read(char *buf, unsigned len) { if (ext4fs_root == NULL || ext4fs_file == NULL) diff --git a/fs/fs.c b/fs/fs.c index 2e60f57bc45..4e9b162d49f 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -102,7 +102,7 @@ static struct fstype_info fstypes[] = { .probe = ext4fs_probe, .close = ext4fs_close, .ls = ext4fs_ls, - .exists = fs_exists_unsupported, + .exists = ext4fs_exists, .read = ext4_read_file, .write = fs_write_unsupported, }, diff --git a/include/ext4fs.h b/include/ext4fs.h index 24293803966..aacb147de24 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -134,6 +134,7 @@ int ext4fs_read(char *buf, unsigned len); int ext4fs_mount(unsigned part_length); void ext4fs_close(void); int ext4fs_ls(const char *dirname); +int ext4fs_exists(const char *filename); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); -- cgit v1.3.1 From b7b5f3195fa5a31ab1505e0c87054dc6dc71627b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Feb 2014 13:21:10 -0700 Subject: fat: implement exists() for FAT fs This hooks into the generic "file exists" support added in an earlier patch, and provides an implementation for the FAT filesystem. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- fs/fat/fat.c | 18 ++++++++++++++---- fs/fs.c | 2 +- include/fat.h | 1 + 3 files changed, 16 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/fs/fat/fat.c b/fs/fat/fat.c index b41d62e3c38..54f42eae0d0 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -808,7 +808,7 @@ __u8 do_fat_read_at_block[MAX_CLUSTSIZE] long do_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize, int dols) + unsigned long maxsize, int dols, int dogetsize) { char fnamecopy[2048]; boot_sector bs; @@ -1152,7 +1152,10 @@ rootdir_done: subname = nextname; } - ret = get_contents(mydata, dentptr, pos, buffer, maxsize); + if (dogetsize) + ret = FAT2CPU32(dentptr->size); + else + ret = get_contents(mydata, dentptr, pos, buffer, maxsize); debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret); exit: @@ -1163,7 +1166,7 @@ exit: long do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols) { - return do_fat_read_at(filename, 0, buffer, maxsize, dols); + return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0); } int file_fat_detectfs(void) @@ -1233,11 +1236,18 @@ int file_fat_ls(const char *dir) return do_fat_read(dir, NULL, 0, LS_YES); } +int fat_exists(const char *filename) +{ + int sz; + sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1); + return sz >= 0; +} + long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, unsigned long maxsize) { printf("reading %s\n", filename); - return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO); + return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0); } long file_fat_read(const char *filename, void *buffer, unsigned long maxsize) diff --git a/fs/fs.c b/fs/fs.c index 4e9b162d49f..79d432d58fe 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -90,7 +90,7 @@ static struct fstype_info fstypes[] = { .probe = fat_set_blk_dev, .close = fat_close, .ls = file_fat_ls, - .exists = fs_exists_unsupported, + .exists = fat_exists, .read = fat_read_file, .write = fs_write_unsupported, }, diff --git a/include/fat.h b/include/fat.h index 2c951e7d79c..c8eb7ccd290 100644 --- a/include/fat.h +++ b/include/fat.h @@ -188,6 +188,7 @@ file_read_func file_fat_read; int file_cd(const char *path); int file_fat_detectfs(void); int file_fat_ls(const char *dir); +int fat_exists(const char *filename); long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, unsigned long maxsize); long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); -- cgit v1.3.1 From 0a4bce32d6ad65ffd1eb23533d66dfe2184c0eb1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 28 Jan 2014 18:06:12 +0900 Subject: mini2440.h: Delete remainder of dead board Commit af5b9b1f removed mini2440 board support, but missed to delete include/configs/mini2440.h. Signed-off-by: Masahiro Yamada --- include/configs/mini2440.h | 170 --------------------------------------------- 1 file changed, 170 deletions(-) delete mode 100644 include/configs/mini2440.h (limited to 'include') diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h deleted file mode 100644 index 5e9e98d2fc2..00000000000 --- a/include/configs/mini2440.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * David Mueller - * - * (C) Copyright 2009-2010 - * Michel Pollet - * - * (C) Copyright 2012 - * Gabriel Huau - * - * Configuation settings for the MINI2440 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_S3C2440_GPIO - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ -#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ -#define CONFIG_MINI2440 /* on a MIN2440 Board */ - -#define MACH_TYPE_MINI2440 1999 -#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 - -/* - * We don't use lowlevel_init - */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F - -/* - * input clock of PLL - */ -/* MINI2440 has 12.0000MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_DM9000 -#define CONFIG_DRIVER_DM9000_NO_EEPROM -#define CONFIG_DM9000_BASE 0x20000300 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 - -/* - * allow to overwrite serial and ethaddr - */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES - -/* - * Miscellaneous configurable options - */ -#define CONFIG_LONGHELP -#define CONFIG_SYS_PROMPT "MINI2440 => " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x30000000 -#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x32000000 - -/* boot parameters address */ -#define CONFIG_BOOT_PARAM_ADDR 0x30000100 - -/* - * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need - * it to wrap 100 times (total 1562500) to get 1 sec. - */ -#define CONFIG_SYS_HZ 1562500 - -/* - * valid baudrates - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BAUDRATE 115200 - -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 -#define CONFIG_SYS_FLASH_BASE 0x0 - -/* - * Stack should be on the SRAM because - * DRAM is not init - */ -#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) - -/* - * NOR FLASH organization - * Now uses the standard CFI interface - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_MONITOR_BASE 0x0 -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* 512 * 4096 sectors, or 32 * 64k blocks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_FLASH_SHOW_PROGRESS 1 - -/* - * Config for NOR flash - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_MY_ENV_OFFSET 0x40000 -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) -/* 16k Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 - -/* ATAG configuration */ -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From df2f6c962134b4263e8726e56e1996da746ae4a8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 28 Jan 2014 18:08:13 +0900 Subject: config: remove platform CONFIG_SYS_HZ definition part 3 This commit removes platform CONFIG_SYS_HZ definition for the remainders of part1 (commit cdb23792) and part2 (commit f232950f). Signed-off-by: Masahiro Yamada Cc: Rob Herring --- board/fads/fads.h | 2 -- include/configs/T1040QDS.h | 1 - include/configs/T1040RDB.h | 1 - include/configs/T1042RDB_PI.h | 1 - include/configs/T2080QDS.h | 1 - include/configs/apf27.h | 5 ----- include/configs/balloon3.h | 1 - include/configs/corvus.h | 1 - include/configs/hummingboard.h | 1 - include/configs/koelsch.h | 1 - include/configs/lager.h | 1 - include/configs/palmld.h | 1 - include/configs/palmtc.h | 1 - include/configs/scb9328.h | 1 - include/configs/taurus.h | 1 - include/configs/udoo.h | 1 - include/configs/usb_a9263.h | 1 - include/configs/zipitz2.h | 1 - 18 files changed, 23 deletions(-) (limited to 'include') diff --git a/board/fads/fads.h b/board/fads/fads.h index cf6c928dc73..fa49080fb73 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -127,8 +127,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 75ea125f539..da6e76002e3 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -669,7 +669,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 7cfda50c8cd..fd010c057c3 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -596,7 +596,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index ed9ca8a3e19..6d07805ffd0 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -604,7 +604,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index 9bd0fe23820..9448ec8c45d 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -680,7 +680,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 1193013ea07..b10c48c20e3 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -355,11 +355,6 @@ #define CONFIG_SYS_RTC_BUS_NUM 0 #endif /* CONFIG_CMD_DATE */ -/* - * Clocks - */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - /* * PLL * diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index b41a823600d..5228ba6ef70 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -84,7 +84,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 11ba4cffc44..959e188d9ad 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -33,7 +33,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91FAMILY diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h index 4055af55bf5..d36d16e6e3e 100644 --- a/include/configs/hummingboard.h +++ b/include/configs/hummingboard.h @@ -190,7 +190,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index cc3c7a8e6a9..964d0dcb4b6 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -171,7 +171,6 @@ #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 /* i2c */ #define CONFIG_CMD_I2C diff --git a/include/configs/lager.h b/include/configs/lager.h index b6c1954a949..32a2655d762 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -196,6 +196,5 @@ #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __LAGER_H */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 2a9fd22dd6b..9480d8daf2f 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -115,7 +115,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index de254076f23..8abce1b425f 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -117,7 +117,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ /* diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index c0048aca78a..e6d272dd1f5 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -69,7 +69,6 @@ #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0x08F00000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index c98002317fe..20d4cee011f 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -37,7 +37,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ -#define CONFIG_SYS_HZ 1000 /* Misc CPU related */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 614e1fe3b5e..28e20b9092a 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -199,7 +199,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index c4d04dec386..3c54870783d 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -20,7 +20,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_HZ 1000 #define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index e38fa89fdac..41a7c99edcf 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -138,7 +138,6 @@ unsigned char zipitz2_spi_read(void); * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* -- cgit v1.3.1 From 95f706271089088cd1359e422d15300009f2b7c6 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 29 Jan 2014 16:29:16 +0900 Subject: fdt: rename IMAAGE_OF_BOARD_SETUP to IMAGE_OF_BOARD_SETUP Signed-off-by: Masahiro Yamada Acked-by: Simon Glass --- common/image-fdt.c | 2 +- include/image.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/common/image-fdt.c b/common/image-fdt.c index 6f9ce7d37c2..a54a919a5b3 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -463,7 +463,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, return -1; } arch_fixup_memory_node(blob); - if (IMAAGE_OF_BOARD_SETUP) + if (IMAGE_OF_BOARD_SETUP) ft_board_setup(blob, gd->bd); fdt_fixup_ethernet(blob); diff --git a/include/image.h b/include/image.h index 3ba8c2ea304..6afd57bafdd 100644 --- a/include/image.h +++ b/include/image.h @@ -99,9 +99,9 @@ struct lmb; #endif #ifdef CONFIG_OF_BOARD_SETUP -# define IMAAGE_OF_BOARD_SETUP 1 +# define IMAGE_OF_BOARD_SETUP 1 #else -# define IMAAGE_OF_BOARD_SETUP 0 +# define IMAGE_OF_BOARD_SETUP 0 #endif /* -- cgit v1.3.1 From fff40a7e02092eee11970e7001c8560df419cac1 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 3 Feb 2014 06:59:01 -0600 Subject: common: spl: Add spl sata boot support Add spl_sata to read a fat partition from a bootable SATA drive. Signed-off-by: Dan Murphy Reviewed-by: Roger Quadros --- common/Makefile | 3 +++ common/cmd_scsi.c | 2 ++ common/spl/Makefile | 1 + common/spl/spl.c | 5 +++++ common/spl/spl_sata.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ include/spl.h | 3 +++ spl/Makefile | 1 + 7 files changed, 64 insertions(+) create mode 100644 common/spl/spl_sata.c (limited to 'include') diff --git a/common/Makefile b/common/Makefile index a83246ee27b..2fe14ccc41b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -202,6 +202,9 @@ ifdef CONFIG_SPL_USB_HOST_SUPPORT obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif +ifdef CONFIG_SPL_SATA_SUPPORT +obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o +endif ifneq ($(CONFIG_SPL_NET_SUPPORT),y) obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 7b97dc9332b..b3f7687aee6 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -168,7 +168,9 @@ removable: scsi_curr_dev = -1; printf("Found %d device(s).\n", scsi_max_devs); +#ifndef CONFIG_SPL_BUILD setenv_ulong("scsidevs", scsi_max_devs); +#endif } int scsi_get_disk_count(void) diff --git a/common/spl/Makefile b/common/spl/Makefile index 65a1484fc4e..64569c2cc6d 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -18,4 +18,5 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o +obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o endif diff --git a/common/spl/spl.c b/common/spl/spl.c index 0645cee789f..774fdad2523 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -209,6 +209,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) case BOOT_DEVICE_USB: spl_usb_load_image(); break; +#endif +#ifdef CONFIG_SPL_SATA_SUPPORT + case BOOT_DEVICE_SATA: + spl_sata_load_image(); + break; #endif default: debug("SPL: Un-supported Boot Device\n"); diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c new file mode 100644 index 00000000000..2e7adca0ca6 --- /dev/null +++ b/common/spl/spl_sata.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2013 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived work from spl_usb.c + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_sata_load_image(void) +{ + int err; + block_dev_desc_t *stor_dev; + + err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: sata init failed: err - %d\n", err); +#endif + hang(); + } else { + /* try to recognize storage devices immediately */ + stor_dev = scsi_get_dev(0); + } + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION, + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + if (err) { + puts("Error loading sata device\n"); + hang(); + } +} diff --git a/include/spl.h b/include/spl.h index dad00c0075d..a7e41da7fd4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -65,6 +65,9 @@ void spl_net_load_image(const char *device); /* USB SPL functions */ void spl_usb_load_image(void); +/* SATA SPL functions */ +void spl_sata_load_image(void); + /* SPL FAT image functions */ int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename); int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition); diff --git a/spl/Makefile b/spl/Makefile index 4143e3810cd..28fcfdd4862 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -85,6 +85,7 @@ LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ LIBS-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/ LIBS-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/ +LIBS-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/ ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) LIBS-y += arch/$(ARCH)/imx-common/ -- cgit v1.3.1 From 2c92b1d6738c35236afaa3544d196a0d5ececa87 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 5 Feb 2014 10:41:27 +0900 Subject: .gitignore: drop include/asm from ignored file list Commit bb02c536 stopped creaing a symbolic link include/asm. Signed-off-by: Masahiro Yamada --- include/.gitignore | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/.gitignore b/include/.gitignore index 7cd3e907002..bf142fc2f9d 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,5 +1,4 @@ /autoconf.mk* -/asm /bmp_logo.h /bmp_logo_data.h /config.h -- cgit v1.3.1 From babb4440cfe1b8806cf2a5a3c5836196e501665d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 5 Feb 2014 10:52:52 +0900 Subject: kernel-doc: fix some errors - Delete fs.xml from DOCBOOKS to fix an error. Commit e3ff797c added fs.xml to DOCBOOKS but missed to add doc/DocBook/fs.tmpl. - Fix the location of include guard in include/linker_lists.h. Signed-off-by: Masahiro Yamada Reported-by: Abraham Varricatt Acked-by: Simon Glass --- doc/DocBook/Makefile | 2 +- include/linker_lists.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 30771340a0d..44afc471486 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -6,7 +6,7 @@ # To add a new book the only step required is to add the book to the # list of DOCBOOKS. -DOCBOOKS := fs.xml linker_lists.xml stdio.xml +DOCBOOKS := linker_lists.xml stdio.xml ### # The build process is as follows (targets): diff --git a/include/linker_lists.h b/include/linker_lists.h index 1eebb95fbb9..997d149b71d 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -8,6 +8,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __LINKER_LISTS_H__ +#define __LINKER_LISTS_H__ + /* * There is no use in including this from ASM files, but that happens * anyway, e.g. PPC kgdb.S includes command.h which incluse us. @@ -97,9 +100,6 @@ * %u_boot_list_2_drivers_3 */ -#ifndef __LINKER_LISTS_H__ -#define __LINKER_LISTS_H__ - /** * ll_entry_declare() - Declare linker-generated array entry * @_type: Data type of the entry -- cgit v1.3.1 From 6ab6b2afa091dbceb37719b8a81637a00834be19 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 5 Feb 2014 11:28:25 +0900 Subject: dts: re-write dts/Makefile more simply with Kbuild Useful rules in scripts/Makefile.lib allows us to easily generate a device tree blob and wrap it in assembly code. We do not need to parse a linker script to get output format and arch. This commit deletes ./u-boot.dtb since it is a copy of dts/dt.dtb. Signed-off-by: Masahiro Yamada --- .gitignore | 1 - Makefile | 16 +++++----- arch/arm/lib/board.c | 2 +- arch/microblaze/lib/board.c | 2 +- arch/x86/lib/init_helpers.c | 2 +- common/board_f.c | 2 +- dts/.gitignore | 2 ++ dts/Makefile | 72 +++++++++++++-------------------------------- include/common.h | 2 +- scripts/Makefile.lib | 12 ++++---- 10 files changed, 41 insertions(+), 72 deletions(-) create mode 100644 dts/.gitignore (limited to 'include') diff --git a/.gitignore b/.gitignore index 24019b37375..5882ff50b1d 100644 --- a/.gitignore +++ b/.gitignore @@ -48,7 +48,6 @@ /u-boot.lds /u-boot.ubl /u-boot.ais -/u-boot.dtb /u-boot.sb # diff --git a/Makefile b/Makefile index 75fd7f32ac2..19deb0fb624 100644 --- a/Makefile +++ b/Makefile @@ -720,7 +720,7 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin -ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.bin ifneq ($(CONFIG_SPL_TARGET),) ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif @@ -744,11 +744,11 @@ endif all: $(ALL-y) -u-boot.dtb: checkdtc u-boot - $(MAKE) $(build)=dts binary - mv dts/dt.dtb $@ +PHONY += dtbs +dtbs dts/dt.dtb: checkdtc u-boot + $(Q)$(MAKE) $(build)=dts dtbs -u-boot-dtb.bin: u-boot.bin u-boot.dtb +u-boot-dtb.bin: u-boot.bin dts/dt.dtb cat $^ >$@ u-boot.hex: u-boot @@ -875,8 +875,8 @@ u-boot-nodtb-tegra.bin: spl/u-boot-spl.bin u-boot.bin rm spl/u-boot-spl-pad.bin ifeq ($(CONFIG_OF_SEPARATE),y) -u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin u-boot.dtb - cat u-boot-nodtb-tegra.bin u-boot.dtb > $@ +u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb + cat $^ > $@ endif endif @@ -1171,7 +1171,7 @@ include/license.h: tools/bin2header COPYING # Directories & files removed with 'make clean' CLEAN_DIRS += $(MODVERDIR) CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \ - board/*/config.tmp board/*/*/config.tmp dts/*.tmp \ + board/*/config.tmp board/*/*/config.tmp \ include/autoconf.mk* include/spl-autoconf.mk \ include/tpl-autoconf.mk diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index b770e25d87b..38b9c7d3c57 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -280,7 +280,7 @@ void board_init_f(ulong bootflag) gd->mon_len = _bss_end_ofs; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_db_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 59956a8673d..fafeeaebd63 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -87,7 +87,7 @@ void board_init_f(ulong not_used) #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = (void *)__end; diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 582c0ffe245..b5d937feb3a 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -92,7 +92,7 @@ int find_fdt(void) { #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = (ulong *)&_end; diff --git a/common/board_f.c b/common/board_f.c index aa70c3e57de..d0ee6f76566 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -360,7 +360,7 @@ static int setup_fdt(void) { #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ # ifdef CONFIG_SYS_SYM_OFFSETS diff --git a/dts/.gitignore b/dts/.gitignore new file mode 100644 index 00000000000..1b3718065ca --- /dev/null +++ b/dts/.gitignore @@ -0,0 +1,2 @@ +*.dtb +*.dtb.S diff --git a/dts/Makefile b/dts/Makefile index 1e7609a4674..c47fba787cc 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -7,64 +7,32 @@ # This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is # enabled. See doc/README.fdt-control for more details. -DTS_INCDIRS = $(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts -DTS_INCDIRS += $(SRCTREE)/board/$(VENDOR)/dts -DTS_INCDIRS += $(SRCTREE)/arch/$(ARCH)/dts +DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) +ifeq ($(DEVICE_TREE),) +DEVICE_TREE := notfound +endif -DTS_CPPFLAGS := -x assembler-with-cpp -undef -D__DTS__ \ - -nostdinc $(addprefix -I,$(DTS_INCDIRS)) +DTS := $(srctree)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts -DTC_FLAGS := -R 4 -p 0x1000 \ - $(addprefix -i ,$(DTS_INCDIRS)) +DTC_FLAGS += -i $(srctree)/arch/$(ARCH)/dts -R 4 -p 0x1000 -# Use a constant name for this so we can access it from C code. -# objcopy doesn't seem to allow us to set the symbol name independently of -# the filename. -DT_BIN := $(obj)/dt.dtb +$(obj)/dt.dtb: $(DTS) FORCE + $(call if_changed_dep,dtc) -DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) -ifeq ($(DEVICE_TREE),) -$(DT_BIN): FORCE - echo >&2 "Please define CONFIG_DEFAULT_DEVICE_TREE in your board header file" -else -$(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts - $(CPP) $(DTS_CPPFLAGS) $< -o $(DT_BIN).dts.tmp - $(DTC) $(DTC_FLAGS) -O dtb -o ${DT_BIN} $(DT_BIN).dts.tmp -endif +targets += dt.dtb -process_lds = \ - $(1) | sed -r -n 's/^OUTPUT_$(2)[ ("]*([^")]*).*/\1/p' +$(DTS): + @echo >&2 + @echo >&2 "Device Tree Source is not specified." + @echo >&2 "Please define 'CONFIG_DEFAULT_DEVICE_TREE'" + @echo >&2 "or build with 'DEVICE_TREE=' argument" + @/bin/false -# Run the compiler and get the link script from the linker -GET_LDS = $(CC) $(c_flags) $(ld_flags) -Wl,--verbose 2>&1 +.SECONDARY: $(obj)/dt.dtb.S -$(obj)/dt.o: $(DT_BIN) - # We want the output format and arch. - # We also hope to win a prize for ugliest Makefile / shell interaction - # We look in the LDSCRIPT first. - # Then try the linker which should give us the answer. - # Then check it worked. - [ -n "$(LDSCRIPT)" ] && \ - oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \ - oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\ - \ - [ -z $${oformat} ] && \ - oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\ - [ -z $${oarch} ] && \ - oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\ - \ - [ -z $${oformat} ] && \ - echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \ - exit 1 || true ;\ - [ -z $${oarch} ] && \ - echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \ - exit 1 || true ;\ - \ - cd $(dir ${DT_BIN}) && \ - $(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \ - $(notdir ${DT_BIN}) $(notdir $@) - rm $(DT_BIN) +obj-$(CONFIG_OF_EMBED) := dt.dtb.o -obj-$(CONFIG_OF_EMBED) := dt.o +dtbs: $(obj)/dt.dtb + @: -binary: $(DT_BIN) +clean-files := dt.dtb.S diff --git a/include/common.h b/include/common.h index 221b7768c5b..672c0b5c170 100644 --- a/include/common.h +++ b/include/common.h @@ -302,7 +302,7 @@ int checkdram (void); int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); -extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ +extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ int set_cpu_clk_info(void); int print_cpuinfo(void); int update_flash_size(int flash_size); diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index d4b5cb5d0ea..ee3ceac7d13 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -151,9 +151,10 @@ cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ ld_flags = $(LDFLAGS) $(ldflags-y) +# Modified for U-Boot dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ - -I$(srctree)/arch/$(SRCARCH)/boot/dts \ - -I$(srctree)/arch/$(SRCARCH)/boot/dts/include \ + -I$(srctree)/board/$(VENDOR)/dts/ \ + -I$(srctree)/arch/$(ARCH)/dts \ -undef -D__DTS__ # Finds the multi-part object the current object will be linked into @@ -247,25 +248,24 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \ # Generate an assembly file to wrap the output of the device tree compiler quiet_cmd_dt_S_dtb= DTB $@ +# Modified for U-Boot cmd_dt_S_dtb= \ ( \ - echo '\#include '; \ echo '.section .dtb.init.rodata,"a"'; \ - echo '.balign STRUCT_ALIGNMENT'; \ echo '.global __dtb_$(*F)_begin'; \ echo '__dtb_$(*F)_begin:'; \ echo '.incbin "$<" '; \ echo '__dtb_$(*F)_end:'; \ echo '.global __dtb_$(*F)_end'; \ - echo '.balign STRUCT_ALIGNMENT'; \ ) > $@ $(obj)/%.dtb.S: $(obj)/%.dtb $(call cmd,dt_S_dtb) quiet_cmd_dtc = DTC $@ +# Modified for U-Boot cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ - $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \ + dtc -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -- cgit v1.3.1 From 627b73e2a79524836b1e933e37e014210ccb80a4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 7 Feb 2014 09:23:03 +0900 Subject: configs: Delete obsolete macro, CONFIG_SYS_GBL_DATA_SIZE CONFIG_SYS_GBL_DATA_SIZE is not used any more. The size of struct "global_data" is automatically calculated by asm-offsets. (See lib/asm-offsets.c) GENERATED_GBL_DATA_SIZE should be used instead of CONFIG_SYS_GBL_DATA_SIZE. Signed-off-by: Masahiro Yamada --- include/configs/M54418TWR.h | 4 +--- include/configs/MERGERBOX.h | 3 +-- include/configs/P1023RDS.h | 3 +-- include/configs/ac14xx.h | 3 +-- include/configs/adp-ag101.h | 5 ----- include/configs/adp-ag101p.h | 5 ----- include/configs/adp-ag102.h | 5 ----- include/configs/ap_sh4a_4a.h | 2 -- include/configs/armadillo-800eva.h | 1 - include/configs/devkit3250.h | 1 - include/configs/dlvision-10g.h | 3 +-- include/configs/ecovec.h | 2 -- include/configs/io.h | 3 +-- include/configs/iocon.h | 3 +-- include/configs/km/km83xx-common.h | 1 - include/configs/koelsch.h | 1 - include/configs/kzm9g.h | 1 - include/configs/lager.h | 1 - include/configs/mxs.h | 1 - include/configs/o2dnt-common.h | 4 +--- include/configs/r0p7734.h | 2 -- include/configs/shmin.h | 1 - include/configs/snowball.h | 2 -- include/configs/u8500_href.h | 1 - include/configs/vl_ma2sc.h | 1 - 25 files changed, 8 insertions(+), 51 deletions(-) (limited to 'include') diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index de063b70d6f..031672eb334 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -268,10 +268,8 @@ /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 256 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_GBL_DATA_SIZE) - 32) + GENERATED_GBL_DATA_SIZE) - 32) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index 3dcea0b595b..930699ba6da 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -121,9 +121,8 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) /* * Local Bus Configuration & Clock Setup diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index b51354525a8..ec72c78861a 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -194,9 +194,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index aa584b77680..f57820d8f59 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -289,9 +289,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h index e31131f6e2a..e318c7543f3 100644 --- a/include/configs/adp-ag101.h +++ b/include/configs/adp-ag101.h @@ -138,11 +138,6 @@ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ #define CONFIG_SYS_MALLOC_LEN (512 << 10) -/* - * size in bytes reserved for initial data - */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index ded3f331e8e..24904b0b7c3 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -138,11 +138,6 @@ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ #define CONFIG_SYS_MALLOC_LEN (512 << 10) -/* - * size in bytes reserved for initial data - */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h index 1e4ce2e7d97..39f7a3cd46f 100644 --- a/include/configs/adp-ag102.h +++ b/include/configs/adp-ag102.h @@ -203,11 +203,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -/* - * size in bytes reserved for initial data -*/ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index bb39491f8b6..4282d702662 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -134,8 +134,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index e5569c72966..17a2da034d9 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -94,7 +94,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_SYS_TEXT_BASE 0xE80C0000 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index bcb21fefe33..3d39b106584 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -29,7 +29,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M #define CONFIG_SYS_TEXT_BASE 0x83FA0000 diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 31fc65d1969..78778970f4a 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -217,9 +217,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 3a5cc74829c..e26591c14f7 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -158,8 +158,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/io.h b/include/configs/io.h index 7f86767e944..9da6cc68559 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -198,9 +198,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/iocon.h b/include/configs/iocon.h index d34b91dfde8..f36c2a3504e 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -238,9 +238,8 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 5e075c8dd2a..ae6b6dcf246 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -84,7 +84,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 964d0dcb4b6..90e2d7a030d 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -106,7 +106,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index f183279ba89..4d11c7d08c0 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -88,7 +88,6 @@ #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_SYS_TEXT_BASE 0x00000000 diff --git a/include/configs/lager.h b/include/configs/lager.h index 32a2655d762..b420e45e63c 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #if defined(CONFIG_SYS_USE_BOOT_NORFLASH) diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 363b277635c..55ecef92a9d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -59,7 +59,6 @@ /* Memory sizes */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 18714eae1e9..133dc6f8cd1 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -275,10 +275,8 @@ #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE #endif -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 53128ecc120..a71709bc7c2 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -140,8 +140,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/shmin.h b/include/configs/shmin.h index f8155efbc98..4d38f6c5540 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -62,7 +62,6 @@ #define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE) #define CONFIG_SYS_MONITOR_LEN (128 * 1024) #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE 256 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 9a069f3cdba..dacb5604cd6 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -41,8 +41,6 @@ #define CONFIG_ENV_SIZE (8*1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ - #define CONFIG_ENV_IS_IN_MMC #define CONFIG_CMD_ENV #define CONFIG_CMD_SAVEENV diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h index 629299d1070..8d7970a376e 100644 --- a/include/configs/u8500_href.h +++ b/include/configs/u8500_href.h @@ -29,7 +29,6 @@ #define CONFIG_ENV_SIZE (128*1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) #endif -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ /* * PL011 Configuration diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 88aaa95fb11..2187f77c5a6 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -363,7 +363,6 @@ */ #define CONFIG_SYS_MALLOC_LEN \ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ #ifndef CONFIG_RAMLOAD #define CONFIG_BOOTCOMMAND "run nfsboot" -- cgit v1.3.1 From 2f13363b0913afe910c22c0f9c12946c6603b1c2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 7 Feb 2014 17:20:52 +0900 Subject: configs: Delete unused CONFIG_SYS_64BIT_{VSPRINTF, STRTOUL} Signed-off-by: Masahiro Yamada --- include/configs/M54418TWR.h | 1 - include/configs/p1_twr.h | 3 --- include/configs/vl_ma2sc.h | 1 - include/configs/x600.h | 1 - 4 files changed, 6 deletions(-) (limited to 'include') diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 031672eb334..3d7dc1fb2dd 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -77,7 +77,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Network configuration */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 601bac72e0a..c296a075994 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -238,9 +238,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS -#define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_64BIT_STRTOUL - /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 2187f77c5a6..14c6e675c1b 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -322,7 +322,6 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ diff --git a/include/configs/x600.h b/include/configs/x600.h index 00b938a2160..d420efe5438 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -170,7 +170,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_64BIT_VSPRINTF /* Use last 2 lwords in internal SRAM for bootcounter */ #define CONFIG_BOOTCOUNT_LIMIT -- cgit v1.3.1 From 365475e6d14bc1ea9d218c0fd1fe96878a9db94e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 13 Feb 2014 18:30:26 +0900 Subject: Move #ifdef(CONFIG_DISPLAY_CPUINFO) from caller to callee - When CONFIG_DISPLAY_CPUINFO is not enabled, print_cpuinfo() should be defined as an empty function in a header, include/common.h - Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif from caller, common/board_f.c and arch/arm/lib/board.c - Remove redundant prototypes in arch/arm/lib/board.c, arch/arm/include/asm/arch-am33x/sys_proto.h and board/nokia/rx51/rx51.h, keeping the one in include/common.h - Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition where it is missing Signed-off-by: Masahiro Yamada --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 3 +++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 4 ---- arch/arm/lib/board.c | 4 ---- board/altera/socfpga/socfpga_cyclone5.c | 2 ++ board/freescale/mx53loco/mx53loco.c | 2 ++ board/nokia/rx51/rx51.h | 2 -- common/board_f.c | 2 -- include/common.h | 7 +++++++ 8 files changed, 14 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index bf2951031d9..ade744e31fe 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -248,6 +248,7 @@ u32 get_device_type(void) (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } +#if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information */ @@ -258,6 +259,8 @@ int print_cpuinfo(void) return 0; } +#endif + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 87b7d367b9d..2e5c356e448 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -17,10 +17,6 @@ u32 get_cpu_rev(void); u32 get_sysboot_value(void); -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void); -#endif - extern struct ctrl_stat *cstat; u32 get_device_type(void); void save_omap_boot_params(void); diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 38b9c7d3c57..c320a35166b 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -197,8 +197,6 @@ static int arm_pci_init(void) */ typedef int (init_fnc_t) (void); -int print_cpuinfo(void); - void __dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; @@ -250,9 +248,7 @@ init_fnc_t *init_sequence[] = { serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ display_banner, /* say that we are here */ -#if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo, /* display cpu info (and speed) */ -#endif #if defined(CONFIG_DISPLAY_BOARDINFO) checkboard, /* display board info */ #endif diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 576066bef13..a960eb60028 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -12,6 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information */ @@ -20,6 +21,7 @@ int print_cpuinfo(void) puts("CPU : Altera SOCFPGA Platform\n"); return 0; } +#endif /* * Print Board information diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index db0bf17363e..08dd66fcc64 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -343,6 +343,7 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { u32 cpurev; @@ -356,6 +357,7 @@ int print_cpuinfo(void) printf("Reset cause: %s\n", get_reset_cause()); return 0; } +#endif /* * Do not overwrite the console diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h index 4a230dd596e..0d2f0a54c56 100644 --- a/board/nokia/rx51/rx51.h +++ b/board/nokia/rx51/rx51.h @@ -22,8 +22,6 @@ struct emu_hal_params_rx51 { u32 param4; }; -int print_cpuinfo(void); - /* * IEN - Input Enable * IDIS - Input Disable diff --git a/common/board_f.c b/common/board_f.c index d0ee6f76566..02965b0df76 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -887,9 +887,7 @@ static init_fnc_t init_sequence_f[] = { #ifdef CONFIG_PPC checkcpu, #endif -#if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo, /* display cpu info (and speed) */ -#endif #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ diff --git a/include/common.h b/include/common.h index 672c0b5c170..08b294cfd91 100644 --- a/include/common.h +++ b/include/common.h @@ -304,7 +304,14 @@ extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void); +#else +static inline int print_cpuinfo(void) +{ + return 0; +} +#endif int update_flash_size(int flash_size); /** -- cgit v1.3.1 From 18948632a92f83cfad125edc6ff4a162a7d90a05 Mon Sep 17 00:00:00 2001 From: Michael Burr Date: Wed, 22 Jan 2014 09:46:08 +0100 Subject: i2c: zynq: Add support for the second i2c controller Initialize the second i2c controller. Signed-off-by: Michael Burr Signed-off-by: Michal Simek --- drivers/i2c/zynq_i2c.c | 44 ++++++++++++++++++++++++++----------------- include/configs/zynq-common.h | 6 +++--- 2 files changed, 30 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index 11ef0f8d4f9..f1f65131a2a 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -64,19 +64,21 @@ struct zynq_i2c_registers { #define ZYNQ_I2C_FIFO_DEPTH 16 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ -#if defined(CONFIG_ZYNQ_I2C0) -# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0 -#else -# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1 -#endif - -static struct zynq_i2c_registers *zynq_i2c = - (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; +static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap) +{ + return adap->hwadapnr ? + /* Zynq PS I2C1 */ + (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 : + /* Zynq PS I2C0 */ + (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0; +} /* I2C init called by cmd_i2c when doing 'i2c reset'. */ static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, int slaveadd) { + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); + /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); @@ -87,7 +89,7 @@ static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, } #ifdef DEBUG -static void zynq_i2c_debug_status(void) +static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c) { int int_status; int status; @@ -129,7 +131,7 @@ static void zynq_i2c_debug_status(void) #endif /* Wait for an interrupt */ -static u32 zynq_i2c_wait(u32 mask) +static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) { int timeout, int_status; @@ -140,7 +142,7 @@ static u32 zynq_i2c_wait(u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c)); #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); @@ -154,6 +156,8 @@ static u32 zynq_i2c_wait(u32 mask) */ static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) { + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); + /* Attempt to read a byte */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_RW); @@ -162,7 +166,7 @@ static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) writel(dev, &zynq_i2c->address); writel(1, &zynq_i2c->transfer_size); - return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | + return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_NACK) & ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; } @@ -177,6 +181,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, u32 status; u32 i = 0; u8 *cur_data = data; + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); /* Check the hardware can handle the requested bytes */ if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) @@ -198,7 +203,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, writel(addr >> (8 * alen), &zynq_i2c->data); /* Wait for the address to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); return -ETIMEDOUT; @@ -214,7 +219,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, /* Wait for data */ do { - status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | + status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_DATA); if (!status) { /* Release the bus */ @@ -243,6 +248,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data, int length) { u8 *cur_data = data; + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); /* Write the register address */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | @@ -254,7 +260,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, while (alen--) writel(addr >> (8 * alen), &zynq_i2c->data); /* Start the tranfer */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); return -ETIMEDOUT; @@ -265,7 +271,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, while (length--) { writel(*(cur_data++), &zynq_i2c->data); if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); @@ -277,7 +283,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, /* All done... release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); /* Wait for the address and data to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) return -ETIMEDOUT; return 0; } @@ -295,3 +301,7 @@ U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, zynq_i2c_write, zynq_i2c_set_bus_speed, CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, 0) +U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, + zynq_i2c_write, zynq_i2c_set_bus_speed, + CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, + 1) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 9b6db043b57..787d32d2b80 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -104,13 +104,13 @@ # define CONFIG_DOS_PARTITION #endif +#define CONFIG_SYS_I2C_ZYNQ /* I2C */ -#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) +#if defined(CONFIG_SYS_I2C_ZYNQ) # define CONFIG_CMD_I2C # define CONFIG_SYS_I2C -# define CONFIG_SYS_I2C_ZYNQ # define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 -# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0 #endif /* EEPROM */ -- cgit v1.3.1 From d5243359e1afc957acd373dbbde1cf6c70ee5485 Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Mon, 3 Feb 2014 21:22:18 +0100 Subject: OMAP24xx I2C: Add support for set-speed Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by: Hannes Petermaier Cc: Heiko Schocher --- drivers/i2c/omap24xx_i2c.c | 147 ++++++++++++++++++++++++++++++--------------- include/i2c.h | 1 + 2 files changed, 98 insertions(+), 50 deletions(-) (limited to 'include') diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index c7840049b11..a39b5917ecd 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -32,6 +32,10 @@ * - Status functions now read irqstatus_raw as per TRM guidelines * (except for OMAP243X and OMAP34XX). * - Driver now supports up to I2C5 (OMAP5). + * + * Copyright (c) 2014 Hannes Petermaier , B&R + * - Added support for set_speed + * */ #include @@ -53,43 +57,66 @@ static int wait_for_bb(struct i2c_adapter *adap); static struct i2c *omap24_get_base(struct i2c_adapter *adap); static u16 wait_for_event(struct i2c_adapter *adap); static void flush_fifo(struct i2c_adapter *adap); - -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) { - struct i2c *i2c_base = omap24_get_base(adap); - int psc, fsscll, fssclh; - int hsscll = 0, hssclh = 0; - u32 scll, sclh; - int timeout = I2C_TIMEOUT; + unsigned int sampleclk, prescaler; + int fsscll, fssclh; - /* Only handle standard, fast and high speeds */ - if ((speed != OMAP_I2C_STANDARD) && - (speed != OMAP_I2C_FAST_MODE) && - (speed != OMAP_I2C_HIGH_SPEED)) { - printf("Error : I2C unsupported speed %d\n", speed); - return; - } + speed <<= 1; + prescaler = 0; + /* + * some divisors may cause a precission loss, but shouldn't + * be a big thing, because i2c_clk is then allready very slow. + */ + while (prescaler <= 0xFF) { + sampleclk = I2C_IP_CLK / (prescaler+1); - psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; - psc -= 1; - if (psc < I2C_PSC_MIN) { - printf("Error : I2C unsupported prescalar %d\n", psc); - return; + fsscll = sampleclk / speed; + fssclh = fsscll; + fsscll -= I2C_FASTSPEED_SCLL_TRIM; + fssclh -= I2C_FASTSPEED_SCLH_TRIM; + + if (((fsscll > 0) && (fssclh > 0)) && + ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) && + (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) { + if (pscl) + *pscl = fsscll; + if (psch) + *psch = fssclh; + + return prescaler; + } + prescaler++; } + return -1; +} +static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int psc, fsscll = 0, fssclh = 0; + int hsscll = 0, hssclh = 0; + u32 scll = 0, sclh = 0; - if (speed == OMAP_I2C_HIGH_SPEED) { + if (speed >= OMAP_I2C_HIGH_SPEED) { /* High speed */ + psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; + psc -= 1; + if (psc < I2C_PSC_MIN) { + printf("Error : I2C unsupported prescaler %d\n", psc); + return -1; + } /* For first phase of HS mode */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / - (2 * OMAP_I2C_FAST_MODE); + fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + + fssclh = fsscll; fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing first phase clock\n"); - return; + return -1; } /* For second phase of HS mode */ @@ -100,7 +127,7 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing second phase clock\n"); - return; + return -1; } scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; @@ -108,20 +135,29 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) } else { /* Standard and fast speed */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); - - fsscll -= I2C_FASTSPEED_SCLL_TRIM; - fssclh -= I2C_FASTSPEED_SCLH_TRIM; - if (((fsscll < 0) || (fssclh < 0)) || - ((fsscll > 255) || (fssclh > 255))) { + psc = omap24_i2c_findpsc(&scll, &sclh, speed); + if (0 > psc) { puts("Error : I2C initializing clock\n"); - return; + return -1; } - - scll = (unsigned int)fsscll; - sclh = (unsigned int)fssclh; } + adap->speed = speed; + adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ + writew(0, &i2c_base->con); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); + writew(I2C_CON_EN, &i2c_base->con); + writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ + + return 0; +} +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int timeout = I2C_TIMEOUT; + if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); @@ -139,14 +175,14 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) udelay(1000); } - writew(0, &i2c_base->con); - writew(psc, &i2c_base->psc); - writew(scll, &i2c_base->scll); - writew(sclh, &i2c_base->sclh); + if (0 != omap24_i2c_setspeed(adap, speed)) { + printf("ERROR: failed to setup I2C bus-speed!\n"); + return; + } /* own address */ writew(slaveadd, &i2c_base->oa); - writew(I2C_CON_EN, &i2c_base->con); + #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have @@ -165,7 +201,8 @@ static void flush_fifo(struct i2c_adapter *adap) struct i2c *i2c_base = omap24_get_base(adap); u16 stat; - /* note: if you try and read data when its not there or ready + /* + * note: if you try and read data when its not there or ready * you get a bus error */ while (1) { @@ -220,8 +257,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { - res = 0; /* Device found */ - udelay(I2C_WAIT); /* Required by AM335X in SPL */ + res = 0; /* Device found */ + udelay(adap->waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); @@ -307,7 +344,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", status); @@ -351,7 +388,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; goto rd_exit; } @@ -379,6 +416,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int i; u16 status; int i2c_error = 0; + int timeout = I2C_TIMEOUT; if (alen < 0) { puts("I2C write: addr len < 0\n"); @@ -428,7 +466,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto wr_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", status); @@ -448,7 +486,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, /* Address phase is over, now write data */ for (i = 0; i < len; i++) { status = wait_for_event(adap); - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", status); @@ -464,6 +502,15 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, goto wr_exit; } } + /* + * poll ARDY bit for making sure that last byte really has been + * transferred on the bus. + */ + do { + status = wait_for_event(adap); + } while (!(status & I2C_STAT_ARDY) && timeout--); + if (timeout <= 0) + printf("i2c_write: timed out writig last byte!\n"); wr_exit: flush_fifo(adap); @@ -490,7 +537,7 @@ static int wait_for_bb(struct i2c_adapter *adap) I2C_STAT_BB) && timeout--) { #endif writew(stat, &i2c_base->stat); - udelay(I2C_WAIT); + udelay(adap->waitdelay); } if (timeout <= 0) { @@ -513,7 +560,7 @@ static u16 wait_for_event(struct i2c_adapter *adap) int timeout = I2C_TIMEOUT; do { - udelay(I2C_WAIT); + udelay(adap->waitdelay); #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) status = readw(&i2c_base->stat); #else @@ -580,12 +627,12 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) #endif U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, - omap24_i2c_read, omap24_i2c_write, NULL, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE, 0) U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, - omap24_i2c_read, omap24_i2c_write, NULL, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, CONFIG_SYS_OMAP24_I2C_SPEED1, CONFIG_SYS_OMAP24_I2C_SLAVE1, 1) diff --git a/include/i2c.h b/include/i2c.h index f93a18366e0..1b4078ed62f 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -68,6 +68,7 @@ struct i2c_adapter { uint (*set_bus_speed)(struct i2c_adapter *adap, uint speed); int speed; + int waitdelay; int slaveaddr; int init_done; int hwadapnr; -- cgit v1.3.1 From f93f589ca2defd02fa76a3d0cde695d61820390d Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 10 Feb 2014 12:20:11 +0400 Subject: spear: move CONFIG_SYS_I2C_BASE from arch-spear/hardware to board configs Having CONFIG_SYS_I2C_BASE requires DW I2C driver to explicitly include which other platforms may not have at all. It's always good to have a driver platform-independent. Signed-off-by: Alexey Brodkin Cc: Tom Rini Cc: Heiko Schocher Cc: Stefan Roese Cc: Vipin Kumar Cc: Armando Visconti --- arch/arm/include/asm/arch-spear/hardware.h | 4 ---- include/configs/spear-common.h | 9 +++++++++ include/configs/x600.h | 1 + 3 files changed, 10 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index f3afd4d0659..c6da405cc07 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_FSMC_BASE 0xD1800000 #define CONFIG_FSMC_NAND_BASE 0xD2000000 @@ -42,11 +41,9 @@ #define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE @@ -63,7 +60,6 @@ #define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x4C000000 #define CONFIG_SPEAR_EMIBASE 0x40000000 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index e090a376d03..c0eba3721d7 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -39,6 +39,15 @@ /* I2C driver configuration */ #define CONFIG_HARD_I2C #define CONFIG_DW_I2C +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#endif #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 diff --git a/include/configs/x600.h b/include/configs/x600.h index d420efe5438..7405419f0e2 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -85,6 +85,7 @@ /* I2C config options */ #define CONFIG_HARD_I2C #define CONFIG_DW_I2C +#define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 #define CONFIG_I2C_CHIPADDRESS 0x50 -- cgit v1.3.1 From c42eb7f2c76ff5553380cb0bfbfb62903194cf0c Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Sat, 8 Feb 2014 10:30:59 +0400 Subject: axs101: change command prompt marker to match marketing name of the board Proper spelling of the boad marketing name is with upper case. So changing it from lower case to upper case here. Cc: Tom Rini Signed-off-by: Alexey Brodkin --- include/configs/axs101.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/axs101.h b/include/configs/axs101.h index af2e63b4db7..f6b569abfdd 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -167,7 +167,7 @@ * Console configuration */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "axs# " +#define CONFIG_SYS_PROMPT "AXS# " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ -- cgit v1.3.1 From 1530f6f51ada57a9dd24f07d0f0955a8bf84c7b8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 21 Feb 2014 08:42:02 -0500 Subject: fs/fdos: Remove We have an unused FAT implementation in fs/fdos, remove. Signed-off-by: Tom Rini --- README | 1 - common/Makefile | 3 +- common/cmd_fdc.c | 67 ---------- fs/Makefile | 1 - fs/fdos/Makefile | 13 -- fs/fdos/dev.c | 174 ------------------------ fs/fdos/dos.h | 159 ---------------------- fs/fdos/fat.c | 122 ----------------- fs/fdos/fdos.c | 156 ---------------------- fs/fdos/fdos.h | 100 -------------- fs/fdos/fs.c | 98 -------------- fs/fdos/subdir.c | 329 ---------------------------------------------- fs/fdos/vfat.c | 336 ----------------------------------------------- include/config_cmd_all.h | 1 - 14 files changed, 1 insertion(+), 1559 deletions(-) delete mode 100644 fs/fdos/Makefile delete mode 100644 fs/fdos/dev.c delete mode 100644 fs/fdos/dos.h delete mode 100644 fs/fdos/fat.c delete mode 100644 fs/fdos/fdos.c delete mode 100644 fs/fdos/fdos.h delete mode 100644 fs/fdos/fs.c delete mode 100644 fs/fdos/subdir.c delete mode 100644 fs/fdos/vfat.c (limited to 'include') diff --git a/README b/README index 423ab2cfcc1..6668631bccc 100644 --- a/README +++ b/README @@ -927,7 +927,6 @@ The following options need to be configured: CONFIG_CMD_SAVEENV saveenv CONFIG_CMD_FDC * Floppy Disk Support CONFIG_CMD_FAT * FAT command support - CONFIG_CMD_FDOS * Dos diskette Support CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support CONFIG_CMD_FUSE * Device fuse support diff --git a/common/Makefile b/common/Makefile index 3b2ff9bb529..6652ad41f8b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -81,9 +81,8 @@ obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o obj-$(CONFIG_CMD_FAT) += cmd_fat.o -obj-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o +obj-$(CONFIG_CMD_FDC) += cmd_fdc.o obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o -obj-$(CONFIG_CMD_FDOS) += cmd_fdos.o obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o obj-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 98b3c4c0014..1cfb656bc07 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -627,72 +627,6 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) return true; } -#if defined(CONFIG_CMD_FDOS) - -/* Low level functions for the Floppy-DOS layer */ - -/************************************************************************** -* int fdc_fdos_init -* initialize the FDC layer -* -*/ -int fdc_fdos_init (int drive) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - /* setup FDC and scan for drives */ - if (fdc_setup(drive, pCMD, pFG) == false) { - printf("\n** Error in setup FDC **\n"); - return false; - } - if (fdc_check_drive(pCMD, pFG) == false) { - printf("\n** Error in check_drives **\n"); - return false; - } - if((pCMD->flags&(1<flags&(0x10<drive=drive; - - /* read first block */ - pCMD->blnr=0; - return true; -} -/************************************************************************** -* int fdc_fdos_seek -* parameter is a block number -*/ -int fdc_fdos_seek (int where) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - pCMD -> blnr = where ; - return (fdc_seek (pCMD, pFG)); -} -/************************************************************************** -* int fdc_fdos_read -* the length is in block number -*/ -int fdc_fdos_read (void *buffer, int len) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - return (fdc_read_data (buffer, len, pCMD, pFG)); -} -#endif - -#if defined(CONFIG_CMD_FDC) /**************************************************************************** * main routine do_fdcboot */ @@ -812,4 +746,3 @@ U_BOOT_CMD( "boot from floppy device", "loadAddr drive" ); -#endif diff --git a/fs/Makefile b/fs/Makefile index 34dc0351edd..18221658fcb 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_CMD_CBFS) += cbfs/ obj-$(CONFIG_CMD_CRAMFS) += cramfs/ obj-$(CONFIG_FS_EXT4) += ext4/ obj-y += fat/ -obj-$(CONFIG_CMD_FDOS) += fdos/ obj-$(CONFIG_CMD_JFFS2) += jffs2/ obj-$(CONFIG_CMD_REISER) += reiserfs/ obj-$(CONFIG_SANDBOX) += sandbox/ diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile deleted file mode 100644 index 2f8b5addd6a..00000000000 --- a/fs/fdos/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Stäubli Faverges - -# Pierre AUBERT p.aubert@staubli.com -# -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := fat.o vfat.o dev.o fdos.o fs.o subdir.o diff --git a/fs/fdos/dev.c b/fs/fdos/dev.c deleted file mode 100644 index 4c48663e091..00000000000 --- a/fs/fdos/dev.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include "dos.h" -#include "fdos.h" - -#define NB_HEADS 2 -#define NB_TRACKS 80 -#define NB_SECTORS 18 - - -static int lastwhere; - -/*----------------------------------------------------------------------------- - * dev_open -- - *----------------------------------------------------------------------------- - */ -int dev_open (void) -{ - lastwhere = 0; - return (0); -} - -/*----------------------------------------------------------------------------- - * dev_read -- len and where are sectors number - *----------------------------------------------------------------------------- - */ -int dev_read (void *buffer, int where, int len) -{ - PRINTF ("dev_read (len = %d, where = %d)\n", len, where); - - /* Si on ne desire pas lire a la position courante, il faut un seek */ - if (where != lastwhere) { - if (!fdc_fdos_seek (where)) { - PRINTF ("seek error in dev_read"); - lastwhere = -1; - return (-1); - } - } - - if (!fdc_fdos_read (buffer, len)) { - PRINTF ("read error\n"); - lastwhere = -1; - return (-1); - } - lastwhere = where + len; - return (0); -} -/*----------------------------------------------------------------------------- - * check_dev -- verify the diskette format - *----------------------------------------------------------------------------- - */ -int check_dev (BootSector_t *boot, Fs_t *fs) -{ - unsigned int heads, sectors, tracks; - int BootP, Infp0, InfpX, InfTm; - int sect_per_track; - - /* Display Boot header */ - PRINTF ("Jump to boot code 0x%02x 0x%02x 0x%02x\n", - boot -> jump [0], boot -> jump [1], boot -> jump[2]); - PRINTF ("OEM name & version '%*.*s'\n", - BANNER_LG, BANNER_LG, boot -> banner ); - PRINTF ("Bytes per sector hopefully 512 %d\n", - __le16_to_cpu (boot -> secsiz)); - PRINTF ("Cluster size in sectors %d\n", - boot -> clsiz); - PRINTF ("Number of reserved (boot) sectors %d\n", - __le16_to_cpu (boot -> nrsvsect)); - PRINTF ("Number of FAT tables hopefully 2 %d\n", - boot -> nfat); - PRINTF ("Number of directory slots %d\n", - __le16_to_cpu (boot -> dirents)); - PRINTF ("Total sectors on disk %d\n", - __le16_to_cpu (boot -> psect)); - PRINTF ("Media descriptor=first byte of FAT %d\n", - boot -> descr); - PRINTF ("Sectors in FAT %d\n", - __le16_to_cpu (boot -> fatlen)); - PRINTF ("Sectors/track %d\n", - __le16_to_cpu (boot -> nsect)); - PRINTF ("Heads %d\n", - __le16_to_cpu (boot -> nheads)); - PRINTF ("number of hidden sectors %d\n", - __le32_to_cpu (boot -> nhs)); - PRINTF ("big total sectors %d\n", - __le32_to_cpu (boot -> bigsect)); - PRINTF ("physical drive ? %d\n", - boot -> physdrive); - PRINTF ("reserved %d\n", - boot -> reserved); - PRINTF ("dos > 4.0 diskette %d\n", - boot -> dos4); - PRINTF ("serial number %d\n", - __le32_to_cpu (boot -> serial)); - PRINTF ("disk label %*.*s\n", - LABEL_LG, LABEL_LG, boot -> label); - PRINTF ("FAT type %8.8s\n", - boot -> fat_type); - PRINTF ("reserved by 2M %d\n", - boot -> res_2m); - PRINTF ("2M checksum (not used) %d\n", - boot -> CheckSum); - PRINTF ("2MF format version %d\n", - boot -> fmt_2mf); - PRINTF ("1 if write track after format %d\n", - boot -> wt); - PRINTF ("data transfer rate on track 0 %d\n", - boot -> rate_0); - PRINTF ("data transfer rate on track<>0 %d\n", - boot -> rate_any); - PRINTF ("offset to boot program %d\n", - __le16_to_cpu (boot -> BootP)); - PRINTF ("T1: information for track 0 %d\n", - __le16_to_cpu (boot -> Infp0)); - PRINTF ("T2: information for track<>0 %d\n", - __le16_to_cpu (boot -> InfpX)); - PRINTF ("T3: track sectors size table %d\n", - __le16_to_cpu (boot -> InfTm)); - PRINTF ("Format date 0x%04x\n", - __le16_to_cpu (boot -> DateF)); - PRINTF ("Format time 0x%04x\n", - __le16_to_cpu (boot -> TimeF)); - - - /* information is extracted from boot sector */ - heads = __le16_to_cpu (boot -> nheads); - sectors = __le16_to_cpu (boot -> nsect); - fs -> tot_sectors = __le32_to_cpu (boot -> bigsect); - if (__le16_to_cpu (boot -> psect) != 0) { - fs -> tot_sectors = __le16_to_cpu (boot -> psect); - } - - sect_per_track = heads * sectors; - tracks = (fs -> tot_sectors + sect_per_track - 1) / sect_per_track; - - BootP = __le16_to_cpu (boot -> BootP); - Infp0 = __le16_to_cpu (boot -> Infp0); - InfpX = __le16_to_cpu (boot -> InfpX); - InfTm = __le16_to_cpu (boot -> InfTm); - - if (boot -> dos4 == EXTENDED_BOOT && - strncmp( boot->banner,"2M", 2 ) == 0 && - BootP < SZ_STD_SECTOR && - Infp0 < SZ_STD_SECTOR && - InfpX < SZ_STD_SECTOR && - InfTm < SZ_STD_SECTOR && - BootP >= InfTm + 2 && - InfTm >= InfpX && - InfpX >= Infp0 && - Infp0 >= 76 ) { - - return (-1); - } - - if (heads != NB_HEADS || - tracks != NB_TRACKS || - sectors != NB_SECTORS || - __le16_to_cpu (boot -> secsiz) != SZ_STD_SECTOR || - fs -> tot_sectors == 0 || - (fs -> tot_sectors % sectors) != 0) { - return (-1); - } - - return (0); -} diff --git a/fs/fdos/dos.h b/fs/fdos/dos.h deleted file mode 100644 index b0b7d2aa06b..00000000000 --- a/fs/fdos/dos.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DOS_H_ -#define _DOS_H_ - -/* Definitions for Dos diskettes */ - -/* General definitions */ -#define SZ_STD_SECTOR 512 /* Standard sector size */ -#define MDIR_SIZE 32 /* Direntry size */ -#define FAT_BITS 12 /* Diskette use 12 bits fat */ - -#define MAX_PATH 128 /* Max size of the MSDOS PATH */ -#define MAX_DIR_SECS 64 /* Taille max d'un repertoire (en */ - /* secteurs) */ -/* Misc. definitions */ -#define DELMARK '\xe5' -#define EXTENDED_BOOT (0x29) -#define MEDIA_STD (0xf0) -#define JUMP_0_1 (0xe9) -#define JUMP_0_2 (0xeb) - -/* Boot size is 256 bytes, but we need to read almost a sector, then - assume bootsize is 512 */ -#define BOOTSIZE 512 - -/* Fat definitions for 12 bits fat */ -#define FAT12_MAX_NB 4086 -#define FAT12_LAST 0x0ff6 -#define FAT12_END 0x0fff - -/* file attributes */ -#define ATTR_READONLY 0x01 -#define ATTR_HIDDEN 0x02 -#define ATTR_SYSTEM 0x04 -#define ATTR_VOLUME 0x08 -#define ATTR_DIRECTORY 0x10 -#define ATTR_ARCHIVE 0x20 -#define ATTR_VSE 0x0f - -/* Name format */ -#define EXTCASE 0x10 -#define BASECASE 0x8 - -/* Definition of the boot sector */ -#define BANNER_LG 8 -#define LABEL_LG 11 - -typedef struct bootsector -{ - unsigned char jump [3]; /* 0 Jump to boot code */ - char banner [BANNER_LG]; /* 3 OEM name & version */ - unsigned short secsiz; /* 11 Bytes per sector hopefully 512 */ - unsigned char clsiz; /* 13 Cluster size in sectors */ - unsigned short nrsvsect; /* 14 Number of reserved (boot) sectors */ - unsigned char nfat; /* 16 Number of FAT tables hopefully 2 */ - unsigned short dirents; /* 17 Number of directory slots */ - unsigned short psect; /* 19 Total sectors on disk */ - unsigned char descr; /* 21 Media descriptor=first byte of FAT */ - unsigned short fatlen; /* 22 Sectors in FAT */ - unsigned short nsect; /* 24 Sectors/track */ - unsigned short nheads; /* 26 Heads */ - unsigned int nhs; /* 28 number of hidden sectors */ - unsigned int bigsect; /* 32 big total sectors */ - unsigned char physdrive; /* 36 physical drive ? */ - unsigned char reserved; /* 37 reserved */ - unsigned char dos4; /* 38 dos > 4.0 diskette */ - unsigned int serial; /* 39 serial number */ - char label [LABEL_LG]; /* 43 disk label */ - char fat_type [8]; /* 54 FAT type */ - unsigned char res_2m; /* 62 reserved by 2M */ - unsigned char CheckSum; /* 63 2M checksum (not used) */ - unsigned char fmt_2mf; /* 64 2MF format version */ - unsigned char wt; /* 65 1 if write track after format */ - unsigned char rate_0; /* 66 data transfer rate on track 0 */ - unsigned char rate_any; /* 67 data transfer rate on track<>0 */ - unsigned short BootP; /* 68 offset to boot program */ - unsigned short Infp0; /* 70 T1: information for track 0 */ - unsigned short InfpX; /* 72 T2: information for track<>0 */ - unsigned short InfTm; /* 74 T3: track sectors size table */ - unsigned short DateF; /* 76 Format date */ - unsigned short TimeF; /* 78 Format time */ - unsigned char junk [BOOTSIZE - 80]; /* 80 remaining data */ -} __attribute__ ((packed)) BootSector_t; - -/* Structure d'une entree de repertoire */ -typedef struct directory { - char name [8]; /* file name */ - char ext [3]; /* file extension */ - unsigned char attr; /* attribute byte */ - unsigned char Case; /* case of short filename */ - unsigned char reserved [9]; /* ?? */ - unsigned char time [2]; /* time stamp */ - unsigned char date [2]; /* date stamp */ - unsigned short start; /* starting cluster number */ - unsigned int size; /* size of the file */ -} __attribute__ ((packed)) Directory_t; - - -#define MAX_VFAT_SUBENTRIES 20 -#define VSE_NAMELEN 13 - -#define VSE1SIZE 5 -#define VSE2SIZE 6 -#define VSE3SIZE 2 - -#define VBUFSIZE ((MAX_VFAT_SUBENTRIES * VSE_NAMELEN) + 1) - -#define MAX_VNAMELEN (255) - -#define VSE_PRESENT 0x01 -#define VSE_LAST 0x40 -#define VSE_MASK 0x1f - -/* Flag used by vfat_lookup */ -#define DO_OPEN 1 -#define ACCEPT_PLAIN 0x20 -#define ACCEPT_DIR 0x10 -#define ACCEPT_LABEL 0x08 -#define SINGLE 2 -#define MATCH_ANY 0x40 - -struct vfat_subentry { - unsigned char id; /* VSE_LAST pour la fin, VSE_MASK */ - /* pour un VSE */ - char text1 [VSE1SIZE * 2]; /* Caracteres encodes sur 16 bits */ - unsigned char attribute; /* 0x0f pour les VFAT */ - unsigned char hash1; /* toujours 0 */ - unsigned char sum; /* Checksum du nom court */ - char text2 [VSE2SIZE * 2]; /* Caracteres encodes sur 16 bits */ - unsigned char sector_l; /* 0 pour les VFAT */ - unsigned char sector_u; /* 0 pour les VFAT */ - char text3 [VSE3SIZE * 2]; /* Caracteres encodes sur 16 bits */ -} __attribute__ ((packed)) ; - -struct vfat_state { - char name [VBUFSIZE]; - int status; /* is now a bit map of 32 bits */ - int subentries; - unsigned char sum; /* no need to remember the sum for each */ - /* entry, it is the same anyways */ -} __attribute__ ((packed)) ; - -/* Conversion macros */ -#define DOS_YEAR(dir) (((dir)->date[1] >> 1) + 1980) -#define DOS_MONTH(dir) (((((dir)->date[1]&0x1) << 3) + ((dir)->date[0] >> 5))) -#define DOS_DAY(dir) ((dir)->date[0] & 0x1f) -#define DOS_HOUR(dir) ((dir)->time[1] >> 3) -#define DOS_MINUTE(dir) (((((dir)->time[1]&0x7) << 3) + ((dir)->time[0] >> 5))) -#define DOS_SEC(dir) (((dir)->time[0] & 0x1f) * 2) - - -#endif diff --git a/fs/fdos/fat.c b/fs/fdos/fat.c deleted file mode 100644 index 408fec76000..00000000000 --- a/fs/fdos/fat.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -/*----------------------------------------------------------------------------- - * fat_decode -- - *----------------------------------------------------------------------------- - */ -unsigned int fat_decode (Fs_t *fs, unsigned int num) -{ - unsigned int start = num * 3 / 2; - unsigned char *address = fs -> fat_buf + start; - - if (num < 2 || start + 1 > (fs -> fat_len * SZ_STD_SECTOR)) - return 1; - - if (num & 1) - return ((address [1] & 0xff) << 4) | ((address [0] & 0xf0 ) >> 4); - else - return ((address [1] & 0xf) << 8) | (address [0] & 0xff ); -} -/*----------------------------------------------------------------------------- - * check_fat -- - *----------------------------------------------------------------------------- - */ -static int check_fat (Fs_t *fs) -{ - int i, f; - - /* Cluster verification */ - for (i = 3 ; i < fs -> num_clus; i++){ - f = fat_decode (fs, i); - if (f < FAT12_LAST && f > fs -> num_clus){ - /* Wrong cluster number detected */ - return (-1); - } - } - return (0); -} -/*----------------------------------------------------------------------------- - * read_one_fat -- - *----------------------------------------------------------------------------- - */ -static int read_one_fat (BootSector_t *boot, Fs_t *fs, int nfat) -{ - if (dev_read (fs -> fat_buf, - (fs -> fat_start + nfat * fs -> fat_len), - fs -> fat_len) < 0) { - return (-1); - } - - if (fs -> fat_buf [0] || fs -> fat_buf [1] || fs -> fat_buf [2]) { - if ((fs -> fat_buf [0] != boot -> descr && - (fs -> fat_buf [0] != 0xf9 || boot -> descr != MEDIA_STD)) || - fs -> fat_buf [0] < MEDIA_STD){ - /* Unknown Media */ - return (-1); - } - if (fs -> fat_buf [1] != 0xff || fs -> fat_buf [2] != 0xff){ - /* FAT doesn't start with good values */ - return (-1); - } - } - - if (fs -> num_clus >= FAT12_MAX_NB) { - /* Too much clusters */ - return (-1); - } - - return check_fat (fs); -} -/*----------------------------------------------------------------------------- - * read_fat -- - *----------------------------------------------------------------------------- - */ -int read_fat (BootSector_t *boot, Fs_t *fs) -{ - unsigned int buflen; - int i; - - /* Allocate Fat Buffer */ - buflen = fs -> fat_len * SZ_STD_SECTOR; - if (fs -> fat_buf) { - free (fs -> fat_buf); - } - - if ((fs -> fat_buf = malloc (buflen)) == NULL) { - return (-1); - } - - /* Try to read each Fat */ - for (i = 0; i< fs -> nb_fat; i++){ - if (read_one_fat (boot, fs, i) == 0) { - /* Fat is OK */ - fs -> num_fat = i; - break; - } - } - - if (i == fs -> nb_fat){ - return (-1); - } - - if (fs -> fat_len > (((fs -> num_clus + 2) * - (FAT_BITS / 4) -1 ) / 2 / - SZ_STD_SECTOR + 1)) { - return (-1); - } - return (0); -} diff --git a/fs/fdos/fdos.c b/fs/fdos/fdos.c deleted file mode 100644 index 4e2f4791915..00000000000 --- a/fs/fdos/fdos.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -const char *month [] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"}; - -Fs_t fs; -File_t file; - -/*----------------------------------------------------------------------------- - * dos_open -- - *----------------------------------------------------------------------------- - */ -int dos_open(char *name) -{ - int lg; - int entry; - char *fname; - - /* We need to suppress the " char around the name */ - if (name [0] == '"') { - name ++; - } - lg = strlen (name); - if (name [lg - 1] == '"') { - name [lg - 1] = '\0'; - } - - /* Open file system */ - if (fs_init (&fs) < 0) { - return -1; - } - - /* Init the file descriptor */ - file.name = name; - file.fs = &fs; - - /* find the subdirectory containing the file */ - if (open_subdir (&file) < 0) { - return (-1); - } - - fname = basename (name); - - /* if we try to open root directory */ - if (*fname == '\0') { - file.file = file.subdir; - return (0); - } - - /* find the file in the subdir */ - entry = 0; - if (vfat_lookup (&file.subdir, - file.fs, - &file.file.dir, - &entry, - 0, - fname, - ACCEPT_DIR | ACCEPT_PLAIN | SINGLE | DO_OPEN, - 0, - &file.file) != 0) { - /* File not found */ - printf ("File not found\n"); - return (-1); - } - - return 0; -} - -/*----------------------------------------------------------------------------- - * dos_read -- - *----------------------------------------------------------------------------- - */ -int dos_read (ulong addr) -{ - int read = 0, nb; - - /* Try to boot a directory ? */ - if (file.file.dir.attr & (ATTR_DIRECTORY | ATTR_VOLUME)) { - printf ("Unable to boot %s !!\n", file.name); - return (-1); - } - while (read < file.file.FileSize) { - PRINTF ("read_file (%ld)\n", (file.file.FileSize - read)); - nb = read_file (&fs, - &file.file, - (char *)addr + read, - read, - (file.file.FileSize - read)); - PRINTF ("read_file -> %d\n", nb); - if (nb < 0) { - printf ("read error\n"); - return (-1); - } - read += nb; - } - return (read); -} -/*----------------------------------------------------------------------------- - * dos_dir -- - *----------------------------------------------------------------------------- - */ -int dos_dir (void) -{ - int entry; - Directory_t dir; - char *name; - - - if ((file.file.dir.attr & ATTR_DIRECTORY) == 0) { - printf ("%s: not a directory !!\n", file.name); - return (1); - } - entry = 0; - if ((name = malloc (MAX_VNAMELEN + 1)) == NULL) { - PRINTF ("Allcation error\n"); - return (1); - } - - while (vfat_lookup (&file.file, - file.fs, - &dir, - &entry, - 0, - NULL, - ACCEPT_DIR | ACCEPT_PLAIN | MATCH_ANY, - name, - NULL) == 0) { - /* Display file info */ - printf ("%3.3s %9d %s %02d %04d %02d:%02d:%02d %s\n", - (dir.attr & ATTR_DIRECTORY) ? "dir" : " ", - __le32_to_cpu (dir.size), - month [DOS_MONTH (&dir) - 1], - DOS_DAY (&dir), - DOS_YEAR (&dir), - DOS_HOUR (&dir), - DOS_MINUTE (&dir), - DOS_SEC (&dir), - name); - - } - free (name); - return (0); -} diff --git a/fs/fdos/fdos.h b/fs/fdos/fdos.h deleted file mode 100644 index 2d8fe9d13d2..00000000000 --- a/fs/fdos/fdos.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FDOS_H_ -#define _FDOS_H_ - - -#undef FDOS_DEBUG - -#ifdef FDOS_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* Data structure describing media */ -typedef struct fs -{ - unsigned long tot_sectors; - - int cluster_size; - int num_clus; - - int fat_start; - int fat_len; - int nb_fat; - int num_fat; - - int dir_start; - int dir_len; - - unsigned char *fat_buf; - -} Fs_t; - -/* Data structure describing one file system slot */ -typedef struct slot { - int (*map) (struct fs *fs, - struct slot *file, - int where, - int *len); - unsigned long FileSize; - - unsigned short int FirstAbsCluNr; - unsigned short int PreviousAbsCluNr; - unsigned short int PreviousRelCluNr; - - Directory_t dir; -} Slot_t; - -typedef struct file { - char *name; - int Case; - Fs_t *fs; - Slot_t subdir; - Slot_t file; -} File_t; - - -/* dev.c */ -int dev_read (void *buffer, int where, int len); -int dev_open (void); -int check_dev (BootSector_t *boot, Fs_t *fs); - -/* fat.c */ -unsigned int fat_decode (Fs_t *fs, unsigned int num); -int read_fat (BootSector_t *boot, Fs_t *fs); - -/* vfat.c */ -int vfat_lookup (Slot_t *dir, - Fs_t *fs, - Directory_t *dirent, - int *entry, - int *vfat_start, - char *filename, - int flags, - char *outname, - Slot_t *file); - -/* subdir.c */ -char *basename (char *name); -int open_subdir (File_t *desc); -int open_file (Slot_t *file, Directory_t *dir); -int read_file (Fs_t *fs, - Slot_t *file, - char *buf, - int where, - int len); -void init_subdir (void); - -/* fs.c */ -int fs_init (Fs_t *fs); - - -#endif diff --git a/fs/fdos/fs.c b/fs/fdos/fs.c deleted file mode 100644 index 39d3eae20d9..00000000000 --- a/fs/fdos/fs.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -/*----------------------------------------------------------------------------- - * fill_fs -- Read info on file system - *----------------------------------------------------------------------------- - */ -static int fill_fs (BootSector_t *boot, Fs_t *fs) -{ - - fs -> fat_start = __le16_to_cpu (boot -> nrsvsect); - fs -> fat_len = __le16_to_cpu (boot -> fatlen); - fs -> nb_fat = boot -> nfat; - - fs -> dir_start = fs -> fat_start + fs -> nb_fat * fs -> fat_len; - fs -> dir_len = __le16_to_cpu (boot -> dirents) * MDIR_SIZE / SZ_STD_SECTOR; - fs -> cluster_size = boot -> clsiz; - fs -> num_clus = (fs -> tot_sectors - fs -> dir_start - fs -> dir_len) / fs -> cluster_size; - - return (0); -} - -/*----------------------------------------------------------------------------- - * fs_init -- - *----------------------------------------------------------------------------- - */ -int fs_init (Fs_t *fs) -{ - BootSector_t *boot; - - /* Initialize physical device */ - if (dev_open () < 0) { - PRINTF ("Unable to initialize the fdc\n"); - return (-1); - } - init_subdir (); - - /* Allocate space for read the boot sector */ - if ((boot = (BootSector_t *)malloc (sizeof (BootSector_t))) == NULL) { - PRINTF ("Unable to allocate space for boot sector\n"); - return (-1); - } - - /* read boot sector */ - if (dev_read (boot, 0, 1)){ - PRINTF ("Error during boot sector read\n"); - free (boot); - return (-1); - } - - /* we verify it'a a DOS diskette */ - if (boot -> jump [0] != JUMP_0_1 && boot -> jump [0] != JUMP_0_2) { - PRINTF ("Not a DOS diskette\n"); - free (boot); - return (-1); - } - - if (boot -> descr < MEDIA_STD) { - /* We handle only recent medias (type F0) */ - PRINTF ("unrecognized diskette type\n"); - free (boot); - return (-1); - } - - if (check_dev (boot, fs) < 0) { - PRINTF ("Bad diskette\n"); - free (boot); - return (-1); - } - - if (fill_fs (boot, fs) < 0) { - free (boot); - - return (-1); - } - - /* Read FAT */ - if (read_fat (boot, fs) < 0) { - free (boot); - return (-1); - } - - free (boot); - return (0); -} diff --git a/fs/fdos/subdir.c b/fs/fdos/subdir.c deleted file mode 100644 index 97f6fb71020..00000000000 --- a/fs/fdos/subdir.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - -static int cache_sect; -static unsigned char cache [SZ_STD_SECTOR]; - - -#define min(x,y) ((x)<(y)?(x):(y)) - -static int descend (Slot_t *parent, - Fs_t *fs, - char *path); - -/*----------------------------------------------------------------------------- - * init_subdir -- - *----------------------------------------------------------------------------- - */ -void init_subdir (void) -{ - cache_sect = -1; -} -/*----------------------------------------------------------------------------- - * basename -- - *----------------------------------------------------------------------------- - */ -char *basename (char *name) -{ - register char *cptr; - - if (!name || !*name) { - return (""); - } - - for (cptr= name; *cptr++; ); - while (--cptr >= name) { - if (*cptr == '/') { - return (cptr + 1); - } - } - return(name); -} -/*----------------------------------------------------------------------------- - * root_map -- - *----------------------------------------------------------------------------- - */ -static int root_map (Fs_t *fs, Slot_t *file, int where, int *len) -{ - *len = min (*len, fs -> dir_len * SZ_STD_SECTOR - where); - if (*len < 0 ) { - *len = 0; - return (-1); - } - return fs -> dir_start * SZ_STD_SECTOR + where; -} -/*----------------------------------------------------------------------------- - * normal_map -- - *----------------------------------------------------------------------------- - */ -static int normal_map (Fs_t *fs, Slot_t *file, int where, int *len) -{ - int offset; - int NrClu; - unsigned short RelCluNr; - unsigned short CurCluNr; - unsigned short NewCluNr; - unsigned short AbsCluNr; - int clus_size; - - clus_size = fs -> cluster_size * SZ_STD_SECTOR; - offset = where % clus_size; - - *len = min (*len, file -> FileSize - where); - - if (*len < 0 ) { - *len = 0; - return (0); - } - - if (file -> FirstAbsCluNr < 2){ - *len = 0; - return (0); - } - - RelCluNr = where / clus_size; - - if (RelCluNr >= file -> PreviousRelCluNr){ - CurCluNr = file -> PreviousRelCluNr; - AbsCluNr = file -> PreviousAbsCluNr; - } else { - CurCluNr = 0; - AbsCluNr = file -> FirstAbsCluNr; - } - - - NrClu = (offset + *len - 1) / clus_size; - while (CurCluNr <= RelCluNr + NrClu) { - if (CurCluNr == RelCluNr){ - /* we have reached the beginning of our zone. Save - * coordinates */ - file -> PreviousRelCluNr = RelCluNr; - file -> PreviousAbsCluNr = AbsCluNr; - } - NewCluNr = fat_decode (fs, AbsCluNr); - if (NewCluNr == 1 || NewCluNr == 0) { - PRINTF("Fat problem while decoding %d %x\n", - AbsCluNr, NewCluNr); - return (-1); - } - if (CurCluNr == RelCluNr + NrClu) { - break; - } - - if (CurCluNr < RelCluNr && NewCluNr == FAT12_END) { - *len = 0; - return 0; - } - - if (CurCluNr >= RelCluNr && NewCluNr != AbsCluNr + 1) - break; - CurCluNr++; - AbsCluNr = NewCluNr; - } - - *len = min (*len, (1 + CurCluNr - RelCluNr) * clus_size - offset); - - return (((file -> PreviousAbsCluNr - 2) * fs -> cluster_size + - fs -> dir_start + fs -> dir_len) * - SZ_STD_SECTOR + offset); -} -/*----------------------------------------------------------------------------- - * open_subdir -- open the subdir containing the file - *----------------------------------------------------------------------------- - */ -int open_subdir (File_t *desc) -{ - char *pathname; - char *tmp, *s, *path; - char terminator; - - if ((pathname = (char *)malloc (MAX_PATH)) == NULL) { - return (-1); - } - - strcpy (pathname, desc -> name); - - /* Suppress file name */ - tmp = basename (pathname); - *tmp = '\0'; - - /* root directory init */ - desc -> subdir.FirstAbsCluNr = 0; - desc -> subdir.FileSize = -1; - desc -> subdir.map = root_map; - desc -> subdir.dir.attr = ATTR_DIRECTORY; - - tmp = pathname; - for (s = tmp; ; ++s) { - if (*s == '/' || *s == '\0') { - path = tmp; - terminator = *s; - *s = '\0'; - if (s != tmp && strcmp (path,".")) { - if (descend (&desc -> subdir, desc -> fs, path) < 0) { - free (pathname); - return (-1); - } - } - if (terminator == 0) { - break; - } - tmp = s + 1; - } - } - free (pathname); - return (0); -} -/*----------------------------------------------------------------------------- - * descend -- - *----------------------------------------------------------------------------- - */ -static int descend (Slot_t *parent, - Fs_t *fs, - char *path) -{ - int entry; - Slot_t SubDir; - - if(path[0] == '\0' || strcmp (path, ".") == 0) { - return (0); - } - - - entry = 0; - if (vfat_lookup (parent, - fs, - &(SubDir.dir), - &entry, - 0, - path, - ACCEPT_DIR | SINGLE | DO_OPEN, - 0, - &SubDir) == 0) { - *parent = SubDir; - return (0); - } - - if (strcmp(path, "..") == 0) { - parent -> FileSize = -1; - parent -> FirstAbsCluNr = 0; - parent -> map = root_map; - return (0); - } - return (-1); -} -/*----------------------------------------------------------------------------- - * open_file -- - *----------------------------------------------------------------------------- - */ -int open_file (Slot_t *file, Directory_t *dir) -{ - int first; - unsigned long size; - - first = __le16_to_cpu (dir -> start); - - if(first == 0 && - (dir -> attr & ATTR_DIRECTORY) != 0) { - file -> FirstAbsCluNr = 0; - file -> FileSize = -1; - file -> map = root_map; - return (0); - } - - if ((dir -> attr & ATTR_DIRECTORY) != 0) { - size = (1UL << 31) - 1; - } - else { - size = __le32_to_cpu (dir -> size); - } - - file -> map = normal_map; - file -> FirstAbsCluNr = first; - file -> PreviousRelCluNr = 0xffff; - file -> FileSize = size; - return (0); -} -/*----------------------------------------------------------------------------- - * read_file -- - *----------------------------------------------------------------------------- - */ -int read_file (Fs_t *fs, - Slot_t *file, - char *buf, - int where, - int len) -{ - int pos; - int read, nb, sect, offset; - - pos = file -> map (fs, file, where, &len); - if (pos < 0) { - return -1; - } - if (len == 0) { - return (0); - } - - /* Compute sector number */ - sect = pos / SZ_STD_SECTOR; - offset = pos % SZ_STD_SECTOR; - read = 0; - - if (offset) { - /* Read doesn't start at the sector beginning. We need to use our */ - /* cache */ - if (sect != cache_sect) { - if (dev_read (cache, sect, 1) < 0) { - return (-1); - } - cache_sect = sect; - } - nb = min (len, SZ_STD_SECTOR - offset); - - memcpy (buf, cache + offset, nb); - read += nb; - len -= nb; - sect += 1; - } - - if (len > SZ_STD_SECTOR) { - nb = (len - 1) / SZ_STD_SECTOR; - if (dev_read (buf + read, sect, nb) < 0) { - return ((read) ? read : -1); - } - /* update sector position */ - sect += nb; - - /* Update byte position */ - nb *= SZ_STD_SECTOR; - read += nb; - len -= nb; - } - - if (len) { - if (sect != cache_sect) { - if (dev_read (cache, sect, 1) < 0) { - return ((read) ? read : -1); - cache_sect = -1; - } - cache_sect = sect; - } - - memcpy (buf + read, cache, len); - read += len; - } - return (read); -} diff --git a/fs/fdos/vfat.c b/fs/fdos/vfat.c deleted file mode 100644 index 2b87d0f5a74..00000000000 --- a/fs/fdos/vfat.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - -static int dir_read (Fs_t *fs, - Slot_t *dir, - Directory_t *dirent, - int num, - struct vfat_state *v); - -static int unicode_read (char *in, char *out, int num); -static int match (const char *s, const char *p); -static unsigned char sum_shortname (char *name); -static int check_vfat (struct vfat_state *v, Directory_t *dir); -static char *conv_name (char *name, char *ext, char Case, char *ans); - - -/*----------------------------------------------------------------------------- - * clear_vfat -- - *----------------------------------------------------------------------------- - */ -static void clear_vfat (struct vfat_state *v) -{ - v -> subentries = 0; - v -> status = 0; -} - -/*----------------------------------------------------------------------------- - * vfat_lookup -- - *----------------------------------------------------------------------------- - */ -int vfat_lookup (Slot_t *dir, - Fs_t *fs, - Directory_t *dirent, - int *entry, - int *vfat_start, - char *filename, - int flags, - char *outname, - Slot_t *file) -{ - int found; - struct vfat_state vfat; - char newfile [VSE_NAMELEN]; - int vfat_present = 0; - - if (*entry == -1) { - return -1; - } - - found = 0; - clear_vfat (&vfat); - while (1) { - if (dir_read (fs, dir, dirent, *entry, &vfat) < 0) { - if (vfat_start) { - *vfat_start = *entry; - } - break; - } - (*entry)++; - - /* Empty slot */ - if (dirent -> name[0] == '\0'){ - if (vfat_start == 0) { - break; - } - continue; - } - - if (dirent -> attr == ATTR_VSE) { - /* VSE entry, continue */ - continue; - } - if ( (dirent -> name [0] == DELMARK) || - ((dirent -> attr & ATTR_DIRECTORY) != 0 && - (flags & ACCEPT_DIR) == 0) || - ((dirent -> attr & ATTR_VOLUME) != 0 && - (flags & ACCEPT_LABEL) == 0) || - (((dirent -> attr & (ATTR_DIRECTORY | ATTR_VOLUME)) == 0) && - (flags & ACCEPT_PLAIN) == 0)) { - clear_vfat (&vfat); - continue; - } - - vfat_present = check_vfat (&vfat, dirent); - if (vfat_start) { - *vfat_start = *entry - 1; - if (vfat_present) { - *vfat_start -= vfat.subentries; - } - } - - if (dirent -> attr & ATTR_VOLUME) { - strncpy (newfile, dirent -> name, 8); - newfile [8] = '\0'; - strncat (newfile, dirent -> ext, 3); - newfile [11] = '\0'; - } - else { - conv_name (dirent -> name, dirent -> ext, dirent -> Case, newfile); - } - - if (flags & MATCH_ANY) { - found = 1; - break; - } - - if ((vfat_present && match (vfat.name, filename)) || - (match (newfile, filename))) { - found = 1; - break; - } - clear_vfat (&vfat); - } - - if (found) { - if ((flags & DO_OPEN) && file) { - if (open_file (file, dirent) < 0) { - return (-1); - } - } - if (outname) { - if (vfat_present) { - strcpy (outname, vfat.name); - } - else { - strcpy (outname, newfile); - } - } - return (0); /* File found */ - } else { - *entry = -1; - return -1; /* File not found */ - } -} - -/*----------------------------------------------------------------------------- - * dir_read -- Read one directory entry - *----------------------------------------------------------------------------- - */ -static int dir_read (Fs_t *fs, - Slot_t *dir, - Directory_t *dirent, - int num, - struct vfat_state *v) -{ - - /* read the directory entry */ - if (read_file (fs, - dir, - (char *)dirent, - num * MDIR_SIZE, - MDIR_SIZE) != MDIR_SIZE) { - return (-1); - } - - if (v && (dirent -> attr == ATTR_VSE)) { - struct vfat_subentry *vse; - unsigned char id, last_flag; - char *c; - - vse = (struct vfat_subentry *) dirent; - id = vse -> id & VSE_MASK; - last_flag = (vse -> id & VSE_LAST); - if (id > MAX_VFAT_SUBENTRIES) { - /* Invalid VSE entry */ - return (-1); - } - - - /* Decode VSE */ - if(v -> sum != vse -> sum) { - clear_vfat (v); - v -> sum = vse -> sum; - } - - - v -> status |= 1 << (id - 1); - if (last_flag) { - v -> subentries = id; - } - - c = &(v -> name [VSE_NAMELEN * (id - 1)]); - c += unicode_read (vse->text1, c, VSE1SIZE); - c += unicode_read (vse->text2, c, VSE2SIZE); - c += unicode_read (vse->text3, c, VSE3SIZE); - - if (last_flag) { - *c = '\0'; /* Null terminate long name */ - } - - } - return (0); -} - -/*----------------------------------------------------------------------------- - * unicode_read -- - *----------------------------------------------------------------------------- - */ -static int unicode_read (char *in, char *out, int num) -{ - int j; - - for (j = 0; j < num; ++j) { - if (in [1]) - *out = '_'; - else - *out = in [0]; - out ++; - in += 2; - } - return num; -} - -/*----------------------------------------------------------------------------- - * match -- - *----------------------------------------------------------------------------- - */ -static int match (const char *s, const char *p) -{ - - for (; *p != '\0'; ) { - if (toupper (*s) != toupper (*p)) { - return (0); - } - p++; - s++; - } - - if (*s != '\0') { - return (0); - } - else { - return (1); - } -} -/*----------------------------------------------------------------------------- - * sum_shortname -- - *----------------------------------------------------------------------------- - */ -static unsigned char sum_shortname (char *name) -{ - unsigned char sum; - int j; - - for (j = sum = 0; j < 11; ++j) { - sum = ((sum & 1) ? 0x80 : 0) + (sum >> 1) + - (name [j] ? name [j] : ' '); - } - return (sum); -} -/*----------------------------------------------------------------------------- - * check_vfat -- - * Return 1 if long name is valid, 0 else - *----------------------------------------------------------------------------- - */ -static int check_vfat (struct vfat_state *v, Directory_t *dir) -{ - char name[12]; - - if (v -> subentries == 0) { - return 0; - } - - strncpy (name, dir -> name, 8); - strncpy (name + 8, dir -> ext, 3); - name [11] = '\0'; - - if (v -> sum != sum_shortname (name)) { - return 0; - } - - if( (v -> status & ((1 << v -> subentries) - 1)) != - (1 << v -> subentries) - 1) { - return 0; - } - v->name [VSE_NAMELEN * v -> subentries] = 0; - - return 1; -} -/*----------------------------------------------------------------------------- - * conv_name -- - *----------------------------------------------------------------------------- - */ -static char *conv_name (char *name, char *ext, char Case, char *ans) -{ - char tname [9], text [4]; - int i; - - i = 0; - while (i < 8 && name [i] != ' ' && name [i] != '\0') { - tname [i] = name [i]; - i++; - } - tname [i] = '\0'; - - if (Case & BASECASE) { - for (i = 0; i < 8 && tname [i]; i++) { - tname [i] = tolower (tname [i]); - } - } - - i = 0; - while (i < 3 && ext [i] != ' ' && ext [i] != '\0') { - text [i] = ext [i]; - i++; - } - text [i] = '\0'; - - if (Case & EXTCASE){ - for (i = 0; i < 3 && text [i]; i++) { - text [i] = tolower (text [i]); - } - } - - if (*text) { - strcpy (ans, tname); - strcat (ans, "."); - strcat (ans, text); - } - else { - strcpy(ans, tname); - } - return (ans); -} diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 3e8983f2443..2c2a05bce11 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -38,7 +38,6 @@ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ -#define CONFIG_CMD_FDOS /* Floppy DOS support */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_FUSE /* Device fuse support */ -- cgit v1.3.1 From 29235b73373f28f2516d2eafbf6ec76ecf8051a3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 5 Feb 2014 20:49:21 -0700 Subject: ARM: rpi_b: convert to use distro defaults Modify the rpi_b board to include the "distro defaults" header, so that all the config options distros expect are enabled. Remove any #defines that enable the same options from the rpi_b.h. Signed-off-by: Stephen Warren --- include/configs/rpi_b.h | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 976ceaa9c1d..202c9c309fc 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -147,37 +147,34 @@ #define CONFIG_BOOTDELAY 2 /* Shell */ -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_MAXARGS 8 #define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE /* Commands */ #include -#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_GPIO #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT -/* Some things don't make sense on this HW or yet */ -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SAVEENV -/* Device tree support for bootm/bootz */ -#define CONFIG_OF_LIBFDT +/* Device tree support */ #define CONFIG_OF_BOARD_SETUP /* ATAGs support for bootm/bootz */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG +#include + +/* Some things don't make sense on this HW or yet */ +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SAVEENV +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING + #endif -- cgit v1.3.1 From 5c92d4823d2d5de03ea63cb3fbfc898c39cf199c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 5 Feb 2014 20:49:22 -0700 Subject: ARM: rpi_b: load /uEnv.txt from MMC at startup The Pi has no flash to store an environment in the usual fashion. However, the user may wish to customize the environment. We know that the SD card must be present, since that's where the boot ROM has loaded U-Boot from. So, load uEnv.txt from there early during boot. This allows the user to e.g. customize boot_targets, in order to automatically select network boot. Signed-off-by: Stephen Warren --- include/configs/rpi_b.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 202c9c309fc..4b5a0c2150f 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -95,6 +95,11 @@ #define CONFIG_SYS_LOAD_ADDR 0x1000000 #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_PREBOOT \ + "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \ + "env import -t ${loadaddr} ${filesize}; " \ + "fi" + /* * Memory layout for where various images get loaded by boot scripts: * -- cgit v1.3.1 From 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:42 -0800 Subject: driver/ddr: Change Freescale ARM DDR driver to support both big and little endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun --- README | 6 +++ drivers/ddr/fsl/arm_ddr_gen3.c | 103 +++++++++++++++++++++-------------------- drivers/ddr/fsl/ctrl_regs.c | 4 +- drivers/ddr/fsl/util.c | 12 ++--- include/fsl_ddr.h | 9 ++++ 5 files changed, 75 insertions(+), 59 deletions(-) (limited to 'include') diff --git a/README b/README index 6668631bccc..413d6828292 100644 --- a/README +++ b/README @@ -486,6 +486,12 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + + CONFIG_SYS_FSL_DDR_LE + Defines the DDR controller register space as Little Endian + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index bf113908fd4..d4ed9aec2ae 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -11,6 +11,7 @@ #include #include #include +#include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -63,54 +64,54 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, goto step2; if (regs->ddr_eor) - out_be32(&ddr->eor, regs->ddr_eor); + ddr_out32(&ddr->eor, regs->ddr_eor); for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs0_config, regs->cs[i].config); + ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs1_config, regs->cs[i].config); + ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs2_config, regs->cs[i].config); + ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs3_config, regs->cs[i].config); + ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); } } - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); - out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); - out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); - out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); - out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); - out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); - out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); + ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); + ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); + ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); + ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); + ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); + ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); + ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); + ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU /* * Skip these two registers if running on emulator @@ -118,23 +119,23 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, */ if (regs->ddr_wrlvl_cntl_2) - out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); if (regs->ddr_wrlvl_cntl_3) - out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); + ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); #endif - out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); - out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); - out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); - out_be32(&ddr->err_disable, regs->err_disable); - out_be32(&ddr->err_int_en, regs->err_int_en); + ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + ddr_out32(&ddr->err_disable, regs->err_disable); + ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { if (regs->debug[i]) { debug("Write to debug_%d as %08x\n", i + 1, regs->debug[i]); - out_be32(&ddr->debug[i], regs->debug[i]); + ddr_out32(&ddr->debug[i], regs->debug[i]); } } @@ -155,7 +156,7 @@ step2: /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); /* * 500 painful micro-seconds must elapse between @@ -167,8 +168,8 @@ step2: asm volatile("dsb sy;isb"); /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("dsb sy;isb"); total_gb_size_per_controller = 0; @@ -202,7 +203,7 @@ step2: debug("Need to wait up to %d * 10ms\n", timeout); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && (timeout >= 0)) { udelay(10000); /* throttle polling rate */ timeout--; diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 6bf22cfbd6f..5acbc737ba0 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -25,8 +25,8 @@ static u32 fsl_ddr_get_version(void) u32 ver_major_minor_errata; ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; return ver_major_minor_errata; } diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 0658261d8da..450a4887126 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -146,21 +146,21 @@ void board_add_ram_info(int use_default) u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); #endif #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - uint32_t cs0_config = in_be32(&ddr->cs0_config); + uint32_t cs0_config = ddr_in32(&ddr->cs0_config); #endif - uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); + uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); int cas_lat; #if CONFIG_NUM_DDR_CONTROLLERS >= 2 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); + sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif #if CONFIG_NUM_DDR_CONTROLLERS >= 3 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); + sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif puts(" (DDR"); @@ -188,8 +188,8 @@ void board_add_ram_info(int use_default) puts(", 64-bit"); /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) + cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; + if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1) cas_lat += (8 << 1); printf(", CL=%d", cas_lat >> 1); if (cas_lat & 0x1) diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index e03f9db5f2e..72c0b2e94ed 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -14,6 +14,14 @@ #include +#ifdef CONFIG_SYS_FSL_DDR_LE +#define ddr_in32(a) in_le32(a) +#define ddr_out32(a, v) out_le32(a, v) +#else +#define ddr_in32(a) in_be32(a) +#define ddr_out32(a, v) out_be32(a, v) +#endif + #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names @@ -93,6 +101,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); +void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, -- cgit v1.3.1 From 6b1e1254f326940e5b65c7029f71b964bdf28fd4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:44 -0800 Subject: driver/ddr: Add 256 byte interleaving support Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun --- README | 5 +++++ drivers/ddr/fsl/ctrl_regs.c | 1 + drivers/ddr/fsl/main.c | 1 + drivers/ddr/fsl/options.c | 17 +++++++++++++++-- drivers/ddr/fsl/util.c | 3 +++ include/fsl_ddr_sdram.h | 1 + 6 files changed, 26 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/README b/README index 355e8988236..f51f17ec693 100644 --- a/README +++ b/README @@ -497,6 +497,11 @@ The following options need to be configured: same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 5acbc737ba0..0882932b070 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -145,6 +145,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, if (!popts->memctl_interleaving) break; switch (popts->memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index dee50a0789b..d62ca63c770 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -291,6 +291,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { if (pinfo->memctl_opts[i].memctl_interleaving) { switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 4aafcceaf59..b0cf046fdcd 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -818,21 +818,33 @@ unsigned int populate_memctl_options(int all_dimms_registered, * If memory controller interleaving is enabled, then the data * bus widths must be programmed identically for all memory controllers. * - * XXX: Attempt to set all controllers to the same chip select + * Attempt to set all controllers to the same chip select * interleaving mode. It will do a best effort to get the * requested ranks interleaved together such that the result * should be a subset of the requested configuration. + * + * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving + * with 256 Byte is enabled. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + ; +#else goto done; - +#endif if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d.\n", ctrl_num); popts->memctl_interleaving = 0; goto done; } popts->memctl_interleaving = 1; +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; + popts->memctl_interleaving = 1; + debug("256 Byte interleaving\n"); + goto done; +#endif /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -1085,6 +1097,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) "Memory controller interleaving disabled.\n"); } else { switch (check_intlv) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 450a4887126..ad53658fc92 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -228,6 +228,9 @@ void board_add_ram_info(int use_default) puts(" DDR Controller Interleaving Mode: "); switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_256B_INTERLEAVING: + puts("256B"); + break; case FSL_DDR_CACHE_LINE_INTERLEAVING: puts("cache line"); break; diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 16cccc77083..2a36431146d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_PAGE_INTERLEAVING 0x1 #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_256B_INTERLEAVING 0x8 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD -- cgit v1.3.1 From e38661634b3d60af80d85ce9eb570a45db4729ca Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 11 Feb 2014 11:57:26 -0800 Subject: common: Add get_effective_memsize() to memsize.c This function has been around for powerpc. It is used for systems with memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory, this feature can limit U-boot to one block without going over the limit. Signed-off-by: York Sun Acked-by: Albert ARIBAUD --- arch/arm/lib/board.c | 2 +- arch/powerpc/cpu/mpc512x/traps.c | 1 - arch/powerpc/cpu/mpc85xx/traps.c | 1 - arch/powerpc/cpu/mpc86xx/traps.c | 1 - arch/powerpc/lib/board.c | 18 ------------------ arch/powerpc/lib/bootm.c | 1 - board/freescale/c29xpcie/spl.c | 2 +- board/freescale/p1022ds/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- common/board_f.c | 11 ----------- common/cmd_log.c | 2 +- common/memsize.c | 16 +++++++++++++++- include/common.h | 1 + 13 files changed, 21 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index c320a35166b..ba62394a9d4 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -318,7 +318,7 @@ void board_init_f(ulong bootflag) gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; + addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c index 10169912b7f..9f5bcd7fc33 100644 --- a/arch/powerpc/cpu/mpc512x/traps.c +++ b/arch/powerpc/cpu/mpc512x/traps.c @@ -27,7 +27,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 3ef6e4ae160..24adbc3078f 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -35,7 +35,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c index 0b7ea3b184d..92fb537453b 100644 --- a/arch/powerpc/cpu/mpc86xx/traps.c +++ b/arch/powerpc/cpu/mpc86xx/traps.c @@ -29,7 +29,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 34bbfca5544..13d761c1f75 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -312,17 +312,6 @@ static init_fnc_t *init_sequence[] = { NULL, /* Terminate this list */ }; -ulong get_effective_memsize(void) -{ -#ifndef CONFIG_VERY_BIG_RAM - return gd->ram_size; -#else - /* limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); -#endif -} - static int __fixup_cpu(void) { return 0; @@ -343,13 +332,6 @@ int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); * initialized, and stack space is limited to a few kB. */ -#ifdef CONFIG_LOGBUFFER -unsigned long logbuffer_base(void) -{ - return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; -} -#endif - void board_init_f(ulong bootflag) { bd_t *bd; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 41fc8f7ff7a..c08b62c47e3 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern ulong get_effective_memsize(void); static ulong get_sp (void); extern void ft_fixup_num_cores(void *blob); static void set_clocks_in_mhz (bd_t *kbd); diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c index 3cfdb723b97..21117114008 100644 --- a/board/freescale/c29xpcie/spl.c +++ b/board/freescale/c29xpcie/spl.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; -ulong get_effective_memsize(void) +phys_size_t get_effective_memsize(void) { return CONFIG_SYS_L2_SIZE; } diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 7f151e38cf9..7bd9d296ee0 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -21,7 +21,7 @@ static const u32 sysclk_tbl[] = { 99999000, 11111000, 12499800, 13333200 }; -ulong get_effective_memsize(void) +phys_size_t get_effective_memsize(void) { return CONFIG_SYS_L2_SIZE; } diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 9bb071692d5..8d0d8504802 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -20,7 +20,7 @@ static const u32 sysclk_tbl[] = { 99999000, 11111000, 12499800, 13333200 }; -ulong get_effective_memsize(void) +phys_size_t get_effective_memsize(void) { return CONFIG_SYS_L2_SIZE; } diff --git a/common/board_f.c b/common/board_f.c index 02965b0df76..a973b953341 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -223,17 +223,6 @@ static int show_dram_config(void) return 0; } -ulong get_effective_memsize(void) -{ -#ifndef CONFIG_VERY_BIG_RAM - return gd->ram_size; -#else - /* limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); -#endif -} - void __dram_init_banksize(void) { #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) diff --git a/common/cmd_log.c b/common/cmd_log.c index 8164bdf4886..38d0f5edfd7 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -52,7 +52,7 @@ static char *lbuf; unsigned long __logbuffer_base(void) { - return CONFIG_SYS_SDRAM_BASE + gd->ram_size - LOGBUFF_LEN; + return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; } unsigned long logbuffer_base(void) __attribute__((weak, alias("__logbuffer_base"))); diff --git a/common/memsize.c b/common/memsize.c index 73b92c8a00e..589400d3b14 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -5,7 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include + +DECLARE_GLOBAL_DATA_PTR; + #ifdef __PPC__ /* * At least on G2 PowerPC cores, sequential accesses to non-existent @@ -76,3 +79,14 @@ long get_ram_size(long *base, long maxsize) return (maxsize); } + +phys_size_t __weak get_effective_memsize(void) +{ +#ifndef CONFIG_VERY_BIG_RAM + return gd->ram_size; +#else + /* limit stack to what we can reasonable map */ + return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size); +#endif +} diff --git a/include/common.h b/include/common.h index 033b5d946d1..96a45a6cf70 100644 --- a/include/common.h +++ b/include/common.h @@ -461,6 +461,7 @@ void api_init (void); /* common/memsize.c */ long get_ram_size (long *, long); +phys_size_t get_effective_memsize(void); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); -- cgit v1.3.1 From da4105dfcd27c20e5cf4eb750f88938f56620d37 Mon Sep 17 00:00:00 2001 From: Lothar Felten Date: Fri, 31 Jan 2014 17:34:14 +0100 Subject: am335x: Initial support for Silica Pengwyn board This patch add support for the Silica Pengwyn board [1] The board is based on a TI AM3354 CPU [2] All jumpers removed it will boot from the SDcard, the console is on UART1 accessible via the FDTI -> USB. The on board NAND flash is supported and can act as boot medium, depending on jumper settings. USB Host, USB Device and Ethernet are also provided but untested. [1] http://www.silica.com/product/silica-pengwyn-board.html [2] http://www.ti.com/product/am3354 Signed-off-by: Lothar Felten [trini: Move CONFIG_BOARD_LATE_INIT into am335x_evm.h, drop unused spi0_pin_mux from Pengwyn support] Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 16 +++ board/silica/pengwyn/Makefile | 13 ++ board/silica/pengwyn/board.c | 207 +++++++++++++++++++++++++++ board/silica/pengwyn/board.h | 15 ++ board/silica/pengwyn/mux.c | 98 +++++++++++++ boards.cfg | 1 + include/configs/am335x_evm.h | 1 + include/configs/pengwyn.h | 208 ++++++++++++++++++++++++++++ include/configs/ti_am335x_common.h | 1 - 9 files changed, 559 insertions(+), 1 deletion(-) create mode 100644 board/silica/pengwyn/Makefile create mode 100644 board/silica/pengwyn/board.c create mode 100644 board/silica/pengwyn/board.h create mode 100644 board/silica/pengwyn/mux.c create mode 100644 include/configs/pengwyn.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index fbe599d1ab3..4d899528f5b 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -58,6 +58,22 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + /* Micron MT41J64M16JT-125 */ #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile new file mode 100644 index 00000000000..c8b4f9a2808 --- /dev/null +++ b/board/silica/pengwyn/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c new file mode 100644 index 00000000000..a553129d29d --- /dev/null +++ b/board/silica/pengwyn/board.c @@ -0,0 +1,207 @@ +/* + * board.c + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if defined(CONFIG_SPL_BUILD) + +/* DDR3 RAM timings */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128MJT187E_RD_DQS, + .datawdsratio0 = MT41K128MJT187E_WR_DQS, + .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE, + .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128MJT187E_RATIO, + .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd1csratio = MT41K128MJT187E_RATIO, + .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd2csratio = MT41K128MJT187E_RATIO, + .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128MJT187E_EMIF_SDCFG, + .ref_ctrl = MT41K128MJT187E_EMIF_SDREF, + .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1, + .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2, + .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3, + .zq_config = MT41K128MJT187E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr_266 = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_303 = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_400 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* + * The pengwyn board uses the TPS650250 PMIC without I2C + * interface and will output the following fixed voltages: + * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) + * VLDO1=1V8 (IO) VLDO2=1V8(IO) + * Vcore=1V1 is fixed, generated by TPS62231 + */ + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* 720MHz cpu, this might change on newer board revisions */ + dpll_mpu_opp100.m = MPUPLL_M_720; + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + /* future configs can return other clock settings */ + return &dpll_ddr_303; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + config_ddr(303, &ddr3_ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif /* if CONFIG_SPL_BUILD */ + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return n; + } + + writel(MII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* if CONFIG_DRIVER_TI_CPSW */ diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h new file mode 100644 index 00000000000..05addf6bb28 --- /dev/null +++ b/board/silica/pengwyn/board.h @@ -0,0 +1,15 @@ +/* + * board.h + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); + +#endif diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c new file mode 100644 index 00000000000..c8be440a208 --- /dev/null +++ b/board/silica/pengwyn/mux.c @@ -0,0 +1,98 @@ +/* + * mux.c + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "board.h" + +/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ + +/* I2C pins C16(scl)/C17(sda) */ +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ + {-1}, +}; + +/* MMC0 pins */ +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +/* MII pins */ +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +/* NAND pins */ +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux() +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} diff --git a/boards.cfg b/boards.cfg index 0e663d93a25..e917753259f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -256,6 +256,7 @@ Active arm armv7 am33xx phytec pcm051 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier Active arm armv7 am33xx siemens rut rut - Roger Meier +Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 73a9adb293e..96ae369c6ac 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -20,6 +20,7 @@ #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#define CONFIG_BOARD_LATE_INIT /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h new file mode 100644 index 00000000000..5a555567d02 --- /dev/null +++ b/include/configs/pengwyn.h @@ -0,0 +1,208 @@ +/* + * pengwyn.h + * + * Copyright (C) 2013 Lothar Felten + * + * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PENGWYN_H +#define __CONFIG_PENGWYN_H + +#define CONFIG_NAND +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 + +#include + +/* Clock Defines */ +#define V_OSCK 24000000 +#define V_SCLK V_OSCK + +/* set env size */ +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=am335x-pengwyn.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration: primary UART via FDTI */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_BAUDRATE 115200 + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1792k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#if defined(CONFIG_MUSB_HOST) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_SPL_BUILD) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* Disable CPSW SPL support so we fit within the 101KiB limit. */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* Network */ +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_NATSEMI + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __CONFIG_PENGWYN_H */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 91f97dd0610..7e9ca01cd5a 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -13,7 +13,6 @@ #define __CONFIG_TI_AM335X_COMMON_H__ #define CONFIG_AM33XX -#define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -- cgit v1.3.1 From 893c04e17cf74db79e052e831fe5de8323cf2aae Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Fri, 7 Feb 2014 08:07:36 +0100 Subject: board: Add support for B&R T-Series Motherboard Adds support for Bernecker & Rainer Industrieelektronik GmbH T-Series Motherboard, using TI's AM3352 SoC. Most of code is derived from TI's AM335x_EVM Signed-off-by: Hannes Petermaier --- board/BuR/common/bur_common.h | 22 +++ board/BuR/common/common.c | 216 +++++++++++++++++++++++++++++ board/BuR/tseries/Makefile | 14 ++ board/BuR/tseries/board.c | 147 ++++++++++++++++++++ board/BuR/tseries/mux.c | 225 ++++++++++++++++++++++++++++++ boards.cfg | 3 + include/configs/bur_am335x_common.h | 197 +++++++++++++++++++++++++++ include/configs/tseries.h | 265 ++++++++++++++++++++++++++++++++++++ 8 files changed, 1089 insertions(+) create mode 100644 board/BuR/common/bur_common.h create mode 100644 board/BuR/common/common.c create mode 100644 board/BuR/tseries/Makefile create mode 100644 board/BuR/tseries/board.c create mode 100644 board/BuR/tseries/mux.c create mode 100644 include/configs/bur_am335x_common.h create mode 100644 include/configs/tseries.h (limited to 'include') diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h new file mode 100644 index 00000000000..15225b0724a --- /dev/null +++ b/board/BuR/common/bur_common.h @@ -0,0 +1,22 @@ +/* + * bur_comon.h + * + * common board information header for B&R boards + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BUR_COMMON_H_ +#define _BUR_COMMON_H_ + +void blink(u32 blinks, u32 intervall, u32 pin); +void pmicsetup(u32 mpupll); +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +int board_eth_init(bd_t *bis); + +#endif diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c new file mode 100644 index 00000000000..6d187eaab20 --- /dev/null +++ b/board/BuR/common/common.c @@ -0,0 +1,216 @@ +/* + * common.c + * + * common board functions for B&R boards + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bur_common.h" + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +/* --------------------------------------------------------------------------*/ +void blink(u32 blinks, u32 intervall, u32 pin) +{ + gpio_direction_output(pin, 0); + int val = 0; + + do { + val ^= 0x01; + gpio_set_value(pin, val); + mdelay(intervall); + } while (blinks--); + + gpio_set_value(pin, 0); +} +#ifdef CONFIG_SPL_BUILD +void pmicsetup(u32 mpupll) +{ + int mpu_vdd; + int usb_cur_lim; + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + if (i2c_probe(TPS65217_CHIP_PM)) { + puts("PMIC (0x24) not found! skip further initalization.\n"); + return; + } + + /* Get the frequency which is defined by device fuses */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + printf("detected max. frequency: %d - ", dpll_mpu_opp100.m); + + if (0 != mpupll) { + dpll_mpu_opp100.m = MPUPLL_M_1000; + printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m); + } else { + puts("ok.\n"); + } + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, + usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set LDO3 to 1.8V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + /* Set LDO4 to 3.3V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +#endif /* CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +/* describing port offsets of TI's CPSW block */ +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + +#if defined(CONFIG_DRIVER_TI_CPSW) + +int board_eth_init(bd_t *bis) +{ + int rv = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC ... "); + + if (is_valid_ether_addr(mac_addr)) { + printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5] + ); + eth_setenv_enetaddr("ethaddr", mac_addr); + } + } + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + + rv = cpsw_register(&cpsw_data); + if (rv < 0) { + printf("Error %d registering CPSW switch\n", rv); + return 0; + } +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + return rv; +} +#endif /* CONFIG_DRIVER_TI_CPSW */ diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile new file mode 100644 index 00000000000..ec0d27a7aa8 --- /dev/null +++ b/board/BuR/tseries/Makefile @@ -0,0 +1,14 @@ +# +# Makefile +# +# Copyright (C) 2013 Hannes Petermaier +# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y := mux.o +endif +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c new file mode 100644 index 00000000000..f0510e599e9 --- /dev/null +++ b/board/BuR/tseries/board.c @@ -0,0 +1,147 @@ +/* + * board.c + * + * Board functions for B&R LEIT Board + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* --------------------------------------------------------------------------*/ +/* -- defines for GPIO -- */ +#define ETHLED_ORANGE (96+16) /* GPIO3_16 */ +#define REPSWITCH (0+20) /* GPIO0_20 */ + + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +/* + * called from spl_nand.c + * return 0 for loading linux, return 1 for loading u-boot + */ +int spl_start_uboot(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + blink(5, 125, ETHLED_ORANGE); + mdelay(1000); + printf("SPL: entering u-boot instead kernel image.\n"); + return 1; + } + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +#define OSC (V_OSCK/1000000) +static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + pmicsetup(1000); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ + +/* Basic board specific setup. Pinmux has been handled already. */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + gpio_direction_output(ETHLED_ORANGE, 0); + + if (0 == gpio_get_value(REPSWITCH)) { + printf("\n\n\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" + "!!!!!!! recovery switch activated !!!!!!!\n" + "!!!!!!! running usbupdate !!!!!!!\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n"); + setenv("bootcmd", "sleep 2; run netupdate;"); + } + + printf("turning on display power+backlight ... "); + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1, + 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2, + 0x62, TPS65217_MASK_ALL_BITS); /* 100% */ + printf("ok.\n"); + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c new file mode 100644 index 00000000000..3c76e969265 --- /dev/null +++ b/board/BuR/tseries/mux.c @@ -0,0 +1,225 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +#ifdef CONFIG_MMC +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; +#endif +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + /* SPI0_SCLK */ + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D0 */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D1 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_CS0 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + /* + * MII2_CRS is shared with + * NAND_WAIT0 + */ + {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ + {-1}, +}; +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif +static struct module_pin_mux gpIOs[] = { + /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ + {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */ + {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ + {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ + {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ + {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ + {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ + {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO2_0 (GPMC_nCS3) - DCOK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* + * GPIO0_7 (PWW0 OUT) + * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) + */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - REP-Switch */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, + /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ + {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, + /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_MMC) + configure_module_pin_mux(mmc1_pin_mux); +#endif + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpIOs); +} diff --git a/boards.cfg b/boards.cfg index e917753259f..897c5e3bcfe 100644 --- a/boards.cfg +++ b/boards.cfg @@ -257,6 +257,9 @@ Active arm armv7 am33xx siemens dxr2 Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier Active arm armv7 am33xx siemens rut rut - Roger Meier Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten +Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h new file mode 100644 index 00000000000..1f57bd2744f --- /dev/null +++ b/include/configs/bur_am335x_common.h @@ -0,0 +1,197 @@ +/* + * bur_am335x_common.h + * + * common parts used by B&R AM335x based boards + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BUR_AM335X_COMMON_H__ +#define __BUR_AM335X_COMMON_H__ +/* ------------------------------------------------------------------------- */ +#define CONFIG_AM33XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* Timer information */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_POWER_TPS65217 + +#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */ + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_BAUDRATE 115200 + +/* Network defines */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 4 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_NATSEMI +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* !CONFIG_SPL_BUILD, ... */ +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* + * ---------------------------------------------------------------------------- + * DDR information. We say (for simplicity) that we have 1 bank, + * always, even when we have more. We always start at 0x80000000, + * and we place the initial stack pointer in our SRAM. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX + +/* GPIO */ +#define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO +/* + * ---------------------------------------------------------------------------- + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* + * For commands to use, we take the default list and add a few other + * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH + * prior to this include, in order to skip a few commands. When we do + * have flash, if we expect these commands they must be enabled in that + * config. If desired, a specific list of desired commands can be used + * instead. + */ +#include +/* undefine commands, which we do not need */ +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CRC32 +/* define command we need always */ +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. We load U-Boot itself into memory at + * 0x80800000 for legacy reasons (to not conflict with older SPLs). We + * have our BSS be placed 1MiB after this, to allow for the default + * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. + * We have the SPL malloc pool at the end of the BSS area. + * + * ---------------------------------------------------------------------------- + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#undef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +/* General parts of the framework, required. */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h new file mode 100644 index 00000000000..8fb87ac4411 --- /dev/null +++ b/include/configs/tseries.h @@ -0,0 +1,265 @@ +/* + * tseries.h + * + * specific parts for B&R T-Series Motherboard + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TSERIES_H__ +#define __CONFIG_TSERIES_H__ + +#include +/* ------------------------------------------------------------------------- */ +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMD_BOOTZ +/*#define CONFIG_MACH_TYPE 3589*/ +#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ + +/* MMC/SD IP block */ +#if defined(CONFIG_EMMC_BOOT) + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_OMAP_HSMMC + #define CONFIG_CMD_MMC + #define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ + #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + #define CONFIG_SPL_MMC_SUPPORT +#endif /* CONFIG_EMMC_BOOT */ + +/* + * When we have SPI or NAND flash we expect to be making use of mtdparts, + * both for ease of use in U-Boot and for passing information on to + * the Linux kernel. + */ +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND) +#define CONFIG_MTD_DEVICE /* Required for mtdparts */ +#define CONFIG_CMD_MTDPARTS +#endif /* CONFIG_SPI_BOOT, ... */ + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* CONFIG_NAND */ +#endif /* CONFIG_SPL_OS_BOOT */ + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif /* CONFIG_NAND */ + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandimgsize=0x500000\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel ${nandimgsize}; " \ + "bootz ${loadaddr}\0" +#else +#define NANDARGS "" +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_MMC +#define MMCARGS \ + "silent=1\0" +#else +#define MMCARGS "" +#endif /* CONFIG_MMC */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80200000\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "rootpath=/tftpboot/tseries/rootfs-small\0" \ + "nfsopts=nolock\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "run netargs; " \ + "bootm ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" \ + NANDARGS \ + MMCARGS +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot1;" +#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + +#ifdef CONFIG_NAND +/* + * GPMC block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_CMD_NAND +/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3)," \ + "512k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env)," \ + "5m(kernel),"\ + "-(rootfs)" +#endif /* CONFIG_NAND */ + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +/* attention! not only for gadget, enables also highspeed in hostmode */ +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ + +#if defined(CONFIG_SPI_BOOT) +/* McSPI IP block */ +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ + +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#elif defined(CONFIG_NAND) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */ +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE +#else +#error "no storage for Environment defined!" +#endif +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_TSERIES_H__ */ -- cgit v1.3.1 From 072cefe07d54879816d0f17830f28198af4c2727 Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Fri, 7 Feb 2014 14:06:50 +0100 Subject: Add support for B&R KWB Motherboard Adds support for Bernecker & Rainer Industrieelektronik GmbH KWB Motherboard, using TI's AM3352 SoC. Most of code is derived from TI's AM335x_EVM Signed-off-by: Hannes Petermaier Cc: trini@ti.com --- arch/arm/include/asm/arch-am33xx/cpu.h | 6 +- board/BuR/kwb/Makefile | 12 ++ board/BuR/kwb/board.c | 240 +++++++++++++++++++++++++++++++++ board/BuR/kwb/mux.c | 195 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/kwb.h | 128 ++++++++++++++++++ 6 files changed, 580 insertions(+), 2 deletions(-) create mode 100644 board/BuR/kwb/Makefile create mode 100644 board/BuR/kwb/board.c create mode 100644 board/BuR/kwb/mux.c create mode 100644 include/configs/kwb.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 9febfa2719a..248dc4d4fcd 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -171,7 +171,8 @@ struct cm_wkuppll { unsigned int resv11[1]; unsigned int wkup_uart0ctrl; /* offset 0xB4 */ unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ - unsigned int resv12[7]; + unsigned int wkup_adctscctrl; /* offset 0xBC */ + unsigned int resv12[6]; unsigned int divm6dpllcore; /* offset 0xD8 */ }; @@ -221,7 +222,8 @@ struct cm_perpll { unsigned int tpccclkctrl; /* offset 0xBC */ unsigned int dcan0clkctrl; /* offset 0xC0 */ unsigned int dcan1clkctrl; /* offset 0xC4 */ - unsigned int resv6[2]; + unsigned int resv6; + unsigned int epwmss1clkctrl; /* offset 0xCC */ unsigned int emiffwclkctrl; /* offset 0xD0 */ unsigned int epwmss0clkctrl; /* offset 0xD4 */ unsigned int epwmss2clkctrl; /* offset 0xD8 */ diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile new file mode 100644 index 00000000000..7b04b26ae4e --- /dev/null +++ b/board/BuR/kwb/Makefile @@ -0,0 +1,12 @@ +# +# Makefile +# +# Copyright (C) 2014 Hannes Petermaier - +# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += mux.o +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c new file mode 100644 index 00000000000..8aa16bcf808 --- /dev/null +++ b/board/BuR/kwb/board.c @@ -0,0 +1,240 @@ +/* + * board.c + * + * Board functions for B&R KWB Board + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" + +/* -------------------------------------------------------------------------*/ +/* -- defines for used GPIO Hardware -- */ +#define KEY (0+4) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) +#define USB2SD_NRST (32+29) +#define USB2SD_PWR (96+13) +/* -------------------------------------------------------------------------*/ +/* -- PSOC Resetcontroller Register defines -- */ + +/* I2C Address of controller */ +#define RSTCTRL_ADDR 0x75 +/* Register for CTRL-word */ +#define RSTCTRL_CTRLREG 0x01 +/* Register for giving some information to VxWorks OS */ +#define RSTCTRL_SCRATCHREG 0x04 + +/* -- defines for RSTCTRL_CTRLREG -- */ +#define RSTCTRL_FORCE_PWR_NEN 0x0404 + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + unsigned int oldspeed; + unsigned short buf; + + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; + /* + * enable additional clocks of modules which are accessed later from + * VxWorks OS + */ + u32 *const clk_domains[] = { 0 }; + + u32 *const clk_modules_kwbspecific[] = { + &cmwkup->wkup_adctscctrl, + &cmper->spi1clkctrl, + &cmper->dcan0clkctrl, + &cmper->dcan1clkctrl, + &cmper->epwmss0clkctrl, + &cmper->epwmss1clkctrl, + &cmper->epwmss2clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1); + + /* power-OFF LCD-Display */ + gpio_direction_output(LCD_PWR, 0); + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + /* power-ON 3V3 via Resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) { + buf = RSTCTRL_FORCE_PWR_NEN; + i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); + } + +#if defined(CONFIG_AM335X_USB0) + /* power on USB2SD Controller */ + gpio_direction_output(USB2SD_PWR, 1); + mdelay(1); + /* give a reset Pulse to USB2SD Controller */ + gpio_direction_output(USB2SD_NRST, 0); + mdelay(1); + gpio_set_value(USB2SD_NRST, 1); +#endif + pmicsetup(0); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + const unsigned int ton = 250; + const unsigned int toff = 1000; + unsigned int cnt = 3; + unsigned short buf = 0xAAAA; + unsigned int oldspeed; + + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */ + + if (gpio_get_value(KEY)) { + do { + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + mdelay(ton); + /* turn off light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x01, 0xFF); + mdelay(toff); + cnt--; + if (!gpio_get_value(KEY) && + gpio_get_value(PUSH_KEY) && 1 == cnt) { + puts("updating from USB ...\n"); + setenv("bootcmd", "run usbupdate"); + break; + } else if (!gpio_get_value(KEY)) { + break; + } + } while (cnt); + } + + switch (cnt) { + case 0: + puts("3 blinks ... entering BOOT mode.\n"); + buf = 0x0000; + break; + case 1: + puts("2 blinks ... entering DIAGNOSE mode.\n"); + buf = 0x0F0F; + break; + case 2: + puts("1 blinks ... entering SERVICE mode.\n"); + buf = 0xB4B4; + break; + case 3: + puts("0 blinks ... entering RUN mode.\n"); + buf = 0x0404; + break; + } + mdelay(ton); + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + /* write bootinfo into scratchregister of resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) { + i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } + /* + * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does + * expect that vectors are there, original u-boot moves them to _start + */ + __asm__("ldr r0,=0x20000"); + __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c new file mode 100644 index 00000000000..1a5ffd57099 --- /dev/null +++ b/board/BuR/kwb/mux.c @@ -0,0 +1,195 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, + /* USB0 DrvBus Receiver disable (from romcode 0x20) */ + {OFFSET(usb0_drvvbus), (MODE(0))}, + /* USB1 DrvBus as GPIO due to HW-Workaround */ + {OFFSET(usb1_drvvbus), (MODE(7))}, + {-1}, +}; +static struct module_pin_mux spi1_pin_mux[] = { + /* SPI1_SCLK */ + {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D0 */ + {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D1 */ + {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_CS0 */ + {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan0_pin_mux[] = { + /* DCAN0 TX */ + {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN0 RX */ + {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan1_pin_mux[] = { + /* DCAN1 TX */ + {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN1 RX */ + {OFFSET(uart1_txd), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux gpios[] = { + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, + /* GPIO0_4 (SPI D1) - TA602 */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, + /* GPIO0_7 (PWW0 OUT) - CAN TERM */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */ + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)}, + /* GPIO0_30 (GPMC_WAIT0) - TA601 */ + {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO2_4 (GPMC_nWE) - TST_BAST */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ + {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ + {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */ + {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(dcan0_pin_mux); + configure_module_pin_mux(dcan1_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpios); +} diff --git a/boards.cfg b/boards.cfg index 897c5e3bcfe..462e35b178a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -260,6 +260,7 @@ Active arm armv7 am33xx silica pengwyn Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier +Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini diff --git a/include/configs/kwb.h b/include/configs/kwb.h new file mode 100644 index 00000000000..0f631c0f605 --- /dev/null +++ b/include/configs/kwb.h @@ -0,0 +1,128 @@ +/* + * kwb.h + * + * specific parts for B&R KWB Motherboard + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_KWB_H__ +#define __CONFIG_KWB_H__ + +#include +/* ------------------------------------------------------------------------- */ +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +#define CONFIG_MACH_TYPE 3589 +/* I2C IP block */ +#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000 + +/* GPIO */ +#define CONFIG_SPL_GPIO_SUPPORT + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SPL_MMC_SUPPORT + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +#endif /* CONFIG_SPL_OS_BOOT */ + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80100000\0" \ + "bootfile=arimg\0" \ + "usbboot=echo Booting from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 ${loadaddr} ${bootfile}; " \ + "usb stop; " \ + "go ${loadaddr};\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload 0; " \ + "dhcp; " \ + "tftp ${loadaddr} arimg; " \ + "go ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run usbupdate;" +#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + +/* undefine command which we not need here */ +#undef CONFIG_BOOTM_LINUX +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS +#undef CONFIG_GZIP +#undef CONFIG_ZLIB +#undef CONFIG_CMD_CRC32 + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +/* attention! not only for gadget, enables also highspeed in hostmode */ +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ + +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_TSERIES_H__ */ -- cgit v1.3.1 From 36481ded99a530f6820961a2335e94b485469ae4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 14 Feb 2014 09:47:17 +0100 Subject: arm: omap3: Fix tao3530/omap3_ha SPL boot hangup (GPIO clocks not enabled) Patch f33b9bd3 [arm: omap3: Enable clocks for peripherals only if they are used] breaks SPL booting on tao3530. Since some gpio input's are read to detect the board revision. But with this patch above, the clocks to the GPIO subsystems are not enabled per default any more. The GPIO banks need to be configured specifically now. Signed-off-by: Stefan Roese Cc: Tom Rini Cc: Michael Trimarchi Reviewed-by: Stefano Babic --- include/configs/tao3530.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9abfe829022..9c04c23ab76 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -83,6 +83,13 @@ #define CONFIG_OMAP_HSMMC #define CONFIG_DOS_PARTITION +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ + /* commands to include */ #include -- cgit v1.3.1 From 9267110270a4b7b4ccdf9de9d82b7ac85ce57d0c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 14 Feb 2014 12:51:25 +0100 Subject: OMAP3: add missing gpio clock init and fix NAND SPL for mcx board Patch contains the same fixes as commit 4b9b2c300a23ca4a85811918dc92e822a9571a87 (missing CONFIG_OMAP3_GPIO_2) and commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30 (missing CONFIG_SPL_NAND_SOFTECC). Same issues are relevant for the mcx board, too. Signed-off-by: Stefano Babic --- include/configs/mcx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/mcx.h b/include/configs/mcx.h index dcd29ce7cbd..209c2bbd7cd 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -98,6 +98,7 @@ /* EHCI */ #define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_2 #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP @@ -395,6 +396,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW +#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -- cgit v1.3.1 From a5d64dbf20dd4b658dafb081afbbea797b27bdc3 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 14 Feb 2014 12:51:27 +0100 Subject: OMAP3: fix default environment for mcx board Patch allows to load a script at the startup from MMC. Signed-off-by: Stefano Babic --- include/configs/mcx.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 209c2bbd7cd..7c5c2f4d1c5 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -264,10 +264,9 @@ "${mtdparts} " \ "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ "omapdss.def_disp=lcd;" \ - "bootm 0x82000000 0x84000000\0" - -#define CONFIG_BOOTCOMMAND \ - "run nandboot" + "bootm 0x82000000 0x84000000\0" \ + "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ + "then source 82000000;else run nandboot;fi\0" #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -- cgit v1.3.1 From bc97f48915907553f350f843f3a0a6987a008248 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 21 Feb 2014 09:28:33 +0100 Subject: arm: omap: cm_t35: Remove CONFIG_SYS_BOOTMAPSZ to fix FDT Linux booting With CONFIG_SYS_BOOTMAPSZ defined, recent Linux kernel booting results in this error: Booting using the fdt blob at 0x81f00000 Loading Kernel Image ... OK ERROR: Failed to allocate 0x1189d bytes below 0x80004000. device tree - allocation error FDT creation failed! hanging...### ERROR ### Please RESET the board ### Removing this define solves this issue. Signed-off-by: Stefan Roese Cc: Nikita Kiryanov Cc: Igor Grinberg Cc: Tom Rini --- include/configs/cm_t35.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include') diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 7729a02ab65..08c67f588c1 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -45,13 +45,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 -/* - * The early kernel mapping on ARM currently only maps from the base of DRAM - * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. - * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, - * so that leaves DRAM base to DRAM base + 0x4000 available. - */ -#define CONFIG_SYS_BOOTMAPSZ 0x4000 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS -- cgit v1.3.1 From 01d92b0472647f339fe3dd495c13173ff7e568b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 21 Jan 2014 17:15:06 -0500 Subject: am335x_evm: Enable GPT commands Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 96ae369c6ac..59a8f36d169 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -32,6 +32,12 @@ /* Always 128 KiB env size */ #define CONFIG_ENV_SIZE (128 << 10) +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #ifdef CONFIG_NAND #define NANDARGS \ "mtdids=" MTDIDS_DEFAULT "\0" \ @@ -65,6 +71,9 @@ "bootfile=zImage\0" \ "fdtfile=undefined\0" \ "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ @@ -296,6 +305,9 @@ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) /* disable host part of MUSB in SPL */ #undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION /* * Disable CPSW SPL support so we fit within the 101KiB limit. */ -- cgit v1.3.1 From 0f1b04439596bc47ea95fab2d7d072b278b2a925 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 21 Jan 2014 17:15:07 -0500 Subject: am43xx_evm: Enable GPT commands Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d3c4756349b..9b4716f5aaa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -84,6 +84,12 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ @@ -95,6 +101,9 @@ "bootdir=/boot\0" \ "bootfile=zImage\0" \ "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ -- cgit v1.3.1 From 2efa79ae00fa935cf336b09ec12188654ae545ce Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 21 Jan 2014 17:15:08 -0500 Subject: dra7xx_evm: Enable GPT commands Signed-off-by: Tom Rini --- include/configs/dra7xx_evm.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 86574c836ab..c67cf60c0c6 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -34,8 +34,19 @@ #define CONFIG_SYS_OMAP_ABE_SYSCK +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + #include +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + /* CPSW Ethernet */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -- cgit v1.3.1 From 4f80d5ba8e79e4bc96b71295703372718528b3a7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 7 Jan 2014 20:06:56 -0600 Subject: omap4_common: config: remove I2C for SPL mode Commit 6789e84ecaa8f45d053084e08c381284a04abff7 (i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework) intended to make I2C driver compatible with latest changes. It unfortunately has had a impact on size on SPL as well. For example on SDP4430, 32032 bytes before/MLO 35416 bytes after/MLO With this mentioned commit, MLO stops booting on SDP4430 as only 32K is accessible for non-secure (bootloader) s/w on GP devices and the size increase to 56K fails boot. On the latest u-boot commit e7be18225fbea76d1f0034b224f0d1e60f07cfcf, MLO is now at size 35592 bytes, However, I2C is not necessary for SPL to function as we use SR_I2C for controlling the PMIC. Disabling I2C reduces MLO to 32224 bytes which allows OMAP4 GP platform to boot up. Since this is common for all OMAP4 platforms, remove the need for I2C for SPL builds in the common config. Signed-off-by: Nishanth Menon Reviewed-by: Sricharan R --- include/configs/ti_omap4_common.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 2f0e4c0f67d..bcb5eabd756 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -163,4 +163,10 @@ #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #endif +#ifdef CONFIG_SPL_BUILD +/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ +#undef CONFIG_SYS_I2C +#undef CONFIG_SYS_I2C_OMAP24XX +#endif + #endif /* __CONFIG_TI_OMAP4_COMMON_H */ -- cgit v1.3.1 From 1998a1a6c32d5e3ed729e0e08867d6f8fa97df50 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 13 Feb 2014 20:44:07 -0700 Subject: ARM: rpi_b: rework boot scripts, enable sysboot Rework rpi_b's bootcmd (and sub-commands) to match Tegra's bootcmd as much as possible. This will aid in a future patch which will create a common header e.g. config_distro_bootcmd.h. While at it, enable booting from extlinux.conf using the sysboot command. The iteration and componentization currently makes a little more sense for Tegra than RPi, but I'd still like to keep the two as similar as possible. USB and networking support is coming to the RPi in due course, and it'll all make more sense then anyway. Signed-off-by: Stephen Warren --- include/configs/rpi_b.h | 85 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 70 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 4b5a0c2150f..6306d61bb27 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -100,12 +100,20 @@ "env import -t ${loadaddr} ${filesize}; " \ "fi" +#define ENV_DEVICE_SETTINGS \ + "stdin=serial,lcd\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + /* * Memory layout for where various images get loaded by boot scripts: * * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it low in memory to avoid conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it low in memory to avoid conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -121,35 +129,82 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stderr=serial,lcd\0" \ - "stdout=serial,lcd\0" \ +#define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ "fdtfile=bcm2835-rpi-b.dtb\0" \ "ramdisk_addr_r=0x02100000\0" \ - "boot_targets=mmc0\0" \ - \ - "script_boot=" \ - "if fatload ${devtype} ${devnum}:1 " \ - "${scriptaddr} boot.scr.uimg; then " \ - "source ${scriptaddr}; " \ - "fi;\0" \ - \ + +#define BOOTCMDS_MMC \ "mmc_boot=" \ "setenv devtype mmc; " \ "if mmc dev ${devnum}; then " \ - "run script_boot; " \ + "run scan_boot; " \ "fi\0" \ + "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" +#define BOOT_TARGETS_MMC "mmc0" + +#define BOOTCMDS_COMMON \ + "rootpart=1\0" \ + \ + "do_script_boot=" \ + "load ${devtype} ${devnum}:${rootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "source ${scriptaddr}\0" \ + \ + "script_boot=" \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} ${devnum}:${rootpart} " \ + "${prefix}${script}; then " \ + "echo Found ${prefix}${script}; " \ + "run do_script_boot; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" \ \ - "bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \ + "do_sysboot_boot=" \ + "sysboot ${devtype} ${devnum}:${rootpart} any " \ + "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \ + \ + "sysboot_boot=" \ + "if test -e ${devtype} ${devnum}:${rootpart} " \ + "${prefix}extlinux/extlinux.conf; then " \ + "echo Found ${prefix}extlinux/extlinux.conf; " \ + "run do_sysboot_boot; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi\0" \ + \ + "scan_boot=" \ + "echo Scanning ${devtype} ${devnum}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run sysboot_boot; " \ + "run script_boot; " \ + "done\0" \ + \ + "boot_targets=" \ + BOOT_TARGETS_MMC " " \ + "\0" \ + \ + "boot_prefixes=/\0" \ + \ + "boot_scripts=boot.scr.uimg\0" \ + \ + BOOTCMDS_MMC #define CONFIG_BOOTCOMMAND \ "for target in ${boot_targets}; do run bootcmd_${target}; done" -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTCOMMAND \ + "for target in ${boot_targets}; do run bootcmd_${target}; done" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_DEVICE_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTCMDS_COMMON + +#define CONFIG_BOOTDELAY 2 /* Shell */ #define CONFIG_SYS_MAXARGS 8 -- cgit v1.3.1 From 989ce049997daefc25c15e1d5bf5307cdca25abb Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Tue, 11 Feb 2014 11:06:34 -0800 Subject: arch: bcm281xx: Initial commit of bcm281xx architecture code Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Reviewed-by: Tim Kryger --- arch/arm/cpu/armv7/bcm281xx/Makefile | 11 + arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 523 ++++++++++++++++++++++++++++ arch/arm/cpu/armv7/bcm281xx/clk-bsc.c | 52 +++ arch/arm/cpu/armv7/bcm281xx/clk-core.c | 513 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/bcm281xx/clk-core.h | 495 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/bcm281xx/clk-sdio.c | 73 ++++ arch/arm/cpu/armv7/bcm281xx/reset.c | 27 ++ arch/arm/include/asm/arch-bcm281xx/gpio.h | 15 + arch/arm/include/asm/arch-bcm281xx/sysmap.h | 25 ++ include/bitfield.h | 58 +++ 10 files changed, 1792 insertions(+) create mode 100644 arch/arm/cpu/armv7/bcm281xx/Makefile create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-bsc.c create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-core.c create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-core.h create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-sdio.c create mode 100644 arch/arm/cpu/armv7/bcm281xx/reset.c create mode 100644 arch/arm/include/asm/arch-bcm281xx/gpio.h create mode 100644 arch/arm/include/asm/arch-bcm281xx/sysmap.h create mode 100644 include/bitfield.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile new file mode 100644 index 00000000000..98f5aa59ca9 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += clk-core.o +obj-y += clk-bcm281xx.o +obj-y += clk-sdio.o +obj-y += clk-bsc.o diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c new file mode 100644 index 00000000000..bc8a170b407 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -0,0 +1,523 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * + * bcm281xx-specific clock tables + * + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define CLOCK_1K 1000 +#define CLOCK_1M (CLOCK_1K * 1000) + +/* declare a reference clock */ +#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ +static struct refclk clk_name = { \ + .clk = { \ + .name = #clk_name, \ + .parent = clk_parent, \ + .rate = clk_rate, \ + .div = clk_div, \ + .ops = &ref_clk_ops, \ + }, \ +} + +/* + * Reference clocks + */ + +/* Declare a list of reference clocks */ +DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); +DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); +DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); +DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); +DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); +DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); +DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); +DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); +DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); +DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); +DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); + +struct refclk_lkup { + struct refclk *procclk; + const char *name; +}; + +/* Lookup table for string to clk tranlation */ +#define MKSTR(x) {&x, #x} +static struct refclk_lkup refclk_str_tbl[] = { + MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), + MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), + MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), + MKSTR(var_52m), MKSTR(var_13m), +}; + +int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); + +/* convert ref clock string to clock structure pointer */ +struct refclk *refclk_str_to_clk(const char *name) +{ + int i; + struct refclk_lkup *tblp = refclk_str_tbl; + for (i = 0; i < refclk_entries; i++, tblp++) { + if (!(strcmp(name, tblp->name))) + return tblp->procclk; + } + return NULL; +} + +/* frequency tables indexed by freq_id */ +unsigned long master_axi_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M, + 208 * CLOCK_1M, + 312 * CLOCK_1M, + 312 * CLOCK_1M +}; + +unsigned long master_ahb_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M, + 104 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M +}; + +unsigned long slave_axi_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M +}; + +unsigned long slave_apb_freq_tbl[8] = { + 26 * CLOCK_1M, + 26 * CLOCK_1M, + 39 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M +}; + +static struct bus_clk_data bsc1_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), +}; + +static struct bus_clk_data bsc2_apb_data = { + .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), +}; + +static struct bus_clk_data bsc3_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), +}; + +/* * Master CCU clocks */ +static struct peri_clk_data sdio1_data = { + .gate = HW_SW_GATE(0x0358, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a28, 0, 3), + .div = DIVIDER(0x0a28, 4, 14), + .trig = TRIGGER(0x0afc, 9), +}; + +static struct peri_clk_data sdio2_data = { + .gate = HW_SW_GATE(0x035c, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a2c, 0, 3), + .div = DIVIDER(0x0a2c, 4, 14), + .trig = TRIGGER(0x0afc, 10), +}; + +static struct peri_clk_data sdio3_data = { + .gate = HW_SW_GATE(0x0364, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a34, 0, 3), + .div = DIVIDER(0x0a34, 4, 14), + .trig = TRIGGER(0x0afc, 12), +}; + +static struct peri_clk_data sdio4_data = { + .gate = HW_SW_GATE(0x0360, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a30, 0, 3), + .div = DIVIDER(0x0a30, 4, 14), + .trig = TRIGGER(0x0afc, 11), +}; + +static struct peri_clk_data sdio1_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0358, 20, 4), +}; + +static struct peri_clk_data sdio2_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x035c, 20, 4), +}; + +static struct peri_clk_data sdio3_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0364, 20, 4), +}; + +static struct peri_clk_data sdio4_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0360, 20, 4), +}; + +static struct bus_clk_data sdio1_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), +}; + +static struct bus_clk_data sdio2_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), +}; + +static struct bus_clk_data sdio3_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), +}; + +static struct bus_clk_data sdio4_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), +}; + +/* * Slave CCU clocks */ +static struct peri_clk_data bsc1_data = { + .gate = HW_SW_GATE(0x0458, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a64, 0, 3), + .trig = TRIGGER(0x0afc, 23), +}; + +static struct peri_clk_data bsc2_data = { + .gate = HW_SW_GATE(0x045c, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a68, 0, 3), + .trig = TRIGGER(0x0afc, 24), +}; + +static struct peri_clk_data bsc3_data = { + .gate = HW_SW_GATE(0x0484, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a84, 0, 3), + .trig = TRIGGER(0x0b00, 2), +}; + +/* + * CCU clocks + */ + +static struct ccu_clock kpm_ccu_clk = { + .clk = { + .name = "kpm_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .num_policy_masks = 1, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = master_axi_freq_tbl, +}; + +static struct ccu_clock kps_ccu_clk = { + .clk = { + .name = "kps_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .num_policy_masks = 2, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .policy0_mask2_offset = 0x00000048, + .policy1_mask2_offset = 0x0000004c, + .policy2_mask2_offset = 0x00000050, + .policy3_mask2_offset = 0x00000054, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = slave_axi_freq_tbl, +}; + +/* + * Bus clocks + */ + +/* KPM bus clocks */ +static struct bus_clock sdio1_ahb_clk = { + .clk = { + .name = "sdio1_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio1_ahb_data, +}; + +static struct bus_clock sdio2_ahb_clk = { + .clk = { + .name = "sdio2_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio2_ahb_data, +}; + +static struct bus_clock sdio3_ahb_clk = { + .clk = { + .name = "sdio3_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio3_ahb_data, +}; + +static struct bus_clock sdio4_ahb_clk = { + .clk = { + .name = "sdio4_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio4_ahb_data, +}; + +static struct bus_clock bsc1_apb_clk = { + .clk = { + .name = "bsc1_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc1_apb_data, +}; + +static struct bus_clock bsc2_apb_clk = { + .clk = { + .name = "bsc2_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc2_apb_data, +}; + +static struct bus_clock bsc3_apb_clk = { + .clk = { + .name = "bsc3_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc3_apb_data, +}; + +/* KPM peripheral */ +static struct peri_clock sdio1_clk = { + .clk = { + .name = "sdio1_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio1_data, +}; + +static struct peri_clock sdio2_clk = { + .clk = { + .name = "sdio2_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio2_data, +}; + +static struct peri_clock sdio3_clk = { + .clk = { + .name = "sdio3_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio3_data, +}; + +static struct peri_clock sdio4_clk = { + .clk = { + .name = "sdio4_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio4_data, +}; + +static struct peri_clock sdio1_sleep_clk = { + .clk = { + .name = "sdio1_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio1_sleep_data, +}; + +static struct peri_clock sdio2_sleep_clk = { + .clk = { + .name = "sdio2_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio2_sleep_data, +}; + +static struct peri_clock sdio3_sleep_clk = { + .clk = { + .name = "sdio3_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio3_sleep_data, +}; + +static struct peri_clock sdio4_sleep_clk = { + .clk = { + .name = "sdio4_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio4_sleep_data, +}; + +/* KPS peripheral clock */ +static struct peri_clock bsc1_clk = { + .clk = { + .name = "bsc1_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc1_data, +}; + +static struct peri_clock bsc2_clk = { + .clk = { + .name = "bsc2_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc2_data, +}; + +static struct peri_clock bsc3_clk = { + .clk = { + .name = "bsc3_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc3_data, +}; + +/* public table for registering clocks */ +struct clk_lookup arch_clk_tbl[] = { + /* Peripheral clocks */ + CLK_LK(sdio1), + CLK_LK(sdio2), + CLK_LK(sdio3), + CLK_LK(sdio4), + CLK_LK(sdio1_sleep), + CLK_LK(sdio2_sleep), + CLK_LK(sdio3_sleep), + CLK_LK(sdio4_sleep), + CLK_LK(bsc1), + CLK_LK(bsc2), + CLK_LK(bsc3), + /* Bus clocks */ + CLK_LK(sdio1_ahb), + CLK_LK(sdio2_ahb), + CLK_LK(sdio3_ahb), + CLK_LK(sdio4_ahb), + CLK_LK(bsc1_apb), + CLK_LK(bsc2_apb), + CLK_LK(bsc3_apb), +}; + +/* public array size */ +unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c new file mode 100644 index 00000000000..ba55d0aeb1a --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for a BSC/I2C port */ +int clk_bsc_enable(void *base) +{ + int ret; + char *bscstr, *apbstr; + + switch ((u32) base) { + case PMU_BSC_BASE_ADDR: + /* PMU clock is always enabled */ + return 0; + case BSC1_BASE_ADDR: + bscstr = "bsc1_clk"; + apbstr = "bsc1_apb_clk"; + break; + case BSC2_BASE_ADDR: + bscstr = "bsc2_clk"; + apbstr = "bsc2_apb_clk"; + break; + case BSC3_BASE_ADDR: + bscstr = "bsc3_clk"; + apbstr = "bsc3_apb_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + /* Note that the bus clock must be enabled first */ + + ret = clk_get_and_enable(apbstr); + if (ret) + return ret; + + ret = clk_get_and_enable(bscstr); + if (ret) + return ret; + + return 0; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c new file mode 100644 index 00000000000..d4425835a1b --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -0,0 +1,513 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * + * bcm281xx architecture clock framework + * + */ + +#include +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define CLK_WR_ACCESS_PASSWORD 0x00a5a501 +#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ +#define POLICY_CTL_GO 1 /* Load and refresh policy masks */ +#define POLICY_CTL_GO_ATL 4 /* Active Load */ + +/* Helper function */ +int clk_get_and_enable(char *clkstr) +{ + int ret = 0; + struct clk *c; + + debug("%s: %s\n", __func__, clkstr); + + c = clk_get(clkstr); + if (c) { + ret = clk_enable(c); + if (ret) + return ret; + } else { + printf("%s: Couldn't find %s\n", __func__, clkstr); + return -EINVAL; + } + return ret; +} + +/* + * Poll a register in a CCU's address space, returning when the + * specified bit in that register's value is set (or clear). Delay + * a microsecond after each read of the register. Returns true if + * successful, or false if we gave up trying. + * + * Caller must ensure the CCU lock is held. + */ +#define CLK_GATE_DELAY_USEC 2000 +static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) +{ + unsigned int tries; + u32 bit_mask = 1 << bit; + + for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) { + u32 val; + bool bit_val; + + val = readl(base + offset); + bit_val = (val & bit_mask) ? 1 : 0; + if (bit_val == want) + return 0; /* success */ + udelay(1); + } + + debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n", + __func__, base + offset, bit, want); + + return -ETIMEDOUT; +} + +/* Enable a peripheral clock */ +static int peri_clk_enable(struct clk *c, int enable) +{ + int ret = 0; + u32 reg; + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + struct bcm_clk_gate *gate = &cd->gate; + void *base = (void *)c->ccu_clk_mgr_base; + + + debug("%s: %s\n", __func__, c->name); + + clk_get_rate(c); /* Make sure rate and sel are filled in */ + + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + if (enable) { + debug("%s %s set rate %lu div %lu sel %d parent %lu\n", + __func__, c->name, c->rate, c->div, c->sel, + c->parent->rate); + + /* + * clkgate - only software controllable gates are + * supported by u-boot which includes all clocks + * that matter. This avoids bringing in a lot of extra + * complexity as done in the kernel framework. + */ + if (gate_exists(gate)) { + reg = readl(base + cd->gate.offset); + reg |= (1 << cd->gate.en_bit); + writel(reg, base + cd->gate.offset); + } + + /* div and pll select */ + if (divider_exists(&cd->div)) { + reg = readl(base + cd->div.offset); + bitfield_replace(reg, cd->div.shift, cd->div.width, + c->div - 1); + writel(reg, base + cd->div.offset); + } + + /* frequency selector */ + if (selector_exists(&cd->sel)) { + reg = readl(base + cd->sel.offset); + bitfield_replace(reg, cd->sel.shift, cd->sel.width, + c->sel); + writel(reg, base + cd->sel.offset); + } + + /* trigger */ + if (trigger_exists(&cd->trig)) { + writel((1 << cd->trig.bit), base + cd->trig.offset); + + /* wait for trigger status bit to go to 0 */ + ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0); + if (ret) + return ret; + } + + /* wait for running (status_bit = 1) */ + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); + if (ret) + return ret; + } else { + debug("%s disable clock %s\n", __func__, c->name); + + /* clkgate */ + reg = readl(base + cd->gate.offset); + reg &= ~(1 << cd->gate.en_bit); + writel(reg, base + cd->gate.offset); + + /* wait for stop (status_bit = 0) */ + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); + } + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Set the rate of a peripheral clock */ +static int peri_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret = 0; + int i; + unsigned long diff; + unsigned long new_rate = 0, div = 1; + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + const char **clock; + + debug("%s: %s\n", __func__, c->name); + diff = rate; + + i = 0; + for (clock = cd->clocks; *clock; clock++, i++) { + struct refclk *ref = refclk_str_to_clk(*clock); + if (!ref) { + printf("%s: Lookup of %s failed\n", __func__, *clock); + return -EINVAL; + } + + /* round to the new rate */ + div = ref->clk.rate / rate; + if (div == 0) + div = 1; + + new_rate = ref->clk.rate / div; + + /* get the min diff */ + if (abs(new_rate - rate) < diff) { + diff = abs(new_rate - rate); + c->sel = i; + c->parent = &ref->clk; + c->rate = new_rate; + c->div = div; + } + } + + debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__, + c->name, c->rate, c->div, c->sel, c->parent->rate); + return ret; +} + +/* Get the rate of a peripheral clock */ +static unsigned long peri_clk_get_rate(struct clk *c) +{ + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + void *base = (void *)c->ccu_clk_mgr_base; + int div = 1; + const char **clock; + struct refclk *ref; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + if (selector_exists(&cd->sel)) { + reg = readl(base + cd->sel.offset); + c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); + } else { + /* + * For peri clocks that don't have a selector, the single + * reference clock will always exist at index 0. + */ + c->sel = 0; + } + + if (divider_exists(&cd->div)) { + reg = readl(base + cd->div.offset); + div = bitfield_extract(reg, cd->div.shift, cd->div.width); + div += 1; + } + + clock = cd->clocks; + ref = refclk_str_to_clk(clock[c->sel]); + if (!ref) { + printf("%s: Can't lookup %s\n", __func__, clock[c->sel]); + return 0; + } + + c->parent = &ref->clk; + c->div = div; + c->rate = c->parent->rate / c->div; + debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__, + c->parent->rate, div, c->sel, c->rate); + + return c->rate; +} + +/* Peripheral clock operations */ +struct clk_ops peri_clk_ops = { + .enable = peri_clk_enable, + .set_rate = peri_clk_set_rate, + .get_rate = peri_clk_get_rate, +}; + +/* Enable a CCU clock */ +static int ccu_clk_enable(struct clk *c, int enable) +{ + struct ccu_clock *ccu_clk = to_ccu_clk(c); + void *base = (void *)c->ccu_clk_mgr_base; + int ret = 0; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + if (!enable) + return -EINVAL; /* CCU clock cannot shutdown */ + + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + /* config enable for policy engine */ + writel(1, base + ccu_clk->lvm_en_offset); + + /* wait for bit to go to 0 */ + ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0); + if (ret) + return ret; + + /* freq ID */ + if (!ccu_clk->freq_bit_shift) + ccu_clk->freq_bit_shift = 8; + + /* Set frequency id for each of the 4 policies */ + reg = ccu_clk->freq_id | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3)); + writel(reg, base + ccu_clk->policy_freq_offset); + + /* enable all clock mask */ + writel(0x7fffffff, base + ccu_clk->policy0_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy1_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy2_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy3_mask_offset); + + if (ccu_clk->num_policy_masks == 2) { + writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset); + } + + /* start policy engine */ + reg = readl(base + ccu_clk->policy_ctl_offset); + reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL); + writel(reg, base + ccu_clk->policy_ctl_offset); + + /* wait till started */ + ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0); + if (ret) + return ret; + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Get the CCU clock rate */ +static unsigned long ccu_clk_get_rate(struct clk *c) +{ + struct ccu_clock *ccu_clk = to_ccu_clk(c); + debug("%s: %s\n", __func__, c->name); + c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id]; + return c->rate; +} + +/* CCU clock operations */ +struct clk_ops ccu_clk_ops = { + .enable = ccu_clk_enable, + .get_rate = ccu_clk_get_rate, +}; + +/* Enable a bus clock */ +static int bus_clk_enable(struct clk *c, int enable) +{ + struct bus_clock *bus_clk = to_bus_clk(c); + struct bus_clk_data *cd = bus_clk->data; + void *base = (void *)c->ccu_clk_mgr_base; + int ret = 0; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + /* enable gating */ + reg = readl(base + cd->gate.offset); + if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) + debug("%s already %s\n", c->name, + enable ? "enabled" : "disabled"); + else { + int want = (enable) ? 1 : 0; + reg |= (1 << cd->gate.hw_sw_sel_bit); + + if (enable) + reg |= (1 << cd->gate.en_bit); + else + reg &= ~(1 << cd->gate.en_bit); + + writel(reg, base + cd->gate.offset); + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, + want); + if (ret) + return ret; + } + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Get the rate of a bus clock */ +static unsigned long bus_clk_get_rate(struct clk *c) +{ + struct bus_clock *bus_clk = to_bus_clk(c); + struct ccu_clock *ccu_clk; + + debug("%s: %s\n", __func__, c->name); + ccu_clk = to_ccu_clk(c->parent); + + c->rate = bus_clk->freq_tbl[ccu_clk->freq_id]; + c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate; + return c->rate; +} + +/* Bus clock operations */ +struct clk_ops bus_clk_ops = { + .enable = bus_clk_enable, + .get_rate = bus_clk_get_rate, +}; + +/* Enable a reference clock */ +static int ref_clk_enable(struct clk *c, int enable) +{ + debug("%s: %s\n", __func__, c->name); + return 0; +} + +/* Reference clock operations */ +struct clk_ops ref_clk_ops = { + .enable = ref_clk_enable, +}; + +/* + * clk.h implementation follows + */ + +/* Initialize the clock framework */ +int clk_init(void) +{ + debug("%s:\n", __func__); + return 0; +} + +/* Get a clock handle, give a name string */ +struct clk *clk_get(const char *con_id) +{ + int i; + struct clk_lookup *clk_tblp; + + debug("%s: %s\n", __func__, con_id); + + clk_tblp = arch_clk_tbl; + for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) { + if (clk_tblp->con_id) { + if (!con_id || strcmp(clk_tblp->con_id, con_id)) + continue; + return clk_tblp->clk; + } + } + return NULL; +} + +/* Enable a clock */ +int clk_enable(struct clk *c) +{ + int ret = 0; + + debug("%s: %s\n", __func__, c->name); + if (!c->ops || !c->ops->enable) + return -1; + + /* enable parent clock first */ + if (c->parent) + ret = clk_enable(c->parent); + + if (ret) + return ret; + + if (!c->use_cnt) { + c->use_cnt++; + ret = c->ops->enable(c, 1); + } + + return ret; +} + +/* Disable a clock */ +void clk_disable(struct clk *c) +{ + debug("%s: %s\n", __func__, c->name); + if (!c->ops || !c->ops->enable) + return; + + if (c->use_cnt) { + c->use_cnt--; + c->ops->enable(c, 0); + } + + /* disable parent */ + if (c->parent) + clk_disable(c->parent); +} + +/* Get the clock rate */ +unsigned long clk_get_rate(struct clk *c) +{ + unsigned long rate; + + debug("%s: %s\n", __func__, c->name); + if (!c || !c->ops || !c->ops->get_rate) + return 0; + + rate = c->ops->get_rate(c); + debug("%s: rate = %ld\n", __func__, rate); + return rate; +} + +/* Set the clock rate */ +int clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + + debug("%s: %s rate=%ld\n", __func__, c->name, rate); + if (!c || !c->ops || !c->ops->set_rate) + return -EINVAL; + + if (c->use_cnt) + return -EINVAL; + + ret = c->ops->set_rate(c, rate); + + return ret; +} + +/* Not required for this arch */ +/* +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *clk_get_parent(struct clk *clk); +*/ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h new file mode 100644 index 00000000000..882a2977979 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h @@ -0,0 +1,495 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifdef CONFIG_CLK_DEBUG +#undef writel +#undef readl +static inline void writel(u32 val, void *addr) +{ + printf("Write [0x%p] = 0x%08x\n", addr, val); + *(u32 *)addr = val; +} + +static inline u32 readl(void *addr) +{ + u32 val = *(u32 *)addr; + printf("Read [0x%p] = 0x%08x\n", addr, val); + return val; +} +#endif + +struct clk; + +struct clk_lookup { + const char *dev_id; + const char *con_id; + struct clk *clk; +}; + +extern struct clk_lookup arch_clk_tbl[]; +extern unsigned int arch_clk_tbl_array_size; + +/** + * struct clk_ops - standard clock operations + * @enable: enable/disable clock, see clk_enable() and clk_disable() + * @set_rate: set the clock rate, see clk_set_rate(). + * @get_rate: get the clock rate, see clk_get_rate(). + * @round_rate: round a given clock rate, see clk_round_rate(). + * @set_parent: set the clock's parent, see clk_set_parent(). + * + * Group the common clock implementations together so that we + * don't have to keep setting the same fiels again. We leave + * enable in struct clk. + * + */ +struct clk_ops { + int (*enable) (struct clk *c, int enable); + int (*set_rate) (struct clk *c, unsigned long rate); + unsigned long (*get_rate) (struct clk *c); + unsigned long (*round_rate) (struct clk *c, unsigned long rate); + int (*set_parent) (struct clk *c, struct clk *parent); +}; + +struct clk { + struct clk *parent; + const char *name; + int use_cnt; + unsigned long rate; /* in HZ */ + + /* programmable divider. 0 means fixed ratio to parent clock */ + unsigned long div; + + struct clk_src *src; + struct clk_ops *ops; + + unsigned long ccu_clk_mgr_base; + int sel; +}; + +struct refclk *refclk_str_to_clk(const char *name); + +#define U8_MAX ((u8)~0U) +#define U32_MAX ((u32)~0U) +#define U64_MAX ((u64)~0U) + +/* The common clock framework uses u8 to represent a parent index */ +#define PARENT_COUNT_MAX ((u32)U8_MAX) + +#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ +#define BAD_CLK_NAME ((const char *)-1) + +#define BAD_SCALED_DIV_VALUE U64_MAX + +/* + * Utility macros for object flag management. If possible, flags + * should be defined such that 0 is the desired default value. + */ +#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag +#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) +#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) +#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) +#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) + +/* Clock field state tests */ + +#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) +#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) +#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) +#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) +#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) +#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) + +#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) + +#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) +#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) +#define divider_has_fraction(div) (!divider_is_fixed(div) && \ + (div)->frac_width > 0) + +#define selector_exists(sel) ((sel)->width != 0) +#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) + +/* Clock type, used to tell common block what it's part of */ +enum bcm_clk_type { + bcm_clk_none, /* undefined clock type */ + bcm_clk_bus, + bcm_clk_core, + bcm_clk_peri +}; + +/* + * Gating control and status is managed by a 32-bit gate register. + * + * There are several types of gating available: + * - (no gate) + * A clock with no gate is assumed to be always enabled. + * - hardware-only gating (auto-gating) + * Enabling or disabling clocks with this type of gate is + * managed automatically by the hardware. Such clocks can be + * considered by the software to be enabled. The current status + * of auto-gated clocks can be read from the gate status bit. + * - software-only gating + * Auto-gating is not available for this type of clock. + * Instead, software manages whether it's enabled by setting or + * clearing the enable bit. The current gate status of a gate + * under software control can be read from the gate status bit. + * To ensure a change to the gating status is complete, the + * status bit can be polled to verify that the gate has entered + * the desired state. + * - selectable hardware or software gating + * Gating for this type of clock can be configured to be either + * under software or hardware control. Which type is in use is + * determined by the hw_sw_sel bit of the gate register. + */ +struct bcm_clk_gate { + u32 offset; /* gate register offset */ + u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ + u32 en_bit; /* 0: disable; 1: enable */ + u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ + u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ +}; + +/* + * Gate flags: + * HW means this gate can be auto-gated + * SW means the state of this gate can be software controlled + * NO_DISABLE means this gate is (only) enabled if under software control + * SW_MANAGED means the status of this gate is under software control + * ENABLED means this software-managed gate is *supposed* to be enabled + */ +#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ +#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ +#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ +#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ +#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ +#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ + +/* + * Gate initialization macros. + * + * Any gate initially under software control will be enabled. + */ + +/* A hardware/software gate initially under software control */ +#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ + FLAG(GATE, EXISTS), \ + } + +/* A hardware/software gate initially under hardware control */ +#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, EXISTS), \ + } + +/* A hardware-or-enabled gate (enabled if not under hardware control) */ +#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ + } + +/* A software-only gate */ +#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ + FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ + } + +/* A hardware-only gate */ +#define HW_ONLY_GATE(_offset, _status_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ + } + +/* + * Each clock can have zero, one, or two dividers which change the + * output rate of the clock. Each divider can be either fixed or + * variable. If there are two dividers, they are the "pre-divider" + * and the "regular" or "downstream" divider. If there is only one, + * there is no pre-divider. + * + * A fixed divider is any non-zero (positive) value, and it + * indicates how the input rate is affected by the divider. + * + * The value of a variable divider is maintained in a sub-field of a + * 32-bit divider register. The position of the field in the + * register is defined by its offset and width. The value recorded + * in this field is always 1 less than the value it represents. + * + * In addition, a variable divider can indicate that some subset + * of its bits represent a "fractional" part of the divider. Such + * bits comprise the low-order portion of the divider field, and can + * be viewed as representing the portion of the divider that lies to + * the right of the decimal point. Most variable dividers have zero + * fractional bits. Variable dividers with non-zero fraction width + * still record a value 1 less than the value they represent; the + * added 1 does *not* affect the low-order bit in this case, it + * affects the bits above the fractional part only. (Often in this + * code a divider field value is distinguished from the value it + * represents by referring to the latter as a "divisor".) + * + * In order to avoid dealing with fractions, divider arithmetic is + * performed using "scaled" values. A scaled value is one that's + * been left-shifted by the fractional width of a divider. Dividing + * a scaled value by a scaled divisor produces the desired quotient + * without loss of precision and without any other special handling + * for fractions. + * + * The recorded value of a variable divider can be modified. To + * modify either divider (or both), a clock must be enabled (i.e., + * using its gate). In addition, a trigger register (described + * below) must be used to commit the change, and polled to verify + * the change is complete. + */ +struct bcm_clk_div { + union { + struct { /* variable divider */ + u32 offset; /* divider register offset */ + u32 shift; /* field shift */ + u32 width; /* field width */ + u32 frac_width; /* field fraction width */ + + u64 scaled_div; /* scaled divider value */ + }; + u32 fixed; /* non-zero fixed divider value */ + }; + u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ +}; + +/* + * Divider flags: + * EXISTS means this divider exists + * FIXED means it is a fixed-rate divider + */ +#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ +#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ + +/* Divider initialization macros */ + +/* A fixed (non-zero) divider */ +#define FIXED_DIVIDER(_value) \ + { \ + .fixed = (_value), \ + .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ + } + +/* A divider with an integral divisor */ +#define DIVIDER(_offset, _shift, _width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .scaled_div = BAD_SCALED_DIV_VALUE, \ + .flags = FLAG(DIV, EXISTS), \ + } + +/* A divider whose divisor has an integer and fractional part */ +#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .frac_width = (_frac_width), \ + .scaled_div = BAD_SCALED_DIV_VALUE, \ + .flags = FLAG(DIV, EXISTS), \ + } + +/* + * Clocks may have multiple "parent" clocks. If there is more than + * one, a selector must be specified to define which of the parent + * clocks is currently in use. The selected clock is indicated in a + * sub-field of a 32-bit selector register. The range of + * representable selector values typically exceeds the number of + * available parent clocks. Occasionally the reset value of a + * selector field is explicitly set to a (specific) value that does + * not correspond to a defined input clock. + * + * We register all known parent clocks with the common clock code + * using a packed array (i.e., no empty slots) of (parent) clock + * names, and refer to them later using indexes into that array. + * We maintain an array of selector values indexed by common clock + * index values in order to map between these common clock indexes + * and the selector values used by the hardware. + * + * Like dividers, a selector can be modified, but to do so a clock + * must be enabled, and a trigger must be used to commit the change. + */ +struct bcm_clk_sel { + u32 offset; /* selector register offset */ + u32 shift; /* field shift */ + u32 width; /* field width */ + + u32 parent_count; /* number of entries in parent_sel[] */ + u32 *parent_sel; /* array of parent selector values */ + u8 clk_index; /* current selected index in parent_sel[] */ +}; + +/* Selector initialization macro */ +#define SELECTOR(_offset, _shift, _width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .clk_index = BAD_CLK_INDEX, \ + } + +/* + * Making changes to a variable divider or a selector for a clock + * requires the use of a trigger. A trigger is defined by a single + * bit within a register. To signal a change, a 1 is written into + * that bit. To determine when the change has been completed, that + * trigger bit is polled; the read value will be 1 while the change + * is in progress, and 0 when it is complete. + * + * Occasionally a clock will have more than one trigger. In this + * case, the "pre-trigger" will be used when changing a clock's + * selector and/or its pre-divider. + */ +struct bcm_clk_trig { + u32 offset; /* trigger register offset */ + u32 bit; /* trigger bit */ + u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ +}; + +/* + * Trigger flags: + * EXISTS means this trigger exists + */ +#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ + +/* Trigger initialization macro */ +#define TRIGGER(_offset, _bit) \ + { \ + .offset = (_offset), \ + .bit = (_bit), \ + .flags = FLAG(TRIG, EXISTS), \ + } + +struct bus_clk_data { + struct bcm_clk_gate gate; +}; + +struct core_clk_data { + struct bcm_clk_gate gate; +}; + +struct peri_clk_data { + struct bcm_clk_gate gate; + struct bcm_clk_trig pre_trig; + struct bcm_clk_div pre_div; + struct bcm_clk_trig trig; + struct bcm_clk_div div; + struct bcm_clk_sel sel; + const char *clocks[]; /* must be last; use CLOCKS() to declare */ +}; +#define CLOCKS(...) { __VA_ARGS__, NULL, } +#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ + +struct refclk { + struct clk clk; +}; + +struct peri_clock { + struct clk clk; + struct peri_clk_data *data; +}; + +struct ccu_clock { + struct clk clk; + + int num_policy_masks; + unsigned long policy_freq_offset; + int freq_bit_shift; /* 8 for most CCUs */ + unsigned long policy_ctl_offset; + unsigned long policy0_mask_offset; + unsigned long policy1_mask_offset; + unsigned long policy2_mask_offset; + unsigned long policy3_mask_offset; + unsigned long policy0_mask2_offset; + unsigned long policy1_mask2_offset; + unsigned long policy2_mask2_offset; + unsigned long policy3_mask2_offset; + unsigned long lvm_en_offset; + + int freq_id; + unsigned long *freq_tbl; +}; + +struct bus_clock { + struct clk clk; + struct bus_clk_data *data; + unsigned long *freq_tbl; +}; + +struct ref_clock { + struct clk clk; +}; + +static inline int is_same_clock(struct clk *a, struct clk *b) +{ + return (a == b); +} + +#define to_clk(p) (&((p)->clk)) +#define name_to_clk(name) (&((name##_clk).clk)) +/* declare a struct clk_lookup */ +#define CLK_LK(name) \ +{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),} + +static inline struct refclk *to_refclk(struct clk *clock) +{ + return container_of(clock, struct refclk, clk); +} + +static inline struct peri_clock *to_peri_clk(struct clk *clock) +{ + return container_of(clock, struct peri_clock, clk); +} + +static inline struct ccu_clock *to_ccu_clk(struct clk *clock) +{ + return container_of(clock, struct ccu_clock, clk); +} + +static inline struct bus_clock *to_bus_clk(struct clk *clock) +{ + return container_of(clock, struct bus_clock, clk); +} + +static inline struct ref_clock *to_ref_clk(struct clk *clock) +{ + return container_of(clock, struct ref_clock, clk); +} + +extern struct clk_ops peri_clk_ops; +extern struct clk_ops ccu_clk_ops; +extern struct clk_ops bus_clk_ops; +extern struct clk_ops ref_clk_ops; + +extern int clk_get_and_enable(char *clkstr); diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c new file mode 100644 index 00000000000..49badcbaa71 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -0,0 +1,73 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for an SDIO port */ +int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) +{ + int ret; + struct clk *c; + + char *clkstr; + char *slpstr; + char *ahbstr; + + switch ((u32) base) { + case CONFIG_SYS_SDIO_BASE0: + clkstr = CONFIG_SYS_SDIO0 "_clk"; + ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO0 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE1: + clkstr = CONFIG_SYS_SDIO1 "_clk"; + ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO1 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE2: + clkstr = CONFIG_SYS_SDIO2 "_clk"; + ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO2 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE3: + clkstr = CONFIG_SYS_SDIO3 "_clk"; + ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO3 "_sleep_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + ret = clk_get_and_enable(ahbstr); + if (ret) + return ret; + + ret = clk_get_and_enable(slpstr); + if (ret) + return ret; + + c = clk_get(clkstr); + if (c) { + ret = clk_set_rate(c, rate); + if (ret) + return ret; + + ret = clk_enable(c); + if (ret) + return ret; + } else { + printf("%s: Couldn't find %s\n", __func__, clkstr); + return -EINVAL; + } + *actual_ratep = rate; + return 0; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c new file mode 100644 index 00000000000..3beb0ed9c78 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -0,0 +1,27 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define EN_MASK 0x08000000 /* Enable timer */ +#define SRSTEN_MASK 0x04000000 /* Enable soft reset */ +#define CLKS_SHIFT 20 /* Clock period shift */ +#define LD_SHIFT 0 /* Reload value shift */ + +void reset_cpu(ulong ignored) +{ + /* + * Set WD enable, RST enable, + * 3.9 msec clock period (8), reload value (8*3.9ms) + */ + u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT); + writel(reg, SECWD2_BASE_ADDR); + + while (1) + ; /* loop forever till reset */ +} diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h new file mode 100644 index 00000000000..1b40a96ad42 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_GPIO_H +#define __ARCH_BCM281XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h new file mode 100644 index 00000000000..880b4e09073 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define GPIO2_BASE_ADDR 0x35003000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define PWRMGR_BASE_ADDR 0x35010000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define SECWD_BASE_ADDR 0x3500c000 +#define SECWD2_BASE_ADDR 0x35002f40 +#define TIMER_BASE_ADDR 0x3e00d000 + +#endif diff --git a/include/bitfield.h b/include/bitfield.h new file mode 100644 index 00000000000..ec4815c8e05 --- /dev/null +++ b/include/bitfield.h @@ -0,0 +1,58 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Bitfield operations + * + * These are generic bitfield operations which allow manipulation of variable + * width bitfields within a word. One use of this would be to use data tables + * to determine how to reprogram fields within R/W hardware registers. + * + * Example: + * + * old_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | old | | + * +--------+----+---+--+-----+----------+ + * + * new_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | new | | + * +--------+----+---+--+-----+----------+ + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract(old_reg_val, 10, 5); + * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new); + * + * The numbers 10 and 5 could for example come from data + * tables which describe all bitfields in all registers. + */ + +#include + +/* Produces a mask of set bits covering a range of a uint value */ +static inline uint bitfield_mask(uint shift, uint width) +{ + return ((1 << width) - 1) << shift; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract(uint reg_val, uint shift, uint width) +{ + return (reg_val & bitfield_mask(shift, width)) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace(uint reg_val, uint shift, uint width, + uint bitfield_val) +{ + uint mask = bitfield_mask(shift, width); + + return (reg_val & ~mask) | (bitfield_val << shift); +} -- cgit v1.3.1 From 9ed679aeeb9899123bf92ed1eafb7cf6965473dc Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Tue, 11 Feb 2014 11:06:38 -0800 Subject: board: bcm28155_ap: Add board files Add support for the bcm28155_ap reference board. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Reviewed-by: Tim Kryger --- board/broadcom/bcm28155_ap/Makefile | 7 ++ board/broadcom/bcm28155_ap/bcm28155_ap.c | 87 +++++++++++++++++++ boards.cfg | 1 + include/configs/bcm28155_ap.h | 140 +++++++++++++++++++++++++++++++ 4 files changed, 235 insertions(+) create mode 100644 board/broadcom/bcm28155_ap/Makefile create mode 100644 board/broadcom/bcm28155_ap/bcm28155_ap.c create mode 100644 include/configs/bcm28155_ap.h (limited to 'include') diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile new file mode 100644 index 00000000000..b18785a0786 --- /dev/null +++ b/board/broadcom/bcm28155_ap/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += $(BOARD).o diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c new file mode 100644 index 00000000000..940a1c2c506 --- /dev/null +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c @@ -0,0 +1,87 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 +#define SECWATCHDOG_SDOGCR_EN_SHIFT 27 +#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 +#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 +#define SECWATCHDOG_SDOGCR_LD_SHIFT 0 + +DECLARE_GLOBAL_DATA_PTR; + +/* + * board_init - early hardware init + */ +int board_init(void) +{ + printf("Relocation Offset is: %08lx\n", gd->reloc_off); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + clk_init(); + + return 0; +} + +/* + * misc_init_r - miscellaneous platform dependent initializations + */ +int misc_init_r(void) +{ + /* Disable watchdog reset - watchdog unused */ + writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) | + (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) | + (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) | + (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT), + (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET)); + + return 0; +} + +/* + * dram_init - sets uboots idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* This is called after dram_init() so use get_ram_size result */ +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +#ifdef CONFIG_KONA_SDHCI +/* + * mmc_init - Initializes mmc + */ +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + + /* Register eMMC - SDIO2 */ + ret = kona_sdhci_init(1, 400000, 0); + if (ret) + return ret; + + /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */ + ret = kona_sdhci_init(3, 400000, 0); + return ret; +} +#endif diff --git a/boards.cfg b/boards.cfg index 0e663d93a25..8130f19c970 100644 --- a/boards.cfg +++ b/boards.cfg @@ -273,6 +273,7 @@ Active arm armv7 am33xx ti ti816x Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen +Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger Active arm armv7 exynos samsung arndale arndale - Inderpal Singh Active arm armv7 exynos samsung origen origen - Chander Kashyap Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h new file mode 100644 index 00000000000..8e1c81fc13a --- /dev/null +++ b/include/configs/bcm28155_ap.h @@ -0,0 +1,140 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCM28155_AP_H +#define __BCM28155_AP_H + +#include +#include + +/* Architecture, CPU, chip, mach, etc */ +#define CONFIG_ARMV7 +#define CONFIG_KONA +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0xae000000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ +#define CONFIG_STACKSIZE SZ_256K + +/* GPIO Driver */ +#define CONFIG_KONA_GPIO + +/* MMC/SD Driver */ +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_KONA_SDHCI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC + +#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR +#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO0 "sdio1" +#define CONFIG_SYS_SDIO1 "sdio2" +#define CONFIG_SYS_SDIO2 "sdio3" +#define CONFIG_SYS_SDIO3 "sdio4" + +/* I2C Driver */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_KONA +#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR +#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR +#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR +#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR + +/* Timer Driver */ +#define CONFIG_SYS_TIMER_RATE 32000 +#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ + +/* Init functions */ +#define CONFIG_MISC_INIT_R /* board's misc_init_r function */ + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* No mtest functions as recommended */ +#undef CONFIG_CMD_MEMORY + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* Serial Info */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* Post pad 3 bytes after each reg addr */ +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 13000000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 0x3e000000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */ + +/* console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * One partition type must be defined for part.c + * This is necessary for the fatls command to work on an SD card + * for example. + */ +#define CONFIG_DOS_PARTITION + +/* version string, parser, etc */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* Initial upstream - boot to cmd prompt only */ +#define CONFIG_BOOTCOMMAND "" + +/* Commands */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_BOOTZ +#define CONFIG_FAT_WRITE + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#endif /* __BCM28155_AP_H */ -- cgit v1.3.1 From f55e911ff4143ad8cbcc4517d5fb0b9350ff6084 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 24 Feb 2014 21:45:48 +0900 Subject: arm: delete unused macro CONFIG_ARCH_DEVICE_TREE Signed-off-by: Masahiro Yamada Cc: Tom Warren Cc: Stephen Warren Cc: Rajeshwari Birje Cc: Inderpal Singh --- arch/arm/cpu/armv7/tegra124/config.mk | 10 ---------- include/configs/arndale.h | 2 -- include/configs/smdk5420.h | 2 -- 3 files changed, 14 deletions(-) delete mode 100644 arch/arm/cpu/armv7/tegra124/config.mk (limited to 'include') diff --git a/arch/arm/cpu/armv7/tegra124/config.mk b/arch/arm/cpu/armv7/tegra124/config.mk deleted file mode 100644 index 2f1c645c695..00000000000 --- a/arch/arm/cpu/armv7/tegra124/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2013 -# NVIDIA Corporation -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_ARCH_DEVICE_TREE := tegra124 diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 9584d82af73..515facfd675 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -22,8 +22,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -/* Enable fdt support for Exynos5250 */ -#define CONFIG_ARCH_DEVICE_TREE exynos5250 #define CONFIG_OF_CONTROL #define CONFIG_OF_SEPARATE diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 447f8e58105..b96eea88908 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -17,8 +17,6 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420 -#define CONFIG_ARCH_DEVICE_TREE exynos5420 - #define CONFIG_VAR_SIZE_SPL #define CONFIG_SYS_SDRAM_BASE 0x20000000 -- cgit v1.3.1 From 254887a57e93a818a10d95451a8ec29cb30c21f4 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 21 Feb 2014 13:16:19 +0800 Subject: powerpc/t2081qds: Add T2081 QDS board support T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor. T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t2080qds/Makefile | 12 - board/freescale/t2080qds/ddr.c | 119 ----- board/freescale/t2080qds/ddr.h | 72 --- board/freescale/t2080qds/eth_t2080qds.c | 517 ------------------- board/freescale/t2080qds/law.c | 34 -- board/freescale/t2080qds/pci.c | 23 - board/freescale/t2080qds/t2080_pbi.cfg | 41 -- board/freescale/t2080qds/t2080_rcw.cfg | 8 - board/freescale/t2080qds/t2080qds.c | 378 -------------- board/freescale/t2080qds/t2080qds.h | 13 - board/freescale/t2080qds/t2080qds_qixis.h | 47 -- board/freescale/t2080qds/tlb.c | 146 ------ board/freescale/t208xqds/Makefile | 14 + board/freescale/t208xqds/ddr.c | 119 +++++ board/freescale/t208xqds/ddr.h | 72 +++ board/freescale/t208xqds/eth_t208xqds.c | 648 ++++++++++++++++++++++++ board/freescale/t208xqds/law.c | 34 ++ board/freescale/t208xqds/pci.c | 23 + board/freescale/t208xqds/t2080_rcw.cfg | 8 + board/freescale/t208xqds/t2081_rcw.cfg | 8 + board/freescale/t208xqds/t208x_pbi.cfg | 41 ++ board/freescale/t208xqds/t208xqds.c | 459 +++++++++++++++++ board/freescale/t208xqds/t208xqds.h | 13 + board/freescale/t208xqds/t208xqds_qixis.h | 49 ++ board/freescale/t208xqds/tlb.c | 146 ++++++ boards.cfg | 15 +- include/configs/T2080QDS.h | 804 ----------------------------- include/configs/T208xQDS.h | 817 ++++++++++++++++++++++++++++++ 28 files changed, 2461 insertions(+), 2219 deletions(-) delete mode 100644 board/freescale/t2080qds/Makefile delete mode 100644 board/freescale/t2080qds/ddr.c delete mode 100644 board/freescale/t2080qds/ddr.h delete mode 100644 board/freescale/t2080qds/eth_t2080qds.c delete mode 100644 board/freescale/t2080qds/law.c delete mode 100644 board/freescale/t2080qds/pci.c delete mode 100644 board/freescale/t2080qds/t2080_pbi.cfg delete mode 100644 board/freescale/t2080qds/t2080_rcw.cfg delete mode 100644 board/freescale/t2080qds/t2080qds.c delete mode 100644 board/freescale/t2080qds/t2080qds.h delete mode 100644 board/freescale/t2080qds/t2080qds_qixis.h delete mode 100644 board/freescale/t2080qds/tlb.c create mode 100644 board/freescale/t208xqds/Makefile create mode 100644 board/freescale/t208xqds/ddr.c create mode 100644 board/freescale/t208xqds/ddr.h create mode 100644 board/freescale/t208xqds/eth_t208xqds.c create mode 100644 board/freescale/t208xqds/law.c create mode 100644 board/freescale/t208xqds/pci.c create mode 100644 board/freescale/t208xqds/t2080_rcw.cfg create mode 100644 board/freescale/t208xqds/t2081_rcw.cfg create mode 100644 board/freescale/t208xqds/t208x_pbi.cfg create mode 100644 board/freescale/t208xqds/t208xqds.c create mode 100644 board/freescale/t208xqds/t208xqds.h create mode 100644 board/freescale/t208xqds/t208xqds_qixis.h create mode 100644 board/freescale/t208xqds/tlb.c delete mode 100644 include/configs/T2080QDS.h create mode 100644 include/configs/T208xQDS.h (limited to 'include') diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t2080qds/Makefile deleted file mode 100644 index 0b8747b8770..00000000000 --- a/board/freescale/t2080qds/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_T2080QDS) += t2080qds.o -obj-$(CONFIG_T2080QDS) += eth_t2080qds.o -obj-$(CONFIG_PCI) += pci.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c deleted file mode 100644 index ed1334d9859..00000000000 --- a/board/freescale/t2080qds/ddr.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[0]; - else - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -} - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing....using SPD\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h deleted file mode 100644 index 9fc879a4ef4..00000000000 --- a/board/freescale/t2080qds/ddr.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - /* TODO: need tuning these parameters if RDIMM is used */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; -#endif diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t2080qds/eth_t2080qds.c deleted file mode 100644 index 3e4ab8fa57c..00000000000 --- a/board/freescale/t2080qds/eth_t2080qds.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Shengzhou Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t2080qds_qixis.h" - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 6 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI2 7 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { - "T2080QDS_MDIO_RGMII1", - "T2080QDS_MDIO_RGMII2", - "T2080QDS_MDIO_SLOT1", - "T2080QDS_MDIO_SLOT3", - "T2080QDS_MDIO_SLOT4", - "T2080QDS_MDIO_SLOT5", - "T2080QDS_MDIO_SLOT2", - "T2080QDS_MDIO_10GC", -}; - -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; - -static const char *T2080qds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = T2080qds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct T2080qds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void T2080qds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct T2080qds_mdio *priv = bus->priv; - - T2080qds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct T2080qds_mdio *priv = bus->priv; - - T2080qds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int T2080qds_mdio_reset(struct mii_dev *bus) -{ - struct T2080qds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int T2080qds_mdio_init(char *realbusname, u8 muxval) -{ - struct T2080qds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate T2080QDS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate T2080QDS private data\n"); - free(bus); - return -1; - } - - bus->read = T2080qds_mdio_read; - bus->write = T2080qds_mdio_write; - bus->reset = T2080qds_mdio_reset; - sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[20]; - struct fixed_link f_link; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - switch (port) { - case FM1_DTSEC1: - case FM1_DTSEC2: - case FM1_DTSEC9: - case FM1_DTSEC10: - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case FM1_DTSEC5: - case FM1_DTSEC6: - if (mdio_mux[port] == EMI1_SLOT1) { - sprintf(alias, "phy_sgmii_s1_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - } else if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } - break; - default: - break; - } - - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - switch (srds_s1) { - case 0x66: /* XFI interface */ - case 0x6b: - case 0x6c: - case 0x6d: - case 0x71: - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for XFI */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -/* - * This function reads RCW to check if Serdes1{E,F,G,H} is configured - * as slot 1/2/3 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { - case 0x51: - case 0x5f: - case 0x65: - case 0x6b: - case 0x71: - lane_to_slot[5] = 2; - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - case 0xd3: - case 0xd9: - case 0xcb: - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xda: - lane_to_slot[4] = 3; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - default: - break; - } -} - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - else - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x1c: - case 0x95: - case 0xa2: - case 0x94: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x51: - case 0x5f: - case 0x65: - /* XAUI/HiGig in Slot3 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x66: - /* - * XFI does not need a PHY to work, but to avoid U-boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause - * error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - break; - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x6c: - case 0x6d: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x71: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa4: - case 0x96: - case 0x8a: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0xd9: - case 0xd3: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4 || FM1_DTSEC10) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if (srds_s1 == 0x51) { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { - lane = serdes_get_first_lane(FSL_SRDS_1, - HIGIG_FM1_MAC9 + idx); - } else { - if (i == FM1_10GEC1 || i == FM1_10GEC2) - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC9 + idx); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - } - - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || - (srds_s1 == 0x71)) { - /* As XFI is in cage intead of a slot, so - * ensure doesn't disable the corresponding port - */ - break; - } - - slot = lane_to_slot[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t2080qds/law.c deleted file mode 100644 index 74e2a53a8fd..00000000000 --- a/board/freescale/t2080qds/law.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef QIXIS_BASE_PHYS - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t2080qds/pci.c deleted file mode 100644 index 84a89dad4f2..00000000000 --- a/board/freescale/t2080qds/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2007-2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t2080qds/t2080_pbi.cfg deleted file mode 100644 index e200d926fb0..00000000000 --- a/board/freescale/t2080qds/t2080_pbi.cfg +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -#enable CPC1 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Errata for slowing down the MDC clock to make it <= 2.5 MHZ -094fc030 00008148 -094fd030 00008148 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t2080qds/t2080_rcw.cfg deleted file mode 100644 index c2ad0fda55c..00000000000 --- a/board/freescale/t2080qds/t2080_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#SerDes Protocol: 0x66_0x16 -#Core/DDR: 1533Mhz/2133MT/s -12100017 15000000 00000000 00000000 -66160002 00008400 e8104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t2080qds/t2080qds.c deleted file mode 100644 index 4fe8ccb54cd..00000000000 --- a/board/freescale/t2080qds/t2080qds.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright 2009-2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/vsc3316_3308.h" -#include "t2080qds.h" -#include "t2080qds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - static const char *freq[4] = { - "100.00MHZ(from 8T49N222A)", "125.00MHz", - "156.25MHZ", "100.00MHz" - }; - - printf("Board: %sQDS, ", cpu->name); - sw = QIXIS_READ(arch); - printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); - printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); - -#ifdef CONFIG_SDCARD - puts("SD/MMC\n"); -#elif CONFIG_SPIFLASH - puts("SPI\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank%d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - - printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), - qixis_read_tag(buf), (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - puts("SERDES Reference Clocks:\n"); - sw = QIXIS_READ(brdcfg[2]); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], - freq[(sw >> 4) & 0x3]); - printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], - freq[sw & 0x3]); - - return 0; -} - -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - -int brd_mux_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - switch (srds_prtcl_s1) { - case 0: - /* SerDes1 is not enabled */ - break; - case 0x1c: - case 0xa2: - /* SD1(A:D) => SLOT3 SGMII - * SD1(G:H) => SLOT1 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x1a); - break; - case 0x94: - case 0x95: - /* SD1(A:B) => SLOT3 SGMII@1.25bps - * SD1(C:D) => SFP Module, SGMII@3.125bps - * SD1(E:H) => SLOT1 SGMII@1.25bps - */ - case 0x96: - /* SD1(A:B) => SLOT3 SGMII@1.25bps - * SD1(C) => SFP Module, SGMII@3.125bps - * SD1(D) => SFP Module, SGMII@1.25bps - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0x3a); - break; - case 0x51: - /* SD1(A:D) => SLOT3 XAUI - * SD1(E) => SLOT1 PCIe4 - * SD1(F:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x15); - break; - case 0x66: - case 0x67: - /* SD1(A:D) => XFI cage - * SD1(E:H) => SLOT1 PCIe4 - */ - QIXIS_WRITE(brdcfg[12], 0xfe); - break; - case 0x6b: - /* SD1(A:D) => XFI cage - * SD1(E) => SLOT1 PCIe4 - * SD1(F:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0xf1); - break; - case 0x6c: - case 0x6d: - /* SD1(A:B) => XFI cage - * SD1(C:D) => SLOT3 SGMII - * SD1(E:H) => SLOT1 PCIe4 - */ - QIXIS_WRITE(brdcfg[12], 0xda); - break; - case 0x6e: - /* SD1(A:B) => SFP Module, XFI - * SD1(C:D) => SLOT3 SGMII - * SD1(E:F) => SLOT1 PCIe4 x2 - * SD1(G:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0xd9); - break; - case 0xda: - /* SD1(A:H) => SLOT3 PCIe3 x8 - */ - QIXIS_WRITE(brdcfg[12], 0x0); - break; - case 0xc8: - /* SD1(A) => SLOT3 PCIe3 x1 - * SD1(B) => SFP Module, SGMII@1.25bps - * SD1(C:D) => SFP Module, SGMII@3.125bps - * SD1(E:F) => SLOT1 PCIe4 x2 - * SD1(G:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x79); - break; - case 0xab: - /* SD1(A:D) => SLOT3 PCIe3 x4 - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0x1a); - break; - default: - printf("WARNING: unsupported for SerDes1 Protocol %d\n", - srds_prtcl_s1); - return -1; - } - - switch (srds_prtcl_s2) { - case 0: - /* SerDes2 is not enabled */ - break; - case 0x01: - case 0x02: - /* SD2(A:H) => SLOT4 PCIe1 */ - QIXIS_WRITE(brdcfg[13], 0x10); - break; - case 0x15: - case 0x16: - /* - * SD2(A:D) => SLOT4 PCIe1 - * SD2(E:F) => SLOT5 PCIe2 - * SD2(G:H) => SATA1,SATA2 - */ - QIXIS_WRITE(brdcfg[13], 0xb0); - break; - case 0x18: - /* - * SD2(A:D) => SLOT4 PCIe1 - * SD2(E:F) => SLOT5 Aurora - * SD2(G:H) => SATA1,SATA2 - */ - QIXIS_WRITE(brdcfg[13], 0x78); - break; - case 0x1f: - /* - * SD2(A:D) => SLOT4 PCIe1 - * SD2(E:H) => SLOT5 PCIe2 - */ - QIXIS_WRITE(brdcfg[13], 0xa0); - break; - case 0x29: - case 0x2d: - case 0x2e: - /* - * SD2(A:D) => SLOT4 SRIO2 - * SD2(E:H) => SLOT5 SRIO1 - */ - QIXIS_WRITE(brdcfg[13], 0xa0); - break; - case 0x36: - /* - * SD2(A:D) => SLOT4 SRIO2 - * SD2(E:F) => Aurora - * SD2(G:H) => SATA1,SATA2 - */ - QIXIS_WRITE(brdcfg[13], 0x78); - break; - default: - printf("WARNING: unsupported for SerDes2 Protocol %d\n", - srds_prtcl_s2); - return -1; - } - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - - /* Disable remote I2C connection to qixis fpga */ - QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); - - brd_mux_lane_to_slot(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("SYS Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: SYS clock measurement is invalid, "); - printf("using value from brdcfg1.\n"); - } -#endif - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("DDR Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: DDR clock measurement is invalid, "); - printf("using value from brdcfg1.\n"); - } -#endif - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -int misc_init_r(void) -{ - return 0; -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_board_enet(blob); -#endif -} diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t2080qds/t2080qds.h deleted file mode 100644 index 39fcef28c3d..00000000000 --- a/board/freescale/t2080qds/t2080qds.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); - -#endif diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t2080qds/t2080qds_qixis.h deleted file mode 100644 index fc83da707fe..00000000000 --- a/board/freescale/t2080qds/t2080qds_qixis.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __T2080QDS_QIXIS_H__ -#define __T2080QDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for T2080QDS */ - -#define QIXIS_SRDS1CLK_122 0x5a -#define QIXIS_SRDS1CLK_125 0x5e - - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ - -#define BRDCFG12_SD3EN_MASK 0x20 -#define BRDCFG12_SD3MX_MASK 0x08 -#define BRDCFG12_SD3MX_SLOT5 0x08 -#define BRDCFG12_SD3MX_SLOT6 0x00 -#define BRDCFG12_SD4EN_MASK 0x04 -#define BRDCFG12_SD4MX_MASK 0x03 -#define BRDCFG12_SD4MX_SLOT7 0x02 -#define BRDCFG12_SD4MX_SLOT8 0x01 -#define BRDCFG12_SD4MX_AURO_SATA 0x00 -#endif diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t2080qds/tlb.c deleted file mode 100644 index 62cd11033ad..00000000000 --- a/board/freescale/t2080qds/tlb.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright 2008-2013 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_512M, 1), - - /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - - /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef QIXIS_BASE_PHYS - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 17, BOOKE_PAGESZ_4K, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 18, BOOKE_PAGESZ_1M, 1), -#endif - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile new file mode 100644 index 00000000000..947b7f73241 --- /dev/null +++ b/board/freescale/t208xqds/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T2080QDS) += t208xqds.o +obj-$(CONFIG_T2080QDS) += eth_t208xqds.o +obj-$(CONFIG_T2081QDS) += t208xqds.o +obj-$(CONFIG_T2081QDS) += eth_t208xqds.o +obj-$(CONFIG_PCI) += pci.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c new file mode 100644 index 00000000000..ed1334d9859 --- /dev/null +++ b/board/freescale/t208xqds/ddr.c @@ -0,0 +1,119 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h new file mode 100644 index 00000000000..9fc879a4ef4 --- /dev/null +++ b/board/freescale/t208xqds/ddr.h @@ -0,0 +1,72 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + /* TODO: need tuning these parameters if RDIMM is used */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; +#endif diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c new file mode 100644 index 00000000000..7d8411bef72 --- /dev/null +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -0,0 +1,648 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/fman.h" +#include "t208xqds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#if defined(CONFIG_T2080QDS) +#define EMI1_SLOT2 6 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#elif defined(CONFIG_T2081QDS) +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#endif +#define EMI2 8 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { +#if defined(CONFIG_T2080QDS) + "T2080QDS_MDIO_RGMII1", + "T2080QDS_MDIO_RGMII2", + "T2080QDS_MDIO_SLOT1", + "T2080QDS_MDIO_SLOT3", + "T2080QDS_MDIO_SLOT4", + "T2080QDS_MDIO_SLOT5", + "T2080QDS_MDIO_SLOT2", + "T2080QDS_MDIO_10GC", +#elif defined(CONFIG_T2081QDS) + "T2081QDS_MDIO_RGMII1", + "T2081QDS_MDIO_RGMII2", + "T2081QDS_MDIO_SLOT1", + "T2081QDS_MDIO_SLOT2", + "T2081QDS_MDIO_SLOT3", + "T2081QDS_MDIO_SLOT5", + "T2081QDS_MDIO_SLOT6", + "T2081QDS_MDIO_SLOT7", + "T2081QDS_MDIO_10GC", +#endif +}; + +/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ +#if defined(CONFIG_T2080QDS) +static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; +#elif defined(CONFIG_T2081QDS) +static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; +#endif + +static const char *t208xqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t208xqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t208xqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t208xqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval < 8) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t208xqds_mdio *priv = bus->priv; + + t208xqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t208xqds_mdio *priv = bus->priv; + + t208xqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t208xqds_mdio_reset(struct mii_dev *bus) +{ + struct t208xqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t208xqds_mdio_init(char *realbusname, u8 muxval) +{ + struct t208xqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t208xqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t208xqds private data\n"); + free(bus); + return -1; + } + + bus->read = t208xqds_mdio_read; + bus->write = t208xqds_mdio_write; + bus->reset = t208xqds_mdio_reset; + sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + int phy; + char alias[20]; + struct fixed_link f_link; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + phy = fm_info_get_phy_address(port); + switch (port) { +#if defined(CONFIG_T2080QDS) + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } + break; + case FM1_DTSEC5: + case FM1_DTSEC6: + if (mdio_mux[port] == EMI1_SLOT1) { + sprintf(alias, "phy_sgmii_s1_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + } else if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } + break; +#elif defined(CONFIG_T2081QDS) + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } else if (mdio_mux[port] == EMI1_SLOT5) { + sprintf(alias, "phy_sgmii_s5_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + } else if (mdio_mux[port] == EMI1_SLOT6) { + sprintf(alias, "phy_sgmii_s6_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + } else if (mdio_mux[port] == EMI1_SLOT7) { + sprintf(alias, "phy_sgmii_s7_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + } + break; +#endif + default: + break; + } + + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + switch (srds_s1) { + case 0x66: /* XFI interface */ + case 0x6b: + case 0x6c: + case 0x6d: + case 0x71: + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +/* + * This function reads RCW to check if Serdes1{A:H} is configured + * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (srds_s1) { +#if defined(CONFIG_T2080QDS) + case 0x51: + case 0x5f: + case 0x65: + case 0x6b: + case 0x71: + lane_to_slot[5] = 2; + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + case 0xd3: + case 0xd9: + case 0xcb: + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xda: + lane_to_slot[4] = 3; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; +#elif defined(CONFIG_T2081QDS) + case 0x6b: + lane_to_slot[4] = 1; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xca: + case 0xcb: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xf2: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 4; + lane_to_slot[6] = 3; + lane_to_slot[7] = 7; + break; +#endif + default: + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); +#if defined(CONFIG_T2080QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); +#endif + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); +#if defined(CONFIG_T2081QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); +#endif + t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + else + fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x1c: + case 0x95: + case 0xa2: + case 0x94: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x51: + case 0x5f: + case 0x65: + /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x66: + /* + * XFI does not need a PHY to work, but to avoid U-boot use + * default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to XFI + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks + * the XAUI card is used for the XFI MAC, which will cause + * error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + break; + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x6c: + case 0x6d: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x71: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa4: + case 0x96: + case 0x8a: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; +#if defined(CONFIG_T2080QDS) + case 0xd9: + case 0xd3: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; +#elif defined(CONFIG_T2081QDS) + case 0xca: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + /* SGMII in Slot5 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot6 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + break; +#endif + case 0xf2: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; +#if defined(CONFIG_T2081QDS) + case 5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 6: + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 7: + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; +#endif + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4 || FM1_DTSEC10) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + if (srds_s1 == 0x51) { + lane = serdes_get_first_lane(FSL_SRDS_1, + XAUI_FM1_MAC9 + idx); + } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { + lane = serdes_get_first_lane(FSL_SRDS_1, + HIGIG_FM1_MAC9 + idx); + } else { + if (i == FM1_10GEC1 || i == FM1_10GEC2) + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC9 + idx); + else + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC1 + idx); + } + + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + + if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || + (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || + (srds_s1 == 0x71)) { + /* As XFI is in cage intead of a slot, so + * ensure doesn't disable the corresponding port + */ + break; + } + + slot = lane_to_slot[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c new file mode 100644 index 00000000000..74e2a53a8fd --- /dev/null +++ b/board/freescale/t208xqds/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c new file mode 100644 index 00000000000..84a89dad4f2 --- /dev/null +++ b/board/freescale/t208xqds/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg new file mode 100644 index 00000000000..c2ad0fda55c --- /dev/null +++ b/board/freescale/t208xqds/t2080_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#SerDes Protocol: 0x66_0x16 +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +66160002 00008400 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg new file mode 100644 index 00000000000..a2d5ecf4adc --- /dev/null +++ b/board/freescale/t208xqds/t2081_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#Default SerDes Protocol: 0x6C +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +6c000002 00008000 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg new file mode 100644 index 00000000000..e200d926fb0 --- /dev/null +++ b/board/freescale/t208xqds/t208x_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c new file mode 100644 index 00000000000..9cfc0bd7c3c --- /dev/null +++ b/board/freescale/t208xqds/t208xqds.c @@ -0,0 +1,459 @@ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "t208xqds.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[4] = { + "100.00MHZ(from 8T49N222A)", "125.00MHz", + "156.25MHZ", "100.00MHz" + }; + + printf("Board: %sQDS, ", cpu->name); + sw = QIXIS_READ(arch); + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank%d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), + qixis_read_tag(buf), (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES Reference Clocks:\n"); + sw = QIXIS_READ(brdcfg[2]); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], + freq[(sw >> 4) & 0x3]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], + freq[sw & 0x3]); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int brd_mux_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; +#if defined(CONFIG_T2080QDS) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; +#endif + + switch (srds_prtcl_s1) { + case 0: + /* SerDes1 is not enabled */ + break; +#if defined(CONFIG_T2080QDS) + case 0x1c: + case 0xa2: + /* SD1(A:D) => SLOT3 SGMII + * SD1(G:H) => SLOT1 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; + case 0x94: + case 0x95: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:H) => SLOT1 SGMII@1.25bps + */ + case 0x96: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C) => SFP Module, SGMII@3.125bps + * SD1(D) => SFP Module, SGMII@1.25bps + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x3a); + break; + case 0x51: + /* SD1(A:D) => SLOT3 XAUI + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x15); + break; + case 0x66: + case 0x67: + /* SD1(A:D) => XFI cage + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xfe); + break; + case 0x6b: + /* SD1(A:D) => XFI cage + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xf1); + break; + case 0x6c: + case 0x6d: + /* SD1(A:B) => XFI cage + * SD1(C:D) => SLOT3 SGMII + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xda); + break; + case 0x6e: + /* SD1(A:B) => SFP Module, XFI + * SD1(C:D) => SLOT3 SGMII + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xd9); + break; + case 0xda: + /* SD1(A:H) => SLOT3 PCIe3 x8 + */ + QIXIS_WRITE(brdcfg[12], 0x0); + break; + case 0xc8: + /* SD1(A) => SLOT3 PCIe3 x1 + * SD1(B) => SFP Module, SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x79); + break; + case 0xab: + /* SD1(A:D) => SLOT3 PCIe3 x4 + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; +#elif defined(CONFIG_T2081QDS) + case 0x51: + /* SD1(A:D) => SLOT2 XAUI + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6b: + /* SD1(A:D) => XFI SFP Module + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6c: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0x6d: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xaa: + case 0xab: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(F:H) => SLOT1 SGMI4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xf8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xca: + case 0xcb: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B) => SLOT7 SGMII + * SD1(C) => SLOT6 SGMII + * SD1(D) => SLOT5 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0xde: + case 0xdf: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x25); + break; + case 0xf2: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B:D) => SLOT7 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x81); + QIXIS_WRITE(brdcfg[13], 0xa5); + break; +#endif + default: + printf("WARNING: unsupported for SerDes1 Protocol %d\n", + srds_prtcl_s1); + return -1; + } + +#ifdef CONFIG_T2080QDS + switch (srds_prtcl_s2) { + case 0: + /* SerDes2 is not enabled */ + break; + case 0x01: + case 0x02: + /* SD2(A:H) => SLOT4 PCIe1 */ + QIXIS_WRITE(brdcfg[13], 0x10); + break; + case 0x15: + case 0x16: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 PCIe2 + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0xb0); + break; + case 0x18: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); + break; + case 0x1f: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:H) => SLOT5 PCIe2 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x29: + case 0x2d: + case 0x2e: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:H) => SLOT5 SRIO1 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x36: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:F) => Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); + break; + default: + printf("WARNING: unsupported for SerDes2 Protocol %d\n", + srds_prtcl_s2); + return -1; + } +#endif + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Disable remote I2C connection to qixis fpga */ + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + + brd_mux_lane_to_slot(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("SYS Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: SYS clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("DDR Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: DDR clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h new file mode 100644 index 00000000000..39fcef28c3d --- /dev/null +++ b/board/freescale/t208xqds/t208xqds.h @@ -0,0 +1,13 @@ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h new file mode 100644 index 00000000000..bdcdc12f597 --- /dev/null +++ b/board/freescale/t208xqds/t208xqds_qixis.h @@ -0,0 +1,49 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T208xQDS_QIXIS_H__ +#define __T208xQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T208xQDS */ + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e + + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ + +#define BRDCFG9_SFP_TX_EN 0x10 + +#define BRDCFG12_SD3EN_MASK 0x20 +#define BRDCFG12_SD3MX_MASK 0x08 +#define BRDCFG12_SD3MX_SLOT5 0x08 +#define BRDCFG12_SD3MX_SLOT6 0x00 +#define BRDCFG12_SD4EN_MASK 0x04 +#define BRDCFG12_SD4MX_MASK 0x03 +#define BRDCFG12_SD4MX_SLOT7 0x02 +#define BRDCFG12_SD4MX_SLOT8 0x01 +#define BRDCFG12_SD4MX_AURO_SATA 0x00 +#endif diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c new file mode 100644 index 00000000000..62cd11033ad --- /dev/null +++ b/board/freescale/t208xqds/tlb.c @@ -0,0 +1,146 @@ +/* + * Copyright 2008-2013 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE_PHYS + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index c97c4bdd5d5..3c3ebb841a5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -972,11 +972,16 @@ Active powerpc mpc85xx - freescale p2041rdb Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal -Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h deleted file mode 100644 index 9bd0fe23820..00000000000 --- a/include/configs/T2080QDS.h +++ /dev/null @@ -1,804 +0,0 @@ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * T2080 QDS board configuration file - */ - -#ifndef __T2080QDS_H -#define __T2080QDS_H - -#define CONFIG_T2080QDS -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_MMC -#define CONFIG_SPI_FLASH -#define CONFIG_USB_EHCI -#define CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - -/* High Level Configuration Options */ -#define CONFIG_PHYS_64BIT -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MP /* support multiple processors */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_IFC /* Enable IFC Support */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg -#endif - -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_NO_FLASH -#endif - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_ENV_IS_NOWHERE -#endif -#else -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_IS_IN_REMOTE -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CTRL_INTLV_PREFERED cacheline - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RST_FORCE_MEM 0x1 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */\ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_MISC_INIT_R -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ -#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ -#define I2C_MUX_CH_DEFAULT 0x8 - - -/* - * RapidIO - */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif - -/* - * eSPI - Enhanced SPI - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE 0 -#endif - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ -#define CONFIG_NET_MULTI -#define CONFIG_E1000 -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define FM1_10GEC1_PHY_ADDR 0x3 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC3" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -#endif - -/* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 -#endif - -/* - * USB - */ -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_EXT2 -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_BDI - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t2080qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=t2080qds/t2080qds.dtb\0" \ - "bdev=sda3\0" \ - "c=ffe\0" - -/* - * For emulation this causes u-boot to jump to the start of the - * proof point app code automatically - */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#ifdef CONFIG_SECURE_BOOT -#include -#undef CONFIG_CMD_USB -#endif - -#endif /* __T2080QDS_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h new file mode 100644 index 00000000000..36afe9e0f98 --- /dev/null +++ b/include/configs/T208xQDS.h @@ -0,0 +1,817 @@ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T2080/T2081 QDS board configuration file + */ + +#ifndef __T208xQDS_H +#define __T208xQDS_H + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CONFIG_MMC +#define CONFIG_SPI_FLASH +#define CONFIG_USB_EHCI +#if defined(CONFIG_PPC_T2080) +#define CONFIG_T2080QDS +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_T2081QDS +#endif + +/* High Level Configuration Options */ +#define CONFIG_PHYS_64BIT +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg +#endif +#endif + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifdef CONFIG_SYS_NO_FLASH +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RST_FORCE_MEM 0x1 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_STMICRO +#if defined(CONFIG_T2080QDS) +#define CONFIG_SPI_FLASH_SPANSION +#elif defined(CONFIG_T2081QDS) +#define CONFIG_SPI_FLASH_EON +#endif + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_NET_MULTI +#define CONFIG_E1000 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x3 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t2080qds/t2080qds.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#undef CONFIG_CMD_USB +#endif + +#endif /* __T208xQDS_H */ -- cgit v1.3.1 From ee4d65117d49db094451f2943944777761e9cfad Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Fri, 24 Jan 2014 15:50:06 +0800 Subject: SPL: powerpc: expand SPL's length to 128K 1. The SPL's length of SDCARD boot has not enough,expand the SPL's length to 128K. 2. deleted unused symbol: CONFIG_SYS_RUN_INDDR Signed-off-by: Ying Zhang Reviewed-by: York Sun --- include/configs/P1022DS.h | 12 ++++++------ include/configs/p1_p2_rdb_pc.h | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 6255b0ae4e6..2f431aa927d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -30,12 +30,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_MMC_BOOT @@ -60,12 +60,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_SPI_BOOT diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 117484da872..26b319645eb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -159,12 +159,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_MMC_BOOT @@ -189,12 +189,12 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_SPI_BOOT -- cgit v1.3.1 From 5a89fa927cf6c54efe36918a4894ce31274d9ef1 Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Fri, 24 Jan 2014 15:50:07 +0800 Subject: SPL: P2020RDB: fix the problem booting from spi flash There was no enough stack in SPL, so the buffer needed in SPL is to malloc from memory pool and to repalce the temporary variable. Signed-off-by: Ying Zhang Reviewed-by: York Sun --- common/env_sf.c | 7 ++++++- include/configs/p1_p2_rdb_pc.h | 12 ++++++++---- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/common/env_sf.c b/common/env_sf.c index 9f806fb090f..be270f21bcf 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -299,13 +299,16 @@ int saveenv(void) void env_relocate_spec(void) { - char buf[CONFIG_ENV_SIZE]; int ret; + char *buf = NULL; + buf = (char *)malloc(CONFIG_ENV_SIZE); env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); if (!env_flash) { set_default_env("!spi_flash_probe() failed"); + if (buf) + free(buf); return; } @@ -321,6 +324,8 @@ void env_relocate_spec(void) gd->env_valid = 1; out: spi_flash_free(env_flash); + if (buf) + free(buf); env_flash = NULL; } #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 26b319645eb..07b61795bb9 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -579,11 +579,15 @@ #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) +#if defined(CONFIG_P2020RDB) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) +#else +#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) +#endif #elif defined(CONFIG_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -- cgit v1.3.1 From 27585bd3572f2743fef87adebd9e48b33483c4be Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Fri, 24 Jan 2014 15:50:08 +0800 Subject: SPL: P1022DS: fix the problem booting from spi flash There was no enough memory for malloc in SPL booting from spi flash, so relayout the memory in SPL: reduce the memory for global data from 16K Bytes to 4K Bytes, save the space for malloc. Signed-off-by: Ying Zhang Reviewed-by: York Sun --- include/configs/P1022DS.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 2f431aa927d..139d4fed251 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -365,10 +365,10 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) #elif defined(CONFIG_NAND) #ifdef CONFIG_TPL_BUILD -- cgit v1.3.1 From c9e1f58818c2e6ac13296406125e43775c4daa55 Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Fri, 24 Jan 2014 15:50:09 +0800 Subject: powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPL In the previous patches, we introduced the SPL/TPL fraamework. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Ying Zhang Reviewed-by: York Sun --- board/freescale/p1010rdb/Makefile | 4 + board/freescale/p1010rdb/spl.c | 108 +++++++++++++++++++++++ board/freescale/p1010rdb/spl_minimal.c | 76 ++-------------- board/freescale/p1010rdb/tlb.c | 12 ++- include/configs/P1010RDB.h | 156 +++++++++++++++++++++++++++++++-- 5 files changed, 275 insertions(+), 81 deletions(-) create mode 100644 board/freescale/p1010rdb/spl.c (limited to 'include') diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index d6f05f3cfe4..660d1bbc2aa 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -18,6 +18,10 @@ obj-y += spl_minimal.o tlb.o law.o else +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + obj-y += p1010rdb.o obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c new file mode 100644 index 00000000000..8fed26d693b --- /dev/null +++ b/board/freescale/p1010rdb/spl.c @@ -0,0 +1,108 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + console_init_f(); + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + +#ifdef CONFIG_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init_all(); + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("\nTertiary program loader running in sram..."); +#else + puts("\nSecond program loader running in sram..."); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 39a5a0f37b9..607957003d0 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -16,78 +16,16 @@ DECLARE_GLOBAL_DATA_PTR; - -void sdram_init(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 ddr_ratio; - unsigned long ddr_freq_mhz; - - ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; - ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000; - - /* mask off E bit */ - u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); - - __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - if (ddr_freq_mhz < 700) { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); - } else { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - } - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - - /* P1014 and it's derivatives support max 16bit DDR width */ - if (svr == SVR_P1014) { - __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); - __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); - /* For CS0_BNDS we divide the start and end address by 2, so we can just - * shift the entire register to achieve the desired result and the mask - * the value so we don't write reserved fields */ - __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); - } - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); -} - void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; @@ -98,9 +36,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); - /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -111,6 +46,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index a3d36b35d56..af40f979d36 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -73,10 +73,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1) + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) #endif }; diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f82fbca77cf..eabfc85f0f4 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -21,19 +21,75 @@ #define CONFIG_NAND_FSL_IFC #ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_SPIFLASH +#ifdef CONFIG_SECURE_BOOT #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#else +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif #endif #ifdef CONFIG_NAND #define CONFIG_SPL +#ifdef CONFIG_SECURE_BOOT #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT @@ -51,8 +107,48 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#else +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif #endif - #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ #define CONFIG_RAMBOOT_NAND @@ -473,6 +569,43 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif + /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -480,7 +613,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -637,12 +770,12 @@ extern unsigned long get_sdram_size(void); /* * Environment */ -#if defined(CONFIG_RAMBOOT_SDCARD) +#if defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#elif defined(CONFIG_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 @@ -653,6 +786,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #if defined(CONFIG_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ @@ -660,7 +797,8 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif -#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_OFFSET (1024 * 1024) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -- cgit v1.3.1 From c6e8f49a16915822ffe25904daf1fc9c28115ed4 Mon Sep 17 00:00:00 2001 From: "Haijun.Zhang" Date: Thu, 13 Feb 2014 09:03:02 +0800 Subject: powerpc/mpc8536DS:Increase binary size for mpc8536DS board u-boot binary size for Freescale mpc8536DS platforms is 512KB. This has been reached to upper limit of the platforms and causig linker error. So increase the u-boot binary size to 768KB. Signed-off-by: Haijun Zhang Reviewed-by: York Sun --- include/configs/MPC8536DS.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 57bf04ff816..2505869a911 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -42,7 +42,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -326,7 +326,7 @@ /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) #define CONFIG_SYS_NAND_U_BOOT_START \ (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) @@ -626,7 +626,7 @@ #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -649,11 +649,7 @@ #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 - #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -- cgit v1.3.1 From 4a377552f01b7b19ea5fc02eb844c786751f7247 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 25 Feb 2014 19:26:48 +0900 Subject: kbuild: Move linker sciript check to prepare1 Same as the previous commit. Move sanity check to prepare1 target to avoid nasty troubles. Before this commit, LDSCRIPT existence was not checked when it was specified by CONFIG_SYS_LDSCRIPT. Now LDSCRIPT existence is checked for all boards. $(wildcard $(LDSCRIPT)) must point to the linker scripts with absolute path. Otherwise, make will terminate with a false error on out-of-tree build. Signed-off-by: Masahiro Yamada --- Makefile | 9 +++++---- include/configs/MPC8536DS.h | 2 +- include/configs/MPC8569MDS.h | 2 +- include/configs/MPC8572DS.h | 2 +- include/configs/P1023RDS.h | 2 +- include/configs/P1_P2_RDB.h | 2 +- 6 files changed, 10 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index 7b7c25a1b29..0281171ae83 100644 --- a/Makefile +++ b/Makefile @@ -495,7 +495,7 @@ ifndef LDSCRIPT #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug ifdef CONFIG_SYS_LDSCRIPT # need to strip off double quotes - LDSCRIPT := $(CONFIG_SYS_LDSCRIPT:"%"=%) + LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%) endif endif @@ -518,9 +518,6 @@ ifndef LDSCRIPT # We don't expect a Makefile here LDSCRIPT_MAKEFILE_DIR = endif - ifeq ($(wildcard $(LDSCRIPT)),) -$(error could not find linker script) - endif endif else @@ -996,6 +993,10 @@ ifeq ($(CONFIG_SYS_GENERIC_BOARD),y) @/bin/false endif endif +ifeq ($(wildcard $(LDSCRIPT)),) + @echo >&2 " Could not find linker script." + @/bin/false +endif archprepare: prepare1 scripts_basic diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 57bf04ff816..9846118fb89 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -24,7 +24,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 33cadb93dd9..58b9c26e93d 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -56,7 +56,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f457719bf4f..7b63945888b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -24,7 +24,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index ec72c78861a..2ffa3546de7 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -26,7 +26,7 @@ #ifdef CONFIG_NAND_SPL #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 32ed0c2714c..2ffaf5c0d93 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif -- cgit v1.3.1 From b60eff31f3bd71a6f14b6c6efc8ad5fb3705de6d Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 22 Feb 2014 17:53:43 +0100 Subject: arm: remove unneeded symbol offsets and _TEXT_BASE Remove the last uses of symbol offsets in ARM U-Boot. Remove some needless uses of _TEXT_BASE. Remove all _TEXT_BASE definitions. Signed-off-by: Albert ARIBAUD --- README | 6 ------ arch/arm/cpu/arm1136/start.S | 27 --------------------------- arch/arm/cpu/arm1176/start.S | 27 --------------------------- arch/arm/cpu/arm720t/start.S | 26 -------------------------- arch/arm/cpu/arm920t/start.S | 26 -------------------------- arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 14 +------------- arch/arm/cpu/arm926ejs/mxs/start.S | 27 --------------------------- arch/arm/cpu/arm926ejs/start.S | 27 --------------------------- arch/arm/cpu/arm946es/start.S | 26 -------------------------- arch/arm/cpu/arm_intcm/start.S | 26 -------------------------- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 3 --- arch/arm/cpu/armv7/start.S | 23 ----------------------- arch/arm/cpu/pxa/start.S | 27 --------------------------- arch/arm/cpu/sa1100/start.S | 26 -------------------------- arch/arm/lib/board.c | 12 ++++++------ board/armltd/integrator/lowlevel_init.S | 2 +- board/cm4008/flash.c | 2 +- board/cm41xx/flash.c | 2 +- board/mpl/vcma9/lowlevel_init.S | 5 +---- board/samsung/goni/lowlevel_init.S | 3 --- board/samsung/smdk2410/lowlevel_init.S | 5 +---- board/samsung/smdkc100/lowlevel_init.S | 3 --- board/ti/omap5912osk/lowlevel_init.S | 4 ---- common/board_f.c | 14 +++----------- common/board_r.c | 4 ++-- include/asm-generic/sections.h | 26 +++++++------------------- 26 files changed, 24 insertions(+), 369 deletions(-) (limited to 'include') diff --git a/README b/README index d4eb0992a35..5b7dec98f61 100644 --- a/README +++ b/README @@ -3707,12 +3707,6 @@ Configuration Settings: its config.mk file). If you find problems enabling this option on your board please report the problem and send patches! -- CONFIG_SYS_SYM_OFFSETS - This is set by architectures that use offsets for link symbols - instead of absolute values. So bss_start is obtained using an - offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than - directly. You should not need to touch this setting. - - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) This is set by OMAP boards for the max time that reset should be asserted. See doc/README.omap-reset-time for details on how diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 00d1b30ba63..3e2358e132b 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -70,32 +70,6 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -295,7 +269,6 @@ cpu_init_crit: #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ .align 5 diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ffd7dd0dcd0..ce620115d4d 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -77,33 +77,6 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ - -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index f180eb8aa69..1a348426903 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -67,32 +67,6 @@ _pad: .word 0x12345678 /* now 16*4=64 */ ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index a67b659fd07..7bf094aec13 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -55,32 +55,6 @@ _fiq: .word fiq ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S index e83968fb7a6..a9ec81a75c8 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S @@ -26,27 +26,18 @@ #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL #endif -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init .type lowlevel_init,function lowlevel_init: - mov r5, pc /* r5 = POS1 + 4 current */ POS1: + adr r5, POS1 /* r5 = POS1 run time */ ldr r0, =POS1 /* r0 = POS1 compile */ - ldr r2, _TEXT_BASE - sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */ - sub r5, r5, #4 /* r1 = text base - current */ /* memory control configuration 1 */ ldr r0, =SMRDATA ldr r2, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 0: @@ -149,9 +140,6 @@ PLL_setup_end: ldr r0, =SMRDATA1 ldr r2, =SMRDATA2 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 2: diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 5de2bad5844..34a0fcb462f 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -101,32 +101,6 @@ fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#ifdef CONFIG_SPL_TEXT_BASE - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -207,6 +181,5 @@ _reset: bx lr _hang: - ldr sp, _TEXT_BASE /* switch to abort stack */ 1: bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 5360f55bc1a..0717327050d 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -102,32 +102,6 @@ _fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -330,7 +304,6 @@ flush_dcache: #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* switch to abort stack */ 1: bl 1b /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index e16b0881410..7d501458362 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -71,32 +71,6 @@ _vectors_end: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 5783df1ef2a..7404ea73481 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -67,32 +67,6 @@ _fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 6f7261b7b8e..78577b1d1c7 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -17,9 +17,6 @@ #include #include -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - #ifdef CONFIG_SPL_BUILD ENTRY(save_boot_params) ldr r4, =omap3_boot_device diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5aac7736444..ac1e55a708d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -70,29 +70,6 @@ _end_vect: * *************************************************************************/ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index d8fb812dbf0..ae0d13ce8fe 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -84,32 +84,6 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -316,7 +290,6 @@ cpu_init_crit: #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ .align 5 diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 27bcda598c6..bf80937a7c7 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -56,32 +56,6 @@ _fiq: .word fiq ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index c320a35166b..1de58122e40 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -105,8 +105,8 @@ static int display_banner(void) { printf("\n\n%s\n\n", version_string); debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", - _TEXT_BASE, - _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE); + (ulong)&_start, + (ulong)&__bss_start, (ulong)&__bss_end); #ifdef CONFIG_MODEM_SUPPORT debug("Modem Support enabled\n"); #endif @@ -273,13 +273,13 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, sizeof(gd_t)); - gd->mon_len = _bss_end_ofs; + gd->mon_len = (ulong)&__bss_end - (ulong)_start; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ gd->fdt_blob = __dtb_db_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ - gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); + gd->fdt_blob = &_end; #endif /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, @@ -451,7 +451,7 @@ void board_init_f(ulong bootflag) gd->relocaddr = addr; gd->start_addr_sp = addr_sp; - gd->reloc_off = addr - _TEXT_BASE; + gd->reloc_off = addr - (ulong)&_start; debug("relocation Offset is: %08lx\n", gd->reloc_off); if (new_fdt) { memcpy(new_fdt, gd->fdt_blob, fdt_size); @@ -516,7 +516,7 @@ void board_init_r(gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); - monitor_flash_len = _end_ofs; + monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start; /* Enable caches */ enable_caches(); diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S index 389d5e90836..0fb42adc6fe 100644 --- a/board/armltd/integrator/lowlevel_init.S +++ b/board/armltd/integrator/lowlevel_init.S @@ -183,7 +183,7 @@ cm_remap: /* Now 0x00000000 is writeable, replace the vectors */ ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_TEXT_BASE /* r2 <- past vectors */ + add r2, r0, #64 /* r2 <- past vectors */ sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 251192839e7..8315a57ed9a 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init (void) */ flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start_ofs, + CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), &flash_info[0]); return size; diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 251192839e7..8315a57ed9a 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init (void) */ flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start_ofs, + CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), &flash_info[0]); return size; diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index b889cf94af6..cca9c0c880b 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -197,13 +197,10 @@ #define REFCNT_266 0 /**************************************/ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: /* use r0 to relocate DATA read/write to flash rather than memory ! */ - ldr r0, _TEXT_BASE + ldr r0, =CONFIG_SYS_TEXT_BASE ldr r13, =BWSCON /* enable minimal access to PLD */ diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 726211a336e..d52bc09f8d2 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -22,9 +22,6 @@ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r11, lr diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S index c7b78fd103e..5de04f10e9a 100644 --- a/board/samsung/smdk2410/lowlevel_init.S +++ b/board/samsung/smdk2410/lowlevel_init.S @@ -110,16 +110,13 @@ #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ /**************************************/ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: /* memory control configuration */ /* make r0 relative the current location so that it */ /* reads SMRDATA out of FLASH rather than memory ! */ ldr r0, =SMRDATA - ldr r1, _TEXT_BASE + ldr r1, =CONFIG_SYS_TEXT_BASE sub r0, r0, r1 ldr r1, =BWSCON /* Bus Width Status Controller */ add r2, r0, #13*4 diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 4df0974af58..65e6b7a73a8 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -17,9 +17,6 @@ * r5 has zero always */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r9, lr diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S index cad0a5acd87..e05a1c7b557 100644 --- a/board/ti/omap5912osk/lowlevel_init.S +++ b/board/ti/omap5912osk/lowlevel_init.S @@ -18,10 +18,6 @@ #include <./configs/omap1510.h> #endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - .globl lowlevel_init lowlevel_init: diff --git a/common/board_f.c b/common/board_f.c index 02965b0df76..5b9ba07d636 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -149,13 +149,9 @@ static int display_text_info(void) #ifndef CONFIG_SANDBOX ulong bss_start, bss_end; -#ifdef CONFIG_SYS_SYM_OFFSETS - bss_start = _bss_start_ofs + _TEXT_BASE; - bss_end = _bss_end_ofs + _TEXT_BASE; -#else bss_start = (ulong)&__bss_start; bss_end = (ulong)&__bss_end; -#endif + debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", CONFIG_SYS_TEXT_BASE, bss_start, bss_end); #endif @@ -279,8 +275,8 @@ static int zero_global_data(void) static int setup_mon_len(void) { -#ifdef CONFIG_SYS_SYM_OFFSETS - gd->mon_len = _bss_end_ofs; +#ifdef __ARM__ + gd->mon_len = (ulong)&__bss_end - (ulong)_start; #elif defined(CONFIG_SANDBOX) gd->mon_len = (ulong)&_end - (ulong)_init; #else @@ -363,11 +359,7 @@ static int setup_fdt(void) gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ -# ifdef CONFIG_SYS_SYM_OFFSETS - gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE); -# else gd->fdt_blob = (ulong *)&_end; -# endif #elif defined(CONFIG_OF_HOSTFILE) if (read_fdt_from_file()) { puts("Failed to read control FDT\n"); diff --git a/common/board_r.c b/common/board_r.c index c2d0763b576..899f377e174 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -128,8 +128,8 @@ __weak int fixup_cpu(void) static int initr_reloc_global_data(void) { -#ifdef CONFIG_SYS_SYM_OFFSETS - monitor_flash_len = _end_ofs; +#ifdef __ARM__ + monitor_flash_len = _end - __image_copy_start; #elif !defined(CONFIG_SANDBOX) monitor_flash_len = (ulong)&__init_end - gd->relocaddr; #endif diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 7e1eb4bf5e0..458952fb58c 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -63,28 +63,16 @@ extern char __image_copy_end[]; extern void _start(void); /* - * ARM needs to use offsets for symbols, since the values of some symbols - * are not resolved prior to relocation (and are just 0). Maybe this can be - * resolved, or maybe other architectures are similar, iwc this should be - * promoted to an architecture option. + * ARM defines its symbols as char[]. Other arches define them as ulongs. */ #ifdef CONFIG_ARM -#define CONFIG_SYS_SYM_OFFSETS -#endif - -#ifdef CONFIG_SYS_SYM_OFFSETS -/* Start/end of the relocation entries, as an offset from _start */ -extern ulong _rel_dyn_start_ofs; -extern ulong _rel_dyn_end_ofs; - -/* End of the region to be relocated, as an offset form _start */ -extern ulong _image_copy_end_ofs; -extern ulong _bss_start_ofs; /* BSS start relative to _start */ -extern ulong _bss_end_ofs; /* BSS end relative to _start */ -extern ulong _end_ofs; /* end of image relative to _start */ - -extern ulong _TEXT_BASE; /* code start */ +extern char __bss_start[]; +extern char __bss_end[]; +extern char __image_copy_start[]; +extern char __image_copy_end[]; +extern char __rel_dyn_start[]; +extern char __rel_dyn_end[]; #else /* don't use offsets: */ -- cgit v1.3.1 From 9c653aad169ffdc9e18482970df9de1a29773034 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 18 Feb 2014 07:31:52 -0500 Subject: drivers: net: cpsw: add support to have phy address from cpsw platform data Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi Signed-off-by: Mugunthan V N [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini --- board/BuR/common/common.c | 4 ++-- board/compulab/cm_t335/cm_t335.c | 2 +- board/isee/igep0033/board.c | 2 +- board/phytec/pcm051/board.c | 4 ++-- board/siemens/dxr2/board.c | 2 +- board/siemens/pxm2/board.c | 4 ++-- board/siemens/rut/board.c | 4 ++-- board/silica/pengwyn/board.c | 4 ++-- board/ti/am335x/board.c | 4 ++-- board/ti/dra7xx/evm.c | 4 ++-- board/ti/ti814x/evm.c | 4 ++-- drivers/net/cpsw.c | 4 ++-- include/configs/am335x_evm.h | 1 - include/configs/am335x_igep0033.h | 1 - include/configs/bur_am335x_common.h | 1 - include/configs/cm_t335.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/dxr2.h | 1 - include/configs/pcm051.h | 1 - include/configs/pengwyn.h | 1 - include/configs/pxm2.h | 1 - include/configs/rut.h | 1 - include/configs/ti814x_evm.h | 1 - include/cpsw.h | 2 +- 24 files changed, 22 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 6d187eaab20..04f3f1f4b23 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -141,12 +141,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, }, }; diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 01019e8eb2f..9583149bed6 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -47,7 +47,7 @@ static void cpsw_control(int enabled) static struct cpsw_slave_data cpsw_slave = { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }; diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 089a835e0c6..9f8fcf2c1cf 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -116,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 7e5e07ff232..1071662ea9e 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -176,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RGMII, }, }; diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 6c316faa8f1..9b8f538312e 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -198,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_MII, }, }; diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index ef3d6cc158d..98083d52cd9 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -181,13 +181,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 25ab54d9a2a..e0ada3f6a5f 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -143,13 +143,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c index a553129d29d..ee88b6f3990 100644 --- a/board/silica/pengwyn/board.c +++ b/board/silica/pengwyn/board.c @@ -141,13 +141,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_MII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_MII, }, }; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57217688d63..862f966e7cf 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -544,12 +544,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, }, }; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index bed828584bf..7990e7990d4 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -149,12 +149,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 2, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 3, }, }; diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 140ad7103ad..54b3dfb82c5 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -132,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x50, .sliver_reg_ofs = 0x700, - .phy_id = 1, + .phy_addr = 1, }, { .slave_reg_ofs = 0x90, .sliver_reg_ofs = 0x740, - .phy_id = 0, + .phy_addr = 0, }, }; diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 50167aab63a..dd6c26a7fb3 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -656,7 +656,7 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); - priv->phy_mask |= 1 << slave->data->phy_id; + priv->phy_mask |= 1 << slave->data->phy_addr; } static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) @@ -948,7 +948,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) SUPPORTED_1000baseT_Full); phydev = phy_connect(priv->bus, - CONFIG_PHY_ADDR, + slave->data->phy_addr, dev, slave->data->phy_if); diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 59a8f36d169..23c056c82cb 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -398,7 +398,6 @@ /* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC /* NAND support */ diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 115d1b37c9e..e72ee05ec8c 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -181,7 +181,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_NET_MULTI #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC /* NAND support */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 1f57bd2744f..7bbe5964ae8 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -51,7 +51,6 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_SPL_ETH_SUPPORT #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_NATSEMI #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 56e9a8e0e82..26b615b8c50 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -114,7 +114,6 @@ /* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_ATHEROS /* NAND support */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index c67cf60c0c6..291c538a346 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -62,7 +62,6 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 2 /* SPI */ #undef CONFIG_OMAP3_SPI diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h index 1e42f5c23c9..e95d74c04c7 100644 --- a/include/configs/dxr2.h +++ b/include/configs/dxr2.h @@ -49,7 +49,6 @@ #undef CONFIG_MII #undef CONFIG_PHY_GIGE -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #define CONFIG_FACTORYSET diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 6f41ee77183..9af3efd4b1a 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -297,7 +297,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 5a555567d02..fc25966e0f2 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -196,7 +196,6 @@ /* Network */ #define CONFIG_CMD_MII #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_RESET 1 #define CONFIG_PHY_NATSEMI diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7722f7be2e7..6276d43395e 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -44,7 +44,6 @@ #undef CONFIG_SPL_NET_VCI_STRING #undef CONFIG_SPL_ETH_SUPPORT -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_ATHEROS #define CONFIG_FACTORYSET diff --git a/include/configs/rut.h b/include/configs/rut.h index d4519f946c3..6bddededaeb 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -41,7 +41,6 @@ #undef CONFIG_SPL_NET_VCI_STRING #undef CONFIG_SPL_ETH_SUPPORT -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_NATSEMI #define CONFIG_FACTORYSET diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index ba16b1c14b5..b51400c4640 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -233,7 +233,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_ET1011C #define CONFIG_PHY_ET1011C_TX_CLK_FIX diff --git a/include/cpsw.h b/include/cpsw.h index 743cb96e7e9..a73843d2f75 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -19,7 +19,7 @@ struct cpsw_slave_data { u32 slave_reg_ofs; u32 sliver_reg_ofs; - int phy_id; + int phy_addr; int phy_if; }; -- cgit v1.3.1 From 4cdd7fda913df76e1267827b71d451e1c07af441 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 18 Feb 2014 07:31:54 -0500 Subject: ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVM Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected to RMII and RGMII phy respectively and enable cpsw in config. Reviewed-by: Felipe Balbi Signed-off-by: Mugunthan V N --- board/ti/am43xx/board.c | 100 +++++++++++++++++++++++++++++++++++++++++++ board/ti/am43xx/mux.c | 44 ++++++++++++++++++- include/configs/am43xx_evm.h | 20 +++++++++ 3 files changed, 162 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 95fd13751b4..0c9f0ef168c 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,9 +19,15 @@ #include #include #include "board.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SPL_BUILD +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#endif + /* * Read header information from EEPROM into global structure. */ @@ -402,3 +408,97 @@ int board_late_init(void) return 0; } #endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + /* Additional controls can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 16, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("ethaddr")) { + puts(" not set. Validating first E-fuse MAC\n"); + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + if (board_is_eposevm()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 16; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 0; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index c330a81c4a2..77c53d2e90e 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -11,6 +11,41 @@ #include #include "board.h" +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */ + {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */ + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {-1}, +}; + +static struct module_pin_mux mdio_pin_mux[] = { + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, @@ -57,10 +92,15 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mdio_pin_mux); - if (board_is_gpevm()) + if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); - configure_module_pin_mux(qspi_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + } else if (board_is_eposevm()) { + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(qspi_pin_mux); + } } void enable_i2c0_pin_mux(void) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index c773a183691..aff17ee74e4 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -204,5 +204,25 @@ "run mmcboot;" \ "run usbboot;" +/* CPSW Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_SYS_RX_ETH_BUFFER 64 +#define CONFIG_PHY_ADDR 16 + #endif #endif /* __CONFIG_AM43XX_EVM_H */ -- cgit v1.3.1 From a35ad51efe363abdc72473b32aea2c1bb271995f Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 18 Feb 2014 07:31:55 -0500 Subject: ARM: AM335x: add support for reading cpsw 2nd mac address from efuse Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also adding mii command support to am335x common config. Acked-by: Tom Rini Signed-off-by: Mugunthan V N --- board/ti/am335x/board.c | 15 +++++++++++++++ include/configs/ti_am335x_common.h | 1 + 2 files changed, 16 insertions(+) (limited to 'include') diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 862f966e7cf..7609a183684 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -602,6 +602,21 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_DRIVER_TI_CPSW + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 7e9ca01cd5a..50c32037ffb 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -30,6 +30,7 @@ /* Network defines. */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME -- cgit v1.3.1 From 3a3939bf3d216900486748ffc330a33d565c242b Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 18 Feb 2014 07:31:58 -0500 Subject: ARM: AM43xx: Add Ethernet boot support to SPL Add Ethernet Boot support to SPL Acked-by: Tom Rini Signed-off-by: Mugunthan V N --- board/ti/am43xx/board.c | 2 -- include/configs/am43xx_evm.h | 10 ++++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 7a2806320da..d7449770a3f 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -24,9 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -#endif /* * Read header information from EEPROM into global structure. diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index aff17ee74e4..614857dd25c 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -204,6 +204,8 @@ "run mmcboot;" \ "run usbboot;" +#endif + /* CPSW Ethernet */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP @@ -221,8 +223,12 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB + +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL" + +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_NET_SUPPORT #define CONFIG_SYS_RX_ETH_BUFFER 64 -#define CONFIG_PHY_ADDR 16 -#endif #endif /* __CONFIG_AM43XX_EVM_H */ -- cgit v1.3.1 From cc07294bc704694ae33db75b25ac557e5917a83f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 25 Feb 2014 11:07:22 +0100 Subject: arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup Since the switch may be re-configured for VLAN usage in Linux (or any other OS), lets reset the switch to its default register values upon power-up. Otherwise network might not be available in U-Boot. Signed-off-by: Stefan Roese Cc: Heiko Schocher Cc: Roger Meier Cc: Lukas Stockmann Cc: Tom Rini --- board/siemens/dxr2/board.c | 7 +++++++ board/siemens/dxr2/mux.c | 2 ++ include/configs/dxr2.h | 1 + 3 files changed, 10 insertions(+) (limited to 'include') diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 9b8f538312e..217237900e3 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -232,6 +232,13 @@ int board_eth_init(bd_t *bis) factoryset_setenv(); + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + /* Set rgmii mode and enable rmii clock to be sourced from chip */ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c index 5c22999bb8a..f2314b5d3e5 100644 --- a/board/siemens/dxr2/mux.c +++ b/board/siemens/dxr2/mux.c @@ -221,6 +221,8 @@ static struct module_pin_mux gpios_pin_mux[] = { {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, + /* nRST for SMSC LAN9303 switch - GPIO2_24 */ + {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */ {-1}, }; diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h index e95d74c04c7..75f7812e7d6 100644 --- a/include/configs/dxr2.h +++ b/include/configs/dxr2.h @@ -26,6 +26,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 #define BOARD_DFU_BUTTON_LED 64 +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ #undef CONFIG_DOS_PARTITION #undef CONFIG_CMD_FAT -- cgit v1.3.1