From d7608aba38d760be4c40cb8f4591057e5e40c2d4 Mon Sep 17 00:00:00 2001 From: Oleksandr Tymoshenko Date: Mon, 24 Oct 2016 10:47:01 -0700 Subject: efi: Use device device path type Messaging for network interface node When adding network interface node use Messaging device path with subtype MAC Address and device's MAC address as a value instead of Media Device path type with subtype File Path and path "Net" Signed-off-by: Oleksandr Tymoshenko Signed-off-by: Alexander Graf --- include/efi_api.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index bdb600e08d7..5c3836a51be 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -268,6 +268,19 @@ struct efi_device_path { u16 length; }; +struct efi_mac_addr { + u8 addr[32]; +}; + +#define DEVICE_PATH_TYPE_MESSAGING_DEVICE 0x03 +# define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b + +struct efi_device_path_mac_addr { + struct efi_device_path dp; + struct efi_mac_addr mac; + u8 if_type; +}; + #define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04 # define DEVICE_PATH_SUB_TYPE_FILE_PATH 0x04 -- cgit v1.3.1 From 5abd9137d5329e84827c265bc950287043eac636 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 7 Nov 2016 08:47:06 -0700 Subject: x86: Tidy up selection of building the EFI stub At present we use a CONFIG option in efi.h to determine whether we are building the EFI stub or not. This means that the same header cannot be used for EFI_LOADER support. The CONFIG option will be enabled for the whole build, even when not building the stub. Use a different define instead, set up just for the files that make up the stub. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Signed-off-by: Alexander Graf --- include/efi.h | 7 +++++-- lib/efi/Makefile | 4 ++-- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/efi.h b/include/efi.h index d07187c7dd0..3d587807e8c 100644 --- a/include/efi.h +++ b/include/efi.h @@ -30,8 +30,11 @@ struct efi_device_path; #define EFI_BITS_PER_LONG BITS_PER_LONG -/* With 64-bit EFI stub, EFI_BITS_PER_LONG has to be 64 */ -#ifdef CONFIG_EFI_STUB_64BIT +/* + * With 64-bit EFI stub, EFI_BITS_PER_LONG has to be 64. EFI_STUB is set + * in lib/efi/Makefile, when building the stub. + */ +#if defined(CONFIG_EFI_STUB_64BIT) && defined(EFI_STUB) #undef EFI_BITS_PER_LONG #define EFI_BITS_PER_LONG 64 #endif diff --git a/lib/efi/Makefile b/lib/efi/Makefile index e32dc14f3d6..9449600b5bd 100644 --- a/lib/efi/Makefile +++ b/lib/efi/Makefile @@ -9,9 +9,9 @@ obj-$(CONFIG_EFI_STUB) += efi_info.o CFLAGS_REMOVE_efi_stub.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -CFLAGS_efi_stub.o := -fpic -fshort-wchar +CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB CFLAGS_REMOVE_efi.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -CFLAGS_efi.o := -fpic -fshort-wchar +CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB extra-$(CONFIG_EFI_STUB) += efi_stub.o efi.o -- cgit v1.3.1 From c7ae3dfdccc171543804d6577ee41ab03e7a09bc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 7 Nov 2016 08:47:08 -0700 Subject: efi: Add support for a hello world test program It is useful to have a basic sanity check for EFI loader support. Add a 'bootefi hello' command which loads HelloWord.efi and runs it under U-Boot. Signed-off-by: Simon Glass [agraf: Fix documentation, add unfulfilled kconfig dep] Signed-off-by: Alexander Graf --- cmd/Kconfig | 9 +++++++++ cmd/bootefi.c | 27 +++++++++++++++++++++------ doc/README.efi | 14 ++++++++++++++ include/asm-generic/sections.h | 2 ++ lib/efi_loader/Makefile | 4 ++++ lib/efi_loader/helloworld.c | 24 ++++++++++++++++++++++++ scripts/Makefile.lib | 33 +++++++++++++++++++++++++++++++++ 7 files changed, 107 insertions(+), 6 deletions(-) create mode 100644 lib/efi_loader/helloworld.c (limited to 'include') diff --git a/cmd/Kconfig b/cmd/Kconfig index e339d8638aa..ebcfd6ddaf0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -181,6 +181,15 @@ config CMD_BOOTEFI help Boot an EFI image from memory. +config CMD_BOOTEFI_HELLO + bool "Allow booting a standard EFI hello world for testing" + depends on CMD_BOOTEFI && NEED_CRT0_ENABLEMENT + help + This adds a standard EFI hello world application to U-Boot so that + it can be used with the 'bootefi hello' command. This is useful + for testing that EFI is working at a basic level, and for bringing + up EFI support on a new architecture. + config CMD_ELF bool "bootelf, bootvx" default y diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 3ab256ec51f..ae1b713197c 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -239,13 +239,23 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 2) return CMD_RET_USAGE; - saddr = argv[1]; +#ifdef CONFIG_CMD_BOOTEFI_HELLO + if (!strcmp(argv[1], "hello")) { + ulong size = __efi_hello_world_end - __efi_hello_world_begin; - addr = simple_strtoul(saddr, NULL, 16); + addr = CONFIG_SYS_LOAD_ADDR; + memcpy((char *)addr, __efi_hello_world_begin, size); + } else +#endif + { + saddr = argv[1]; - if (argc > 2) { - sfdt = argv[2]; - fdt_addr = simple_strtoul(sfdt, NULL, 16); + addr = simple_strtoul(saddr, NULL, 16); + + if (argc > 2) { + sfdt = argv[2]; + fdt_addr = simple_strtoul(sfdt, NULL, 16); + } } printf("## Starting EFI application at %08lx ...\n", addr); @@ -263,7 +273,12 @@ static char bootefi_help_text[] = " [fdt address]\n" " - boot EFI payload stored at address .\n" " If specified, the device tree located at gets\n" - " exposed as EFI configuration table.\n"; + " exposed as EFI configuration table.\n" +#ifdef CONFIG_CMD_BOOTEFI_HELLO + "hello\n" + " - boot a sample Hello World application stored within U-Boot" +#endif + ; #endif U_BOOT_CMD( diff --git a/doc/README.efi b/doc/README.efi index 1fd3f004c39..66259f3e260 100644 --- a/doc/README.efi +++ b/doc/README.efi @@ -310,6 +310,20 @@ Removable media booting (search for /efi/boot/boota{a64,arm}.efi) is supported. Simple use cases like "Plug this SD card into my ARM device and it just boots into grub which boots into Linux", work very well. + +Running HelloWord.efi +--------------------- + +You can run a simple 'hello world' EFI program in U-Boot. +Enable the option CONFIG_CMD_BOOTEFI_HELLO. + +Then you can boot into U-Boot and type: + + > bootefi hello + +The 'hello world EFI' program will then run, print a message and exit. + + Future work ----------- diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index d69bc6035be..daf021b647e 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -22,6 +22,8 @@ extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __entry_text_start[], __entry_text_end[]; extern char __initdata_begin[], __initdata_end[]; extern char __start_rodata[], __end_rodata[]; +extern char __efi_hello_world_begin[]; +extern char __efi_hello_world_end[]; /* Start and end of .ctors section - used for constructor calls. */ extern char __ctors_start[], __ctors_end[]; diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 12159dd5ce8..f4664085e57 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -7,6 +7,10 @@ # This file only gets included with CONFIG_EFI_LOADER set, so all # object inclusion implicitly depends on it +CFLAGS_helloworld.o := $(CFLAGS_EFI) +CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI) + +obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o obj-y += efi_memory.o obj-$(CONFIG_LCD) += efi_gop.o diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c new file mode 100644 index 00000000000..03e65ab1336 --- /dev/null +++ b/lib/efi_loader/helloworld.c @@ -0,0 +1,24 @@ +/* + * EFI hello world + * + * Copyright (c) 2016 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +efi_status_t EFIAPI efi_main(efi_handle_t handle, + struct efi_system_table *systable) +{ + struct efi_simple_text_output_protocol *con_out = systable->con_out; + struct efi_boot_services *boottime = systable->boottime; + + con_out->output_string(con_out, L"Hello, world!\n"); + boottime->exit(handle, 0, 0, NULL); + + return EFI_SUCCESS; +} diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 45a0e1d486c..956a8a9b044 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -321,6 +321,39 @@ cmd_S_ttf= \ $(obj)/%.S: $(src)/%.ttf $(call cmd,S_ttf) +# EFI Hello World application +# --------------------------------------------------------------------------- + +# Generate an assembly file to wrap the EFI app +cmd_S_efi= \ +( \ + echo '.section .rodata.efi.init,"a"'; \ + echo '.balign 16'; \ + echo '.global __efi_hello_world_begin'; \ + echo '__efi_hello_world_begin:'; \ + echo '.incbin "$<" '; \ + echo '__efi_hello_world_end:'; \ + echo '.global __efi_hello_world_end'; \ + echo '.balign 16'; \ +) > $@ + +$(obj)/%_efi.S: $(obj)/%.efi + $(call cmd,S_efi) + +$(obj)/%.efi: $(obj)/%.so + $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j .dynamic \ + -j .dynsym -j .rel* -j .rela* -j .reloc \ + $(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@ + +EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS) + +$(obj)/helloworld.so: $(EFI_LDS_PATH) + +$(obj)/helloworld.so: $(obj)/helloworld.o arch/$(ARCH)/lib/$(EFI_CRT0) \ + arch/$(ARCH)/lib/$(EFI_RELOC) + $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared -Bsymbolic \ + $^ -o $@ + # ACPI # --------------------------------------------------------------------------- quiet_cmd_acpi_c_asl= ASL $< -- cgit v1.3.1 From c70f74a081c2005b0a4749cf8762fc14b7369ddb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 7 Nov 2016 08:47:09 -0700 Subject: elf: arm: Add a few ARM relocation types Rather than hard-coding the relocation type, add it to the ELF header file and use it from there. Signed-off-by: Simon Glass Signed-off-by: Alexander Graf --- arch/arm/lib/relocate.S | 3 ++- arch/arm/lib/relocate_64.S | 3 ++- include/elf.h | 13 +++++++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 475d503dd9d..a6fb07c401d 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -8,6 +8,7 @@ #include #include +#include #include #ifdef CONFIG_CPU_V7M #include @@ -96,7 +97,7 @@ copy_loop: fixloop: ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */ and r1, r1, #0xff - cmp r1, #23 /* relative fixup? */ + cmp r1, #R_ARM_RELATIVE bne fixnext /* relative fix: increase location by offset */ diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 5c51cae8ab0..242e56e9608 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -47,7 +48,7 @@ fixloop: ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ ldr x4, [x2], #8 /* x4 <- addend */ and x1, x1, #0xffffffff - cmp x1, #1027 /* relative fixup? */ + cmp x1, #R_AARCH64_RELATIVE bne fixnext /* relative fix: store addend plus offset at dest location */ diff --git a/include/elf.h b/include/elf.h index bcc5eb7b079..aaecac799ef 100644 --- a/include/elf.h +++ b/include/elf.h @@ -13,6 +13,7 @@ #ifndef _ELF_H #define _ELF_H +#ifndef __ASSEMBLER__ #include "compiler.h" /* @@ -517,6 +518,8 @@ unsigned long elf_hash(const unsigned char *name); #define ELF_TARG_VER 1 /* The ver for which this code is intended */ +#endif /* __ASSEMBLER */ + /* * XXX - PowerPC defines really don't belong in here, * but we'll put them in for simplicity. @@ -602,6 +605,16 @@ unsigned long elf_hash(const unsigned char *name); that may still be in object files. */ #define R_PPC_TOC16 255 + /* ARM relocs */ +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ + +/* AArch64 relocs */ +#define R_AARCH64_NONE 0 /* No relocation. */ +#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */ + +#ifndef __ASSEMBLER__ int valid_elf_image(unsigned long addr); +#endif #endif /* _ELF_H */ -- cgit v1.3.1 From 2d48caa47de849c6ecd9f8f1db784a985aa55b2d Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 30 Sep 2016 08:13:13 +0200 Subject: ARM: zynq: Add support for the topic-miami system-on-modules and carrier boards The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 2 + arch/arm/dts/zynq-topic-miami.dts | 97 +++++++++ arch/arm/dts/zynq-topic-miamiplus.dts | 17 ++ board/topic/zynq/MAINTAINERS | 6 + board/topic/zynq/Makefile | 10 + board/topic/zynq/board.c | 1 + board/topic/zynq/ps7_init_common.c | 117 +++++++++++ board/topic/zynq/ps7_init_gpl.h | 34 +++ board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 227 ++++++++++++++++++++ board/topic/zynq/zynq-topic-miami/ps7_regs.txt | 61 ++++++ .../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 233 +++++++++++++++++++++ board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt | 61 ++++++ configs/topic_miami_defconfig | 49 +++++ configs/topic_miamiplus_defconfig | 49 +++++ include/configs/topic_miami.h | 149 +++++++++++++ include/configs/topic_miamiplus.h | 2 + 16 files changed, 1115 insertions(+) create mode 100644 arch/arm/dts/zynq-topic-miami.dts create mode 100644 arch/arm/dts/zynq-topic-miamiplus.dts create mode 100644 board/topic/zynq/MAINTAINERS create mode 100644 board/topic/zynq/Makefile create mode 100644 board/topic/zynq/board.c create mode 100644 board/topic/zynq/ps7_init_common.c create mode 100644 board/topic/zynq/ps7_init_gpl.h create mode 100644 board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c create mode 100644 board/topic/zynq/zynq-topic-miami/ps7_regs.txt create mode 100644 board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c create mode 100644 board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt create mode 100644 configs/topic_miami_defconfig create mode 100644 configs/topic_miamiplus_defconfig create mode 100644 include/configs/topic_miami.h create mode 100644 include/configs/topic_miamiplus.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 836a8c4d1ee..2c5b2f22c64 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -97,6 +97,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zybo.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ + zynq-topic-miami.dtb \ + zynq-topic-miamiplus.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts new file mode 100644 index 00000000000..8e988f92877 --- /dev/null +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -0,0 +1,97 @@ +/* + * Topic Miami board DTS + * + * Copyright (C) 2014-2016 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Topic Miami Zynq Board"; + compatible = "topic,miami", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + spi0 = &qspi; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "st,m25p80", "n25q256a"; + m25p,fast-read; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <100000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-u-boot-spl { + label = "qspi-u-boot-spl"; + reg = <0x00000 0x10000>; + }; + partition@qspi-u-boot-img { + label = "qspi-u-boot-img"; + reg = <0x10000 0x60000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x70000 0x10000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x80000 0x400000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x480000 0x1b80000>; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts new file mode 100644 index 00000000000..3036f6ea9cf --- /dev/null +++ b/arch/arm/dts/zynq-topic-miamiplus.dts @@ -0,0 +1,17 @@ +/* + * Topic Miami Plus board DTS + * + * Copyright (C) 2016 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include "zynq-topic-miami.dts" + +/ { + model = "Topic Miami+ Zynq Board"; + compatible = "topic,miamiplus", "xlnx,zynq-7000"; +}; + +&qspi { + is-dual = <1>; +}; diff --git a/board/topic/zynq/MAINTAINERS b/board/topic/zynq/MAINTAINERS new file mode 100644 index 00000000000..d795b304e5e --- /dev/null +++ b/board/topic/zynq/MAINTAINERS @@ -0,0 +1,6 @@ +TOPIC BOARD +M: Mike Looijmans +S: Maintained +F: board/topic/zynq/ +F: include/configs/topic*.h +F: configs/topic_*_defconfig diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile new file mode 100644 index 00000000000..eaf59cd55c6 --- /dev/null +++ b/board/topic/zynq/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o + +# Remove quotes +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) + +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o diff --git a/board/topic/zynq/board.c b/board/topic/zynq/board.c new file mode 100644 index 00000000000..a95c9d1eff0 --- /dev/null +++ b/board/topic/zynq/board.c @@ -0,0 +1 @@ +#include "../../xilinx/zynq/board.c" diff --git a/board/topic/zynq/ps7_init_common.c b/board/topic/zynq/ps7_init_common.c new file mode 100644 index 00000000000..b1d45c242f8 --- /dev/null +++ b/board/topic/zynq/ps7_init_common.c @@ -0,0 +1,117 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "ps7_init_gpl.h" +#include + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 +#define APU_FREQ 666666666 + +#define PS7_MASK_POLL_TIME 100000000 + +/* IO accessors. No memory barriers desired. */ +static inline void iowrite(unsigned long val, unsigned long addr) +{ + __raw_writel(val, addr); +} + +static inline unsigned long ioread(unsigned long addr) +{ + return __raw_readl(addr); +} + +/* start timer */ +static void perf_start_clock(void) +{ + iowrite((1 << 0) | /* Timer Enable */ + (1 << 3) | /* Auto-increment */ + (0 << 8), /* Pre-scale */ + SCU_GLOBAL_TIMER_CONTROL); +} + +/* Compute mask for given delay in miliseconds*/ +static int get_number_of_cycles_for_delay(unsigned int delay) +{ + return (APU_FREQ / (2 * 1000)) * delay; +} + +/* stop timer */ +static void perf_disable_clock(void) +{ + iowrite(0, SCU_GLOBAL_TIMER_CONTROL); +} + +/* stop timer and reset timer count regs */ +static void perf_reset_clock(void) +{ + perf_disable_clock(); + iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32); + iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32); +} + +static void perf_reset_and_start_timer(void) +{ + perf_reset_clock(); + perf_start_clock(); +} + +int ps7_config(unsigned long *ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + unsigned long opcode; + unsigned long addr; + unsigned long val; + unsigned long mask; + unsigned int numargs; + int i; + int delay; + + for (;;) { + opcode = ptr[0]; + if (opcode == OPCODE_EXIT) + return PS7_INIT_SUCCESS; + addr = (opcode & OPCODE_ADDRESS_MASK); + + switch (opcode & ~OPCODE_ADDRESS_MASK) { + case OPCODE_MASKWRITE: + numargs = 3; + mask = ptr[1]; + val = ptr[2]; + iowrite((ioread(addr) & ~mask) | (val & mask), addr); + break; + + case OPCODE_MASKPOLL: + numargs = 2; + mask = ptr[1]; + i = 0; + while (!(ioread(addr) & mask)) { + if (i == PS7_MASK_POLL_TIME) + return PS7_INIT_TIMEOUT; + i++; + } + break; + + case OPCODE_MASKDELAY: + numargs = 2; + mask = ptr[1]; + delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while (ioread(addr) < delay) + ; + break; + + default: + return PS7_INIT_CORRUPT; + } + + ptr += numargs; + } +} diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h new file mode 100644 index 00000000000..ef719acabad --- /dev/null +++ b/board/topic/zynq/ps7_init_gpl.h @@ -0,0 +1,34 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define OPCODE_EXIT 0U +#define OPCODE_MASKWRITE 0U +#define OPCODE_MASKPOLL 1U +#define OPCODE_MASKDELAY 2U +#define OPCODE_ADDRESS_MASK (~3U) + +/* Sentinel */ +#define EMIT_EXIT() OPCODE_EXIT +/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */ +#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val +#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask +#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask + +/* Returns codes of ps7_init* */ +#define PS7_INIT_SUCCESS (0) +#define PS7_INIT_CORRUPT (1) +#define PS7_INIT_TIMEOUT (2) +#define PS7_POLL_FAILED_DDR_INIT (3) +#define PS7_POLL_FAILED_DMA (4) +#define PS7_POLL_FAILED_PLL (5) + +/* Called by spl.c */ +int ps7_init(void); +int ps7_post_config(void); + +/* Defined in ps7_init_common.c */ +int ps7_config(unsigned long *ps7_config_init); diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c new file mode 100644 index 00000000000..b195d7a25bf --- /dev/null +++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c @@ -0,0 +1,227 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../ps7_init_gpl.h" + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/topic/zynq/zynq-topic-miami/ps7_regs.txt b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt new file mode 100644 index 00000000000..2ad9da69724 --- /dev/null +++ b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt @@ -0,0 +1,61 @@ +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) +0xf8000700 0x1210 // MIO configuration +0xf8000704 0x202 +0xf8000708 0x202 +0xf800070c 0x202 +0xf8000710 0x202 +0xf8000714 0x202 +0xf8000718 0x202 +0xf800071c 0x210 +0xf8000720 0x202 +0xf8000724 0x1210 +0xf8000728 0x1210 +0xf800072c 0x1210 +0xf8000730 0x1210 +0xf8000734 0x1210 +0xf8000738 0x1211 +0xf800073c 0x1200 +0xf8000740 0x1210 +0xf8000744 0x1210 +0xf8000748 0x1210 +0xf800074c 0x1210 +0xf8000750 0x1210 +0xf8000754 0x1210 +0xf8000758 0x1210 +0xf800075c 0x1210 +0xf8000760 0x1201 +0xf8000764 0x200 +0xf8000768 0x12e1 +0xf800076c 0x2e0 +0xf8000770 0x304 +0xf8000774 0x305 +0xf8000778 0x304 +0xf800077c 0x305 +0xf8000780 0x304 +0xf8000784 0x304 +0xf8000788 0x304 +0xf800078c 0x304 +0xf8000790 0x305 +0xf8000794 0x304 +0xf8000798 0x304 +0xf800079c 0x304 +0xf80007a0 0x380 +0xf80007a4 0x380 +0xf80007a8 0x380 +0xf80007ac 0x380 +0xf80007b0 0x380 +0xf80007b4 0x380 +0xf80007b8 0x1261 +0xf80007bc 0x1260 +0xf80007c0 0x1261 +0xf80007c4 0x1261 +0xf80007c8 0x1240 +0xf80007cc 0x1240 +0xf80007d0 0x1240 +0xf80007d4 0x1240 +0xf8000830 0x180037 +0xf8000834 0x3a0039 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) +0xE000D000 0x800238C1 // QSPI config - divide-by-2 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay +0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c new file mode 100644 index 00000000000..5a923366eb7 --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c @@ -0,0 +1,233 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../ps7_init_gpl.h" + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt new file mode 100644 index 00000000000..7b102de378b --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt @@ -0,0 +1,61 @@ +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz) +0xf8000700 0x1202 // MIO configuration +0xf8000704 0x1202 +0xf8000708 0x202 +0xf800070c 0x202 +0xf8000710 0x202 +0xf8000714 0x202 +0xf8000718 0x202 +0xf800071c 0x200 +0xf8000720 0x202 +0xf8000724 0x202 +0xf8000728 0x202 +0xf800072c 0x202 +0xf8000730 0x202 +0xf8000734 0x202 +0xf8000738 0x12e1 +0xf800073c 0x12e0 +0xf8000740 0x1202 +0xf8000744 0x1202 +0xf8000748 0x1202 +0xf800074c 0x1202 +0xf8000750 0x1202 +0xf8000754 0x1202 +0xf8000758 0x1203 +0xf800075c 0x1203 +0xf8000760 0x1203 +0xf8000764 0x203 +0xf8000768 0x1203 +0xf800076c 0x203 +0xf8000770 0x304 +0xf8000774 0x305 +0xf8000778 0x304 +0xf800077c 0x305 +0xf8000780 0x304 +0xf8000784 0x304 +0xf8000788 0x304 +0xf800078c 0x304 +0xf8000790 0x305 +0xf8000794 0x304 +0xf8000798 0x304 +0xf800079c 0x304 +0xf80007a0 0x380 +0xf80007a4 0x380 +0xf80007a8 0x380 +0xf80007ac 0x380 +0xf80007b0 0x380 +0xf80007b4 0x380 +0xf80007b8 0x1200 +0xf80007bc 0x1201 +0xf80007c0 0x1240 +0xf80007c4 0x1240 +0xf80007c8 0x1240 +0xf80007cc 0x1240 +0xf80007d0 0x1280 +0xf80007d4 0x1280 +0xf8000830 0x2f0037 +0xf8000834 0x3a0039 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 +0xE000D000 0x800238C1 // QSPI config - divide-by-2 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay +0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig new file mode 100644 index 00000000000..3d6161e9f9b --- /dev/null +++ b/configs/topic_miami_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="topic" +CONFIG_SYS_CONFIG_NAME="topic_miami" +CONFIG_ARCH_ZYNQ=y +CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" +CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" +CONFIG_BOOTDELAY=0 +CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="zynq-uboot> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_NETDEVICES is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig new file mode 100644 index 00000000000..3160f00ba61 --- /dev/null +++ b/configs/topic_miamiplus_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="topic" +CONFIG_SYS_CONFIG_NAME="topic_miamiplus" +CONFIG_ARCH_ZYNQ=y +CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" +CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" +CONFIG_BOOTDELAY=0 +CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="zynq-uboot> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_NETDEVICES is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h new file mode 100644 index 00000000000..3b0fa29890f --- /dev/null +++ b/include/configs/topic_miami.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2014 Topic Embedded Products + * + * Configuration for Zynq Evaluation and Development Board - Miami + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TOPIC_MIAMI_H +#define __CONFIG_TOPIC_MIAMI_H + +#define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL + +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 + +/* Speed up boot time by ignoring the environment which we never used */ +#define CONFIG_ENV_IS_NOWHERE + +#include "zynq-common.h" + +/* Fixup settings */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE 0x8000 +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET 0x80000 + +/* SPL settings */ +#undef CONFIG_SPL_ETH_SUPPORT +#undef CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#undef CONFIG_SPL_MAX_FOOTPRINT +#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +/* sspi command isn't useful */ +#undef CONFIG_CMD_SPI + +/* No useful gpio */ +#undef CONFIG_ZYNQ_GPIO +#undef CONFIG_CMD_GPIO + +/* No falcon support */ +#undef CONFIG_SPL_OS_BOOT +#undef CONFIG_SPL_FPGA_SUPPORT + +/* FPGA commands that we don't use */ +#undef CONFIG_CMD_FPGA_LOADMK +#undef CONFIG_CMD_FPGA_LOADP +#undef CONFIG_CMD_FPGA_LOADBP +#undef CONFIG_CMD_FPGA_LOADFS + +/* Extras */ +#define CONFIG_CMD_MEMTEST +#undef CONFIG_SYS_MEMTEST_START +#define CONFIG_SYS_MEMTEST_START 0 +#undef CONFIG_SYS_MEMTEST_END +#define CONFIG_SYS_MEMTEST_END 0x18000000 + +/* Faster flash, ours may run at 108 MHz */ +#undef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 108000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#undef CONFIG_SF_DUAL_FLASH +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#undef CONFIG_SPI_FLASH_WINBOND +#undef CONFIG_SPI_FLASH_ISSI + +/* Setup proper boot sequences for Miami boards */ + +#if defined(CONFIG_USB) +# define EXTRA_ENV_USB \ + "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\ + "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \ + "usbboot=run usbreset && if usb start; then " \ + "echo Booting from USB... && " \ + "if load usb 0 0x1900000 ${bootscript}; then "\ + "source 0x1900000; fi; " \ + "load usb 0 ${kernel_addr} ${kernel_image} && " \ + "load usb 0 ${devicetree_addr} ${devicetree_image} && " \ + "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \ + "bootm ${kernel_addr} ${ramdisk_load_address} "\ + "${devicetree_addr}; " \ + "fi\0" + /* Note that addresses here should match the addresses in the env */ +# undef DFU_ALT_INFO +# define DFU_ALT_INFO \ + "dfu_alt_info=" \ + "uImage ram 0x2080000 0x500000;" \ + "devicetree.dtb ram 0x2000000 0x20000;" \ + "uramdisk.image.gz ram 0x4000000 0x10000000\0" \ + "dfu_ram=run usbreset && dfu 0 ram 0\0" \ + "thor_ram=run usbreset && thordown 0 ram 0\0" +#else +# define EXTRA_ENV_USB +#endif + +#undef CONFIG_PREBOOT + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_image=uImage\0" \ + "kernel_addr=0x2080000\0" \ + "ramdisk_image=uramdisk.image.gz\0" \ + "ramdisk_load_address=0x4000000\0" \ + "devicetree_image=devicetree.dtb\0" \ + "devicetree_addr=0x2000000\0" \ + "bitstream_image=fpga.bin\0" \ + "bootscript=autorun.scr\0" \ + "loadbit_addr=0x100000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "kernel_size=0x400000\0" \ + "devicetree_size=0x10000\0" \ + "boot_size=0xF00000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ + "mmcinfo && " \ + "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ + "fpga load 0 ${loadbit_addr} ${filesize}\0" \ + "qspiboot=echo Booting from QSPI flash... && " \ + "sf probe && " \ + "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \ + "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \ + "bootm ${kernel_addr} - ${devicetree_addr}\0" \ + "sdboot=if mmcinfo; then " \ + "setenv bootargs console=ttyPS0,115200 " \ + "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \ + "rootwait quiet ; " \ + "load mmc 0 ${kernel_addr} ${kernel_image}&& " \ + "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \ + "bootm ${kernel_addr} - ${devicetree_addr}; " \ + "fi\0" \ + EXTRA_ENV_USB \ + DFU_ALT_INFO + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \ + "if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \ + "fi; fi; run $modeboot" +#undef CONFIG_DISPLAY_BOARDINFO + +/* Further tweaks to reduce image size */ +#undef CONFIG_CMD_BOOTZ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_AES + +#endif /* __CONFIG_TOPIC_MIAMI_H */ diff --git a/include/configs/topic_miamiplus.h b/include/configs/topic_miamiplus.h new file mode 100644 index 00000000000..46ca6bda045 --- /dev/null +++ b/include/configs/topic_miamiplus.h @@ -0,0 +1,2 @@ +#include "topic_miami.h" +#define CONFIG_SF_DUAL_FLASH -- cgit v1.3.1 From ba8adb26a0ad99097a0e222fb8c29c52e69d0162 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 27 Sep 2016 10:55:47 +0530 Subject: zynq: nand: Enable Nand flash controller driver a zynq board Enable zynq Nand flash controller driver for a zynq ZC770 XM011(dc2) board. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- configs/zynq_zc770_xm011_defconfig | 2 ++ include/configs/zynq-common.h | 7 +++++++ 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 56c28511545..2f4fc1e37db 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -13,6 +13,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y @@ -22,4 +23,5 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_NAND_ZYNQ=y CONFIG_ZYNQ_GEM=y diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 4f0253cd7d4..3a2080f9e54 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -76,6 +76,13 @@ # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif +#ifdef CONFIG_NAND_ZYNQ +#define CONFIG_CMD_NAND_LOCK_UNLOCK +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_MTD_DEVICE +#endif + /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC -- cgit v1.3.1 From 05c59d0bc83f28888e5f2cc11b679a721605a46b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Oct 2016 16:10:25 +0200 Subject: ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: Michal Simek --- board/xilinx/zynq/board.c | 12 ++++++++++++ include/zynqpl.h | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'include') diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 183f6427534..2c86940957e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -19,7 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static xilinx_desc fpga; /* It can be done differently */ +static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); +static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); @@ -37,9 +40,18 @@ int board_init(void) idcode = zynq_slcr_get_idcode(); switch (idcode) { + case XILINX_ZYNQ_7007S: + fpga = fpga007s; + break; case XILINX_ZYNQ_7010: fpga = fpga010; break; + case XILINX_ZYNQ_7012S: + fpga = fpga012s; + break; + case XILINX_ZYNQ_7014S: + fpga = fpga014s; + break; case XILINX_ZYNQ_7015: fpga = fpga015; break; diff --git a/include/zynqpl.h b/include/zynqpl.h index 1d37a51a04e..5a34a17daef 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -19,7 +19,10 @@ extern struct xilinx_fpga_op zynq_op; # define FPGA_ZYNQPL_OPS NULL #endif +#define XILINX_ZYNQ_7007S 0x3 #define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7012S 0x1c +#define XILINX_ZYNQ_7014S 0x8 #define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc @@ -28,7 +31,10 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_7100 0x16 /* Device Image Sizes */ +#define XILINX_XC7Z007S_SIZE 16669920/8 #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z012S_SIZE 28085344/8 +#define XILINX_XC7Z014S_SIZE 32364512/8 #define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 @@ -37,10 +43,22 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z100_SIZE 139330784/8 /* Descriptor Macros */ +#define XILINX_XC7Z007S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z007s" } + #define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z010" } +#define XILINX_XC7Z012S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z012s" } + +#define XILINX_XC7Z014S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z014s" } + #define XILINX_XC7Z015_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z015" } -- cgit v1.3.1 From 0cba6abbba5c0bd5c80e652c35d0bd74e644a49e Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 29 Sep 2016 11:44:41 -0700 Subject: ARM64: zynqmp: Adjust to new SMC interface to get silicon version The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 11 +++++++++++ include/zynqmppl.h | 6 ++++++ 2 files changed, 17 insertions(+) (limited to 'include') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ba4dfbb4762..b0acaa5b772 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -86,6 +86,17 @@ static int chip_id(void) smc_call(®s); + /* + * SMC returns: + * regs[0][31:0] = status of the operation + * regs[0][63:32] = CSU.IDCODE register + * regs[1][31:0] = CSU.version register + */ + regs.regs[0] = upper_32_bits(regs.regs[0]); + regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | + ZYNQMP_CSU_IDCODE_SVD_MASK; + regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; + return regs.regs[0]; } diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 542ace9a03b..fb5200ec84a 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -16,6 +16,12 @@ #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ + ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT) + extern struct xilinx_fpga_op zynqmp_op; #define XILINX_ZYNQMP_DESC \ -- cgit v1.3.1 From 913a6eeb55bd7c632ea4395662ff1ff55ad16751 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 1 Nov 2016 23:49:53 +0530 Subject: ARM64: zynqmp: Correct the sdhci minimum frequency for ep108 Correct the sdhci minimum frequency for ep platform. It should be right shift instead of left shift operand. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_ep.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 8e4b96033b8..d0ce768e6e1 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -14,7 +14,7 @@ #define __CONFIG_ZYNQMP_EP_H #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 -#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) +#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9) #define CONFIG_ZYNQ_EEPROM #define CONFIG_SATA_CEVA #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ -- cgit v1.3.1 From 97d014446cec3ba98c7f3efe16c423dbcf769379 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Thu, 17 Nov 2016 01:02:56 +0100 Subject: efi_loader: Fix efi_add_runtime_mmio definition The efi_add_runtime_mmio prototype for disabled CONFIG_EFI_LOADER was different from the enabled one. Sync them. Signed-off-by: Alexander Graf --- include/efi_loader.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 35b3fe2d398..99619f53a94 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -181,7 +181,7 @@ void efi_get_time_init(void); /* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */ #define __efi_runtime_data #define __efi_runtime -static inline void efi_add_runtime_mmio(void **mmio_ptr, u64 len) { } +static inline void efi_add_runtime_mmio(void *mmio_ptr, u64 len) { } /* No loader configured, stub out EFI_ENTRY */ static inline void efi_restore_gd(void) { } -- cgit v1.3.1 From b99ebaf9f01ebe864061818e00beb70cb1ddc635 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Thu, 17 Nov 2016 01:03:02 +0100 Subject: ls2080ardb: Convert to distro boot Most new systems in U-Boot these days make use of the generic "distro" framework which allows a user to have U-Boot scan for a bootable OS on all available media types. This patch extends the LS2080ARDB board to use that framework if the hard coded NOR flash location does not contain a bootable image. Signed-off-by: Alexander Graf --- Kconfig | 1 + include/configs/ls2080ardb.h | 26 +++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index 1263d0b612d..f3a9f73dd0f 100644 --- a/Kconfig +++ b/Kconfig @@ -56,6 +56,7 @@ config CC_OPTIMIZE_FOR_SIZE config DISTRO_DEFAULTS bool "Select defaults suitable for booting general purpose Linux distributions" default y if ARCH_SUNXI + default y if ARCH_LS2080A default n select CMD_BOOTZ if ARM && !ARM64 select CMD_BOOTI if ARM64 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b9cb6d38795..32fa0eb3ee3 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -316,10 +316,25 @@ unsigned long get_board_sys_clk(void); #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#undef CONFIG_CMDLINE_EDITING +#include + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ "ramdisk_addr=0x800000\0" \ @@ -329,8 +344,10 @@ unsigned long get_board_sys_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "fdtfile=fsl-ls2080a-rdb.dtb\0" \ "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" + " 0x580800000 \0" \ + BOOTENV #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ @@ -338,6 +355,13 @@ unsigned long get_board_sys_clk(void); "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" +#undef CONFIG_BOOTCOMMAND +/* Try to boot an on-NOR kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \ + " && cp.b $kernel_start $kernel_load $kernel_size" \ + " && bootm $kernel_load" \ + " || run distro_bootcmd" + /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_PHYLIB_10G -- cgit v1.3.1 From f790ca7c7dfd6b96d418a29d4a8654cdfebbdfc3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 30 Oct 2016 23:16:10 +0530 Subject: sf: Adopt flash table INFO macro from Linux INFO macro make flash table entries more adjustable like adding new flash_info attributes, update ID length bytes and so on and more over it will sync to Linux way of defining flash_info attributes. - Add JEDEC_ID - Add JEDEC_EXT macro - Add JEDEC_MFR - spi_flash_params => spi_flash_info - params => info Cc: Simon Glass Cc: Bin Meng Cc: York Sun Cc: Vignesh R Cc: Mugunthan V N Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Reviewed-by: Jagan Teki Tested-by: Jagan Teki Signed-off-by: Jagan Teki --- drivers/mtd/spi/sandbox.c | 10 +- drivers/mtd/spi/sf_internal.h | 26 +++-- drivers/mtd/spi/sf_params.c | 217 ++++++++++++++++++++++-------------------- drivers/mtd/spi/spi_flash.c | 136 +++++++++++++------------- include/linux/err.h | 5 + 5 files changed, 214 insertions(+), 180 deletions(-) (limited to 'include') diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index f59134ff926..d68ee4a293b 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -88,7 +88,7 @@ struct sandbox_spi_flash { /* The current flash status (see STAT_XXX defines above) */ u16 status; /* Data describing the flash we're emulating */ - const struct spi_flash_params *data; + const struct spi_flash_info *data; /* The file on disk to serv up data from */ int fd; }; @@ -112,7 +112,7 @@ static int sandbox_sf_probe(struct udevice *dev) struct sandbox_spi_flash *sbsf = dev_get_priv(dev); const char *file; size_t len, idname_len; - const struct spi_flash_params *data; + const struct spi_flash_info *data; struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev); struct sandbox_state *state = state_get_current(); struct udevice *bus = dev->parent; @@ -168,7 +168,7 @@ static int sandbox_sf_probe(struct udevice *dev) } debug("%s: device='%s'\n", __func__, spec); - for (data = spi_flash_params_table; data->name; data++) { + for (data = spi_flash_ids; data->name; data++) { len = strlen(data->name); if (idname_len != len) continue; @@ -359,7 +359,9 @@ static int sandbox_sf_xfer(struct udevice *dev, unsigned int bitlen, debug(" id: off:%u tx:", sbsf->off); if (sbsf->off < IDCODE_LEN) { /* Extract correct byte from ID 0x00aabbcc */ - id = sbsf->data->jedec >> + id = ((((sbsf->data)->id[0]) << 16) | + (((sbsf->data)->id[1]) << 8 | + ((sbsf->data)->id[2]))) >> (8 * (IDCODE_LEN - 1 - sbsf->off)); } else { id = 0; diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index cde4cfbf2e3..a9455ac8952 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -103,24 +103,36 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, #define CMD_SPANSION_RDAR 0x65 /* Read any device register */ #define CMD_SPANSION_WRAR 0x71 /* Write any device register */ #endif + +#define JEDEC_MFR(info) ((info)->id[0]) +#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2])) +#define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4])) + /** - * struct spi_flash_params - SPI/QSPI flash device params structure + * struct spi_flash_info - SPI/QSPI flash device params structure * * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) - * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) - * @ext_jedec: Device ext_jedec ID * @sector_size: Isn't necessarily a sector size from vendor, * the size listed here is what works with CMD_ERASE_64K * @nr_sectors: No.of sectors on this device * @flags: Important param, for flash specific behaviour */ -struct spi_flash_params { +struct spi_flash_info { const char *name; - u32 jedec; - u16 ext_jedec; + + /* + * This array stores the ID bytes. + * The first three bytes are the JEDIC ID. + * JEDEC ID zero means "no ID" (mostly older chips). + */ + u8 id[5]; + u8 id_len; + u32 sector_size; u32 nr_sectors; + u16 page_size; + u16 flags; #define SECT_4K BIT(0) #define E_FSR BIT(1) @@ -133,7 +145,7 @@ struct spi_flash_params { #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) }; -extern const struct spi_flash_params spi_flash_params_table[]; +extern const struct spi_flash_info spi_flash_ids[]; /* Send a single-byte command to the device and read the response */ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5b50114dda1..7fcc3bc3dec 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -12,125 +12,140 @@ #include "sf_internal.h" +/* Used when the "_ext_id" is two bytes at most */ +#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .id = { \ + ((_jedec_id) >> 16) & 0xff, \ + ((_jedec_id) >> 8) & 0xff, \ + (_jedec_id) & 0xff, \ + ((_ext_id) >> 8) & 0xff, \ + (_ext_id) & 0xff, \ + }, \ + .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ + .sector_size = (_sector_size), \ + .nr_sectors = (_n_sectors), \ + .page_size = 256, \ + .flags = (_flags), + /* SPI/QSPI flash device params structure */ -const struct spi_flash_params spi_flash_params_table[] = { +const struct spi_flash_info spi_flash_ids[] = { #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K}, - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K}, - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K}, - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K}, - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K}, - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K}, - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K}, - {"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K}, - {"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, SECT_4K}, - {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, SECT_4K}, + {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, + {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, + {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, + {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, + {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, + {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, + {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, + {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, + {"AT25DF321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, + {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0}, - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0}, - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0}, + {"EN25Q32B", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, + {"EN25Q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"EN25Q128B", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, + {"EN25S64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K}, - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K}, + {"GD25Q64B", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"GD25LQ32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ - {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, 0}, - {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, 0}, - {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, 0}, + {"IS25LP032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, + {"IS25LP064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, + {"IS25LP128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0}, - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0}, - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0}, - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0}, - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0}, - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0}, - {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP}, - {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP}, - {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP}, - {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP}, + {"MX25L2006E", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, + {"MX25L4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, + {"MX25L8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, + {"MX25L1605D", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, + {"MX25L3205D", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, + {"MX25L6405D", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, + {"MX25L12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"MX25L25635F", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {"MX25L51235F", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {"MX25L12855E", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0}, - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0}, - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0}, - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0}, - {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, 0}, - {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, 0}, - {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP}, - {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP}, - {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP}, - {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP}, - {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP}, - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP}, - {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP}, - {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP}, - {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP}, - {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP}, - {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP}, - {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP}, + {"S25FL008A", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, + {"S25FL016A", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, + {"S25FL032A", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, + {"S25FL064A", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, + {"S25FL116K", INFO(0x014015, 0x0, 64 * 1024, 128, 0) }, + {"S25FL164K", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, + {"S25FL128P_256K", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {"S25FL128P_64K", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"S25FL032P", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, + {"S25FL064P", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {"S25FL128S_64K", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, + {"S25FL256S_64K", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {"S25FS512S", INFO(0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP) }, + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + {"S25FL512S_64K", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {"S25FL512S_512K", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0}, - {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0}, - {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0}, - {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, SECT_4K}, - {"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, SECT_4K}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K}, + {"M25P10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, + {"M25P20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, + {"M25P40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, + {"M25P80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, + {"M25P16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, + {"M25PE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, + {"M25PX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, + {"M25P32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, + {"M25P64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, + {"M25P128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, + {"M25PX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, + {"N25Q016A", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, + {"N25Q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q32A", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q64A", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"N25Q128A", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"N25Q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q256A", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"N25Q512A", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"N25Q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"N25Q1024A", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR}, - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR}, - {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, SECT_4K}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR}, + {"SST25VF040B", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {"SST25VF080B", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + {"SST25VF016B", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, + {"SST25VF032B", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, + {"SST25VF064C", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, + {"SST25WF512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, + {"SST25WF010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, + {"SST25WF020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, + {"SST25WF040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {"SST25WF040B", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, + {"SST25WF080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, #endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0}, - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0}, - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0}, - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K}, - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K}, - {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K}, + {"W25P80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, + {"W25P16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, + {"W25P32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, + {"W25X40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, + {"W25X16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, + {"W25X32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, + {"W25X64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"W25Q80BL", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q16CL", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q32BV", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q64CV", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q128BV", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q80BW", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q16DW", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q32DW", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q64DW", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q128FW", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, #endif {}, /* Empty entry to terminate the list */ /* diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 7f6e9ae23ea..95ee5ac6283 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -165,7 +165,8 @@ bar_end: return flash->bank_curr; } -static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) +static int spi_flash_read_bar(struct spi_flash *flash, + const struct spi_flash_info *info) { u8 curr_bank = 0; int ret; @@ -173,7 +174,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) if (flash->size <= SPI_FLASH_16MB_BOUN) goto bar_end; - switch (idcode0) { + switch (JEDEC_MFR(info)) { case SPI_FLASH_CFI_MFR_SPANSION: flash->bank_read_cmd = CMD_BANKADDR_BRRD; flash->bank_write_cmd = CMD_BANKADDR_BRWR; @@ -924,9 +925,35 @@ static int micron_quad_enable(struct spi_flash *flash) } #endif -static int set_quad_mode(struct spi_flash *flash, u8 idcode0) +static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) { - switch (idcode0) { + int tmp; + u8 id[5]; + const struct spi_flash_info *info; + + tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, 5); + if (tmp < 0) { + printf("SF: error %d reading JEDEC ID\n", tmp); + return ERR_PTR(tmp); + } + + info = spi_flash_ids; + for (; info->name != NULL; info++) { + if (info->id_len) { + if (!memcmp(info->id, id, info->id_len)) + return info; + } + } + + printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n", + id[0], id[1], id[2]); + return ERR_PTR(-ENODEV); +} + +static int set_quad_mode(struct spi_flash *flash, + const struct spi_flash_info *info) +{ + switch (JEDEC_MFR(info)) { #ifdef CONFIG_SPI_FLASH_MACRONIX case SPI_FLASH_CFI_MFR_MACRONIX: return macronix_quad_enable(flash); @@ -941,7 +968,8 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) return micron_quad_enable(flash); #endif default: - printf("SF: Need set QEB func for %02x flash\n", idcode0); + printf("SF: Need set QEB func for %02x flash\n", + JEDEC_MFR(info)); return -1; } } @@ -1011,45 +1039,12 @@ static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi) int spi_flash_scan(struct spi_flash *flash) { struct spi_slave *spi = flash->spi; - const struct spi_flash_params *params; - u16 jedec, ext_jedec; - u8 idcode[5]; - int ret; - - /* Read the ID codes */ - ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); - if (ret) { - printf("SF: Failed to get idcodes\n"); - return ret; - } - -#ifdef DEBUG - printf("SF: Got idcodes\n"); - print_buffer(0, idcode, 1, sizeof(idcode), 0); -#endif - - jedec = idcode[1] << 8 | idcode[2]; - ext_jedec = idcode[3] << 8 | idcode[4]; - - /* Validate params from spi_flash_params table */ - params = spi_flash_params_table; - for (; params->name != NULL; params++) { - if ((params->jedec >> 16) == idcode[0]) { - if ((params->jedec & 0xFFFF) == jedec) { - if (params->ext_jedec == 0) - break; - else if (params->ext_jedec == ext_jedec) - break; - } - } - } + const struct spi_flash_info *info = NULL; + int ret = -1; - if (!params->name) { - printf("SF: Unsupported flash IDs: "); - printf("manuf %02x, jedec %04x, ext_jedec %04x\n", - idcode[0], jedec, ext_jedec); - return -EPROTONOSUPPORT; - } + info = spi_flash_read_id(flash); + if (IS_ERR_OR_NULL(info)) + return -ENOENT; #ifdef CONFIG_SPI_FLASH_SPANSION /* @@ -1065,11 +1060,17 @@ int spi_flash_scan(struct spi_flash *flash) * sector that is not overlaid by the parameter sectors. * The uniform sector erase command has no effect on parameter sectors. */ - if ((jedec == 0x0219 || (jedec == 0x0220)) && - (ext_jedec & 0xff00) == 0x4d00) { + if ((JEDEC_ID(info) == 0x0219 || (JEDEC_ID(info) == 0x0220)) && + (JEDEC_EXT(info) & 0xff00) == 0x4d00) { int ret; + u8 idcode[5]; u8 id[6]; + /* Read the ID codes again, 5 bytes */ + ret = spi_flash_cmd(flash->spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) + return -EIO; + /* Read the ID codes again, 6 bytes */ ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id)); if (ret) @@ -1088,18 +1089,18 @@ int spi_flash_scan(struct spi_flash *flash) } #endif /* Flash powers up read-only, so clear BP# bits */ - if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL || - idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX || - idcode[0] == SPI_FLASH_CFI_MFR_SST) + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || + JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || + JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) write_sr(flash, 0); /* Assign spi data */ - flash->name = params->name; + flash->name = info->name; flash->memory_map = spi->memory_map; flash->dual_flash = spi->option; /* Assign spi flash flags */ - if (params->flags & SST_WR) + if (info->flags & SST_WR) flash->flags |= SNOR_F_SST_WR; /* Assign spi_flash ops */ @@ -1118,7 +1119,7 @@ int spi_flash_scan(struct spi_flash *flash) #endif /* lock hooks are flash specific - assign them based on idcode0 */ - switch (idcode[0]) { + switch (JEDEC_MFR(info)) { #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) case SPI_FLASH_CFI_MFR_STMICRO: case SPI_FLASH_CFI_MFR_SST: @@ -1128,28 +1129,26 @@ int spi_flash_scan(struct spi_flash *flash) #endif break; default: - debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); + debug("SF: Lock ops not supported for %02x flash\n", JEDEC_MFR(info)); } /* Compute the flash size */ flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; + flash->page_size = info->page_size; /* * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with * the 0x4d00 Extended JEDEC code have 512b pages. All of the others * have 256b pages. */ - if (ext_jedec == 0x4d00) { - if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220)) - flash->page_size = 256; - else + if (JEDEC_EXT(info) == 0x4d00) { + if ((JEDEC_ID(info) != 0x0215) && + (JEDEC_ID(info) != 0x0216)) flash->page_size = 512; - } else { - flash->page_size = 256; } flash->page_size <<= flash->shift; - flash->sector_size = params->sector_size << flash->shift; - flash->size = flash->sector_size * params->nr_sectors << flash->shift; + flash->sector_size = info->sector_size << flash->shift; + flash->size = flash->sector_size * info->nr_sectors << flash->shift; #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash & SF_DUAL_STACKED_FLASH) flash->size <<= 1; @@ -1157,7 +1156,7 @@ int spi_flash_scan(struct spi_flash *flash) #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS /* Compute erase sector and command */ - if (params->flags & SECT_4K) { + if (info->flags & SECT_4K) { flash->erase_cmd = CMD_ERASE_4K; flash->erase_size = 4096 << flash->shift; } else @@ -1174,13 +1173,13 @@ int spi_flash_scan(struct spi_flash *flash) flash->read_cmd = CMD_READ_ARRAY_FAST; if (spi->mode & SPI_RX_SLOW) flash->read_cmd = CMD_READ_ARRAY_SLOW; - else if (spi->mode & SPI_RX_QUAD && params->flags & RD_QUAD) + else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD) flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; - else if (spi->mode & SPI_RX_DUAL && params->flags & RD_DUAL) + else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL) flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; /* Look for write commands */ - if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) + if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD) flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; else /* Go for default supported write cmd */ @@ -1190,9 +1189,10 @@ int spi_flash_scan(struct spi_flash *flash) if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { - ret = set_quad_mode(flash, idcode[0]); + ret = set_quad_mode(flash, info); if (ret) { - debug("SF: Fail to set QEB for %02x\n", idcode[0]); + debug("SF: Fail to set QEB for %02x\n", + JEDEC_MFR(info)); return -EINVAL; } } @@ -1217,13 +1217,13 @@ int spi_flash_scan(struct spi_flash *flash) } #ifdef CONFIG_SPI_FLASH_STMICRO - if (params->flags & E_FSR) + if (info->flags & E_FSR) flash->flags |= SNOR_F_USE_FSR; #endif /* Configure the BAR - discover bank cmds and read current bank */ #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_read_bar(flash, idcode[0]); + ret = spi_flash_read_bar(flash, info); if (ret < 0) return ret; #endif diff --git a/include/linux/err.h b/include/linux/err.h index e4d22d508c8..22e5756eddc 100644 --- a/include/linux/err.h +++ b/include/linux/err.h @@ -36,6 +36,11 @@ static inline long IS_ERR(const void *ptr) return IS_ERR_VALUE((unsigned long)ptr); } +static inline bool IS_ERR_OR_NULL(const void *ptr) +{ + return !ptr || IS_ERR_VALUE((unsigned long)ptr); +} + /** * ERR_CAST - Explicitly cast an error-valued pointer to another pointer type * @ptr: The pointer to cast. -- cgit v1.3.1 From 38fed8abe7d2e7ba90deb352d0e7aed4364c5236 Mon Sep 17 00:00:00 2001 From: Semen Protsenko Date: Wed, 16 Nov 2016 19:19:05 +0200 Subject: spl: Convert CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to Kconfig Signed-off-by: Sam Protsenko [trini: Fix sniper and kc1 migration] Signed-off-by: Tom Rini --- README | 5 ++-- common/spl/Kconfig | 27 ++++++++++++++++++++++ common/spl/spl_mmc.c | 4 ++-- configs/brppt1_mmc_defconfig | 2 ++ configs/brppt1_nand_defconfig | 2 ++ configs/brppt1_spi_defconfig | 2 ++ configs/brxre1_defconfig | 2 ++ configs/clearfog_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/cm_t43_defconfig | 2 ++ configs/cm_t54_defconfig | 1 + configs/draco_defconfig | 2 ++ configs/etamin_defconfig | 2 ++ configs/kc1_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 2 ++ configs/ls1021aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1021aqds_sdcard_qspi_defconfig | 2 ++ .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig | 2 ++ configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043ardb_nand_defconfig | 2 ++ configs/ls1043ardb_sdcard_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig | 2 ++ configs/ls1046aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1046ardb_emmc_defconfig | 2 ++ configs/ls1046ardb_sdcard_defconfig | 2 ++ configs/pxm2_defconfig | 2 ++ configs/rastaban_defconfig | 2 ++ configs/rut_defconfig | 2 ++ configs/sniper_defconfig | 1 + configs/thuban_defconfig | 2 ++ configs/ti814x_evm_defconfig | 2 ++ configs/ti816x_evm_defconfig | 2 ++ configs/woodburn_sd_defconfig | 2 ++ include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/brppt1.h | 1 - include/configs/brxre1.h | 1 - include/configs/clearfog.h | 2 -- include/configs/cm_fx6.h | 2 -- include/configs/cm_t35.h | 1 - include/configs/cm_t43.h | 2 -- include/configs/cm_t54.h | 2 -- include/configs/da850evm.h | 1 - include/configs/db-88f6820-gp.h | 1 - include/configs/imx6_spl.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/mcx.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/picosam9g45.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/siemens-am33x-common.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/tam3517-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 1 - include/configs/ti_armv7_common.h | 1 - include/configs/tricorder.h | 1 - include/configs/uniphier.h | 1 - include/configs/woodburn_sd.h | 1 - include/configs/zynq-common.h | 1 - scripts/config_whitelist.txt | 1 - 80 files changed, 96 insertions(+), 51 deletions(-) (limited to 'include') diff --git a/README b/README index 00830d76df9..cbf42e73d5a 100644 --- a/README +++ b/README @@ -3338,9 +3338,8 @@ FIT uImage format: CONFIG_SPL_INIT_MINIMAL Arch init code should be built for a very small image - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, - CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS, - Address and partition on the MMC to load U-Boot from + CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS + Size of partition on the MMC to load U-Boot from when the MMC is being used in raw mode. CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION diff --git a/common/spl/Kconfig b/common/spl/Kconfig index bb99f1fcff4..df9e0ce68f9 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -70,6 +70,33 @@ config SPL_DISPLAY_PRINT banner ("U-Boot SPL ..."). This function should be provided by the board. +config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + bool "MMC raw mode: by sector" + depends on SPL + default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_MX6 || \ + ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ + ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ + OMAP44XX || OMAP54XX || AM33XX || AM43XX + help + Use sector number for specifying U-Boot location on MMC/SD in + raw mode. + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + hex "Address on the MMC to load U-Boot from" + depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + default 0x50 if ARCH_SUNXI + default 0x75 if ARCH_DAVINCI + default 0x80 if ARCH_UNIPHIER + default 0x8a if ARCH_MX6 + default 0x100 if ARCH_ROCKCHIP + default 0x140 if ARCH_MVEBU + default 0x200 if ARCH_SOCFPGA || ARCH_AT91 + default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \ + OMAP54XX || AM33XX || AM43XX + help + Address on the MMC to load U-Boot from, when the MMC is being used + in raw mode. Units: MMC sectors (1 sector = 512 bytes). + config TPL bool depends on SPL && SUPPORT_TPL diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index c674e61cbde..0b681c23de9 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -165,7 +165,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, return -1; } -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR return mmc_load_image_raw_sector(spl_image, mmc, info.start + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #else @@ -327,7 +327,7 @@ static int spl_mmc_load_image(struct spl_image_info *spl_image, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION); if (!err) return err; -#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR err = mmc_load_image_raw_sector(spl_image, mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); if (!err) diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 78f3093c92c..41eac1828cf 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -20,6 +20,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 8e5325ecb60..f8d5539ad40 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -20,6 +20,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 9a5ed65514f..17b9cb1e800 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -23,6 +23,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 16415334ca6..7c0cf965cd2 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -18,6 +18,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 0891b917b0b..d06b75c027c 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 9c3a6ec6993..dc7544a17f1 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -15,6 +15,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" CONFIG_BOOTDELAY=3 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-FX6 # " CONFIG_CMD_BOOTZ=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index d359fabf684..2d7884119d6 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -16,6 +16,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_MTD_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T43 # " diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index c30ee0be6db..e002e1c8511 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_SATA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T54 # " diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 5212facc534..0cb44129931 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -19,6 +19,8 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 4e5baac33c9..8fb6ebd7bf0 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -19,6 +19,8 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig index b73a2de1b6f..c2d5d47692b 100644 --- a/configs/kc1_defconfig +++ b/configs/kc1_defconfig @@ -31,3 +31,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 2bdc7239432..e28aa487b98 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -21,6 +21,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 402cce77a74..beed9ac6bd8 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -20,6 +20,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 6f3588ebbbd..d6b08de2a26 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -20,6 +20,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 8178e8a0a24..ae0d8143d94 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -19,6 +19,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_CRYPTO_SUPPORT=y CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index eef1c1c9bdd..22be22ce573 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -19,6 +19,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 3f6fb17945f..80329fcf75f 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -20,6 +20,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index dbdb416f544..de0780157c5 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 24220edccc8..48ea853b9a2 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index fdcbf8a612e..fd0922da032 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index b21f47e13b8..da699860100 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 12ac6482628..c0b0a9253e4 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 01140b9c56b..74fcd4ae723 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -8,6 +8,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index e6eeadd6e98..fe9ad0efcaa 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -8,6 +8,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 8a148625351..17000820a45 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -8,6 +8,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index ba28047c299..fd21959becd 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -8,6 +8,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4,EMMC_BOOT" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 01e63979ee2..0b810d3bc4b 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -8,6 +8,8 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index b73e42687e2..650d23d7a0b 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index ab65c145bd5..d3ac645ad6a 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -19,6 +19,8 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index ff3c57190b7..4c99c13c825 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 02b51c46d50..d529a69d6a4 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -32,3 +32,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index a9d3e7ed600..7e1b63bc807 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -19,6 +19,8 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index 9d1df816b2b..029791718e9 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -14,6 +14,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " # CONFIG_CMD_IMLS is not set diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index e3a9f03e135..7d3a7d6634c 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot/ti816x# " # CONFIG_CMD_IMLS is not set diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index 01aae3b06bd..085c2dff6f6 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -10,6 +10,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="woodburn U-Boot > " CONFIG_CMD_MMC=y diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 6d271100c73..943ab3a6733 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -275,7 +275,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index cc89a160db4..deb1babf469 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -335,7 +335,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 5e37e2a8423..cb066ac57ca 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -194,7 +194,6 @@ #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 7fddf4f5daa..faa232c1c81 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -238,7 +238,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index db9bdefa091..efdf88db0c2 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -237,7 +237,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 0e138648d52..724343ea1d2 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -53,7 +53,6 @@ #define CONFIG_OMAP_HSMMC #define CONFIG_SUPPORT_EMMC_BOOT /* RAW SD card / eMMC locations. */ - #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #endif /* CONFIG_EMMC_BOOT */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index b9f69be27d3..d3ce692d522 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -48,7 +48,6 @@ #define CONFIG_OMAP_HSMMC #define CONFIG_SUPPORT_EMMC_BOOT /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ /* Always 64 KiB env size */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index a8cda40f684..bf123bb628b 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -131,8 +131,6 @@ /* SPL related MMC defines */ #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\ - + 1) #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ #ifdef CONFIG_SPL_BUILD #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 0ac3ec7da4c..c47d1fb768d 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -245,8 +245,6 @@ /* SPL */ #include "imx6_spl.h" -#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #define CONFIG_SPL_SPI_LOAD diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 6caac1dfcac..66727758994 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -292,7 +292,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 3a605f7504b..5ec4926dd8e 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -91,7 +91,6 @@ #include #undef CONFIG_SYS_MONITOR_LEN -#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -152,7 +151,6 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x480 #define CONFIG_SPL_SPI_LOAD /* EEPROM */ diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index a3b1e5fe8b8..abca5be75bb 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -31,10 +31,8 @@ #define CONFIG_BAUDRATE 115200 /* SD/MMC RAW boot */ -#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR #undef CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* 0x40000 - 256 KB */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */ /* MMC ENV related defines */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 2403ca3148a..35601159dde 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -346,7 +346,6 @@ /* Load U-Boot Image From MMC */ #ifdef CONFIG_SPL_MMC_LOAD -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75 #undef CONFIG_SPL_SPI_LOAD #endif diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 72c38e2407f..70c5e6ac264 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -133,7 +133,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ #ifdef CONFIG_SPL_BUILD #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 76d1ca088d6..be31d1a0bf9 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -37,7 +37,6 @@ /* MMC support */ #if defined(CONFIG_SPL_MMC_SUPPORT) -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 53f03688141..fdef29b31c8 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -61,7 +61,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 #define CONFIG_SPL_TEXT_BASE 0x10000000 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 4a579b1adbe..3cc97cd8016 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -106,7 +106,6 @@ #endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 #ifdef CONFIG_SECURE_BOOT #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 64682b18756..06c29740a44 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -52,7 +52,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 #define CONFIG_SPL_TEXT_BASE 0x10000000 diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index c4bbd5600d3..df482e2fcbc 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -61,7 +61,6 @@ #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x110 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index b9a2ad35212..7db9e5a1dd6 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -328,7 +328,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index b2a84125b6b..16f897dc009 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -52,7 +52,6 @@ #define CONFIG_OMAP_HSMMC /* SPL */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 64db0dac37b..36fe94dbc6b 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -171,7 +171,6 @@ #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 0868612c136..5358372587b 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -50,7 +50,6 @@ #define CONFIG_CMD_PART /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) /* FAT sd card locations. */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index d75feadab7c..aa646c6f52d 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -41,7 +41,6 @@ #define CONFIG_CMD_PART /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) /* FAT sd card locations. */ diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index f6946453e5d..55ec9175148 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -112,7 +112,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 5e6617410c4..c72fc5303fb 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -129,7 +129,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 1b053a6362c..f9ca9149d6c 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -168,7 +168,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 249e661d8b7..0ae858d4968 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -128,7 +128,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 00ed4009faa..5588a1822b1 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -126,7 +126,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 7de3cf6d9ae..31fcc947dde 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -129,7 +129,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_FS_FAT diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d37e5958b58..58a65508449 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -320,7 +320,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #else #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */ #endif #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 8363414828f..2e02f8cd185 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -199,7 +199,6 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" #endif -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ #if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 1527d90afd7..098c9bcc6c2 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -210,7 +210,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9e85b1da023..6a169b0f0d3 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -276,7 +276,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index e7f4fba132d..5cfed0d6196 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -161,7 +161,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 390c5aee26e..0a459fb5c56 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -125,7 +125,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 0d74c50bffa..03496c7b35b 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -236,7 +236,6 @@ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ /* FAT sd card locations. */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 6cd3ca5328c..fbef1f0e410 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -318,7 +318,6 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5be46e5c5a2..f9c9f821bfa 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -280,7 +280,6 @@ /* subtract sizeof(struct image_header) */ #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h index 5a04b99400a..4c509dfca88 100644 --- a/include/configs/woodburn_sd.h +++ b/include/configs/woodburn_sd.h @@ -23,7 +23,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x100 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */ #define CONFIG_SPL_TEXT_BASE 0x10002300 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 3a2080f9e54..f305598fde5 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -303,7 +303,6 @@ /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d476367088c..f511e29715e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -6482,7 +6482,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMC_BASE CONFIG_SYS_MMC_CD_PIN CONFIG_SYS_MMC_CLK_OD -- cgit v1.3.1 From 693d4c9f1dc40fcf24ced459bc4d1b46db33298a Mon Sep 17 00:00:00 2001 From: Semen Protsenko Date: Wed, 16 Nov 2016 19:19:06 +0200 Subject: spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS This option isn't used for anything, so get rid of it. Signed-off-by: Sam Protsenko --- README | 4 ---- include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/brppt1.h | 2 -- include/configs/brxre1.h | 2 -- include/configs/clearfog.h | 1 - include/configs/cm_fx6.h | 1 - include/configs/cm_t35.h | 1 - include/configs/cm_t54.h | 5 ----- include/configs/db-88f6820-gp.h | 1 - include/configs/draco.h | 2 -- include/configs/etamin.h | 2 -- include/configs/imx6_spl.h | 3 +-- include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 6 +----- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/picosam9g45.h | 1 - include/configs/pxm2.h | 2 -- include/configs/rastaban.h | 2 -- include/configs/rut.h | 2 -- include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/tao3530.h | 1 - include/configs/thuban.h | 2 -- include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 1 - include/configs/ti_armv7_common.h | 3 --- include/configs/woodburn_sd.h | 1 - include/configs/zynq-common.h | 1 - scripts/config_whitelist.txt | 1 - 38 files changed, 2 insertions(+), 60 deletions(-) (limited to 'include') diff --git a/README b/README index cbf42e73d5a..47bc215fe9c 100644 --- a/README +++ b/README @@ -3338,10 +3338,6 @@ FIT uImage format: CONFIG_SPL_INIT_MINIMAL Arch init code should be built for a very small image - CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS - Size of partition on the MMC to load U-Boot from - when the MMC is being used in raw mode. - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION Partition on the MMC to load U-Boot from when the MMC is being used in raw mode diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 943ab3a6733..2f20e10eff9 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -275,7 +275,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index deb1babf469..a4ae5453b2f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -335,7 +335,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index cb066ac57ca..fd0504d40b5 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -193,7 +193,6 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index faa232c1c81..b825464f704 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -237,7 +237,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index efdf88db0c2..843f03a1ea7 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -236,7 +236,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 724343ea1d2..a5fdbbba3a9 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -52,8 +52,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_SUPPORT_EMMC_BOOT -/* RAW SD card / eMMC locations. */ - #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #endif /* CONFIG_EMMC_BOOT */ /* diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index d3ce692d522..a6369d63b8e 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -47,8 +47,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_SUPPORT_EMMC_BOOT -/* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ /* Always 64 KiB env size */ #define CONFIG_ENV_SIZE (64 << 10) diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index bf123bb628b..c976ec867c5 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -131,7 +131,6 @@ /* SPL related MMC defines */ #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ #ifdef CONFIG_SPL_BUILD #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #endif diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index c47d1fb768d..0dad9c3bd75 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -240,7 +240,6 @@ /* misc */ #define CONFIG_STACKSIZE (128 * 1024) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #define CONFIG_MISC_INIT_R /* SPL */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 66727758994..201711d987f 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -292,7 +292,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index abca5be75bb..952538d5a14 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -30,11 +30,6 @@ #define CONFIG_SYS_NS16550_COM4 UART4_BASE #define CONFIG_BAUDRATE 115200 -/* SD/MMC RAW boot */ -#undef CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS - -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */ - /* MMC ENV related defines */ #undef CONFIG_ENV_OFFSET #undef CONFIG_ENV_SIZE diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 70c5e6ac264..b8c52321789 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -133,7 +133,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ #ifdef CONFIG_SPL_BUILD #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #endif diff --git a/include/configs/draco.h b/include/configs/draco.h index 5e4bf484131..7c4179d23f9 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -45,8 +45,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 - #undef CONFIG_MII #undef CONFIG_PHY_GIGE #define CONFIG_PHY_SMSC diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 9e5ee91c890..eb17d68d880 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -103,8 +103,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 - #undef CONFIG_MII #undef CONFIG_PHY_GIGE #define CONFIG_PHY_SMSC diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index be31d1a0bf9..0662053f859 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -37,9 +37,8 @@ /* MMC support */ #if defined(CONFIG_SPL_MMC_SUPPORT) -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) +#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index fdef29b31c8..128da8a3528 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -61,7 +61,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3cc97cd8016..145833287e5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -108,15 +108,11 @@ #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along * with U-Boot image. */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ - (CONFIG_U_BOOT_HDR_SIZE / 512) -#else -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_SECURE_BOOT */ #define CONFIG_SPL_TEXT_BASE 0x10000000 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 06c29740a44..7a407aa70a2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -52,7 +52,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1d000 diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index df482e2fcbc..3887faa97b0 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -61,7 +61,6 @@ #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ #define CONFIG_SPL_STACK 0x10020000 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 16f897dc009..f4f4e4917a5 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -52,7 +52,6 @@ #define CONFIG_OMAP_HSMMC /* SPL */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 36fe94dbc6b..9051c1cefcc 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -170,7 +170,6 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 2aa184a2c2d..d797a2ce4d7 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -40,8 +40,6 @@ #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 - #define CONFIG_PHY_ATHEROS #define CONFIG_FACTORYSET diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 5adad665566..d6fead27db3 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -48,8 +48,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 - #undef CONFIG_MII #undef CONFIG_PHY_GIGE #define CONFIG_PHY_SMSC diff --git a/include/configs/rut.h b/include/configs/rut.h index 3d7b85f306c..e5933b85ee1 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 - #define CONFIG_PHY_NATSEMI #define CONFIG_FACTORYSET diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 55ec9175148..61e337617cf 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -111,7 +111,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index c72fc5303fb..f48559e3219 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -128,7 +128,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index f9ca9149d6c..ed91bdc1243 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -167,7 +167,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 0ae858d4968..5d788474508 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -127,7 +127,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 5588a1822b1..498b32b639d 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -125,7 +125,6 @@ #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 6a169b0f0d3..861e5027754 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -276,7 +276,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/thuban.h b/include/configs/thuban.h index e844cdd2792..a2352538dd9 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -41,8 +41,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 - #undef CONFIG_MII #undef CONFIG_PHY_GIGE #define CONFIG_PHY_SMSC diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 5cfed0d6196..a5dc91b3bae 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -161,7 +161,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 0a459fb5c56..381e9a37175 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -125,7 +125,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 03496c7b35b..1be8137e33f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -235,9 +235,6 @@ #endif -/* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ - /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h index 4c509dfca88..eb42d8c347f 100644 --- a/include/configs/woodburn_sd.h +++ b/include/configs/woodburn_sd.h @@ -23,7 +23,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */ #define CONFIG_SPL_TEXT_BASE 0x10002300 #define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index f305598fde5..8524b280b95 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -303,7 +303,6 @@ /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f511e29715e..fc2a08a8566 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7830,7 +7830,6 @@ CONFIG_SYS_USE_SERIALFLASH CONFIG_SYS_USE_SPIFLASH CONFIG_SYS_USE_UBI CONFIG_SYS_USR_EXCEP -CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_VA_BITS CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR -- cgit v1.3.1 From 20343ff3ad7005ac128866978443c7ebfa82a852 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sun, 30 Oct 2016 23:16:26 +0530 Subject: spi: Remove dual flash options/flags Dual flash code in spi are usually take the spi controller to work with dual connected flash devices. Usually these dual connection operation's are referred to flash controller protocol rather with spi controller protocol, these are still present in flash side for the usage of spi-nor controllers. So, this patch remove the dual_flash options or flags in sf which are triggered from spi controller side. Cc: Bin Meng Cc: York Sun Cc: Vignesh R Cc: Mugunthan V N Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki Reviewed-by: Simon Glass Reviewed-by: Jagan Teki --- drivers/mtd/spi/sf.c | 4 ---- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi_flash.c | 7 ++----- include/spi.h | 6 ------ 4 files changed, 3 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index 664e86082b1..d5e175ca000 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,10 +18,6 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; -#ifdef CONFIG_SF_DUAL_FLASH - if (spi->flags & SPI_XFER_U_PAGE) - flags |= SPI_XFER_U_PAGE; -#endif if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index fc10562d0b2..2463686617e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -23,6 +23,7 @@ enum spi_dual_flash { enum spi_nor_option_flags { SNOR_F_SST_WR = BIT(0), SNOR_F_USE_FSR = BIT(1), + SNOR_F_USE_UPAGE = BIT(3), }; #define SPI_FLASH_3B_ADDR_LEN 3 diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index cfecd53cea0..2576c2cd3d9 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -199,15 +199,13 @@ bar_end: #ifdef CONFIG_SF_DUAL_FLASH static void spi_flash_dual(struct spi_flash *flash, u32 *addr) { - struct spi_slave *spi = flash->spi; - switch (flash->dual_flash) { case SF_DUAL_STACKED_FLASH: if (*addr >= (flash->size >> 1)) { *addr -= flash->size >> 1; - spi->flags |= SPI_XFER_U_PAGE; + flash->flags |= SNOR_F_USE_UPAGE; } else { - spi->flags &= ~SPI_XFER_U_PAGE; + flash->flags &= ~SNOR_F_USE_UPAGE; } break; case SF_DUAL_PARALLEL_FLASH: @@ -1016,7 +1014,6 @@ int spi_flash_scan(struct spi_flash *flash) flash->name = info->name; flash->memory_map = spi->memory_map; - flash->dual_flash = spi->option; if (info->flags & SST_WR) flash->flags |= SNOR_F_SST_WR; diff --git a/include/spi.h b/include/spi.h index 4c179838eef..deb65efdfb7 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,10 +30,6 @@ #define SPI_RX_DUAL BIT(12) /* receive with 2 wires */ #define SPI_RX_QUAD BIT(13) /* receive with 4 wires */ -/* SPI bus connection options - see enum spi_dual_flash */ -#define SPI_CONN_DUAL_SHARED (1 << 0) -#define SPI_CONN_DUAL_SEPARATED (1 << 1) - /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@ -93,7 +89,6 @@ struct dm_spi_slave_platdata { * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. - * @option: Varies SPI bus options - separate, shared bus. * @flags: Indication of SPI flags. */ struct spi_slave { @@ -117,7 +112,6 @@ struct spi_slave { #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) #define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */ #define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */ -#define SPI_XFER_U_PAGE BIT(4) }; /** -- cgit v1.3.1 From 185e586dac02be44c7e707754cf6bb313ade2bba Mon Sep 17 00:00:00 2001 From: Pratiyush Srivastava Date: Mon, 10 Oct 2016 18:45:15 +0530 Subject: armv8:ls1012a: Update bootargs for fast-boot Add optimization parameters like "quiet" in bootargs to reduce the system boot time Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Harninder Rai Reviewed-by: York Sun --- include/configs/ls1012a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 80603c9e467..20f0c6143ca 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -110,7 +110,7 @@ "kernel_size=0x2800000\0" \ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" + "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" -- cgit v1.3.1 From 21640db51b905aa9bee75a01ca89446ce4795ff1 Mon Sep 17 00:00:00 2001 From: Yuan Yao Date: Tue, 11 Oct 2016 12:13:40 +0800 Subject: configs: ls2080ardb: Enable DSPI flash support There is the stmicro DSPI flash on LS12080ARDB. Enable DSPI flash related configure options. Signed-off-by: Yuan Yao Reviewed-by: York Sun --- include/configs/ls2080ardb.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 32fa0eb3ee3..31df7819349 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -269,6 +269,7 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_STMICRO #endif /* -- cgit v1.3.1 From 20c700f8daee0b3995c5a6d2c5f69eef1c7acd4e Mon Sep 17 00:00:00 2001 From: Feng Li Date: Thu, 3 Nov 2016 14:15:17 +0800 Subject: armv7: Add support of ls1021a-iot board The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun --- arch/arm/Kconfig | 15 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/ls1021a-iot-duart.dts | 16 ++ arch/arm/dts/ls1021a-iot.dtsi | 103 ++++++++ board/freescale/ls1021aiot/Kconfig | 15 ++ board/freescale/ls1021aiot/MAINTAINERS | 7 + board/freescale/ls1021aiot/Makefile | 9 + board/freescale/ls1021aiot/README | 58 ++++ board/freescale/ls1021aiot/dcu.c | 47 ++++ board/freescale/ls1021aiot/ls1021aiot.c | 259 ++++++++++++++++++ board/freescale/ls1021aiot/ls102xa_pbi.cfg | 14 + board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | 27 ++ board/freescale/ls1021aiot/psci.S | 28 ++ configs/ls1021aiot_qspi_defconfig | 15 ++ configs/ls1021aiot_sdcard_defconfig | 17 ++ include/configs/ls1021aiot.h | 367 ++++++++++++++++++++++++++ 16 files changed, 999 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ls1021a-iot-duart.dts create mode 100644 arch/arm/dts/ls1021a-iot.dtsi create mode 100644 board/freescale/ls1021aiot/Kconfig create mode 100644 board/freescale/ls1021aiot/MAINTAINERS create mode 100644 board/freescale/ls1021aiot/Makefile create mode 100644 board/freescale/ls1021aiot/README create mode 100644 board/freescale/ls1021aiot/dcu.c create mode 100644 board/freescale/ls1021aiot/ls1021aiot.c create mode 100644 board/freescale/ls1021aiot/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg create mode 100644 board/freescale/ls1021aiot/psci.S create mode 100644 configs/ls1021aiot_qspi_defconfig create mode 100644 configs/ls1021aiot_sdcard_defconfig create mode 100644 include/configs/ls1021aiot.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7a9b11c766..9d4d74235a1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,20 @@ config TARGET_LS1021ATWR select ARCH_SUPPORT_PSCI select LS1_DEEP_SLEEP +config TARGET_LS1021AIOT + bool "Support ls1021aiot" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SUPPORT_SPL + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + help + Support for Freescale LS1021AIOT platform. + The LS1021A Freescale board (IOT) is a high-performance + development platform that supports the QorIQ LS1021A + Layerscape Architecture processor. + config TARGET_LS1043AQDS bool "Support ls1043aqds" select ARCH_LS1043A @@ -962,6 +976,7 @@ source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2c5b2f22c64..36133f59e30 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -143,7 +143,8 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ - ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb + ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ + ls1021a-iot-duart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ diff --git a/arch/arm/dts/ls1021a-iot-duart.dts b/arch/arm/dts/ls1021a-iot-duart.dts new file mode 100644 index 00000000000..62e4c670403 --- /dev/null +++ b/arch/arm/dts/ls1021a-iot-duart.dts @@ -0,0 +1,16 @@ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a-iot.dtsi" + +/ { + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/ls1021a-iot.dtsi b/arch/arm/dts/ls1021a-iot.dtsi new file mode 100644 index 00000000000..1817c62c04c --- /dev/null +++ b/arch/arm/dts/ls1021a-iot.dtsi @@ -0,0 +1,103 @@ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include "ls1021a.dtsi" + +/ { + model = "LS1021A IOT Board"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + spi0 = &qspi; + spi1 = &dspi1; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: n25q128a13@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dspiflash: at26df081a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig new file mode 100644 index 00000000000..4a12c1687fc --- /dev/null +++ b/board/freescale/ls1021aiot/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021AIOT + +config SYS_BOARD + default "ls1021aiot" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021aiot" + +endif diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS new file mode 100644 index 00000000000..2dab7988eeb --- /dev/null +++ b/board/freescale/ls1021aiot/MAINTAINERS @@ -0,0 +1,7 @@ +LS1021AIOT BOARD +M: Feng Li +S: Maintained +F: board/freescale/ls1021aiot/ +F: include/configs/ls1021aiot.h +F: configs/ls1021aiot_sdcard_defconfig +F: configs/ls1021aiot_qspi_defconfig diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile new file mode 100644 index 00000000000..05709e685cc --- /dev/null +++ b/board/freescale/ls1021aiot/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aiot.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README new file mode 100644 index 00000000000..08b0268b9bd --- /dev/null +++ b/board/freescale/ls1021aiot/README @@ -0,0 +1,58 @@ +Overview +-------- +The LS1021A-IOT is a Freescale reference board that hosts +the LS1021A SoC. + +LS1021AIOT board Overview +------------------------- + - DDR Controller + - Supports 1GB un-buffered DDR3L SDRAM discrete + devices(32-bit bus) with 4 bit ECC + - DDR power supplies 1.35V to all devices with + automatic tracking of VTT + - Soldered DDR chip + - Supprot one fixed speed + - Ethernet + - Two on-board SGMII 10/100/1G ethernet ports + - One Gbit Etherent RGMII interface to 4-ports switch + with 4x 10/100/1000 RJ145 ports + - CPLD + - 8-bit registers in CPLD for system configuration + - connected to IFC_AD[0:7] + - Power Supplies + - 12V@5A DC + - SDHC + - SDHC port connects directly to a full 8-bit SD/MMC slot + - Support for SDIO devices + - USB + - Two on-board USB 3.0 + - One on-board USB k22 + - PCIe + - Two MiniPCIe Solts + - SATA + - Support SATA Connector + - AUDIO + - AUDIO in and out + - I/O Expansion + - Arduino Shield Connector + - Port0 - CAN/GPIO/Flextimer + - Port1 - GPIO/CPLD Expansion + - Port2 - SPI/I2C/UART + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB +0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB +0x00_6000_0000 0x00_6000_FFFF CPLD 64K +0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB + +Boot description +----------------- +LS1021A-IOT support two ways of boot: +Qspi boot and SD boot +The board doesn't support boot from another +source without changing any switch/jumper. diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c new file mode 100644 index 00000000000..e27647f6e65 --- /dev/null +++ b/board/freescale/ls1021aiot/dcu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "div64.h" +#include "../common/dcu_sii9022a.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + + if (strncmp(port, "twr_lcd", 4) == 0) { + name = "TWR_LCD_RGB card"; + } else { + name = "HDMI"; + dcu_set_dvi_encoder(dcu_fb_videomode); + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c new file mode 100644 index 00000000000..3340e4db80b --- /dev/null +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -0,0 +1,259 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_SIZE 0x40000000 + + +int checkboard(void) +{ + puts("Board: LS1021AIOT\n"); + +#ifndef CONFIG_QSPI_BOOT + struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cpldrev; + + cpldrev = in_be32(&dcfg->gpporcr1); + + printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & + 0xf)); +#endif + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(500); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + ddrmc_init(); +#endif + + gd->ram_size = DDR_SIZE; + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} + +#endif + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + +#endif + + arch_soc_init(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + /* Allow OCRAM access permission as R/W */ + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + board_init_r(NULL, 0); +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#endif + + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_init(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); + +#endif + +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg new file mode 100644 index 00000000000..b5ac5e27e9d --- /dev/null +++ b/board/freescale/ls1021aiot/ls102xa_pbi.cfg @@ -0,0 +1,14 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF + +09ea085c 00502880 diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg new file mode 100644 index 00000000000..a1984c713d5 --- /dev/null +++ b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg @@ -0,0 +1,27 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol + +#Default with 2 x SGMII (no SATA) +0608000a 00000000 00000000 00000000 +20000000 08407900 60025a00 21046000 +00000000 00000000 00000000 20038000 +20024800 881b1340 00000000 00000000 + +#SATA set-up +#0608000a 00000000 00000000 00000000 +#70000000 08007900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#20024800 881b1340 00000000 00000000 + +#HDMI set-up +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#00000000 881b1340 00000000 00000000 + +#QE testing +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 00038000 +#20094800 881b1340 00000000 00000000 diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S new file mode 100644 index 00000000000..564145c42a9 --- /dev/null +++ b/board/freescale/ls1021aiot/psci.S @@ -0,0 +1,28 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Feng Li + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + +.globl psci_text_end +psci_text_end: + nop + .popsection diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig new file mode 100644 index 00000000000..6c9140bd458 --- /dev/null +++ b/configs/ls1021aiot_qspi_defconfig @@ -0,0 +1,15 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_ARM=y +CONFIG_DM_SPI=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_TARGET_LS1021AIOT=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig new file mode 100644 index 00000000000..4b082ab0f96 --- /dev/null +++ b/configs/ls1021aiot_sdcard_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021AIOT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" +CONFIG_DM_SPI=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_CMD_DM=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h new file mode 100644 index 00000000000..182a0036031 --- /dev/null +++ b/include/configs/ls1021aiot.h @@ -0,0 +1,367 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_LS102XA + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* XHCI Support - enabled by default */ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +/* + * Generic Timer Definitions + */ +#define GENERIC_TIMER_CLK 12500000 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +/* + * DDR: 800 MHz ( 1600 MT/s data rate ) + */ + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1021aiot/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_FSL_CAAM /* Enable CAAM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CONFIG_BAUDRATE 115200 + +/* + * I2C + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * MMC + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#ifndef PCI_DEVICE_ID_FREESCALE_AHCI +#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 +#endif +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ + PCI_DEVICE_ID_FREESCALE_AHCI} + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* SPI */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SPI_FLASH_SPANSION + +/* QSPI */ +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION +#endif + +/* DM SPI */ +#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#endif + +/* + * eTSEC + */ +#define CONFIG_TSEC_ENET + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII +#define CONFIG_MII_DEFAULT_TSEC 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC2" + +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ + +/* Use common FSL Layerscape PCIe code */ +#define CONFIG_PCIE_LAYERSCAPE +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#endif + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII + +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) +#undef CONFIG_CMD_IMLS +#endif + +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ +"initrd_high=0xffffffff\0" \ +"fdt_high=0xffffffff\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +/* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + +/* + * Environment + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif + +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS +#define CONFIG_CMD_BOOTZ + +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ + +#ifdef CONFIG_FSL_CAAM + +#define CONFIG_CMD_HASH + +#define CONFIG_SHA_HW_ACCEL + +#endif + +#include + +#endif -- cgit v1.3.1 From fdc2b54cb864210437010ef84934b3d04bb723c6 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 28 Oct 2016 14:24:02 +0800 Subject: armv8: ls1046aqds: add lpuart support LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++++++++++ arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +++ arch/arm/dts/fsl-ls1046a.dtsi | 54 +++++++++++++++++++++++++++++++++ board/freescale/ls1046aqds/ls1046aqds.c | 18 +++++++++++ configs/ls1046aqds_lpuart_defconfig | 30 ++++++++++++++++++ include/configs/ls1046aqds.h | 8 +++++ 7 files changed, 131 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts create mode 100644 configs/ls1046aqds_lpuart_defconfig (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 36133f59e30..26f1e92ee4a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -151,6 +151,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts new file mode 100644 index 00000000000..21243d07663 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1046a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c5122930fe1..a49ca08d888 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -75,3 +75,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 87dd9976d15..359a9d13bf8 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -151,6 +151,60 @@ clocks = <&clockgen 4 0>; }; + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + qspi: quadspi@1550000 { compatible = "fsl,vf610-qspi"; #address-cells = <1>; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 8c185385030..552365b9d88 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ + return gd->bus_clk; +} +#endif + int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -157,6 +164,9 @@ int board_early_init_f(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif +#ifdef CONFIG_LPUART + u8 uart; +#endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); @@ -175,6 +185,14 @@ int board_early_init_f(void) out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + return 0; } diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig new file mode 100644 index 00000000000..25bb5f9f735 --- /dev/null +++ b/configs/ls1046aqds_lpuart_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_FSL_DDR4=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_BOOTDELAY=10 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_FSL_DSPI=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index c0f5bd3562e..29e0aa5ee1e 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -127,6 +127,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x2 +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- cgit v1.3.1 From ada03c3c3d41ba9b9886c5d4ba75e744c2b0cf88 Mon Sep 17 00:00:00 2001 From: Semen Protsenko Date: Mon, 24 Oct 2016 18:41:11 +0300 Subject: ti_omap5_common: Respect USB controller number in fastboot On "fastboot reboot-bootloader" we check "dofastboot" variable and do "fastboot 0" command in U-Boot if it's 1. But there are boards which have USB controller number other than 0, so it should be respected when performing "fastboot" command. This patch reuses CONFIG_FASTBOOT_USB_DEV option toprovide correct USB controller number to "fastboot" command. Signed-off-by: Sam Protsenko Reviewed-by: Tom Rini --- include/configs/ti_omap5_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 29b7d96d962..b85fae39bcc 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -114,7 +114,8 @@ "if test ${dofastboot} -eq 1; then " \ "echo Boot fastboot requested, resetting dofastboot ...;" \ "setenv dofastboot 0; saveenv;" \ - "echo Booting into fastboot ...; fastboot 0;" \ + "echo Booting into fastboot ...; " \ + "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \ "fi;" \ "run findfdt; " \ "run envboot; " \ -- cgit v1.3.1 From c721fd6ee01cca436176a820a741a95e038108ba Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Tue, 25 Oct 2016 18:50:32 +0200 Subject: omap3_beagle: use config_distro_bootcmd Add support for distro_bootcmd on MMC and fall back to prior behavior if distro_bootcmd fails. Tested on Beagleboad xM to boot GRUB2 (and then Linux kernel) in EFI mode from MMC. Signed-off-by: Guillaume GARDET Cc: Tom Rini Reviewed-by: Tom Rini --- include/configs/omap3_beagle.h | 76 ++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 8a69a5f9764..9850aa6c059 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -104,11 +104,52 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run userbutton; then " \ + "setenv bootenv uEnv.txt;" \ + "else " \ + "setenv bootenv user.txt;" \ + "fi;" \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi; " \ + "fi;" \ + "run nandboot;" \ + "setenv bootfile zImage;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcbootz; " \ + "fi; " \ + +#include + #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ + "kernel_addr_r=0x80200000\0" \ "rdaddr=0x81000000\0" \ + "initrd_addr_r=0x81000000\0" \ "fdt_high=0xffffffff\0" \ "fdtaddr=0x80f80000\0" \ + "fdt_addr_r=0x80f80000\0" \ "usbtty=cdc_acm\0" \ "bootfile=uImage\0" \ "ramdisk=ramdisk.gz\0" \ @@ -203,39 +244,8 @@ "userbutton=if gpio input 173; then run userbutton_xm; " \ "else run userbutton_nonxm; fi;\0" \ "userbutton_xm=gpio input 4;\0" \ - "userbutton_nonxm=gpio input 7;\0" -/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run userbutton; then " \ - "setenv bootenv uEnv.txt;" \ - "else " \ - "setenv bootenv user.txt;" \ - "fi;" \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot;" \ - "fi;" \ - "fi; " \ - "fi;" \ - "run nandboot;" \ - "setenv bootfile zImage;" \ - "if run loadimage; then " \ - "run loadfdt;" \ - "run mmcbootz; " \ - "fi; " \ + "userbutton_nonxm=gpio input 7;\0" \ + BOOTENV /* * OMAP3 has 12 GP timers, they can be driven by the system clock -- cgit v1.3.1 From a42cfa4f82efaff1373d1417c8d85036f1189491 Mon Sep 17 00:00:00 2001 From: Semen Protsenko Date: Mon, 31 Oct 2016 19:53:38 +0200 Subject: arm: am57xx: Define Android partition table "fastboot oem format" command reuses "gpt write" command, which in turn requires correct partitions defined in $partitions variable. This patch adds such definition of Android partitions for DRA7XX EVM board. By default $partitions variable contains Linux partition table. In order to prepare Android environment one can run next commands from U-Boot shell: => env set partitions $partitions_android => env save After those operations one can go to fastboot mode and perform "fastboot oem format" to create Android partition table. While at it, enable CONFIG_RANDOM_UUID to spare user from providing UUIDs for each partition manually. Signed-off-by: Sam Protsenko --- include/configs/am57xx_evm.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d865f415bcc..bcbe3cdc84d 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -38,14 +38,33 @@ /* Define the default GPT table for eMMC */ #define PARTS_DEFAULT \ + /* Linux partitions */ \ "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + /* Android partitions */ \ + "partitions_android=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ + "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ + "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ + "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ + "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ + "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ + "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ + "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ + "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ + "name=system,size=768M,uuid=${uuid_gpt_system};" \ + "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ + "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ + "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ + "name=userdata,size=-,uuid=${uuid_gpt_userdata}" #include /* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT #define CONFIG_EFI_PARTITION +#define CONFIG_RANDOM_UUID /* CPSW Ethernet */ #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ -- cgit v1.3.1 From b52ee279ca21aeba23ac731357255ec05534af1b Mon Sep 17 00:00:00 2001 From: Semen Protsenko Date: Mon, 31 Oct 2016 19:53:42 +0200 Subject: arm: am57xx: Enable 8-bit eMMC access Signed-off-by: Sam Protsenko --- include/configs/am57xx_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index bcbe3cdc84d..d009900c397 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -65,6 +65,7 @@ #define CONFIG_CMD_GPT #define CONFIG_EFI_PARTITION #define CONFIG_RANDOM_UUID +#define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ -- cgit v1.3.1 From 4886de76080a970a7153ab802cd083f0a97eb115 Mon Sep 17 00:00:00 2001 From: Semen Protsenko Date: Mon, 31 Oct 2016 19:53:46 +0200 Subject: arm: dra7xx: Unify Android partition table Make Android partition table the same as for AM57x EVM. 1. Make "bootloader" partition start from 0x300 sectors offset, so DRA7 is bootable in Android mode (see CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR option). 2. Increase "bootloader" partition size, because size of u-boot.img is about 632 KiB (when building DT defconfig, with FIT image enabled). 3. Specify "reserved" partition explicitly, rather than specifying "efs" partition start. Reserved area will be used to store U-Boot environment on eMMC. It's convenient to have it exposed explicitly so we can read/write U-Boot environment. 4. Keep all Android partitions locations intact, by reducing "reserved" partition size. CONFIG_ENV_SIZE is considered. Signed-off-by: Sam Protsenko --- include/configs/dra7xx_evm.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 798002d4cd8..1834d04afde 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -54,11 +54,12 @@ /* Android partitions */ \ "partitions_android=" \ "uuid_disk=${uuid_gpt_disk};" \ - "name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=384K,uuid=${uuid_gpt_bootloader};" \ + "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ + "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ - "name=efs,start=1280K,size=16M,uuid=${uuid_gpt_efs};" \ + "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ + "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ -- cgit v1.3.1 From 66a47ff2d8f037e1e9d641623257894a9975c325 Mon Sep 17 00:00:00 2001 From: Stefan Brüns Date: Sun, 6 Nov 2016 18:33:57 +0100 Subject: ext4: Allow reading files with non-zero offset, clamp read len MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Support was already implemented, but not hooked up. This fixes several fails in the test cases. Signed-off-by: Stefan Brüns Acked-by: Stephen Warren --- common/spl/spl_ext.c | 8 ++++---- fs/ext4/ext4fs.c | 17 ++++++----------- include/ext4fs.h | 2 +- 3 files changed, 11 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index b93e1eacd30..1b8e15e37d6 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -42,7 +42,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image, puts("spl: ext4fs_open failed\n"); goto end; } - err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen); + err = ext4fs_read((char *)header, 0, sizeof(struct image_header), &actlen); if (err < 0) { puts("spl: ext4fs_read failed\n"); goto end; @@ -54,7 +54,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image, goto end; } - err = ext4fs_read((char *)spl_image->load_addr, filelen, &actlen); + err = ext4fs_read((char *)spl_image->load_addr, 0, filelen, &actlen); end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -97,7 +97,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image, puts("spl: ext4fs_open failed\n"); goto defaults; } - err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen); + err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, &actlen); if (err < 0) { printf("spl: error reading image %s, err - %d, falling back to default\n", file, err); @@ -127,7 +127,7 @@ defaults: if (err < 0) puts("spl: ext4fs_open failed\n"); - err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen); + err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, &actlen); if (err < 0) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("%s: error reading image %s, err - %d\n", diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 30787377708..7187dcfb056 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -65,8 +65,8 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, short status; /* Adjust len so it we can't read past the end of the file. */ - if (len > filesize) - len = filesize; + if (len + pos > filesize) + len = (filesize - pos); blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize); @@ -190,12 +190,12 @@ int ext4fs_size(const char *filename, loff_t *size) return ext4fs_open(filename, size); } -int ext4fs_read(char *buf, loff_t len, loff_t *actread) +int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread) { if (ext4fs_root == NULL || ext4fs_file == NULL) - return 0; + return -1; - return ext4fs_read_file(ext4fs_file, 0, len, buf, actread); + return ext4fs_read_file(ext4fs_file, offset, len, buf, actread); } int ext4fs_probe(struct blk_desc *fs_dev_desc, @@ -217,11 +217,6 @@ int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, loff_t file_len; int ret; - if (offset != 0) { - printf("** Cannot support non-zero offset **\n"); - return -1; - } - ret = ext4fs_open(filename, &file_len); if (ret < 0) { printf("** File not found %s **\n", filename); @@ -231,7 +226,7 @@ int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, if (len == 0) len = file_len; - return ext4fs_read(buf, len, len_read); + return ext4fs_read(buf, offset, len, len_read); } int ext4fs_uuid(char *uuid_str) diff --git a/include/ext4fs.h b/include/ext4fs.h index 965cd9e9c50..bb556391072 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -135,7 +135,7 @@ int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len, struct ext_filesystem *get_fs(void); int ext4fs_open(const char *filename, loff_t *len); -int ext4fs_read(char *buf, loff_t len, loff_t *actread); +int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread); int ext4fs_mount(unsigned part_length); void ext4fs_close(void); void ext4fs_reinit_global(void); -- cgit v1.3.1 From 983e37007da506e8145f9b3a9e1dce5c11116fb0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 7 Nov 2016 21:34:54 -0500 Subject: arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by: Tom Rini --- arch/arm/Kconfig | 5 +- arch/arm/Makefile | 1 + arch/arm/cpu/armv7/Makefile | 5 - arch/arm/cpu/armv7/am33xx/Kconfig | 137 --- arch/arm/cpu/armv7/am33xx/Makefile | 22 - arch/arm/cpu/armv7/am33xx/board.c | 317 ----- arch/arm/cpu/armv7/am33xx/clk_synthesizer.c | 104 -- arch/arm/cpu/armv7/am33xx/clock.c | 246 ---- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 234 ---- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 231 ---- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 410 ------ arch/arm/cpu/armv7/am33xx/clock_ti816x.c | 450 ------- arch/arm/cpu/armv7/am33xx/config.mk | 48 - arch/arm/cpu/armv7/am33xx/ddr.c | 377 ------ arch/arm/cpu/armv7/am33xx/emif4.c | 140 --- arch/arm/cpu/armv7/am33xx/mux.c | 33 - arch/arm/cpu/armv7/am33xx/sys_info.c | 176 --- arch/arm/cpu/armv7/am33xx/u-boot-spl.lds | 56 - arch/arm/cpu/armv7/omap-common/Kconfig | 17 - arch/arm/cpu/armv7/omap-common/Makefile | 40 - arch/arm/cpu/armv7/omap-common/abb.c | 121 -- arch/arm/cpu/armv7/omap-common/boot-common.c | 252 ---- arch/arm/cpu/armv7/omap-common/clocks-common.c | 892 -------------- arch/arm/cpu/armv7/omap-common/config_secure.mk | 113 -- arch/arm/cpu/armv7/omap-common/emif-common.c | 1504 ----------------------- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 296 ----- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 90 -- arch/arm/cpu/armv7/omap-common/mem-common.c | 174 --- arch/arm/cpu/armv7/omap-common/omap-cache.c | 77 -- arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 231 ---- arch/arm/cpu/armv7/omap-common/pipe3-phy.h | 36 - arch/arm/cpu/armv7/omap-common/reset.c | 29 - arch/arm/cpu/armv7/omap-common/sata.c | 93 -- arch/arm/cpu/armv7/omap-common/sec-common.c | 139 --- arch/arm/cpu/armv7/omap-common/timer.c | 103 -- arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 57 - arch/arm/cpu/armv7/omap-common/utils.c | 113 -- arch/arm/cpu/armv7/omap-common/vc.c | 151 --- arch/arm/cpu/armv7/omap3/Kconfig | 154 --- arch/arm/cpu/armv7/omap3/Makefile | 21 - arch/arm/cpu/armv7/omap3/am35x_musb.c | 61 - arch/arm/cpu/armv7/omap3/board.c | 434 ------- arch/arm/cpu/armv7/omap3/boot.c | 104 -- arch/arm/cpu/armv7/omap3/clock.c | 799 ------------ arch/arm/cpu/armv7/omap3/config.mk | 15 - arch/arm/cpu/armv7/omap3/emac.c | 29 - arch/arm/cpu/armv7/omap3/emif4.c | 165 --- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 476 ------- arch/arm/cpu/armv7/omap3/sdrc.c | 241 ---- arch/arm/cpu/armv7/omap3/spl_id_nand.c | 57 - arch/arm/cpu/armv7/omap3/sys_info.c | 343 ------ arch/arm/cpu/armv7/omap4/Kconfig | 65 - arch/arm/cpu/armv7/omap4/Makefile | 13 - arch/arm/cpu/armv7/omap4/boot.c | 105 -- arch/arm/cpu/armv7/omap4/config.mk | 15 - arch/arm/cpu/armv7/omap4/emif.c | 112 -- arch/arm/cpu/armv7/omap4/hw_data.c | 460 ------- arch/arm/cpu/armv7/omap4/hwinit.c | 177 --- arch/arm/cpu/armv7/omap4/prcm-regs.c | 307 ----- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 324 ----- arch/arm/cpu/armv7/omap5/Kconfig | 94 -- arch/arm/cpu/armv7/omap5/Makefile | 17 - arch/arm/cpu/armv7/omap5/abb.c | 57 - arch/arm/cpu/armv7/omap5/boot.c | 46 - arch/arm/cpu/armv7/omap5/config.mk | 22 - arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c | 274 ----- arch/arm/cpu/armv7/omap5/emif.c | 88 -- arch/arm/cpu/armv7/omap5/fdt.c | 244 ---- arch/arm/cpu/armv7/omap5/hw_data.c | 776 ------------ arch/arm/cpu/armv7/omap5/hwinit.c | 453 ------- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1024 --------------- arch/arm/cpu/armv7/omap5/sdram.c | 742 ----------- arch/arm/cpu/armv7/omap5/sec-fxns.c | 126 -- arch/arm/mach-omap2/Kconfig | 17 + arch/arm/mach-omap2/Makefile | 45 + arch/arm/mach-omap2/abb.c | 121 ++ arch/arm/mach-omap2/am33xx/Kconfig | 137 +++ arch/arm/mach-omap2/am33xx/Makefile | 22 + arch/arm/mach-omap2/am33xx/board.c | 317 +++++ arch/arm/mach-omap2/am33xx/clk_synthesizer.c | 104 ++ arch/arm/mach-omap2/am33xx/clock.c | 246 ++++ arch/arm/mach-omap2/am33xx/clock_am33xx.c | 234 ++++ arch/arm/mach-omap2/am33xx/clock_am43xx.c | 231 ++++ arch/arm/mach-omap2/am33xx/clock_ti814x.c | 410 ++++++ arch/arm/mach-omap2/am33xx/clock_ti816x.c | 450 +++++++ arch/arm/mach-omap2/am33xx/ddr.c | 377 ++++++ arch/arm/mach-omap2/am33xx/emif4.c | 140 +++ arch/arm/mach-omap2/am33xx/mux.c | 33 + arch/arm/mach-omap2/am33xx/sys_info.c | 176 +++ arch/arm/mach-omap2/am33xx/u-boot-spl.lds | 56 + arch/arm/mach-omap2/boot-common.c | 252 ++++ arch/arm/mach-omap2/clocks-common.c | 892 ++++++++++++++ arch/arm/mach-omap2/config.mk | 53 + arch/arm/mach-omap2/config_secure.mk | 113 ++ arch/arm/mach-omap2/emif-common.c | 1504 +++++++++++++++++++++++ arch/arm/mach-omap2/hwinit-common.c | 296 +++++ arch/arm/mach-omap2/lowlevel_init.S | 90 ++ arch/arm/mach-omap2/mem-common.c | 174 +++ arch/arm/mach-omap2/omap-cache.c | 77 ++ arch/arm/mach-omap2/omap3/Kconfig | 154 +++ arch/arm/mach-omap2/omap3/Makefile | 21 + arch/arm/mach-omap2/omap3/am35x_musb.c | 61 + arch/arm/mach-omap2/omap3/board.c | 434 +++++++ arch/arm/mach-omap2/omap3/boot.c | 104 ++ arch/arm/mach-omap2/omap3/clock.c | 799 ++++++++++++ arch/arm/mach-omap2/omap3/emac.c | 29 + arch/arm/mach-omap2/omap3/emif4.c | 165 +++ arch/arm/mach-omap2/omap3/lowlevel_init.S | 476 +++++++ arch/arm/mach-omap2/omap3/sdrc.c | 241 ++++ arch/arm/mach-omap2/omap3/spl_id_nand.c | 57 + arch/arm/mach-omap2/omap3/sys_info.c | 343 ++++++ arch/arm/mach-omap2/omap4/Kconfig | 65 + arch/arm/mach-omap2/omap4/Makefile | 13 + arch/arm/mach-omap2/omap4/boot.c | 105 ++ arch/arm/mach-omap2/omap4/emif.c | 112 ++ arch/arm/mach-omap2/omap4/hw_data.c | 460 +++++++ arch/arm/mach-omap2/omap4/hwinit.c | 177 +++ arch/arm/mach-omap2/omap4/prcm-regs.c | 307 +++++ arch/arm/mach-omap2/omap4/sdram_elpida.c | 324 +++++ arch/arm/mach-omap2/omap5/Kconfig | 94 ++ arch/arm/mach-omap2/omap5/Makefile | 17 + arch/arm/mach-omap2/omap5/abb.c | 57 + arch/arm/mach-omap2/omap5/boot.c | 46 + arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 274 +++++ arch/arm/mach-omap2/omap5/emif.c | 88 ++ arch/arm/mach-omap2/omap5/fdt.c | 244 ++++ arch/arm/mach-omap2/omap5/hw_data.c | 776 ++++++++++++ arch/arm/mach-omap2/omap5/hwinit.c | 453 +++++++ arch/arm/mach-omap2/omap5/prcm-regs.c | 1024 +++++++++++++++ arch/arm/mach-omap2/omap5/sdram.c | 742 +++++++++++ arch/arm/mach-omap2/omap5/sec-fxns.c | 126 ++ arch/arm/mach-omap2/pipe3-phy.c | 231 ++++ arch/arm/mach-omap2/pipe3-phy.h | 36 + arch/arm/mach-omap2/reset.c | 29 + arch/arm/mach-omap2/sata.c | 93 ++ arch/arm/mach-omap2/sec-common.c | 139 +++ arch/arm/mach-omap2/timer.c | 103 ++ arch/arm/mach-omap2/u-boot-spl.lds | 57 + arch/arm/mach-omap2/utils.c | 113 ++ arch/arm/mach-omap2/vc.c | 151 +++ include/configs/am335x_evm.h | 2 +- include/configs/am335x_igep0033.h | 2 +- include/configs/am335x_shc.h | 2 +- include/configs/am335x_sl50.h | 2 +- include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/baltos.h | 2 +- include/configs/bav335x.h | 2 +- include/configs/bur_am335x_common.h | 2 +- include/configs/cm_t335.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/cm_t43.h | 2 +- include/configs/imx6_spl.h | 2 +- include/configs/kc1.h | 2 +- include/configs/mcx.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/pcm051.h | 2 +- include/configs/pengwyn.h | 2 +- include/configs/pepper.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/sniper.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tao3530.h | 2 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_omap3_common.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/ti_omap5_common.h | 2 +- include/configs/tricorder.h | 2 +- 170 files changed, 15940 insertions(+), 15987 deletions(-) delete mode 100644 arch/arm/cpu/armv7/am33xx/Kconfig delete mode 100644 arch/arm/cpu/armv7/am33xx/Makefile delete mode 100644 arch/arm/cpu/armv7/am33xx/board.c delete mode 100644 arch/arm/cpu/armv7/am33xx/clk_synthesizer.c delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c delete mode 100644 arch/arm/cpu/armv7/am33xx/clock_am33xx.c delete mode 100644 arch/arm/cpu/armv7/am33xx/clock_am43xx.c delete mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti814x.c delete mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti816x.c delete mode 100644 arch/arm/cpu/armv7/am33xx/config.mk delete mode 100644 arch/arm/cpu/armv7/am33xx/ddr.c delete mode 100644 arch/arm/cpu/armv7/am33xx/emif4.c delete mode 100644 arch/arm/cpu/armv7/am33xx/mux.c delete mode 100644 arch/arm/cpu/armv7/am33xx/sys_info.c delete mode 100644 arch/arm/cpu/armv7/am33xx/u-boot-spl.lds delete mode 100644 arch/arm/cpu/armv7/omap-common/Kconfig delete mode 100644 arch/arm/cpu/armv7/omap-common/Makefile delete mode 100644 arch/arm/cpu/armv7/omap-common/abb.c delete mode 100644 arch/arm/cpu/armv7/omap-common/boot-common.c delete mode 100644 arch/arm/cpu/armv7/omap-common/clocks-common.c delete mode 100644 arch/arm/cpu/armv7/omap-common/config_secure.mk delete mode 100644 arch/arm/cpu/armv7/omap-common/emif-common.c delete mode 100644 arch/arm/cpu/armv7/omap-common/hwinit-common.c delete mode 100644 arch/arm/cpu/armv7/omap-common/lowlevel_init.S delete mode 100644 arch/arm/cpu/armv7/omap-common/mem-common.c delete mode 100644 arch/arm/cpu/armv7/omap-common/omap-cache.c delete mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c delete mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h delete mode 100644 arch/arm/cpu/armv7/omap-common/reset.c delete mode 100644 arch/arm/cpu/armv7/omap-common/sata.c delete mode 100644 arch/arm/cpu/armv7/omap-common/sec-common.c delete mode 100644 arch/arm/cpu/armv7/omap-common/timer.c delete mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds delete mode 100644 arch/arm/cpu/armv7/omap-common/utils.c delete mode 100644 arch/arm/cpu/armv7/omap-common/vc.c delete mode 100644 arch/arm/cpu/armv7/omap3/Kconfig delete mode 100644 arch/arm/cpu/armv7/omap3/Makefile delete mode 100644 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delete mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c delete mode 100644 arch/arm/cpu/armv7/omap5/Kconfig delete mode 100644 arch/arm/cpu/armv7/omap5/Makefile delete mode 100644 arch/arm/cpu/armv7/omap5/abb.c delete mode 100644 arch/arm/cpu/armv7/omap5/boot.c delete mode 100644 arch/arm/cpu/armv7/omap5/config.mk delete mode 100644 arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c delete mode 100644 arch/arm/cpu/armv7/omap5/emif.c delete mode 100644 arch/arm/cpu/armv7/omap5/fdt.c delete mode 100644 arch/arm/cpu/armv7/omap5/hw_data.c delete mode 100644 arch/arm/cpu/armv7/omap5/hwinit.c delete mode 100644 arch/arm/cpu/armv7/omap5/prcm-regs.c delete mode 100644 arch/arm/cpu/armv7/omap5/sdram.c delete mode 100644 arch/arm/cpu/armv7/omap5/sec-fxns.c create mode 100644 arch/arm/mach-omap2/Kconfig create mode 100644 arch/arm/mach-omap2/Makefile create mode 100644 arch/arm/mach-omap2/abb.c create mode 100644 arch/arm/mach-omap2/am33xx/Kconfig create mode 100644 arch/arm/mach-omap2/am33xx/Makefile create mode 100644 arch/arm/mach-omap2/am33xx/board.c create mode 100644 arch/arm/mach-omap2/am33xx/clk_synthesizer.c create mode 100644 arch/arm/mach-omap2/am33xx/clock.c create mode 100644 arch/arm/mach-omap2/am33xx/clock_am33xx.c create mode 100644 arch/arm/mach-omap2/am33xx/clock_am43xx.c create mode 100644 arch/arm/mach-omap2/am33xx/clock_ti814x.c create mode 100644 arch/arm/mach-omap2/am33xx/clock_ti816x.c create mode 100644 arch/arm/mach-omap2/am33xx/ddr.c create mode 100644 arch/arm/mach-omap2/am33xx/emif4.c create mode 100644 arch/arm/mach-omap2/am33xx/mux.c create mode 100644 arch/arm/mach-omap2/am33xx/sys_info.c create mode 100644 arch/arm/mach-omap2/am33xx/u-boot-spl.lds create mode 100644 arch/arm/mach-omap2/boot-common.c create mode 100644 arch/arm/mach-omap2/clocks-common.c create mode 100644 arch/arm/mach-omap2/config.mk create mode 100644 arch/arm/mach-omap2/config_secure.mk create mode 100644 arch/arm/mach-omap2/emif-common.c create mode 100644 arch/arm/mach-omap2/hwinit-common.c create mode 100644 arch/arm/mach-omap2/lowlevel_init.S create mode 100644 arch/arm/mach-omap2/mem-common.c create mode 100644 arch/arm/mach-omap2/omap-cache.c create mode 100644 arch/arm/mach-omap2/omap3/Kconfig create mode 100644 arch/arm/mach-omap2/omap3/Makefile create mode 100644 arch/arm/mach-omap2/omap3/am35x_musb.c create mode 100644 arch/arm/mach-omap2/omap3/board.c create mode 100644 arch/arm/mach-omap2/omap3/boot.c create mode 100644 arch/arm/mach-omap2/omap3/clock.c create mode 100644 arch/arm/mach-omap2/omap3/emac.c create mode 100644 arch/arm/mach-omap2/omap3/emif4.c create mode 100644 arch/arm/mach-omap2/omap3/lowlevel_init.S create mode 100644 arch/arm/mach-omap2/omap3/sdrc.c create mode 100644 arch/arm/mach-omap2/omap3/spl_id_nand.c create mode 100644 arch/arm/mach-omap2/omap3/sys_info.c create mode 100644 arch/arm/mach-omap2/omap4/Kconfig create mode 100644 arch/arm/mach-omap2/omap4/Makefile create mode 100644 arch/arm/mach-omap2/omap4/boot.c create mode 100644 arch/arm/mach-omap2/omap4/emif.c create mode 100644 arch/arm/mach-omap2/omap4/hw_data.c create mode 100644 arch/arm/mach-omap2/omap4/hwinit.c create mode 100644 arch/arm/mach-omap2/omap4/prcm-regs.c create mode 100644 arch/arm/mach-omap2/omap4/sdram_elpida.c create mode 100644 arch/arm/mach-omap2/omap5/Kconfig create mode 100644 arch/arm/mach-omap2/omap5/Makefile create mode 100644 arch/arm/mach-omap2/omap5/abb.c create mode 100644 arch/arm/mach-omap2/omap5/boot.c create mode 100644 arch/arm/mach-omap2/omap5/dra7xx_iodelay.c create mode 100644 arch/arm/mach-omap2/omap5/emif.c create mode 100644 arch/arm/mach-omap2/omap5/fdt.c create mode 100644 arch/arm/mach-omap2/omap5/hw_data.c create mode 100644 arch/arm/mach-omap2/omap5/hwinit.c create mode 100644 arch/arm/mach-omap2/omap5/prcm-regs.c create mode 100644 arch/arm/mach-omap2/omap5/sdram.c create mode 100644 arch/arm/mach-omap2/omap5/sec-fxns.c create mode 100644 arch/arm/mach-omap2/pipe3-phy.c create mode 100644 arch/arm/mach-omap2/pipe3-phy.h create mode 100644 arch/arm/mach-omap2/reset.c create mode 100644 arch/arm/mach-omap2/sata.c create mode 100644 arch/arm/mach-omap2/sec-common.c create mode 100644 arch/arm/mach-omap2/timer.c create mode 100644 arch/arm/mach-omap2/u-boot-spl.lds create mode 100644 arch/arm/mach-omap2/utils.c create mode 100644 arch/arm/mach-omap2/vc.c (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 308245185b8..acd689beccc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -544,8 +544,7 @@ config ARCH_SOCFPGA config TARGET_CM_T43 bool "Support cm_t43" - select CPU_V7 - select SUPPORT_SPL + select ARCH_OMAP2 config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" @@ -891,7 +890,7 @@ source "arch/arm/cpu/armv7/mx6/Kconfig" source "arch/arm/cpu/armv7/mx5/Kconfig" -source "arch/arm/cpu/armv7/omap-common/Kconfig" +source "arch/arm/mach-omap2/Kconfig" source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 42093c2b5e2..236debb4528 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -63,6 +63,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x +machine-$(CONFIG_ARCH_OMAP2) += omap2 machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 4d3bc9440fa..0e515a4603d 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -23,14 +23,12 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o obj-$(CONFIG_IPROC) += iproc-common/ obj-$(CONFIG_KONA) += kona-common/ -obj-$(CONFIG_OMAP_COMMON) += omap-common/ obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o ifneq (,$(filter s5pc1xx exynos,$(SOC))) obj-y += s5p-common/ endif -obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ @@ -39,9 +37,6 @@ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ obj-$(if $(filter mx5,$(SOC)),y) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ -obj-$(CONFIG_OMAP34XX) += omap3/ -obj-$(CONFIG_OMAP44XX) += omap4/ -obj-$(CONFIG_OMAP54XX) += omap5/ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig deleted file mode 100644 index 8fd32c2a46d..00000000000 --- a/arch/arm/cpu/armv7/am33xx/Kconfig +++ /dev/null @@ -1,137 +0,0 @@ -if AM33XX - -choice - prompt "AM33xx board select" - optional - -config TARGET_AM335X_EVM - bool "Support am335x_evm" - select DM - select DM_SERIAL - select DM_GPIO - select TI_I2C_BOARD_DETECT - help - This option specifies support for the AM335x - GP and HS EVM development platforms. The AM335x - GP EVM is a standalone test, development, and - evaluation module system that enables developers - to write software and develop hardware around - an AM335x processor subsystem. - -config TARGET_AM335X_BALTOS - bool "Support am335x_baltos" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_AM335X_IGEP0033 - bool "Support am335x_igep0033" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_AM335X_SHC - bool "Support am335x based shc board from bosch" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_AM335X_SL50 - bool "Support am335x_sl50" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_BAV335X - bool "Support bav335x" - select DM - select DM_SERIAL - help - The BAV335x OEM Network Processor integrates all the functions of an - embedded network computer in a small, easy to use SODIMM module which - incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8 - processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit - ethernet with simple connection to external connectors. - - For more information, visit: http://birdland.com/oem - -config TARGET_CM_T335 - bool "Support cm_t335" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_PCM051 - bool "Support pcm051" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_PENGWYN - bool "Support pengwyn" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_PEPPER - bool "Support pepper" - select DM - select DM_SERIAL - select DM_GPIO - -endchoice - -endif - -if AM43XX - -config SPL_EXT_SUPPORT - default y - -config SPL_GPIO_SUPPORT - default y - -config SPL_I2C_SUPPORT - default y - -config TARGET_AM43XX_EVM - bool "Support am43xx_evm" - select TI_I2C_BOARD_DETECT - help - This option specifies support for the AM43xx - GP and HS EVM development platforms.The AM437x - GP EVM is a standalone test, development, and - evaluation module system that enables developers - to write software and develop hardware around - an AM43xx processor subsystem. -endif - -if AM43XX || AM33XX -config ISW_ENTRY_ADDR - hex "Address in memory or XIP flash of bootloader entry point" - help - After any reset, the boot ROM on the AM43XX SOC - searches the boot media for a valid boot image. - For non-XIP devices, the ROM then copies the - image into internal memory. - For all boot modes, after the ROM processes the - boot image it eventually computes the entry - point address depending on the device type - (secure/non-secure), boot media (xip/non-xip) and - image headers. - default 0x402F4000 - -config PUB_ROM_DATA_SIZE - hex "Size in bytes of the L3 SRAM reserved by ROM to store data" - help - During the device boot, the public ROM uses the top of - the public L3 OCMC RAM to store r/w data like stack, - heap, globals etc. When the ROM is copying the boot - image from the boot media into memory, the image must - not spill over into this area. This value can be used - during compile time to determine the maximum size of a - boot image. Once the ROM transfers control to the boot - image, this area is no longer used, and can be reclaimed - for run time use by the boot image. - default 0x8400 -endif diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile deleted file mode 100644 index 6fda4825fce..00000000000 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_AM33XX) += clock_am33xx.o -obj-$(CONFIG_TI814X) += clock_ti814x.o -obj-$(CONFIG_AM43XX) += clock_am43xx.o - -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) -obj-y += clock.o -endif - -obj-$(CONFIG_TI816X) += clock_ti816x.o -obj-y += sys_info.o -obj-y += ddr.o -obj-y += emif4.o -obj-y += board.o -obj-y += mux.o - -obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c deleted file mode 100644 index 5ebeac0ee1e..00000000000 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * board.c - * - * Common board functions for AM33XX based boards - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if !CONFIG_IS_ENABLED(OF_CONTROL) -static const struct ns16550_platdata am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, -# ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, -# ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, -# endif -# endif -}; - -U_BOOT_DEVICES(am33xx_uarts) = { - { "ns16550_serial", &am33xx_serial[0] }, -# ifdef CONFIG_SYS_NS16550_COM2 - { "ns16550_serial", &am33xx_serial[1] }, -# ifdef CONFIG_SYS_NS16550_COM3 - { "ns16550_serial", &am33xx_serial[2] }, - { "ns16550_serial", &am33xx_serial[3] }, - { "ns16550_serial", &am33xx_serial[4] }, - { "ns16550_serial", &am33xx_serial[5] }, -# endif -# endif -}; - -#ifdef CONFIG_DM_GPIO -static const struct omap_gpio_platdata am33xx_gpio[] = { - { 0, AM33XX_GPIO0_BASE }, - { 1, AM33XX_GPIO1_BASE }, - { 2, AM33XX_GPIO2_BASE }, - { 3, AM33XX_GPIO3_BASE }, -#ifdef CONFIG_AM43XX - { 4, AM33XX_GPIO4_BASE }, - { 5, AM33XX_GPIO5_BASE }, -#endif -}; - -U_BOOT_DEVICES(am33xx_gpios) = { - { "gpio_omap", &am33xx_gpio[0] }, - { "gpio_omap", &am33xx_gpio[1] }, - { "gpio_omap", &am33xx_gpio[2] }, - { "gpio_omap", &am33xx_gpio[3] }, -#ifdef CONFIG_AM43XX - { "gpio_omap", &am33xx_gpio[4] }, - { "gpio_omap", &am33xx_gpio[5] }, -#endif -}; -#endif -#endif - -#ifndef CONFIG_DM_GPIO -static const struct gpio_bank gpio_bank_am33xx[] = { - { (void *)AM33XX_GPIO0_BASE }, - { (void *)AM33XX_GPIO1_BASE }, - { (void *)AM33XX_GPIO2_BASE }, - { (void *)AM33XX_GPIO3_BASE }, -#ifdef CONFIG_AM43XX - { (void *)AM33XX_GPIO4_BASE }, - { (void *)AM33XX_GPIO5_BASE }, -#endif -}; - -const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; -#endif - -#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) -int cpu_mmc_init(bd_t *bis) -{ - int ret; - - ret = omap_mmc_init(0, 0, 0, -1, -1); - if (ret) - return ret; - - return omap_mmc_init(1, 0, 0, -1, -1); -} -#endif - -/* AM33XX has two MUSB controllers which can be host or gadget */ -#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ - (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -/* USB 2.0 PHY Control */ -#define CM_PHY_PWRDN (1 << 0) -#define CM_PHY_OTG_PWRDN (1 << 1) -#define OTGVDET_EN (1 << 19) -#define OTGSESSENDEN (1 << 20) - -static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) -{ - if (on) { - clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, - OTGVDET_EN | OTGSESSENDEN); - } else { - clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); - } -} - -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - -#ifdef CONFIG_AM335X_USB0 -static void am33xx_otg0_set_phy_power(u8 on) -{ - am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); -} - -struct omap_musb_board_data otg0_board_data = { - .set_phy_power = am33xx_otg0_set_phy_power, -}; - -static struct musb_hdrc_platform_data otg0_plat = { - .mode = CONFIG_AM335X_USB0_MODE, - .config = &musb_config, - .power = 50, - .platform_ops = &musb_dsps_ops, - .board_data = &otg0_board_data, -}; -#endif - -#ifdef CONFIG_AM335X_USB1 -static void am33xx_otg1_set_phy_power(u8 on) -{ - am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); -} - -struct omap_musb_board_data otg1_board_data = { - .set_phy_power = am33xx_otg1_set_phy_power, -}; - -static struct musb_hdrc_platform_data otg1_plat = { - .mode = CONFIG_AM335X_USB1_MODE, - .config = &musb_config, - .power = 50, - .platform_ops = &musb_dsps_ops, - .board_data = &otg1_board_data, -}; -#endif -#endif - -int arch_misc_init(void) -{ -#ifdef CONFIG_AM335X_USB0 - musb_register(&otg0_plat, &otg0_board_data, - (void *)USB0_OTG_BASE); -#endif -#ifdef CONFIG_AM335X_USB1 - musb_register(&otg1_plat, &otg1_board_data, - (void *)USB1_OTG_BASE); -#endif - return 0; -} - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -/* - * In the case of non-SPL based booting we'll want to call these - * functions a tiny bit later as it will require gd to be set and cleared - * and that's not true in s_init in this case so we cannot do it there. - */ -int board_early_init_f(void) -{ - prcm_init(); - set_mux_conf_regs(); - - return 0; -} - -/* - * This function is the place to do per-board things such as ramp up the - * MPU clock frequency. - */ -__weak void am33xx_spl_board_init(void) -{ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); -} - -#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) -static void rtc32k_enable(void) -{ - struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; - - /* - * Unlock the RTC's registers. For more details please see the - * RTC_SS section of the TRM. In order to unlock we need to - * write these specific values (keys) in this order. - */ - writel(RTC_KICK0R_WE, &rtc->kick0r); - writel(RTC_KICK1R_WE, &rtc->kick1r); - - /* Enable the RTC 32K OSC by setting bits 3 and 6. */ - writel((1 << 3) | (1 << 6), &rtc->osc); -} -#endif - -static void uart_soft_reset(void) -{ - struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; - u32 regval; - - regval = readl(&uart_base->uartsyscfg); - regval |= UART_RESET; - writel(regval, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regval = readl(&uart_base->uartsyscfg); - regval |= UART_SMART_IDLE_EN; - writel(regval, &uart_base->uartsyscfg); -} - -static void watchdog_disable(void) -{ - struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; -} - -void s_init(void) -{ -} - -void early_system_init(void) -{ - /* - * The ROM will only have set up sufficient pinmux to allow for the - * first 4KiB NOR to be read, we must finish doing what we know of - * the NOR mux in this space in order to continue. - */ -#ifdef CONFIG_NOR_BOOT - enable_norboot_pin_mux(); -#endif - watchdog_disable(); - set_uart_mux_conf(); - setup_early_clocks(); - uart_soft_reset(); -#ifdef CONFIG_TI_I2C_BOARD_DETECT - do_board_detect(); -#endif -#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) - /* Enable RTC32K clock */ - rtc32k_enable(); -#endif -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - early_system_init(); - board_early_init_f(); - sdram_init(); -} -#endif - -#endif - -int arch_cpu_init_dm(void) -{ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - early_system_init(); -#endif - return 0; -} diff --git a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c deleted file mode 100644 index 316e677c65c..00000000000 --- a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * clk-synthesizer.c - * - * Clock synthesizer apis - * - * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include - -/** - * clk_synthesizer_reg_read - Read register from synthesizer. - * @addr: addr within the i2c device - * buf: Buffer to which value is to be read. - * - * For reading the register from this clock synthesizer, a command needs to - * be send along with enabling byte read more, and then read can happen. - * Returns 0 on success - */ -static int clk_synthesizer_reg_read(int addr, uint8_t *buf) -{ - int rc; - - /* Enable Bye read */ - addr = addr | CLK_SYNTHESIZER_BYTE_MODE; - - /* Send the command byte */ - rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); - if (rc) - printf("Failed to send command to clock synthesizer\n"); - - /* Read the Data */ - return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); -} - -/** - * clk_synthesizer_reg_write - Write a value to register in synthesizer. - * @addr: addr within the i2c device - * val: Value to be written in the addr. - * - * Enable the byte read mode in the address and start the i2c transfer. - * Returns 0 on success - */ -static int clk_synthesizer_reg_write(int addr, uint8_t val) -{ - uint8_t cmd[2]; - int rc = 0; - - /* Enable byte write */ - cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE; - cmd[1] = val; - - rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2); - if (rc) - printf("Clock synthesizer reg write failed at addr = 0x%x\n", - addr); - return rc; -} - -/** - * setup_clock_syntherizer - Program the clock synthesizer to get the desired - * frequency. - * @data: Data containing the desired output - * - * This is a PLL-based high performance synthesizer which gives 3 outputs - * as per the PLL_DIV and load capacitor programmed. - */ -int setup_clock_synthesizer(struct clk_synth *data) -{ - int rc; - uint8_t val; - - rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR); - if (rc) { - printf("i2c probe failed at address 0x%x\n", - CLK_SYNTHESIZER_I2C_ADDR); - return rc; - } - - rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val); - if (val != data->id) - return rc; - - /* Crystal Load capacitor selection */ - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor); - if (rc) - return rc; - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux); - if (rc) - return rc; - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2); - if (rc) - return rc; - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3); - if (rc) - return rc; - - return 0; -} diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c deleted file mode 100644 index 3d17698e186..00000000000 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * clock.c - * - * Clock initialization for AM33XX boards. - * Derived from OMAP4 boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -static void setup_post_dividers(const struct dpll_regs *dpll_regs, - const struct dpll_params *params) -{ - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, dpll_regs->cm_div_m3_dpll); - if (params->m4 >= 0) - writel(params->m4, dpll_regs->cm_div_m4_dpll); - if (params->m5 >= 0) - writel(params->m5, dpll_regs->cm_div_m5_dpll); - if (params->m6 >= 0) - writel(params->m6, dpll_regs->cm_div_m6_dpll); -} - -static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) -{ - clrsetbits_le32(dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_lock(const struct dpll_regs *dpll_regs) -{ - if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, - (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("DPLL locking failed for 0x%x\n", - dpll_regs->cm_clkmode_dpll); - hang(); - } -} - -static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) -{ - clrsetbits_le32(dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_bypass(const struct dpll_regs *dpll_regs) -{ - if (!wait_on_value(ST_DPLL_CLK_MASK, 0, - (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("Bypassing DPLL failed 0x%x\n", - dpll_regs->cm_clkmode_dpll); - } -} - -static void bypass_dpll(const struct dpll_regs *dpll_regs) -{ - do_bypass_dpll(dpll_regs); - wait_for_bypass(dpll_regs); -} - -void do_setup_dpll(const struct dpll_regs *dpll_regs, - const struct dpll_params *params) -{ - u32 temp; - - if (!params) - return; - - temp = readl(dpll_regs->cm_clksel_dpll); - - bypass_dpll(dpll_regs); - - /* Set M & N */ - temp &= ~CM_CLKSEL_DPLL_M_MASK; - temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; - - temp &= ~CM_CLKSEL_DPLL_N_MASK; - temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; - - writel(temp, dpll_regs->cm_clksel_dpll); - - setup_post_dividers(dpll_regs, params); - - /* Wait till the DPLL locks */ - do_lock_dpll(dpll_regs); - wait_for_lock(dpll_regs); -} - -static void setup_dplls(void) -{ - const struct dpll_params *params; - - params = get_dpll_core_params(); - do_setup_dpll(&dpll_core_regs, params); - - params = get_dpll_mpu_params(); - do_setup_dpll(&dpll_mpu_regs, params); - - params = get_dpll_per_params(); - do_setup_dpll(&dpll_per_regs, params); - writel(0x300, &cmwkup->clkdcoldodpllper); - - params = get_dpll_ddr_params(); - do_setup_dpll(&dpll_ddr_regs, params); -} - -static inline void wait_for_clk_enable(u32 *clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; - u32 bound = LDELAY; - - while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || - (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock enable failed for 0x%p idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} - -static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, - u32 wait_for_enable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Enable clock module - %p\n", clkctrl_addr); - if (wait_for_enable) - wait_for_clk_enable(clkctrl_addr); -} - -static inline void wait_for_clk_disable(u32 *clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; - u32 bound = LDELAY; - - while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) { - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock disable failed for 0x%p idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} -static inline void disable_clock_module(u32 *const clkctrl_addr, - u32 wait_for_disable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Disable clock module - %p\n", clkctrl_addr); - if (wait_for_disable) - wait_for_clk_disable(clkctrl_addr); -} - -static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Enable clock domain - %p\n", clkctrl_reg); -} - -static inline void disable_clock_domain(u32 *const clkctrl_reg) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Disable clock domain - %p\n", clkctrl_reg); -} - -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_explicit_en, u8 wait_for_enable) -{ - u32 i, max = 100; - - /* Put the clock domains in SW_WKUP mode */ - for (i = 0; (i < max) && clk_domains[i]; i++) { - enable_clock_domain(clk_domains[i], - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - } - - /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ - for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { - enable_clock_module(clk_modules_explicit_en[i], - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, - wait_for_enable); - }; -} - -void do_disable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_disable, - u8 wait_for_disable) -{ - u32 i, max = 100; - - - /* Clock modules that need to be put in SW_DISABLE */ - for (i = 0; (i < max) && clk_modules_disable[i]; i++) - disable_clock_module(clk_modules_disable[i], - wait_for_disable); - - /* Put the clock domains in SW_SLEEP mode */ - for (i = 0; (i < max) && clk_domains[i]; i++) - disable_clock_domain(clk_domains[i]); -} - -/* - * Before scaling up the clocks we need to have the PMIC scale up the - * voltages first. This will be dependent on which PMIC is in use - * and in some cases we may not be scaling things up at all and thus not - * need to do anything here. - */ -__weak void scale_vcores(void) -{ -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); - enable_basic_clocks(); - timer_init(); -} - -void prcm_init(void) -{ - scale_vcores(); - setup_dplls(); -} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c deleted file mode 100644 index 7b841b2d556..00000000000 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * clock_am33xx.c - * - * clocks for AM33XX based boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#define OSC (V_OSCK/1000000) - -struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; -struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; -struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; -struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC; - -const struct dpll_regs dpll_mpu_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x88, - .cm_idlest_dpll = CM_WKUP + 0x20, - .cm_clksel_dpll = CM_WKUP + 0x2C, - .cm_div_m2_dpll = CM_WKUP + 0xA8, -}; - -const struct dpll_regs dpll_core_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x90, - .cm_idlest_dpll = CM_WKUP + 0x5C, - .cm_clksel_dpll = CM_WKUP + 0x68, - .cm_div_m4_dpll = CM_WKUP + 0x80, - .cm_div_m5_dpll = CM_WKUP + 0x84, - .cm_div_m6_dpll = CM_WKUP + 0xD8, -}; - -const struct dpll_regs dpll_per_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x8C, - .cm_idlest_dpll = CM_WKUP + 0x70, - .cm_clksel_dpll = CM_WKUP + 0x9C, - .cm_div_m2_dpll = CM_WKUP + 0xAC, -}; - -const struct dpll_regs dpll_ddr_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x94, - .cm_idlest_dpll = CM_WKUP + 0x34, - .cm_clksel_dpll = CM_WKUP + 0x40, - .cm_div_m2_dpll = CM_WKUP + 0xA0, -}; - -struct dpll_params dpll_mpu_opp100 = { - CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_core_opp100 = { - 1000, OSC-1, -1, -1, 10, 8, 4}; -const struct dpll_params dpll_mpu = { - MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - 50, OSC-1, -1, -1, 1, 1, 1}; -const struct dpll_params dpll_per = { - 960, OSC-1, 5, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_mpu_params(void) -{ - return &dpll_mpu; -} - -const struct dpll_params *get_dpll_core_params(void) -{ - return &dpll_core; -} - -const struct dpll_params *get_dpll_per_params(void) -{ - return &dpll_per; -} - -void setup_clocks_for_console(void) -{ - clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - - clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - - clrsetbits_le32(&cmwkup->wkup_uart0ctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&cmper->uart1clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&cmper->uart2clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&cmper->uart3clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&cmper->uart4clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&cmper->uart5clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - -void enable_basic_clocks(void) -{ - u32 *const clk_domains[] = { - &cmper->l3clkstctrl, - &cmper->l4fwclkstctrl, - &cmper->l3sclkstctrl, - &cmper->l4lsclkstctrl, - &cmwkup->wkclkstctrl, - &cmper->emiffwclkctrl, - &cmrtc->clkstctrl, - 0 - }; - - u32 *const clk_modules_explicit_en[] = { - &cmper->l3clkctrl, - &cmper->l4lsclkctrl, - &cmper->l4fwclkctrl, - &cmwkup->wkl4wkclkctrl, - &cmper->l3instrclkctrl, - &cmper->l4hsclkctrl, - &cmwkup->wkgpio0clkctrl, - &cmwkup->wkctrlclkctrl, - &cmper->timer2clkctrl, - &cmper->gpmcclkctrl, - &cmper->elmclkctrl, - &cmper->mmc0clkctrl, - &cmper->mmc1clkctrl, - &cmwkup->wkup_i2c0ctrl, - &cmper->gpio1clkctrl, - &cmper->gpio2clkctrl, - &cmper->gpio3clkctrl, - &cmper->i2c1clkctrl, - &cmper->cpgmac0clkctrl, - &cmper->spi0clkctrl, - &cmrtc->rtcclkctrl, - &cmper->usb0clkctrl, - &cmper->emiffwclkctrl, - &cmper->emifclkctrl, - 0 - }; - - do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); - - /* Select the Master osc 24 MHZ as Timer2 clock source */ - writel(0x1, &cmdpll->clktimer2clk); -} - -/* - * Enable Spread Spectrum for the MPU by calculating the required - * values and setting the registers accordingly. - * @param permille The spreading in permille (10th of a percent) - */ -void set_mpu_spreadspectrum(int permille) -{ - u32 multiplier_m; - u32 predivider_n; - u32 cm_clksel_dpll_mpu; - u32 cm_clkmode_dpll_mpu; - u32 ref_clock; - u32 pll_bandwidth; - u32 mod_freq_divider; - u32 exponent; - u32 mantissa; - u32 delta_m_step; - - printf("Enabling Spread Spectrum of %d permille for MPU\n", - permille); - - /* Read PLL parameter m and n */ - cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu); - multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF; - predivider_n = cm_clksel_dpll_mpu & 0x7F; - - /* - * Calculate reference clock (clock after pre-divider), - * its max. PLL bandwidth, - * and resulting mod_freq_divider - */ - ref_clock = V_OSCK / (predivider_n + 1); - pll_bandwidth = ref_clock / 70; - mod_freq_divider = ref_clock / (4 * pll_bandwidth); - - /* Calculate Mantissa/Exponent */ - exponent = 0; - mantissa = mod_freq_divider; - while ((mantissa > 127) && (exponent < 7)) { - exponent++; - mantissa /= 2; - } - if (mantissa > 127) - mantissa = 127; - - mod_freq_divider = mantissa << exponent; - - /* - * Calculate Modulation steps - * As we use Downspread only, the spread is twice the value of - * permille, so Div2! - * As it takes the value in percent, divide by ten! - */ - delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18; - delta_m_step /= 100; - delta_m_step /= mod_freq_divider; - if (delta_m_step > 0xFFFFF) - delta_m_step = 0xFFFFF; - - /* Setup Spread Spectrum */ - writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu); - writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu); - cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu); - /* clear all SSC flags */ - cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT); - /* enable SSC with Downspread only */ - cm_clkmode_dpll_mpu |= CM_CLKMODE_DPLL_SSC_EN_MASK | - CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK; - writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu); - while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000)) - ; -} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c deleted file mode 100644 index 73ea955a6cf..00000000000 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * clock_am43xx.c - * - * clocks for AM43XX based boards - * Derived from AM33XX based boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; -struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; -struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; - -const struct dpll_regs dpll_mpu_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x560, - .cm_idlest_dpll = CM_WKUP + 0x564, - .cm_clksel_dpll = CM_WKUP + 0x56c, - .cm_div_m2_dpll = CM_WKUP + 0x570, -}; - -const struct dpll_regs dpll_core_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x520, - .cm_idlest_dpll = CM_WKUP + 0x524, - .cm_clksel_dpll = CM_WKUP + 0x52C, - .cm_div_m4_dpll = CM_WKUP + 0x538, - .cm_div_m5_dpll = CM_WKUP + 0x53C, - .cm_div_m6_dpll = CM_WKUP + 0x540, -}; - -const struct dpll_regs dpll_per_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x5E0, - .cm_idlest_dpll = CM_WKUP + 0x5E4, - .cm_clksel_dpll = CM_WKUP + 0x5EC, - .cm_div_m2_dpll = CM_WKUP + 0x5F0, -}; - -const struct dpll_regs dpll_ddr_regs = { - .cm_clkmode_dpll = CM_WKUP + 0x5A0, - .cm_idlest_dpll = CM_WKUP + 0x5A4, - .cm_clksel_dpll = CM_WKUP + 0x5AC, - .cm_div_m2_dpll = CM_WKUP + 0x5B0, - .cm_div_m4_dpll = CM_WKUP + 0x5B8, -}; - -void setup_clocks_for_console(void) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; - - /* Do not add any spl_debug prints in this function */ - clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - - /* Enable UART0 */ - clrsetbits_le32(&cmwkup->wkup_uart0ctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || - (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { - clkctrl = readl(&cmwkup->wkup_uart0ctrl); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - } -} - -void enable_basic_clocks(void) -{ - u32 *const clk_domains[] = { - &cmper->l3clkstctrl, - &cmper->l3sclkstctrl, - &cmper->l4lsclkstctrl, - &cmwkup->wkclkstctrl, - &cmper->emifclkstctrl, - 0 - }; - - u32 *const clk_modules_explicit_en[] = { - &cmper->l3clkctrl, - &cmper->l4lsclkctrl, - &cmper->l4fwclkctrl, - &cmwkup->wkl4wkclkctrl, - &cmper->l3instrclkctrl, - &cmper->l4hsclkctrl, - &cmwkup->wkgpio0clkctrl, - &cmwkup->wkctrlclkctrl, - &cmper->timer2clkctrl, - &cmper->gpmcclkctrl, - &cmper->elmclkctrl, - &cmper->mmc0clkctrl, - &cmper->mmc1clkctrl, - &cmwkup->wkup_i2c0ctrl, - &cmper->gpio1clkctrl, - &cmper->gpio2clkctrl, - &cmper->gpio3clkctrl, - &cmper->gpio4clkctrl, - &cmper->gpio5clkctrl, - &cmper->i2c1clkctrl, - &cmper->cpgmac0clkctrl, - &cmper->emiffwclkctrl, - &cmper->emifclkctrl, - &cmper->otfaemifclkctrl, - &cmper->qspiclkctrl, - &cmper->spi0clkctrl, - 0 - }; - - do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); - - /* Select the Master osc clk as Timer2 clock source */ - writel(0x1, &cmdpll->clktimer2clk); - - /* For OPP100 the mac clock should be /5. */ - writel(0x4, &cmdpll->clkselmacclk); -} - -#ifdef CONFIG_TI_EDMA3 -void enable_edma3_clocks(void) -{ - u32 *const clk_domains_edma3[] = { - 0 - }; - - u32 *const clk_modules_explicit_en_edma3[] = { - &cmper->tpccclkctrl, - &cmper->tptc0clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_edma3, - clk_modules_explicit_en_edma3, - 1); -} - -void disable_edma3_clocks(void) -{ - u32 *const clk_domains_edma3[] = { - 0 - }; - - u32 *const clk_modules_disable_edma3[] = { - &cmper->tpccclkctrl, - &cmper->tptc0clkctrl, - 0 - }; - - do_disable_clocks(clk_domains_edma3, - clk_modules_disable_edma3, - 1); -} -#endif - -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) -void enable_usb_clocks(int index) -{ - u32 *usbclkctrl = 0; - u32 *usbphyocp2scpclkctrl = 0; - - if (index == 0) { - usbclkctrl = &cmper->usb0clkctrl; - usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl; - setbits_le32(&cmper->usb0clkctrl, - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - setbits_le32(&cmwkup->usbphy0clkctrl, - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); - } else if (index == 1) { - usbclkctrl = &cmper->usb1clkctrl; - usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl; - setbits_le32(&cmper->usb1clkctrl, - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - setbits_le32(&cmwkup->usbphy1clkctrl, - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); - } - - u32 *const clk_domains_usb[] = { - 0 - }; - - u32 *const clk_modules_explicit_en_usb[] = { - usbclkctrl, - usbphyocp2scpclkctrl, - 0 - }; - - do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1); -} - -void disable_usb_clocks(int index) -{ - u32 *usbclkctrl = 0; - u32 *usbphyocp2scpclkctrl = 0; - - if (index == 0) { - usbclkctrl = &cmper->usb0clkctrl; - usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl; - clrbits_le32(&cmper->usb0clkctrl, - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - clrbits_le32(&cmwkup->usbphy0clkctrl, - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); - } else if (index == 1) { - usbclkctrl = &cmper->usb1clkctrl; - usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl; - clrbits_le32(&cmper->usb1clkctrl, - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - clrbits_le32(&cmwkup->usbphy1clkctrl, - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); - } - - u32 *const clk_domains_usb[] = { - 0 - }; - - u32 *const clk_modules_disable_usb[] = { - usbclkctrl, - usbphyocp2scpclkctrl, - 0 - }; - - do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1); -} -#endif diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c deleted file mode 100644 index 50bd631cf6b..00000000000 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * clock_ti814x.c - * - * Clocks for TI814X based boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* PRCM */ -#define PRCM_MOD_EN 0x2 - -/* CLK_SRC */ -#define OSC_SRC0 0 -#define OSC_SRC1 1 - -#define L3_OSC_SRC OSC_SRC0 - -#define OSC_0_FREQ 20 - -#define DCO_HS2_MIN 500 -#define DCO_HS2_MAX 1000 -#define DCO_HS1_MIN 1000 -#define DCO_HS1_MAX 2000 - -#define SELFREQDCO_HS2 0x00000801 -#define SELFREQDCO_HS1 0x00001001 - -#define MPU_N 0x1 -#define MPU_M 0x3C -#define MPU_M2 1 -#define MPU_CLKCTRL 0x1 - -#define L3_N 19 -#define L3_M 880 -#define L3_M2 4 -#define L3_CLKCTRL 0x801 - -#define DDR_N 19 -#define DDR_M 666 -#define DDR_M2 2 -#define DDR_CLKCTRL 0x801 - -/* ADPLLJ register values */ -#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) -#define ADPLLJ_CLKCTRL_IDLE (1 << 23) -#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) -#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) -#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) -#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) -#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) -#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) -#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) -#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ - ADPLLJ_CLKCTRL_CLKOUTEN | \ - ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ - ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) - -#define ADPLLJ_STATUS_PHASELOCK (1 << 10) -#define ADPLLJ_STATUS_FREQLOCK (1 << 9) -#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ - ADPLLJ_STATUS_FREQLOCK) -#define ADPLLJ_STATUS_BYPASSACK (1 << 8) -#define ADPLLJ_STATUS_BYPASS (1 << 0) -#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ - ADPLLJ_STATUS_BYPASS) - -#define ADPLLJ_TENABLE_ENB (1 << 0) -#define ADPLLJ_TENABLEDIV_ENB (1 << 0) - -#define ADPLLJ_M2NDIV_M2SHIFT 16 - -#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) -#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) -#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) - -struct ad_pll { - unsigned int pwrctrl; - unsigned int clkctrl; - unsigned int tenable; - unsigned int tenablediv; - unsigned int m2ndiv; - unsigned int mn2div; - unsigned int fracdiv; - unsigned int bwctrl; - unsigned int fracctrl; - unsigned int status; - unsigned int m3div; - unsigned int rampctrl; -}; - -#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) - -#define ENET_CLKCTRL_CMPL 0x30000 - -#define SATA_PLL_BASE (CTRL_BASE + 0x0720) - -struct sata_pll { - unsigned int pllcfg0; - unsigned int pllcfg1; - unsigned int pllcfg2; - unsigned int pllcfg3; - unsigned int pllcfg4; - unsigned int pllstatus; - unsigned int rxstatus; - unsigned int txstatus; - unsigned int testcfg; -}; - -#define SEL_IN_FREQ (0x1 << 31) -#define DIGCLRZ (0x1 << 30) -#define ENDIGLDO (0x1 << 4) -#define APLL_CP_CURR (0x1 << 3) -#define ENBGSC_REF (0x1 << 2) -#define ENPLLLDO (0x1 << 1) -#define ENPLL (0x1 << 0) - -#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) -#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) -#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) -#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ - ENPLLLDO | ENPLL) - -#define PLL_LOCK (0x1 << 0) - -#define ENSATAMODE (0x1 << 31) -#define PLLREFSEL (0x1 << 30) -#define MDIVINT (0x4b << 18) -#define EN_CLKAUX (0x1 << 5) -#define EN_CLK125M (0x1 << 4) -#define EN_CLK100M (0x1 << 3) -#define EN_CLK50M (0x1 << 2) - -#define SATA_PLLCFG1 (ENSATAMODE | \ - PLLREFSEL | \ - MDIVINT | \ - EN_CLKAUX | \ - EN_CLK125M | \ - EN_CLK100M | \ - EN_CLK50M) - -#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) -#define PLLDO_EN_LDO_STABLE (0x1 << 11) -#define PLLDO_EN_BUF_CUR (0x1 << 7) -#define PLLDO_EN_LP (0x1 << 6) -#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) - -#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ - PLLDO_EN_LDO_STABLE | \ - PLLDO_EN_BUF_CUR | \ - PLLDO_EN_LP | \ - PLLDO_CTRL_TRIM_1_4V) - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; - -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) -{ - /* HSMMC1 */ - writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); - while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - - /* RTC clocks */ - writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); - while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) - ; -} - -/* - * select the HS1 or HS2 for DCO Freq - * return : CLKCTRL - */ -static u32 pll_dco_freq_sel(u32 clkout_dco) -{ - if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) - return SELFREQDCO_HS2; - else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) - return SELFREQDCO_HS1; - else - return -1; -} - -/* - * select the sigma delta config - * return: sigma delta val - */ -static u32 pll_sigma_delta_val(u32 clkout_dco) -{ - u32 sig_val = 0; - - sig_val = (clkout_dco + 225) / 250; - sig_val = sig_val << 24; - - return sig_val; -} - -/* - * configure individual ADPLLJ - */ -static void pll_config(u32 base, u32 n, u32 m, u32 m2, - u32 clkctrl_val, int adpllj) -{ - const struct ad_pll *adpll = (struct ad_pll *)base; - u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; - u32 sig_val = 0, hs_mod = 0; - - m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; - mn2val = m; - - /* calculate clkout_dco */ - clkout_dco = ((OSC_0_FREQ / (n+1)) * m); - - /* sigma delta & Hs mode selection skip for ADPLLS*/ - if (adpllj) { - sig_val = pll_sigma_delta_val(clkout_dco); - hs_mod = pll_dco_freq_sel(clkout_dco); - } - - /* by-pass pll */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); - while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) - != ADPLLJ_STATUS_BYPASSANDACK) - ; - - /* clear TINITZ */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* - * ref_clk = 20/(n + 1); - * clkout_dco = ref_clk * m; - * clk_out = clkout_dco/m2; - */ - read_clkctrl = readl(&adpll->clkctrl) & - ~(ADPLLJ_CLKCTRL_LPMODE | - ADPLLJ_CLKCTRL_DRIFTGUARDIAN | - ADPLLJ_CLKCTRL_REGM4XEN); - writel(m2nval, &adpll->m2ndiv); - writel(mn2val, &adpll->mn2div); - - /* Skip for modena(ADPLLS) */ - if (adpllj) { - writel(sig_val, &adpll->fracdiv); - writel((read_clkctrl | hs_mod), &adpll->clkctrl); - } - - /* Load M2, N2 dividers of ADPLL */ - writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - - /* Load M, N dividers of ADPLL */ - writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); - writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); - - /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; - if (adpllj) - writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), - &adpll->clkctrl); - - /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; - writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* Wait for phase and freq lock */ - while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != - ADPLLJ_STATUS_PHSFRQLOCK) - ; -} - -static void unlock_pll_control_mmr(void) -{ - /* TRM 2.10.1.4 and 3.2.7-3.2.11 */ - writel(0x1EDA4C3D, 0x481C5040); - writel(0x2FF1AC2B, 0x48140060); - writel(0xF757FDC0, 0x48140064); - writel(0xE2BC3A6D, 0x48140068); - writel(0x1EBF131D, 0x4814006c); - writel(0x6F361E05, 0x48140070); -} - -static void mpu_pll_config(void) -{ - pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); -} - -static void l3_pll_config(void) -{ - u32 l3_osc_src, rd_osc_src = 0; - - l3_osc_src = L3_OSC_SRC; - rd_osc_src = readl(OSC_SRC_CTRL); - - if (OSC_SRC0 == l3_osc_src) - writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); - else - writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); - - pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); -} - -void ddr_pll_config(unsigned int ddrpll_m) -{ - pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); -} - -void sata_pll_config(void) -{ - /* - * This sequence for configuring the SATA PLL - * resident in the control module is documented - * in TI8148 TRM section 21.3.1 - */ - writel(SATA_PLLCFG1, &spll->pllcfg1); - udelay(50); - - writel(SATA_PLLCFG3, &spll->pllcfg3); - udelay(50); - - writel(SATA_PLLCFG0_1, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_2, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_3, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_4, &spll->pllcfg0); - udelay(50); - - while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) - ; -} - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->fwclkctrl); - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) - ; - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_clocks_for_console(void) -{ - unlock_pll_control_mmr(); - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void prcm_init(void) -{ - /* Enable the control module */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - /* Configure PLLs */ - mpu_pll_config(); - l3_pll_config(); - sata_pll_config(); - - /* Enable the required peripherals */ - enable_per_clocks(); -} diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c deleted file mode 100644 index 079ddd7eb9f..00000000000 --- a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c +++ /dev/null @@ -1,450 +0,0 @@ -/* - * clock_ti816x.c - * - * Clocks for TI816X based boards - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - * - * Based on TI-PSP-04.00.02.14 : - * - * Copyright (C) 2009, Texas Instruments, Incorporated - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#define CM_PLL_BASE (CTRL_BASE + 0x0400) - -/* Main PLL */ -#define MAIN_N 64 -#define MAIN_P 0x1 -#define MAIN_INTFREQ1 0x8 -#define MAIN_FRACFREQ1 0x800000 -#define MAIN_MDIV1 0x2 -#define MAIN_INTFREQ2 0xE -#define MAIN_FRACFREQ2 0x0 -#define MAIN_MDIV2 0x1 -#define MAIN_INTFREQ3 0x8 -#define MAIN_FRACFREQ3 0xAAAAB0 -#define MAIN_MDIV3 0x3 -#define MAIN_INTFREQ4 0x9 -#define MAIN_FRACFREQ4 0x55554F -#define MAIN_MDIV4 0x3 -#define MAIN_INTFREQ5 0x9 -#define MAIN_FRACFREQ5 0x374BC6 -#define MAIN_MDIV5 0xC -#define MAIN_MDIV6 0x48 -#define MAIN_MDIV7 0x4 - -/* DDR PLL */ -#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x4 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x3 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ -#define DDR_N 50 -#define DDR_P 0x1 -#define DDR_MDIV1 0x2 -#define DDR_INTFREQ2 0x9 -#define DDR_FRACFREQ2 0x0 -#define DDR_MDIV2 0x19 -#define DDR_INTFREQ3 0x13 -#define DDR_FRACFREQ3 0x800000 -#define DDR_MDIV3 0x2 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x2 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#endif - -#define CONTROL_STATUS (CTRL_BASE + 0x40) -#define DDR_RCD (CTRL_BASE + 0x070C) -#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) -#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) -#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) - -#define INTCPS_SYSCONFIG 0x48200010 -#define CM_SYSCLK10_CLKSEL 0x48180324 - -struct cm_pll { - unsigned int mainpll_ctrl; /* offset 0x400 */ - unsigned int mainpll_pwd; - unsigned int mainpll_freq1; - unsigned int mainpll_div1; - unsigned int mainpll_freq2; - unsigned int mainpll_div2; - unsigned int mainpll_freq3; - unsigned int mainpll_div3; - unsigned int mainpll_freq4; - unsigned int mainpll_div4; - unsigned int mainpll_freq5; - unsigned int mainpll_div5; - unsigned int resv0[1]; - unsigned int mainpll_div6; - unsigned int resv1[1]; - unsigned int mainpll_div7; - unsigned int ddrpll_ctrl; /* offset 0x440 */ - unsigned int ddrpll_pwd; - unsigned int resv2[1]; - unsigned int ddrpll_div1; - unsigned int ddrpll_freq2; - unsigned int ddrpll_div2; - unsigned int ddrpll_freq3; - unsigned int ddrpll_div3; - unsigned int ddrpll_freq4; - unsigned int ddrpll_div4; - unsigned int ddrpll_freq5; - unsigned int ddrpll_div5; - unsigned int videopll_ctrl; /* offset 0x470 */ - unsigned int videopll_pwd; - unsigned int videopll_freq1; - unsigned int videopll_div1; - unsigned int videopll_freq2; - unsigned int videopll_div2; - unsigned int videopll_freq3; - unsigned int videopll_div3; - unsigned int resv3[4]; - unsigned int audiopll_ctrl; /* offset 0x4A0 */ - unsigned int audiopll_pwd; - unsigned int resv4[2]; - unsigned int audiopll_freq2; - unsigned int audiopll_div2; - unsigned int audiopll_freq3; - unsigned int audiopll_div3; - unsigned int audiopll_freq4; - unsigned int audiopll_div4; - unsigned int audiopll_freq5; - unsigned int audiopll_div5; -}; - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; -const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - - /* Wait for clocks to be active */ - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - /* Wait for emif0 to be fully functional, including OCP */ - while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) - ; - /* Wait for emif1 to be fully functional, including OCP */ - while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) - ; - - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - /* Wait for dmm to be fully functional, including OCP */ - while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) - ; - - /* Enable Tiled Access */ - writel(0x80000000, DMM_PAT_BASE_ADDR); -} - -/* assume delay is aprox at least 1us */ -static void ddr_delay(int d) -{ - int i; - - /* - * read a control register. - * this is a bit more delay and cannot be optimized by the compiler - * assuming one read takes 200 cycles and A8 is runing 1 GHz - * somewhat conservative setting - */ - for (i = 0; i < 50*d; i++) - readl(CONTROL_STATUS); -} - -static void main_pll_init_ti816x(void) -{ - u32 main_pll_ctrl = 0; - - /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFFB; - main_pll_ctrl |= BIT(2); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Enable PLL by setting BIT3 in its ctrl reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFF7; - main_pll_ctrl |= BIT(3); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Write the values of N,P in the CTRL reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFF; - main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Power up clock1-7 */ - writel(0x0, &cmpll->mainpll_pwd); - - /* Program the freq and divider values for clock1-7 */ - writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), - &cmpll->mainpll_freq1); - writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), - &cmpll->mainpll_freq2); - writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), - &cmpll->mainpll_freq3); - writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), - &cmpll->mainpll_freq4); - writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), - &cmpll->mainpll_freq5); - writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); - - writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); - - writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); - - /* Wait for PLL to lock */ - while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) - ; - - /* Put the PLL in normal mode, disable bypass */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFFB; - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); -} - -static void ddr_pll_bypass_ti816x(void) -{ - u32 ddr_pll_ctrl = 0; - - /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFFFFFFFB; - ddr_pll_ctrl |= BIT(2); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); -} - -static void ddr_pll_init_ti816x(void) -{ - u32 ddr_pll_ctrl = 0; - /* Enable PLL by setting BIT3 in its ctrl reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFFFFFFF7; - ddr_pll_ctrl |= BIT(3); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); - - /* Write the values of N,P in the CTRL reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFF; - ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); - - ddr_delay(10); - - /* Power up clock1-5 */ - writel(0x0, &cmpll->ddrpll_pwd); - - /* Program the freq and divider values for clock1-3 */ - writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); - ddr_delay(1); - writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); - writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), - &cmpll->ddrpll_freq2); - writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); - writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); - ddr_delay(1); - writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); - ddr_delay(1); - writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), - &cmpll->ddrpll_freq3); - ddr_delay(1); - writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), - &cmpll->ddrpll_freq3); - - ddr_delay(5); - - /* Wait for PLL to lock */ - while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) - ; - - /* Power up RCD */ - writel(BIT(0), DDR_RCD); -} - -static void peripheral_enable(void) -{ - /* Wake-up the l3_slow clock */ - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - - /* - * Note on Timers: - * There are 8 timers(0-7) out of which timer 0 is a secure timer. - * Timer 0 mux should not be changed - * - * To access the timer registers we need the to be - * enabled which is what we do in the first step - */ - - /* Enable timer1 */ - writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); - /* Select timer1 clock to be CLKIN (27MHz) */ - writel(BIT(1), CM_TIMER1_CLKSEL); - - /* Wait for timer1 to be ON-ACTIVE */ - while (((readl(&cmalwon->l3slowclkstctrl) - & (0x80000<<1))>>20) != 1) - ; - /* Wait for timer1 to be enabled */ - while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) - ; - /* Active posted mode */ - writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); - while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) - ; - /* Start timer1 */ - writel(BIT(0), (DM_TIMER1_BASE + 0x38)); - - /* eFuse */ - writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); - while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) - ; - - /* Enable gpio0 */ - writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); - while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) - ; - writel((BIT(8)), &cmalwon->gpio0clkctrl); - - /* Enable spi */ - writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); - while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) - ; - - /* Enable i2c0 */ - writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); - while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) - ; - - /* Enable ethernet0 */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - - /* Enable hsmmc */ - writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); - while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) - ; -} - -void setup_clocks_for_console(void) -{ - /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ - writel(0x0, CM_SYSCLK10_CLKSEL); - - ddr_pll_bypass_ti816x(); - - /* Enable uart0-2 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); - while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); - while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) - ; - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -void prcm_init(void) -{ - /* Enable the control */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - main_pll_init_ti816x(); - ddr_pll_init_ti816x(); - - /* - * With clk freqs setup to desired values, - * enable the required peripherals - */ - peripheral_enable(); -} diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk deleted file mode 100644 index 87b76d96a83..00000000000 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk - -ifdef CONFIG_SPL_BUILD -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -# -# For booting from SPI use -# u-boot-spl_HS_SPI_X-LOADER to program flash -# -# On AM43XX: -# -# For booting spl from all other media use -# u-boot-spl_HS_ISSW -# -# On AM33XX: -# -# For booting spl from NAND flash use -# u-boot-spl_HS_X-LOADER -# -# For booting spl from SD/MMC/eMMC media use -# u-boot-spl_HS_MLO -# -# For booting spl over UART, USB, or Ethernet use -# u-boot-spl_HS_2ND -# -# Refer to README.ti-secure for more info -# -ALL-y += u-boot-spl_HS_ISSW -ALL-y += u-boot-spl_HS_SPI_X-LOADER -ALL-y += u-boot-spl_HS_X-LOADER -ALL-y += u-boot-spl_HS_MLO -ALL-y += u-boot-spl_HS_2ND -else -ALL-y += MLO -ALL-y += MLO.byteswap -endif -else -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER -ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img -endif -ALL-y += u-boot.img -endif diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c deleted file mode 100644 index 6acf30c5db0..00000000000 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * DDR Configuration for AM33xx devices. - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/** - * Base address for EMIF instances - */ -static struct emif_reg_struct *emif_reg[2] = { - (struct emif_reg_struct *)EMIF4_0_CFG_BASE, - (struct emif_reg_struct *)EMIF4_1_CFG_BASE}; - -/** - * Base addresses for DDR PHY cmd/data regs - */ -static struct ddr_cmd_regs *ddr_cmd_reg[2] = { - (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR, - (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2}; - -static struct ddr_data_regs *ddr_data_reg[2] = { - (struct ddr_data_regs *)DDR_PHY_DATA_ADDR, - (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2}; - -/** - * Base address for ddr io control instances - */ -static struct ddr_cmdtctrl *ioctrl_reg = { - (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; - -static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) -{ - u32 mr; - - mr_addr |= cs << EMIF_REG_CS_SHIFT; - writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); - - mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); - debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); - if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && - ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && - ((mr & 0xff000000) >> 24) == (mr & 0xff)) - return mr & 0xff; - else - return mr; -} - -static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) -{ - mr_addr |= cs << EMIF_REG_CS_SHIFT; - writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); - writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); -} - -static void configure_mr(int nr, u32 cs) -{ - u32 mr_addr; - - while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) - ; - set_mr(nr, cs, LPDDR2_MR10, 0x56); - - set_mr(nr, cs, LPDDR2_MR1, 0x43); - set_mr(nr, cs, LPDDR2_MR2, 0x2); - - mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; - set_mr(nr, cs, mr_addr, 0x2); -} - -/* - * Configure EMIF4D5 registers and MR registers For details about these magic - * values please see the EMIF registers section of the TRM. - */ -void config_sdram_emif4d5(const struct emif_regs *regs, int nr) -{ - writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); - writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); - writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); - - writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); - writel(regs->emif_rd_wr_lvl_rmp_win, - &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); - writel(regs->emif_rd_wr_lvl_rmp_ctl, - &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); - writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); - writel(regs->emif_rd_wr_exec_thresh, - &emif_reg[nr]->emif_rd_wr_exec_thresh); - - /* - * for most SOCs these registers won't need to be changed so only - * write to these registers if someone explicitly has set the - * register's value. - */ - if(regs->emif_cos_config) { - writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map); - writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map); - writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map); - writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); - } - - /* - * Sequence to ensure that the PHY is in a known state prior to - * startting hardware leveling. Also acts as to latch some state from - * the EMIF into the PHY. - */ - writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); - writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); - writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); - - clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, - EMIF_REG_INITREF_DIS_MASK); - - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - writel(regs->sdram_config, &cstat->secure_emif_sdram_config); - - /* Wait 1ms because of L3 timeout error */ - udelay(1000); - - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); - - /* Perform hardware leveling for DDR3 */ - if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { - writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | - 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); - writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | - 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); - - writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); - - /* Enable read leveling */ - writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); - - /* - * Enable full read and write leveling. Wait for read and write - * leveling bit to clear RDWRLVLFULL_START bit 31 - */ - while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) - != 0) - ; - - /* Check the timeout register to see if leveling is complete */ - if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) - puts("DDR3 H/W leveling incomplete with errors\n"); - - } else { - /* DDR2 */ - configure_mr(nr, 0); - configure_mr(nr, 1); - } -} - -/** - * Configure SDRAM - */ -void config_sdram(const struct emif_regs *regs, int nr) -{ - if (regs->zq_config) { - writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); - writel(regs->sdram_config, &cstat->secure_emif_sdram_config); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - - /* Trigger initialization */ - writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); - /* Wait 1ms because of L3 timeout error */ - udelay(1000); - - /* Write proper sdram_ref_cref_ctrl value */ - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); - } - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); -} - -/** - * Set SDRAM timings - */ -void set_sdram_timings(const struct emif_regs *regs, int nr) -{ - writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); - writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); - writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2); - writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw); - writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3); - writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); -} - -/* - * Configure EXT PHY registers for software leveling - */ -static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr) -{ - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - __maybe_unused const u32 *ext_phy_ctrl_const_regs; - u32 i = 0; - __maybe_unused u32 size; - - ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = - (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); - - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - -#ifdef CONFIG_AM43XX - /* - * External phy 6-24 registers do not change with ddr frequency. - * These only need to be set on DDR2 on AM43xx. - */ - emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); - - if (!size) - return; - - for (i = 0; i < size; i++) { - writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); - } -#endif -} - -/* - * Configure EXT PHY registers for hardware leveling - */ -static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) -{ - /* - * Enable hardware leveling on the EMIF. For details about these - * magic values please see the EMIF registers section of the TRM. - */ - writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); - writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); - writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); - writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw); - writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24); - writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw); - writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25); - writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30); - writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); - writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); - - /* - * Sequence to ensure that the PHY is again in a known state after - * hardware leveling. - */ - writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); - writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); - writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); -} - -/** - * Configure DDR PHY - */ -void config_ddr_phy(const struct emif_regs *regs, int nr) -{ - /* - * Disable initialization and refreshes for now until we finish - * programming EMIF regs and set time between rising edge of - * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec. - * We currently hardcode a value based on a max expected frequency - * of 400MHz. - */ - writel(EMIF_REG_INITREF_DIS_MASK | 0x3100, - &emif_reg[nr]->emif_sdram_ref_ctrl); - - writel(regs->emif_ddr_phy_ctlr_1, - &emif_reg[nr]->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, - &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); - - if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) { - if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) - ext_phy_settings_hwlvl(regs, nr); - else - ext_phy_settings_swlvl(regs, nr); - } -} - -/** - * Configure DDR CMD control registers - */ -void config_cmd_ctrl(const struct cmd_control *cmd, int nr) -{ - if (!cmd) - return; - - writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); - writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); - - writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); - writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); - - writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); - writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); -} - -/** - * Configure DDR DATA registers - */ -void config_ddr_data(const struct ddr_data *data, int nr) -{ - int i; - - if (!data) - return; - - for (i = 0; i < DDR_DATA_REGS_NR; i++) { - writel(data->datardsratio0, - &(ddr_data_reg[nr]+i)->dt0rdsratio0); - writel(data->datawdsratio0, - &(ddr_data_reg[nr]+i)->dt0wdsratio0); - writel(data->datawiratio0, - &(ddr_data_reg[nr]+i)->dt0wiratio0); - writel(data->datagiratio0, - &(ddr_data_reg[nr]+i)->dt0giratio0); - writel(data->datafwsratio0, - &(ddr_data_reg[nr]+i)->dt0fwsratio0); - writel(data->datawrsratio0, - &(ddr_data_reg[nr]+i)->dt0wrsratio0); - } -} - -void config_io_ctrl(const struct ctrl_ioregs *ioregs) -{ - if (!ioregs) - return; - - writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); - writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); - writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); - writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); - writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); -#ifdef CONFIG_AM43XX - writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); - writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); - writel(ioregs->emif_sdram_config_ext, - &ioctrl_reg->emif_sdram_config_ext); -#endif -} diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c deleted file mode 100644 index 27fa3fb4628..00000000000 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * emif4.c - * - * AM33XX emif4 configuration file - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - sdram_init(); -#endif - - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_TI81XX -static struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; -#endif -#ifndef CONFIG_TI816X -static struct vtp_reg *vtpreg[2] = { - (struct vtp_reg *)VTP0_CTRL_ADDR, - (struct vtp_reg *)VTP1_CTRL_ADDR}; -#endif -#ifdef CONFIG_AM33XX -static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; -#endif -#ifdef CONFIG_AM43XX -static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; -static struct cm_device_inst *cm_device = - (struct cm_device_inst *)CM_DEVICE_INST; -#endif - -#ifdef CONFIG_TI81XX -void config_dmm(const struct dmm_lisa_map_regs *regs) -{ - enable_dmm_clocks(); - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); -} -#endif - -#ifndef CONFIG_TI816X -static void config_vtp(int nr) -{ - writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, - &vtpreg[nr]->vtp0ctrlreg); - writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), - &vtpreg[nr]->vtp0ctrlreg); - writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, - &vtpreg[nr]->vtp0ctrlreg); - - /* Poll for READY */ - while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != - VTP_CTRL_READY) - ; -} -#endif - -void __weak ddr_pll_config(unsigned int ddrpll_m) -{ -} - -void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, - const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, int nr) -{ - ddr_pll_config(pll); -#ifndef CONFIG_TI816X - config_vtp(nr); -#endif - config_cmd_ctrl(ctrl, nr); - - config_ddr_data(data, nr); -#ifdef CONFIG_AM33XX - config_io_ctrl(ioregs); - - /* Set CKE to be controlled by EMIF/DDR PHY */ - writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - -#endif -#ifdef CONFIG_AM43XX - writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); - while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) - ; - - config_io_ctrl(ioregs); - - /* Set CKE to be controlled by EMIF/DDR PHY */ - writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - - if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) - /* Allow EMIF to control DDR_RESET */ - writel(0x00000000, &ddrctrl->ddrioctrl); -#endif - - /* Program EMIF instance */ - config_ddr_phy(regs, nr); - set_sdram_timings(regs, nr); - if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) - config_sdram_emif4d5(regs, nr); - else - config_sdram(regs, nr); -} -#endif diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c deleted file mode 100644 index 2ded47228d6..00000000000 --- a/arch/arm/cpu/armv7/am33xx/mux.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * mux.c - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* - * Configure the pin mux for the module - */ -void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux) -{ - int i; - - if (!mod_pin_mux) - return; - - for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) - MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); -} diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c deleted file mode 100644 index f0f72fa6d4d..00000000000 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * sys_info.c - * - * System information functions - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; - -/** - * get_cpu_rev(void) - extract rev info - */ -u32 get_cpu_rev(void) -{ - u32 id; - u32 rev; - - id = readl(DEVICE_ID); - rev = (id >> 28) & 0xff; - - return rev; -} - -/** - * get_cpu_type(void) - extract cpu info - */ -u32 get_cpu_type(void) -{ - u32 id = 0; - u32 partnum; - - id = readl(DEVICE_ID); - partnum = (id >> 12) & 0xffff; - - return partnum; -} - -/** - * get_device_type(): tell if GP/HS/EMU/TST - */ -u32 get_device_type(void) -{ - int mode; - mode = readl(&cstat->statusreg) & (DEVICE_MASK); - return mode >>= 8; -} - -/** - * get_sysboot_value(void) - return SYS_BOOT[4:0] - */ -u32 get_sysboot_value(void) -{ - return readl(&cstat->statusreg) & SYSBOOT_MASK; -} - -#ifdef CONFIG_DISPLAY_CPUINFO -static char *cpu_revs[] = { - "1.0", - "2.0", - "2.1"}; - - -static char *dev_types[] = { - "TST", - "EMU", - "HS", - "GP"}; - -/** - * Print CPU information - */ -int print_cpuinfo(void) -{ - char *cpu_s, *sec_s, *rev_s; - - switch (get_cpu_type()) { - case AM335X: - cpu_s = "AM335X"; - break; - case TI81XX: - cpu_s = "TI81XX"; - break; - case AM437X: - cpu_s = "AM437X"; - break; - default: - cpu_s = "Unknown CPU type"; - break; - } - - if (get_cpu_rev() < ARRAY_SIZE(cpu_revs)) - rev_s = cpu_revs[get_cpu_rev()]; - else - rev_s = "?"; - - if (get_device_type() < ARRAY_SIZE(dev_types)) - sec_s = dev_types[get_device_type()]; - else - sec_s = "?"; - - printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s); - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ - -#ifdef CONFIG_AM33XX -int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) -{ - int sil_rev; - - sil_rev = readl(&cdev->deviceid) >> 28; - - if (sil_rev == 1) - /* PG 2.0, efuse may not be set. */ - return MPUPLL_M_800; - else if (sil_rev >= 2) { - /* Check what the efuse says our max speed is. */ - int efuse_arm_mpu_max_freq; - efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); - switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { - case AM335X_ZCZ_1000: - return MPUPLL_M_1000; - case AM335X_ZCZ_800: - return MPUPLL_M_800; - case AM335X_ZCZ_720: - return MPUPLL_M_720; - case AM335X_ZCZ_600: - case AM335X_ZCE_600: - return MPUPLL_M_600; - case AM335X_ZCZ_300: - case AM335X_ZCE_300: - return MPUPLL_M_300; - } - } - - /* PG 1.0 or otherwise unknown, use the PG1.0 max */ - return MPUPLL_M_720; -} - -int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) -{ - /* For PG2.1 and later, we have one set of values. */ - if (sil_rev >= 2) { - switch (frequency) { - case MPUPLL_M_1000: - return TPS65910_OP_REG_SEL_1_3_2_5; - case MPUPLL_M_800: - return TPS65910_OP_REG_SEL_1_2_6; - case MPUPLL_M_720: - return TPS65910_OP_REG_SEL_1_2_0; - case MPUPLL_M_600: - case MPUPLL_M_300: - return TPS65910_OP_REG_SEL_1_1_3; - } - } - - /* Default to PG1.0/PG2.0 values. */ - return TPS65910_OP_REG_SEL_1_1_3; -} -#endif diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds deleted file mode 100644 index 07cf2678782..00000000000 --- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2010 - * Texas Instruments, - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/armv7/start.o (.text) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig deleted file mode 100644 index 4daccd93ffc..00000000000 --- a/arch/arm/cpu/armv7/omap-common/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config TI_SECURE_DEVICE - bool "HS Device Type Support" - depends on OMAP54XX || AM43XX || AM33XX - help - If a high secure (HS) device type is being used, this config - must be set. This option impacts various aspects of the - build system (to create signed boot images that can be - authenticated) and the code. See the doc/README.ti-secure - file for further details. - -source "arch/arm/cpu/armv7/omap3/Kconfig" - -source "arch/arm/cpu/armv7/omap4/Kconfig" - -source "arch/arm/cpu/armv7/omap5/Kconfig" - -source "arch/arm/cpu/armv7/am33xx/Kconfig" diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile deleted file mode 100644 index 3172bae105b..00000000000 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := reset.o -ifeq ($(CONFIG_TIMER),) -obj-y += timer.o -else -ifdef CONFIG_SPL_BUILD -obj-y += timer.o -endif -endif -obj-y += utils.o - -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) -obj-y += hwinit-common.o -obj-y += clocks-common.o -obj-y += emif-common.o -obj-y += vc.o -obj-y += abb.o -endif - -ifneq ($(CONFIG_OMAP54XX),) -obj-y += pipe3-phy.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o -endif - -ifeq ($(CONFIG_SYS_DCACHE_OFF),) -obj-y += omap-cache.o -endif - -obj-y += boot-common.o -obj-y += lowlevel_init.o - -obj-y += mem-common.o - -obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c deleted file mode 100644 index a0add6643e1..00000000000 --- a/arch/arm/cpu/armv7/omap-common/abb.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Adaptive Body Bias programming sequence for OMAP family - * - * (C) Copyright 2013 - * Texas Instruments, - * - * Andrii Tseglytskyi - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) -{ - return -1; -} - -static void abb_setup_timings(u32 setup) -{ - u32 sys_rate, sr2_cnt, clk_cycles; - - /* - * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a - * transition and must be programmed with the correct time at boot. - * The value programmed into the register is the number of SYS_CLK - * clock cycles that match a given wall time profiled for the ldo. - * This value depends on: - * settling time of ldo in micro-seconds (varies per OMAP family), - * of clock cycles per SYS_CLK period (varies per OMAP family), - * the SYS_CLK frequency in MHz (varies per board) - * The formula is: - * - * ldo settling time (in micro-seconds) - * SR2_WTCNT_VALUE = ------------------------------------------ - * (# system clock cycles) * (sys_clk period) - * - * Put another way: - * - * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate)) - * - * To avoid dividing by zero multiply both "# clock cycles" and - * "settling time" by 10 such that the final result is the one we want. - */ - - /* calculate SR2_WTCNT_VALUE */ - sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000); - clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); - sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); - - setbits_le32(setup, - sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); -} - -void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, - u32 txdone, u32 txdone_mask, u32 opp) -{ - u32 abb_type_mask, opp_sel_mask; - - /* sanity check */ - if (!setup || !control || !txdone) - return; - - /* setup ABB only in case of Fast or Slow OPP */ - switch (opp) { - case OMAP_ABB_FAST_OPP: - abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK; - opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK; - break; - case OMAP_ABB_SLOW_OPP: - abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK; - opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK; - break; - default: - return; - } - - /* - * For some OMAP silicons additional setup for LDOVBB register is - * required. This is determined by data retrieved from corresponding - * OPP EFUSE register. Data, which is retrieved from EFUSE - is - * ABB enable/disable flag and VSET value, which must be copied - * to LDOVBB register. If function call fails - return quietly, - * it means no ABB is required for such silicon. - * - * For silicons, which don't require LDOVBB setup "fuse" and - * "ldovbb" offsets are not defined. ABB will be initialized in - * the common way for them. - */ - if (fuse && ldovbb) { - if (abb_setup_ldovbb(fuse, ldovbb)) - return; - } - - /* clear ABB registers */ - writel(0, setup); - writel(0, control); - - /* configure timings, based on oscillator value */ - abb_setup_timings(setup); - - /* clear pending interrupts before setup */ - setbits_le32(txdone, txdone_mask); - - /* select ABB type */ - setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); - - /* initiate ABB ldo change */ - setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); - - /* wait until transition complete */ - if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY)) - puts("Error: ABB txdone is not set\n"); - - /* clear ABB tranxdone */ - setbits_le32(txdone, txdone_mask); -} diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c deleted file mode 100644 index 385310ba1ec..00000000000 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * boot-common.c - * - * Common bootmode functions for omap based boards - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -__weak u32 omap_sys_boot_device(void) -{ - return BOOT_DEVICE_NONE; -} - -void save_omap_boot_params(void) -{ - u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); - struct omap_boot_parameters *omap_boot_params; - int sys_boot_device = 0; - u32 boot_device; - u32 boot_mode; - - if ((boot_params < NON_SECURE_SRAM_START) || - (boot_params > NON_SECURE_SRAM_END)) - return; - - omap_boot_params = (struct omap_boot_parameters *)boot_params; - - boot_device = omap_boot_params->boot_device; - boot_mode = MMCSD_MODE_UNDEFINED; - - /* Boot device */ - -#ifdef BOOT_DEVICE_NAND_I2C - /* - * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. - * Otherwise the SPL boot IF can't handle this device correctly. - * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens - * Draco leads to this boot-device passed to SPL from the BootROM. - */ - if (boot_device == BOOT_DEVICE_NAND_I2C) - boot_device = BOOT_DEVICE_NAND; -#endif -#ifdef BOOT_DEVICE_QSPI_4 - /* - * We get different values for QSPI_1 and QSPI_4 being used, but - * don't actually care about this difference. Rather than - * mangle the later code, if we're coming in as QSPI_4 just - * change to the QSPI_1 value. - */ - if (boot_device == BOOT_DEVICE_QSPI_4) - boot_device = BOOT_DEVICE_SPI; -#endif - /* - * When booting from peripheral booting, the boot device is not usable - * as-is (unless there is support for it), so the boot device is instead - * figured out using the SYS_BOOT pins. - */ - switch (boot_device) { -#if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT) - case BOOT_DEVICE_UART: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT) - case BOOT_DEVICE_USB: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT) - case BOOT_DEVICE_USBETH: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT) - case BOOT_DEVICE_CPGMAC: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT) - case BOOT_DEVICE_DFU: - sys_boot_device = 1; - break; -#endif - } - - if (sys_boot_device) { - boot_device = omap_sys_boot_device(); - - /* MMC raw mode will fallback to FS mode. */ - if ((boot_device >= MMC_BOOT_DEVICES_START) && - (boot_device <= MMC_BOOT_DEVICES_END)) - boot_mode = MMCSD_MODE_RAW; - } - - gd->arch.omap_boot_device = boot_device; - - /* Boot mode */ - -#ifdef CONFIG_OMAP34XX - if ((boot_device >= MMC_BOOT_DEVICES_START) && - (boot_device <= MMC_BOOT_DEVICES_END)) { - switch (boot_device) { - case BOOT_DEVICE_MMC1: - boot_mode = MMCSD_MODE_FS; - break; - case BOOT_DEVICE_MMC2: - boot_mode = MMCSD_MODE_RAW; - break; - } - } -#else - /* - * If the boot device was dynamically changed and doesn't match what - * the bootrom initially booted, we cannot use the boot device - * descriptor to figure out the boot mode. - */ - if ((boot_device == omap_boot_params->boot_device) && - (boot_device >= MMC_BOOT_DEVICES_START) && - (boot_device <= MMC_BOOT_DEVICES_END)) { - boot_params = omap_boot_params->boot_device_descriptor; - if ((boot_params < NON_SECURE_SRAM_START) || - (boot_params > NON_SECURE_SRAM_END)) - return; - - boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET)); - if ((boot_params < NON_SECURE_SRAM_START) || - (boot_params > NON_SECURE_SRAM_END)) - return; - - boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET)); - - if (boot_mode != MMCSD_MODE_FS && - boot_mode != MMCSD_MODE_RAW) -#ifdef CONFIG_SUPPORT_EMMC_BOOT - boot_mode = MMCSD_MODE_EMMCBOOT; -#else - boot_mode = MMCSD_MODE_UNDEFINED; -#endif - } -#endif - - gd->arch.omap_boot_mode = boot_mode; - -#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ - !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) - - /* CH flags */ - - gd->arch.omap_ch_flags = omap_boot_params->ch_flags; -#endif -} - -#ifdef CONFIG_SPL_BUILD -u32 spl_boot_device(void) -{ - return gd->arch.omap_boot_device; -} - -u32 spl_boot_mode(const u32 boot_device) -{ - return gd->arch.omap_boot_mode; -} - -void spl_board_init(void) -{ - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ - save_omap_boot_params(); - - /* Prepare console output */ - preloader_console_init(); - -#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) - gpmc_init(); -#endif -#ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif -#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) - arch_misc_init(); -#endif -#if defined(CONFIG_HW_WATCHDOG) - hw_watchdog_init(); -#endif -#ifdef CONFIG_AM33XX - am33xx_spl_board_init(); -#endif -} - -__weak int board_mmc_init(bd_t *bis) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1, -1); - break; - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - omap_mmc_init(0, 0, 0, -1, -1); - omap_mmc_init(1, 0, 0, -1, -1); - break; - } - return 0; -} - -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - typedef void __noreturn (*image_entry_noargs_t)(u32 *); - image_entry_noargs_t image_entry = - (image_entry_noargs_t) spl_image->entry_point; - - u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); - - debug("image entry point: 0x%X\n", spl_image->entry_point); - /* Pass the saved boot_params from rom code */ - image_entry((u32 *)boot_params); -} -#endif - -#ifdef CONFIG_SCSI_AHCI_PLAT -void arch_preboot_os(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); -} -#endif - -#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE) -int fb_set_reboot_flag(void) -{ - printf("Setting reboot to fastboot flag ...\n"); - setenv("dofastboot", "1"); - saveenv(); - return 0; -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c deleted file mode 100644 index 9b975831046..00000000000 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ /dev/null @@ -1,892 +0,0 @@ -/* - * - * Clock initialization for OMAP4 - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * - * Based on previous work by: - * Santosh Shilimkar - * Rajendra Nayak - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif - -const u32 sys_clk_array[8] = { - 12000000, /* 12 MHz */ - 20000000, /* 20 MHz */ - 16800000, /* 16.8 MHz */ - 19200000, /* 19.2 MHz */ - 26000000, /* 26 MHz */ - 27000000, /* 27 MHz */ - 38400000, /* 38.4 MHz */ -}; - -static inline u32 __get_sys_clk_index(void) -{ - s8 ind; - /* - * For ES1 the ROM code calibration of sys clock is not reliable - * due to hw issue. So, use hard-coded value. If this value is not - * correct for any board over-ride this function in board file - * From ES2.0 onwards you will get this information from - * CM_SYS_CLKSEL - */ - if (omap_revision() == OMAP4430_ES1_0) - ind = OMAP_SYS_CLK_IND_38_4_MHZ; - else { - /* SYS_CLKSEL - 1 to match the dpll param array indices */ - ind = (readl((*prcm)->cm_sys_clksel) & - CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; - } - return ind; -} - -u32 get_sys_clk_index(void) - __attribute__ ((weak, alias("__get_sys_clk_index"))); - -u32 get_sys_clk_freq(void) -{ - u8 index = get_sys_clk_index(); - return sys_clk_array[index]; -} - -void setup_post_dividers(u32 const base, const struct dpll_params *params) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, &dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, &dpll_regs->cm_div_m3_dpll); - if (params->m4_h11 >= 0) - writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); - if (params->m5_h12 >= 0) - writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); - if (params->m6_h13 >= 0) - writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); - if (params->m7_h14 >= 0) - writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); - if (params->h21 >= 0) - writel(params->h21, &dpll_regs->cm_div_h21_dpll); - if (params->h22 >= 0) - writel(params->h22, &dpll_regs->cm_div_h22_dpll); - if (params->h23 >= 0) - writel(params->h23, &dpll_regs->cm_div_h23_dpll); - if (params->h24 >= 0) - writel(params->h24, &dpll_regs->cm_div_h24_dpll); -} - -static inline void do_bypass_dpll(u32 const base) -{ - struct dpll_regs *dpll_regs = (struct dpll_regs *)base; - - clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_FAST_RELOCK_BYPASS << - CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_bypass(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, - LDELAY)) { - printf("Bypassing DPLL failed %x\n", base); - } -} - -static inline void do_lock_dpll(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_lock(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, - &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("DPLL locking failed for %x\n", base); - hang(); - } -} - -inline u32 check_for_lock(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; - - return lock; -} - -const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->mpu[sysclk_ind]; -} - -const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->core[sysclk_ind]; -} - -const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->per[sysclk_ind]; -} - -const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->iva[sysclk_ind]; -} - -const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->usb[sysclk_ind]; -} - -const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) -{ -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->abe[sysclk_ind]; -#else - return dpll_data->abe; -#endif -} - -static const struct dpll_params *get_ddr_dpll_params - (struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - - if (!dpll_data->ddr) - return NULL; - return &dpll_data->ddr[sysclk_ind]; -} - -#ifdef CONFIG_DRIVER_TI_CPSW -static const struct dpll_params *get_gmac_dpll_params - (struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - - if (!dpll_data->gmac) - return NULL; - return &dpll_data->gmac[sysclk_ind]; -} -#endif - -static void do_setup_dpll(u32 const base, const struct dpll_params *params, - u8 lock, char *dpll) -{ - u32 temp, M, N; - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!params) - return; - - temp = readl(&dpll_regs->cm_clksel_dpll); - - if (check_for_lock(base)) { - /* - * The Dpll has already been locked by rom code using CH. - * Check if M,N are matching with Ideal nominal opp values. - * If matches, skip the rest otherwise relock. - */ - M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; - N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT; - if ((M != (params->m)) || (N != (params->n))) { - debug("\n %s Dpll locked, but not for ideal M = %d," - "N = %d values, current values are M = %d," - "N= %d" , dpll, params->m, params->n, - M, N); - } else { - /* Dpll locked with ideal values for nominal opps. */ - debug("\n %s Dpll already locked with ideal" - "nominal opp values", dpll); - - bypass_dpll(base); - goto setup_post_dividers; - } - } - - bypass_dpll(base); - - /* Set M & N */ - temp &= ~CM_CLKSEL_DPLL_M_MASK; - temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; - - temp &= ~CM_CLKSEL_DPLL_N_MASK; - temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; - - writel(temp, &dpll_regs->cm_clksel_dpll); - -setup_post_dividers: - setup_post_dividers(base, params); - - /* Lock */ - if (lock) - do_lock_dpll(base); - - /* Wait till the DPLL locks */ - if (lock) - wait_for_lock(base); -} - -u32 omap_ddr_clk(void) -{ - u32 ddr_clk, sys_clk_khz, omap_rev, divider; - const struct dpll_params *core_dpll_params; - - omap_rev = omap_revision(); - sys_clk_khz = get_sys_clk_freq() / 1000; - - core_dpll_params = get_core_dpll_params(*dplls_data); - - debug("sys_clk %d\n ", sys_clk_khz * 1000); - - /* Find Core DPLL locked frequency first */ - ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / - (core_dpll_params->n + 1); - - if (omap_rev < OMAP5430_ES1_0) { - /* - * DDR frequency is PHY_ROOT_CLK/2 - * PHY_ROOT_CLK = Fdpll/2/M2 - */ - divider = 4; - } else { - /* - * DDR frequency is PHY_ROOT_CLK - * PHY_ROOT_CLK = Fdpll/2/M2 - */ - divider = 2; - } - - ddr_clk = ddr_clk / divider / core_dpll_params->m2; - ddr_clk *= 1000; /* convert to Hz */ - debug("ddr_clk %d\n ", ddr_clk); - - return ddr_clk; -} - -/* - * Lock MPU dpll - * - * Resulting MPU frequencies: - * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled - */ -void configure_mpu_dpll(void) -{ - const struct dpll_params *params; - struct dpll_regs *mpu_dpll_regs; - u32 omap_rev; - omap_rev = omap_revision(); - - /* - * DCC and clock divider settings for 4460. - * DCC is required, if more than a certain frequency is required. - * For, 4460 > 1GHZ. - * 5430 > 1.4GHZ. - */ - if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { - mpu_dpll_regs = - (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); - bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); - clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); - clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, - CM_CLKSEL_DCC_EN_MASK); - } - - params = get_mpu_dpll_params(*dplls_data); - - do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); - debug("MPU DPLL locked\n"); -} - -#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) -static void setup_usb_dpll(void) -{ - const struct dpll_params *params; - u32 sys_clk_khz, sd_div, num, den; - - sys_clk_khz = get_sys_clk_freq() / 1000; - /* - * USB: - * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction - * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) - * - where CLKINP is sys_clk in MHz - * Use CLKINP in KHz and adjust the denominator accordingly so - * that we have enough accuracy and at the same time no overflow - */ - params = get_usb_dpll_params(*dplls_data); - num = params->m * sys_clk_khz; - den = (params->n + 1) * 250 * 1000; - num += den - 1; - sd_div = num / den; - clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, - CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, - sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); - - /* Now setup the dpll with the regular function */ - do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); -} -#endif - -static void setup_dplls(void) -{ - u32 temp; - const struct dpll_params *params; - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - debug("setup_dplls\n"); - - /* CORE dpll */ - params = get_core_dpll_params(*dplls_data); /* default - safest */ - /* - * Do not lock the core DPLL now. Just set it up. - * Core DPLL will be locked after setting up EMIF - * using the FREQ_UPDATE method(freq_update_core()) - */ - if (emif_sdram_type(readl(&emif->emif_sdram_config)) == - EMIF_SDRAM_TYPE_LPDDR2) - do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, - DPLL_NO_LOCK, "core"); - else - do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, - DPLL_LOCK, "core"); - /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ - temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | - (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | - (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); - writel(temp, (*prcm)->cm_clksel_core); - debug("Core DPLL configured\n"); - - /* lock PER dpll */ - params = get_per_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_per, - params, DPLL_LOCK, "per"); - debug("PER DPLL locked\n"); - - /* MPU dpll */ - configure_mpu_dpll(); - -#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) - setup_usb_dpll(); -#endif - params = get_ddr_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, - params, DPLL_LOCK, "ddr"); - -#ifdef CONFIG_DRIVER_TI_CPSW - params = get_gmac_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, - DPLL_LOCK, "gmac"); -#endif -} - -u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) -{ - u32 offset_code; - - volt_offset -= pmic->base_offset; - - offset_code = (volt_offset + pmic->step - 1) / pmic->step; - - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - return offset_code + pmic->start_code; -} - -void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) -{ - u32 offset_code; - u32 offset = volt_mv; - int ret = 0; - - if (!volt_mv) - return; - - pmic->pmic_bus_init(); - /* See if we can first get the GPIO if needed */ - if (pmic->gpio_en) - ret = gpio_request(pmic->gpio, "PMIC_GPIO"); - - if (ret < 0) { - printf("%s: gpio %d request failed %d\n", __func__, - pmic->gpio, ret); - return; - } - - /* Pull the GPIO low to select SET0 register, while we program SET1 */ - if (pmic->gpio_en) - gpio_direction_output(pmic->gpio, 0); - - /* convert to uV for better accuracy in the calculations */ - offset *= 1000; - - offset_code = get_offset_code(offset, pmic); - - debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, - offset_code); - - if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) - printf("Scaling voltage failed for 0x%x\n", vcore_reg); - if (pmic->gpio_en) - gpio_direction_output(pmic->gpio, 1); -} - -static u32 optimize_vcore_voltage(struct volts const *v) -{ - u32 val; - if (!v->value) - return 0; - if (!v->efuse.reg) - return v->value; - - switch (v->efuse.reg_bits) { - case 16: - val = readw(v->efuse.reg); - break; - case 32: - val = readl(v->efuse.reg); - break; - default: - printf("Error: efuse 0x%08x bits=%d unknown\n", - v->efuse.reg, v->efuse.reg_bits); - return v->value; - } - - if (!val) { - printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", - v->efuse.reg, v->efuse.reg_bits, v->value); - return v->value; - } - - debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", - __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); - return val; -} - -#ifdef CONFIG_IODELAY_RECALIBRATION -void __weak recalibrate_iodelay(void) -{ -} -#endif - -/* - * Setup the voltages for the main SoC core power domains. - * We start with the maximum voltages allowed here, as set in the corresponding - * vcores_data struct, and then scale (usually down) to the fused values that - * are retrieved from the SoC. The scaling happens only if the efuse.reg fields - * are initialised. - * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is - * compiled conditionally. Note that the new code writes the scaled (or zeroed) - * values back to the vcores_data struct for eventual reuse. Zero values mean - * that the corresponding rails are not controlled separately, and are not sent - * to the PMIC. - */ -void scale_vcores(struct vcores_data const *vcores) -{ - int i; - struct volts *pv = (struct volts *)vcores; - struct volts *px; - - for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) { - debug("%d -> ", pv->value); - if (pv->value) { - /* Handle non-empty members only */ - pv->value = optimize_vcore_voltage(pv); - px = (struct volts *)vcores; - while (px < pv) { - /* - * Scan already handled non-empty members to see - * if we have a group and find the max voltage, - * which is set to the first occurance of the - * particular SMPS; the other group voltages are - * zeroed. - */ - if (px->value) { - if ((pv->pmic->i2c_slave_addr == - px->pmic->i2c_slave_addr) && - (pv->addr == px->addr)) { - /* Same PMIC, same SMPS */ - if (pv->value > px->value) - px->value = pv->value; - - pv->value = 0; - } - } - px++; - } - } - debug("%d\n", pv->value); - pv++; - } - - debug("cor: %d\n", vcores->core.value); - do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); - /* - * IO delay recalibration should be done immediately after - * adjusting AVS voltages for VDD_CORE_L. - * Respective boards should call __recalibrate_iodelay() - * with proper mux, virtual and manual mode configurations. - */ -#ifdef CONFIG_IODELAY_RECALIBRATION - recalibrate_iodelay(); -#endif - - debug("mpu: %d\n", vcores->mpu.value); - do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); - /* Configure MPU ABB LDO after scale */ - abb_setup(vcores->mpu.efuse.reg, - (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, - (*prcm)->prm_abbldo_mpu_setup, - (*prcm)->prm_abbldo_mpu_ctrl, - (*prcm)->prm_irqstatus_mpu_2, - vcores->mpu.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - - debug("mm: %d\n", vcores->mm.value); - do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); - /* Configure MM ABB LDO after scale */ - abb_setup(vcores->mm.efuse.reg, - (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl, - (*prcm)->prm_abbldo_mm_setup, - (*prcm)->prm_abbldo_mm_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->mm.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - - debug("gpu: %d\n", vcores->gpu.value); - do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic); - /* Configure GPU ABB LDO after scale */ - abb_setup(vcores->gpu.efuse.reg, - (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl, - (*prcm)->prm_abbldo_gpu_setup, - (*prcm)->prm_abbldo_gpu_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->gpu.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - debug("eve: %d\n", vcores->eve.value); - do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic); - /* Configure EVE ABB LDO after scale */ - abb_setup(vcores->eve.efuse.reg, - (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl, - (*prcm)->prm_abbldo_eve_setup, - (*prcm)->prm_abbldo_eve_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->eve.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - debug("iva: %d\n", vcores->iva.value); - do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic); - /* Configure IVA ABB LDO after scale */ - abb_setup(vcores->iva.efuse.reg, - (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl, - (*prcm)->prm_abbldo_iva_setup, - (*prcm)->prm_abbldo_iva_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->iva.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); -} - -static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Enable clock domain - %x\n", clkctrl_reg); -} - -static inline void disable_clock_domain(u32 const clkctrl_reg) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Disable clock domain - %x\n", clkctrl_reg); -} - -static inline void wait_for_clk_enable(u32 clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; - u32 bound = LDELAY; - - while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || - (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { - - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock enable failed for 0x%x idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} - -static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, - u32 wait_for_enable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Enable clock module - %x\n", clkctrl_addr); - if (wait_for_enable) - wait_for_clk_enable(clkctrl_addr); -} - -static inline void wait_for_clk_disable(u32 clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; - u32 bound = LDELAY; - - while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) { - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock disable failed for 0x%x idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} - -static inline void disable_clock_module(u32 const clkctrl_addr, - u32 wait_for_disable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Disable clock module - %x\n", clkctrl_addr); - if (wait_for_disable) - wait_for_clk_disable(clkctrl_addr); -} - -void freq_update_core(void) -{ - u32 freq_config1 = 0; - const struct dpll_params *core_dpll_params; - u32 omap_rev = omap_revision(); - - core_dpll_params = get_core_dpll_params(*dplls_data); - /* Put EMIF clock domain in sw wakeup mode */ - enable_clock_domain((*prcm)->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); - wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); - - freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | - SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; - - freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & - SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; - - freq_config1 |= (core_dpll_params->m2 << - SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & - SHADOW_FREQ_CONFIG1_M2_DIV_MASK; - - writel(freq_config1, (*prcm)->cm_shadow_freq_config1); - if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, - (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { - puts("FREQ UPDATE procedure failed!!"); - hang(); - } - - /* - * Putting EMIF in HW_AUTO is seen to be causing issues with - * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP - * in OMAP5430 ES1.0 silicon - */ - if (omap_rev != OMAP5430_ES1_0) { - /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain((*prcm)->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); - wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); - } -} - -void bypass_dpll(u32 const base) -{ - do_bypass_dpll(base); - wait_for_bypass(base); -} - -void lock_dpll(u32 const base) -{ - do_lock_dpll(base); - wait_for_lock(base); -} - -static void setup_clocks_for_console(void) -{ - /* Do not add any spl_debug prints in this function */ - clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - - /* Enable all UARTs - console will be on one of them */ - clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO << - CD_CLKCTRL_CLKTRCTRL_SHIFT); -} - -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable) -{ - u32 i, max = 100; - - /* Put the clock domains in SW_WKUP mode */ - for (i = 0; (i < max) && clk_domains[i]; i++) { - enable_clock_domain(clk_domains[i], - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - } - - /* Clock modules that need to be put in HW_AUTO */ - for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) { - enable_clock_module(clk_modules_hw_auto[i], - MODULE_CLKCTRL_MODULEMODE_HW_AUTO, - wait_for_enable); - }; - - /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ - for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { - enable_clock_module(clk_modules_explicit_en[i], - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, - wait_for_enable); - }; - - /* Put the clock domains in HW_AUTO mode now */ - for (i = 0; (i < max) && clk_domains[i]; i++) { - enable_clock_domain(clk_domains[i], - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - } -} - -void do_disable_clocks(u32 const *clk_domains, - u32 const *clk_modules_disable, - u8 wait_for_disable) -{ - u32 i, max = 100; - - - /* Clock modules that need to be put in SW_DISABLE */ - for (i = 0; (i < max) && clk_modules_disable[i]; i++) - disable_clock_module(clk_modules_disable[i], - wait_for_disable); - - /* Put the clock domains in SW_SLEEP mode */ - for (i = 0; (i < max) && clk_domains[i]; i++) - disable_clock_domain(clk_domains[i]); -} - -/** - * setup_early_clocks() - Setup early clocks needed for SoC - * - * Setup clocks for console, SPL basic initialization clocks and initialize - * the timer. This is invoked prior prcm_init. - */ -void setup_early_clocks(void) -{ - switch (omap_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - setup_clocks_for_console(); - enable_basic_clocks(); - timer_init(); - /* Fall through */ - } -} - -void prcm_init(void) -{ - switch (omap_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - scale_vcores(*omap_vcores); - setup_dplls(); - setup_warmreset_time(); - break; - default: - break; - } - - if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) - enable_basic_uboot_clocks(); -} - -void gpi2c_init(void) -{ - static int gpi2c = 1; - - if (gpi2c) { - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE); - gpi2c = 0; - } -} diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk deleted file mode 100644 index 1122439e38b..00000000000 --- a/arch/arm/cpu/armv7/omap-common/config_secure.mk +++ /dev/null @@ -1,113 +0,0 @@ -# -# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# -quiet_cmd_mkomapsecimg = MKIMAGE $@ -ifneq ($(TI_SECURE_DEV_PKG),) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) -ifneq ($(CONFIG_SPL_BUILD),) -cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ - $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -else -cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ - $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -endif -else -cmd_mkomapsecimg = echo "WARNING:" \ - "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \ - "$@ was NOT created!" -endif -else -cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ - "variable must be defined for TI secure devices. $@ was NOT created!" -endif - -ifdef CONFIG_SPL_LOAD_FIT -quiet_cmd_omapsecureimg = SECURE $@ -ifneq ($(TI_SECURE_DEV_PKG),) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),) -cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \ - $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -else -cmd_omapsecureimg = echo "WARNING:" \ - "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \ - "$@ was NOT created!"; cp $< $@ -endif -else -cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ - "variable must be defined for TI secure devices." \ - "$@ was NOT created!"; cp $< $@ -endif -endif - - -# Standard X-LOADER target (QPSI, NOR flash) -u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# For MLO targets (SD card boot) the final file name that is copied to the SD -# card FAT partition must be MLO, so we make a copy of the output file to a new -# file with that name -u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - @if [ -f $@ ]; then \ - cp -f $@ MLO; \ - fi - -# Standard 2ND target (certain peripheral boot modes) -u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# Standard ULO target (certain peripheral boot modes) -u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# Standard ISSW target (certain devices, various boot modes) -u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# For SPI flash on AM335x and AM43xx, these require special byte swap handling -# so we use the SPI_X-LOADER target instead of X-LOADER and let the -# create-boot-image.sh script handle that -u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot -# file, not an SPL. In this case the mkomapsecimg command looks for a -# u-boot-HS_* prefix -u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin - $(call if_changed,mkomapsecimg) - -# For supporting the SPL loading and interpreting of FIT images whose -# components are pre-processed before being integrated into the FIT image in -# order to secure them in some way -ifdef CONFIG_SPL_LOAD_FIT - -MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ - -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) - -OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -$(OF_LIST_TARGETS): dtbs - -%_HS.dtb: %.dtb - $(call if_changed,omapsecureimg) - $(Q)if [ -f $@ ]; then \ - cp -f $@ $<; \ - fi - -u-boot-nodtb_HS.bin: u-boot-nodtb.bin - $(call if_changed,omapsecureimg) - -u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS)) - $(call if_changed,mkimage) - $(Q)if [ -f $@ ]; then \ - cp -f $@ u-boot.img; \ - fi - -endif diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c deleted file mode 100644 index b26984e26c5..00000000000 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ /dev/null @@ -1,1504 +0,0 @@ -/* - * EMIF programming - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static int emif1_enabled = -1, emif2_enabled = -1; - -void set_lpmode_selfrefresh(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 reg; - - reg = readl(&emif->emif_pwr_mgmt_ctrl); - reg &= ~EMIF_REG_LP_MODE_MASK; - reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; - reg &= ~EMIF_REG_SR_TIM_MASK; - writel(reg, &emif->emif_pwr_mgmt_ctrl); - - /* dummy read for the new SR_TIM to be loaded */ - readl(&emif->emif_pwr_mgmt_ctrl); -} - -void force_emif_self_refresh() -{ - set_lpmode_selfrefresh(EMIF1_BASE); - if (!is_dra72x()) - set_lpmode_selfrefresh(EMIF2_BASE); -} - -inline u32 emif_num(u32 base) -{ - if (base == EMIF1_BASE) - return 1; - else if (base == EMIF2_BASE) - return 2; - else - return 0; -} - -static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) -{ - u32 mr; - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - mr_addr |= cs << EMIF_REG_CS_SHIFT; - writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); - if (omap_revision() == OMAP4430_ES2_0) - mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); - else - mr = readl(&emif->emif_lpddr2_mode_reg_data); - debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), - cs, mr_addr, mr); - if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && - ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && - ((mr & 0xff000000) >> 24) == (mr & 0xff)) - return mr & 0xff; - else - return mr; -} - -static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - mr_addr |= cs << EMIF_REG_CS_SHIFT; - writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); - writel(mr_val, &emif->emif_lpddr2_mode_reg_data); -} - -void emif_reset_phy(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 iodft; - - iodft = readl(&emif->emif_iodft_tlgc); - iodft |= EMIF_REG_RESET_PHY_MASK; - writel(iodft, &emif->emif_iodft_tlgc); -} - -static void do_lpddr2_init(u32 base, u32 cs) -{ - u32 mr_addr; - const struct lpddr2_mr_regs *mr_regs; - - get_lpddr2_mr_regs(&mr_regs); - /* Wait till device auto initialization is complete */ - while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) - ; - set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); - /* - * tZQINIT = 1 us - * Enough loops assuming a maximum of 2GHz - */ - - sdelay(2000); - - set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); - set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); - - /* - * Enable refresh along with writing MR2 - * Encoding of RL in MR2 is (RL - 2) - */ - mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; - set_mr(base, cs, mr_addr, mr_regs->mr2); - - if (mr_regs->mr3 > 0) - set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); -} - -static void lpddr2_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* Not NVM */ - clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); - - /* - * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM - * when EMIF_SDRAM_CONFIG register is written - */ - setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); - - /* - * Set the SDRAM_CONFIG and PHY_CTRL for the - * un-locked frequency & default RL - */ - writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - - do_ext_phy_settings(base, regs); - - do_lpddr2_init(base, CS0); - if (regs->sdram_config & EMIF_REG_EBANK_MASK) - do_lpddr2_init(base, CS1); - - writel(regs->sdram_config, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - - /* Enable refresh now */ - clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); - - } - -__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) -{ -} - -void emif_update_timings(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (!is_dra7xx()) - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); - else - writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); - - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); - if (omap_revision() == OMAP4430_ES1_0) { - /* ES1 bug EMIF should be in force idle during freq_update */ - writel(0, &emif->emif_pwr_mgmt_ctrl); - } else { - writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); - writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); - } - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); - writel(regs->zq_config, &emif->emif_zq_config); - writel(regs->temp_alert_config, &emif->emif_temp_alert_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - - if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, - &emif->emif_l3_config); - } else if (omap_revision() >= OMAP4460_ES1_0) { - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, - &emif->emif_l3_config); - } else { - writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, - &emif->emif_l3_config); - } -} - -#ifndef CONFIG_OMAP44XX -static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* keep sdram in self-refresh */ - writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); - __udelay(130); - - /* - * Set invert_clkout (if activated)--DDR_PHYCTRL_1 - * Invert clock adds an additional half cycle delay on the - * command interface. The additional half cycle, is usually - * meant to enable leveling in the situation that DQS is later - * than CK on the board.It also helps provide some additional - * margin for leveling. - */ - writel(regs->emif_ddr_phy_ctlr_1, - &emif->emif_ddr_phy_ctrl_1); - - writel(regs->emif_ddr_phy_ctlr_1, - &emif->emif_ddr_phy_ctrl_1_shdw); - __udelay(130); - - writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); - - /* Launch Full leveling */ - writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); - - /* Wait till full leveling is complete */ - readl(&emif->emif_rd_wr_lvl_ctl); - __udelay(130); - - /* Read data eye leveling no of samples */ - config_data_eye_leveling_samples(base); - - /* - * Launch 8 incremental WR_LVL- to compensate for - * PHY limitation. - */ - writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, - &emif->emif_rd_wr_lvl_ctl); - - __udelay(130); - - /* Launch Incremental leveling */ - writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); - __udelay(130); -} - -static void update_hwleveling_output(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; - u32 reg, i, phy; - - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; - phy = readl(&emif->emif_ddr_phy_ctrl_1); - - /* Update PHY_REG_RDDQS_RATIO */ - emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; - if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) - for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } - - /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ - emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; - if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) - for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } - - /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ - emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; - if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) - for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } - - /* Disable Leveling */ - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); -} - -static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* Clear Error Status */ - clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); - - clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); - - /* Disable refreshed before leveling */ - clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, - EMIF_REG_INITREF_DIS_MASK); - - /* Start Full leveling */ - writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); - - __udelay(300); - - /* Check for leveling timeout */ - if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { - printf("Leveling timeout on EMIF%d\n", emif_num(base)); - return; - } - - /* Enable refreshes after leveling */ - clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); - - debug("HW leveling success\n"); - /* - * Update slave ratios in EXT_PHY_CTRLx registers - * as per HW leveling output - */ - update_hwleveling_output(base, regs); -} - -static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (warm_reset()) { - emif_reset_phy(base); - writel(0x0, &emif->emif_pwr_mgmt_ctrl); - } - do_ext_phy_settings(base, regs); - - writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, - &emif->emif_sdram_ref_ctrl); - /* Update timing registers */ - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); - - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - writel(regs->zq_config, &emif->emif_zq_config); - writel(regs->temp_alert_config, &emif->emif_temp_alert_config); - writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); - - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); - - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); - - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - - __udelay(1000); - - writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); - - if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) - dra7_ddr3_leveling(base, regs); -} - -static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - /* - * Set SDRAM_CONFIG and PHY control registers to locked frequency - * and RL =7. As the default values of the Mode Registers are not - * defined, contents of mode Registers must be fully initialized. - * H/W takes care of this initialization - */ - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - - /* Update timing registers */ - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); - - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - do_ext_phy_settings(base, regs); - - writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - omap5_ddr3_leveling(base, regs); -} - -static void ddr3_init(u32 base, const struct emif_regs *regs) -{ - if (is_omap54xx()) - omap5_ddr3_init(base, regs); - else - dra7_ddr3_init(base, regs); -} -#endif - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) - -/* - * Organization and refresh requirements for LPDDR2 devices of different - * types and densities. Derived from JESD209-2 section 2.4 - */ -const struct lpddr2_addressing addressing_table[] = { - /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ - {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ - {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ - {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ - {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ - {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ - {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ - {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ - {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ - {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ - {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ -}; - -static const u32 lpddr2_density_2_size_in_mbytes[] = { - 8, /* 64Mb */ - 16, /* 128Mb */ - 32, /* 256Mb */ - 64, /* 512Mb */ - 128, /* 1Gb */ - 256, /* 2Gb */ - 512, /* 4Gb */ - 1024, /* 8Gb */ - 2048, /* 16Gb */ - 4096 /* 32Gb */ -}; - -/* - * Calculate the period of DDR clock from frequency value and set the - * denominator and numerator in global variables for easy access later - */ -static void set_ddr_clk_period(u32 freq) -{ - /* - * period = 1/freq - * period_in_ns = 10^9/freq - */ - *T_num = 1000000000; - *T_den = freq; - cancel_out(T_num, T_den, 200); - -} - -/* - * Convert time in nano seconds to number of cycles of DDR clock - */ -static inline u32 ns_2_cycles(u32 ns) -{ - return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); -} - -/* - * ns_2_cycles with the difference that the time passed is 2 times the actual - * value(to avoid fractions). The cycles returned is for the original value of - * the timing parameter - */ -static inline u32 ns_x2_2_cycles(u32 ns) -{ - return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); -} - -/* - * Find addressing table index based on the device's type(S2 or S4) and - * density - */ -s8 addressing_table_index(u8 type, u8 density, u8 width) -{ - u8 index; - if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) - return -1; - - /* - * Look at the way ADDR_TABLE_INDEX* values have been defined - * in emif.h compared to LPDDR2_DENSITY_* values - * The table is layed out in the increasing order of density - * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed - * at the end - */ - if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) - index = ADDR_TABLE_INDEX1GS2; - else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) - index = ADDR_TABLE_INDEX2GS2; - else - index = density; - - debug("emif: addressing table index %d\n", index); - - return index; -} - -/* - * Find the the right timing table from the array of timing - * tables of the device using DDR clock frequency - */ -static const struct lpddr2_ac_timings *get_timings_table(const struct - lpddr2_ac_timings const *const *device_timings, - u32 freq) -{ - u32 i, temp, freq_nearest; - const struct lpddr2_ac_timings *timings = 0; - - emif_assert(freq <= MAX_LPDDR2_FREQ); - emif_assert(device_timings); - - /* - * Start with the maximum allowed frequency - that is always safe - */ - freq_nearest = MAX_LPDDR2_FREQ; - /* - * Find the timings table that has the max frequency value: - * i. Above or equal to the DDR frequency - safe - * ii. The lowest that satisfies condition (i) - optimal - */ - for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { - temp = device_timings[i]->max_freq; - if ((temp >= freq) && (temp <= freq_nearest)) { - freq_nearest = temp; - timings = device_timings[i]; - } - } - debug("emif: timings table: %d\n", freq_nearest); - return timings; -} - -/* - * Finds the value of emif_sdram_config_reg - * All parameters are programmed based on the device on CS0. - * If there is a device on CS1, it will be same as that on CS0 or - * it will be NVM. We don't support NVM yet. - * If cs1_device pointer is NULL it is assumed that there is no device - * on CS1 - */ -static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, - const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 RL) -{ - u32 config_reg = 0; - - config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; - config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << - EMIF_REG_IBANK_POS_SHIFT; - - config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; - - config_reg |= RL << EMIF_REG_CL_SHIFT; - - config_reg |= addressing->row_sz[cs0_device->io_width] << - EMIF_REG_ROWSIZE_SHIFT; - - config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; - - config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << - EMIF_REG_EBANK_SHIFT; - - config_reg |= addressing->col_sz[cs0_device->io_width] << - EMIF_REG_PAGESIZE_SHIFT; - - return config_reg; -} - -static u32 get_sdram_ref_ctrl(u32 freq, - const struct lpddr2_addressing *addressing) -{ - u32 ref_ctrl = 0, val = 0, freq_khz; - freq_khz = freq / 1000; - /* - * refresh rate to be set is 'tREFI * freq in MHz - * division by 10000 to account for khz and x10 in t_REFI_us_x10 - */ - val = addressing->t_REFI_us_x10 * freq_khz / 10000; - ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; - - return ref_ctrl; -} - -static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck, - const struct lpddr2_addressing *addressing) -{ - u32 tim1 = 0, val = 0; - val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; - tim1 |= val << EMIF_REG_T_WTR_SHIFT; - - if (addressing->num_banks == BANKS8) - val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / - (4 * (*T_num)) - 1; - else - val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; - - tim1 |= val << EMIF_REG_T_RRD_SHIFT; - - val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; - tim1 |= val << EMIF_REG_T_RC_SHIFT; - - val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; - tim1 |= val << EMIF_REG_T_RAS_SHIFT; - - val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; - tim1 |= val << EMIF_REG_T_WR_SHIFT; - - val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; - tim1 |= val << EMIF_REG_T_RCD_SHIFT; - - val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; - tim1 |= val << EMIF_REG_T_RP_SHIFT; - - return tim1; -} - -static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck) -{ - u32 tim2 = 0, val = 0; - val = max(min_tck->tCKE, timings->tCKE) - 1; - tim2 |= val << EMIF_REG_T_CKE_SHIFT; - - val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; - tim2 |= val << EMIF_REG_T_RTP_SHIFT; - - /* - * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the - * same value - */ - val = ns_2_cycles(timings->tXSR) - 1; - tim2 |= val << EMIF_REG_T_XSRD_SHIFT; - tim2 |= val << EMIF_REG_T_XSNR_SHIFT; - - val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; - tim2 |= val << EMIF_REG_T_XP_SHIFT; - - return tim2; -} - -static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck, - const struct lpddr2_addressing *addressing) -{ - u32 tim3 = 0, val = 0; - val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); - tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; - - val = ns_2_cycles(timings->tRFCab) - 1; - tim3 |= val << EMIF_REG_T_RFC_SHIFT; - - val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; - tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; - - val = ns_2_cycles(timings->tZQCS) - 1; - tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; - - val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; - tim3 |= val << EMIF_REG_T_CKESR_SHIFT; - - return tim3; -} - -static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 volt_ramp) -{ - u32 zq = 0, val = 0; - if (volt_ramp) - val = - EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / - addressing->t_REFI_us_x10; - else - val = - EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / - addressing->t_REFI_us_x10; - zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; - - zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; - - zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; - - zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; - - /* - * Assuming that two chipselects have a single calibration resistor - * If there are indeed two calibration resistors, then this flag should - * be enabled to take advantage of dual calibration feature. - * This data should ideally come from board files. But considering - * that none of the boards today have calibration resistors per CS, - * it would be an unnecessary overhead. - */ - zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; - - zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; - - zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; - - return zq; -} - -static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 is_derated) -{ - u32 alert = 0, interval; - interval = - TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; - if (is_derated) - interval *= 4; - alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; - - alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; - - alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; - - alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; - - alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; - - alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; - - return alert; -} - -static u32 get_read_idle_ctrl_reg(u8 volt_ramp) -{ - u32 idle = 0, val = 0; - if (volt_ramp) - val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; - else - /*Maximum value in normal conditions - suggested by hw team */ - val = 0x1FF; - idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; - - idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; - - return idle; -} - -static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) -{ - u32 phy = 0, val = 0; - - phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; - - if (freq <= 100000000) - val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; - else if (freq <= 200000000) - val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; - else - val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; - phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; - - /* Other fields are constant magic values. Hardcode them together */ - phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << - EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; - - return phy; -} - -static u32 get_emif_mem_size(u32 base) -{ - u32 size_mbytes = 0, temp; - struct emif_device_details dev_details; - struct lpddr2_device_details cs0_dev_details, cs1_dev_details; - u32 emif_nr = emif_num(base); - - emif_reset_phy(base); - dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, - &cs0_dev_details); - dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, - &cs1_dev_details); - emif_reset_phy(base); - - if (dev_details.cs0_device_details) { - temp = dev_details.cs0_device_details->density; - size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; - } - - if (dev_details.cs1_device_details) { - temp = dev_details.cs1_device_details->density; - size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; - } - /* convert to bytes */ - return size_mbytes << 20; -} - -/* Gets the encoding corresponding to a given DMM section size */ -u32 get_dmm_section_size_map(u32 section_size) -{ - /* - * Section size mapping: - * 0x0: 16-MiB section - * 0x1: 32-MiB section - * 0x2: 64-MiB section - * 0x3: 128-MiB section - * 0x4: 256-MiB section - * 0x5: 512-MiB section - * 0x6: 1-GiB section - * 0x7: 2-GiB section - */ - section_size >>= 24; /* divide by 16 MB */ - return log_2_n_round_down(section_size); -} - -static void emif_calculate_regs( - const struct emif_device_details *emif_dev_details, - u32 freq, struct emif_regs *regs) -{ - u32 temp, sys_freq; - const struct lpddr2_addressing *addressing; - const struct lpddr2_ac_timings *timings; - const struct lpddr2_min_tck *min_tck; - const struct lpddr2_device_details *cs0_dev_details = - emif_dev_details->cs0_device_details; - const struct lpddr2_device_details *cs1_dev_details = - emif_dev_details->cs1_device_details; - const struct lpddr2_device_timings *cs0_dev_timings = - emif_dev_details->cs0_device_timings; - - emif_assert(emif_dev_details); - emif_assert(regs); - /* - * You can not have a device on CS1 without one on CS0 - * So configuring EMIF without a device on CS0 doesn't - * make sense - */ - emif_assert(cs0_dev_details); - emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); - /* - * If there is a device on CS1 it should be same type as CS0 - * (or NVM. But NVM is not supported in this driver yet) - */ - emif_assert((cs1_dev_details == NULL) || - (cs1_dev_details->type == LPDDR2_TYPE_NVM) || - (cs0_dev_details->type == cs1_dev_details->type)); - emif_assert(freq <= MAX_LPDDR2_FREQ); - - set_ddr_clk_period(freq); - - /* - * The device on CS0 is used for all timing calculations - * There is only one set of registers for timings per EMIF. So, if the - * second CS(CS1) has a device, it should have the same timings as the - * device on CS0 - */ - timings = get_timings_table(cs0_dev_timings->ac_timings, freq); - emif_assert(timings); - min_tck = cs0_dev_timings->min_tck; - - temp = addressing_table_index(cs0_dev_details->type, - cs0_dev_details->density, - cs0_dev_details->io_width); - - emif_assert((temp >= 0)); - addressing = &(addressing_table[temp]); - emif_assert(addressing); - - sys_freq = get_sys_clk_freq(); - - regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, - cs1_dev_details, - addressing, RL_BOOT); - - regs->sdram_config = get_sdram_config_reg(cs0_dev_details, - cs1_dev_details, - addressing, RL_FINAL); - - regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); - - regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); - - regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); - - regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); - - regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); - - regs->temp_alert_config = - get_temp_alert_config(cs1_dev_details, addressing, 0); - - regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, - LPDDR2_VOLTAGE_STABLE); - - regs->emif_ddr_phy_ctlr_1_init = - get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); - - regs->emif_ddr_phy_ctlr_1 = - get_ddr_phy_ctrl_1(freq, RL_FINAL); - - regs->freq = freq; - - print_timing_reg(regs->sdram_config_init); - print_timing_reg(regs->sdram_config); - print_timing_reg(regs->ref_ctrl); - print_timing_reg(regs->sdram_tim1); - print_timing_reg(regs->sdram_tim2); - print_timing_reg(regs->sdram_tim3); - print_timing_reg(regs->read_idle_ctrl); - print_timing_reg(regs->temp_alert_config); - print_timing_reg(regs->zq_config); - print_timing_reg(regs->emif_ddr_phy_ctlr_1); - print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); -} -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - -#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -const char *get_lpddr2_type(u8 type_id) -{ - switch (type_id) { - case LPDDR2_TYPE_S4: - return "LPDDR2-S4"; - case LPDDR2_TYPE_S2: - return "LPDDR2-S2"; - default: - return NULL; - } -} - -const char *get_lpddr2_io_width(u8 width_id) -{ - switch (width_id) { - case LPDDR2_IO_WIDTH_8: - return "x8"; - case LPDDR2_IO_WIDTH_16: - return "x16"; - case LPDDR2_IO_WIDTH_32: - return "x32"; - default: - return NULL; - } -} - -const char *get_lpddr2_manufacturer(u32 manufacturer) -{ - switch (manufacturer) { - case LPDDR2_MANUFACTURER_SAMSUNG: - return "Samsung"; - case LPDDR2_MANUFACTURER_QIMONDA: - return "Qimonda"; - case LPDDR2_MANUFACTURER_ELPIDA: - return "Elpida"; - case LPDDR2_MANUFACTURER_ETRON: - return "Etron"; - case LPDDR2_MANUFACTURER_NANYA: - return "Nanya"; - case LPDDR2_MANUFACTURER_HYNIX: - return "Hynix"; - case LPDDR2_MANUFACTURER_MOSEL: - return "Mosel"; - case LPDDR2_MANUFACTURER_WINBOND: - return "Winbond"; - case LPDDR2_MANUFACTURER_ESMT: - return "ESMT"; - case LPDDR2_MANUFACTURER_SPANSION: - return "Spansion"; - case LPDDR2_MANUFACTURER_SST: - return "SST"; - case LPDDR2_MANUFACTURER_ZMOS: - return "ZMOS"; - case LPDDR2_MANUFACTURER_INTEL: - return "Intel"; - case LPDDR2_MANUFACTURER_NUMONYX: - return "Numonyx"; - case LPDDR2_MANUFACTURER_MICRON: - return "Micron"; - default: - return NULL; - } -} - -static void display_sdram_details(u32 emif_nr, u32 cs, - struct lpddr2_device_details *device) -{ - const char *mfg_str; - const char *type_str; - char density_str[10]; - u32 density; - - debug("EMIF%d CS%d\t", emif_nr, cs); - - if (!device) { - debug("None\n"); - return; - } - - mfg_str = get_lpddr2_manufacturer(device->manufacturer); - type_str = get_lpddr2_type(device->type); - - density = lpddr2_density_2_size_in_mbytes[device->density]; - if ((density / 1024 * 1024) == density) { - density /= 1024; - sprintf(density_str, "%d GB", density); - } else - sprintf(density_str, "%d MB", density); - if (mfg_str && type_str) - debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); -} - -static u8 is_lpddr2_sdram_present(u32 base, u32 cs, - struct lpddr2_device_details *lpddr2_device) -{ - u32 mr = 0, temp; - - mr = get_mr(base, cs, LPDDR2_MR0); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; - if (temp) { - /* Not SDRAM */ - return 0; - } - temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; - - if (temp) { - /* DNV supported - But DNV is only supported for NVM */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR4); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR5); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - if (!get_lpddr2_manufacturer(mr)) { - /* Manufacturer not identified */ - return 0; - } - lpddr2_device->manufacturer = mr; - - mr = get_mr(base, cs, LPDDR2_MR6); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR7); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR8); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; - if (!get_lpddr2_type(temp)) { - /* Not SDRAM */ - return 0; - } - lpddr2_device->type = temp; - - temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; - if (temp > LPDDR2_DENSITY_32Gb) { - /* Density not supported */ - return 0; - } - lpddr2_device->density = temp; - - temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; - if (!get_lpddr2_io_width(temp)) { - /* IO width unsupported value */ - return 0; - } - lpddr2_device->io_width = temp; - - /* - * If all the above tests pass we should - * have a device on this chip-select - */ - return 1; -} - -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details) -{ - u32 phy; - u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; - - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (!lpddr2_dev_details) - return NULL; - - /* Do the minimum init for mode register accesses */ - if (!(running_from_sdram() || warm_reset())) { - phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); - writel(phy, &emif->emif_ddr_phy_ctrl_1); - } - - if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) - return NULL; - - display_sdram_details(emif_num(base), cs, lpddr2_dev_details); - - return lpddr2_dev_details; -} -#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ - -static void do_sdram_init(u32 base) -{ - const struct emif_regs *regs; - u32 in_sdram, emif_nr; - - debug(">>do_sdram_init() %x\n", base); - - in_sdram = running_from_sdram(); - emif_nr = (base == EMIF1_BASE) ? 1 : 2; - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - emif_get_reg_dump(emif_nr, ®s); - if (!regs) { - debug("EMIF: reg dump not provided\n"); - return; - } -#else - /* - * The user has not provided the register values. We need to - * calculate it based on the timings and the DDR frequency - */ - struct emif_device_details dev_details; - struct emif_regs calculated_regs; - - /* - * Get device details: - * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set - * - Obtained from user otherwise - */ - struct lpddr2_device_details cs0_dev_details, cs1_dev_details; - emif_reset_phy(base); - dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, - &cs0_dev_details); - dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, - &cs1_dev_details); - emif_reset_phy(base); - - /* Return if no devices on this EMIF */ - if (!dev_details.cs0_device_details && - !dev_details.cs1_device_details) { - return; - } - - /* - * Get device timings: - * - Default timings specified by JESD209-2 if - * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set - * - Obtained from user otherwise - */ - emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, - &dev_details.cs1_device_timings); - - /* Calculate the register values */ - emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); - regs = &calculated_regs; -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - - /* - * Initializing the DDR device can not happen from SDRAM. - * Changing the timing registers in EMIF can happen(going from one - * OPP to another) - */ - if (!in_sdram && (!warm_reset() || is_dra7xx())) { - if (emif_sdram_type(regs->sdram_config) == - EMIF_SDRAM_TYPE_LPDDR2) - lpddr2_init(base, regs); -#ifndef CONFIG_OMAP44XX - else - ddr3_init(base, regs); -#endif - } -#ifdef CONFIG_OMAP54X - if (warm_reset() && (emif_sdram_type(regs->sdram_config) == - EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { - set_lpmode_selfrefresh(base); - emif_reset_phy(base); - omap5_ddr3_leveling(base, regs); - } -#endif - - /* Write to the shadow registers */ - emif_update_timings(base, regs); - - debug("<emif_pwr_mgmt_ctrl); -} - -void dmm_init(u32 base) -{ - const struct dmm_lisa_map_regs *lisa_map_regs; - u32 i, section, valid; - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - emif_get_dmm_regs(&lisa_map_regs); -#else - u32 emif1_size, emif2_size, mapped_size, section_map = 0; - u32 section_cnt, sys_addr; - struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; - - mapped_size = 0; - section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; - emif1_size = get_emif_mem_size(EMIF1_BASE); - emif2_size = get_emif_mem_size(EMIF2_BASE); - debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); - - if (!emif1_size && !emif2_size) - return; - - /* symmetric interleaved section */ - if (emif1_size && emif2_size) { - mapped_size = min(emif1_size, emif2_size); - section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; - section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= (sys_addr >> 24) << - EMIF_SYS_ADDR_SHIFT; - section_map |= get_dmm_section_size_map(mapped_size * 2) - << EMIF_SYS_SIZE_SHIFT; - lis_map_regs_calculated.dmm_lisa_map_3 = section_map; - emif1_size -= mapped_size; - emif2_size -= mapped_size; - sys_addr += (mapped_size * 2); - section_cnt--; - } - - /* - * Single EMIF section(we can have a maximum of 1 single EMIF - * section- either EMIF1 or EMIF2 or none, but not both) - */ - if (emif1_size) { - section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; - section_map |= get_dmm_section_size_map(emif1_size) - << EMIF_SYS_SIZE_SHIFT; - /* only MSB */ - section_map |= (mapped_size >> 24) << - EMIF_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; - section_cnt--; - } - if (emif2_size) { - section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; - section_map |= get_dmm_section_size_map(emif2_size) << - EMIF_SYS_SIZE_SHIFT; - /* only MSB */ - section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; - section_cnt--; - } - - if (section_cnt == 2) { - /* Only 1 section - either symmetric or single EMIF */ - lis_map_regs_calculated.dmm_lisa_map_3 = section_map; - lis_map_regs_calculated.dmm_lisa_map_2 = 0; - lis_map_regs_calculated.dmm_lisa_map_1 = 0; - } else { - /* 2 sections - 1 symmetric, 1 single EMIF */ - lis_map_regs_calculated.dmm_lisa_map_2 = section_map; - lis_map_regs_calculated.dmm_lisa_map_1 = 0; - } - - /* TRAP for invalid TILER mappings in section 0 */ - lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; - - if (omap_revision() >= OMAP4460_ES1_0) - lis_map_regs_calculated.is_ma_present = 1; - - lisa_map_regs = &lis_map_regs_calculated; -#endif - struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)base; - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(lisa_map_regs->dmm_lisa_map_3, - &hw_lisa_map_regs->dmm_lisa_map_3); - writel(lisa_map_regs->dmm_lisa_map_2, - &hw_lisa_map_regs->dmm_lisa_map_2); - writel(lisa_map_regs->dmm_lisa_map_1, - &hw_lisa_map_regs->dmm_lisa_map_1); - writel(lisa_map_regs->dmm_lisa_map_0, - &hw_lisa_map_regs->dmm_lisa_map_0); - - if (lisa_map_regs->is_ma_present) { - hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)MA_BASE; - - writel(lisa_map_regs->dmm_lisa_map_3, - &hw_lisa_map_regs->dmm_lisa_map_3); - writel(lisa_map_regs->dmm_lisa_map_2, - &hw_lisa_map_regs->dmm_lisa_map_2); - writel(lisa_map_regs->dmm_lisa_map_1, - &hw_lisa_map_regs->dmm_lisa_map_1); - writel(lisa_map_regs->dmm_lisa_map_0, - &hw_lisa_map_regs->dmm_lisa_map_0); - - setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); - } - - /* - * EMIF should be configured only when - * memory is mapped on it. Using emif1_enabled - * and emif2_enabled variables for this. - */ - emif1_enabled = 0; - emif2_enabled = 0; - for (i = 0; i < 4; i++) { - section = __raw_readl(DMM_BASE + i*4); - valid = (section & EMIF_SDRC_MAP_MASK) >> - (EMIF_SDRC_MAP_SHIFT); - if (valid == 3) { - emif1_enabled = 1; - emif2_enabled = 1; - break; - } - - if (valid == 1) - emif1_enabled = 1; - - if (valid == 2) - emif2_enabled = 1; - } -} - -static void do_bug0039_workaround(u32 base) -{ - u32 val, i, clkctrl; - struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; - const struct read_write_regs *bug_00339_regs; - u32 iterations; - u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; - u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; - - if (is_dra7xx()) - phy_status_base++; - - bug_00339_regs = get_bug_regs(&iterations); - - /* Put EMIF in to idle */ - clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); - __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); - - /* Copy the phy status registers in to phy ctrl shadow registers */ - for (i = 0; i < iterations; i++) { - val = __raw_readl(phy_status_base + - bug_00339_regs[i].read_reg - 1); - - __raw_writel(val, phy_ctrl_base + - ((bug_00339_regs[i].write_reg - 1) << 1)); - - __raw_writel(val, phy_ctrl_base + - (bug_00339_regs[i].write_reg << 1) - 1); - } - - /* Disable leveling */ - writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); - - __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); -} - -/* - * SDRAM initialization: - * SDRAM initialization has two parts: - * 1. Configuring the SDRAM device - * 2. Update the AC timings related parameters in the EMIF module - * (1) should be done only once and should not be done while we are - * running from SDRAM. - * (2) can and should be done more than once if OPP changes. - * Particularly, this may be needed when we boot without SPL and - * and using Configuration Header(CH). ROM code supports only at 50% OPP - * at boot (low power boot). So u-boot has to switch to OPP100 and update - * the frequency. So, - * Doing (1) and (2) makes sense - first time initialization - * Doing (2) and not (1) makes sense - OPP change (when using CH) - * Doing (1) and not (2) doen't make sense - * See do_sdram_init() for the details - */ -void sdram_init(void) -{ - u32 in_sdram, size_prog, size_detect; - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); - - debug(">>sdram_init()\n"); - - if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) - return; - - in_sdram = running_from_sdram(); - debug("in_sdram = %d\n", in_sdram); - - if (!in_sdram) { - if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) - bypass_dpll((*prcm)->cm_clkmode_dpll_core); - else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) - writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); - } - - if (!in_sdram) - dmm_init(DMM_BASE); - - if (emif1_enabled) - do_sdram_init(EMIF1_BASE); - - if (emif2_enabled) - do_sdram_init(EMIF2_BASE); - - if (!(in_sdram || warm_reset())) { - if (emif1_enabled) - emif_post_init_config(EMIF1_BASE); - if (emif2_enabled) - emif_post_init_config(EMIF2_BASE); - } - - /* for the shadow registers to take effect */ - if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) - freq_update_core(); - - /* Do some testing after the init */ - if (!in_sdram) { - size_prog = omap_sdram_size(); - size_prog = log_2_n_round_down(size_prog); - size_prog = (1 << size_prog); - - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - size_prog); - /* Compare with the size programmed */ - if (size_detect != size_prog) { - printf("SDRAM: identified size not same as expected" - " size identified: %x expected: %x\n", - size_detect, - size_prog); - } else - debug("get_ram_size() successful"); - } - -#if defined(CONFIG_TI_SECURE_DEVICE) - /* - * On HS devices, do static EMIF firewall configuration - * but only do it if not already running in SDRAM - */ - if (!in_sdram) - if (0 != secure_emif_reserve()) - hang(); - - /* On HS devices, ensure static EMIF firewall APIs are locked */ - if (0 != secure_emif_firewall_lock()) - hang(); -#endif - - if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && - (!in_sdram && !warm_reset()) && (!is_dra7xx())) { - if (emif1_enabled) - do_bug0039_workaround(EMIF1_BASE); - if (emif2_enabled) - do_bug0039_workaround(EMIF2_BASE); - } - - debug("< - * - * Author : - * Aneesh V - * Steve Sakoman - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) -{ - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -static void set_mux_conf_regs(void) -{ - switch (omap_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - set_muxconf_regs(); - break; - case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: - break; - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - set_muxconf_regs(); - break; - } -} - -u32 cortex_rev(void) -{ - - unsigned int rev; - - /* Read Main ID Register (MIDR) */ - asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); - - return rev; -} - -static void omap_rev_string(void) -{ - u32 omap_rev = omap_revision(); - u32 soc_variant = (omap_rev & 0xF0000000) >> 28; - u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; - u32 major_rev = (omap_rev & 0x00000F00) >> 8; - u32 minor_rev = (omap_rev & 0x000000F0) >> 4; - - const char *sec_s; - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - if (soc_variant) - printf("OMAP"); - else - printf("DRA"); - printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); -} - -#ifdef CONFIG_SPL_BUILD -void spl_display_print(void) -{ - omap_rev_string(); -} -#endif - -void __weak srcomp_enable(void) -{ -} - -/** - * do_board_detect() - Detect board description - * - * Function to detect board description. This is expected to be - * overridden in the SoC family board file where desired. - */ -void __weak do_board_detect(void) -{ -} - -/** - * vcores_init() - Assign omap_vcores based on board - * - * Function to pick the vcores based on board. This is expected to be - * overridden in the SoC family board file where desired. - */ -void __weak vcores_init(void) -{ -} - -void s_init(void) -{ -} - -/** - * early_system_init - Does Early system initialization. - * - * Does early system init of watchdog, muxing, andclocks - * Watchdog disable is done always. For the rest what gets done - * depends on the boot mode in which this function is executed when - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. U-Boot loaded to SDRAM by SPL - * 4. U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * Please have a look at the respective functions to see what gets - * done in each of these cases - * This function is called with SRAM stack. - */ -void early_system_init(void) -{ - init_omap_revision(); - hw_data_init(); - -#ifdef CONFIG_SPL_BUILD - if (warm_reset()) - force_emif_self_refresh(); -#endif - watchdog_init(); - set_mux_conf_regs(); -#ifdef CONFIG_SPL_BUILD - srcomp_enable(); - do_io_settings(); -#endif - setup_early_clocks(); - do_board_detect(); - vcores_init(); - prcm_init(); -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - early_system_init(); -#ifdef CONFIG_BOARD_EARLY_INIT_F - board_early_init_f(); -#endif - /* For regular u-boot sdram_init() is called from dram_init() */ - sdram_init(); -} -#endif - -int arch_cpu_init_dm(void) -{ - early_system_init(); - return 0; -} - -/* - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - */ -void wait_for_command_complete(struct watchdog *wd_base) -{ - int pending = 1; - do { - pending = readl(&wd_base->wwps); - } while (pending); -} - -/* - * Routine: watchdog_init - * Description: Shut down watch dogs - */ -void watchdog_init(void) -{ - struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; - - writel(WD_UNLOCK1, &wd2_base->wspr); - wait_for_command_complete(wd2_base); - writel(WD_UNLOCK2, &wd2_base->wspr); -} - - -/* - * This function finds the SDRAM size available in the system - * based on DMM section configurations - * This is needed because the size of memory installed may be - * different on different versions of the board - */ -u32 omap_sdram_size(void) -{ - u32 section, i, valid; - u64 sdram_start = 0, sdram_end = 0, addr, - size, total_size = 0, trap_size = 0, trap_start = 0; - - for (i = 0; i < 4; i++) { - section = __raw_readl(DMM_BASE + i*4); - valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> - (EMIF_SDRC_ADDRSPC_SHIFT); - addr = section & EMIF_SYS_ADDR_MASK; - - /* See if the address is valid */ - if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && - (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { - size = ((section & EMIF_SYS_SIZE_MASK) >> - EMIF_SYS_SIZE_SHIFT); - size = 1 << size; - size *= SZ_16M; - - if (valid != DMM_SDRC_ADDR_SPC_INVALID) { - if (!sdram_start || (addr < sdram_start)) - sdram_start = addr; - if (!sdram_end || ((addr + size) > sdram_end)) - sdram_end = addr + size; - } else { - trap_size = size; - trap_start = addr; - } - } - } - - if ((trap_start >= sdram_start) && (trap_start < sdram_end)) - total_size = (sdram_end - sdram_start) - (trap_size); - else - total_size = sdram_end - sdram_start; - - return total_size; -} - - -/* - * Routine: dram_init - * Description: sets uboots idea of sdram size - */ -int dram_init(void) -{ - sdram_init(); - gd->ram_size = omap_sdram_size(); - return 0; -} - -/* - * Print board information - */ -int checkboard(void) -{ - puts(sysinfo.board_string); - return 0; -} - -/* - * get_device_type(): tell if GP/HS/EMU/TST - */ -u32 get_device_type(void) -{ - return (readl((*ctrl)->control_status) & - (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -/* - * Print CPU information - */ -int print_cpuinfo(void) -{ - puts("CPU : "); - omap_rev_string(); - - return 0; -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S deleted file mode 100644 index 8ce12c8e9ae..00000000000 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Author : - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -.arch_extension sec - -#ifdef CONFIG_SPL -ENTRY(save_boot_params) - ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS - str r0, [r1] - b save_boot_params_ret -ENDPROC(save_boot_params) - -#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) -ENTRY(switch_to_hypervisor) - -/* - * Switch to hypervisor mode - */ - adr r0, save_sp - str sp, [r0] - adr r1, restore_from_hyp - ldr r0, =0x102 - b omap_smc1 -restore_from_hyp: - adr r0, save_sp - ldr sp, [r0] - MRC p15, 4, R0, c1, c0, 0 - ldr r1, =0X1004 @Set cache enable bits for hypervisor mode - orr r0, r0, r1 - MCR p15, 4, R0, c1, c0, 0 - b switch_to_hypervisor_ret -save_sp: - .word 0x0 -ENDPROC(switch_to_hypervisor) -#endif -#endif - -ENTRY(omap_smc1) - push {r4-r12, lr} @ save registers - ROM code may pollute - @ our registers - mov r12, r0 @ Service - mov r0, r1 @ Argument - - dsb - dmb - smc 0 @ SMC #0 to enter monitor mode - @ call ROM Code API for the service requested - pop {r4-r12, pc} -ENDPROC(omap_smc1) - -ENTRY(omap_smc_sec) - push {r4-r12, lr} @ save registers - ROM code may pollute - @ our registers - mov r6, #0xFF @ Indicate new Task call - mov r12, #0x00 @ Secure Service ID in R12 - - dsb - dmb - smc 0 @ SMC #0 to enter monitor mode - - b omap_smc_sec_end @ exit at end of the service execution - nop - - @ In case of IRQ happening in Secure, then ARM will branch here. - @ At that moment, IRQ will be pending and ARM will jump to Non Secure - @ IRQ handler - mov r12, #0xFE - - dsb - dmb - smc 0 @ SMC #0 to enter monitor mode - -omap_smc_sec_end: - pop {r4-r12, pc} -ENDPROC(omap_smc_sec) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c deleted file mode 100644 index d72e82e0283..00000000000 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, - * - * Author : - * Mansoor Ahamed - * - * Initial Code from: - * Manikandan Pillai - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; - -#if defined(CONFIG_NOR) -char gpmc_cs0_flash = MTD_DEV_TYPE_NOR; -#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) -char gpmc_cs0_flash = MTD_DEV_TYPE_NAND; -#elif defined(CONFIG_CMD_ONENAND) -char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; -#else -char gpmc_cs0_flash = -1; -#endif - -#if defined(CONFIG_OMAP34XX) -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in guessing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(u32 cs) -{ - u32 val1, val2, addr; - u32 pattern = 0x12345678; - - addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); - - writel(0x0, addr + 0x400); /* clear pos A */ - writel(pattern, addr); /* pattern to pos B */ - writel(0x0, addr + 4); /* remove pattern off the bus */ - val1 = readl(addr + 0x400); /* get pos A value */ - val2 = readl(addr); /* get val2 */ - writel(0x0, addr + 0x400); /* clear pos A */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ - return 0; - else - return 1; -} -#endif - -void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, - u32 base, u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); - sdelay(2000); -} - -void set_gpmc_cs0(int flash_type) -{ - const u32 *gpmc_regs; - u32 base, size; -#if defined(CONFIG_NOR) - const u32 gpmc_regs_nor[GPMC_MAX_REG] = { - STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, - STNOR_GPMC_CONFIG7 - }; -#endif -#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) - const u32 gpmc_regs_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0 - }; -#endif -#if defined(CONFIG_CMD_ONENAND) - const u32 gpmc_regs_onenand[GPMC_MAX_REG] = { - ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, - 0 - }; -#endif - - switch (flash_type) { -#if defined(CONFIG_NOR) - case MTD_DEV_TYPE_NOR: - gpmc_regs = gpmc_regs_nor; - base = CONFIG_SYS_FLASH_BASE; - size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : - GPMC_SIZE_16M))); - break; -#endif -#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) - case MTD_DEV_TYPE_NAND: - gpmc_regs = gpmc_regs_nand; - base = CONFIG_SYS_NAND_BASE; - size = GPMC_SIZE_16M; - break; -#endif -#if defined(CONFIG_CMD_ONENAND) - case MTD_DEV_TYPE_ONENAND: - gpmc_regs = gpmc_regs_onenand; - base = CONFIG_SYS_ONENAND_BASE; - size = GPMC_SIZE_128M; - break; -#endif - default: - /* disable the GPMC0 config set by ROM code */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - return; - } - - /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* global settings */ - writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000000, &gpmc_cfg->irqstatus); - writel(0x00000000, &gpmc_cfg->irqenable); - /* disable timeout, set a safe reset value */ - writel(0x00001ff0, &gpmc_cfg->timeout_control); - writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ? - 0x00000200 : 0x00000012, &gpmc_cfg->config); - - set_gpmc_cs0(gpmc_cs0_flash); -} diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c deleted file mode 100644 index b37163a4f3e..00000000000 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * - * Common functions for OMAP4/5 based boards - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Author : - * Aneesh V - * Steve Sakoman - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Without LPAE short descriptors are used - * Set C - Cache Bit3 - * Set B - Buffer Bit2 - * The last 2 bits set to 0b10 - * Do Not set XN bit4 - * So value is 0xe - * - * With LPAE cache configuration happens via MAIR0 register - * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. - * 0xFF maps to Cache writeback with Read and Write Allocate set - * The bits[1:0] should have the value 0b01 for the first level - * descriptor. - * So the value is 0xd - */ - -#ifdef CONFIG_ARMV7_LPAE -#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC -#else -#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK -#endif - -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; - u32 end = start + size; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_POLICY); -} - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c deleted file mode 100644 index e02e3ec23ee..00000000000 --- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "pipe3-phy.h" - -/* PLLCTRL Registers */ -#define PLL_STATUS 0x00000004 -#define PLL_GO 0x00000008 -#define PLL_CONFIGURATION1 0x0000000C -#define PLL_CONFIGURATION2 0x00000010 -#define PLL_CONFIGURATION3 0x00000014 -#define PLL_CONFIGURATION4 0x00000020 - -#define PLL_REGM_MASK 0x001FFE00 -#define PLL_REGM_SHIFT 9 -#define PLL_REGM_F_MASK 0x0003FFFF -#define PLL_REGM_F_SHIFT 0 -#define PLL_REGN_MASK 0x000001FE -#define PLL_REGN_SHIFT 1 -#define PLL_SELFREQDCO_MASK 0x0000000E -#define PLL_SELFREQDCO_SHIFT 1 -#define PLL_SD_MASK 0x0003FC00 -#define PLL_SD_SHIFT 10 -#define SET_PLL_GO 0x1 -#define PLL_TICOPWDN BIT(16) -#define PLL_LDOPWDN BIT(15) -#define PLL_LOCK 0x2 -#define PLL_IDLE 0x1 - -/* PHY POWER CONTROL Register */ -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE - -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 - -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 - - -#define PLL_IDLE_TIME 100 /* in milliseconds */ -#define PLL_LOCK_TIME 100 /* in milliseconds */ - -static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) -{ - return __raw_readl(addr + offset); -} - -static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, - u32 data) -{ - __raw_writel(data, addr + offset); -} - -static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 - *pipe3) -{ - u32 rate; - struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - printf("%s: No DPLL configuration for %u Hz SYS CLK\n", - __func__, rate); - return NULL; -} - - -static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_LOCK_TIME; - - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (val & PLL_LOCK) - break; - } while (--timeout); - - if (!(val & PLL_LOCK)) { - printf("%s: DPLL failed to lock\n", __func__); - return -EBUSY; - } - - return 0; -} - -static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) -{ - u32 val; - struct pipe3_dpll_params *dpll_params; - - dpll_params = omap_pipe3_get_dpll_params(phy); - if (!dpll_params) { - printf("%s: Invalid DPLL parameters\n", __func__); - return -EINVAL; - } - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); - - omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - - return omap_pipe3_wait_lock(phy); -} - -static void omap_control_phy_power(struct omap_pipe3 *phy, int on) -{ - u32 val, rate; - - val = readl(phy->power_reg); - - rate = get_sys_clk_freq(); - rate = rate/1000000; - - if (on) { - val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; - } else { - val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - } - - writel(val, phy->power_reg); -} - -int phy_pipe3_power_on(struct omap_pipe3 *phy) -{ - int ret; - u32 val; - - /* Program the DPLL only if not locked */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (!(val & PLL_LOCK)) { - ret = omap_pipe3_dpll_program(phy); - if (ret) - return ret; - } else { - /* else just bring it out of IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - if (val & PLL_IDLE) { - val &= ~PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, - PLL_CONFIGURATION2, val); - ret = omap_pipe3_wait_lock(phy); - if (ret) - return ret; - } - } - - /* Power up the PHY */ - omap_control_phy_power(phy, 1); - - return 0; -} - -int phy_pipe3_power_off(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_IDLE_TIME; - - /* Power down the PHY */ - omap_control_phy_power(phy, 0); - - /* Put DPLL in IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val |= PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - /* wait for LDO and Oscillator to power down */ - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) - break; - } while (--timeout); - - if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { - printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", - __func__, val); - return -EBUSY; - } - - return 0; -} - diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h deleted file mode 100644 index 441f49a3f97..00000000000 --- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __OMAP_PIPE3_PHY_H -#define __OMAP_PIPE3_PHY_H - -struct pipe3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct pipe3_dpll_map { - unsigned long rate; - struct pipe3_dpll_params params; -}; - -struct omap_pipe3 { - void __iomem *pll_ctrl_base; - void __iomem *power_reg; - struct pipe3_dpll_map *dpll_map; -}; - - -int phy_pipe3_power_on(struct omap_pipe3 *phy); -int phy_pipe3_power_off(struct omap_pipe3 *pipe3); - -#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c deleted file mode 100644 index 91ad031ddd3..00000000000 --- a/arch/arm/cpu/armv7/omap-common/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * - * Common layer for reset related functionality of OMAP based socs. - * - * (C) Copyright 2012 - * Texas Instruments, - * - * Sricharan R - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include - -void __weak reset_cpu(unsigned long ignored) -{ - writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); -} - -u32 __weak warm_reset(void) -{ - return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); -} - -void __weak setup_warmreset_time(void) -{ -} diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c deleted file mode 100644 index 2c2d1bce363..00000000000 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * TI SATA platform driver - * - * (C) Copyright 2013 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include "pipe3-phy.h" - -static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ - {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -struct omap_pipe3 sata_phy = { - .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, - /* .power_reg is updated at runtime */ - .dpll_map = dpll_map_sata, -}; - -int init_sata(int dev) -{ - int ret; - u32 val; - - u32 const clk_domains_sata[] = { - 0 - }; - - u32 const clk_modules_hw_auto_sata[] = { - (*prcm)->cm_l3init_ocp2scp3_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_sata[] = { - (*prcm)->cm_l3init_sata_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_sata, - clk_modules_hw_auto_sata, - clk_modules_explicit_en_sata, - 0); - - /* Enable optional functional clock for SATA */ - setbits_le32((*prcm)->cm_l3init_sata_clkctrl, - SATA_CLKCTRL_OPTFCLKEN_MASK); - - sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; - - /* Power up the PHY */ - phy_pipe3_power_on(&sata_phy); - - /* Enable SATA module, No Idle, No Standby */ - val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; - writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); - - ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return ret; -} - -int reset_sata(int dev) -{ - return 0; -} - -/* On OMAP platforms SATA provides the SCSI subsystem */ -void scsi_init(void) -{ - init_sata(0); - scsi_scan(1); -} - -void scsi_bus_reset(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); - ahci_init((void __iomem *)DWC_AHSATA_BASE); -} diff --git a/arch/arm/cpu/armv7/omap-common/sec-common.c b/arch/arm/cpu/armv7/omap-common/sec-common.c deleted file mode 100644 index 246a2393dab..00000000000 --- a/arch/arm/cpu/armv7/omap-common/sec-common.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * - * Common security related functions for OMAP devices - * - * (C) Copyright 2016 - * Texas Instruments, - * - * Daniel Allred - * Andreas Dannenberg - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include -#include -#include -#include -#include - -/* Index for signature verify ROM API */ -#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E) - -static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN); - -u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...) -{ - int i; - u32 num_args; - va_list ap; - - va_start(ap, flag); - - num_args = va_arg(ap, u32); - - if (num_args > 4) - return 1; - - /* Copy args to aligned args structure */ - for (i = 0; i < num_args; i++) - secure_rom_call_args[i + 1] = va_arg(ap, u32); - - secure_rom_call_args[0] = num_args; - - va_end(ap); - - /* if data cache is enabled, flush the aligned args structure */ - flush_dcache_range( - (unsigned int)&secure_rom_call_args[0], - (unsigned int)&secure_rom_call_args[0] + - roundup(sizeof(secure_rom_call_args), ARCH_DMA_MINALIGN)); - - return omap_smc_sec(service, proc_id, flag, secure_rom_call_args); -} - -static u32 find_sig_start(char *image, size_t size) -{ - char *image_end = image + size; - char *sig_start_magic = "CERT_"; - int magic_str_len = strlen(sig_start_magic); - char *ch; - - while (--image_end > image) { - if (*image_end == '_') { - ch = image_end - magic_str_len + 1; - if (!strncmp(ch, sig_start_magic, magic_str_len)) - return (u32)ch; - } - } - return 0; -} - -int secure_boot_verify_image(void **image, size_t *size) -{ - int result = 1; - u32 cert_addr, sig_addr; - size_t cert_size; - - /* Perform cache writeback on input buffer */ - flush_dcache_range( - (u32)*image, - (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); - - cert_addr = (uint32_t)*image; - sig_addr = find_sig_start((char *)*image, *size); - - if (sig_addr == 0) { - printf("No signature found in image!\n"); - result = 1; - goto auth_exit; - } - - *size = sig_addr - cert_addr; /* Subtract out the signature size */ - cert_size = *size; - - /* Check if image load address is 32-bit aligned */ - if (!IS_ALIGNED(cert_addr, 4)) { - printf("Image is not 4-byte aligned!\n"); - result = 1; - goto auth_exit; - } - - /* Image size also should be multiple of 4 */ - if (!IS_ALIGNED(cert_size, 4)) { - printf("Image size is not 4-byte aligned!\n"); - result = 1; - goto auth_exit; - } - - /* Call ROM HAL API to verify certificate signature */ - debug("%s: load_addr = %x, size = %x, sig_addr = %x\n", __func__, - cert_addr, cert_size, sig_addr); - - result = secure_rom_call( - API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0, - 4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF); -auth_exit: - if (result != 0) { - printf("Authentication failed!\n"); - printf("Return Value = %08X\n", result); - hang(); - } - - /* - * Output notification of successful authentication as well the name of - * the signing certificate used to re-assure the user that the secure - * code is being processed as expected. However suppress any such log - * output in case of building for SPL and booting via YMODEM. This is - * done to avoid disturbing the YMODEM serial protocol transactions. - */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && - IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && - spl_boot_device() == BOOT_DEVICE_UART)) - printf("Authentication passed: %s\n", (char *)sig_addr); - - return result; -} diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c deleted file mode 100644 index 49e3a971d96..00000000000 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments - * - * Richard Woodruff - * Syed Moahmmed Khasim - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; - -/* - * Nothing really to do with interrupts, just starts up a counter. - */ - -#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) -#define TIMER_OVERFLOW_VAL 0xffffffff -#define TIMER_LOAD_VAL 0 - -int timer_init(void) -{ - /* start the counter ticking up, reload value on overflow */ - writel(TIMER_LOAD_VAL, &timer_base->tldr); - /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - &timer_base->tclr); - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds */ -void __udelay(unsigned long usec) -{ - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - unsigned long now, last = readl(&timer_base->tcrr); - - while (tmo > 0) { - now = readl(&timer_base->tcrr); - if (last > now) /* count up timer overflow */ - tmo -= TIMER_OVERFLOW_VAL - last + now + 1; - else - tmo -= now - last; - last = now; - } -} - -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { /* we have rollover of incrementer */ - gd->arch.tbl += ((TIMER_OVERFLOW_VAL / (TIMER_CLOCK / - CONFIG_SYS_HZ)) - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds deleted file mode 100644 index 8fec715ca56..00000000000 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2010 - * Texas Instruments, - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c deleted file mode 100644 index 2d03ebfbd3d..00000000000 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2011 Linaro Limited - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -static void do_cancel_out(u32 *num, u32 *den, u32 factor) -{ - while (1) { - if (((*num)/factor*factor == (*num)) && - ((*den)/factor*factor == (*den))) { - (*num) /= factor; - (*den) /= factor; - } else - break; - } -} - -/* - * Cancel out the denominator and numerator of a fraction - * to get smaller numerator and denominator. - */ -void cancel_out(u32 *num, u32 *den, u32 den_limit) -{ - do_cancel_out(num, den, 2); - do_cancel_out(num, den, 3); - do_cancel_out(num, den, 5); - do_cancel_out(num, den, 7); - do_cancel_out(num, den, 11); - do_cancel_out(num, den, 13); - do_cancel_out(num, den, 17); - while ((*den) > den_limit) { - *num /= 2; - /* - * Round up the denominator so that the final fraction - * (num/den) is always <= the desired value - */ - *den = (*den + 1) / 2; - } -} - -__weak void omap_die_id(unsigned int *die_id) -{ - die_id[0] = die_id[1] = die_id[2] = die_id[3] = 0; -} - -void omap_die_id_serial(void) -{ - unsigned int die_id[4] = { 0 }; - char serial_string[17] = { 0 }; - - omap_die_id((unsigned int *)&die_id); - - if (!getenv("serial#")) { - snprintf(serial_string, sizeof(serial_string), - "%08x%08x", die_id[0], die_id[3]); - - setenv("serial#", serial_string); - } -} - -void omap_die_id_get_board_serial(struct tag_serialnr *serialnr) -{ - char *serial_string; - unsigned long long serial; - - serial_string = getenv("serial#"); - - if (serial_string) { - serial = simple_strtoull(serial_string, NULL, 16); - - serialnr->high = (unsigned int) (serial >> 32); - serialnr->low = (unsigned int) (serial & 0xffffffff); - } else { - serialnr->high = 0; - serialnr->low = 0; - } -} - -void omap_die_id_usbethaddr(void) -{ - unsigned int die_id[4] = { 0 }; - unsigned char mac[6] = { 0 }; - - omap_die_id((unsigned int *)&die_id); - - if (!getenv("usbethaddr")) { - /* - * Create a fake MAC address from the processor ID code. - * First byte is 0x02 to signify locally administered. - */ - mac[0] = 0x02; - mac[1] = die_id[3] & 0xff; - mac[2] = die_id[2] & 0xff; - mac[3] = die_id[1] & 0xff; - mac[4] = die_id[0] & 0xff; - mac[5] = (die_id[0] >> 8) & 0xff; - - eth_setenv_enetaddr("usbethaddr", mac); - } -} - -void omap_die_id_display(void) -{ - unsigned int die_id[4] = { 0 }; - - omap_die_id(die_id); - - printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2], - die_id[1], die_id[0]); -} diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c deleted file mode 100644 index a68f1d145dc..00000000000 --- a/arch/arm/cpu/armv7/omap-common/vc.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Voltage Controller implementation for OMAP - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Nishanth Menon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* - * Define Master code if there are multiple masters on the I2C_SR bus. - * Normally not required - */ -#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE -#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0 -#endif - -/* Register defines and masks for VC IP Block */ -/* PRM_VC_CFG_I2C_MODE */ -#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6) -#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4) -#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3) -#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0 -#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3 - -/* PRM_VC_CFG_I2C_CLK */ -#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24 -#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16 -#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 -#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 -#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24) -#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 -#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F -#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 -#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF -#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 -#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF - -/** - * omap_vc_init() - Initialization for Voltage controller - * @speed_khz: I2C buspeed in KHz - */ -static void omap_vc_init(u16 speed_khz) -{ - u32 val; - u32 sys_clk_khz, cycles_hi, cycles_low; - - sys_clk_khz = get_sys_clk_freq() / 1000; - - if (speed_khz > 400) { - puts("higher speed requested - throttle to 400Khz\n"); - speed_khz = 400; - } - - /* - * Setup the dedicated I2C controller for Voltage Control - * I2C clk - high period 40% low period 60% - */ - speed_khz /= 10; - cycles_hi = sys_clk_khz * 4 / speed_khz; - cycles_low = sys_clk_khz * 6 / speed_khz; - /* values to be set in register - less by 5 & 7 respectively */ - cycles_hi -= 5; - cycles_low -= 7; - val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | - (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); - writel(val, (*prcm)->prm_vc_cfg_i2c_clk); - - val = CONFIG_OMAP_VC_I2C_HS_MCODE << - PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; - /* No HS mode for now */ - val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; - writel(val, (*prcm)->prm_vc_cfg_i2c_mode); -} - -/** - * omap_vc_bypass_send_value() - Send a data using VC Bypass command - * @sa: 7 bit I2C slave address of the PMIC - * @reg_addr: I2C register address(8 bit) address in PMIC - * @reg_data: what 8 bit data to write - */ -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) -{ - /* - * Unfortunately we need to loop here instead of a defined time - * use arbitary large value - */ - u32 timeout = 0xFFFF; - u32 reg_val; - - sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK; - reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; - reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; - - /* program VC to send data */ - reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | - reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | - reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; - writel(reg_val, (*prcm)->prm_vc_val_bypass); - - /* Signal VC to send data */ - writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, - (*prcm)->prm_vc_val_bypass); - - /* Wait on VC to complete transmission */ - do { - reg_val = readl((*prcm)->prm_vc_val_bypass) & - PRM_VC_VAL_BYPASS_VALID_BIT; - if (!reg_val) - break; - - sdelay(100); - } while (--timeout); - - /* Optional: cleanup PRM_IRQSTATUS_Ax */ - /* In case we can do something about it in future.. */ - if (!timeout) - return -1; - - /* All good.. */ - return 0; -} - -void sri2c_init(void) -{ - static int sri2c = 1; - - if (sri2c) { - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - sri2c = 0; - } - return; -} diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig deleted file mode 100644 index 7d884a237bb..00000000000 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ /dev/null @@ -1,154 +0,0 @@ -if OMAP34XX - -config SPL_EXT_SUPPORT - default y - -config SPL_FAT_SUPPORT - default y - -config SPL_GPIO_SUPPORT - default y - -config SPL_I2C_SUPPORT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - default y - -config SPL_NAND_SUPPORT - default y - -config SPL_POWER_SUPPORT - default y - -config SPL_SERIAL_SUPPORT - default y - -choice - prompt "OMAP3 board select" - optional - -config TARGET_AM3517_EVM - bool "AM3517 EVM" - -config TARGET_MT_VENTOUX - bool "TeeJet Mt.Ventoux" - -config TARGET_OMAP3_BEAGLE - bool "TI OMAP3 BeagleBoard" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_CM_T35 - bool "CompuLab CM-T3530 and CM-T3730 boards" - -config TARGET_CM_T3517 - bool "CompuLab CM-T3517 boards" - -config TARGET_DEVKIT8000 - bool "TimLL OMAP3 Devkit8000" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_OMAP3_EVM - bool "TI OMAP3 EVM" - -config TARGET_OMAP3_IGEP00X0 - bool "IGEP" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_OMAP3_OVERO - bool "OMAP35xx Gumstix Overo" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_OMAP3_ZOOM1 - bool "TI Zoom1" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_AM3517_CRANE - bool "am3517_crane" - -config TARGET_OMAP3_PANDORA - bool "OMAP3 Pandora" - -config TARGET_ECO5PK - bool "ECO5PK" - -config TARGET_TRICORDER - bool "Tricorder" - -config TARGET_MCX - bool "MCX" - -config TARGET_OMAP3_LOGIC - bool "OMAP3 Logic" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_NOKIA_RX51 - bool "Nokia RX51" - -config TARGET_TAO3530 - bool "TAO3530" - -config TARGET_TWISTER - bool "Twister" - -config TARGET_OMAP3_CAIRO - bool "QUIPOS CAIRO" - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_SNIPER - bool "LG Optimus Black" - select DM - select DM_SERIAL - select DM_GPIO - -endchoice - -config SYS_SOC - default "omap3" - -source "board/logicpd/am3517evm/Kconfig" -source "board/teejet/mt_ventoux/Kconfig" -source "board/ti/beagle/Kconfig" -source "board/compulab/cm_t35/Kconfig" -source "board/compulab/cm_t3517/Kconfig" -source "board/timll/devkit8000/Kconfig" -source "board/ti/evm/Kconfig" -source "board/isee/igep00x0/Kconfig" -source "board/overo/Kconfig" -source "board/logicpd/zoom1/Kconfig" -source "board/ti/am3517crane/Kconfig" -source "board/pandora/Kconfig" -source "board/8dtech/eco5pk/Kconfig" -source "board/corscience/tricorder/Kconfig" -source "board/htkw/mcx/Kconfig" -source "board/logicpd/omap3som/Kconfig" -source "board/nokia/rx51/Kconfig" -source "board/technexion/tao3530/Kconfig" -source "board/technexion/twister/Kconfig" -source "board/quipos/cairo/Kconfig" -source "board/lg/sniper/Kconfig" - -endif diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile deleted file mode 100644 index b2fce966d9a..00000000000 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := lowlevel_init.o - -obj-y += board.o -obj-y += boot.o -obj-y += clock.o -obj-y += sys_info.o -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o -endif - -obj-$(CONFIG_DRIVER_TI_EMAC) += emac.o -obj-$(CONFIG_EMIF4) += emif4.o -obj-$(CONFIG_SDRC) += sdrc.o -obj-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c deleted file mode 100644 index 74dd105eb6f..00000000000 --- a/arch/arm/cpu/armv7/omap3/am35x_musb.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file configures the internal USB PHY in AM35X. - * - * Copyright (C) 2012 Ilya Yanok - * - * Based on omap_phy_internal.c code from Linux by - * Hema HK - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void am35x_musb_reset(void) -{ - /* Reset the musb interface */ - clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, - 0, USBOTGSS_SW_RST); - clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, - USBOTGSS_SW_RST, 0); -} - -void am35x_musb_phy_power(u8 on) -{ - unsigned long start = get_timer(0); - - if (on) { - /* - * Start the on-chip PHY and its PLL. - */ - clrsetbits_le32(&am35x_scm_general_regs->devconf2, - CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN, - CONF2_PHY_PLLON); - - debug("Waiting for PHY clock good...\n"); - while (!(readl(&am35x_scm_general_regs->devconf2) - & CONF2_PHYCLKGD)) { - - if (get_timer(start) > CONFIG_SYS_HZ / 10) { - printf("musb PHY clock good timed out\n"); - break; - } - } - } else { - /* - * Power down the on-chip PHY. - */ - clrsetbits_le32(&am35x_scm_general_regs->devconf2, - CONF2_PHY_PLLON, - CONF2_PHYPWRDN | CONF2_OTGPWRDN); - } -} - -void am35x_musb_clear_irq(void) -{ - clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, - 0, USBOTGSS_INT_CLR); - readl(&am35x_scm_general_regs->lvl_intr_clr); -} diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c deleted file mode 100644 index 5f5597772b6..00000000000 --- a/arch/arm/cpu/armv7/omap3/board.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * - * Common board functions for OMAP3 based boards. - * - * (C) Copyright 2004-2008 - * Texas Instruments, - * - * Author : - * Sunil Kumar - * Shashi Ranjan - * - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* Declarations */ -extern omap3_sysinfo sysinfo; -#ifndef CONFIG_SYS_L2CACHE_OFF -static void omap3_invalidate_l2_cache_secure(void); -#endif - -#ifdef CONFIG_DM_GPIO -static const struct omap_gpio_platdata omap34xx_gpio[] = { - { 0, OMAP34XX_GPIO1_BASE }, - { 1, OMAP34XX_GPIO2_BASE }, - { 2, OMAP34XX_GPIO3_BASE }, - { 3, OMAP34XX_GPIO4_BASE }, - { 4, OMAP34XX_GPIO5_BASE }, - { 5, OMAP34XX_GPIO6_BASE }, -}; - -U_BOOT_DEVICES(am33xx_gpios) = { - { "gpio_omap", &omap34xx_gpio[0] }, - { "gpio_omap", &omap34xx_gpio[1] }, - { "gpio_omap", &omap34xx_gpio[2] }, - { "gpio_omap", &omap34xx_gpio[3] }, - { "gpio_omap", &omap34xx_gpio[4] }, - { "gpio_omap", &omap34xx_gpio[5] }, -}; - -#else - -static const struct gpio_bank gpio_bank_34xx[6] = { - { (void *)OMAP34XX_GPIO1_BASE }, - { (void *)OMAP34XX_GPIO2_BASE }, - { (void *)OMAP34XX_GPIO3_BASE }, - { (void *)OMAP34XX_GPIO4_BASE }, - { (void *)OMAP34XX_GPIO5_BASE }, - { (void *)OMAP34XX_GPIO6_BASE }, -}; - -const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; - -#endif - -/****************************************************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************************************************/ -void secure_unlock_mem(void) -{ - struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; - struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; - struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; - struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; - struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE; - - /* Protection Module Register Target APE (PM_RT) */ - writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); - writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); - writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); - writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); - - writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); - writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); - writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); - - writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); - writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); - writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); - writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2); - - /* IVA Changes */ - writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); - writel(UNLOCK_3, &pm_iva2_base->read_permission_0); - writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0); - - /* SDRC region 0 public */ - writel(UNLOCK_1, &sms_base->rg_att0); -} - -/****************************************************************************** - * Routine: secureworld_exit() - * Description: If chip is EMU and boot type is external - * configure secure registers and exit secure world - * general use. - *****************************************************************************/ -void secureworld_exit(void) -{ - unsigned long i; - - /* configure non-secure access control register */ - __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); - /* enabling co-processor CP10 and CP11 accesses in NS world */ - __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); - /* - * allow allocation of locked TLBs and L2 lines in NS world - * allow use of PLE registers in NS world also - */ - __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); - - /* Enable ASA in ACR register */ - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - - /* Exiting secure world */ - __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); -} - -/****************************************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP/EMU(special) type, unlock the SRAM for - * general use. - *****************************************************************************/ -void try_unlock_memory(void) -{ - int mode; - int in_sdram = is_running_in_sdram(); - - /* - * if GP device unlock device SRAM for general use - * secure code breaks for Secure/Emulation device - HS/E/T - */ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock_mem(); - - /* - * If device is EMU and boot is XIP external booting - * Unlock firewalls and disable L2 and put chip - * out of secure world - * - * Assuming memories are unlocked by the demon who put us in SDRAM - */ - if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) - && (!in_sdram)) { - secure_unlock_mem(); - secureworld_exit(); - } - - return; -} - -/****************************************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with SRAM stack. - *****************************************************************************/ -void s_init(void) -{ - watchdog_init(); - - try_unlock_memory(); - -#ifndef CONFIG_SYS_L2CACHE_OFF - /* Invalidate L2-cache from secure mode */ - omap3_invalidate_l2_cache_secure(); -#endif - - set_muxconf_regs(); - sdelay(100); - - prcm_init(); - - per_clocks_enable(); - -#ifdef CONFIG_USB_EHCI_OMAP - ehci_clocks_enable(); -#endif -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - mem_init(); -} -#endif - -/* - * Routine: misc_init_r - * Description: A basic misc_init_r that just displays the die ID - */ -int __weak misc_init_r(void) -{ - omap_die_id_display(); - - return 0; -} - -/****************************************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - *****************************************************************************/ -static void wait_for_command_complete(struct watchdog *wd_base) -{ - int pending = 1; - do { - pending = readl(&wd_base->wwps); - } while (pending); -} - -/****************************************************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************************************************/ -void watchdog_init(void) -{ - struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - - /* - * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - - setbits_le32(&prcm_base->fclken_wkup, 0x20); - setbits_le32(&prcm_base->iclken_wkup, 0x20); - wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); - - writel(WD_UNLOCK1, &wd2_base->wspr); - wait_for_command_complete(wd2_base); - writel(WD_UNLOCK2, &wd2_base->wspr); -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} - -#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) -/****************************************************************************** - * OMAP3 specific command to switch between NAND HW and SW ecc - *****************************************************************************/ -static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2 || argc > 3) - goto usage; - - if (strncmp(argv[1], "hw", 2) == 0) { - if (argc == 2) { - omap_nand_switch_ecc(1, 1); - } else { - if (strncmp(argv[2], "hamming", 7) == 0) - omap_nand_switch_ecc(1, 1); - else if (strncmp(argv[2], "bch8", 4) == 0) - omap_nand_switch_ecc(1, 8); - else if (strncmp(argv[2], "bch16", 5) == 0) - omap_nand_switch_ecc(1, 16); - else - goto usage; - } - } else if (strncmp(argv[1], "sw", 2) == 0) { - if (argc == 2) { - omap_nand_switch_ecc(0, 1); - } else { - if (strncmp(argv[2], "hamming", 7) == 0) - omap_nand_switch_ecc(0, 1); - else if (strncmp(argv[2], "bch8", 4) == 0) - omap_nand_switch_ecc(0, 8); - else - goto usage; - } - } else { - goto usage; - } - - return 0; - -usage: - printf ("Usage: nandecc %s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - nandecc, 3, 1, do_switch_ecc, - "switch OMAP3 NAND ECC calculation algorithm", - "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming" - " and 8-bit/16-bit BCH\n" - " ecc calculation (second parameter may" - " be omitted).\n" - "nandecc sw - Switch to NAND software ecc algorithm." -); - -#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ - -#ifdef CONFIG_DISPLAY_BOARDINFO -/** - * Print board information - */ -int checkboard (void) -{ - char *mem_s ; - - if (is_mem_sdr()) - mem_s = "mSDR"; - else - mem_s = "LPDDR"; - - printf("%s + %s/%s\n", sysinfo.board_string, mem_s, - sysinfo.nand_string); - - return 0; -} -#endif /* CONFIG_DISPLAY_BOARDINFO */ - -static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) -{ - u32 i, num_params = *parameters; - u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; - - /* - * copy the parameters to an un-cached area to avoid coherency - * issues - */ - for (i = 0; i < num_params; i++) { - __raw_writel(*parameters, sram_scratch_space); - parameters++; - sram_scratch_space++; - } - - /* Now make the PPA call */ - do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); -} - -void __weak omap3_set_aux_cr_secure(u32 acr) -{ - struct emu_hal_params emu_romcode_params; - - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = acr; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); -} - -void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, - u32 cpu_variant, u32 cpu_rev) -{ - /* Write ACR - affects secure banked bits */ - if (get_device_type() == GP_DEVICE) - omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); - else - omap3_set_aux_cr_secure(acr); - - /* Write ACR - affects non-secure banked bits - some erratas need it */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - - -#ifndef CONFIG_SYS_L2CACHE_OFF -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); - -} - -/* Invalidate the entire L2 cache from secure mode */ -static void omap3_invalidate_l2_cache_secure(void) -{ - if (get_device_type() == GP_DEVICE) { - omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = 0; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, - (u32 *)&emu_romcode_params); - } -} - -void v7_outer_cache_enable(void) -{ - - /* - * Set L2EN - * On some revisions L2EN bit is banked on some revisions it's not - * No harm in setting both banked bits(in fact this is required - * by an erratum) - */ - omap3_update_aux_cr(0x2, 0); -} - -void omap3_outer_cache_disable(void) -{ - /* - * Clear L2EN - * On some revisions L2EN bit is banked on some revisions it's not - * No harm in clearing both banked bits(in fact this is required - * by an erratum) - */ - omap3_update_aux_cr(0, 0x2); -} -#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/cpu/armv7/omap3/boot.c deleted file mode 100644 index 64b242b752b..00000000000 --- a/arch/arm/cpu/armv7/omap3/boot.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * OMAP3 boot - * - * Copyright (C) 2015 Paul Kocialkowski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static u32 boot_devices[] = { - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_NAND, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_MMC2_2, -}; - -u32 omap_sys_boot_device(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - u32 sys_boot; - - /* Grab the first 5 bits of the status register for SYS_BOOT. */ - sys_boot = readl(&ctrl_base->status) & ((1 << 5) - 1); - - if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) - return BOOT_DEVICE_NONE; - - return boot_devices[sys_boot]; -} - -int omap_reboot_mode(char *mode, unsigned int length) -{ - u32 reboot_mode; - char c; - - if (length < 2) - return -1; - - reboot_mode = readl((u32 *)(OMAP34XX_SCRATCHPAD + - OMAP_REBOOT_REASON_OFFSET)); - - c = (reboot_mode >> 24) & 0xff; - if (c != 'B') - return -1; - - c = (reboot_mode >> 16) & 0xff; - if (c != 'M') - return -1; - - c = reboot_mode & 0xff; - - mode[0] = c; - mode[1] = '\0'; - - return 0; -} - -int omap_reboot_mode_clear(void) -{ - writel(0, (u32 *)(OMAP34XX_SCRATCHPAD + OMAP_REBOOT_REASON_OFFSET)); - - return 0; -} - -int omap_reboot_mode_store(char *mode) -{ - u32 reboot_mode; - - reboot_mode = 'B' << 24 | 'M' << 16 | mode[0]; - - writel(reboot_mode, (u32 *)(OMAP34XX_SCRATCHPAD + - OMAP_REBOOT_REASON_OFFSET)); - - return 0; -} diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c deleted file mode 100644 index 006969e780b..00000000000 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ /dev/null @@ -1,799 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * - * Author : - * Manikandan Pillai - * - * Derived from Beagle Board and OMAP3 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/****************************************************************************** - * get_sys_clk_speed() - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *****************************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - struct prm *prm_base = (struct prm *)PRM_BASE; - struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; - struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE; - - val = readl(&prm_base->clksrc_ctrl); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1; - - /* select sys_clk for GPT1 */ - writel(val, &prcm_base->clksel_wkup); - - /* Enable I and F Clocks for GPT1 */ - val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC; - writel(val, &prcm_base->iclken_wkup); - - val = readl(&prcm_base->fclken_wkup) | EN_GPT1; - writel(val, &prcm_base->fclken_wkup); - - writel(0, &gpt1_base->tldr); /* start counting at 0 */ - writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ - - /* enable 32kHz source, determine sys_clk via gauging */ - - /* start time in 20 cycles */ - start = 20 + readl(&s32k_base->s32k_cr); - - /* dead loop till start time */ - while (readl(&s32k_base->s32k_cr) < start); - - /* get start sys_clk count */ - cstart = readl(&gpt1_base->tcrr); - - /* wait for 40 cycles */ - while (readl(&s32k_base->s32k_cr) < (start + 20)) ; - cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * input oscillator clock frequency. - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - switch(osc_clk) { - case S38_4M: - *sys_clkin_sel = 4; - break; - case S26M: - *sys_clkin_sel = 3; - break; - case S19_2M: - *sys_clkin_sel = 2; - break; - case S13M: - *sys_clkin_sel = 1; - break; - case S12M: - default: - *sys_clkin_sel = 0; - } -} - -/* - * OMAP34XX/35XX specific functions - */ - -static void dpll3_init_34xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_core_dpll_param(); - void (*f_lock_pll) (u32, u32, u32, u32); - int xip_safe, p0, p1, p2, p3; - - xip_safe = is_running_in_sram(); - - /* Moving to the right sysclk and ES rev base */ - ptr = ptr + (3 * clk_index) + sil_index; - - if (xip_safe) { - /* - * CORE DPLL - */ - clrsetbits_le32(&prcm_base->clken_pll, - 0x00000007, PLL_FAST_RELOCK_BYPASS); - wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, - LDELAY); - - /* - * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't - * work. write another value and then default value. - */ - - /* CM_CLKSEL1_EMU[DIV_DPLL3] */ - clrsetbits_le32(&prcm_base->clksel1_emu, - 0x001F0000, (CORE_M3X2 + 1) << 16) ; - clrsetbits_le32(&prcm_base->clksel1_emu, - 0x001F0000, CORE_M3X2 << 16); - - /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - clrsetbits_le32(&prcm_base->clksel1_pll, - 0xF8000000, ptr->m2 << 27); - - /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - clrsetbits_le32(&prcm_base->clksel1_pll, - 0x07FF0000, ptr->m << 16); - - /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - clrsetbits_le32(&prcm_base->clksel1_pll, - 0x00007F00, ptr->n << 8); - - /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); - - /* SSI */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x00000F00, CORE_SSI_DIV << 8); - /* FSUSB */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x00000030, CORE_FUSB_DIV << 4); - /* L4 */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x0000000C, CORE_L4_DIV << 2); - /* L3 */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x00000003, CORE_L3_DIV); - /* GFX */ - clrsetbits_le32(&prcm_base->clksel_gfx, - 0x00000007, GFX_DIV); - /* RESET MGR */ - clrsetbits_le32(&prcm_base->clksel_wkup, - 0x00000006, WKUP_RSM << 1); - /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - clrsetbits_le32(&prcm_base->clken_pll, - 0x000000F0, ptr->fsel << 4); - /* LOCK MODE */ - clrsetbits_le32(&prcm_base->clken_pll, - 0x00000007, PLL_LOCK); - - wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, - LDELAY); - } else if (is_running_in_flash()) { - /* - * if running from flash, jump to small relocated code - * area in SRAM. - */ - f_lock_pll = (void *) (SRAM_CLK_CODE); - - p0 = readl(&prcm_base->clken_pll); - clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); - /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); - - p1 = readl(&prcm_base->clksel1_pll); - /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); - /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); - /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); - /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - clrbits_le32(&p1, 0x00000040); - - p2 = readl(&prcm_base->clksel_core); - /* SSI */ - clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); - /* FSUSB */ - clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); - /* L4 */ - clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); - /* L3 */ - clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); - - p3 = (u32)&prcm_base->idlest_ckgen; - - (*f_lock_pll) (p0, p1, p2, p3); - } -} - -static void dpll4_init_34xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_per_dpll_param(); - - /* Moving it to the right sysclk base */ - ptr = ptr + clk_index; - - /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ - clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); - wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); - - /* - * Errata 1.50 Workaround for OMAP3 ES1.0 only - * If using default divisors, write default divisor + 1 - * and then the actual divisor value - */ - /* M6 */ - clrsetbits_le32(&prcm_base->clksel1_emu, - 0x1F000000, (PER_M6X2 + 1) << 24); - clrsetbits_le32(&prcm_base->clksel1_emu, - 0x1F000000, PER_M6X2 << 24); - /* M5 */ - clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); - clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); - /* M4 */ - clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); - clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); - /* M3 */ - clrsetbits_le32(&prcm_base->clksel_dss, - 0x00001F00, (PER_M3X2 + 1) << 8); - clrsetbits_le32(&prcm_base->clksel_dss, - 0x00001F00, PER_M3X2 << 8); - /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ - clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); - clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); - /* Workaround end */ - - /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */ - clrsetbits_le32(&prcm_base->clksel2_pll, - 0x0007FF00, ptr->m << 8); - - /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ - clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); - - /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */ - clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); - - /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ - clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); - wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); -} - -static void dpll5_init_34xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_per2_dpll_param(); - - /* Moving it to the right sysclk base */ - ptr = ptr + clk_index; - - /* PER2 DPLL (DPLL5) */ - clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); - wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); - /* set M2 (usbtll_fck) */ - clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); - /* set m (11-bit multiplier) */ - clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); - /* set n (7-bit divider)*/ - clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); - /* FREQSEL */ - clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); - /* lock mode */ - clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); - wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); -} - -static void mpu_init_34xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_mpu_dpll_param(); - - /* Moving to the right sysclk and ES rev base */ - ptr = ptr + (3 * clk_index) + sil_index; - - /* MPU DPLL (unlocked already) */ - - /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ - clrsetbits_le32(&prcm_base->clksel2_pll_mpu, - 0x0000001F, ptr->m2); - - /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ - clrsetbits_le32(&prcm_base->clksel1_pll_mpu, - 0x0007FF00, ptr->m << 8); - - /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ - clrsetbits_le32(&prcm_base->clksel1_pll_mpu, - 0x0000007F, ptr->n); - - /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */ - clrsetbits_le32(&prcm_base->clken_pll_mpu, - 0x000000F0, ptr->fsel << 4); -} - -static void iva_init_34xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_iva_dpll_param(); - - /* Moving to the right sysclk and ES rev base */ - ptr = ptr + (3 * clk_index) + sil_index; - - /* IVA DPLL */ - /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ - clrsetbits_le32(&prcm_base->clken_pll_iva2, - 0x00000007, PLL_STOP); - wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); - - /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ - clrsetbits_le32(&prcm_base->clksel2_pll_iva2, - 0x0000001F, ptr->m2); - - /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ - clrsetbits_le32(&prcm_base->clksel1_pll_iva2, - 0x0007FF00, ptr->m << 8); - - /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ - clrsetbits_le32(&prcm_base->clksel1_pll_iva2, - 0x0000007F, ptr->n); - - /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */ - clrsetbits_le32(&prcm_base->clken_pll_iva2, - 0x000000F0, ptr->fsel << 4); - - /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ - clrsetbits_le32(&prcm_base->clken_pll_iva2, - 0x00000007, PLL_LOCK); - - wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); -} - -/* - * OMAP3630 specific functions - */ - -static void dpll3_init_36xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); - void (*f_lock_pll) (u32, u32, u32, u32); - int xip_safe, p0, p1, p2, p3; - - xip_safe = is_running_in_sram(); - - /* Moving it to the right sysclk base */ - ptr += clk_index; - - if (xip_safe) { - /* CORE DPLL */ - - /* Select relock bypass: CM_CLKEN_PLL[0:2] */ - clrsetbits_le32(&prcm_base->clken_pll, - 0x00000007, PLL_FAST_RELOCK_BYPASS); - wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, - LDELAY); - - /* CM_CLKSEL1_EMU[DIV_DPLL3] */ - clrsetbits_le32(&prcm_base->clksel1_emu, - 0x001F0000, CORE_M3X2 << 16); - - /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - clrsetbits_le32(&prcm_base->clksel1_pll, - 0xF8000000, ptr->m2 << 27); - - /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - clrsetbits_le32(&prcm_base->clksel1_pll, - 0x07FF0000, ptr->m << 16); - - /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - clrsetbits_le32(&prcm_base->clksel1_pll, - 0x00007F00, ptr->n << 8); - - /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); - - /* SSI */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x00000F00, CORE_SSI_DIV << 8); - /* FSUSB */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x00000030, CORE_FUSB_DIV << 4); - /* L4 */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x0000000C, CORE_L4_DIV << 2); - /* L3 */ - clrsetbits_le32(&prcm_base->clksel_core, - 0x00000003, CORE_L3_DIV); - /* GFX */ - clrsetbits_le32(&prcm_base->clksel_gfx, - 0x00000007, GFX_DIV_36X); - /* RESET MGR */ - clrsetbits_le32(&prcm_base->clksel_wkup, - 0x00000006, WKUP_RSM << 1); - /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - clrsetbits_le32(&prcm_base->clken_pll, - 0x000000F0, ptr->fsel << 4); - /* LOCK MODE */ - clrsetbits_le32(&prcm_base->clken_pll, - 0x00000007, PLL_LOCK); - - wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, - LDELAY); - } else if (is_running_in_flash()) { - /* - * if running from flash, jump to small relocated code - * area in SRAM. - */ - f_lock_pll = (void *) (SRAM_CLK_CODE); - - p0 = readl(&prcm_base->clken_pll); - clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); - /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); - - p1 = readl(&prcm_base->clksel1_pll); - /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); - /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); - /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); - /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - clrbits_le32(&p1, 0x00000040); - - p2 = readl(&prcm_base->clksel_core); - /* SSI */ - clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); - /* FSUSB */ - clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); - /* L4 */ - clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); - /* L3 */ - clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); - - p3 = (u32)&prcm_base->idlest_ckgen; - - (*f_lock_pll) (p0, p1, p2, p3); - } -} - -static void dpll4_init_36xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - struct dpll_per_36x_param *ptr; - - ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param(); - - /* Moving it to the right sysclk base */ - ptr += clk_index; - - /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ - clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); - wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); - - /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */ - clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24); - - /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ - clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); - - /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ - clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4); - - /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */ - clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8); - - /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ - clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); - - /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */ - clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8); - - /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ - clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); - - /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */ - clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12); - - /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ - clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); - wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); -} - -static void dpll5_init_36xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param(); - - /* Moving it to the right sysclk base */ - ptr = ptr + clk_index; - - /* PER2 DPLL (DPLL5) */ - clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); - wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); - /* set M2 (usbtll_fck) */ - clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); - /* set m (11-bit multiplier) */ - clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); - /* set n (7-bit divider)*/ - clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); - /* lock mode */ - clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); - wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); -} - -static void mpu_init_36xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param(); - - /* Moving to the right sysclk */ - ptr += clk_index; - - /* MPU DPLL (unlocked already */ - - /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ - clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); - - /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ - clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); - - /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ - clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); -} - -static void iva_init_36xx(u32 sil_index, u32 clk_index) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param(); - - /* Moving to the right sysclk */ - ptr += clk_index; - - /* IVA DPLL */ - /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ - clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); - wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); - - /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ - clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2); - - /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ - clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8); - - /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ - clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n); - - /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ - clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK); - - wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - u32 clk_index, sil_index = 0; - struct prm *prm_base = (struct prm *)PRM_BASE; - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - - /* - * Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - /* set input crystal speed */ - clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - /* input clock divider */ - clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); - clk_index = sys_clkin_sel / 2; - } else { - /* input clock divider */ - clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); - clk_index = sys_clkin_sel; - } - - if (get_cpu_family() == CPU_OMAP36XX) { - /* - * In warm reset conditions on OMAP36xx/AM/DM37xx - * the rom code incorrectly sets the DPLL4 clock - * input divider to /6.5. Section 3.5.3.3.3.2.1 of - * the AM/DM37x TRM explains that the /6.5 divider - * is used only when the input clock is 13MHz. - * - * If the part is in this cpu family *and* the input - * clock *is not* 13 MHz, then reset the DPLL4 clock - * input divider to /1 as it should never set to /6.5 - * in this case. - */ - if (sys_clkin_sel != 1) { /* 13 MHz */ - /* Bit 8: DPLL4_CLKINP_DIV */ - clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); - } - - /* Unlock MPU DPLL (slows things down, and needed later) */ - clrsetbits_le32(&prcm_base->clken_pll_mpu, - 0x00000007, PLL_LOW_POWER_BYPASS); - wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, - LDELAY); - - dpll3_init_36xx(0, clk_index); - dpll4_init_36xx(0, clk_index); - dpll5_init_36xx(0, clk_index); - iva_init_36xx(0, clk_index); - mpu_init_36xx(0, clk_index); - - /* Lock MPU DPLL to set frequency */ - clrsetbits_le32(&prcm_base->clken_pll_mpu, - 0x00000007, PLL_LOCK); - wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, - LDELAY); - } else { - /* - * The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if (((get_cpu_family() == CPU_OMAP34XX) - && (get_cpu_rev() >= CPU_3XX_ES20)) || - (get_cpu_family() == CPU_AM35XX)) - sil_index = 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - clrsetbits_le32(&prcm_base->clken_pll_mpu, - 0x00000007, PLL_LOW_POWER_BYPASS); - wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, - LDELAY); - - dpll3_init_34xx(sil_index, clk_index); - dpll4_init_34xx(sil_index, clk_index); - dpll5_init_34xx(sil_index, clk_index); - if (get_cpu_family() != CPU_AM35XX) - iva_init_34xx(sil_index, clk_index); - - mpu_init_34xx(sil_index, clk_index); - - /* Lock MPU DPLL to set frequency */ - clrsetbits_le32(&prcm_base->clken_pll_mpu, - 0x00000007, PLL_LOCK); - wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, - LDELAY); - } - - /* Set up GPTimers to sys_clk source only */ - setbits_le32(&prcm_base->clksel_per, 0x000000FF); - setbits_le32(&prcm_base->clksel_wkup, 1); - - sdelay(5000); -} - -/* - * Enable usb ehci uhh, tll clocks - */ -void ehci_clocks_enable(void) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - - /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ - setbits_le32(&prcm_base->iclken_usbhost, 1); - /* - * Enable USBHOST_48M_FCLK (USBHOST_FCLK1) - * and USBHOST_120M_FCLK (USBHOST_FCLK2) - */ - setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); - /* Enable USBTTL_ICLK */ - setbits_le32(&prcm_base->iclken3_core, 0x00000004); - /* Enable USBTTL_FCLK */ - setbits_le32(&prcm_base->fclken3_core, 0x00000004); -} - -/****************************************************************************** - * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...) - *****************************************************************************/ -void per_clocks_enable(void) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - - /* Enable GP2 timer. */ - setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ - setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ - setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ - - /* Enable GP9 timer. */ - setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ - setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */ - setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */ - -#ifdef CONFIG_SYS_NS16550 - /* Enable UART1 clocks */ - setbits_le32(&prcm_base->fclken1_core, 0x00002000); - setbits_le32(&prcm_base->iclken1_core, 0x00002000); - - /* Enable UART2 clocks */ - setbits_le32(&prcm_base->fclken1_core, 0x00004000); - setbits_le32(&prcm_base->iclken1_core, 0x00004000); - - /* UART 3 Clocks */ - setbits_le32(&prcm_base->fclken_per, 0x00000800); - setbits_le32(&prcm_base->iclken_per, 0x00000800); -#endif - -#ifdef CONFIG_OMAP3_GPIO_2 - setbits_le32(&prcm_base->fclken_per, 0x00002000); - setbits_le32(&prcm_base->iclken_per, 0x00002000); -#endif -#ifdef CONFIG_OMAP3_GPIO_3 - setbits_le32(&prcm_base->fclken_per, 0x00004000); - setbits_le32(&prcm_base->iclken_per, 0x00004000); -#endif -#ifdef CONFIG_OMAP3_GPIO_4 - setbits_le32(&prcm_base->fclken_per, 0x00008000); - setbits_le32(&prcm_base->iclken_per, 0x00008000); -#endif -#ifdef CONFIG_OMAP3_GPIO_5 - setbits_le32(&prcm_base->fclken_per, 0x00010000); - setbits_le32(&prcm_base->iclken_per, 0x00010000); -#endif -#ifdef CONFIG_OMAP3_GPIO_6 - setbits_le32(&prcm_base->fclken_per, 0x00020000); - setbits_le32(&prcm_base->iclken_per, 0x00020000); -#endif - -#ifdef CONFIG_SYS_I2C_OMAP34XX - /* Turn on all 3 I2C clocks */ - setbits_le32(&prcm_base->fclken1_core, 0x00038000); - setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ -#endif - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - setbits_le32(&prcm_base->iclken_wkup, 0x00000004); - - if (get_cpu_family() != CPU_AM35XX) - out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON); - - out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON); - out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON); - out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON); - out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON); - out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON); - out_le32(&prcm_base->fclken_dss, FCK_DSS_ON); - out_le32(&prcm_base->iclken_dss, ICK_DSS_ON); - if (get_cpu_family() != CPU_AM35XX) { - out_le32(&prcm_base->fclken_cam, FCK_CAM_ON); - out_le32(&prcm_base->iclken_cam, ICK_CAM_ON); - } - - sdelay(1000); -} diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk deleted file mode 100644 index ad44d638401..00000000000 --- a/arch/arm/cpu/armv7/omap3/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2011 Linaro Limited -# -# (C) Copyright 2010 -# Texas Instruments, -# -# Aneesh V -# -# SPDX-License-Identifier: GPL-2.0+ -# -ifdef CONFIG_SPL_BUILD -ALL-y += MLO -else -ALL-y += u-boot.img -endif diff --git a/arch/arm/cpu/armv7/omap3/emac.c b/arch/arm/cpu/armv7/omap3/emac.c deleted file mode 100644 index 37f4b8b4901..00000000000 --- a/arch/arm/cpu/armv7/omap3/emac.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * - * DaVinci EMAC initialization. - * - * (C) Copyright 2011, Ilya Yanok, Emcraft Systems - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ - u32 reset; - - /* ensure that the module is out of reset */ - reset = readl(&am35x_scm_general_regs->ip_sw_reset); - reset &= ~CPGMACSS_SW_RST; - writel(reset, &am35x_scm_general_regs->ip_sw_reset); - - return davinci_emac_initialize(); -} diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c deleted file mode 100644 index a2aadc98169..00000000000 --- a/arch/arm/cpu/armv7/omap3/emif4.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Author : - * Vaibhav Hiremath - * - * Based on mem.c and sdrc.c - * - * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; -extern omap3_sysinfo sysinfo; - -static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE; - -/* - * is_mem_sdr - - * - Return 1 if mem type in use is SDR - */ -u32 is_mem_sdr(void) -{ - return 0; -} - -/* - * get_sdr_cs_size - - * - Get size of chip select 0/1 - */ -u32 get_sdr_cs_size(u32 cs) -{ - u32 size = 0; - - /* TODO: Calculate the size based on EMIF4 configuration */ - if (cs == CS0) - size = CONFIG_SYS_CS0_SIZE; - - return size; -} - -/* - * get_sdr_cs_offset - - * - Get offset of cs from cs0 start - */ -u32 get_sdr_cs_offset(u32 cs) -{ - u32 offset = 0; - - return offset; -} - -/* - * do_emif4_init - - * - Init the emif4 module for DDR access - * - Early init routines, called from flash or SRAM. - */ -static void do_emif4_init(void) -{ - unsigned int regval; - /* Set the DDR PHY parameters in PHY ctrl registers */ - regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | - EMIF4_DDR1_EXT_STRB_DIS); - writel(regval, &emif4_base->ddr_phyctrl1); - writel(regval, &emif4_base->ddr_phyctrl1_shdw); - writel(0, &emif4_base->ddr_phyctrl2); - - /* Reset the DDR PHY and wait till completed */ - regval = readl(&emif4_base->sdram_iodft_tlgc); - regval |= (1<<10); - writel(regval, &emif4_base->sdram_iodft_tlgc); - /*Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1); - /*Re-verify the DDR PHY status*/ - while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0); - - regval |= (1<<0); - writel(regval, &emif4_base->sdram_iodft_tlgc); - /* Set SDR timing registers */ - regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | - EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | - EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | - EMIF4_TIM1_T_RP); - writel(regval, &emif4_base->sdram_time1); - writel(regval, &emif4_base->sdram_time1_shdw); - - regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | - EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | - EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); - writel(regval, &emif4_base->sdram_time2); - writel(regval, &emif4_base->sdram_time2_shdw); - - regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); - writel(regval, &emif4_base->sdram_time3); - writel(regval, &emif4_base->sdram_time3_shdw); - - /* Set the PWR control register */ - regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | - EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); - writel(regval, &emif4_base->sdram_pwr_mgmt); - writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); - - /* Set the DDR refresh rate control register */ - regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); - writel(regval, &emif4_base->sdram_refresh_ctrl); - writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); - - /* set the SDRAM configuration register */ - regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | - EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | - EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | - EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | - EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | - EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); - writel(regval, &emif4_base->sdram_config); -} - -/* - * dram_init - - * - Sets uboots idea of sdram size - */ -int dram_init(void) -{ - unsigned int size0 = 0, size1 = 0; - - size0 = get_sdr_cs_size(CS0); - /* - * If a second bank of DDR is attached to CS1 this is - * where it can be started. Early init code will init - * memory on CS0. - */ - if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) - size1 = get_sdr_cs_size(CS1); - - gd->ram_size = size0 + size1; - return 0; -} - -void dram_init_banksize (void) -{ - unsigned int size0 = 0, size1 = 0; - - size0 = get_sdr_cs_size(CS0); - size1 = get_sdr_cs_size(CS1); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; -} - -/* - * mem_init() - - * - Initialize memory subsystem - */ -void mem_init(void) -{ - do_emif4_init(); -} diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S deleted file mode 100644 index 1e587723cec..00000000000 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ /dev/null @@ -1,476 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2008 - * Texas Instruments, - * - * Initial Code by: - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * Funtion for making PPA HAL API calls in secure devices - * Input: - * R0 - Service ID - * R1 - paramer list - */ -ENTRY(do_omap3_emu_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Secure Service ID in R12 - MOV r3, r1 @ Copy the pointer to va_list in R3 - MOV r1, #0 @ Process ID - 0 - MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer - @ to va_list in R3 - MOV r6, #0xFF @ Indicate new Task call - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(do_omap3_emu_romcode_call) - -#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -ENTRY(cpy_clk_code) - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* copy from start of go_to_speed... */ - adr r2, lowlevel_init /* ... up to start of low_level_init */ -next2: - ldmia r0!, {r3 - r10} /* copy from source address [r0] */ - stmia r1!, {r3 - r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - blo next2 - mov pc, lr /* back to caller */ -ENDPROC(cpy_clk_code) - -/* *************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this - * code runs from flash before SDR is init so that should be ok. - ****************************************************************************/ -ENTRY(go_to_speed) - stmfd sp!, {r4 - r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4 - r6} - mov pc, lr /* back to caller, locked */ -ENDPROC(go_to_speed) - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -ENTRY(lowlevel_init) - ldr sp, SRAM_STACK - str ip, [sp] /* stash ip register */ - mov ip, lr /* save link reg across call */ -#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) -/* - * No need to copy/exec the clock code - DPLL adjust already done - * in NAND/oneNAND Boot. - */ - ldr r1, =SRAM_CLK_CODE - bl cpy_clk_code -#endif /* NAND Boot */ - mov lr, ip /* restore link reg */ - ldr ip, [sp] /* restore save ip */ - /* tail-call s_init to setup pll, mux, memory */ - b s_init - -ENDPROC(lowlevel_init) - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ - -/* - * Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1 -/* ES2 */ -.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2 -/* 3410 */ -.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12 - -/* 13MHz */ -/* ES1 */ -.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1 -/* ES2 */ -.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2 -/* 3410 */ -.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1 -/* ES2 */ -.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2 -/* 3410 */ -.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2 - -/* 26MHz */ -/* ES1 */ -.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1 -/* ES2 */ -.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2 -/* 3410 */ -.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1 -/* ES2 */ -.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2 -/* 3410 */ -.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1 -/* ES2 */ -.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2 -/* 3410 */ -.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12 - -/* 13MHz */ -/* ES1 */ -.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1 -/* ES2 */ -.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2 -/* 3410 */ -.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1 -/* ES2 */ -.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2 -/* 3410 */ -.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2 - -/* 26MHz */ -/* ES1 */ -.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1 -/* ES2 */ -.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2 -/* 3410 */ -.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1 -/* ES2 */ -.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2 -/* 3410 */ -.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1 -/* ES2 */ -.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 -/* 3410 */ -.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 - -/* 13MHz */ -/* ES1 */ -.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1 -/* ES2 */ -.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 -/* 3410 */ -.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1 -/* ES2 */ -.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 -/* 3410 */ -.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 - -/* 26MHz */ -/* ES1 */ -.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1 -/* ES2 */ -.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 -/* 3410 */ -.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1 -/* ES2 */ -.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 -/* 3410 */ -.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12 - -/* 13MHz */ -.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13 - -/* 19.2MHz */ -.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2 - -/* 26MHz */ -.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26 - -/* 38.4MHz */ -.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - -/* PER2 DPLL values */ -per2_dpll_param: -/* 12MHz */ -.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12 - -/* 13MHz */ -.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13 - -/* 19.2MHz */ -.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2 - -/* 26MHz */ -.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26 - -/* 38.4MHz */ -.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 - -.globl get_per2_dpll_param -get_per2_dpll_param: - adr r0, per2_dpll_param - mov pc, lr - -/* - * Tables for 36XX/37XX devices - * - */ -mpu_36x_dpll_param: -/* 12MHz */ -.word 50, 0, 0, 1 -/* 13MHz */ -.word 600, 12, 0, 1 -/* 19.2MHz */ -.word 125, 3, 0, 1 -/* 26MHz */ -.word 300, 12, 0, 1 -/* 38.4MHz */ -.word 125, 7, 0, 1 - -iva_36x_dpll_param: -/* 12MHz */ -.word 130, 2, 0, 1 -/* 13MHz */ -.word 20, 0, 0, 1 -/* 19.2MHz */ -.word 325, 11, 0, 1 -/* 26MHz */ -.word 10, 0, 0, 1 -/* 38.4MHz */ -.word 325, 23, 0, 1 - -core_36x_dpll_param: -/* 12MHz */ -.word 100, 2, 0, 1 -/* 13MHz */ -.word 400, 12, 0, 1 -/* 19.2MHz */ -.word 375, 17, 0, 1 -/* 26MHz */ -.word 200, 12, 0, 1 -/* 38.4MHz */ -.word 375, 35, 0, 1 - -per_36x_dpll_param: -/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ -.word 12000, 360, 4, 9, 16, 5, 4, 3, 1 -.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 -.word 19200, 360, 7, 9, 16, 5, 4, 3, 1 -.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 -.word 38400, 360, 15, 9, 16, 5, 4, 3, 1 - -per2_36x_dpll_param: -/* 12MHz */ -.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 -/* 13MHz */ -.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 -/* 19.2MHz */ -.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 -/* 26MHz */ -.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 -/* 38.4MHz */ -.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 - - -ENTRY(get_36x_mpu_dpll_param) - adr r0, mpu_36x_dpll_param - mov pc, lr -ENDPROC(get_36x_mpu_dpll_param) - -ENTRY(get_36x_iva_dpll_param) - adr r0, iva_36x_dpll_param - mov pc, lr -ENDPROC(get_36x_iva_dpll_param) - -ENTRY(get_36x_core_dpll_param) - adr r0, core_36x_dpll_param - mov pc, lr -ENDPROC(get_36x_core_dpll_param) - -ENTRY(get_36x_per_dpll_param) - adr r0, per_36x_dpll_param - mov pc, lr -ENDPROC(get_36x_per_dpll_param) - -ENTRY(get_36x_per2_dpll_param) - adr r0, per2_36x_dpll_param - mov pc, lr -ENDPROC(get_36x_per2_dpll_param) diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c deleted file mode 100644 index 4f15ac9cb55..00000000000 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Functions related to OMAP3 SDRC. - * - * This file has been created after exctracting and consolidating - * the SDRC related content from mem.c and board.c, also created - * generic init function (mem_init). - * - * Copyright (C) 2004-2010 - * Texas Instruments Incorporated - http://www.ti.com/ - * - * Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz - * - * Author : - * Vaibhav Hiremath - * - * Original implementation by (mem.c, board.c) : - * Sunil Kumar - * Shashi Ranjan - * Manikandan Pillai - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; -extern omap3_sysinfo sysinfo; - -static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; - -/* - * is_mem_sdr - - * - Return 1 if mem type in use is SDR - */ -u32 is_mem_sdr(void) -{ - if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) - return 1; - return 0; -} - -/* - * make_cs1_contiguous - - * - When we have CS1 populated we want to have it mapped after cs0 to allow - * command line mem=xyz use all memory with out discontinuous support - * compiled in. We could do it in the ATAG, but there really is two banks... - */ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(CS0); - size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); - -} - - -/* - * get_sdr_cs_size - - * - Get size of chip select 0/1 - */ -u32 get_sdr_cs_size(u32 cs) -{ - u32 size; - - /* get ram size field */ - size = readl(&sdrc_base->cs[cs].mcfg) >> 8; - size &= 0x3FF; /* remove unwanted bits */ - size <<= 21; /* multiply by 2 MiB to find size in MB */ - return size; -} - -/* - * get_sdr_cs_offset - - * - Get offset of cs from cs0 start - */ -u32 get_sdr_cs_offset(u32 cs) -{ - u32 offset; - - if (!cs) - return 0; - - offset = readl(&sdrc_base->cs_cfg); - offset = (offset & 15) << 27 | (offset & 0x300) << 17; - - return offset; -} - -/* - * write_sdrc_timings - - * - Takes CS and associated timings and initalize SDRAM - * - Test CS to make sure it's OK for use - */ -static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, - struct board_sdrc_timings *timings) -{ - /* Setup timings we got from the board. */ - writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); - writel(timings->ctrla, &sdrc_actim_base->ctrla); - writel(timings->ctrlb, &sdrc_actim_base->ctrlb); - writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(timings->mr, &sdrc_base->cs[cs].mr); - - /* - * Test ram in this bank - * Disable if bad or not present - */ - if (!mem_ok(cs)) - writel(0, &sdrc_base->cs[cs].mcfg); -} - -/* - * do_sdrc_init - - * - Code called once in C-Stack only context for CS0 and with early being - * true and a possible 2nd time depending on memory configuration from - * stack+global context. - */ -void do_sdrc_init(u32 cs, u32 early) -{ - struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; - struct board_sdrc_timings timings; - - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - - /* set some default timings */ - timings.sharing = SDRC_SHARING; - - /* - * When called in the early context this may be SPL and we will - * need to set all of the timings. This ends up being board - * specific so we call a helper function to take care of this - * for us. Otherwise, to be safe, we need to copy the settings - * from the first bank to the second. We will setup CS0, - * then set cs_cfg to the appropriate value then try and - * setup CS1. - */ -#ifdef CONFIG_SPL_BUILD - /* set/modify board-specific timings */ - get_board_mem_timings(&timings); -#endif - if (early) { - /* reset sdrc controller */ - writel(SOFTRESET, &sdrc_base->sysconfig); - wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, - 12000000); - writel(0, &sdrc_base->sysconfig); - - /* setup sdrc to ball mux */ - writel(timings.sharing, &sdrc_base->sharing); - - /* Disable Power Down of CKE because of 1 CKE on combo part */ - writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, - &sdrc_base->power); - - writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); - sdelay(0x20000); -#ifdef CONFIG_SPL_BUILD - write_sdrc_timings(CS0, sdrc_actim_base0, &timings); - make_cs1_contiguous(); - write_sdrc_timings(CS1, sdrc_actim_base1, &timings); -#endif - - } - - /* - * If we aren't using SPL we have been loaded by some - * other means which may not have correctly initialized - * both CS0 and CS1 (such as some older versions of x-loader) - * so we may be asked now to setup CS1. - */ - if (cs == CS1) { - timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), - timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); - timings.ctrla = readl(&sdrc_actim_base0->ctrla); - timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); - timings.mr = readl(&sdrc_base->cs[CS0].mr); - write_sdrc_timings(cs, sdrc_actim_base1, &timings); - } -} - -/* - * dram_init - - * - Sets uboots idea of sdram size - */ -int dram_init(void) -{ - unsigned int size0 = 0, size1 = 0; - - size0 = get_sdr_cs_size(CS0); - /* - * We always need to have cs_cfg point at where the second - * bank would be, if present. Failure to do so can lead to - * strange situations where memory isn't detected and - * configured correctly. CS0 will already have been setup - * at this point. - */ - make_cs1_contiguous(); - do_sdrc_init(CS1, NOT_EARLY); - size1 = get_sdr_cs_size(CS1); - - gd->ram_size = size0 + size1; - - return 0; -} - -void dram_init_banksize (void) -{ - unsigned int size0 = 0, size1 = 0; - - size0 = get_sdr_cs_size(CS0); - size1 = get_sdr_cs_size(CS1); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; -} - -/* - * mem_init - - * - Init the sdrc chip, - * - Selects CS0 and CS1, - */ -void mem_init(void) -{ - /* only init up first bank here */ - do_sdrc_init(CS0, EARLY_INIT); -} diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c deleted file mode 100644 index 0e2f0a2f6d6..00000000000 --- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2011 - * Texas Instruments, - * - * Author : - * Tom Rini - * - * Initial Code from: - * Richard Woodruff - * Jian Zhang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * Many boards will want to know the results of the NAND_CMD_READID command - * in order to decide what to do about DDR initialization. This function - * allows us to do that very early and to pass those results back to the - * board so it can make whatever decisions need to be made. - */ -int identify_nand_chip(int *mfr, int *id) -{ - int loops = 1000; - - /* Make sure that we have setup GPMC for NAND correctly. */ - set_gpmc_cs0(MTD_DEV_TYPE_NAND); - - sdelay(2000); - - /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { - sdelay(100); - if (--loops == 0) - return 1; - } - writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); - - /* Set the address to read to 0x0 */ - writeb(0x0, &gpmc_cfg->cs[0].nand_adr); - - /* Read off the manufacturer and device id. */ - *mfr = readb(&gpmc_cfg->cs[0].nand_dat); - *id = readb(&gpmc_cfg->cs[0].nand_dat); - - return 0; -} diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c deleted file mode 100644 index 6818fab253c..00000000000 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * - * Author : - * Manikandan Pillai - * - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include /* get mem tables */ -#include -#include - -#include -#include - -extern omap3_sysinfo sysinfo; -static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - -#ifdef CONFIG_DISPLAY_CPUINFO -static char *rev_s[CPU_3XX_MAX_REV] = { - "1.0", - "2.0", - "2.1", - "3.0", - "3.1", - "UNKNOWN", - "UNKNOWN", - "3.1.2"}; - -/* this is the revision table for 37xx CPUs */ -static char *rev_s_37xx[CPU_37XX_MAX_REV] = { - "1.0", - "1.1", - "1.2"}; -#endif /* CONFIG_DISPLAY_CPUINFO */ - -void omap_die_id(unsigned int *die_id) -{ - struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; - - die_id[0] = readl(&id_base->die_id_0); - die_id[1] = readl(&id_base->die_id_1); - die_id[2] = readl(&id_base->die_id_2); - die_id[3] = readl(&id_base->die_id_3); -} - -/****************************************** - * get_cpu_type(void) - extract cpu info - ******************************************/ -u32 get_cpu_type(void) -{ - return readl(&ctrl_base->ctrl_omap_stat); -} - -/****************************************** - * get_cpu_id(void) - extract cpu id - * returns 0 for ES1.0, cpuid otherwise - ******************************************/ -u32 get_cpu_id(void) -{ - struct ctrl_id *id_base; - u32 cpuid = 0; - - /* - * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate between ES1.0 and > ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) { - return 0; - } else { - /* Decode the IDs on > ES1.0 */ - id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE; - - cpuid = readl(&id_base->idcode); - } - - return cpuid; -} - -/****************************************** - * get_cpu_family(void) - extract cpu info - ******************************************/ -u32 get_cpu_family(void) -{ - u16 hawkeye; - u32 cpu_family; - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_OMAP34XX; - - hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; - switch (hawkeye) { - case HAWKEYE_OMAP34XX: - cpu_family = CPU_OMAP34XX; - break; - case HAWKEYE_AM35XX: - cpu_family = CPU_AM35XX; - break; - case HAWKEYE_OMAP36XX: - cpu_family = CPU_OMAP36XX; - break; - default: - cpu_family = CPU_OMAP34XX; - } - - return cpu_family; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_3XX_ES10; - else - return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; -} - -/***************************************************************** - * get_sku_id(void) - read sku_id to get info on max clock rate - *****************************************************************/ -u32 get_sku_id(void) -{ - struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; - return readl(&id_base->sku_id) & SKUID_CLK_MASK; -} - -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = readl(&gpmc_cfg->cs[0].config7); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return b; -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - return WIDTH_16BIT; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) - *************************************************************************/ -#ifdef CONFIG_REVISION_TAG -u32 __weak get_board_rev(void) -{ - return 0x20; -} -#endif - -/******************************************************** - * get_base(); get upper addr of current execution - *******************************************************/ -static u32 get_base(void) -{ - u32 val; - - __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); - val &= 0xF0000000; - val >>= 28; - return val; -} - -/******************************************************** - * is_running_in_flash() - tell if currently running in - * FLASH. - *******************************************************/ -u32 is_running_in_flash(void) -{ - if (get_base() < 4) - return 1; /* in FLASH */ - - return 0; /* running in SRAM or SDRAM */ -} - -/******************************************************** - * is_running_in_sram() - tell if currently running in - * SRAM. - *******************************************************/ -u32 is_running_in_sram(void) -{ - if (get_base() == 4) - return 1; /* in SRAM */ - - return 0; /* running in FLASH or SDRAM */ -} - -/******************************************************** - * is_running_in_sdram() - tell if currently running in - * SDRAM. - *******************************************************/ -u32 is_running_in_sdram(void) -{ - if (get_base() > 4) - return 1; /* in SDRAM */ - - return 0; /* running in SRAM or FLASH */ -} - -/*************************************************************** - * get_boot_type() - Is this an XIP type device or a stream one - * bits 4-0 specify type. Bit 5 says mem/perif - ***************************************************************/ -u32 get_boot_type(void) -{ - return (readl(&ctrl_base->status) & SYSBOOT_MASK); -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8); -} - -#ifdef CONFIG_DISPLAY_CPUINFO -/** - * Print CPU information - */ -int print_cpuinfo (void) -{ - char *cpu_family_s, *cpu_s, *sec_s, *max_clk; - - switch (get_cpu_family()) { - case CPU_OMAP34XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; - break; - case OMAP3515: - cpu_s = "3515"; - break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; - break; - default: - cpu_s = "35XX"; - break; - } - if ((get_cpu_rev() >= CPU_3XX_ES31) && - (get_sku_id() == SKUID_CLK_720MHZ)) - max_clk = "720 MHz"; - else - max_clk = "600 MHz"; - - break; - case CPU_AM35XX: - cpu_family_s = "AM"; - switch (get_cpu_type()) { - case AM3505: - cpu_s = "3505"; - break; - case AM3517: - cpu_s = "3517"; - break; - default: - cpu_s = "35XX"; - break; - } - max_clk = "600 Mhz"; - break; - case CPU_OMAP36XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3730: - cpu_s = "3630/3730"; - break; - default: - cpu_s = "36XX/37XX"; - break; - } - max_clk = "1 Ghz"; - break; - default: - cpu_family_s = "OMAP"; - cpu_s = "35XX"; - max_clk = "600 Mhz"; - } - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - if (CPU_OMAP36XX == get_cpu_family()) - printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n", - cpu_family_s, cpu_s, sec_s, - rev_s_37xx[get_cpu_rev()], max_clk); - else - printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", - cpu_family_s, cpu_s, sec_s, - rev_s[get_cpu_rev()], max_clk); - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig deleted file mode 100644 index 2091dd78151..00000000000 --- a/arch/arm/cpu/armv7/omap4/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if OMAP44XX - -config SPL_EXT_SUPPORT - default y - -config SPL_FAT_SUPPORT - default y - -config SPL_GPIO_SUPPORT - default y - -config SPL_I2C_SUPPORT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - default y - -config SPL_NAND_SUPPORT - default y - -config SPL_POWER_SUPPORT - default y - -config SPL_SERIAL_SUPPORT - default y - -config SPL_DISPLAY_PRINT - default y - -choice - prompt "OMAP4 board select" - optional - -config TARGET_DUOVERO - bool "OMAP4430 Gumstix Duovero" - -config TARGET_OMAP4_PANDA - bool "TI OMAP4 PandaBoard" - -config TARGET_OMAP4_SDP4430 - bool "TI OMAP4 SDP4430" - -config TARGET_KC1 - bool "Amazon Kindle Fire (first generation)" - -endchoice - -config SYS_SOC - default "omap4" - -source "board/gumstix/duovero/Kconfig" -source "board/ti/panda/Kconfig" -source "board/ti/sdp4430/Kconfig" -source "board/amazon/kc1/Kconfig" - -endif diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile deleted file mode 100644 index 564f1f632f3..00000000000 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += boot.o -obj-y += sdram_elpida.o -obj-y += hwinit.o -obj-y += emif.o -obj-y += prcm-regs.o -obj-y += hw_data.o diff --git a/arch/arm/cpu/armv7/omap4/boot.c b/arch/arm/cpu/armv7/omap4/boot.c deleted file mode 100644 index 7f5791e9ed6..00000000000 --- a/arch/arm/cpu/armv7/omap4/boot.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * OMAP4 boot - * - * Copyright (C) 2015 Paul Kocialkowski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -static u32 boot_devices[] = { - BOOT_DEVICE_MMC2, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_NAND, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIPWAIT, - BOOT_DEVICE_NAND, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_ONENAND, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_XIP, - BOOT_DEVICE_MMC2_2, - BOOT_DEVICE_NAND, - BOOT_DEVICE_MMC2_2, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_MMC2_2, - BOOT_DEVICE_MMC2_2, - BOOT_DEVICE_NONE, - BOOT_DEVICE_XIPWAIT, -}; - -u32 omap_sys_boot_device(void) -{ - u32 sys_boot; - - /* Grab the first 5 bits of the status register for SYS_BOOT. */ - sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1); - - if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) - return BOOT_DEVICE_NONE; - - return boot_devices[sys_boot]; -} - -int omap_reboot_mode(char *mode, unsigned int length) -{ - unsigned int limit; - unsigned int i; - - if (length < 2) - return -1; - - if (!warm_reset()) - return -1; - - limit = (length < OMAP_REBOOT_REASON_SIZE) ? length : - OMAP_REBOOT_REASON_SIZE; - - for (i = 0; i < (limit - 1); i++) - mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE + - OMAP_REBOOT_REASON_OFFSET + i)); - - mode[i] = '\0'; - - return 0; -} - -int omap_reboot_mode_clear(void) -{ - writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET)); - - return 0; -} - -int omap_reboot_mode_store(char *mode) -{ - unsigned int i; - - for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++) - writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE + - OMAP_REBOOT_REASON_OFFSET + i)); - - writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE + - OMAP_REBOOT_REASON_OFFSET + i)); - - return 0; -} diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk deleted file mode 100644 index ad44d638401..00000000000 --- a/arch/arm/cpu/armv7/omap4/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2011 Linaro Limited -# -# (C) Copyright 2010 -# Texas Instruments, -# -# Aneesh V -# -# SPDX-License-Identifier: GPL-2.0+ -# -ifdef CONFIG_SPL_BUILD -ALL-y += MLO -else -ALL-y += u-boot.img -endif diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c deleted file mode 100644 index 403c3c6146e..00000000000 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * EMIF programming - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; -u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; -#endif - -#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -/* Base AC Timing values specified by JESD209-2 for 400MHz operation */ -static const struct lpddr2_ac_timings timings_jedec_400_mhz = { - .max_freq = 400000000, - .RL = 6, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 15, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */ -static const struct lpddr2_ac_timings timings_jedec_200_mhz = { - .max_freq = 200000000, - .RL = 3, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 20, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -/* - * Min tCK values specified by JESD209-2 - * Min tCK specifies the minimum duration of some AC timing parameters in terms - * of the number of cycles. If the calculated number of cycles based on the - * absolute time value is less than the min tCK value, min tCK value should - * be used instead. This typically happens at low frequencies. - */ -static const struct lpddr2_min_tck min_tck_jedec = { - .tRL = 3, - .tRP_AB = 3, - .tRCD = 3, - .tWR = 3, - .tRAS_MIN = 3, - .tRRD = 2, - .tWTR = 2, - .tXP = 2, - .tRTP = 2, - .tCKE = 3, - .tCKESR = 3, - .tFAW = 8 -}; - -static const struct lpddr2_ac_timings const* - jedec_ac_timings[MAX_NUM_SPEEDBINS] = { - &timings_jedec_200_mhz, - &timings_jedec_400_mhz -}; - -const struct lpddr2_device_timings jedec_default_timings = { - .ac_timings = jedec_ac_timings, - .min_tck = &min_tck_jedec -}; - -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) -{ - /* Assume Identical devices on EMIF1 & EMIF2 */ - *cs0_device_timings = &jedec_default_timings; - *cs1_device_timings = &jedec_default_timings; -} -#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c deleted file mode 100644 index 02c06c15776..00000000000 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ /dev/null @@ -1,460 +0,0 @@ -/* - * - * HW data initialization for OMAP4 - * - * (C) Copyright 2013 - * Texas Instruments, - * - * Sricharan R - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include - -struct prcm_regs const **prcm = - (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; -struct dplls const **dplls_data = - (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; -struct vcores_data const **omap_vcores = - (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; -struct omap_sys_ctrl_regs const **ctrl = - (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; - -/* - * The M & N values in the following tables are created using the - * following tool: - * tools/omap/clocks_get_m_n.c - * Please use this tool for creating the table for any new frequency. - */ - -/* - * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF - * OMAP4460 OPP_NOM frequency - */ -static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { - {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* - * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) - * OMAP4430 OPP_TURBO frequency - * OMAP4470 OPP_NOM frequency - */ -static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* - * dpll locked at 1200 MHz - MPU clk at 600 MHz - * OMAP4430 OPP_NOM frequency - */ -static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OMAP4460 OPP_NOM frequency */ -/* OMAP4470 OPP_NOM (Low Power) frequency */ -static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OMAP4430 ES1 OPP_NOM frequency */ -static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OMAP4430 ES2.X OPP_NOM frequency */ -static const struct dpll_params - core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { - {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ - {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ - {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ - {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ - {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ - {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ - {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { - {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with sys_clk as source */ -static const struct dpll_params - abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with 32K clock as source */ -static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 -}; - -static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -struct dplls omap4430_dplls_es1 = { - .mpu = mpu_dpll_params_1200mhz, - .core = core_dpll_params_es1_1524mhz, - .per = per_dpll_params_1536mhz, - .iva = iva_dpll_params_1862mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct dplls omap4430_dplls_es20 = { - .mpu = mpu_dpll_params_1200mhz, - .core = core_dpll_params_es2_1600mhz_ddr200mhz, - .per = per_dpll_params_1536mhz, - .iva = iva_dpll_params_1862mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct dplls omap4430_dplls = { - .mpu = mpu_dpll_params_1200mhz, - .core = core_dpll_params_1600mhz, - .per = per_dpll_params_1536mhz, - .iva = iva_dpll_params_1862mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct dplls omap4460_dplls = { - .mpu = mpu_dpll_params_1400mhz, - .core = core_dpll_params_1600mhz, - .per = per_dpll_params_1536mhz, - .iva = iva_dpll_params_1862mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct dplls omap4470_dplls = { - .mpu = mpu_dpll_params_1600mhz, - .core = core_dpll_params_1600mhz, - .per = per_dpll_params_1536mhz, - .iva = iva_dpll_params_1862mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct pmic_data twl6030_4430es1 = { - .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, - .step = 12660, /* 12.66 mV represented in uV */ - /* The code starts at 1 not 0 */ - .start_code = 1, - .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, - .pmic_bus_init = sri2c_init, - .pmic_write = omap_vc_bypass_send_value, -}; - -/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ -struct pmic_data twl6030 = { - .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, - .step = 12660, /* 12.66 mV represented in uV */ - /* The code starts at 1 not 0 */ - .start_code = 1, - .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, - .pmic_bus_init = sri2c_init, - .pmic_write = omap_vc_bypass_send_value, -}; - -struct pmic_data tps62361 = { - .base_offset = TPS62361_BASE_VOLT_MV, - .step = 10000, /* 10 mV represented in uV */ - .start_code = 0, - .gpio = TPS62361_VSEL0_GPIO, - .gpio_en = 1, - .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, - .pmic_bus_init = sri2c_init, - .pmic_write = omap_vc_bypass_send_value, -}; - -struct vcores_data omap4430_volts_es1 = { - .mpu.value = 1325, - .mpu.addr = SMPS_REG_ADDR_VCORE1, - .mpu.pmic = &twl6030_4430es1, - - .core.value = 1200, - .core.addr = SMPS_REG_ADDR_VCORE3, - .core.pmic = &twl6030_4430es1, - - .mm.value = 1200, - .mm.addr = SMPS_REG_ADDR_VCORE2, - .mm.pmic = &twl6030_4430es1, -}; - -struct vcores_data omap4430_volts = { - .mpu.value = 1325, - .mpu.addr = SMPS_REG_ADDR_VCORE1, - .mpu.pmic = &twl6030, - - .core.value = 1200, - .core.addr = SMPS_REG_ADDR_VCORE3, - .core.pmic = &twl6030, - - .mm.value = 1200, - .mm.addr = SMPS_REG_ADDR_VCORE2, - .mm.pmic = &twl6030, -}; - -struct vcores_data omap4460_volts = { - .mpu.value = 1203, - .mpu.addr = TPS62361_REG_ADDR_SET1, - .mpu.pmic = &tps62361, - - .core.value = 1200, - .core.addr = SMPS_REG_ADDR_VCORE1, - .core.pmic = &twl6030, - - .mm.value = 1200, - .mm.addr = SMPS_REG_ADDR_VCORE2, - .mm.pmic = &twl6030, -}; - -/* - * Take closest integer part of the mV value corresponding to a TWL6032 SMPS - * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. - */ -struct vcores_data omap4470_volts = { - .mpu.value = 1202, - .mpu.addr = SMPS_REG_ADDR_SMPS1, - .mpu.pmic = &twl6030, - - .core.value = 1126, - .core.addr = SMPS_REG_ADDR_SMPS2, - .core.pmic = &twl6030, - - .mm.value = 1139, - .mm.addr = SMPS_REG_ADDR_SMPS5, - .mm.pmic = &twl6030, -}; - -/* - * Enable essential clock domains, modules and - * do some additional special settings needed - */ -void enable_basic_clocks(void) -{ - u32 const clk_domains_essential[] = { - (*prcm)->cm_l4per_clkstctrl, - (*prcm)->cm_l3init_clkstctrl, - (*prcm)->cm_memif_clkstctrl, - (*prcm)->cm_l4cfg_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3_gpmc_clkctrl, - (*prcm)->cm_memif_emif_1_clkctrl, - (*prcm)->cm_memif_emif_2_clkctrl, - (*prcm)->cm_l4cfg_l4_cfg_clkctrl, - (*prcm)->cm_wkup_gpio1_clkctrl, - (*prcm)->cm_l4per_gpio2_clkctrl, - (*prcm)->cm_l4per_gpio3_clkctrl, - (*prcm)->cm_l4per_gpio4_clkctrl, - (*prcm)->cm_l4per_gpio5_clkctrl, - (*prcm)->cm_l4per_gpio6_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_wkup_gptimer1_clkctrl, - (*prcm)->cm_l3init_hsmmc1_clkctrl, - (*prcm)->cm_l3init_hsmmc2_clkctrl, - (*prcm)->cm_l4per_gptimer2_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_l4per_uart3_clkctrl, - (*prcm)->cm_l4per_i2c1_clkctrl, - (*prcm)->cm_l4per_i2c2_clkctrl, - (*prcm)->cm_l4per_i2c3_clkctrl, - (*prcm)->cm_l4per_i2c4_clkctrl, - 0 - }; - - /* Enable optional additional functional clock for GPIO4 */ - setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, - GPIO4_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - - /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, - GPTIMER1_CLKCTRL_CLKSEL_MASK); - - /* Enable optional 48M functional clock for USB PHY */ - setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, - USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); - - /* Enable 32 KHz clock for USB PHY */ - setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -void enable_basic_uboot_clocks(void) -{ - u32 const clk_domains_essential[] = { - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3init_hsusbotg_clkctrl, - (*prcm)->cm_l3init_usbphy_clkctrl, - (*prcm)->cm_clksel_usb_60mhz, - (*prcm)->cm_l3init_hsusbtll_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_l4per_mcspi1_clkctrl, - (*prcm)->cm_l3init_hsusbhost_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -void hw_data_init(void) -{ - u32 omap_rev = omap_revision(); - - (*prcm) = &omap4_prcm; - - switch (omap_rev) { - - case OMAP4430_ES1_0: - *dplls_data = &omap4430_dplls_es1; - *omap_vcores = &omap4430_volts_es1; - break; - - case OMAP4430_ES2_0: - *dplls_data = &omap4430_dplls_es20; - *omap_vcores = &omap4430_volts; - break; - - case OMAP4430_ES2_1: - case OMAP4430_ES2_2: - case OMAP4430_ES2_3: - *dplls_data = &omap4430_dplls; - *omap_vcores = &omap4430_volts; - break; - - case OMAP4460_ES1_0: - case OMAP4460_ES1_1: - *dplls_data = &omap4460_dplls; - *omap_vcores = &omap4460_volts; - break; - - case OMAP4470_ES1_0: - *dplls_data = &omap4470_dplls; - *omap_vcores = &omap4470_volts; - break; - - default: - printf("\n INVALID OMAP REVISION "); - } - - *ctrl = &omap4_ctrl; -} diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c deleted file mode 100644 index 7c6638ca80d..00000000000 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * - * Common functions for OMAP4 based boards - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Author : - * Aneesh V - * Steve Sakoman - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; - -static const struct gpio_bank gpio_bank_44xx[6] = { - { (void *)OMAP44XX_GPIO1_BASE }, - { (void *)OMAP44XX_GPIO2_BASE }, - { (void *)OMAP44XX_GPIO3_BASE }, - { (void *)OMAP44XX_GPIO4_BASE }, - { (void *)OMAP44XX_GPIO5_BASE }, - { (void *)OMAP44XX_GPIO6_BASE }, -}; - -const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; - -#ifdef CONFIG_SPL_BUILD -/* - * Some tuning of IOs for optimal power and performance - */ -void do_io_settings(void) -{ - u32 lpddr2io; - - u32 omap4_rev = omap_revision(); - - if (omap4_rev == OMAP4430_ES1_0) - lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; - else if (omap4_rev == OMAP4430_ES2_0) - lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; - else - lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; - - /* EMIF1 */ - writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); - writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); - /* No pull for GR10 as per hw team's recommendation */ - writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - (*ctrl)->control_lpddr2io1_2); - writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); - - /* EMIF2 */ - writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); - writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); - /* No pull for GR10 as per hw team's recommendation */ - writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - (*ctrl)->control_lpddr2io2_2); - writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); - - /* - * Some of these settings (TRIM values) come from eFuse and are - * in turn programmed in the eFuse at manufacturing time after - * calibration of the device. Do the software over-ride only if - * the device is not correctly trimmed - */ - if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { - - writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - (*ctrl)->control_ldosram_iva_voltage_ctrl); - - writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - (*ctrl)->control_ldosram_mpu_voltage_ctrl); - - writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - (*ctrl)->control_ldosram_core_voltage_ctrl); - } - - /* - * Over-ride the register - * i. unconditionally for all 4430 - * ii. only if un-trimmed for 4460 - */ - if (!readl((*ctrl)->control_efuse_1)) - writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); - - if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) - writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); -} -#endif /* CONFIG_SPL_BUILD */ - -/* dummy fuction for omap4 */ -void config_data_eye_leveling_samples(u32 emif_base) -{ -} - -void init_omap_revision(void) -{ - /* - * For some of the ES2/ES1 boards ID_CODE is not reliable: - * Also, ES1 and ES2 have different ARM revisions - * So use ARM revision for identification - */ - unsigned int arm_rev = cortex_rev(); - - switch (arm_rev) { - case MIDR_CORTEX_A9_R0P1: - *omap_si_rev = OMAP4430_ES1_0; - break; - case MIDR_CORTEX_A9_R1P2: - switch (readl(CONTROL_ID_CODE)) { - case OMAP4_CONTROL_ID_CODE_ES2_0: - *omap_si_rev = OMAP4430_ES2_0; - break; - case OMAP4_CONTROL_ID_CODE_ES2_1: - *omap_si_rev = OMAP4430_ES2_1; - break; - case OMAP4_CONTROL_ID_CODE_ES2_2: - *omap_si_rev = OMAP4430_ES2_2; - break; - default: - *omap_si_rev = OMAP4430_ES2_0; - break; - } - break; - case MIDR_CORTEX_A9_R1P3: - *omap_si_rev = OMAP4430_ES2_3; - break; - case MIDR_CORTEX_A9_R2P10: - switch (readl(CONTROL_ID_CODE)) { - case OMAP4470_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP4470_ES1_0; - break; - case OMAP4460_CONTROL_ID_CODE_ES1_1: - *omap_si_rev = OMAP4460_ES1_1; - break; - case OMAP4460_CONTROL_ID_CODE_ES1_0: - default: - *omap_si_rev = OMAP4460_ES1_0; - break; - } - break; - default: - *omap_si_rev = OMAP4430_SILICON_ID_INVALID; - break; - } -} - -void omap_die_id(unsigned int *die_id) -{ - die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); - die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); - die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); - die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); -} - -#ifndef CONFIG_SYS_L2CACHE_OFF -void v7_outer_cache_enable(void) -{ - omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); -} - -void v7_outer_cache_disable(void) -{ - omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); -} -#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c deleted file mode 100644 index 2f0e1e851ac..00000000000 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * - * HW regs data for OMAP4 - * - * (C) Copyright 2013 - * Texas Instruments, - * - * Sricharan R - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -struct prcm_regs const omap4_prcm = { - /* cm1.ckgen */ - .cm_clksel_core = 0x4a004100, - .cm_clksel_abe = 0x4a004108, - .cm_dll_ctrl = 0x4a004110, - .cm_clkmode_dpll_core = 0x4a004120, - .cm_idlest_dpll_core = 0x4a004124, - .cm_autoidle_dpll_core = 0x4a004128, - .cm_clksel_dpll_core = 0x4a00412c, - .cm_div_m2_dpll_core = 0x4a004130, - .cm_div_m3_dpll_core = 0x4a004134, - .cm_div_m4_dpll_core = 0x4a004138, - .cm_div_m5_dpll_core = 0x4a00413c, - .cm_div_m6_dpll_core = 0x4a004140, - .cm_div_m7_dpll_core = 0x4a004144, - .cm_ssc_deltamstep_dpll_core = 0x4a004148, - .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, - .cm_emu_override_dpll_core = 0x4a004150, - .cm_clkmode_dpll_mpu = 0x4a004160, - .cm_idlest_dpll_mpu = 0x4a004164, - .cm_autoidle_dpll_mpu = 0x4a004168, - .cm_clksel_dpll_mpu = 0x4a00416c, - .cm_div_m2_dpll_mpu = 0x4a004170, - .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, - .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, - .cm_bypclk_dpll_mpu = 0x4a00419c, - .cm_clkmode_dpll_iva = 0x4a0041a0, - .cm_idlest_dpll_iva = 0x4a0041a4, - .cm_autoidle_dpll_iva = 0x4a0041a8, - .cm_clksel_dpll_iva = 0x4a0041ac, - .cm_div_m4_dpll_iva = 0x4a0041b8, - .cm_div_m5_dpll_iva = 0x4a0041bc, - .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, - .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, - .cm_bypclk_dpll_iva = 0x4a0041dc, - .cm_clkmode_dpll_abe = 0x4a0041e0, - .cm_idlest_dpll_abe = 0x4a0041e4, - .cm_autoidle_dpll_abe = 0x4a0041e8, - .cm_clksel_dpll_abe = 0x4a0041ec, - .cm_div_m2_dpll_abe = 0x4a0041f0, - .cm_div_m3_dpll_abe = 0x4a0041f4, - .cm_ssc_deltamstep_dpll_abe = 0x4a004208, - .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, - .cm_clkmode_dpll_ddrphy = 0x4a004220, - .cm_idlest_dpll_ddrphy = 0x4a004224, - .cm_autoidle_dpll_ddrphy = 0x4a004228, - .cm_clksel_dpll_ddrphy = 0x4a00422c, - .cm_div_m2_dpll_ddrphy = 0x4a004230, - .cm_div_m4_dpll_ddrphy = 0x4a004238, - .cm_div_m5_dpll_ddrphy = 0x4a00423c, - .cm_div_m6_dpll_ddrphy = 0x4a004240, - .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, - .cm_shadow_freq_config1 = 0x4a004260, - .cm_mpu_mpu_clkctrl = 0x4a004320, - - /* cm1.dsp */ - .cm_dsp_clkstctrl = 0x4a004400, - .cm_dsp_dsp_clkctrl = 0x4a004420, - - /* cm1.abe */ - .cm1_abe_clkstctrl = 0x4a004500, - .cm1_abe_l4abe_clkctrl = 0x4a004520, - .cm1_abe_aess_clkctrl = 0x4a004528, - .cm1_abe_pdm_clkctrl = 0x4a004530, - .cm1_abe_dmic_clkctrl = 0x4a004538, - .cm1_abe_mcasp_clkctrl = 0x4a004540, - .cm1_abe_mcbsp1_clkctrl = 0x4a004548, - .cm1_abe_mcbsp2_clkctrl = 0x4a004550, - .cm1_abe_mcbsp3_clkctrl = 0x4a004558, - .cm1_abe_slimbus_clkctrl = 0x4a004560, - .cm1_abe_timer5_clkctrl = 0x4a004568, - .cm1_abe_timer6_clkctrl = 0x4a004570, - .cm1_abe_timer7_clkctrl = 0x4a004578, - .cm1_abe_timer8_clkctrl = 0x4a004580, - .cm1_abe_wdt3_clkctrl = 0x4a004588, - - /* cm2.ckgen */ - .cm_clksel_mpu_m3_iss_root = 0x4a008100, - .cm_clksel_usb_60mhz = 0x4a008104, - .cm_scale_fclk = 0x4a008108, - .cm_core_dvfs_perf1 = 0x4a008110, - .cm_core_dvfs_perf2 = 0x4a008114, - .cm_core_dvfs_perf3 = 0x4a008118, - .cm_core_dvfs_perf4 = 0x4a00811c, - .cm_core_dvfs_current = 0x4a008124, - .cm_iva_dvfs_perf_tesla = 0x4a008128, - .cm_iva_dvfs_perf_ivahd = 0x4a00812c, - .cm_iva_dvfs_perf_abe = 0x4a008130, - .cm_iva_dvfs_current = 0x4a008138, - .cm_clkmode_dpll_per = 0x4a008140, - .cm_idlest_dpll_per = 0x4a008144, - .cm_autoidle_dpll_per = 0x4a008148, - .cm_clksel_dpll_per = 0x4a00814c, - .cm_div_m2_dpll_per = 0x4a008150, - .cm_div_m3_dpll_per = 0x4a008154, - .cm_div_m4_dpll_per = 0x4a008158, - .cm_div_m5_dpll_per = 0x4a00815c, - .cm_div_m6_dpll_per = 0x4a008160, - .cm_div_m7_dpll_per = 0x4a008164, - .cm_ssc_deltamstep_dpll_per = 0x4a008168, - .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, - .cm_emu_override_dpll_per = 0x4a008170, - .cm_clkmode_dpll_usb = 0x4a008180, - .cm_idlest_dpll_usb = 0x4a008184, - .cm_autoidle_dpll_usb = 0x4a008188, - .cm_clksel_dpll_usb = 0x4a00818c, - .cm_div_m2_dpll_usb = 0x4a008190, - .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, - .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, - .cm_clkdcoldo_dpll_usb = 0x4a0081b4, - .cm_clkmode_dpll_unipro = 0x4a0081c0, - .cm_idlest_dpll_unipro = 0x4a0081c4, - .cm_autoidle_dpll_unipro = 0x4a0081c8, - .cm_clksel_dpll_unipro = 0x4a0081cc, - .cm_div_m2_dpll_unipro = 0x4a0081d0, - .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, - .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, - .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, - - /* cm2.core */ - .cm_l3_1_clkstctrl = 0x4a008700, - .cm_l3_1_dynamicdep = 0x4a008708, - .cm_l3_1_l3_1_clkctrl = 0x4a008720, - .cm_l3_2_clkstctrl = 0x4a008800, - .cm_l3_2_dynamicdep = 0x4a008808, - .cm_l3_2_l3_2_clkctrl = 0x4a008820, - .cm_l3_gpmc_clkctrl = 0x4a008828, - .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, - .cm_mpu_m3_clkstctrl = 0x4a008900, - .cm_mpu_m3_staticdep = 0x4a008904, - .cm_mpu_m3_dynamicdep = 0x4a008908, - .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, - .cm_sdma_clkstctrl = 0x4a008a00, - .cm_sdma_staticdep = 0x4a008a04, - .cm_sdma_dynamicdep = 0x4a008a08, - .cm_sdma_sdma_clkctrl = 0x4a008a20, - .cm_memif_clkstctrl = 0x4a008b00, - .cm_memif_dmm_clkctrl = 0x4a008b20, - .cm_memif_emif_fw_clkctrl = 0x4a008b28, - .cm_memif_emif_1_clkctrl = 0x4a008b30, - .cm_memif_emif_2_clkctrl = 0x4a008b38, - .cm_memif_dll_clkctrl = 0x4a008b40, - .cm_memif_emif_h1_clkctrl = 0x4a008b50, - .cm_memif_emif_h2_clkctrl = 0x4a008b58, - .cm_memif_dll_h_clkctrl = 0x4a008b60, - .cm_c2c_clkstctrl = 0x4a008c00, - .cm_c2c_staticdep = 0x4a008c04, - .cm_c2c_dynamicdep = 0x4a008c08, - .cm_c2c_sad2d_clkctrl = 0x4a008c20, - .cm_c2c_modem_icr_clkctrl = 0x4a008c28, - .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, - .cm_l4cfg_clkstctrl = 0x4a008d00, - .cm_l4cfg_dynamicdep = 0x4a008d08, - .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, - .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, - .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, - .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, - .cm_l3instr_clkstctrl = 0x4a008e00, - .cm_l3instr_l3_3_clkctrl = 0x4a008e20, - .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, - .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40, - .cm_ivahd_clkstctrl = 0x4a008f00, - - /* cm2.ivahd */ - .cm_ivahd_ivahd_clkctrl = 0x4a008f20, - .cm_ivahd_sl2_clkctrl = 0x4a008f28, - - /* cm2.cam */ - .cm_cam_clkstctrl = 0x4a009000, - .cm_cam_iss_clkctrl = 0x4a009020, - .cm_cam_fdif_clkctrl = 0x4a009028, - - /* cm2.dss */ - .cm_dss_clkstctrl = 0x4a009100, - .cm_dss_dss_clkctrl = 0x4a009120, - - /* cm2.sgx */ - .cm_sgx_clkstctrl = 0x4a009200, - .cm_sgx_sgx_clkctrl = 0x4a009220, - - /* cm2.l3init */ - .cm_l3init_clkstctrl = 0x4a009300, - .cm_l3init_hsmmc1_clkctrl = 0x4a009328, - .cm_l3init_hsmmc2_clkctrl = 0x4a009330, - .cm_l3init_hsi_clkctrl = 0x4a009338, - .cm_l3init_hsusbhost_clkctrl = 0x4a009358, - .cm_l3init_hsusbotg_clkctrl = 0x4a009360, - .cm_l3init_hsusbtll_clkctrl = 0x4a009368, - .cm_l3init_p1500_clkctrl = 0x4a009378, - .cm_l3init_fsusb_clkctrl = 0x4a0093d0, - .cm_l3init_usbphy_clkctrl = 0x4a0093e0, - - /* cm2.l4per */ - .cm_l4per_clkstctrl = 0x4a009400, - .cm_l4per_dynamicdep = 0x4a009408, - .cm_l4per_adc_clkctrl = 0x4a009420, - .cm_l4per_gptimer10_clkctrl = 0x4a009428, - .cm_l4per_gptimer11_clkctrl = 0x4a009430, - .cm_l4per_gptimer2_clkctrl = 0x4a009438, - .cm_l4per_gptimer3_clkctrl = 0x4a009440, - .cm_l4per_gptimer4_clkctrl = 0x4a009448, - .cm_l4per_gptimer9_clkctrl = 0x4a009450, - .cm_l4per_elm_clkctrl = 0x4a009458, - .cm_l4per_gpio2_clkctrl = 0x4a009460, - .cm_l4per_gpio3_clkctrl = 0x4a009468, - .cm_l4per_gpio4_clkctrl = 0x4a009470, - .cm_l4per_gpio5_clkctrl = 0x4a009478, - .cm_l4per_gpio6_clkctrl = 0x4a009480, - .cm_l4per_hdq1w_clkctrl = 0x4a009488, - .cm_l4per_hecc1_clkctrl = 0x4a009490, - .cm_l4per_hecc2_clkctrl = 0x4a009498, - .cm_l4per_i2c1_clkctrl = 0x4a0094a0, - .cm_l4per_i2c2_clkctrl = 0x4a0094a8, - .cm_l4per_i2c3_clkctrl = 0x4a0094b0, - .cm_l4per_i2c4_clkctrl = 0x4a0094b8, - .cm_l4per_l4per_clkctrl = 0x4a0094c0, - .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, - .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, - .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0, - .cm_l4per_mgate_clkctrl = 0x4a0094e8, - .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, - .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, - .cm_l4per_mcspi3_clkctrl = 0x4a009500, - .cm_l4per_mcspi4_clkctrl = 0x4a009508, - .cm_l4per_mmcsd3_clkctrl = 0x4a009520, - .cm_l4per_mmcsd4_clkctrl = 0x4a009528, - .cm_l4per_msprohg_clkctrl = 0x4a009530, - .cm_l4per_slimbus2_clkctrl = 0x4a009538, - .cm_l4per_uart1_clkctrl = 0x4a009540, - .cm_l4per_uart2_clkctrl = 0x4a009548, - .cm_l4per_uart3_clkctrl = 0x4a009550, - .cm_l4per_uart4_clkctrl = 0x4a009558, - .cm_l4per_mmcsd5_clkctrl = 0x4a009560, - .cm_l4per_i2c5_clkctrl = 0x4a009568, - .cm_l4sec_clkstctrl = 0x4a009580, - .cm_l4sec_staticdep = 0x4a009584, - .cm_l4sec_dynamicdep = 0x4a009588, - .cm_l4sec_aes1_clkctrl = 0x4a0095a0, - .cm_l4sec_aes2_clkctrl = 0x4a0095a8, - .cm_l4sec_des3des_clkctrl = 0x4a0095b0, - .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, - .cm_l4sec_rng_clkctrl = 0x4a0095c0, - .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, - .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, - - /* l4 wkup regs */ - .cm_abe_pll_ref_clksel = 0x4a30610c, - .cm_sys_clksel = 0x4a306110, - .cm_wkup_clkstctrl = 0x4a307800, - .cm_wkup_l4wkup_clkctrl = 0x4a307820, - .cm_wkup_wdtimer1_clkctrl = 0x4a307828, - .cm_wkup_wdtimer2_clkctrl = 0x4a307830, - .cm_wkup_gpio1_clkctrl = 0x4a307838, - .cm_wkup_gptimer1_clkctrl = 0x4a307840, - .cm_wkup_gptimer12_clkctrl = 0x4a307848, - .cm_wkup_synctimer_clkctrl = 0x4a307850, - .cm_wkup_usim_clkctrl = 0x4a307858, - .cm_wkup_sarram_clkctrl = 0x4a307860, - .cm_wkup_keyboard_clkctrl = 0x4a307878, - .cm_wkup_rtc_clkctrl = 0x4a307880, - .cm_wkup_bandgap_clkctrl = 0x4a307888, - .prm_vc_val_bypass = 0x4a307ba0, - .prm_vc_cfg_channel = 0x4a307ba4, - .prm_vc_cfg_i2c_mode = 0x4a307ba8, - .prm_vc_cfg_i2c_clk = 0x4a307bac, -}; - -struct omap_sys_ctrl_regs const omap4_ctrl = { - .control_status = 0x4A0022C4, - .control_std_fuse_die_id_0 = 0x4A002200, - .control_std_fuse_die_id_1 = 0x4A002208, - .control_std_fuse_die_id_2 = 0x4A00220C, - .control_std_fuse_die_id_3 = 0x4A002210, - .control_std_fuse_opp_bgap = 0x4a002260, - .control_status = 0x4a0022c4, - .control_ldosram_iva_voltage_ctrl = 0x4A002320, - .control_ldosram_mpu_voltage_ctrl = 0x4A002324, - .control_ldosram_core_voltage_ctrl = 0x4A002328, - .control_usbotghs_ctrl = 0x4A00233C, - .control_padconf_core_base = 0x4A100000, - .control_pbiaslite = 0x4A100600, - .control_lpddr2io1_0 = 0x4A100638, - .control_lpddr2io1_1 = 0x4A10063C, - .control_lpddr2io1_2 = 0x4A100640, - .control_lpddr2io1_3 = 0x4A100644, - .control_lpddr2io2_0 = 0x4A100648, - .control_lpddr2io2_1 = 0x4A10064C, - .control_lpddr2io2_2 = 0x4A100650, - .control_lpddr2io2_3 = 0x4A100654, - .control_efuse_1 = 0x4A100700, - .control_efuse_2 = 0x4A100704, - .control_padconf_wkup_base = 0x4A31E000, -}; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c deleted file mode 100644 index 78b4f09ce24..00000000000 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Timing and Organization details of the Elpida parts used in OMAP4 - * SDPs and Panda - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* - * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430 - * SDP and Panda. Since the parts used and geometry are identical for - * SDP and Panda for a given OMAP4 revision, this information is kept - * here instead of being in board directory. However the key functions - * exported are weakly linked so that they can be over-ridden in the board - * directory if there is a OMAP4 board in the future that uses a different - * memory device or geometry. - * - * For any new board with different memory devices over-ride one or more - * of the following functions as per the CONFIG flags you intend to enable: - * - emif_get_reg_dump() - * - emif_get_dmm_regs() - * - emif_get_device_details() - * - emif_get_device_timings() - */ - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -const struct emif_regs emif_regs_elpida_200_mhz_2cs = { - .sdram_config_init = 0x80000eb9, - .sdram_config = 0x80001ab9, - .ref_ctrl = 0x0000030c, - .sdram_tim1 = 0x08648311, - .sdram_tim2 = 0x101b06ca, - .sdram_tim3 = 0x0048a19f, - .read_idle_ctrl = 0x000501ff, - .zq_config = 0x500b3214, - .temp_alert_config = 0xd8016893, - .emif_ddr_phy_ctlr_1_init = 0x049ffff5, - .emif_ddr_phy_ctlr_1 = 0x049ff808 -}; - -const struct emif_regs emif_regs_elpida_380_mhz_1cs = { - .sdram_config_init = 0x80000eb1, - .sdram_config = 0x80001ab1, - .ref_ctrl = 0x000005cd, - .sdram_tim1 = 0x10cb0622, - .sdram_tim2 = 0x20350d52, - .sdram_tim3 = 0x00b1431f, - .read_idle_ctrl = 0x000501ff, - .zq_config = 0x500b3214, - .temp_alert_config = 0x58016893, - .emif_ddr_phy_ctlr_1_init = 0x049ffff5, - .emif_ddr_phy_ctlr_1 = 0x049ff418 -}; - -const struct emif_regs emif_regs_elpida_400_mhz_1cs = { - .sdram_config_init = 0x80800eb2, - .sdram_config = 0x80801ab2, - .ref_ctrl = 0x00000618, - .sdram_tim1 = 0x10eb0662, - .sdram_tim2 = 0x20370dd2, - .sdram_tim3 = 0x00b1c33f, - .read_idle_ctrl = 0x000501ff, - .zq_config = 0x500b3215, - .temp_alert_config = 0x58016893, - .emif_ddr_phy_ctlr_1_init = 0x049ffff5, - .emif_ddr_phy_ctlr_1 = 0x049ff418 -}; - -const struct emif_regs emif_regs_elpida_400_mhz_2cs = { - .sdram_config_init = 0x80000eb9, - .sdram_config = 0x80001ab9, - .ref_ctrl = 0x00000618, - .sdram_tim1 = 0x10eb0662, - .sdram_tim2 = 0x20370dd2, - .sdram_tim3 = 0x00b1c33f, - .read_idle_ctrl = 0x000501ff, - .zq_config = 0xd00b3214, - .temp_alert_config = 0xd8016893, - .emif_ddr_phy_ctlr_1_init = 0x049ffff5, - .emif_ddr_phy_ctlr_1 = 0x049ff418 -}; - -const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0xFF020100, - .dmm_lisa_map_1 = 0, - .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80540300, - .is_ma_present = 0x0 -}; - -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { - .dmm_lisa_map_0 = 0xFF020100, - .dmm_lisa_map_1 = 0, - .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80640300, - .is_ma_present = 0x0 -}; - -const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { - .dmm_lisa_map_0 = 0xFF020100, - .dmm_lisa_map_1 = 0, - .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80640300, - .is_ma_present = 0x1 -}; - -static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) -{ - u32 omap4_rev = omap_revision(); - - /* Same devices and geometry on both EMIFs */ - if (omap4_rev == OMAP4430_ES1_0) - *regs = &emif_regs_elpida_380_mhz_1cs; - else if (omap4_rev == OMAP4430_ES2_0) - *regs = &emif_regs_elpida_200_mhz_2cs; - else if (omap4_rev < OMAP4470_ES1_0) - *regs = &emif_regs_elpida_400_mhz_2cs; - else - *regs = &emif_regs_elpida_400_mhz_1cs; -} -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) - __attribute__((weak, alias("emif_get_reg_dump_sdp"))); - -static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs - **dmm_lisa_regs) -{ - u32 omap_rev = omap_revision(); - - if (omap_rev == OMAP4430_ES1_0) - *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; - else if (omap_rev < OMAP4460_ES1_0) - *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; - else - *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; -} - -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) - __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); - -#else - -const struct lpddr2_device_details elpida_2G_S4_details = { - .type = LPDDR2_TYPE_S4, - .density = LPDDR2_DENSITY_2Gb, - .io_width = LPDDR2_IO_WIDTH_32, - .manufacturer = LPDDR2_MANUFACTURER_ELPIDA -}; - -const struct lpddr2_device_details elpida_4G_S4_details = { - .type = LPDDR2_TYPE_S4, - .density = LPDDR2_DENSITY_4Gb, - .io_width = LPDDR2_IO_WIDTH_32, - .manufacturer = LPDDR2_MANUFACTURER_ELPIDA -}; - -struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details) -{ - u32 omap_rev = omap_revision(); - - /* EMIF1 & EMIF2 have identical configuration */ - if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) - && (cs == CS1)) { - /* Nothing connected on CS1 for 4430/4470 ES1.0 */ - return NULL; - } else if (omap_rev < OMAP4470_ES1_0) { - /* In all other 4430/4460 cases Elpida 2G device */ - *lpddr2_dev_details = elpida_2G_S4_details; - } else { - /* 4470: 4G device */ - *lpddr2_dev_details = elpida_4G_S4_details; - } - return lpddr2_dev_details; -} - -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details) - __attribute__((weak, alias("emif_get_device_details_sdp"))); - -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - -#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -static const struct lpddr2_ac_timings timings_elpida_400_mhz = { - .max_freq = 400000000, - .RL = 6, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 15, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -static const struct lpddr2_ac_timings timings_elpida_333_mhz = { - .max_freq = 333000000, - .RL = 5, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 15, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -static const struct lpddr2_ac_timings timings_elpida_200_mhz = { - .max_freq = 200000000, - .RL = 3, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 20, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -static const struct lpddr2_min_tck min_tck_elpida = { - .tRL = 3, - .tRP_AB = 3, - .tRCD = 3, - .tWR = 3, - .tRAS_MIN = 3, - .tRRD = 2, - .tWTR = 2, - .tXP = 2, - .tRTP = 2, - .tCKE = 3, - .tCKESR = 3, - .tFAW = 8 -}; - -static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { - &timings_elpida_200_mhz, - &timings_elpida_333_mhz, - &timings_elpida_400_mhz -}; - -const struct lpddr2_device_timings elpida_2G_S4_timings = { - .ac_timings = elpida_ac_timings, - .min_tck = &min_tck_elpida, -}; - -void emif_get_device_timings_sdp(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) -{ - u32 omap_rev = omap_revision(); - - /* Identical devices on EMIF1 & EMIF2 */ - *cs0_device_timings = &elpida_2G_S4_timings; - - if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) - *cs1_device_timings = NULL; - else - *cs1_device_timings = &elpida_2G_S4_timings; -} - -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) - __attribute__((weak, alias("emif_get_device_timings_sdp"))); - -#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ - -const struct lpddr2_mr_regs mr_regs = { - .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3, - .mr2 = 0x4, - .mr3 = -1, - .mr10 = MR10_ZQ_ZQINIT, - .mr16 = MR16_REF_FULL_ARRAY -}; - -void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) -{ - *regs = &mr_regs; -} - -__weak const struct read_write_regs *get_bug_regs(u32 *iterations) -{ - return 0; -} diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig deleted file mode 100644 index 22259dcc5cf..00000000000 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ /dev/null @@ -1,94 +0,0 @@ -if OMAP54XX - -config SPL_EXT_SUPPORT - default y - -config SPL_FAT_SUPPORT - default y - -config SPL_GPIO_SUPPORT - default y - -config SPL_I2C_SUPPORT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - default y - -config SPL_NAND_SUPPORT - default y - -config SPL_POWER_SUPPORT - default y - -config SPL_SERIAL_SUPPORT - default y - -config SPL_DISPLAY_PRINT - default y - -choice - prompt "OMAP5 board select" - optional - -config TARGET_CM_T54 - bool "CompuLab CM-T54" - -config TARGET_OMAP5_UEVM - bool "TI OMAP5 uEVM board" - -config TARGET_DRA7XX_EVM - bool "TI DRA7XX" - select TI_I2C_BOARD_DETECT - select PHYS_64BIT - -config TARGET_AM57XX_EVM - bool "AM57XX" - select TI_I2C_BOARD_DETECT - -endchoice - -config SYS_SOC - default "omap5" - -config TI_SECURE_EMIF_REGION_START - hex "Reserved EMIF region start address" - depends on TI_SECURE_DEVICE - default 0x0 - help - Reserved EMIF region start address. Set to "0" to auto-select - to be at the end of the external memory region. - -config TI_SECURE_EMIF_TOTAL_REGION_SIZE - hex "Reserved EMIF region size" - depends on TI_SECURE_DEVICE - default 0x0 - help - Total reserved EMIF region size. Default is 0, which means no reserved EMIF - region on secure devices. - -config TI_SECURE_EMIF_PROTECTED_REGION_SIZE - hex "Size of protected region within reserved EMIF region" - depends on TI_SECURE_DEVICE - default 0x0 - help - This config option is used to specify the size of the portion of the total - reserved EMIF region set aside for secure OS needs that will be protected - using hardware memory firewalls. This value must be smaller than the - TI_SECURE_EMIF_TOTAL_REGION_SIZE value. - -source "board/compulab/cm_t54/Kconfig" -source "board/ti/omap5_uevm/Kconfig" -source "board/ti/dra7xx/Kconfig" -source "board/ti/am57xx/Kconfig" - -endif diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile deleted file mode 100644 index 0212df73c15..00000000000 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += boot.o -obj-y += hwinit.o -obj-y += emif.o -obj-y += sdram.o -obj-y += prcm-regs.o -obj-y += hw_data.o -obj-y += abb.o -obj-y += fdt.o -obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o -obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c deleted file mode 100644 index 3bf88979e5d..00000000000 --- a/arch/arm/cpu/armv7/omap5/abb.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Adaptive Body Bias programming sequence for OMAP5 family - * - * (C) Copyright 2013 - * Texas Instruments, - * - * Andrii Tseglytskyi - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Setup LDOVBB for OMAP5. - * On OMAP5+ some ABB settings are fused. They are handled - * in the following way: - * - * 1. corresponding EFUSE register contains ABB enable bit - * and VSET value - * 2. If ABB enable bit is set to 1, than ABB should be - * enabled, otherwise ABB should be disabled - * 3. If ABB is enabled, than VSET value should be copied - * to corresponding MUX control register - */ -s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) -{ - u32 vset; - u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; - u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; - - if (!is_omap54xx()) { - /* DRA7 */ - fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK; - fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK; - } - /* - * ABB parameters must be properly fused - * otherwise ABB should be disabled - */ - vset = readl(fuse); - if (!(vset & fuse_enable_mask)) - return -1; - - /* prepare VSET value for LDOVBB mux register */ - vset &= fuse_vset_mask; - vset >>= ffs(fuse_vset_mask) - 1; - vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; - vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; - - /* setup LDOVBB using fused value */ - clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset); - - return 0; -} diff --git a/arch/arm/cpu/armv7/omap5/boot.c b/arch/arm/cpu/armv7/omap5/boot.c deleted file mode 100644 index 583beccad5a..00000000000 --- a/arch/arm/cpu/armv7/omap5/boot.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * OMAP5 boot - * - * Copyright (C) 2015 Paul Kocialkowski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static u32 boot_devices[] = { -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - BOOT_DEVICE_MMC2, - BOOT_DEVICE_NAND, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_SATA, - BOOT_DEVICE_XIP, - BOOT_DEVICE_XIP, - BOOT_DEVICE_SPI, - BOOT_DEVICE_SPI, -#else - BOOT_DEVICE_MMC2, - BOOT_DEVICE_NAND, - BOOT_DEVICE_MMC1, - BOOT_DEVICE_SATA, - BOOT_DEVICE_XIP, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_XIPWAIT, -#endif -}; - -u32 omap_sys_boot_device(void) -{ - u32 sys_boot; - - /* Grab the first 4 bits of the status register for SYS_BOOT. */ - sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1); - - if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) - return BOOT_DEVICE_NONE; - - return boot_devices[sys_boot]; -} diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk deleted file mode 100644 index 286ca8688d7..00000000000 --- a/arch/arm/cpu/armv7/omap5/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2011 Linaro Limited -# -# Aneesh V -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk - -ifdef CONFIG_SPL_BUILD -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER -else -ALL-y += MLO -endif -else -ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img -endif -ALL-y += u-boot.img -endif diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c deleted file mode 100644 index 87987308ace..00000000000 --- a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2015 - * Texas Instruments Incorporated, - * - * Lokesh Vutla - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static int isolate_io(u32 isolate) -{ - if (isolate) { - clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, - SDCARD_PWRDNZ); - clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, - SDCARD_BIAS_PWRDNZ); - } - - /* Override control on ISOCLKIN signal to IO pad ring. */ - clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, - PMCTRL_ISOCLK_OVERRIDE_CTRL); - if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK, - (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) - return ERR_DEISOLATE_IO << isolate; - - /* Isolate/Deisolate IO */ - clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, - isolate << CTRL_ISOLATE_SHIFT); - /* Dummy read to add delay t > 10ns */ - readl((*ctrl)->ctrl_core_sma_sw_0); - - /* Return control on ISOCLKIN to hardware */ - clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, - PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL); - if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, - 0 << PMCTRL_ISOCLK_STATUS_SHIFT, - (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) - return ERR_DEISOLATE_IO << isolate; - - return 0; -} - -static int calibrate_iodelay(u32 base) -{ - u32 reg; - - /* Configure REFCLK period */ - reg = readl(base + CFG_REG_2_OFFSET); - reg &= ~CFG_REG_REFCLK_PERIOD_MASK; - reg |= CFG_REG_REFCLK_PERIOD; - writel(reg, base + CFG_REG_2_OFFSET); - - /* Initiate Calibration */ - clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK, - CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT); - if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END, - (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) - return ERR_CALIBRATE_IODELAY; - - return 0; -} - -static int update_delay_mechanism(u32 base) -{ - /* Initiate the reload of calibrated values. */ - clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK, - CFG_REG_ROM_READ_START); - if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END, - (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) - return ERR_UPDATE_DELAY; - - return 0; -} - -static u32 calculate_delay(u32 base, u16 offset, u16 den) -{ - u16 refclk_period, dly_cnt, ref_cnt; - u32 reg, q, r; - - refclk_period = readl(base + CFG_REG_2_OFFSET) & - CFG_REG_REFCLK_PERIOD_MASK; - - reg = readl(base + offset); - dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT; - ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT; - - if (!dly_cnt || !den) - return 0; - - /* - * To avoid overflow and integer truncation, delay value - * is calculated as quotient + remainder. - */ - q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den)); - r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) / - (2 * dly_cnt * den); - - return q + r; -} - -static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde) -{ - u32 g_delay_coarse, g_delay_fine; - u32 a_delay_coarse, a_delay_fine; - u32 c_elements, f_elements; - u32 total_delay, reg = 0; - - g_delay_coarse = g_delay / 920; - g_delay_fine = ((g_delay % 920) * 10) / 60; - - a_delay_coarse = a_delay / cpde; - a_delay_fine = ((a_delay % cpde) * 10) / fpde; - - c_elements = g_delay_coarse + a_delay_coarse; - f_elements = (g_delay_fine + a_delay_fine) / 10; - - if (f_elements > 22) { - total_delay = c_elements * cpde + f_elements * fpde; - - c_elements = total_delay / cpde; - f_elements = (total_delay % cpde) / fpde; - } - - reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK; - reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK; - reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT; - reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT; - - return reg; -} - -int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, - int niodelays) -{ - struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array; - u32 reg, cpde, fpde, i; - - if (!niodelays) - return 0; - - cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET, - 88); - if (!cpde) - return ERR_CPDE; - - fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET, - 264); - if (!fpde) - return ERR_FPDE; - - for (i = 0; i < niodelays; i++, iodelay++) { - reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde, - fpde); - writel(reg, base + iodelay->offset); - } - - return 0; -} - -int __recalibrate_iodelay_start(void) -{ - int ret = 0; - - /* IO recalibration should be done only from SRAM */ - if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { - puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); - return -1; - } - - /* unlock IODELAY CONFIG registers */ - writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + - CFG_REG_8_OFFSET); - - ret = calibrate_iodelay((*ctrl)->iodelay_config_base); - if (ret) - goto err; - - ret = isolate_io(ISOLATE_IO); - if (ret) - goto err; - - ret = update_delay_mechanism((*ctrl)->iodelay_config_base); - -err: - return ret; -} - -void __recalibrate_iodelay_end(int ret) -{ - - /* IO recalibration should be done only from SRAM */ - if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { - puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); - return; - } - - if (!ret) - ret = isolate_io(DEISOLATE_IO); - - /* lock IODELAY CONFIG registers */ - writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + - CFG_REG_8_OFFSET); - - /* - * UART cannot be used during IO recalibration sequence as IOs are in - * isolation. So error handling and debug prints are done after - * complete IO delay recalibration sequence - */ - switch (ret) { - case ERR_CALIBRATE_IODELAY: - puts("IODELAY: IO delay calibration sequence failed\n"); - break; - case ERR_ISOLATE_IO: - puts("IODELAY: Isolation of Device IOs failed\n"); - break; - case ERR_UPDATE_DELAY: - puts("IODELAY: Delay mechanism update with new calibrated values failed\n"); - break; - case ERR_DEISOLATE_IO: - puts("IODELAY: De-isolation of Device IOs failed\n"); - break; - case ERR_CPDE: - puts("IODELAY: CPDE calculation failed\n"); - break; - case ERR_FPDE: - puts("IODELAY: FPDE calculation failed\n"); - break; - case -1: - puts("IODELAY: Wrong Context call?\n"); - break; - default: - debug("IODELAY: IO delay recalibration successfully completed\n"); - } - - return; -} - -void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, - struct iodelay_cfg_entry const *iodelay, - int niodelays) -{ - int ret = 0; - - /* IO recalibration should be done only from SRAM */ - if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { - puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); - return; - } - - ret = __recalibrate_iodelay_start(); - if (ret) - goto err; - - /* Configure Mux settings */ - do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); - - /* Configure Manual IO timing modes */ - ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); - if (ret) - goto err; - -err: - __recalibrate_iodelay_end(ret); - -} diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c deleted file mode 100644 index b1203a37afc..00000000000 --- a/arch/arm/cpu/armv7/omap5/emif.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * EMIF programming - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V for OMAP4 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) -static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; -static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; -#endif - -#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -/* Base AC Timing values specified by JESD209-2 for 532MHz operation */ -static const struct lpddr2_ac_timings timings_jedec_532_mhz = { - .max_freq = 532000000, - .RL = 8, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 15, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -/* - * Min tCK values specified by JESD209-2 - * Min tCK specifies the minimum duration of some AC timing parameters in terms - * of the number of cycles. If the calculated number of cycles based on the - * absolute time value is less than the min tCK value, min tCK value should - * be used instead. This typically happens at low frequencies. - */ -static const struct lpddr2_min_tck min_tck_jedec = { - .tRL = 3, - .tRP_AB = 3, - .tRCD = 3, - .tWR = 3, - .tRAS_MIN = 3, - .tRRD = 2, - .tWTR = 2, - .tXP = 2, - .tRTP = 2, - .tCKE = 3, - .tCKESR = 3, - .tFAW = 8 -}; - -static const struct lpddr2_ac_timings const* - jedec_ac_timings[MAX_NUM_SPEEDBINS] = { - &timings_jedec_532_mhz -}; - -static const struct lpddr2_device_timings jedec_default_timings = { - .ac_timings = jedec_ac_timings, - .min_tck = &min_tck_jedec -}; - -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) -{ - /* Assume Identical devices on EMIF1 & EMIF2 */ - *cs0_device_timings = &jedec_default_timings; - *cs1_device_timings = NULL; -} -#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c deleted file mode 100644 index da8d59bb59f..00000000000 --- a/arch/arm/cpu/armv7/omap5/fdt.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright 2016 Texas Instruments, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_TI_SECURE_DEVICE - -/* Give zero values if not already defined */ -#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ -#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0) -#endif -#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ -#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0) -#endif - -static u32 hs_irq_skip[] = { - 8, /* Secure violation reporting interrupt */ - 15, /* One interrupt for SDMA by secure world */ - 118 /* One interrupt for Crypto DMA by secure world */ -}; - -static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd) -{ - const char *path; - int offs; - int ret; - int len, i, old_cnt, new_cnt; - u32 *temp; - const u32 *p_data; - - /* - * Increase the size of the fdt - * so we have some breathing room - */ - ret = fdt_increase_size(fdt, 512); - if (ret < 0) { - printf("Could not increase size of device tree: %s\n", - fdt_strerror(ret)); - return ret; - } - - /* Reserve IRQs that are used/needed by secure world */ - path = "/ocp/crossbar"; - offs = fdt_path_offset(fdt, path); - if (offs < 0) { - debug("Node %s not found.\n", path); - return 0; - } - - /* Get current entries */ - p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len); - if (p_data) - old_cnt = len / sizeof(u32); - else - old_cnt = 0; - - new_cnt = sizeof(hs_irq_skip) / - sizeof(hs_irq_skip[0]); - - /* Create new/updated skip list for HS parts */ - temp = malloc(sizeof(u32) * (old_cnt + new_cnt)); - for (i = 0; i < new_cnt; i++) - temp[i] = cpu_to_fdt32(hs_irq_skip[i]); - for (i = 0; i < old_cnt; i++) - temp[i + new_cnt] = p_data[i]; - - /* Blow away old data and set new data */ - fdt_delprop(fdt, offs, "ti,irqs-skip"); - ret = fdt_setprop(fdt, offs, "ti,irqs-skip", - temp, - (old_cnt + new_cnt) * sizeof(u32)); - free(temp); - - /* Check if the update worked */ - if (ret < 0) { - printf("Could not add ti,irqs-skip property to node %s: %s\n", - path, fdt_strerror(ret)); - return ret; - } - - return 0; -} - -static int ft_hs_disable_rng(void *fdt, bd_t *bd) -{ - const char *path; - int offs; - int ret; - - /* Make HW RNG reserved for secure world use */ - path = "/ocp/rng"; - offs = fdt_path_offset(fdt, path); - if (offs < 0) { - debug("Node %s not found.\n", path); - return 0; - } - ret = fdt_setprop_string(fdt, offs, - "status", "disabled"); - if (ret < 0) { - printf("Could not add status property to node %s: %s\n", - path, fdt_strerror(ret)); - return ret; - } - return 0; -} - -#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \ - (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0)) -static int ft_hs_fixup_sram(void *fdt, bd_t *bd) -{ - const char *path; - int offs; - int ret; - u32 temp[2]; - - /* - * Update SRAM reservations on secure devices. The OCMC RAM - * is always reserved for secure use from the start of that - * memory region - */ - path = "/ocp/ocmcram@40300000/sram-hs"; - offs = fdt_path_offset(fdt, path); - if (offs < 0) { - debug("Node %s not found.\n", path); - return 0; - } - - /* relative start offset */ - temp[0] = cpu_to_fdt32(0); - /* reservation size */ - temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ, - CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ)); - fdt_delprop(fdt, offs, "reg"); - ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32)); - if (ret < 0) { - printf("Could not add reg property to node %s: %s\n", - path, fdt_strerror(ret)); - return ret; - } - - return 0; -} -#else -static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; } -#endif - -#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0) -static int ft_hs_fixup_dram(void *fdt, bd_t *bd) -{ - const char *path, *subpath; - int offs; - u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START; - u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE; - fdt64_t temp[2]; - - /* If start address is zero, place at end of DRAM */ - if (0 == sec_mem_start) - sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + - (omap_sdram_size() - sec_mem_size)); - - /* Delete any original secure_reserved node */ - path = "/reserved-memory/secure_reserved"; - offs = fdt_path_offset(fdt, path); - if (offs >= 0) - fdt_del_node(fdt, offs); - - /* Add new secure_reserved node */ - path = "/reserved-memory"; - offs = fdt_path_offset(fdt, path); - if (offs < 0) { - debug("Node %s not found\n", path); - path = "/"; - subpath = "reserved-memory"; - fdt_path_offset(fdt, path); - offs = fdt_add_subnode(fdt, offs, subpath); - if (offs < 0) { - printf("Could not create %s%s node.\n", path, subpath); - return 1; - } - path = "/reserved-memory"; - offs = fdt_path_offset(fdt, path); - } - - subpath = "secure_reserved"; - offs = fdt_add_subnode(fdt, offs, subpath); - if (offs < 0) { - printf("Could not create %s%s node.\n", path, subpath); - return 1; - } - - temp[0] = cpu_to_fdt64(((u64)sec_mem_start)); - temp[1] = cpu_to_fdt64(((u64)sec_mem_size)); - fdt_setprop_string(fdt, offs, "compatible", - "ti,dra7-secure-memory"); - fdt_setprop_string(fdt, offs, "status", "okay"); - fdt_setprop(fdt, offs, "no-map", NULL, 0); - fdt_setprop(fdt, offs, "reg", temp, sizeof(temp)); - - return 0; -} -#else -static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; } -#endif - -static void ft_hs_fixups(void *fdt, bd_t *bd) -{ - /* Check we are running on an HS/EMU device type */ - if (GP_DEVICE != get_device_type()) { - if ((ft_hs_fixup_crossbar(fdt, bd) == 0) && - (ft_hs_disable_rng(fdt, bd) == 0) && - (ft_hs_fixup_sram(fdt, bd) == 0) && - (ft_hs_fixup_dram(fdt, bd) == 0)) - return; - } else { - printf("ERROR: Incorrect device type (GP) detected!"); - } - /* Fixup failed or wrong device type */ - hang(); -} -#else -static void ft_hs_fixups(void *fdt, bd_t *bd) -{ -} -#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */ - -/* - * Place for general cpu/SoC FDT fixups. Board specific - * fixups should remain in the board files which is where - * this function should be called from. - */ -void ft_cpu_setup(void *fdt, bd_t *bd) -{ - ft_hs_fixups(fdt, bd); -} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c deleted file mode 100644 index fc991358248..00000000000 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ /dev/null @@ -1,776 +0,0 @@ -/* - * - * HW data initialization for OMAP5 - * - * (C) Copyright 2013 - * Texas Instruments, - * - * Sricharan R - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct prcm_regs const **prcm = - (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; -struct dplls const **dplls_data = - (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; -struct vcores_data const **omap_vcores = - (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; -struct omap_sys_ctrl_regs const **ctrl = - (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; - -/* OPP HIGH FREQUENCY for ES2.0 */ -static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { - {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OPP NOM FREQUENCY for ES1.0 */ -static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OPP LOW FREQUENCY for ES1.0 */ -static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { - {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OPP LOW FREQUENCY for ES2.0 */ -static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { - {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ -static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { - {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ - {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ - {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ - {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ - {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ - {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { - {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ - {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ - {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ - {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ - {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ - {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ - {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { - {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ - {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ - {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { - {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { - {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ - {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ - {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { - {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { - {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ - {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -/* ABE M & N values with sys_clk as source */ -static const struct dpll_params - abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with 32K clock as source */ -static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 -}; - -/* ABE M & N values with sysclk2(22.5792 MHz) as input */ -static const struct dpll_params - abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { - {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ - {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { - {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ - {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { - {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ - {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ - {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ -}; - -struct dplls omap5_dplls_es1 = { - .mpu = mpu_dpll_params_800mhz, - .core = core_dpll_params_2128mhz_ddr532, - .per = per_dpll_params_768mhz, - .iva = iva_dpll_params_2330mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct dplls omap5_dplls_es2 = { - .mpu = mpu_dpll_params_1ghz, - .core = core_dpll_params_2128mhz_ddr532_es2, - .per = per_dpll_params_768mhz_es2, - .iva = iva_dpll_params_2330mhz, -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - .abe = abe_dpll_params_sysclk_196608khz, -#else - .abe = &abe_dpll_params_32k_196608khz, -#endif - .usb = usb_dpll_params_1920mhz, - .ddr = NULL -}; - -struct dplls dra7xx_dplls = { - .mpu = mpu_dpll_params_1ghz, - .core = core_dpll_params_2128mhz_dra7xx, - .per = per_dpll_params_768mhz_dra7xx, - .abe = abe_dpll_params_sysclk2_361267khz, - .iva = iva_dpll_params_2330mhz_dra7xx, - .usb = usb_dpll_params_1920mhz, - .ddr = ddr_dpll_params_2128mhz, - .gmac = gmac_dpll_params_2000mhz, -}; - -struct dplls dra72x_dplls = { - .mpu = mpu_dpll_params_1ghz, - .core = core_dpll_params_2128mhz_dra7xx, - .per = per_dpll_params_768mhz_dra7xx, - .abe = abe_dpll_params_sysclk2_361267khz, - .iva = iva_dpll_params_2330mhz_dra7xx, - .usb = usb_dpll_params_1920mhz, - .ddr = ddr_dpll_params_2664mhz, - .gmac = gmac_dpll_params_2000mhz, -}; - -struct pmic_data palmas = { - .base_offset = PALMAS_SMPS_BASE_VOLT_UV, - .step = 10000, /* 10 mV represented in uV */ - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - .start_code = 6, - .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, - .pmic_bus_init = sri2c_init, - .pmic_write = omap_vc_bypass_send_value, - .gpio_en = 0, -}; - -/* The TPS659038 and TPS65917 are software-compatible, use common struct */ -struct pmic_data tps659038 = { - .base_offset = PALMAS_SMPS_BASE_VOLT_UV, - .step = 10000, /* 10 mV represented in uV */ - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - .start_code = 6, - .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, - .pmic_bus_init = gpi2c_init, - .pmic_write = palmas_i2c_write_u8, - .gpio_en = 0, -}; - -struct vcores_data omap5430_volts = { - .mpu.value = VDD_MPU, - .mpu.addr = SMPS_REG_ADDR_12_MPU, - .mpu.pmic = &palmas, - - .core.value = VDD_CORE, - .core.addr = SMPS_REG_ADDR_8_CORE, - .core.pmic = &palmas, - - .mm.value = VDD_MM, - .mm.addr = SMPS_REG_ADDR_45_IVA, - .mm.pmic = &palmas, -}; - -struct vcores_data omap5430_volts_es2 = { - .mpu.value = VDD_MPU_ES2, - .mpu.addr = SMPS_REG_ADDR_12_MPU, - .mpu.pmic = &palmas, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - - .core.value = VDD_CORE_ES2, - .core.addr = SMPS_REG_ADDR_8_CORE, - .core.pmic = &palmas, - - .mm.value = VDD_MM_ES2, - .mm.addr = SMPS_REG_ADDR_45_IVA, - .mm.pmic = &palmas, - .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, -}; - -/* - * Enable essential clock domains, modules and - * do some additional special settings needed - */ -void enable_basic_clocks(void) -{ - u32 const clk_domains_essential[] = { - (*prcm)->cm_l4per_clkstctrl, - (*prcm)->cm_l3init_clkstctrl, - (*prcm)->cm_memif_clkstctrl, - (*prcm)->cm_l4cfg_clkstctrl, -#ifdef CONFIG_DRIVER_TI_CPSW - (*prcm)->cm_gmac_clkstctrl, -#endif - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3_gpmc_clkctrl, - (*prcm)->cm_memif_emif_1_clkctrl, - (*prcm)->cm_memif_emif_2_clkctrl, - (*prcm)->cm_l4cfg_l4_cfg_clkctrl, - (*prcm)->cm_wkup_gpio1_clkctrl, - (*prcm)->cm_l4per_gpio2_clkctrl, - (*prcm)->cm_l4per_gpio3_clkctrl, - (*prcm)->cm_l4per_gpio4_clkctrl, - (*prcm)->cm_l4per_gpio5_clkctrl, - (*prcm)->cm_l4per_gpio6_clkctrl, - (*prcm)->cm_l4per_gpio7_clkctrl, - (*prcm)->cm_l4per_gpio8_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_wkup_gptimer1_clkctrl, - (*prcm)->cm_l3init_hsmmc1_clkctrl, - (*prcm)->cm_l3init_hsmmc2_clkctrl, - (*prcm)->cm_l4per_gptimer2_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_l4per_uart3_clkctrl, - (*prcm)->cm_l4per_i2c1_clkctrl, -#ifdef CONFIG_DRIVER_TI_CPSW - (*prcm)->cm_gmac_gmac_clkctrl, -#endif - -#ifdef CONFIG_TI_QSPI - (*prcm)->cm_l4per_qspi_clkctrl, -#endif - 0 - }; - - /* Enable optional additional functional clock for GPIO4 */ - setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, - GPIO4_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - - /* Set the correct clock dividers for mmc */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - - /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, - GPTIMER1_CLKCTRL_CLKSEL_MASK); - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); - -#ifdef CONFIG_TI_QSPI - setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); -#endif - - /* Enable SCRM OPT clocks for PER and CORE dpll */ - setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_PER_MASK); - setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_CORE_MASK); -} - -void enable_basic_uboot_clocks(void) -{ - u32 const clk_domains_essential[] = { -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - (*prcm)->cm_ipu_clkstctrl, -#endif - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3init_hsusbtll_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_l4per_mcspi1_clkctrl, - (*prcm)->cm_l4per_i2c2_clkctrl, - (*prcm)->cm_l4per_i2c3_clkctrl, - (*prcm)->cm_l4per_i2c4_clkctrl, -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - (*prcm)->cm_ipu_i2c5_clkctrl, -#else - (*prcm)->cm_l4per_i2c5_clkctrl, -#endif - (*prcm)->cm_l3init_hsusbhost_clkctrl, - (*prcm)->cm_l3init_fsusb_clkctrl, - 0 - }; - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -#ifdef CONFIG_TI_EDMA3 -void enable_edma3_clocks(void) -{ - u32 const clk_domains_edma3[] = { - 0 - }; - - u32 const clk_modules_hw_auto_edma3[] = { - (*prcm)->cm_l3main1_tptc1_clkctrl, - (*prcm)->cm_l3main1_tptc2_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_edma3[] = { - 0 - }; - - do_enable_clocks(clk_domains_edma3, - clk_modules_hw_auto_edma3, - clk_modules_explicit_en_edma3, - 1); -} - -void disable_edma3_clocks(void) -{ - u32 const clk_domains_edma3[] = { - 0 - }; - - u32 const clk_modules_disable_edma3[] = { - (*prcm)->cm_l3main1_tptc1_clkctrl, - (*prcm)->cm_l3main1_tptc2_clkctrl, - 0 - }; - - do_disable_clocks(clk_domains_edma3, - clk_modules_disable_edma3, - 1); -} -#endif - -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) -void enable_usb_clocks(int index) -{ - u32 cm_l3init_usb_otg_ss_clkctrl = 0; - - if (index == 0) { - cm_l3init_usb_otg_ss_clkctrl = - (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; - /* Enable 960 MHz clock for dwc3 */ - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OPTFCLKEN_REFCLK960M); - - /* Enable 32 KHz clock for USB_PHY1 */ - setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - /* Enable 32 KHz clock for USB_PHY3 */ - if (is_dra7xx()) - setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - } else if (index == 1) { - cm_l3init_usb_otg_ss_clkctrl = - (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; - /* Enable 960 MHz clock for dwc3 */ - setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, - OPTFCLKEN_REFCLK960M); - - /* Enable 32 KHz clock for dwc3 */ - setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - /* Enable 60 MHz clock for USB2PHY2 */ - setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, - L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); - } - - u32 const clk_domains_usb[] = { - 0 - }; - - u32 const clk_modules_hw_auto_usb[] = { - (*prcm)->cm_l3init_ocp2scp1_clkctrl, - cm_l3init_usb_otg_ss_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_usb[] = { - 0 - }; - - do_enable_clocks(clk_domains_usb, - clk_modules_hw_auto_usb, - clk_modules_explicit_en_usb, - 1); -} - -void disable_usb_clocks(int index) -{ - u32 cm_l3init_usb_otg_ss_clkctrl = 0; - - if (index == 0) { - cm_l3init_usb_otg_ss_clkctrl = - (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; - /* Disable 960 MHz clock for dwc3 */ - clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OPTFCLKEN_REFCLK960M); - - /* Disable 32 KHz clock for USB_PHY1 */ - clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - /* Disable 32 KHz clock for USB_PHY3 */ - if (is_dra7xx()) - clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - } else if (index == 1) { - cm_l3init_usb_otg_ss_clkctrl = - (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; - /* Disable 960 MHz clock for dwc3 */ - clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, - OPTFCLKEN_REFCLK960M); - - /* Disable 32 KHz clock for dwc3 */ - clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - /* Disable 60 MHz clock for USB2PHY2 */ - clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, - L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); - } - - u32 const clk_domains_usb[] = { - 0 - }; - - u32 const clk_modules_disable[] = { - (*prcm)->cm_l3init_ocp2scp1_clkctrl, - cm_l3init_usb_otg_ss_clkctrl, - 0 - }; - - do_disable_clocks(clk_domains_usb, - clk_modules_disable, - 1); -} -#endif - -const struct ctrl_ioregs ioregs_omap5430 = { - .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, -}; - -const struct ctrl_ioregs ioregs_omap5432_es1 = { - .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - .ctrl_lpddr2ch = 0x0, - .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, - .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, - .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, - .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, -}; - -const struct ctrl_ioregs ioregs_omap5432_es2 = { - .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, - .ctrl_lpddr2ch = 0x0, - .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, - .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, - .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, - .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, - .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, -}; - -const struct ctrl_ioregs ioregs_dra7xx_es1 = { - .ctrl_ddrch = 0x40404040, - .ctrl_lpddr2ch = 0x40404040, - .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0x00094A40, - .ctrl_ddrio_1 = 0x04A52000, - .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, - .ctrl_ddr_ctrl_ext_0 = 0xA2000000, -}; - -const struct ctrl_ioregs ioregs_dra72x_es1 = { - .ctrl_ddrch = 0x40404040, - .ctrl_lpddr2ch = 0x40404040, - .ctrl_ddr3ch = 0x60606080, - .ctrl_ddrio_0 = 0x00094A40, - .ctrl_ddrio_1 = 0x04A52000, - .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, - .ctrl_ddr_ctrl_ext_0 = 0xA2000000, -}; - -const struct ctrl_ioregs ioregs_dra72x_es2 = { - .ctrl_ddrch = 0x40404040, - .ctrl_lpddr2ch = 0x40404040, - .ctrl_ddr3ch = 0x60606060, - .ctrl_ddrio_0 = 0x00094A40, - .ctrl_ddrio_1 = 0x00000000, - .ctrl_ddrio_2 = 0x00000000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, - .ctrl_ddr_ctrl_ext_0 = 0xA2000000, -}; - -void __weak hw_data_init(void) -{ - u32 omap_rev = omap_revision(); - - switch (omap_rev) { - - case OMAP5430_ES1_0: - case OMAP5432_ES1_0: - *prcm = &omap5_es1_prcm; - *dplls_data = &omap5_dplls_es1; - *omap_vcores = &omap5430_volts; - *ctrl = &omap5_ctrl; - break; - - case OMAP5430_ES2_0: - case OMAP5432_ES2_0: - *prcm = &omap5_es2_prcm; - *dplls_data = &omap5_dplls_es2; - *omap_vcores = &omap5430_volts_es2; - *ctrl = &omap5_ctrl; - break; - - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - *prcm = &dra7xx_prcm; - *dplls_data = &dra7xx_dplls; - *ctrl = &dra7xx_ctrl; - break; - - case DRA722_ES1_0: - case DRA722_ES2_0: - *prcm = &dra7xx_prcm; - *dplls_data = &dra72x_dplls; - *ctrl = &dra7xx_ctrl; - break; - - default: - printf("\n INVALID OMAP REVISION "); - } -} - -void get_ioregs(const struct ctrl_ioregs **regs) -{ - u32 omap_rev = omap_revision(); - - switch (omap_rev) { - case OMAP5430_ES1_0: - case OMAP5430_ES2_0: - *regs = &ioregs_omap5430; - break; - case OMAP5432_ES1_0: - *regs = &ioregs_omap5432_es1; - break; - case OMAP5432_ES2_0: - *regs = &ioregs_omap5432_es2; - break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - *regs = &ioregs_dra7xx_es1; - break; - case DRA722_ES1_0: - *regs = &ioregs_dra72x_es1; - break; - case DRA722_ES2_0: - *regs = &ioregs_dra72x_es2; - break; - - default: - printf("\n INVALID OMAP REVISION "); - } -} diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c deleted file mode 100644 index e3ac8bbe952..00000000000 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * - * Functions for omap5 based boards. - * - * (C) Copyright 2011 - * Texas Instruments, - * - * Author : - * Aneesh V - * Steve Sakoman - * Sricharan - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; - -#ifndef CONFIG_DM_GPIO -static struct gpio_bank gpio_bank_54xx[8] = { - { (void *)OMAP54XX_GPIO1_BASE }, - { (void *)OMAP54XX_GPIO2_BASE }, - { (void *)OMAP54XX_GPIO3_BASE }, - { (void *)OMAP54XX_GPIO4_BASE }, - { (void *)OMAP54XX_GPIO5_BASE }, - { (void *)OMAP54XX_GPIO6_BASE }, - { (void *)OMAP54XX_GPIO7_BASE }, - { (void *)OMAP54XX_GPIO8_BASE }, -}; - -const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; -#endif - -void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) -{ - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); -} - -#ifdef CONFIG_SPL_BUILD -/* LPDDR2 specific IO settings */ -static void io_settings_lpddr2(void) -{ - const struct ctrl_ioregs *ioregs; - - get_ioregs(&ioregs); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); - writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); - writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); - writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); -} - -/* DDR3 specific IO settings */ -static void io_settings_ddr3(void) -{ - u32 io_settings = 0; - const struct ctrl_ioregs *ioregs; - - get_ioregs(&ioregs); - writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); - - writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); - writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); - - writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); - writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); - - if (!is_dra7xx()) { - writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); - } - - /* omap5432 does not use lpddr2 */ - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); - - writel(ioregs->ctrl_emif_sdram_config_ext, - (*ctrl)->control_emif1_sdram_config_ext); - if (!is_dra72x()) - writel(ioregs->ctrl_emif_sdram_config_ext, - (*ctrl)->control_emif2_sdram_config_ext); - - if (is_omap54xx()) { - /* Disable DLL select */ - io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) - & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif1_sdram_config); - - io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) - & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif2_sdram_config); - } else { - writel(ioregs->ctrl_ddr_ctrl_ext_0, - (*ctrl)->control_ddr_control_ext_0); - } -} - -/* - * Some tuning of IOs for optimal power and performance - */ -void do_io_settings(void) -{ - u32 io_settings = 0, mask = 0; - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - /* Impedance settings EMMC, C2C 1,2, hsi2 */ - mask = (ds_mask << 2) | (ds_mask << 8) | - (ds_mask << 16) | (ds_mask << 18); - io_settings = readl((*ctrl)->control_smart1io_padconf_0) & - (~mask); - io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | - (ds_45_ohm << 18) | (ds_60_ohm << 2); - writel(io_settings, (*ctrl)->control_smart1io_padconf_0); - - /* Impedance settings Mcspi2 */ - mask = (ds_mask << 30); - io_settings = readl((*ctrl)->control_smart1io_padconf_1) & - (~mask); - io_settings |= (ds_60_ohm << 30); - writel(io_settings, (*ctrl)->control_smart1io_padconf_1); - - /* Impedance settings C2C 3,4 */ - mask = (ds_mask << 14) | (ds_mask << 16); - io_settings = readl((*ctrl)->control_smart1io_padconf_2) & - (~mask); - io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); - writel(io_settings, (*ctrl)->control_smart1io_padconf_2); - - /* Slew rate settings EMMC, C2C 1,2 */ - mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); - io_settings = readl((*ctrl)->control_smart2io_padconf_0) & - (~mask); - io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); - writel(io_settings, (*ctrl)->control_smart2io_padconf_0); - - /* Slew rate settings hsi2, Mcspi2 */ - mask = (sc_mask << 24) | (sc_mask << 28); - io_settings = readl((*ctrl)->control_smart2io_padconf_1) & - (~mask); - io_settings |= (sc_fast << 28) | (sc_fast << 24); - writel(io_settings, (*ctrl)->control_smart2io_padconf_1); - - /* Slew rate settings C2C 3,4 */ - mask = (sc_mask << 16) | (sc_mask << 18); - io_settings = readl((*ctrl)->control_smart2io_padconf_2) & - (~mask); - io_settings |= (sc_na << 16) | (sc_na << 18); - writel(io_settings, (*ctrl)->control_smart2io_padconf_2); - - /* impedance and slew rate settings for usb */ - mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | - (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); - io_settings = readl((*ctrl)->control_smart3io_padconf_1) & - (~mask); - io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | - (ds_60_ohm << 23) | (sc_fast << 20) | - (sc_fast << 17) | (sc_fast << 14); - writel(io_settings, (*ctrl)->control_smart3io_padconf_1); - - if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) - io_settings_lpddr2(); - else - io_settings_ddr3(); -} - -static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { - {0x45, 0x1}, /* 12 MHz */ - {-1, -1}, /* 13 MHz */ - {0x63, 0x2}, /* 16.8 MHz */ - {0x57, 0x2}, /* 19.2 MHz */ - {0x20, 0x1}, /* 26 MHz */ - {-1, -1}, /* 27 MHz */ - {0x41, 0x3} /* 38.4 MHz */ -}; - -void srcomp_enable(void) -{ - u32 srcomp_value, mul_factor, div_factor, clk_val, i; - u32 sysclk_ind = get_sys_clk_index(); - u32 omap_rev = omap_revision(); - - if (!is_omap54xx()) - return; - - mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; - div_factor = srcomp_parameters[sysclk_ind].divide_factor; - - for (i = 0; i < 4; i++) { - srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); - srcomp_value &= - ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); - srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | - (div_factor << DIVIDE_FACTOR_XS_SHIFT); - writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); - } - - if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { - clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); - clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; - writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); - - for (i = 0; i < 4; i++) { - srcomp_value = - readl((*ctrl)->control_srcomp_north_side + i*4); - srcomp_value &= ~PWRDWN_XS_MASK; - writel(srcomp_value, - (*ctrl)->control_srcomp_north_side + i*4); - - while (((readl((*ctrl)->control_srcomp_north_side + i*4) - & SRCODE_READ_XS_MASK) >> - SRCODE_READ_XS_SHIFT) == 0) - ; - - srcomp_value = - readl((*ctrl)->control_srcomp_north_side + i*4); - srcomp_value &= ~OVERRIDE_XS_MASK; - writel(srcomp_value, - (*ctrl)->control_srcomp_north_side + i*4); - } - } else { - srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); - srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | - DIVIDE_FACTOR_XS_MASK); - srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | - (div_factor << DIVIDE_FACTOR_XS_SHIFT); - writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); - - for (i = 0; i < 4; i++) { - srcomp_value = - readl((*ctrl)->control_srcomp_north_side + i*4); - srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; - writel(srcomp_value, - (*ctrl)->control_srcomp_north_side + i*4); - - srcomp_value = - readl((*ctrl)->control_srcomp_north_side + i*4); - srcomp_value &= ~OVERRIDE_XS_MASK; - writel(srcomp_value, - (*ctrl)->control_srcomp_north_side + i*4); - } - - srcomp_value = - readl((*ctrl)->control_srcomp_east_side_wkup); - srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; - writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); - - srcomp_value = - readl((*ctrl)->control_srcomp_east_side_wkup); - srcomp_value &= ~OVERRIDE_XS_MASK; - writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); - - clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); - clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; - writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); - - clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); - clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; - writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); - - for (i = 0; i < 4; i++) { - while (((readl((*ctrl)->control_srcomp_north_side + i*4) - & SRCODE_READ_XS_MASK) >> - SRCODE_READ_XS_SHIFT) == 0) - ; - - srcomp_value = - readl((*ctrl)->control_srcomp_north_side + i*4); - srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; - writel(srcomp_value, - (*ctrl)->control_srcomp_north_side + i*4); - } - - while (((readl((*ctrl)->control_srcomp_east_side_wkup) & - SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) - ; - - srcomp_value = - readl((*ctrl)->control_srcomp_east_side_wkup); - srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; - writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); - } -} -#endif - -void config_data_eye_leveling_samples(u32 emif_base) -{ - const struct ctrl_ioregs *ioregs; - - get_ioregs(&ioregs); - - /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ - if (emif_base == EMIF1_BASE) - writel(ioregs->ctrl_emif_sdram_config_ext_final, - (*ctrl)->control_emif1_sdram_config_ext); - else if (emif_base == EMIF2_BASE) - writel(ioregs->ctrl_emif_sdram_config_ext_final, - (*ctrl)->control_emif2_sdram_config_ext); -} - -void init_cpu_configuration(void) -{ - u32 l2actlr; - - asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); - /* - * L2ACTLR: Ensure to enable the following: - * 3: Disable clean/evict push to external - * 4: Disable WriteUnique and WriteLineUnique transactions from master - * 8: Disable DVM/CMO message broadcast - */ - l2actlr |= 0x118; - omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); -} - -void init_omap_revision(void) -{ - /* - * For some of the ES2/ES1 boards ID_CODE is not reliable: - * Also, ES1 and ES2 have different ARM revisions - * So use ARM revision for identification - */ - unsigned int rev = cortex_rev(); - - switch (readl(CONTROL_ID_CODE)) { - case OMAP5430_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP5430_ES1_0; - if (rev == MIDR_CORTEX_A15_R2P2) - *omap_si_rev = OMAP5430_ES2_0; - break; - case OMAP5432_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP5432_ES1_0; - if (rev == MIDR_CORTEX_A15_R2P2) - *omap_si_rev = OMAP5432_ES2_0; - break; - case OMAP5430_CONTROL_ID_CODE_ES2_0: - *omap_si_rev = OMAP5430_ES2_0; - break; - case OMAP5432_CONTROL_ID_CODE_ES2_0: - *omap_si_rev = OMAP5432_ES2_0; - break; - case DRA752_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = DRA752_ES1_0; - break; - case DRA752_CONTROL_ID_CODE_ES1_1: - *omap_si_rev = DRA752_ES1_1; - break; - case DRA752_CONTROL_ID_CODE_ES2_0: - *omap_si_rev = DRA752_ES2_0; - break; - case DRA722_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = DRA722_ES1_0; - break; - case DRA722_CONTROL_ID_CODE_ES2_0: - *omap_si_rev = DRA722_ES2_0; - break; - default: - *omap_si_rev = OMAP5430_SILICON_ID_INVALID; - } - init_cpu_configuration(); -} - -void omap_die_id(unsigned int *die_id) -{ - die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); - die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); - die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); - die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); -} - -void reset_cpu(ulong ignored) -{ - u32 omap_rev = omap_revision(); - - /* - * WARM reset is not functional in case of OMAP5430 ES1.0 soc. - * So use cold reset in case instead. - */ - if (omap_rev == OMAP5430_ES1_0) - writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); - else - writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); -} - -u32 warm_reset(void) -{ - return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; -} - -void setup_warmreset_time(void) -{ - u32 rst_time, rst_val; - -#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC - rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC; -#else - rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC; -#endif - rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT; - - if (rst_time > RSTTIME1_MASK) - rst_time = RSTTIME1_MASK; - - rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; - rst_val |= rst_time; - writel(rst_val, (*prcm)->prm_rsttime); -} - -void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, - u32 cpu_rev_comb, u32 cpu_variant, - u32 cpu_rev) -{ - omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); -} - -void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, - u32 cpu_variant, u32 cpu_rev) -{ - -#ifdef CONFIG_ARM_ERRATA_801819 - /* - * DRA72x processors are uniprocessors and DONOT have - * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency - * Extensions) Hence the erratum workaround is not applicable for - * DRA72x processors. - */ - if (is_dra72x()) - acr &= ~((0x3 << 23) | (0x3 << 25)); -#endif - omap_smc1(OMAP5_SERVICE_ACR_SET, acr); -} diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c deleted file mode 100644 index b5f1d700fd8..00000000000 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ /dev/null @@ -1,1024 +0,0 @@ -/* - * - * HW regs data for OMAP5 Soc - * - * (C) Copyright 2013 - * Texas Instruments, - * - * Sricharan R - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct prcm_regs const omap5_es1_prcm = { - /* cm1.ckgen */ - .cm_clksel_core = 0x4a004100, - .cm_clksel_abe = 0x4a004108, - .cm_dll_ctrl = 0x4a004110, - .cm_clkmode_dpll_core = 0x4a004120, - .cm_idlest_dpll_core = 0x4a004124, - .cm_autoidle_dpll_core = 0x4a004128, - .cm_clksel_dpll_core = 0x4a00412c, - .cm_div_m2_dpll_core = 0x4a004130, - .cm_div_m3_dpll_core = 0x4a004134, - .cm_div_h11_dpll_core = 0x4a004138, - .cm_div_h12_dpll_core = 0x4a00413c, - .cm_div_h13_dpll_core = 0x4a004140, - .cm_div_h14_dpll_core = 0x4a004144, - .cm_ssc_deltamstep_dpll_core = 0x4a004148, - .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, - .cm_emu_override_dpll_core = 0x4a004150, - .cm_div_h22_dpllcore = 0x4a004154, - .cm_div_h23_dpll_core = 0x4a004158, - .cm_clkmode_dpll_mpu = 0x4a004160, - .cm_idlest_dpll_mpu = 0x4a004164, - .cm_autoidle_dpll_mpu = 0x4a004168, - .cm_clksel_dpll_mpu = 0x4a00416c, - .cm_div_m2_dpll_mpu = 0x4a004170, - .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, - .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, - .cm_bypclk_dpll_mpu = 0x4a00419c, - .cm_clkmode_dpll_iva = 0x4a0041a0, - .cm_idlest_dpll_iva = 0x4a0041a4, - .cm_autoidle_dpll_iva = 0x4a0041a8, - .cm_clksel_dpll_iva = 0x4a0041ac, - .cm_div_h11_dpll_iva = 0x4a0041b8, - .cm_div_h12_dpll_iva = 0x4a0041bc, - .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, - .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, - .cm_bypclk_dpll_iva = 0x4a0041dc, - .cm_clkmode_dpll_abe = 0x4a0041e0, - .cm_idlest_dpll_abe = 0x4a0041e4, - .cm_autoidle_dpll_abe = 0x4a0041e8, - .cm_clksel_dpll_abe = 0x4a0041ec, - .cm_div_m2_dpll_abe = 0x4a0041f0, - .cm_div_m3_dpll_abe = 0x4a0041f4, - .cm_ssc_deltamstep_dpll_abe = 0x4a004208, - .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, - .cm_clkmode_dpll_ddrphy = 0x4a004220, - .cm_idlest_dpll_ddrphy = 0x4a004224, - .cm_autoidle_dpll_ddrphy = 0x4a004228, - .cm_clksel_dpll_ddrphy = 0x4a00422c, - .cm_div_m2_dpll_ddrphy = 0x4a004230, - .cm_div_h11_dpll_ddrphy = 0x4a004238, - .cm_div_h12_dpll_ddrphy = 0x4a00423c, - .cm_div_h13_dpll_ddrphy = 0x4a004240, - .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, - .cm_shadow_freq_config1 = 0x4a004260, - .cm_mpu_mpu_clkctrl = 0x4a004320, - - /* cm1.dsp */ - .cm_dsp_clkstctrl = 0x4a004400, - .cm_dsp_dsp_clkctrl = 0x4a004420, - - /* cm1.abe */ - .cm1_abe_clkstctrl = 0x4a004500, - .cm1_abe_l4abe_clkctrl = 0x4a004520, - .cm1_abe_aess_clkctrl = 0x4a004528, - .cm1_abe_pdm_clkctrl = 0x4a004530, - .cm1_abe_dmic_clkctrl = 0x4a004538, - .cm1_abe_mcasp_clkctrl = 0x4a004540, - .cm1_abe_mcbsp1_clkctrl = 0x4a004548, - .cm1_abe_mcbsp2_clkctrl = 0x4a004550, - .cm1_abe_mcbsp3_clkctrl = 0x4a004558, - .cm1_abe_slimbus_clkctrl = 0x4a004560, - .cm1_abe_timer5_clkctrl = 0x4a004568, - .cm1_abe_timer6_clkctrl = 0x4a004570, - .cm1_abe_timer7_clkctrl = 0x4a004578, - .cm1_abe_timer8_clkctrl = 0x4a004580, - .cm1_abe_wdt3_clkctrl = 0x4a004588, - - /* cm2.ckgen */ - .cm_clksel_mpu_m3_iss_root = 0x4a008100, - .cm_clksel_usb_60mhz = 0x4a008104, - .cm_scale_fclk = 0x4a008108, - .cm_core_dvfs_perf1 = 0x4a008110, - .cm_core_dvfs_perf2 = 0x4a008114, - .cm_core_dvfs_perf3 = 0x4a008118, - .cm_core_dvfs_perf4 = 0x4a00811c, - .cm_core_dvfs_current = 0x4a008124, - .cm_iva_dvfs_perf_tesla = 0x4a008128, - .cm_iva_dvfs_perf_ivahd = 0x4a00812c, - .cm_iva_dvfs_perf_abe = 0x4a008130, - .cm_iva_dvfs_current = 0x4a008138, - .cm_clkmode_dpll_per = 0x4a008140, - .cm_idlest_dpll_per = 0x4a008144, - .cm_autoidle_dpll_per = 0x4a008148, - .cm_clksel_dpll_per = 0x4a00814c, - .cm_div_m2_dpll_per = 0x4a008150, - .cm_div_m3_dpll_per = 0x4a008154, - .cm_div_h11_dpll_per = 0x4a008158, - .cm_div_h12_dpll_per = 0x4a00815c, - .cm_div_h14_dpll_per = 0x4a008164, - .cm_ssc_deltamstep_dpll_per = 0x4a008168, - .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, - .cm_emu_override_dpll_per = 0x4a008170, - .cm_clkmode_dpll_usb = 0x4a008180, - .cm_idlest_dpll_usb = 0x4a008184, - .cm_autoidle_dpll_usb = 0x4a008188, - .cm_clksel_dpll_usb = 0x4a00818c, - .cm_div_m2_dpll_usb = 0x4a008190, - .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, - .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, - .cm_clkdcoldo_dpll_usb = 0x4a0081b4, - .cm_clkmode_dpll_unipro = 0x4a0081c0, - .cm_idlest_dpll_unipro = 0x4a0081c4, - .cm_autoidle_dpll_unipro = 0x4a0081c8, - .cm_clksel_dpll_unipro = 0x4a0081cc, - .cm_div_m2_dpll_unipro = 0x4a0081d0, - .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, - .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, - - /* cm2.core */ - .cm_coreaon_bandgap_clkctrl = 0x4a008648, - .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, - .cm_l3_1_clkstctrl = 0x4a008700, - .cm_l3_1_dynamicdep = 0x4a008708, - .cm_l3_1_l3_1_clkctrl = 0x4a008720, - .cm_l3_2_clkstctrl = 0x4a008800, - .cm_l3_2_dynamicdep = 0x4a008808, - .cm_l3_2_l3_2_clkctrl = 0x4a008820, - .cm_l3_gpmc_clkctrl = 0x4a008828, - .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, - .cm_mpu_m3_clkstctrl = 0x4a008900, - .cm_mpu_m3_staticdep = 0x4a008904, - .cm_mpu_m3_dynamicdep = 0x4a008908, - .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, - .cm_sdma_clkstctrl = 0x4a008a00, - .cm_sdma_staticdep = 0x4a008a04, - .cm_sdma_dynamicdep = 0x4a008a08, - .cm_sdma_sdma_clkctrl = 0x4a008a20, - .cm_memif_clkstctrl = 0x4a008b00, - .cm_memif_dmm_clkctrl = 0x4a008b20, - .cm_memif_emif_fw_clkctrl = 0x4a008b28, - .cm_memif_emif_1_clkctrl = 0x4a008b30, - .cm_memif_emif_2_clkctrl = 0x4a008b38, - .cm_memif_dll_clkctrl = 0x4a008b40, - .cm_memif_emif_h1_clkctrl = 0x4a008b50, - .cm_memif_emif_h2_clkctrl = 0x4a008b58, - .cm_memif_dll_h_clkctrl = 0x4a008b60, - .cm_c2c_clkstctrl = 0x4a008c00, - .cm_c2c_staticdep = 0x4a008c04, - .cm_c2c_dynamicdep = 0x4a008c08, - .cm_c2c_sad2d_clkctrl = 0x4a008c20, - .cm_c2c_modem_icr_clkctrl = 0x4a008c28, - .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, - .cm_l4cfg_clkstctrl = 0x4a008d00, - .cm_l4cfg_dynamicdep = 0x4a008d08, - .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, - .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, - .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, - .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, - .cm_l3instr_clkstctrl = 0x4a008e00, - .cm_l3instr_l3_3_clkctrl = 0x4a008e20, - .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, - .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, - - /* cm2.ivahd */ - .cm_ivahd_clkstctrl = 0x4a008f00, - .cm_ivahd_ivahd_clkctrl = 0x4a008f20, - .cm_ivahd_sl2_clkctrl = 0x4a008f28, - - /* cm2.cam */ - .cm_cam_clkstctrl = 0x4a009000, - .cm_cam_iss_clkctrl = 0x4a009020, - .cm_cam_fdif_clkctrl = 0x4a009028, - - /* cm2.dss */ - .cm_dss_clkstctrl = 0x4a009100, - .cm_dss_dss_clkctrl = 0x4a009120, - - /* cm2.sgx */ - .cm_sgx_clkstctrl = 0x4a009200, - .cm_sgx_sgx_clkctrl = 0x4a009220, - - /* cm2.l3init */ - .cm_l3init_clkstctrl = 0x4a009300, - .cm_l3init_hsmmc1_clkctrl = 0x4a009328, - .cm_l3init_hsmmc2_clkctrl = 0x4a009330, - .cm_l3init_hsi_clkctrl = 0x4a009338, - .cm_l3init_hsusbhost_clkctrl = 0x4a009358, - .cm_l3init_hsusbotg_clkctrl = 0x4a009360, - .cm_l3init_hsusbtll_clkctrl = 0x4a009368, - .cm_l3init_p1500_clkctrl = 0x4a009378, - .cm_l3init_sata_clkctrl = 0x4a009388, - .cm_l3init_fsusb_clkctrl = 0x4a0093d0, - .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, - .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, - - /* cm2.l4per */ - .cm_l4per_clkstctrl = 0x4a009400, - .cm_l4per_dynamicdep = 0x4a009408, - .cm_l4per_adc_clkctrl = 0x4a009420, - .cm_l4per_gptimer10_clkctrl = 0x4a009428, - .cm_l4per_gptimer11_clkctrl = 0x4a009430, - .cm_l4per_gptimer2_clkctrl = 0x4a009438, - .cm_l4per_gptimer3_clkctrl = 0x4a009440, - .cm_l4per_gptimer4_clkctrl = 0x4a009448, - .cm_l4per_gptimer9_clkctrl = 0x4a009450, - .cm_l4per_elm_clkctrl = 0x4a009458, - .cm_l4per_gpio2_clkctrl = 0x4a009460, - .cm_l4per_gpio3_clkctrl = 0x4a009468, - .cm_l4per_gpio4_clkctrl = 0x4a009470, - .cm_l4per_gpio5_clkctrl = 0x4a009478, - .cm_l4per_gpio6_clkctrl = 0x4a009480, - .cm_l4per_hdq1w_clkctrl = 0x4a009488, - .cm_l4per_hecc1_clkctrl = 0x4a009490, - .cm_l4per_hecc2_clkctrl = 0x4a009498, - .cm_l4per_i2c1_clkctrl = 0x4a0094a0, - .cm_l4per_i2c2_clkctrl = 0x4a0094a8, - .cm_l4per_i2c3_clkctrl = 0x4a0094b0, - .cm_l4per_i2c4_clkctrl = 0x4a0094b8, - .cm_l4per_l4per_clkctrl = 0x4a0094c0, - .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, - .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, - .cm_l4per_mgate_clkctrl = 0x4a0094e8, - .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, - .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, - .cm_l4per_mcspi3_clkctrl = 0x4a009500, - .cm_l4per_mcspi4_clkctrl = 0x4a009508, - .cm_l4per_gpio7_clkctrl = 0x4a009510, - .cm_l4per_gpio8_clkctrl = 0x4a009518, - .cm_l4per_mmcsd3_clkctrl = 0x4a009520, - .cm_l4per_mmcsd4_clkctrl = 0x4a009528, - .cm_l4per_msprohg_clkctrl = 0x4a009530, - .cm_l4per_slimbus2_clkctrl = 0x4a009538, - .cm_l4per_uart1_clkctrl = 0x4a009540, - .cm_l4per_uart2_clkctrl = 0x4a009548, - .cm_l4per_uart3_clkctrl = 0x4a009550, - .cm_l4per_uart4_clkctrl = 0x4a009558, - .cm_l4per_mmcsd5_clkctrl = 0x4a009560, - .cm_l4per_i2c5_clkctrl = 0x4a009568, - .cm_l4per_uart5_clkctrl = 0x4a009570, - .cm_l4per_uart6_clkctrl = 0x4a009578, - .cm_l4sec_clkstctrl = 0x4a009580, - .cm_l4sec_staticdep = 0x4a009584, - .cm_l4sec_dynamicdep = 0x4a009588, - .cm_l4sec_aes1_clkctrl = 0x4a0095a0, - .cm_l4sec_aes2_clkctrl = 0x4a0095a8, - .cm_l4sec_des3des_clkctrl = 0x4a0095b0, - .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, - .cm_l4sec_rng_clkctrl = 0x4a0095c0, - .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, - .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, - - /* l4 wkup regs */ - .cm_abe_pll_ref_clksel = 0x4ae0610c, - .cm_sys_clksel = 0x4ae06110, - .cm_wkup_clkstctrl = 0x4ae07800, - .cm_wkup_l4wkup_clkctrl = 0x4ae07820, - .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, - .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, - .cm_wkup_gpio1_clkctrl = 0x4ae07838, - .cm_wkup_gptimer1_clkctrl = 0x4ae07840, - .cm_wkup_gptimer12_clkctrl = 0x4ae07848, - .cm_wkup_synctimer_clkctrl = 0x4ae07850, - .cm_wkup_usim_clkctrl = 0x4ae07858, - .cm_wkup_sarram_clkctrl = 0x4ae07860, - .cm_wkup_keyboard_clkctrl = 0x4ae07878, - .cm_wkup_rtc_clkctrl = 0x4ae07880, - .cm_wkup_bandgap_clkctrl = 0x4ae07888, - .cm_wkupaon_scrm_clkctrl = 0x4ae07890, - .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, - .prm_rstctrl = 0x4ae07b00, - .prm_rstst = 0x4ae07b04, - .prm_rsttime = 0x4ae07b08, - .prm_vc_val_bypass = 0x4ae07ba0, - .prm_vc_cfg_i2c_mode = 0x4ae07bb4, - .prm_vc_cfg_i2c_clk = 0x4ae07bb8, - - /* SCRM stuff, used by some boards */ - .scrm_auxclk0 = 0x4ae0a310, - .scrm_auxclk1 = 0x4ae0a314, -}; - -struct omap_sys_ctrl_regs const omap5_ctrl = { - .control_status = 0x4A002134, - .control_std_fuse_die_id_0 = 0x4A002200, - .control_std_fuse_die_id_1 = 0x4A002208, - .control_std_fuse_die_id_2 = 0x4A00220C, - .control_std_fuse_die_id_3 = 0x4A002210, - .control_phy_power_usb = 0x4A002370, - .control_phy_power_sata = 0x4A002374, - .control_padconf_core_base = 0x4A002800, - .control_paconf_global = 0x4A002DA0, - .control_paconf_mode = 0x4A002DA4, - .control_smart1io_padconf_0 = 0x4A002DA8, - .control_smart1io_padconf_1 = 0x4A002DAC, - .control_smart1io_padconf_2 = 0x4A002DB0, - .control_smart2io_padconf_0 = 0x4A002DB4, - .control_smart2io_padconf_1 = 0x4A002DB8, - .control_smart2io_padconf_2 = 0x4A002DBC, - .control_smart3io_padconf_0 = 0x4A002DC0, - .control_smart3io_padconf_1 = 0x4A002DC4, - .control_pbias = 0x4A002E00, - .control_i2c_0 = 0x4A002E04, - .control_camera_rx = 0x4A002E08, - .control_hdmi_tx_phy = 0x4A002E0C, - .control_uniportm = 0x4A002E10, - .control_dsiphy = 0x4A002E14, - .control_mcbsplp = 0x4A002E18, - .control_usb2phycore = 0x4A002E1C, - .control_hdmi_1 = 0x4A002E20, - .control_hsi = 0x4A002E24, - .control_ddr3ch1_0 = 0x4A002E30, - .control_ddr3ch2_0 = 0x4A002E34, - .control_ddrch1_0 = 0x4A002E38, - .control_ddrch1_1 = 0x4A002E3C, - .control_ddrch2_0 = 0x4A002E40, - .control_ddrch2_1 = 0x4A002E44, - .control_lpddr2ch1_0 = 0x4A002E48, - .control_lpddr2ch1_1 = 0x4A002E4C, - .control_ddrio_0 = 0x4A002E50, - .control_ddrio_1 = 0x4A002E54, - .control_ddrio_2 = 0x4A002E58, - .control_hyst_1 = 0x4A002E5C, - .control_usbb_hsic_control = 0x4A002E60, - .control_c2c = 0x4A002E64, - .control_core_control_spare_rw = 0x4A002E68, - .control_core_control_spare_r = 0x4A002E6C, - .control_core_control_spare_r_c0 = 0x4A002E70, - .control_srcomp_north_side = 0x4A002E74, - .control_srcomp_south_side = 0x4A002E78, - .control_srcomp_east_side = 0x4A002E7C, - .control_srcomp_west_side = 0x4A002E80, - .control_srcomp_code_latch = 0x4A002E84, - .control_port_emif1_sdram_config = 0x4AE0C110, - .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, - .control_port_emif2_sdram_config = 0x4AE0C118, - .control_emif1_sdram_config_ext = 0x4AE0C144, - .control_emif2_sdram_config_ext = 0x4AE0C148, - .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, - .control_wkup_ldovbb_mm_voltage_ctrl = 0x4AE0C314, - .control_padconf_wkup_base = 0x4AE0C800, - .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, - .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, - .control_padconf_mode = 0x4AE0CDA8, - .control_xtal_oscillator = 0x4AE0CDAC, - .control_i2c_2 = 0x4AE0CDB0, - .control_ckobuffer = 0x4AE0CDB4, - .control_wkup_control_spare_rw = 0x4AE0CDB8, - .control_wkup_control_spare_r = 0x4AE0CDBC, - .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, - .control_srcomp_east_side_wkup = 0x4AE0CDC4, - .control_efuse_1 = 0x4AE0CDC8, - .control_efuse_2 = 0x4AE0CDCC, - .control_efuse_3 = 0x4AE0CDD0, - .control_efuse_4 = 0x4AE0CDD4, - .control_efuse_5 = 0x4AE0CDD8, - .control_efuse_6 = 0x4AE0CDDC, - .control_efuse_7 = 0x4AE0CDE0, - .control_efuse_8 = 0x4AE0CDE4, - .control_efuse_9 = 0x4AE0CDE8, - .control_efuse_10 = 0x4AE0CDEC, - .control_efuse_11 = 0x4AE0CDF0, - .control_efuse_12 = 0x4AE0CDF4, - .control_efuse_13 = 0x4AE0CDF8, -}; - -struct omap_sys_ctrl_regs const dra7xx_ctrl = { - .control_status = 0x4A002134, - .control_phy_power_usb = 0x4A002370, - .control_phy_power_sata = 0x4A002374, - .ctrl_core_sma_sw_0 = 0x4A0023FC, - .ctrl_core_sma_sw_1 = 0x4A002534, - .control_core_mac_id_0_lo = 0x4A002514, - .control_core_mac_id_0_hi = 0x4A002518, - .control_core_mac_id_1_lo = 0x4A00251C, - .control_core_mac_id_1_hi = 0x4A002520, - .control_core_mmr_lock1 = 0x4A002540, - .control_core_mmr_lock2 = 0x4A002544, - .control_core_mmr_lock3 = 0x4A002548, - .control_core_mmr_lock4 = 0x4A00254C, - .control_core_mmr_lock5 = 0x4A002550, - .control_core_control_io1 = 0x4A002554, - .control_core_control_io2 = 0x4A002558, - .control_paconf_global = 0x4A002DA0, - .control_paconf_mode = 0x4A002DA4, - .control_smart1io_padconf_0 = 0x4A002DA8, - .control_smart1io_padconf_1 = 0x4A002DAC, - .control_smart1io_padconf_2 = 0x4A002DB0, - .control_smart2io_padconf_0 = 0x4A002DB4, - .control_smart2io_padconf_1 = 0x4A002DB8, - .control_smart2io_padconf_2 = 0x4A002DBC, - .control_smart3io_padconf_0 = 0x4A002DC0, - .control_smart3io_padconf_1 = 0x4A002DC4, - .control_pbias = 0x4A002E00, - .control_i2c_0 = 0x4A002E04, - .control_camera_rx = 0x4A002E08, - .control_hdmi_tx_phy = 0x4A002E0C, - .control_uniportm = 0x4A002E10, - .control_dsiphy = 0x4A002E14, - .control_mcbsplp = 0x4A002E18, - .control_usb2phycore = 0x4A002E1C, - .control_hdmi_1 = 0x4A002E20, - .control_hsi = 0x4A002E24, - .control_ddr3ch1_0 = 0x4A002E30, - .control_ddr3ch2_0 = 0x4A002E34, - .control_ddrch1_0 = 0x4A002E38, - .control_ddrch1_1 = 0x4A002E3C, - .control_ddrch2_0 = 0x4A002E40, - .control_ddrch2_1 = 0x4A002E44, - .control_lpddr2ch1_0 = 0x4A002E48, - .control_lpddr2ch1_1 = 0x4A002E4C, - .control_ddrio_0 = 0x4A002E50, - .control_ddrio_1 = 0x4A002E54, - .control_ddrio_2 = 0x4A002E58, - .control_hyst_1 = 0x4A002E5C, - .control_usbb_hsic_control = 0x4A002E60, - .control_c2c = 0x4A002E64, - .control_core_control_spare_rw = 0x4A002E68, - .control_core_control_spare_r = 0x4A002E6C, - .control_core_control_spare_r_c0 = 0x4A002E70, - .control_srcomp_north_side = 0x4A002E74, - .control_srcomp_south_side = 0x4A002E78, - .control_srcomp_east_side = 0x4A002E7C, - .control_srcomp_west_side = 0x4A002E80, - .control_srcomp_code_latch = 0x4A002E84, - .control_ddr_control_ext_0 = 0x4A002E88, - .control_padconf_core_base = 0x4A003400, - .control_port_emif1_sdram_config = 0x4AE0C110, - .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, - .control_port_emif2_sdram_config = 0x4AE0C118, - .control_emif1_sdram_config_ext = 0x4AE0C144, - .control_emif2_sdram_config_ext = 0x4AE0C148, - .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, - .control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470, - .control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C, - .control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154, - .control_std_fuse_die_id_0 = 0x4AE0C200, - .control_std_fuse_die_id_1 = 0x4AE0C208, - .control_std_fuse_die_id_2 = 0x4AE0C20C, - .control_std_fuse_die_id_3 = 0x4AE0C210, - .control_padconf_mode = 0x4AE0C5A0, - .control_xtal_oscillator = 0x4AE0C5A4, - .control_i2c_2 = 0x4AE0C5A8, - .control_ckobuffer = 0x4AE0C5AC, - .control_wkup_control_spare_rw = 0x4AE0C5B0, - .control_wkup_control_spare_r = 0x4AE0C5B4, - .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, - .control_srcomp_east_side_wkup = 0x4AE0C5BC, - .control_efuse_1 = 0x4AE0C5C8, - .control_efuse_2 = 0x4AE0C5CC, - .control_efuse_3 = 0x4AE0C5D0, - .control_efuse_4 = 0x4AE0C5D4, - .control_efuse_13 = 0x4AE0C5F0, - .iodelay_config_base = 0x4844A000, -}; - -struct prcm_regs const omap5_es2_prcm = { - /* cm1.ckgen */ - .cm_clksel_core = 0x4a004100, - .cm_clksel_abe = 0x4a004108, - .cm_dll_ctrl = 0x4a004110, - .cm_clkmode_dpll_core = 0x4a004120, - .cm_idlest_dpll_core = 0x4a004124, - .cm_autoidle_dpll_core = 0x4a004128, - .cm_clksel_dpll_core = 0x4a00412c, - .cm_div_m2_dpll_core = 0x4a004130, - .cm_div_m3_dpll_core = 0x4a004134, - .cm_div_h11_dpll_core = 0x4a004138, - .cm_div_h12_dpll_core = 0x4a00413c, - .cm_div_h13_dpll_core = 0x4a004140, - .cm_div_h14_dpll_core = 0x4a004144, - .cm_ssc_deltamstep_dpll_core = 0x4a004148, - .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, - .cm_div_h21_dpll_core = 0x4a004150, - .cm_div_h22_dpllcore = 0x4a004154, - .cm_div_h23_dpll_core = 0x4a004158, - .cm_div_h24_dpll_core = 0x4a00415c, - .cm_clkmode_dpll_mpu = 0x4a004160, - .cm_idlest_dpll_mpu = 0x4a004164, - .cm_autoidle_dpll_mpu = 0x4a004168, - .cm_clksel_dpll_mpu = 0x4a00416c, - .cm_div_m2_dpll_mpu = 0x4a004170, - .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, - .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, - .cm_bypclk_dpll_mpu = 0x4a00419c, - .cm_clkmode_dpll_iva = 0x4a0041a0, - .cm_idlest_dpll_iva = 0x4a0041a4, - .cm_autoidle_dpll_iva = 0x4a0041a8, - .cm_clksel_dpll_iva = 0x4a0041ac, - .cm_div_h11_dpll_iva = 0x4a0041b8, - .cm_div_h12_dpll_iva = 0x4a0041bc, - .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, - .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, - .cm_bypclk_dpll_iva = 0x4a0041dc, - .cm_clkmode_dpll_abe = 0x4a0041e0, - .cm_idlest_dpll_abe = 0x4a0041e4, - .cm_autoidle_dpll_abe = 0x4a0041e8, - .cm_clksel_dpll_abe = 0x4a0041ec, - .cm_div_m2_dpll_abe = 0x4a0041f0, - .cm_div_m3_dpll_abe = 0x4a0041f4, - .cm_ssc_deltamstep_dpll_abe = 0x4a004208, - .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, - .cm_clkmode_dpll_ddrphy = 0x4a004220, - .cm_idlest_dpll_ddrphy = 0x4a004224, - .cm_autoidle_dpll_ddrphy = 0x4a004228, - .cm_clksel_dpll_ddrphy = 0x4a00422c, - .cm_div_m2_dpll_ddrphy = 0x4a004230, - .cm_div_h11_dpll_ddrphy = 0x4a004238, - .cm_div_h12_dpll_ddrphy = 0x4a00423c, - .cm_div_h13_dpll_ddrphy = 0x4a004240, - .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, - .cm_shadow_freq_config1 = 0x4a004260, - .cm_mpu_mpu_clkctrl = 0x4a004320, - - /* cm1.dsp */ - .cm_dsp_clkstctrl = 0x4a004400, - .cm_dsp_dsp_clkctrl = 0x4a004420, - - /* cm1.abe */ - .cm1_abe_clkstctrl = 0x4a004500, - .cm1_abe_l4abe_clkctrl = 0x4a004520, - .cm1_abe_aess_clkctrl = 0x4a004528, - .cm1_abe_pdm_clkctrl = 0x4a004530, - .cm1_abe_dmic_clkctrl = 0x4a004538, - .cm1_abe_mcasp_clkctrl = 0x4a004540, - .cm1_abe_mcbsp1_clkctrl = 0x4a004548, - .cm1_abe_mcbsp2_clkctrl = 0x4a004550, - .cm1_abe_mcbsp3_clkctrl = 0x4a004558, - .cm1_abe_slimbus_clkctrl = 0x4a004560, - .cm1_abe_timer5_clkctrl = 0x4a004568, - .cm1_abe_timer6_clkctrl = 0x4a004570, - .cm1_abe_timer7_clkctrl = 0x4a004578, - .cm1_abe_timer8_clkctrl = 0x4a004580, - .cm1_abe_wdt3_clkctrl = 0x4a004588, - - /* cm2.ckgen */ - .cm_clksel_mpu_m3_iss_root = 0x4a008100, - .cm_clksel_usb_60mhz = 0x4a008104, - .cm_scale_fclk = 0x4a008108, - .cm_core_dvfs_perf1 = 0x4a008110, - .cm_core_dvfs_perf2 = 0x4a008114, - .cm_core_dvfs_perf3 = 0x4a008118, - .cm_core_dvfs_perf4 = 0x4a00811c, - .cm_core_dvfs_current = 0x4a008124, - .cm_iva_dvfs_perf_tesla = 0x4a008128, - .cm_iva_dvfs_perf_ivahd = 0x4a00812c, - .cm_iva_dvfs_perf_abe = 0x4a008130, - .cm_iva_dvfs_current = 0x4a008138, - .cm_clkmode_dpll_per = 0x4a008140, - .cm_idlest_dpll_per = 0x4a008144, - .cm_autoidle_dpll_per = 0x4a008148, - .cm_clksel_dpll_per = 0x4a00814c, - .cm_div_m2_dpll_per = 0x4a008150, - .cm_div_m3_dpll_per = 0x4a008154, - .cm_div_h11_dpll_per = 0x4a008158, - .cm_div_h12_dpll_per = 0x4a00815c, - .cm_div_h13_dpll_per = 0x4a008160, - .cm_div_h14_dpll_per = 0x4a008164, - .cm_ssc_deltamstep_dpll_per = 0x4a008168, - .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, - .cm_emu_override_dpll_per = 0x4a008170, - .cm_clkmode_dpll_usb = 0x4a008180, - .cm_idlest_dpll_usb = 0x4a008184, - .cm_autoidle_dpll_usb = 0x4a008188, - .cm_clksel_dpll_usb = 0x4a00818c, - .cm_div_m2_dpll_usb = 0x4a008190, - .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, - .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, - .cm_clkdcoldo_dpll_usb = 0x4a0081b4, - .cm_clkmode_dpll_unipro = 0x4a0081c0, - .cm_idlest_dpll_unipro = 0x4a0081c4, - .cm_autoidle_dpll_unipro = 0x4a0081c8, - .cm_clksel_dpll_unipro = 0x4a0081cc, - .cm_div_m2_dpll_unipro = 0x4a0081d0, - .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, - .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, - .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640, - .cm_coreaon_bandgap_clkctrl = 0x4a008648, - .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, - - /* cm2.core */ - .cm_l3_1_clkstctrl = 0x4a008700, - .cm_l3_1_dynamicdep = 0x4a008708, - .cm_l3_1_l3_1_clkctrl = 0x4a008720, - .cm_l3_2_clkstctrl = 0x4a008800, - .cm_l3_2_dynamicdep = 0x4a008808, - .cm_l3_2_l3_2_clkctrl = 0x4a008820, - .cm_l3_gpmc_clkctrl = 0x4a008828, - .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, - .cm_mpu_m3_clkstctrl = 0x4a008900, - .cm_mpu_m3_staticdep = 0x4a008904, - .cm_mpu_m3_dynamicdep = 0x4a008908, - .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, - .cm_sdma_clkstctrl = 0x4a008a00, - .cm_sdma_staticdep = 0x4a008a04, - .cm_sdma_dynamicdep = 0x4a008a08, - .cm_sdma_sdma_clkctrl = 0x4a008a20, - .cm_memif_clkstctrl = 0x4a008b00, - .cm_memif_dmm_clkctrl = 0x4a008b20, - .cm_memif_emif_fw_clkctrl = 0x4a008b28, - .cm_memif_emif_1_clkctrl = 0x4a008b30, - .cm_memif_emif_2_clkctrl = 0x4a008b38, - .cm_memif_dll_clkctrl = 0x4a008b40, - .cm_memif_emif_h1_clkctrl = 0x4a008b50, - .cm_memif_emif_h2_clkctrl = 0x4a008b58, - .cm_memif_dll_h_clkctrl = 0x4a008b60, - .cm_c2c_clkstctrl = 0x4a008c00, - .cm_c2c_staticdep = 0x4a008c04, - .cm_c2c_dynamicdep = 0x4a008c08, - .cm_c2c_sad2d_clkctrl = 0x4a008c20, - .cm_c2c_modem_icr_clkctrl = 0x4a008c28, - .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, - .cm_l4cfg_clkstctrl = 0x4a008d00, - .cm_l4cfg_dynamicdep = 0x4a008d08, - .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, - .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, - .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, - .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, - .cm_l3instr_clkstctrl = 0x4a008e00, - .cm_l3instr_l3_3_clkctrl = 0x4a008e20, - .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, - .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, - .cm_l4per_clkstctrl = 0x4a009000, - .cm_l4per_dynamicdep = 0x4a009008, - .cm_l4per_adc_clkctrl = 0x4a009020, - .cm_l4per_gptimer10_clkctrl = 0x4a009028, - .cm_l4per_gptimer11_clkctrl = 0x4a009030, - .cm_l4per_gptimer2_clkctrl = 0x4a009038, - .cm_l4per_gptimer3_clkctrl = 0x4a009040, - .cm_l4per_gptimer4_clkctrl = 0x4a009048, - .cm_l4per_gptimer9_clkctrl = 0x4a009050, - .cm_l4per_elm_clkctrl = 0x4a009058, - .cm_l4per_gpio2_clkctrl = 0x4a009060, - .cm_l4per_gpio3_clkctrl = 0x4a009068, - .cm_l4per_gpio4_clkctrl = 0x4a009070, - .cm_l4per_gpio5_clkctrl = 0x4a009078, - .cm_l4per_gpio6_clkctrl = 0x4a009080, - .cm_l4per_hdq1w_clkctrl = 0x4a009088, - .cm_l4per_hecc1_clkctrl = 0x4a009090, - .cm_l4per_hecc2_clkctrl = 0x4a009098, - .cm_l4per_i2c1_clkctrl = 0x4a0090a0, - .cm_l4per_i2c2_clkctrl = 0x4a0090a8, - .cm_l4per_i2c3_clkctrl = 0x4a0090b0, - .cm_l4per_i2c4_clkctrl = 0x4a0090b8, - .cm_l4per_l4per_clkctrl = 0x4a0090c0, - .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, - .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, - .cm_l4per_mgate_clkctrl = 0x4a0090e8, - .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, - .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, - .cm_l4per_mcspi3_clkctrl = 0x4a009100, - .cm_l4per_mcspi4_clkctrl = 0x4a009108, - .cm_l4per_gpio7_clkctrl = 0x4a009110, - .cm_l4per_gpio8_clkctrl = 0x4a009118, - .cm_l4per_mmcsd3_clkctrl = 0x4a009120, - .cm_l4per_mmcsd4_clkctrl = 0x4a009128, - .cm_l4per_msprohg_clkctrl = 0x4a009130, - .cm_l4per_slimbus2_clkctrl = 0x4a009138, - .cm_l4per_uart1_clkctrl = 0x4a009140, - .cm_l4per_uart2_clkctrl = 0x4a009148, - .cm_l4per_uart3_clkctrl = 0x4a009150, - .cm_l4per_uart4_clkctrl = 0x4a009158, - .cm_l4per_mmcsd5_clkctrl = 0x4a009160, - .cm_l4per_i2c5_clkctrl = 0x4a009168, - .cm_l4per_uart5_clkctrl = 0x4a009170, - .cm_l4per_uart6_clkctrl = 0x4a009178, - .cm_l4sec_clkstctrl = 0x4a009180, - .cm_l4sec_staticdep = 0x4a009184, - .cm_l4sec_dynamicdep = 0x4a009188, - .cm_l4sec_aes1_clkctrl = 0x4a0091a0, - .cm_l4sec_aes2_clkctrl = 0x4a0091a8, - .cm_l4sec_des3des_clkctrl = 0x4a0091b0, - .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, - .cm_l4sec_rng_clkctrl = 0x4a0091c0, - .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, - .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, - - /* cm2.ivahd */ - .cm_ivahd_clkstctrl = 0x4a009200, - .cm_ivahd_ivahd_clkctrl = 0x4a009220, - .cm_ivahd_sl2_clkctrl = 0x4a009228, - - /* cm2.cam */ - .cm_cam_clkstctrl = 0x4a009300, - .cm_cam_iss_clkctrl = 0x4a009320, - .cm_cam_fdif_clkctrl = 0x4a009328, - - /* cm2.dss */ - .cm_dss_clkstctrl = 0x4a009400, - .cm_dss_dss_clkctrl = 0x4a009420, - - /* cm2.sgx */ - .cm_sgx_clkstctrl = 0x4a009500, - .cm_sgx_sgx_clkctrl = 0x4a009520, - - /* cm2.l3init */ - .cm_l3init_clkstctrl = 0x4a009600, - - /* cm2.l3init */ - .cm_l3init_hsmmc1_clkctrl = 0x4a009628, - .cm_l3init_hsmmc2_clkctrl = 0x4a009630, - .cm_l3init_hsi_clkctrl = 0x4a009638, - .cm_l3init_hsusbhost_clkctrl = 0x4a009658, - .cm_l3init_hsusbotg_clkctrl = 0x4a009660, - .cm_l3init_hsusbtll_clkctrl = 0x4a009668, - .cm_l3init_p1500_clkctrl = 0x4a009678, - .cm_l3init_sata_clkctrl = 0x4a009688, - .cm_l3init_fsusb_clkctrl = 0x4a0096d0, - .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, - .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, - .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0, - - /* prm irqstatus regs */ - .prm_irqstatus_mpu = 0x4ae06010, - .prm_irqstatus_mpu_2 = 0x4ae06014, - - /* l4 wkup regs */ - .cm_abe_pll_ref_clksel = 0x4ae0610c, - .cm_sys_clksel = 0x4ae06110, - .cm_wkup_clkstctrl = 0x4ae07900, - .cm_wkup_l4wkup_clkctrl = 0x4ae07920, - .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, - .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, - .cm_wkup_gpio1_clkctrl = 0x4ae07938, - .cm_wkup_gptimer1_clkctrl = 0x4ae07940, - .cm_wkup_gptimer12_clkctrl = 0x4ae07948, - .cm_wkup_synctimer_clkctrl = 0x4ae07950, - .cm_wkup_usim_clkctrl = 0x4ae07958, - .cm_wkup_sarram_clkctrl = 0x4ae07960, - .cm_wkup_keyboard_clkctrl = 0x4ae07978, - .cm_wkup_rtc_clkctrl = 0x4ae07980, - .cm_wkup_bandgap_clkctrl = 0x4ae07988, - .cm_wkupaon_scrm_clkctrl = 0x4ae07990, - .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, - .prm_rstctrl = 0x4ae07c00, - .prm_rstst = 0x4ae07c04, - .prm_rsttime = 0x4ae07c08, - .prm_vc_val_bypass = 0x4ae07ca0, - .prm_vc_cfg_i2c_mode = 0x4ae07cb4, - .prm_vc_cfg_i2c_clk = 0x4ae07cb8, - - .prm_abbldo_mpu_setup = 0x4ae07cdc, - .prm_abbldo_mpu_ctrl = 0x4ae07ce0, - .prm_abbldo_mm_setup = 0x4ae07ce4, - .prm_abbldo_mm_ctrl = 0x4ae07ce8, - - /* SCRM stuff, used by some boards */ - .scrm_auxclk0 = 0x4ae0a310, - .scrm_auxclk1 = 0x4ae0a314, -}; - -struct prcm_regs const dra7xx_prcm = { - /* cm1.ckgen */ - .cm_clksel_core = 0x4a005100, - .cm_clksel_abe = 0x4a005108, - .cm_dll_ctrl = 0x4a005110, - .cm_clkmode_dpll_core = 0x4a005120, - .cm_idlest_dpll_core = 0x4a005124, - .cm_autoidle_dpll_core = 0x4a005128, - .cm_clksel_dpll_core = 0x4a00512c, - .cm_div_m2_dpll_core = 0x4a005130, - .cm_div_m3_dpll_core = 0x4a005134, - .cm_div_h11_dpll_core = 0x4a005138, - .cm_div_h12_dpll_core = 0x4a00513c, - .cm_div_h13_dpll_core = 0x4a005140, - .cm_div_h14_dpll_core = 0x4a005144, - .cm_ssc_deltamstep_dpll_core = 0x4a005148, - .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c, - .cm_div_h21_dpll_core = 0x4a005150, - .cm_div_h22_dpllcore = 0x4a005154, - .cm_div_h23_dpll_core = 0x4a005158, - .cm_div_h24_dpll_core = 0x4a00515c, - .cm_clkmode_dpll_mpu = 0x4a005160, - .cm_idlest_dpll_mpu = 0x4a005164, - .cm_autoidle_dpll_mpu = 0x4a005168, - .cm_clksel_dpll_mpu = 0x4a00516c, - .cm_div_m2_dpll_mpu = 0x4a005170, - .cm_ssc_deltamstep_dpll_mpu = 0x4a005188, - .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c, - .cm_bypclk_dpll_mpu = 0x4a00519c, - .cm_clkmode_dpll_iva = 0x4a0051a0, - .cm_idlest_dpll_iva = 0x4a0051a4, - .cm_autoidle_dpll_iva = 0x4a0051a8, - .cm_clksel_dpll_iva = 0x4a0051ac, - .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8, - .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc, - .cm_bypclk_dpll_iva = 0x4a0051dc, - .cm_clkmode_dpll_abe = 0x4a0051e0, - .cm_idlest_dpll_abe = 0x4a0051e4, - .cm_autoidle_dpll_abe = 0x4a0051e8, - .cm_clksel_dpll_abe = 0x4a0051ec, - .cm_div_m2_dpll_abe = 0x4a0051f0, - .cm_div_m3_dpll_abe = 0x4a0051f4, - .cm_ssc_deltamstep_dpll_abe = 0x4a005208, - .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c, - .cm_clkmode_dpll_ddrphy = 0x4a005210, - .cm_idlest_dpll_ddrphy = 0x4a005214, - .cm_autoidle_dpll_ddrphy = 0x4a005218, - .cm_clksel_dpll_ddrphy = 0x4a00521c, - .cm_div_m2_dpll_ddrphy = 0x4a005220, - .cm_div_h11_dpll_ddrphy = 0x4a005228, - .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, - .cm_clkmode_dpll_dsp = 0x4a005234, - .cm_shadow_freq_config1 = 0x4a005260, - .cm_clkmode_dpll_gmac = 0x4a0052a8, - .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, - .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, - .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698, - .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0, - - /* cm1.mpu */ - .cm_mpu_mpu_clkctrl = 0x4a005320, - - /* cm1.dsp */ - .cm_dsp_clkstctrl = 0x4a005400, - .cm_dsp_dsp_clkctrl = 0x4a005420, - - /* cm IPU */ - .cm_ipu_clkstctrl = 0x4a005540, - .cm_ipu_i2c5_clkctrl = 0x4a005578, - - /* prm irqstatus regs */ - .prm_irqstatus_mpu = 0x4ae06010, - .prm_irqstatus_mpu_2 = 0x4ae06014, - - /* cm2.ckgen */ - .cm_clksel_usb_60mhz = 0x4a008104, - .cm_clkmode_dpll_per = 0x4a008140, - .cm_idlest_dpll_per = 0x4a008144, - .cm_autoidle_dpll_per = 0x4a008148, - .cm_clksel_dpll_per = 0x4a00814c, - .cm_div_m2_dpll_per = 0x4a008150, - .cm_div_m3_dpll_per = 0x4a008154, - .cm_div_h11_dpll_per = 0x4a008158, - .cm_div_h12_dpll_per = 0x4a00815c, - .cm_div_h13_dpll_per = 0x4a008160, - .cm_div_h14_dpll_per = 0x4a008164, - .cm_ssc_deltamstep_dpll_per = 0x4a008168, - .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, - .cm_clkmode_dpll_usb = 0x4a008180, - .cm_idlest_dpll_usb = 0x4a008184, - .cm_autoidle_dpll_usb = 0x4a008188, - .cm_clksel_dpll_usb = 0x4a00818c, - .cm_div_m2_dpll_usb = 0x4a008190, - .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, - .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, - .cm_clkdcoldo_dpll_usb = 0x4a0081b4, - .cm_clkmode_dpll_pcie_ref = 0x4a008200, - .cm_clkmode_apll_pcie = 0x4a00821c, - .cm_idlest_apll_pcie = 0x4a008220, - .cm_div_m2_apll_pcie = 0x4a008224, - .cm_clkvcoldo_apll_pcie = 0x4a008228, - - /* cm2.core */ - .cm_l3_1_clkstctrl = 0x4a008700, - .cm_l3_1_dynamicdep = 0x4a008708, - .cm_l3_1_l3_1_clkctrl = 0x4a008720, - .cm_l3_gpmc_clkctrl = 0x4a008728, - .cm_mpu_m3_clkstctrl = 0x4a008900, - .cm_mpu_m3_staticdep = 0x4a008904, - .cm_mpu_m3_dynamicdep = 0x4a008908, - .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, - .cm_sdma_clkstctrl = 0x4a008a00, - .cm_sdma_staticdep = 0x4a008a04, - .cm_sdma_dynamicdep = 0x4a008a08, - .cm_sdma_sdma_clkctrl = 0x4a008a20, - .cm_memif_clkstctrl = 0x4a008b00, - .cm_memif_dmm_clkctrl = 0x4a008b20, - .cm_memif_emif_fw_clkctrl = 0x4a008b28, - .cm_memif_emif_1_clkctrl = 0x4a008b30, - .cm_memif_emif_2_clkctrl = 0x4a008b38, - .cm_memif_dll_clkctrl = 0x4a008b40, - .cm_l4cfg_clkstctrl = 0x4a008d00, - .cm_l4cfg_dynamicdep = 0x4a008d08, - .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, - .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, - .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, - .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, - .cm_l3instr_clkstctrl = 0x4a008e00, - .cm_l3instr_l3_3_clkctrl = 0x4a008e20, - .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, - .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, - - /* cm2.ivahd */ - .cm_ivahd_clkstctrl = 0x4a008f00, - .cm_ivahd_ivahd_clkctrl = 0x4a008f20, - .cm_ivahd_sl2_clkctrl = 0x4a008f28, - - /* cm2.cam */ - .cm_cam_clkstctrl = 0x4a009000, - .cm_cam_vip1_clkctrl = 0x4a009020, - .cm_cam_vip2_clkctrl = 0x4a009028, - .cm_cam_vip3_clkctrl = 0x4a009030, - .cm_cam_lvdsrx_clkctrl = 0x4a009038, - .cm_cam_csi1_clkctrl = 0x4a009040, - .cm_cam_csi2_clkctrl = 0x4a009048, - - /* cm2.dss */ - .cm_dss_clkstctrl = 0x4a009100, - .cm_dss_dss_clkctrl = 0x4a009120, - - /* cm2.sgx */ - .cm_sgx_clkstctrl = 0x4a009200, - .cm_sgx_sgx_clkctrl = 0x4a009220, - - /* cm2.l3init */ - .cm_l3init_clkstctrl = 0x4a009300, - - /* cm2.l3init */ - .cm_l3init_hsmmc1_clkctrl = 0x4a009328, - .cm_l3init_hsmmc2_clkctrl = 0x4a009330, - .cm_l3init_hsusbhost_clkctrl = 0x4a009340, - .cm_l3init_hsusbotg_clkctrl = 0x4a009348, - .cm_l3init_hsusbtll_clkctrl = 0x4a009350, - .cm_l3init_sata_clkctrl = 0x4a009388, - .cm_gmac_clkstctrl = 0x4a0093c0, - .cm_gmac_gmac_clkctrl = 0x4a0093d0, - .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, - .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, - .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, - .cm_l3init_usb_otg_ss2_clkctrl = 0x4a009340, - - /* cm2.l4per */ - .cm_l4per_clkstctrl = 0x4a009700, - .cm_l4per_dynamicdep = 0x4a009708, - .cm_l4per_gptimer10_clkctrl = 0x4a009728, - .cm_l4per_gptimer11_clkctrl = 0x4a009730, - .cm_l4per_gptimer2_clkctrl = 0x4a009738, - .cm_l4per_gptimer3_clkctrl = 0x4a009740, - .cm_l4per_gptimer4_clkctrl = 0x4a009748, - .cm_l4per_gptimer9_clkctrl = 0x4a009750, - .cm_l4per_elm_clkctrl = 0x4a009758, - .cm_l4per_gpio2_clkctrl = 0x4a009760, - .cm_l4per_gpio3_clkctrl = 0x4a009768, - .cm_l4per_gpio4_clkctrl = 0x4a009770, - .cm_l4per_gpio5_clkctrl = 0x4a009778, - .cm_l4per_gpio6_clkctrl = 0x4a009780, - .cm_l4per_hdq1w_clkctrl = 0x4a009788, - .cm_l4per_i2c1_clkctrl = 0x4a0097a0, - .cm_l4per_i2c2_clkctrl = 0x4a0097a8, - .cm_l4per_i2c3_clkctrl = 0x4a0097b0, - .cm_l4per_i2c4_clkctrl = 0x4a0097b8, - .cm_l4per_l4per_clkctrl = 0x4a0097c0, - .cm_l4per_mcspi1_clkctrl = 0x4a0097f0, - .cm_l4per_mcspi2_clkctrl = 0x4a0097f8, - .cm_l4per_mcspi3_clkctrl = 0x4a009800, - .cm_l4per_mcspi4_clkctrl = 0x4a009808, - .cm_l4per_gpio7_clkctrl = 0x4a009810, - .cm_l4per_gpio8_clkctrl = 0x4a009818, - .cm_l4per_mmcsd3_clkctrl = 0x4a009820, - .cm_l4per_mmcsd4_clkctrl = 0x4a009828, - .cm_l4per_qspi_clkctrl = 0x4a009838, - .cm_l4per_uart1_clkctrl = 0x4a009840, - .cm_l4per_uart2_clkctrl = 0x4a009848, - .cm_l4per_uart3_clkctrl = 0x4a009850, - .cm_l4per_uart4_clkctrl = 0x4a009858, - .cm_l4per_uart5_clkctrl = 0x4a009870, - .cm_l4sec_clkstctrl = 0x4a009880, - .cm_l4sec_staticdep = 0x4a009884, - .cm_l4sec_dynamicdep = 0x4a009888, - .cm_l4sec_aes1_clkctrl = 0x4a0098a0, - .cm_l4sec_aes2_clkctrl = 0x4a0098a8, - .cm_l4sec_des3des_clkctrl = 0x4a0098b0, - .cm_l4sec_rng_clkctrl = 0x4a0098c0, - .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8, - .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8, - - /* l4 wkup regs */ - .cm_abe_pll_ref_clksel = 0x4ae0610c, - .cm_sys_clksel = 0x4ae06110, - .cm_abe_pll_sys_clksel = 0x4ae06118, - .cm_wkup_clkstctrl = 0x4ae07800, - .cm_wkup_l4wkup_clkctrl = 0x4ae07820, - .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, - .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, - .cm_wkup_gpio1_clkctrl = 0x4ae07838, - .cm_wkup_gptimer1_clkctrl = 0x4ae07840, - .cm_wkup_gptimer12_clkctrl = 0x4ae07848, - .cm_wkup_sarram_clkctrl = 0x4ae07860, - .cm_wkup_keyboard_clkctrl = 0x4ae07878, - .cm_wkupaon_scrm_clkctrl = 0x4ae07890, - .prm_rstctrl = 0x4ae07d00, - .prm_rstst = 0x4ae07d04, - .prm_rsttime = 0x4ae07d08, - .prm_io_pmctrl = 0x4ae07d20, - .prm_vc_val_bypass = 0x4ae07da0, - .prm_vc_cfg_i2c_mode = 0x4ae07db4, - .prm_vc_cfg_i2c_clk = 0x4ae07db8, - - .prm_abbldo_mpu_setup = 0x4AE07DDC, - .prm_abbldo_mpu_ctrl = 0x4AE07DE0, - .prm_abbldo_iva_setup = 0x4AE07E34, - .prm_abbldo_iva_ctrl = 0x4AE07E24, - .prm_abbldo_eve_setup = 0x4AE07E30, - .prm_abbldo_eve_ctrl = 0x4AE07E20, - .prm_abbldo_gpu_setup = 0x4AE07DE4, - .prm_abbldo_gpu_ctrl = 0x4AE07DE8, - - /*l3main1 edma*/ - .cm_l3main1_tptc1_clkctrl = 0x4a008778, - .cm_l3main1_tptc2_clkctrl = 0x4a008780, -}; - -void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits) -{ - u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 : - (*ctrl)->ctrl_core_sma_sw_0; - clrsetbits_le32(reg, clear_bits, set_bits); -} diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c deleted file mode 100644 index 7712923d857..00000000000 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ /dev/null @@ -1,742 +0,0 @@ -/* - * Timing and Organization details of the ddr device parts used in OMAP5 - * EVM - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * Sricharan R - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* - * This file provides details of the LPDDR2 SDRAM parts used on OMAP5 - * EVM. Since the parts used and geometry are identical for - * evm for a given OMAP5 revision, this information is kept - * here instead of being in board directory. However the key functions - * exported are weakly linked so that they can be over-ridden in the board - * directory if there is a OMAP5 board in the future that uses a different - * memory device or geometry. - * - * For any new board with different memory devices over-ride one or more - * of the following functions as per the CONFIG flags you intend to enable: - * - emif_get_reg_dump() - * - emif_get_dmm_regs() - * - emif_get_device_details() - * - emif_get_device_timings() - */ - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -const struct emif_regs emif_regs_532_mhz_2cs = { - .sdram_config_init = 0x80800EBA, - .sdram_config = 0x808022BA, - .ref_ctrl = 0x0000081A, - .sdram_tim1 = 0x772F6873, - .sdram_tim2 = 0x304a129a, - .sdram_tim3 = 0x02f7e45f, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x000b3215, - .temp_alert_config = 0x08000a05, - .emif_ddr_phy_ctlr_1_init = 0x0E28420d, - .emif_ddr_phy_ctlr_1 = 0x0E28420d, - .emif_ddr_ext_phy_ctrl_1 = 0x04020080, - .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, - .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, - .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, - .emif_ddr_ext_phy_ctrl_5 = 0x04010040 -}; - -const struct emif_regs emif_regs_532_mhz_2cs_es2 = { - .sdram_config_init = 0x80800EBA, - .sdram_config = 0x808022BA, - .ref_ctrl = 0x0000081A, - .sdram_tim1 = 0x772F6873, - .sdram_tim2 = 0x304a129a, - .sdram_tim3 = 0x02f7e45f, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x100b3215, - .temp_alert_config = 0x08000a05, - .emif_ddr_phy_ctlr_1_init = 0x0E30400d, - .emif_ddr_phy_ctlr_1 = 0x0E30400d, - .emif_ddr_ext_phy_ctrl_1 = 0x04020080, - .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, - .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, - .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, - .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33, -}; - -const struct emif_regs emif_regs_266_mhz_2cs = { - .sdram_config_init = 0x80800EBA, - .sdram_config = 0x808022BA, - .ref_ctrl = 0x0000040D, - .sdram_tim1 = 0x2A86B419, - .sdram_tim2 = 0x1025094A, - .sdram_tim3 = 0x026BA22F, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x000b3215, - .temp_alert_config = 0x08000a05, - .emif_ddr_phy_ctlr_1_init = 0x0E28420d, - .emif_ddr_phy_ctlr_1 = 0x0E28420d, - .emif_ddr_ext_phy_ctrl_1 = 0x04020080, - .emif_ddr_ext_phy_ctrl_2 = 0x0A414829, - .emif_ddr_ext_phy_ctrl_3 = 0x14829052, - .emif_ddr_ext_phy_ctrl_4 = 0x000520A4, - .emif_ddr_ext_phy_ctrl_5 = 0x04010040 -}; - -const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { - .sdram_config_init = 0x61851B32, - .sdram_config = 0x61851B32, - .sdram_config2 = 0x0, - .ref_ctrl = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0020420A, - .emif_ddr_phy_ctlr_1 = 0x0024420A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00000000, - .emif_ddr_ext_phy_ctrl_3 = 0x00000000, - .emif_ddr_ext_phy_ctrl_4 = 0x00000000, - .emif_ddr_ext_phy_ctrl_5 = 0x04010040, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { - .sdram_config_init = 0x61851B32, - .sdram_config = 0x61851B32, - .sdram_config2 = 0x0, - .ref_ctrl = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x1007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0030400A, - .emif_ddr_phy_ctlr_1 = 0x0034400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00000000, - .emif_ddr_ext_phy_ctrl_3 = 0x00000000, - .emif_ddr_ext_phy_ctrl_4 = 0x00000000, - .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x40000305 -}; - -const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80740300, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) -{ - switch (omap_revision()) { - case OMAP5430_ES1_0: - *regs = &emif_regs_532_mhz_2cs; - break; - case OMAP5432_ES1_0: - *regs = &emif_regs_ddr3_532_mhz_1cs; - break; - case OMAP5430_ES2_0: - *regs = &emif_regs_532_mhz_2cs_es2; - break; - case OMAP5432_ES2_0: - default: - *regs = &emif_regs_ddr3_532_mhz_1cs_es2; - break; - } -} - -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) - __attribute__((weak, alias("emif_get_reg_dump_sdp"))); - -static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs - **dmm_lisa_regs) -{ - switch (omap_revision()) { - case OMAP5430_ES1_0: - case OMAP5430_ES2_0: - case OMAP5432_ES1_0: - case OMAP5432_ES2_0: - default: - *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; - break; - } - -} - -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) - __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); -#else - -static const struct lpddr2_device_details dev_4G_S4_details = { - .type = LPDDR2_TYPE_S4, - .density = LPDDR2_DENSITY_4Gb, - .io_width = LPDDR2_IO_WIDTH_32, - .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG -}; - -static void emif_get_device_details_sdp(u32 emif_nr, - struct lpddr2_device_details *cs0_device_details, - struct lpddr2_device_details *cs1_device_details) -{ - /* EMIF1 & EMIF2 have identical configuration */ - *cs0_device_details = dev_4G_S4_details; - *cs1_device_details = dev_4G_S4_details; -} - -void emif_get_device_details(u32 emif_nr, - struct lpddr2_device_details *cs0_device_details, - struct lpddr2_device_details *cs1_device_details) - __attribute__((weak, alias("emif_get_device_details_sdp"))); - -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - -const u32 ext_phy_ctrl_const_base[] = { - 0x01004010, - 0x00001004, - 0x04010040, - 0x01004010, - 0x00001004, - 0x00000000, - 0x00000000, - 0x00000000, - 0x80080080, - 0x00800800, - 0x08102040, - 0x00000001, - 0x540A8150, - 0xA81502a0, - 0x002A0540, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000077, - 0x0 -}; - -const u32 ddr3_ext_phy_ctrl_const_base_es1[] = { - 0x01004010, - 0x00001004, - 0x04010040, - 0x01004010, - 0x00001004, - 0x00000000, - 0x00000000, - 0x00000000, - 0x80080080, - 0x00800800, - 0x08102040, - 0x00000002, - 0x0, - 0x0, - 0x0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000057, - 0x0 -}; - -const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { - 0x50D4350D, - 0x00000D43, - 0x04010040, - 0x01004010, - 0x00001004, - 0x00000000, - 0x00000000, - 0x00000000, - 0x80080080, - 0x00800800, - 0x08102040, - 0x00000002, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000057, - 0x0 -}; - -/* Ext phy ctrl 1-35 regs */ -const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { - 0x10040100, - 0x00910091, - 0x00950095, - 0x009B009B, - 0x009E009E, - 0x00980098, - 0x00340034, - 0x00350035, - 0x00340034, - 0x00310031, - 0x00340034, - 0x007F007F, - 0x007F007F, - 0x007F007F, - 0x007F007F, - 0x007F007F, - 0x00480048, - 0x004A004A, - 0x00520052, - 0x00550055, - 0x00500050, - 0x00000000, - 0x00600020, - 0x40011080, - 0x08102040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -/* Ext phy ctrl 1-35 regs */ -const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { - 0x10040100, - 0x00910091, - 0x00950095, - 0x009B009B, - 0x009E009E, - 0x00980098, - 0x00330033, - 0x00330033, - 0x002F002F, - 0x00320032, - 0x00310031, - 0x007F007F, - 0x007F007F, - 0x007F007F, - 0x007F007F, - 0x007F007F, - 0x00520052, - 0x00520052, - 0x00470047, - 0x00490049, - 0x00500050, - 0x00000000, - 0x00600020, - 0x40011080, - 0x08102040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -/* Ext phy ctrl 1-35 regs */ -const u32 -dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { - 0x10040100, - 0x00A400A4, - 0x00A900A9, - 0x00B000B0, - 0x00B000B0, - 0x00A400A4, - 0x00390039, - 0x00320032, - 0x00320032, - 0x00320032, - 0x00440044, - 0x00550055, - 0x00550055, - 0x00550055, - 0x00550055, - 0x007F007F, - 0x004D004D, - 0x00430043, - 0x00560056, - 0x00540054, - 0x00600060, - 0x0, - 0x00600020, - 0x40010080, - 0x08102040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { - 0x04040100, - 0x006B009F, - 0x006B00A2, - 0x006B00A8, - 0x006B00A8, - 0x006B00B2, - 0x002F002F, - 0x002F002F, - 0x002F002F, - 0x002F002F, - 0x002F002F, - 0x00600073, - 0x00600071, - 0x0060007C, - 0x0060007E, - 0x00600084, - 0x00400053, - 0x00400051, - 0x0040005C, - 0x0040005E, - 0x00400064, - 0x00800080, - 0x00800080, - 0x40010080, - 0x08102040, - 0x005B008F, - 0x005B0092, - 0x005B0098, - 0x005B0098, - 0x005B00A2, - 0x00300043, - 0x00300041, - 0x0030004C, - 0x0030004E, - 0x00300054, - 0x00000077 -}; - -const struct lpddr2_mr_regs mr_regs = { - .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, - .mr2 = 0x6, - .mr3 = 0x1, - .mr10 = MR10_ZQ_ZQINIT, - .mr16 = MR16_REF_FULL_ARRAY -}; - -void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, - const u32 **regs, - u32 *size) -{ - switch (omap_revision()) { - case OMAP5430_ES1_0: - case OMAP5430_ES2_0: - *regs = ext_phy_ctrl_const_base; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base); - break; - case OMAP5432_ES1_0: - *regs = ddr3_ext_phy_ctrl_const_base_es1; - *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1); - break; - case OMAP5432_ES2_0: - *regs = ddr3_ext_phy_ctrl_const_base_es2; - *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); - break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - if (emif_nr == 1) { - *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; - *size = - ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1); - } else { - *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; - *size = - ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2); - } - break; - case DRA722_ES1_0: - *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; - *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); - break; - case DRA722_ES2_0: - *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; - *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); - break; - default: - *regs = ddr3_ext_phy_ctrl_const_base_es2; - *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); - - } -} - -void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) -{ - *regs = &mr_regs; -} - -static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs) -{ - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - u32 emif_nr; - const u32 *ext_phy_ctrl_const_regs; - u32 i = 0; - u32 size; - - emif_nr = (base == EMIF1_BASE) ? 1 : 2; - - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); - - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - - /* - * external phy 6-24 registers do not change with - * ddr frequency - */ - emif_get_ext_phy_ctrl_const_regs(emif_nr, - &ext_phy_ctrl_const_regs, &size); - - for (i = 0; i < size; i++) { - writel(ext_phy_ctrl_const_regs[i], - emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ext_phy_ctrl_const_regs[i], - emif_ext_phy_ctrl_base++); - } -} - -static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *emif_ext_phy_ctrl_base = 0; - u32 emif_nr; - const u32 *ext_phy_ctrl_const_regs; - u32 i, hw_leveling, size, phy; - - emif_nr = (base == EMIF1_BASE) ? 1 : 2; - - hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; - phy = regs->emif_ddr_phy_ctlr_1_init; - - emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); - - emif_get_ext_phy_ctrl_const_regs(emif_nr, - &ext_phy_ctrl_const_regs, &size); - - writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); - writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); - - /* - * Copy the predefined PHY register values - * if leveling is disabled. - */ - if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK) - for (i = 1; i < 6; i++) { - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2]); - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2 + 1]); - } - - if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK) - for (i = 6; i < 11; i++) { - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2]); - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2 + 1]); - } - - if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK) - for (i = 11; i < 25; i++) { - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2]); - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2 + 1]); - } - - if (hw_leveling) { - /* - * Write the init value for HW levling to occur - */ - for (i = 21; i < 35; i++) { - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2]); - writel(ext_phy_ctrl_const_regs[i], - &emif_ext_phy_ctrl_base[i * 2 + 1]); - } - } -} - -void do_ext_phy_settings(u32 base, const struct emif_regs *regs) -{ - if (is_omap54xx()) - do_ext_phy_settings_omap5(base, regs); - else - do_ext_phy_settings_dra7(base, regs); -} - -#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -static const struct lpddr2_ac_timings timings_jedec_532_mhz = { - .max_freq = 532000000, - .RL = 8, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 15, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - -static const struct lpddr2_min_tck min_tck = { - .tRL = 3, - .tRP_AB = 3, - .tRCD = 3, - .tWR = 3, - .tRAS_MIN = 3, - .tRRD = 2, - .tWTR = 2, - .tXP = 2, - .tRTP = 2, - .tCKE = 3, - .tCKESR = 3, - .tFAW = 8 -}; - -static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = { - &timings_jedec_532_mhz -}; - -static const struct lpddr2_device_timings dev_4G_S4_timings = { - .ac_timings = ac_timings, - .min_tck = &min_tck, -}; - -/* - * List of status registers to be controlled back to control registers - * after initial leveling - * readreg, writereg - */ -const struct read_write_regs omap5_bug_00339_regs[] = { - { 8, 5 }, - { 9, 6 }, - { 10, 7 }, - { 14, 8 }, - { 15, 9 }, - { 16, 10 }, - { 11, 2 }, - { 12, 3 }, - { 13, 4 }, - { 17, 11 }, - { 18, 12 }, - { 19, 13 }, -}; - -const struct read_write_regs dra_bug_00339_regs[] = { - { 7, 7 }, - { 8, 8 }, - { 9, 9 }, - { 10, 10 }, - { 11, 11 }, - { 12, 2 }, - { 13, 3 }, - { 14, 4 }, - { 15, 5 }, - { 16, 6 }, - { 17, 12 }, - { 18, 13 }, - { 19, 14 }, - { 20, 15 }, - { 21, 16 }, - { 22, 17 }, - { 23, 18 }, - { 24, 19 }, - { 25, 20 }, - { 26, 21} -}; - -const struct read_write_regs *get_bug_regs(u32 *iterations) -{ - const struct read_write_regs *bug_00339_regs_ptr = NULL; - - switch (omap_revision()) { - case OMAP5430_ES1_0: - case OMAP5430_ES2_0: - case OMAP5432_ES1_0: - case OMAP5432_ES2_0: - bug_00339_regs_ptr = omap5_bug_00339_regs; - *iterations = sizeof(omap5_bug_00339_regs)/ - sizeof(omap5_bug_00339_regs[0]); - break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - case DRA722_ES1_0: - case DRA722_ES2_0: - bug_00339_regs_ptr = dra_bug_00339_regs; - *iterations = sizeof(dra_bug_00339_regs)/ - sizeof(dra_bug_00339_regs[0]); - break; - default: - printf("\n Error: UnKnown SOC"); - } - - return bug_00339_regs_ptr; -} - -void emif_get_device_timings_sdp(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) -{ - /* Identical devices on EMIF1 & EMIF2 */ - *cs0_device_timings = &dev_4G_S4_timings; - *cs1_device_timings = &dev_4G_S4_timings; -} - -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings) - __attribute__((weak, alias("emif_get_device_timings_sdp"))); - -#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/cpu/armv7/omap5/sec-fxns.c b/arch/arm/cpu/armv7/omap5/sec-fxns.c deleted file mode 100644 index 33d4ea4eaca..00000000000 --- a/arch/arm/cpu/armv7/omap5/sec-fxns.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * - * Security related functions for OMAP5 class devices - * - * (C) Copyright 2016 - * Texas Instruments, - * - * Daniel Allred - * Harinarayan Bhatta - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include -#include -#include -#include -#include - -/* Index for signature PPA-based TI HAL APIs */ -#define PPA_HAL_SERVICES_START_INDEX (0x200) -#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25) -#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26) -#define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27) - -static u32 get_sec_mem_start(void) -{ - u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START; - u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE; - /* - * Total reserved region is all contiguous with protected - * region coming first, followed by the non-secure region. - * If 0x0 start address is given, we simply put the reserved - * region at the end of the external DRAM. - */ - if (sec_mem_start == 0) - sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + - (omap_sdram_size() - sec_mem_size)); - return sec_mem_start; -} - -int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr, - uint32_t size, uint32_t access_perm, - uint32_t initiator_perm) -{ - int result = 1; - - /* - * Call PPA HAL API to do any other general firewall - * configuration for regions 1-6 of the EMIF firewall. - */ - debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__, - region_num, start_addr, size); - - result = secure_rom_call( - PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4, - (start_addr & 0xFFFFFFF0) | (region_num & 0x0F), - size, access_perm, initiator_perm); - - if (result != 0) { - puts("Secure EMIF Firewall Setup failed!\n"); - debug("Return Value = %x\n", result); - } - - return result; -} - -#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE < \ - CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE) -#error "TI Secure EMIF: Protected size cannot be larger than total size." -#endif -int secure_emif_reserve(void) -{ - int result = 1; - u32 sec_mem_start = get_sec_mem_start(); - u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE; - - /* If there is no protected region, there is no reservation to make */ - if (sec_prot_size == 0) - return 0; - - /* - * Call PPA HAL API to reserve a chunk of EMIF SDRAM - * for secure world use. This region should be carved out - * from use by any public code. EMIF firewall region 7 - * will be used to protect this block of memory. - */ - result = secure_rom_call( - PPA_SERV_HAL_SETUP_SEC_RESVD_REGION, - 0, 0, 2, sec_mem_start, sec_prot_size); - - if (result != 0) { - puts("SDRAM Firewall: Secure memory reservation failed!\n"); - debug("Return Value = %x\n", result); - } - - return result; -} - -int secure_emif_firewall_lock(void) -{ - int result = 1; - - /* - * Call PPA HAL API to lock the EMIF firewall configurations. - * After this API is called, none of the PPA HAL APIs for - * configuring the EMIF firewalls will be usable again (that - * is, calls to those APIs will return failure and have no - * effect). - */ - - result = secure_rom_call( - PPA_SERV_HAL_LOCK_EMIF_FW, - 0, 0, 0); - - if (result != 0) { - puts("Secure EMIF Firewall Lock failed!\n"); - debug("Return Value = %x\n", result); - } - - return result; -} diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig new file mode 100644 index 00000000000..24bc4851958 --- /dev/null +++ b/arch/arm/mach-omap2/Kconfig @@ -0,0 +1,17 @@ +config TI_SECURE_DEVICE + bool "HS Device Type Support" + depends on OMAP54XX || AM43XX || AM33XX + help + If a high secure (HS) device type is being used, this config + must be set. This option impacts various aspects of the + build system (to create signed boot images that can be + authenticated) and the code. See the doc/README.ti-secure + file for further details. + +source "arch/arm/mach-omap2/omap3/Kconfig" + +source "arch/arm/mach-omap2/omap4/Kconfig" + +source "arch/arm/mach-omap2/omap5/Kconfig" + +source "arch/arm/mach-omap2/am33xx/Kconfig" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile new file mode 100644 index 00000000000..e814eb008e4 --- /dev/null +++ b/arch/arm/mach-omap2/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ +obj-$(CONFIG_OMAP34XX) += omap3/ +obj-$(CONFIG_OMAP44XX) += omap4/ +obj-$(CONFIG_OMAP54XX) += omap5/ + +obj-y += reset.o +ifeq ($(CONFIG_TIMER),) +obj-y += timer.o +else +ifdef CONFIG_SPL_BUILD +obj-y += timer.o +endif +endif +obj-y += utils.o + +ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +obj-y += hwinit-common.o +obj-y += clocks-common.o +obj-y += emif-common.o +obj-y += vc.o +obj-y += abb.o +endif + +ifneq ($(CONFIG_OMAP54XX),) +obj-y += pipe3-phy.o +obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o +endif + +ifeq ($(CONFIG_SYS_DCACHE_OFF),) +obj-y += omap-cache.o +endif + +obj-y += boot-common.o +obj-y += lowlevel_init.o + +obj-y += mem-common.o + +obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o diff --git a/arch/arm/mach-omap2/abb.c b/arch/arm/mach-omap2/abb.c new file mode 100644 index 00000000000..a0add6643e1 --- /dev/null +++ b/arch/arm/mach-omap2/abb.c @@ -0,0 +1,121 @@ +/* + * Adaptive Body Bias programming sequence for OMAP family + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Andrii Tseglytskyi + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) +{ + return -1; +} + +static void abb_setup_timings(u32 setup) +{ + u32 sys_rate, sr2_cnt, clk_cycles; + + /* + * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a + * transition and must be programmed with the correct time at boot. + * The value programmed into the register is the number of SYS_CLK + * clock cycles that match a given wall time profiled for the ldo. + * This value depends on: + * settling time of ldo in micro-seconds (varies per OMAP family), + * of clock cycles per SYS_CLK period (varies per OMAP family), + * the SYS_CLK frequency in MHz (varies per board) + * The formula is: + * + * ldo settling time (in micro-seconds) + * SR2_WTCNT_VALUE = ------------------------------------------ + * (# system clock cycles) * (sys_clk period) + * + * Put another way: + * + * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate)) + * + * To avoid dividing by zero multiply both "# clock cycles" and + * "settling time" by 10 such that the final result is the one we want. + */ + + /* calculate SR2_WTCNT_VALUE */ + sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000); + clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); + sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); + + setbits_le32(setup, + sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); +} + +void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, + u32 txdone, u32 txdone_mask, u32 opp) +{ + u32 abb_type_mask, opp_sel_mask; + + /* sanity check */ + if (!setup || !control || !txdone) + return; + + /* setup ABB only in case of Fast or Slow OPP */ + switch (opp) { + case OMAP_ABB_FAST_OPP: + abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK; + opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK; + break; + case OMAP_ABB_SLOW_OPP: + abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK; + opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK; + break; + default: + return; + } + + /* + * For some OMAP silicons additional setup for LDOVBB register is + * required. This is determined by data retrieved from corresponding + * OPP EFUSE register. Data, which is retrieved from EFUSE - is + * ABB enable/disable flag and VSET value, which must be copied + * to LDOVBB register. If function call fails - return quietly, + * it means no ABB is required for such silicon. + * + * For silicons, which don't require LDOVBB setup "fuse" and + * "ldovbb" offsets are not defined. ABB will be initialized in + * the common way for them. + */ + if (fuse && ldovbb) { + if (abb_setup_ldovbb(fuse, ldovbb)) + return; + } + + /* clear ABB registers */ + writel(0, setup); + writel(0, control); + + /* configure timings, based on oscillator value */ + abb_setup_timings(setup); + + /* clear pending interrupts before setup */ + setbits_le32(txdone, txdone_mask); + + /* select ABB type */ + setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); + + /* initiate ABB ldo change */ + setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); + + /* wait until transition complete */ + if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY)) + puts("Error: ABB txdone is not set\n"); + + /* clear ABB tranxdone */ + setbits_le32(txdone, txdone_mask); +} diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig new file mode 100644 index 00000000000..8fd32c2a46d --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -0,0 +1,137 @@ +if AM33XX + +choice + prompt "AM33xx board select" + optional + +config TARGET_AM335X_EVM + bool "Support am335x_evm" + select DM + select DM_SERIAL + select DM_GPIO + select TI_I2C_BOARD_DETECT + help + This option specifies support for the AM335x + GP and HS EVM development platforms. The AM335x + GP EVM is a standalone test, development, and + evaluation module system that enables developers + to write software and develop hardware around + an AM335x processor subsystem. + +config TARGET_AM335X_BALTOS + bool "Support am335x_baltos" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_AM335X_IGEP0033 + bool "Support am335x_igep0033" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_AM335X_SHC + bool "Support am335x based shc board from bosch" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_AM335X_SL50 + bool "Support am335x_sl50" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_BAV335X + bool "Support bav335x" + select DM + select DM_SERIAL + help + The BAV335x OEM Network Processor integrates all the functions of an + embedded network computer in a small, easy to use SODIMM module which + incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8 + processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit + ethernet with simple connection to external connectors. + + For more information, visit: http://birdland.com/oem + +config TARGET_CM_T335 + bool "Support cm_t335" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_PCM051 + bool "Support pcm051" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_PENGWYN + bool "Support pengwyn" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_PEPPER + bool "Support pepper" + select DM + select DM_SERIAL + select DM_GPIO + +endchoice + +endif + +if AM43XX + +config SPL_EXT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config TARGET_AM43XX_EVM + bool "Support am43xx_evm" + select TI_I2C_BOARD_DETECT + help + This option specifies support for the AM43xx + GP and HS EVM development platforms.The AM437x + GP EVM is a standalone test, development, and + evaluation module system that enables developers + to write software and develop hardware around + an AM43xx processor subsystem. +endif + +if AM43XX || AM33XX +config ISW_ENTRY_ADDR + hex "Address in memory or XIP flash of bootloader entry point" + help + After any reset, the boot ROM on the AM43XX SOC + searches the boot media for a valid boot image. + For non-XIP devices, the ROM then copies the + image into internal memory. + For all boot modes, after the ROM processes the + boot image it eventually computes the entry + point address depending on the device type + (secure/non-secure), boot media (xip/non-xip) and + image headers. + default 0x402F4000 + +config PUB_ROM_DATA_SIZE + hex "Size in bytes of the L3 SRAM reserved by ROM to store data" + help + During the device boot, the public ROM uses the top of + the public L3 OCMC RAM to store r/w data like stack, + heap, globals etc. When the ROM is copying the boot + image from the boot media into memory, the image must + not spill over into this area. This value can be used + during compile time to determine the maximum size of a + boot image. Once the ROM transfers control to the boot + image, this area is no longer used, and can be reclaimed + for run time use by the boot image. + default 0x8400 +endif diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile new file mode 100644 index 00000000000..6fda4825fce --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -0,0 +1,22 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_AM33XX) += clock_am33xx.o +obj-$(CONFIG_TI814X) += clock_ti814x.o +obj-$(CONFIG_AM43XX) += clock_am43xx.o + +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) +obj-y += clock.o +endif + +obj-$(CONFIG_TI816X) += clock_ti816x.o +obj-y += sys_info.o +obj-y += ddr.o +obj-y += emif4.o +obj-y += board.o +obj-y += mux.o + +obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c new file mode 100644 index 00000000000..5ebeac0ee1e --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -0,0 +1,317 @@ +/* + * board.c + * + * Common board functions for AM33XX based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct ns16550_platdata am33xx_serial[] = { + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, +# ifdef CONFIG_SYS_NS16550_COM2 + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, +# ifdef CONFIG_SYS_NS16550_COM3 + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, +# endif +# endif +}; + +U_BOOT_DEVICES(am33xx_uarts) = { + { "ns16550_serial", &am33xx_serial[0] }, +# ifdef CONFIG_SYS_NS16550_COM2 + { "ns16550_serial", &am33xx_serial[1] }, +# ifdef CONFIG_SYS_NS16550_COM3 + { "ns16550_serial", &am33xx_serial[2] }, + { "ns16550_serial", &am33xx_serial[3] }, + { "ns16550_serial", &am33xx_serial[4] }, + { "ns16550_serial", &am33xx_serial[5] }, +# endif +# endif +}; + +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata am33xx_gpio[] = { + { 0, AM33XX_GPIO0_BASE }, + { 1, AM33XX_GPIO1_BASE }, + { 2, AM33XX_GPIO2_BASE }, + { 3, AM33XX_GPIO3_BASE }, +#ifdef CONFIG_AM43XX + { 4, AM33XX_GPIO4_BASE }, + { 5, AM33XX_GPIO5_BASE }, +#endif +}; + +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &am33xx_gpio[0] }, + { "gpio_omap", &am33xx_gpio[1] }, + { "gpio_omap", &am33xx_gpio[2] }, + { "gpio_omap", &am33xx_gpio[3] }, +#ifdef CONFIG_AM43XX + { "gpio_omap", &am33xx_gpio[4] }, + { "gpio_omap", &am33xx_gpio[5] }, +#endif +}; +#endif +#endif + +#ifndef CONFIG_DM_GPIO +static const struct gpio_bank gpio_bank_am33xx[] = { + { (void *)AM33XX_GPIO0_BASE }, + { (void *)AM33XX_GPIO1_BASE }, + { (void *)AM33XX_GPIO2_BASE }, + { (void *)AM33XX_GPIO3_BASE }, +#ifdef CONFIG_AM43XX + { (void *)AM33XX_GPIO4_BASE }, + { (void *)AM33XX_GPIO5_BASE }, +#endif +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; +#endif + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int cpu_mmc_init(bd_t *bis) +{ + int ret; + + ret = omap_mmc_init(0, 0, 0, -1, -1); + if (ret) + return ret; + + return omap_mmc_init(1, 0, 0, -1, -1); +} +#endif + +/* AM33XX has two MUSB controllers which can be host or gadget */ +#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ + (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* USB 2.0 PHY Control */ +#define CM_PHY_PWRDN (1 << 0) +#define CM_PHY_OTG_PWRDN (1 << 1) +#define OTGVDET_EN (1 << 19) +#define OTGSESSENDEN (1 << 20) + +static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) +{ + if (on) { + clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, + OTGVDET_EN | OTGSESSENDEN); + } else { + clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); + } +} + +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +#ifdef CONFIG_AM335X_USB0 +static void am33xx_otg0_set_phy_power(u8 on) +{ + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); +} + +struct omap_musb_board_data otg0_board_data = { + .set_phy_power = am33xx_otg0_set_phy_power, +}; + +static struct musb_hdrc_platform_data otg0_plat = { + .mode = CONFIG_AM335X_USB0_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg0_board_data, +}; +#endif + +#ifdef CONFIG_AM335X_USB1 +static void am33xx_otg1_set_phy_power(u8 on) +{ + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); +} + +struct omap_musb_board_data otg1_board_data = { + .set_phy_power = am33xx_otg1_set_phy_power, +}; + +static struct musb_hdrc_platform_data otg1_plat = { + .mode = CONFIG_AM335X_USB1_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg1_board_data, +}; +#endif +#endif + +int arch_misc_init(void) +{ +#ifdef CONFIG_AM335X_USB0 + musb_register(&otg0_plat, &otg0_board_data, + (void *)USB0_OTG_BASE); +#endif +#ifdef CONFIG_AM335X_USB1 + musb_register(&otg1_plat, &otg1_board_data, + (void *)USB1_OTG_BASE); +#endif + return 0; +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +/* + * In the case of non-SPL based booting we'll want to call these + * functions a tiny bit later as it will require gd to be set and cleared + * and that's not true in s_init in this case so we cannot do it there. + */ +int board_early_init_f(void) +{ + prcm_init(); + set_mux_conf_regs(); + + return 0; +} + +/* + * This function is the place to do per-board things such as ramp up the + * MPU clock frequency. + */ +__weak void am33xx_spl_board_init(void) +{ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) +static void rtc32k_enable(void) +{ + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(RTC_KICK0R_WE, &rtc->kick0r); + writel(RTC_KICK1R_WE, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); +} +#endif + +static void uart_soft_reset(void) +{ + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + u32 regval; + + regval = readl(&uart_base->uartsyscfg); + regval |= UART_RESET; + writel(regval, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regval = readl(&uart_base->uartsyscfg); + regval |= UART_SMART_IDLE_EN; + writel(regval, &uart_base->uartsyscfg); +} + +static void watchdog_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} + +void s_init(void) +{ +} + +void early_system_init(void) +{ + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + enable_norboot_pin_mux(); +#endif + watchdog_disable(); + set_uart_mux_conf(); + setup_early_clocks(); + uart_soft_reset(); +#ifdef CONFIG_TI_I2C_BOARD_DETECT + do_board_detect(); +#endif +#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) + /* Enable RTC32K clock */ + rtc32k_enable(); +#endif +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + early_system_init(); + board_early_init_f(); + sdram_init(); +} +#endif + +#endif + +int arch_cpu_init_dm(void) +{ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + early_system_init(); +#endif + return 0; +} diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c new file mode 100644 index 00000000000..316e677c65c --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c @@ -0,0 +1,104 @@ +/* + * clk-synthesizer.c + * + * Clock synthesizer apis + * + * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include +#include +#include + +/** + * clk_synthesizer_reg_read - Read register from synthesizer. + * @addr: addr within the i2c device + * buf: Buffer to which value is to be read. + * + * For reading the register from this clock synthesizer, a command needs to + * be send along with enabling byte read more, and then read can happen. + * Returns 0 on success + */ +static int clk_synthesizer_reg_read(int addr, uint8_t *buf) +{ + int rc; + + /* Enable Bye read */ + addr = addr | CLK_SYNTHESIZER_BYTE_MODE; + + /* Send the command byte */ + rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); + if (rc) + printf("Failed to send command to clock synthesizer\n"); + + /* Read the Data */ + return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); +} + +/** + * clk_synthesizer_reg_write - Write a value to register in synthesizer. + * @addr: addr within the i2c device + * val: Value to be written in the addr. + * + * Enable the byte read mode in the address and start the i2c transfer. + * Returns 0 on success + */ +static int clk_synthesizer_reg_write(int addr, uint8_t val) +{ + uint8_t cmd[2]; + int rc = 0; + + /* Enable byte write */ + cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE; + cmd[1] = val; + + rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2); + if (rc) + printf("Clock synthesizer reg write failed at addr = 0x%x\n", + addr); + return rc; +} + +/** + * setup_clock_syntherizer - Program the clock synthesizer to get the desired + * frequency. + * @data: Data containing the desired output + * + * This is a PLL-based high performance synthesizer which gives 3 outputs + * as per the PLL_DIV and load capacitor programmed. + */ +int setup_clock_synthesizer(struct clk_synth *data) +{ + int rc; + uint8_t val; + + rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR); + if (rc) { + printf("i2c probe failed at address 0x%x\n", + CLK_SYNTHESIZER_I2C_ADDR); + return rc; + } + + rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val); + if (val != data->id) + return rc; + + /* Crystal Load capacitor selection */ + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor); + if (rc) + return rc; + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux); + if (rc) + return rc; + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2); + if (rc) + return rc; + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3); + if (rc) + return rc; + + return 0; +} diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c new file mode 100644 index 00000000000..3d17698e186 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -0,0 +1,246 @@ +/* + * clock.c + * + * Clock initialization for AM33XX boards. + * Derived from OMAP4 boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static void setup_post_dividers(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, dpll_regs->cm_div_m6_dpll); +} + +static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for 0x%x\n", + dpll_regs->cm_clkmode_dpll); + hang(); + } +} + +static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("Bypassing DPLL failed 0x%x\n", + dpll_regs->cm_clkmode_dpll); + } +} + +static void bypass_dpll(const struct dpll_regs *dpll_regs) +{ + do_bypass_dpll(dpll_regs); + wait_for_bypass(dpll_regs); +} + +void do_setup_dpll(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + u32 temp; + + if (!params) + return; + + temp = readl(dpll_regs->cm_clksel_dpll); + + bypass_dpll(dpll_regs); + + /* Set M & N */ + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, dpll_regs->cm_clksel_dpll); + + setup_post_dividers(dpll_regs, params); + + /* Wait till the DPLL locks */ + do_lock_dpll(dpll_regs); + wait_for_lock(dpll_regs); +} + +static void setup_dplls(void) +{ + const struct dpll_params *params; + + params = get_dpll_core_params(); + do_setup_dpll(&dpll_core_regs, params); + + params = get_dpll_mpu_params(); + do_setup_dpll(&dpll_mpu_regs, params); + + params = get_dpll_per_params(); + do_setup_dpll(&dpll_per_regs, params); + writel(0x300, &cmwkup->clkdcoldodpllper); + + params = get_dpll_ddr_params(); + do_setup_dpll(&dpll_ddr_regs, params); +} + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - %p\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +static inline void wait_for_clk_disable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; + u32 bound = LDELAY; + + while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) { + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock disable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} +static inline void disable_clock_module(u32 *const clkctrl_addr, + u32 wait_for_disable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Disable clock module - %p\n", clkctrl_addr); + if (wait_for_disable) + wait_for_clk_disable(clkctrl_addr); +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - %p\n", clkctrl_reg); +} + +static inline void disable_clock_domain(u32 *const clkctrl_reg) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Disable clock domain - %p\n", clkctrl_reg); +} + +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_explicit_en, u8 wait_for_enable) +{ + u32 i, max = 100; + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { + enable_clock_module(clk_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; +} + +void do_disable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_disable, + u8 wait_for_disable) +{ + u32 i, max = 100; + + + /* Clock modules that need to be put in SW_DISABLE */ + for (i = 0; (i < max) && clk_modules_disable[i]; i++) + disable_clock_module(clk_modules_disable[i], + wait_for_disable); + + /* Put the clock domains in SW_SLEEP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) + disable_clock_domain(clk_domains[i]); +} + +/* + * Before scaling up the clocks we need to have the PMIC scale up the + * voltages first. This will be dependent on which PMIC is in use + * and in some cases we may not be scaling things up at all and thus not + * need to do anything here. + */ +__weak void scale_vcores(void) +{ +} + +void setup_early_clocks(void) +{ + setup_clocks_for_console(); + enable_basic_clocks(); + timer_init(); +} + +void prcm_init(void) +{ + scale_vcores(); + setup_dplls(); +} diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c new file mode 100644 index 00000000000..7b841b2d556 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -0,0 +1,234 @@ +/* + * clock_am33xx.c + * + * clocks for AM33XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define OSC (V_OSCK/1000000) + +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; +struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC; + +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x88, + .cm_idlest_dpll = CM_WKUP + 0x20, + .cm_clksel_dpll = CM_WKUP + 0x2C, + .cm_div_m2_dpll = CM_WKUP + 0xA8, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x90, + .cm_idlest_dpll = CM_WKUP + 0x5C, + .cm_clksel_dpll = CM_WKUP + 0x68, + .cm_div_m4_dpll = CM_WKUP + 0x80, + .cm_div_m5_dpll = CM_WKUP + 0x84, + .cm_div_m6_dpll = CM_WKUP + 0xD8, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x8C, + .cm_idlest_dpll = CM_WKUP + 0x70, + .cm_clksel_dpll = CM_WKUP + 0x9C, + .cm_div_m2_dpll = CM_WKUP + 0xAC, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x94, + .cm_idlest_dpll = CM_WKUP + 0x34, + .cm_clksel_dpll = CM_WKUP + 0x40, + .cm_div_m2_dpll = CM_WKUP + 0xA0, +}; + +struct dpll_params dpll_mpu_opp100 = { + CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core_opp100 = { + 1000, OSC-1, -1, -1, 10, 8, 4}; +const struct dpll_params dpll_mpu = { + MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + 50, OSC-1, -1, -1, 1, 1, 1}; +const struct dpll_params dpll_per = { + 960, OSC-1, 5, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + +void setup_clocks_for_console(void) +{ + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart1clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart2clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart3clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart4clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart5clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + +void enable_basic_clocks(void) +{ + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l4fwclkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emiffwclkctrl, + &cmrtc->clkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, + &cmper->spi0clkctrl, + &cmrtc->rtcclkctrl, + &cmper->usb0clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + /* Select the Master osc 24 MHZ as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); +} + +/* + * Enable Spread Spectrum for the MPU by calculating the required + * values and setting the registers accordingly. + * @param permille The spreading in permille (10th of a percent) + */ +void set_mpu_spreadspectrum(int permille) +{ + u32 multiplier_m; + u32 predivider_n; + u32 cm_clksel_dpll_mpu; + u32 cm_clkmode_dpll_mpu; + u32 ref_clock; + u32 pll_bandwidth; + u32 mod_freq_divider; + u32 exponent; + u32 mantissa; + u32 delta_m_step; + + printf("Enabling Spread Spectrum of %d permille for MPU\n", + permille); + + /* Read PLL parameter m and n */ + cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu); + multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF; + predivider_n = cm_clksel_dpll_mpu & 0x7F; + + /* + * Calculate reference clock (clock after pre-divider), + * its max. PLL bandwidth, + * and resulting mod_freq_divider + */ + ref_clock = V_OSCK / (predivider_n + 1); + pll_bandwidth = ref_clock / 70; + mod_freq_divider = ref_clock / (4 * pll_bandwidth); + + /* Calculate Mantissa/Exponent */ + exponent = 0; + mantissa = mod_freq_divider; + while ((mantissa > 127) && (exponent < 7)) { + exponent++; + mantissa /= 2; + } + if (mantissa > 127) + mantissa = 127; + + mod_freq_divider = mantissa << exponent; + + /* + * Calculate Modulation steps + * As we use Downspread only, the spread is twice the value of + * permille, so Div2! + * As it takes the value in percent, divide by ten! + */ + delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18; + delta_m_step /= 100; + delta_m_step /= mod_freq_divider; + if (delta_m_step > 0xFFFFF) + delta_m_step = 0xFFFFF; + + /* Setup Spread Spectrum */ + writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu); + writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu); + cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu); + /* clear all SSC flags */ + cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT); + /* enable SSC with Downspread only */ + cm_clkmode_dpll_mpu |= CM_CLKMODE_DPLL_SSC_EN_MASK | + CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK; + writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu); + while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000)) + ; +} diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c new file mode 100644 index 00000000000..73ea955a6cf --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c @@ -0,0 +1,231 @@ +/* + * clock_am43xx.c + * + * clocks for AM43XX based boards + * Derived from AM33XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; + +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x560, + .cm_idlest_dpll = CM_WKUP + 0x564, + .cm_clksel_dpll = CM_WKUP + 0x56c, + .cm_div_m2_dpll = CM_WKUP + 0x570, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x520, + .cm_idlest_dpll = CM_WKUP + 0x524, + .cm_clksel_dpll = CM_WKUP + 0x52C, + .cm_div_m4_dpll = CM_WKUP + 0x538, + .cm_div_m5_dpll = CM_WKUP + 0x53C, + .cm_div_m6_dpll = CM_WKUP + 0x540, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5E0, + .cm_idlest_dpll = CM_WKUP + 0x5E4, + .cm_clksel_dpll = CM_WKUP + 0x5EC, + .cm_div_m2_dpll = CM_WKUP + 0x5F0, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5A0, + .cm_idlest_dpll = CM_WKUP + 0x5A4, + .cm_clksel_dpll = CM_WKUP + 0x5AC, + .cm_div_m2_dpll = CM_WKUP + 0x5B0, + .cm_div_m4_dpll = CM_WKUP + 0x5B8, +}; + +void setup_clocks_for_console(void) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable UART0 */ + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(&cmwkup->wkup_uart0ctrl); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + } +} + +void enable_basic_clocks(void) +{ + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emifclkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->gpio4clkctrl, + &cmper->gpio5clkctrl, + &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + &cmper->otfaemifclkctrl, + &cmper->qspiclkctrl, + &cmper->spi0clkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + /* Select the Master osc clk as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); + + /* For OPP100 the mac clock should be /5. */ + writel(0x4, &cmdpll->clkselmacclk); +} + +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks(void) +{ + u32 *const clk_domains_edma3[] = { + 0 + }; + + u32 *const clk_modules_explicit_en_edma3[] = { + &cmper->tpccclkctrl, + &cmper->tptc0clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_edma3, + clk_modules_explicit_en_edma3, + 1); +} + +void disable_edma3_clocks(void) +{ + u32 *const clk_domains_edma3[] = { + 0 + }; + + u32 *const clk_modules_disable_edma3[] = { + &cmper->tpccclkctrl, + &cmper->tptc0clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_edma3, + clk_modules_disable_edma3, + 1); +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) +void enable_usb_clocks(int index) +{ + u32 *usbclkctrl = 0; + u32 *usbphyocp2scpclkctrl = 0; + + if (index == 0) { + usbclkctrl = &cmper->usb0clkctrl; + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl; + setbits_le32(&cmper->usb0clkctrl, + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); + setbits_le32(&cmwkup->usbphy0clkctrl, + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + usbclkctrl = &cmper->usb1clkctrl; + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl; + setbits_le32(&cmper->usb1clkctrl, + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); + setbits_le32(&cmwkup->usbphy1clkctrl, + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); + } + + u32 *const clk_domains_usb[] = { + 0 + }; + + u32 *const clk_modules_explicit_en_usb[] = { + usbclkctrl, + usbphyocp2scpclkctrl, + 0 + }; + + do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1); +} + +void disable_usb_clocks(int index) +{ + u32 *usbclkctrl = 0; + u32 *usbphyocp2scpclkctrl = 0; + + if (index == 0) { + usbclkctrl = &cmper->usb0clkctrl; + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl; + clrbits_le32(&cmper->usb0clkctrl, + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); + clrbits_le32(&cmwkup->usbphy0clkctrl, + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + usbclkctrl = &cmper->usb1clkctrl; + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl; + clrbits_le32(&cmper->usb1clkctrl, + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); + clrbits_le32(&cmwkup->usbphy1clkctrl, + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); + } + + u32 *const clk_domains_usb[] = { + 0 + }; + + u32 *const clk_modules_disable_usb[] = { + usbclkctrl, + usbphyocp2scpclkctrl, + 0 + }; + + do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1); +} +#endif diff --git a/arch/arm/mach-omap2/am33xx/clock_ti814x.c b/arch/arm/mach-omap2/am33xx/clock_ti814x.c new file mode 100644 index 00000000000..50bd631cf6b --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/clock_ti814x.c @@ -0,0 +1,410 @@ +/* + * clock_ti814x.c + * + * Clocks for TI814X based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* PRCM */ +#define PRCM_MOD_EN 0x2 + +/* CLK_SRC */ +#define OSC_SRC0 0 +#define OSC_SRC1 1 + +#define L3_OSC_SRC OSC_SRC0 + +#define OSC_0_FREQ 20 + +#define DCO_HS2_MIN 500 +#define DCO_HS2_MAX 1000 +#define DCO_HS1_MIN 1000 +#define DCO_HS1_MAX 2000 + +#define SELFREQDCO_HS2 0x00000801 +#define SELFREQDCO_HS1 0x00001001 + +#define MPU_N 0x1 +#define MPU_M 0x3C +#define MPU_M2 1 +#define MPU_CLKCTRL 0x1 + +#define L3_N 19 +#define L3_M 880 +#define L3_M2 4 +#define L3_CLKCTRL 0x801 + +#define DDR_N 19 +#define DDR_M 666 +#define DDR_M2 2 +#define DDR_CLKCTRL 0x801 + +/* ADPLLJ register values */ +#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ +#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ +#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) +#define ADPLLJ_CLKCTRL_IDLE (1 << 23) +#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) +#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) +#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) +#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) +#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) +#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) +#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) +#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ + ADPLLJ_CLKCTRL_CLKOUTEN | \ + ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ + ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) + +#define ADPLLJ_STATUS_PHASELOCK (1 << 10) +#define ADPLLJ_STATUS_FREQLOCK (1 << 9) +#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ + ADPLLJ_STATUS_FREQLOCK) +#define ADPLLJ_STATUS_BYPASSACK (1 << 8) +#define ADPLLJ_STATUS_BYPASS (1 << 0) +#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ + ADPLLJ_STATUS_BYPASS) + +#define ADPLLJ_TENABLE_ENB (1 << 0) +#define ADPLLJ_TENABLEDIV_ENB (1 << 0) + +#define ADPLLJ_M2NDIV_M2SHIFT 16 + +#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) +#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) +#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) + +struct ad_pll { + unsigned int pwrctrl; + unsigned int clkctrl; + unsigned int tenable; + unsigned int tenablediv; + unsigned int m2ndiv; + unsigned int mn2div; + unsigned int fracdiv; + unsigned int bwctrl; + unsigned int fracctrl; + unsigned int status; + unsigned int m3div; + unsigned int rampctrl; +}; + +#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) + +#define ENET_CLKCTRL_CMPL 0x30000 + +#define SATA_PLL_BASE (CTRL_BASE + 0x0720) + +struct sata_pll { + unsigned int pllcfg0; + unsigned int pllcfg1; + unsigned int pllcfg2; + unsigned int pllcfg3; + unsigned int pllcfg4; + unsigned int pllstatus; + unsigned int rxstatus; + unsigned int txstatus; + unsigned int testcfg; +}; + +#define SEL_IN_FREQ (0x1 << 31) +#define DIGCLRZ (0x1 << 30) +#define ENDIGLDO (0x1 << 4) +#define APLL_CP_CURR (0x1 << 3) +#define ENBGSC_REF (0x1 << 2) +#define ENPLLLDO (0x1 << 1) +#define ENPLL (0x1 << 0) + +#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) +#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) +#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) +#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ + ENPLLLDO | ENPLL) + +#define PLL_LOCK (0x1 << 0) + +#define ENSATAMODE (0x1 << 31) +#define PLLREFSEL (0x1 << 30) +#define MDIVINT (0x4b << 18) +#define EN_CLKAUX (0x1 << 5) +#define EN_CLK125M (0x1 << 4) +#define EN_CLK100M (0x1 << 3) +#define EN_CLK50M (0x1 << 2) + +#define SATA_PLLCFG1 (ENSATAMODE | \ + PLLREFSEL | \ + MDIVINT | \ + EN_CLKAUX | \ + EN_CLK125M | \ + EN_CLK100M | \ + EN_CLK50M) + +#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) +#define PLLDO_EN_LDO_STABLE (0x1 << 11) +#define PLLDO_EN_BUF_CUR (0x1 << 7) +#define PLLDO_EN_LP (0x1 << 6) +#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) + +#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ + PLLDO_EN_LDO_STABLE | \ + PLLDO_EN_BUF_CUR | \ + PLLDO_EN_LP | \ + PLLDO_CTRL_TRIM_1_4V) + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; + +/* + * Enable the peripheral clock for required peripherals + */ +static void enable_per_clocks(void) +{ + /* HSMMC1 */ + writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); + while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) + ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) + ; + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) + ; + + /* RTC clocks */ + writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); + while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) + ; +} + +/* + * select the HS1 or HS2 for DCO Freq + * return : CLKCTRL + */ +static u32 pll_dco_freq_sel(u32 clkout_dco) +{ + if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) + return SELFREQDCO_HS2; + else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) + return SELFREQDCO_HS1; + else + return -1; +} + +/* + * select the sigma delta config + * return: sigma delta val + */ +static u32 pll_sigma_delta_val(u32 clkout_dco) +{ + u32 sig_val = 0; + + sig_val = (clkout_dco + 225) / 250; + sig_val = sig_val << 24; + + return sig_val; +} + +/* + * configure individual ADPLLJ + */ +static void pll_config(u32 base, u32 n, u32 m, u32 m2, + u32 clkctrl_val, int adpllj) +{ + const struct ad_pll *adpll = (struct ad_pll *)base; + u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; + u32 sig_val = 0, hs_mod = 0; + + m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; + mn2val = m; + + /* calculate clkout_dco */ + clkout_dco = ((OSC_0_FREQ / (n+1)) * m); + + /* sigma delta & Hs mode selection skip for ADPLLS*/ + if (adpllj) { + sig_val = pll_sigma_delta_val(clkout_dco); + hs_mod = pll_dco_freq_sel(clkout_dco); + } + + /* by-pass pll */ + read_clkctrl = readl(&adpll->clkctrl); + writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); + while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) + != ADPLLJ_STATUS_BYPASSANDACK) + ; + + /* clear TINITZ */ + read_clkctrl = readl(&adpll->clkctrl); + writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); + + /* + * ref_clk = 20/(n + 1); + * clkout_dco = ref_clk * m; + * clk_out = clkout_dco/m2; + */ + read_clkctrl = readl(&adpll->clkctrl) & + ~(ADPLLJ_CLKCTRL_LPMODE | + ADPLLJ_CLKCTRL_DRIFTGUARDIAN | + ADPLLJ_CLKCTRL_REGM4XEN); + writel(m2nval, &adpll->m2ndiv); + writel(mn2val, &adpll->mn2div); + + /* Skip for modena(ADPLLS) */ + if (adpllj) { + writel(sig_val, &adpll->fracdiv); + writel((read_clkctrl | hs_mod), &adpll->clkctrl); + } + + /* Load M2, N2 dividers of ADPLL */ + writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); + writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); + + /* Load M, N dividers of ADPLL */ + writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); + writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); + + /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ + read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; + if (adpllj) + writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), + &adpll->clkctrl); + + /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ + read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; + writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); + + /* Wait for phase and freq lock */ + while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != + ADPLLJ_STATUS_PHSFRQLOCK) + ; +} + +static void unlock_pll_control_mmr(void) +{ + /* TRM 2.10.1.4 and 3.2.7-3.2.11 */ + writel(0x1EDA4C3D, 0x481C5040); + writel(0x2FF1AC2B, 0x48140060); + writel(0xF757FDC0, 0x48140064); + writel(0xE2BC3A6D, 0x48140068); + writel(0x1EBF131D, 0x4814006c); + writel(0x6F361E05, 0x48140070); +} + +static void mpu_pll_config(void) +{ + pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); +} + +static void l3_pll_config(void) +{ + u32 l3_osc_src, rd_osc_src = 0; + + l3_osc_src = L3_OSC_SRC; + rd_osc_src = readl(OSC_SRC_CTRL); + + if (OSC_SRC0 == l3_osc_src) + writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); + else + writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); + + pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); +} + +void ddr_pll_config(unsigned int ddrpll_m) +{ + pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); +} + +void sata_pll_config(void) +{ + /* + * This sequence for configuring the SATA PLL + * resident in the control module is documented + * in TI8148 TRM section 21.3.1 + */ + writel(SATA_PLLCFG1, &spll->pllcfg1); + udelay(50); + + writel(SATA_PLLCFG3, &spll->pllcfg3); + udelay(50); + + writel(SATA_PLLCFG0_1, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_2, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_3, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_4, &spll->pllcfg0); + udelay(50); + + while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) + ; +} + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->fwclkctrl); + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) + ; + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +void setup_clocks_for_console(void) +{ + unlock_pll_control_mmr(); + /* UART0 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; +} + +void setup_early_clocks(void) +{ + setup_clocks_for_console(); +} + +/* + * Configure the PLL/PRCM for necessary peripherals + */ +void prcm_init(void) +{ + /* Enable the control module */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + /* Configure PLLs */ + mpu_pll_config(); + l3_pll_config(); + sata_pll_config(); + + /* Enable the required peripherals */ + enable_per_clocks(); +} diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c new file mode 100644 index 00000000000..079ddd7eb9f --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/clock_ti816x.c @@ -0,0 +1,450 @@ +/* + * clock_ti816x.c + * + * Clocks for TI816X based boards + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2009, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define CM_PLL_BASE (CTRL_BASE + 0x0400) + +/* Main PLL */ +#define MAIN_N 64 +#define MAIN_P 0x1 +#define MAIN_INTFREQ1 0x8 +#define MAIN_FRACFREQ1 0x800000 +#define MAIN_MDIV1 0x2 +#define MAIN_INTFREQ2 0xE +#define MAIN_FRACFREQ2 0x0 +#define MAIN_MDIV2 0x1 +#define MAIN_INTFREQ3 0x8 +#define MAIN_FRACFREQ3 0xAAAAB0 +#define MAIN_MDIV3 0x3 +#define MAIN_INTFREQ4 0x9 +#define MAIN_FRACFREQ4 0x55554F +#define MAIN_MDIV4 0x3 +#define MAIN_INTFREQ5 0x9 +#define MAIN_FRACFREQ5 0x374BC6 +#define MAIN_MDIV5 0xC +#define MAIN_MDIV6 0x48 +#define MAIN_MDIV7 0x4 + +/* DDR PLL */ +#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x4 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x3 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ +#define DDR_N 50 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x9 +#define DDR_FRACFREQ2 0x0 +#define DDR_MDIV2 0x19 +#define DDR_INTFREQ3 0x13 +#define DDR_FRACFREQ3 0x800000 +#define DDR_MDIV3 0x2 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +#define CONTROL_STATUS (CTRL_BASE + 0x40) +#define DDR_RCD (CTRL_BASE + 0x070C) +#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) +#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) + +#define INTCPS_SYSCONFIG 0x48200010 +#define CM_SYSCLK10_CLKSEL 0x48180324 + +struct cm_pll { + unsigned int mainpll_ctrl; /* offset 0x400 */ + unsigned int mainpll_pwd; + unsigned int mainpll_freq1; + unsigned int mainpll_div1; + unsigned int mainpll_freq2; + unsigned int mainpll_div2; + unsigned int mainpll_freq3; + unsigned int mainpll_div3; + unsigned int mainpll_freq4; + unsigned int mainpll_div4; + unsigned int mainpll_freq5; + unsigned int mainpll_div5; + unsigned int resv0[1]; + unsigned int mainpll_div6; + unsigned int resv1[1]; + unsigned int mainpll_div7; + unsigned int ddrpll_ctrl; /* offset 0x440 */ + unsigned int ddrpll_pwd; + unsigned int resv2[1]; + unsigned int ddrpll_div1; + unsigned int ddrpll_freq2; + unsigned int ddrpll_div2; + unsigned int ddrpll_freq3; + unsigned int ddrpll_div3; + unsigned int ddrpll_freq4; + unsigned int ddrpll_div4; + unsigned int ddrpll_freq5; + unsigned int ddrpll_div5; + unsigned int videopll_ctrl; /* offset 0x470 */ + unsigned int videopll_pwd; + unsigned int videopll_freq1; + unsigned int videopll_div1; + unsigned int videopll_freq2; + unsigned int videopll_div2; + unsigned int videopll_freq3; + unsigned int videopll_div3; + unsigned int resv3[4]; + unsigned int audiopll_ctrl; /* offset 0x4A0 */ + unsigned int audiopll_pwd; + unsigned int resv4[2]; + unsigned int audiopll_freq2; + unsigned int audiopll_div2; + unsigned int audiopll_freq3; + unsigned int audiopll_div3; + unsigned int audiopll_freq4; + unsigned int audiopll_div4; + unsigned int audiopll_freq5; + unsigned int audiopll_div5; +}; + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; +const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + + /* Wait for clocks to be active */ + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + /* Wait for emif0 to be fully functional, including OCP */ + while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) + ; + /* Wait for emif1 to be fully functional, including OCP */ + while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) + ; + + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + /* Wait for dmm to be fully functional, including OCP */ + while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) + ; + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); +} + +/* assume delay is aprox at least 1us */ +static void ddr_delay(int d) +{ + int i; + + /* + * read a control register. + * this is a bit more delay and cannot be optimized by the compiler + * assuming one read takes 200 cycles and A8 is runing 1 GHz + * somewhat conservative setting + */ + for (i = 0; i < 50*d; i++) + readl(CONTROL_STATUS); +} + +static void main_pll_init_ti816x(void) +{ + u32 main_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + main_pll_ctrl |= BIT(2); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Enable PLL by setting BIT3 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFF7; + main_pll_ctrl |= BIT(3); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFF; + main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Power up clock1-7 */ + writel(0x0, &cmpll->mainpll_pwd); + + /* Program the freq and divider values for clock1-7 */ + writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), + &cmpll->mainpll_freq1); + writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), + &cmpll->mainpll_freq2); + writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), + &cmpll->mainpll_freq3); + writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), + &cmpll->mainpll_freq4); + writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), + &cmpll->mainpll_freq5); + writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); + + writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); + + writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Put the PLL in normal mode, disable bypass */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); +} + +static void ddr_pll_bypass_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFFB; + ddr_pll_ctrl |= BIT(2); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); +} + +static void ddr_pll_init_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + /* Enable PLL by setting BIT3 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFF7; + ddr_pll_ctrl |= BIT(3); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFF; + ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + ddr_delay(10); + + /* Power up clock1-5 */ + writel(0x0, &cmpll->ddrpll_pwd); + + /* Program the freq and divider values for clock1-3 */ + writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), + &cmpll->ddrpll_freq2); + writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); + writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + ddr_delay(1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + + ddr_delay(5); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Power up RCD */ + writel(BIT(0), DDR_RCD); +} + +static void peripheral_enable(void) +{ + /* Wake-up the l3_slow clock */ + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + + /* + * Note on Timers: + * There are 8 timers(0-7) out of which timer 0 is a secure timer. + * Timer 0 mux should not be changed + * + * To access the timer registers we need the to be + * enabled which is what we do in the first step + */ + + /* Enable timer1 */ + writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); + /* Select timer1 clock to be CLKIN (27MHz) */ + writel(BIT(1), CM_TIMER1_CLKSEL); + + /* Wait for timer1 to be ON-ACTIVE */ + while (((readl(&cmalwon->l3slowclkstctrl) + & (0x80000<<1))>>20) != 1) + ; + /* Wait for timer1 to be enabled */ + while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) + ; + /* Active posted mode */ + writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); + while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) + ; + /* Start timer1 */ + writel(BIT(0), (DM_TIMER1_BASE + 0x38)); + + /* eFuse */ + writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); + while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) + ; + + /* Enable gpio0 */ + writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); + while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) + ; + writel((BIT(8)), &cmalwon->gpio0clkctrl); + + /* Enable spi */ + writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); + while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) + ; + + /* Enable i2c0 */ + writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); + while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) + ; + + /* Enable ethernet0 */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + + /* Enable hsmmc */ + writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); + while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) + ; +} + +void setup_clocks_for_console(void) +{ + /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ + writel(0x0, CM_SYSCLK10_CLKSEL); + + ddr_pll_bypass_ti816x(); + + /* Enable uart0-2 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); + while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); + while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) + ; + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +void setup_early_clocks(void) +{ + setup_clocks_for_console(); +} + +void prcm_init(void) +{ + /* Enable the control */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + main_pll_init_ti816x(); + ddr_pll_init_ti816x(); + + /* + * With clk freqs setup to desired values, + * enable the required peripherals + */ + peripheral_enable(); +} diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c new file mode 100644 index 00000000000..6acf30c5db0 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -0,0 +1,377 @@ +/* + * DDR Configuration for AM33xx devices. + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/** + * Base address for EMIF instances + */ +static struct emif_reg_struct *emif_reg[2] = { + (struct emif_reg_struct *)EMIF4_0_CFG_BASE, + (struct emif_reg_struct *)EMIF4_1_CFG_BASE}; + +/** + * Base addresses for DDR PHY cmd/data regs + */ +static struct ddr_cmd_regs *ddr_cmd_reg[2] = { + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR, + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2}; + +static struct ddr_data_regs *ddr_data_reg[2] = { + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR, + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2}; + +/** + * Base address for ddr io control instances + */ +static struct ddr_cmdtctrl *ioctrl_reg = { + (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; + +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) +{ + u32 mr; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + + mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) +{ + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); +} + +static void configure_mr(int nr, u32 cs) +{ + u32 mr_addr; + + while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(nr, cs, LPDDR2_MR10, 0x56); + + set_mr(nr, cs, LPDDR2_MR1, 0x43); + set_mr(nr, cs, LPDDR2_MR2, 0x2); + + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(nr, cs, mr_addr, 0x2); +} + +/* + * Configure EMIF4D5 registers and MR registers For details about these magic + * values please see the EMIF registers section of the TRM. + */ +void config_sdram_emif4d5(const struct emif_regs *regs, int nr) +{ + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); + + writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_win, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); + writel(regs->emif_rd_wr_lvl_rmp_ctl, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + writel(regs->emif_rd_wr_exec_thresh, + &emif_reg[nr]->emif_rd_wr_exec_thresh); + + /* + * for most SOCs these registers won't need to be changed so only + * write to these registers if someone explicitly has set the + * register's value. + */ + if(regs->emif_cos_config) { + writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map); + writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map); + writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map); + writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); + } + + /* + * Sequence to ensure that the PHY is in a known state prior to + * startting hardware leveling. Also acts as to latch some state from + * the EMIF into the PHY. + */ + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + + clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); + + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + + /* Perform hardware leveling for DDR3 */ + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + + /* Enable read leveling */ + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + + /* + * Enable full read and write leveling. Wait for read and write + * leveling bit to clear RDWRLVLFULL_START bit 31 + */ + while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) + != 0) + ; + + /* Check the timeout register to see if leveling is complete */ + if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) + puts("DDR3 H/W leveling incomplete with errors\n"); + + } else { + /* DDR2 */ + configure_mr(nr, 0); + configure_mr(nr, 1); + } +} + +/** + * Configure SDRAM + */ +void config_sdram(const struct emif_regs *regs, int nr) +{ + if (regs->zq_config) { + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + /* Trigger initialization */ + writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + + /* Write proper sdram_ref_cref_ctrl value */ + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + } + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); +} + +/** + * Set SDRAM timings + */ +void set_sdram_timings(const struct emif_regs *regs, int nr) +{ + writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); +} + +/* + * Configure EXT PHY registers for software leveling + */ +static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + __maybe_unused const u32 *ext_phy_ctrl_const_regs; + u32 i = 0; + __maybe_unused u32 size; + + ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = + (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + +#ifdef CONFIG_AM43XX + /* + * External phy 6-24 registers do not change with ddr frequency. + * These only need to be set on DDR2 on AM43xx. + */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); + + if (!size) + return; + + for (i = 0; i < size; i++) { + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + } +#endif +} + +/* + * Configure EXT PHY registers for hardware leveling + */ +static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) +{ + /* + * Enable hardware leveling on the EMIF. For details about these + * magic values please see the EMIF registers section of the TRM. + */ + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); + writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); + writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw); + writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24); + writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw); + writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25); + writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); + writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + + /* + * Sequence to ensure that the PHY is again in a known state after + * hardware leveling. + */ + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); +} + +/** + * Configure DDR PHY + */ +void config_ddr_phy(const struct emif_regs *regs, int nr) +{ + /* + * Disable initialization and refreshes for now until we finish + * programming EMIF regs and set time between rising edge of + * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec. + * We currently hardcode a value based on a max expected frequency + * of 400MHz. + */ + writel(EMIF_REG_INITREF_DIS_MASK | 0x3100, + &emif_reg[nr]->emif_sdram_ref_ctrl); + + writel(regs->emif_ddr_phy_ctlr_1, + &emif_reg[nr]->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, + &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); + + if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) { + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) + ext_phy_settings_hwlvl(regs, nr); + else + ext_phy_settings_swlvl(regs, nr); + } +} + +/** + * Configure DDR CMD control registers + */ +void config_cmd_ctrl(const struct cmd_control *cmd, int nr) +{ + if (!cmd) + return; + + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); + writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); + + writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); + writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); + + writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); + writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); +} + +/** + * Configure DDR DATA registers + */ +void config_ddr_data(const struct ddr_data *data, int nr) +{ + int i; + + if (!data) + return; + + for (i = 0; i < DDR_DATA_REGS_NR; i++) { + writel(data->datardsratio0, + &(ddr_data_reg[nr]+i)->dt0rdsratio0); + writel(data->datawdsratio0, + &(ddr_data_reg[nr]+i)->dt0wdsratio0); + writel(data->datawiratio0, + &(ddr_data_reg[nr]+i)->dt0wiratio0); + writel(data->datagiratio0, + &(ddr_data_reg[nr]+i)->dt0giratio0); + writel(data->datafwsratio0, + &(ddr_data_reg[nr]+i)->dt0fwsratio0); + writel(data->datawrsratio0, + &(ddr_data_reg[nr]+i)->dt0wrsratio0); + } +} + +void config_io_ctrl(const struct ctrl_ioregs *ioregs) +{ + if (!ioregs) + return; + + writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); + writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); + writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); + writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); + writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); +#ifdef CONFIG_AM43XX + writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); + writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); + writel(ioregs->emif_sdram_config_ext, + &ioctrl_reg->emif_sdram_config_ext); +#endif +} diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c new file mode 100644 index 00000000000..27fa3fb4628 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -0,0 +1,140 @@ +/* + * emif4.c + * + * AM33XX emif4 configuration file + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + sdram_init(); +#endif + + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_TI81XX +static struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)DMM_BASE; +#endif +#ifndef CONFIG_TI816X +static struct vtp_reg *vtpreg[2] = { + (struct vtp_reg *)VTP0_CTRL_ADDR, + (struct vtp_reg *)VTP1_CTRL_ADDR}; +#endif +#ifdef CONFIG_AM33XX +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +#endif +#ifdef CONFIG_AM43XX +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +static struct cm_device_inst *cm_device = + (struct cm_device_inst *)CM_DEVICE_INST; +#endif + +#ifdef CONFIG_TI81XX +void config_dmm(const struct dmm_lisa_map_regs *regs) +{ + enable_dmm_clocks(); + + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); + + writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); +} +#endif + +#ifndef CONFIG_TI816X +static void config_vtp(int nr) +{ + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, + &vtpreg[nr]->vtp0ctrlreg); + + /* Poll for READY */ + while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != + VTP_CTRL_READY) + ; +} +#endif + +void __weak ddr_pll_config(unsigned int ddrpll_m) +{ +} + +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, + const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, int nr) +{ + ddr_pll_config(pll); +#ifndef CONFIG_TI816X + config_vtp(nr); +#endif + config_cmd_ctrl(ctrl, nr); + + config_ddr_data(data, nr); +#ifdef CONFIG_AM33XX + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + +#endif +#ifdef CONFIG_AM43XX + writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); + while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) + ; + + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) + /* Allow EMIF to control DDR_RESET */ + writel(0x00000000, &ddrctrl->ddrioctrl); +#endif + + /* Program EMIF instance */ + config_ddr_phy(regs, nr); + set_sdram_timings(regs, nr); + if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) + config_sdram_emif4d5(regs, nr); + else + config_sdram(regs, nr); +} +#endif diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c new file mode 100644 index 00000000000..2ded47228d6 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/mux.c @@ -0,0 +1,33 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* + * Configure the pin mux for the module + */ +void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux) +{ + int i; + + if (!mod_pin_mux) + return; + + for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) + MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); +} diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c new file mode 100644 index 00000000000..f0f72fa6d4d --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -0,0 +1,176 @@ +/* + * sys_info.c + * + * System information functions + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff + * Syed Mohammed Khasim + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; + +/** + * get_cpu_rev(void) - extract rev info + */ +u32 get_cpu_rev(void) +{ + u32 id; + u32 rev; + + id = readl(DEVICE_ID); + rev = (id >> 28) & 0xff; + + return rev; +} + +/** + * get_cpu_type(void) - extract cpu info + */ +u32 get_cpu_type(void) +{ + u32 id = 0; + u32 partnum; + + id = readl(DEVICE_ID); + partnum = (id >> 12) & 0xffff; + + return partnum; +} + +/** + * get_device_type(): tell if GP/HS/EMU/TST + */ +u32 get_device_type(void) +{ + int mode; + mode = readl(&cstat->statusreg) & (DEVICE_MASK); + return mode >>= 8; +} + +/** + * get_sysboot_value(void) - return SYS_BOOT[4:0] + */ +u32 get_sysboot_value(void) +{ + return readl(&cstat->statusreg) & SYSBOOT_MASK; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +static char *cpu_revs[] = { + "1.0", + "2.0", + "2.1"}; + + +static char *dev_types[] = { + "TST", + "EMU", + "HS", + "GP"}; + +/** + * Print CPU information + */ +int print_cpuinfo(void) +{ + char *cpu_s, *sec_s, *rev_s; + + switch (get_cpu_type()) { + case AM335X: + cpu_s = "AM335X"; + break; + case TI81XX: + cpu_s = "TI81XX"; + break; + case AM437X: + cpu_s = "AM437X"; + break; + default: + cpu_s = "Unknown CPU type"; + break; + } + + if (get_cpu_rev() < ARRAY_SIZE(cpu_revs)) + rev_s = cpu_revs[get_cpu_rev()]; + else + rev_s = "?"; + + if (get_device_type() < ARRAY_SIZE(dev_types)) + sec_s = dev_types[get_device_type()]; + else + sec_s = "?"; + + printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_AM33XX +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) +{ + int sil_rev; + + sil_rev = readl(&cdev->deviceid) >> 28; + + if (sil_rev == 1) + /* PG 2.0, efuse may not be set. */ + return MPUPLL_M_800; + else if (sil_rev >= 2) { + /* Check what the efuse says our max speed is. */ + int efuse_arm_mpu_max_freq; + efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { + case AM335X_ZCZ_1000: + return MPUPLL_M_1000; + case AM335X_ZCZ_800: + return MPUPLL_M_800; + case AM335X_ZCZ_720: + return MPUPLL_M_720; + case AM335X_ZCZ_600: + case AM335X_ZCE_600: + return MPUPLL_M_600; + case AM335X_ZCZ_300: + case AM335X_ZCE_300: + return MPUPLL_M_300; + } + } + + /* PG 1.0 or otherwise unknown, use the PG1.0 max */ + return MPUPLL_M_720; +} + +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) +{ + /* For PG2.1 and later, we have one set of values. */ + if (sil_rev >= 2) { + switch (frequency) { + case MPUPLL_M_1000: + return TPS65910_OP_REG_SEL_1_3_2_5; + case MPUPLL_M_800: + return TPS65910_OP_REG_SEL_1_2_6; + case MPUPLL_M_720: + return TPS65910_OP_REG_SEL_1_2_0; + case MPUPLL_M_600: + case MPUPLL_M_300: + return TPS65910_OP_REG_SEL_1_1_3; + } + } + + /* Default to PG1.0/PG2.0 values. */ + return TPS65910_OP_REG_SEL_1_1_3; +} +#endif diff --git a/arch/arm/mach-omap2/am33xx/u-boot-spl.lds b/arch/arm/mach-omap2/am33xx/u-boot-spl.lds new file mode 100644 index 00000000000..07cf2678782 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/u-boot-spl.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c new file mode 100644 index 00000000000..385310ba1ec --- /dev/null +++ b/arch/arm/mach-omap2/boot-common.c @@ -0,0 +1,252 @@ +/* + * boot-common.c + * + * Common bootmode functions for omap based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +__weak u32 omap_sys_boot_device(void) +{ + return BOOT_DEVICE_NONE; +} + +void save_omap_boot_params(void) +{ + u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + struct omap_boot_parameters *omap_boot_params; + int sys_boot_device = 0; + u32 boot_device; + u32 boot_mode; + + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + omap_boot_params = (struct omap_boot_parameters *)boot_params; + + boot_device = omap_boot_params->boot_device; + boot_mode = MMCSD_MODE_UNDEFINED; + + /* Boot device */ + +#ifdef BOOT_DEVICE_NAND_I2C + /* + * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. + * Otherwise the SPL boot IF can't handle this device correctly. + * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens + * Draco leads to this boot-device passed to SPL from the BootROM. + */ + if (boot_device == BOOT_DEVICE_NAND_I2C) + boot_device = BOOT_DEVICE_NAND; +#endif +#ifdef BOOT_DEVICE_QSPI_4 + /* + * We get different values for QSPI_1 and QSPI_4 being used, but + * don't actually care about this difference. Rather than + * mangle the later code, if we're coming in as QSPI_4 just + * change to the QSPI_1 value. + */ + if (boot_device == BOOT_DEVICE_QSPI_4) + boot_device = BOOT_DEVICE_SPI; +#endif + /* + * When booting from peripheral booting, the boot device is not usable + * as-is (unless there is support for it), so the boot device is instead + * figured out using the SYS_BOOT pins. + */ + switch (boot_device) { +#if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT) + case BOOT_DEVICE_UART: + sys_boot_device = 1; + break; +#endif +#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT) + case BOOT_DEVICE_USB: + sys_boot_device = 1; + break; +#endif +#if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT) + case BOOT_DEVICE_USBETH: + sys_boot_device = 1; + break; +#endif +#if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT) + case BOOT_DEVICE_CPGMAC: + sys_boot_device = 1; + break; +#endif +#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT) + case BOOT_DEVICE_DFU: + sys_boot_device = 1; + break; +#endif + } + + if (sys_boot_device) { + boot_device = omap_sys_boot_device(); + + /* MMC raw mode will fallback to FS mode. */ + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) + boot_mode = MMCSD_MODE_RAW; + } + + gd->arch.omap_boot_device = boot_device; + + /* Boot mode */ + +#ifdef CONFIG_OMAP34XX + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + switch (boot_device) { + case BOOT_DEVICE_MMC1: + boot_mode = MMCSD_MODE_FS; + break; + case BOOT_DEVICE_MMC2: + boot_mode = MMCSD_MODE_RAW; + break; + } + } +#else + /* + * If the boot device was dynamically changed and doesn't match what + * the bootrom initially booted, we cannot use the boot device + * descriptor to figure out the boot mode. + */ + if ((boot_device == omap_boot_params->boot_device) && + (boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + boot_params = omap_boot_params->boot_device_descriptor; + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET)); + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET)); + + if (boot_mode != MMCSD_MODE_FS && + boot_mode != MMCSD_MODE_RAW) +#ifdef CONFIG_SUPPORT_EMMC_BOOT + boot_mode = MMCSD_MODE_EMMCBOOT; +#else + boot_mode = MMCSD_MODE_UNDEFINED; +#endif + } +#endif + + gd->arch.omap_boot_mode = boot_mode; + +#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ + !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) + + /* CH flags */ + + gd->arch.omap_ch_flags = omap_boot_params->ch_flags; +#endif +} + +#ifdef CONFIG_SPL_BUILD +u32 spl_boot_device(void) +{ + return gd->arch.omap_boot_device; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return gd->arch.omap_boot_mode; +} + +void spl_board_init(void) +{ + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ + save_omap_boot_params(); + + /* Prepare console output */ + preloader_console_init(); + +#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) + gpmc_init(); +#endif +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); +#endif +#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) + arch_misc_init(); +#endif +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif +#ifdef CONFIG_AM33XX + am33xx_spl_board_init(); +#endif +} + +__weak int board_mmc_init(bd_t *bis) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + omap_mmc_init(0, 0, 0, -1, -1); + break; + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + break; + } + return 0; +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(u32 *); + image_entry_noargs_t image_entry = + (image_entry_noargs_t) spl_image->entry_point; + + u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + + debug("image entry point: 0x%X\n", spl_image->entry_point); + /* Pass the saved boot_params from rom code */ + image_entry((u32 *)boot_params); +} +#endif + +#ifdef CONFIG_SCSI_AHCI_PLAT +void arch_preboot_os(void) +{ + ahci_reset((void __iomem *)DWC_AHSATA_BASE); +} +#endif + +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE) +int fb_set_reboot_flag(void) +{ + printf("Setting reboot to fastboot flag ...\n"); + setenv("dofastboot", "1"); + saveenv(); + return 0; +} +#endif diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c new file mode 100644 index 00000000000..9b975831046 --- /dev/null +++ b/arch/arm/mach-omap2/clocks-common.c @@ -0,0 +1,892 @@ +/* + * + * Clock initialization for OMAP4 + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * Based on previous work by: + * Santosh Shilimkar + * Rajendra Nayak + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_SPL_BUILD +/* + * printing to console doesn't work unless + * this code is executed from SPL + */ +#define printf(fmt, args...) +#define puts(s) +#endif + +const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 20000000, /* 20 MHz */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 27000000, /* 27 MHz */ + 38400000, /* 38.4 MHz */ +}; + +static inline u32 __get_sys_clk_index(void) +{ + s8 ind; + /* + * For ES1 the ROM code calibration of sys clock is not reliable + * due to hw issue. So, use hard-coded value. If this value is not + * correct for any board over-ride this function in board file + * From ES2.0 onwards you will get this information from + * CM_SYS_CLKSEL + */ + if (omap_revision() == OMAP4430_ES1_0) + ind = OMAP_SYS_CLK_IND_38_4_MHZ; + else { + /* SYS_CLKSEL - 1 to match the dpll param array indices */ + ind = (readl((*prcm)->cm_sys_clksel) & + CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + } + return ind; +} + +u32 get_sys_clk_index(void) + __attribute__ ((weak, alias("__get_sys_clk_index"))); + +u32 get_sys_clk_freq(void) +{ + u8 index = get_sys_clk_index(); + return sys_clk_array[index]; +} + +void setup_post_dividers(u32 const base, const struct dpll_params *params) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->m4_h11 >= 0) + writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); + if (params->m5_h12 >= 0) + writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); + if (params->m6_h13 >= 0) + writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); + if (params->m7_h14 >= 0) + writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); + if (params->h21 >= 0) + writel(params->h21, &dpll_regs->cm_div_h21_dpll); + if (params->h22 >= 0) + writel(params->h22, &dpll_regs->cm_div_h22_dpll); + if (params->h23 >= 0) + writel(params->h23, &dpll_regs->cm_div_h23_dpll); + if (params->h24 >= 0) + writel(params->h24, &dpll_regs->cm_div_h24_dpll); +} + +static inline void do_bypass_dpll(u32 const base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_FAST_RELOCK_BYPASS << + CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(u32 const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, + LDELAY)) { + printf("Bypassing DPLL failed %x\n", base); + } +} + +static inline void do_lock_dpll(u32 const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(u32 const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + &dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for %x\n", base); + hang(); + } +} + +inline u32 check_for_lock(u32 const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; + + return lock; +} + +const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->mpu[sysclk_ind]; +} + +const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->core[sysclk_ind]; +} + +const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->per[sysclk_ind]; +} + +const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->iva[sysclk_ind]; +} + +const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->usb[sysclk_ind]; +} + +const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) +{ +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->abe[sysclk_ind]; +#else + return dpll_data->abe; +#endif +} + +static const struct dpll_params *get_ddr_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->ddr) + return NULL; + return &dpll_data->ddr[sysclk_ind]; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static const struct dpll_params *get_gmac_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->gmac) + return NULL; + return &dpll_data->gmac[sysclk_ind]; +} +#endif + +static void do_setup_dpll(u32 const base, const struct dpll_params *params, + u8 lock, char *dpll) +{ + u32 temp, M, N; + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!params) + return; + + temp = readl(&dpll_regs->cm_clksel_dpll); + + if (check_for_lock(base)) { + /* + * The Dpll has already been locked by rom code using CH. + * Check if M,N are matching with Ideal nominal opp values. + * If matches, skip the rest otherwise relock. + */ + M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; + N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT; + if ((M != (params->m)) || (N != (params->n))) { + debug("\n %s Dpll locked, but not for ideal M = %d," + "N = %d values, current values are M = %d," + "N= %d" , dpll, params->m, params->n, + M, N); + } else { + /* Dpll locked with ideal values for nominal opps. */ + debug("\n %s Dpll already locked with ideal" + "nominal opp values", dpll); + + bypass_dpll(base); + goto setup_post_dividers; + } + } + + bypass_dpll(base); + + /* Set M & N */ + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, &dpll_regs->cm_clksel_dpll); + +setup_post_dividers: + setup_post_dividers(base, params); + + /* Lock */ + if (lock) + do_lock_dpll(base); + + /* Wait till the DPLL locks */ + if (lock) + wait_for_lock(base); +} + +u32 omap_ddr_clk(void) +{ + u32 ddr_clk, sys_clk_khz, omap_rev, divider; + const struct dpll_params *core_dpll_params; + + omap_rev = omap_revision(); + sys_clk_khz = get_sys_clk_freq() / 1000; + + core_dpll_params = get_core_dpll_params(*dplls_data); + + debug("sys_clk %d\n ", sys_clk_khz * 1000); + + /* Find Core DPLL locked frequency first */ + ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / + (core_dpll_params->n + 1); + + if (omap_rev < OMAP5430_ES1_0) { + /* + * DDR frequency is PHY_ROOT_CLK/2 + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + divider = 4; + } else { + /* + * DDR frequency is PHY_ROOT_CLK + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + divider = 2; + } + + ddr_clk = ddr_clk / divider / core_dpll_params->m2; + ddr_clk *= 1000; /* convert to Hz */ + debug("ddr_clk %d\n ", ddr_clk); + + return ddr_clk; +} + +/* + * Lock MPU dpll + * + * Resulting MPU frequencies: + * 4430 ES1.0 : 600 MHz + * 4430 ES2.x : 792 MHz (OPP Turbo) + * 4460 : 920 MHz (OPP Turbo) - DCC disabled + */ +void configure_mpu_dpll(void) +{ + const struct dpll_params *params; + struct dpll_regs *mpu_dpll_regs; + u32 omap_rev; + omap_rev = omap_revision(); + + /* + * DCC and clock divider settings for 4460. + * DCC is required, if more than a certain frequency is required. + * For, 4460 > 1GHZ. + * 5430 > 1.4GHZ. + */ + if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { + mpu_dpll_regs = + (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); + bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); + clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); + setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); + clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, + CM_CLKSEL_DCC_EN_MASK); + } + + params = get_mpu_dpll_params(*dplls_data); + + do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); + debug("MPU DPLL locked\n"); +} + +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ + defined(CONFIG_USB_MUSB_OMAP2PLUS) +static void setup_usb_dpll(void) +{ + const struct dpll_params *params; + u32 sys_clk_khz, sd_div, num, den; + + sys_clk_khz = get_sys_clk_freq() / 1000; + /* + * USB: + * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction + * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) + * - where CLKINP is sys_clk in MHz + * Use CLKINP in KHz and adjust the denominator accordingly so + * that we have enough accuracy and at the same time no overflow + */ + params = get_usb_dpll_params(*dplls_data); + num = params->m * sys_clk_khz; + den = (params->n + 1) * 250 * 1000; + num += den - 1; + sd_div = num / den; + clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, + CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, + sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); + + /* Now setup the dpll with the regular function */ + do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); +} +#endif + +static void setup_dplls(void) +{ + u32 temp; + const struct dpll_params *params; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + debug("setup_dplls\n"); + + /* CORE dpll */ + params = get_core_dpll_params(*dplls_data); /* default - safest */ + /* + * Do not lock the core DPLL now. Just set it up. + * Core DPLL will be locked after setting up EMIF + * using the FREQ_UPDATE method(freq_update_core()) + */ + if (emif_sdram_type(readl(&emif->emif_sdram_config)) == + EMIF_SDRAM_TYPE_LPDDR2) + do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, + DPLL_NO_LOCK, "core"); + else + do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, + DPLL_LOCK, "core"); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ + temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | + (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | + (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); + writel(temp, (*prcm)->cm_clksel_core); + debug("Core DPLL configured\n"); + + /* lock PER dpll */ + params = get_per_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_per, + params, DPLL_LOCK, "per"); + debug("PER DPLL locked\n"); + + /* MPU dpll */ + configure_mpu_dpll(); + +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ + defined(CONFIG_USB_MUSB_OMAP2PLUS) + setup_usb_dpll(); +#endif + params = get_ddr_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, + params, DPLL_LOCK, "ddr"); + +#ifdef CONFIG_DRIVER_TI_CPSW + params = get_gmac_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, + DPLL_LOCK, "gmac"); +#endif +} + +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) +{ + u32 offset_code; + + volt_offset -= pmic->base_offset; + + offset_code = (volt_offset + pmic->step - 1) / pmic->step; + + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + return offset_code + pmic->start_code; +} + +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) +{ + u32 offset_code; + u32 offset = volt_mv; + int ret = 0; + + if (!volt_mv) + return; + + pmic->pmic_bus_init(); + /* See if we can first get the GPIO if needed */ + if (pmic->gpio_en) + ret = gpio_request(pmic->gpio, "PMIC_GPIO"); + + if (ret < 0) { + printf("%s: gpio %d request failed %d\n", __func__, + pmic->gpio, ret); + return; + } + + /* Pull the GPIO low to select SET0 register, while we program SET1 */ + if (pmic->gpio_en) + gpio_direction_output(pmic->gpio, 0); + + /* convert to uV for better accuracy in the calculations */ + offset *= 1000; + + offset_code = get_offset_code(offset, pmic); + + debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, + offset_code); + + if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) + printf("Scaling voltage failed for 0x%x\n", vcore_reg); + if (pmic->gpio_en) + gpio_direction_output(pmic->gpio, 1); +} + +static u32 optimize_vcore_voltage(struct volts const *v) +{ + u32 val; + if (!v->value) + return 0; + if (!v->efuse.reg) + return v->value; + + switch (v->efuse.reg_bits) { + case 16: + val = readw(v->efuse.reg); + break; + case 32: + val = readl(v->efuse.reg); + break; + default: + printf("Error: efuse 0x%08x bits=%d unknown\n", + v->efuse.reg, v->efuse.reg_bits); + return v->value; + } + + if (!val) { + printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", + v->efuse.reg, v->efuse.reg_bits, v->value); + return v->value; + } + + debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", + __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); + return val; +} + +#ifdef CONFIG_IODELAY_RECALIBRATION +void __weak recalibrate_iodelay(void) +{ +} +#endif + +/* + * Setup the voltages for the main SoC core power domains. + * We start with the maximum voltages allowed here, as set in the corresponding + * vcores_data struct, and then scale (usually down) to the fused values that + * are retrieved from the SoC. The scaling happens only if the efuse.reg fields + * are initialised. + * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is + * compiled conditionally. Note that the new code writes the scaled (or zeroed) + * values back to the vcores_data struct for eventual reuse. Zero values mean + * that the corresponding rails are not controlled separately, and are not sent + * to the PMIC. + */ +void scale_vcores(struct vcores_data const *vcores) +{ + int i; + struct volts *pv = (struct volts *)vcores; + struct volts *px; + + for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) { + debug("%d -> ", pv->value); + if (pv->value) { + /* Handle non-empty members only */ + pv->value = optimize_vcore_voltage(pv); + px = (struct volts *)vcores; + while (px < pv) { + /* + * Scan already handled non-empty members to see + * if we have a group and find the max voltage, + * which is set to the first occurance of the + * particular SMPS; the other group voltages are + * zeroed. + */ + if (px->value) { + if ((pv->pmic->i2c_slave_addr == + px->pmic->i2c_slave_addr) && + (pv->addr == px->addr)) { + /* Same PMIC, same SMPS */ + if (pv->value > px->value) + px->value = pv->value; + + pv->value = 0; + } + } + px++; + } + } + debug("%d\n", pv->value); + pv++; + } + + debug("cor: %d\n", vcores->core.value); + do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); + /* + * IO delay recalibration should be done immediately after + * adjusting AVS voltages for VDD_CORE_L. + * Respective boards should call __recalibrate_iodelay() + * with proper mux, virtual and manual mode configurations. + */ +#ifdef CONFIG_IODELAY_RECALIBRATION + recalibrate_iodelay(); +#endif + + debug("mpu: %d\n", vcores->mpu.value); + do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); + /* Configure MPU ABB LDO after scale */ + abb_setup(vcores->mpu.efuse.reg, + (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, + (*prcm)->prm_abbldo_mpu_setup, + (*prcm)->prm_abbldo_mpu_ctrl, + (*prcm)->prm_irqstatus_mpu_2, + vcores->mpu.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); + + debug("mm: %d\n", vcores->mm.value); + do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); + /* Configure MM ABB LDO after scale */ + abb_setup(vcores->mm.efuse.reg, + (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl, + (*prcm)->prm_abbldo_mm_setup, + (*prcm)->prm_abbldo_mm_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->mm.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); + + debug("gpu: %d\n", vcores->gpu.value); + do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic); + /* Configure GPU ABB LDO after scale */ + abb_setup(vcores->gpu.efuse.reg, + (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl, + (*prcm)->prm_abbldo_gpu_setup, + (*prcm)->prm_abbldo_gpu_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->gpu.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); + debug("eve: %d\n", vcores->eve.value); + do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic); + /* Configure EVE ABB LDO after scale */ + abb_setup(vcores->eve.efuse.reg, + (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl, + (*prcm)->prm_abbldo_eve_setup, + (*prcm)->prm_abbldo_eve_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->eve.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); + debug("iva: %d\n", vcores->iva.value); + do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic); + /* Configure IVA ABB LDO after scale */ + abb_setup(vcores->iva.efuse.reg, + (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl, + (*prcm)->prm_abbldo_iva_setup, + (*prcm)->prm_abbldo_iva_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->iva.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); +} + +static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - %x\n", clkctrl_reg); +} + +static inline void disable_clock_domain(u32 const clkctrl_reg) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Disable clock domain - %x\n", clkctrl_reg); +} + +static inline void wait_for_clk_enable(u32 clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%x idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - %x\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +static inline void wait_for_clk_disable(u32 clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; + u32 bound = LDELAY; + + while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) { + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock disable failed for 0x%x idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void disable_clock_module(u32 const clkctrl_addr, + u32 wait_for_disable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Disable clock module - %x\n", clkctrl_addr); + if (wait_for_disable) + wait_for_clk_disable(clkctrl_addr); +} + +void freq_update_core(void) +{ + u32 freq_config1 = 0; + const struct dpll_params *core_dpll_params; + u32 omap_rev = omap_revision(); + + core_dpll_params = get_core_dpll_params(*dplls_data); + /* Put EMIF clock domain in sw wakeup mode */ + enable_clock_domain((*prcm)->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); + + freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | + SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; + + freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & + SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; + + freq_config1 |= (core_dpll_params->m2 << + SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & + SHADOW_FREQ_CONFIG1_M2_DIV_MASK; + + writel(freq_config1, (*prcm)->cm_shadow_freq_config1); + if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, + (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { + puts("FREQ UPDATE procedure failed!!"); + hang(); + } + + /* + * Putting EMIF in HW_AUTO is seen to be causing issues with + * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP + * in OMAP5430 ES1.0 silicon + */ + if (omap_rev != OMAP5430_ES1_0) { + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain((*prcm)->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); + } +} + +void bypass_dpll(u32 const base) +{ + do_bypass_dpll(base); + wait_for_bypass(base); +} + +void lock_dpll(u32 const base) +{ + do_lock_dpll(base); + wait_for_lock(base); +} + +static void setup_clocks_for_console(void) +{ + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable all UARTs - console will be on one of them */ + clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO << + CD_CLKCTRL_CLKTRCTRL_SHIFT); +} + +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, + u8 wait_for_enable) +{ + u32 i, max = 100; + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) { + enable_clock_module(clk_modules_hw_auto[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { + enable_clock_module(clk_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } +} + +void do_disable_clocks(u32 const *clk_domains, + u32 const *clk_modules_disable, + u8 wait_for_disable) +{ + u32 i, max = 100; + + + /* Clock modules that need to be put in SW_DISABLE */ + for (i = 0; (i < max) && clk_modules_disable[i]; i++) + disable_clock_module(clk_modules_disable[i], + wait_for_disable); + + /* Put the clock domains in SW_SLEEP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) + disable_clock_domain(clk_domains[i]); +} + +/** + * setup_early_clocks() - Setup early clocks needed for SoC + * + * Setup clocks for console, SPL basic initialization clocks and initialize + * the timer. This is invoked prior prcm_init. + */ +void setup_early_clocks(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + setup_clocks_for_console(); + enable_basic_clocks(); + timer_init(); + /* Fall through */ + } +} + +void prcm_init(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + scale_vcores(*omap_vcores); + setup_dplls(); + setup_warmreset_time(); + break; + default: + break; + } + + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) + enable_basic_uboot_clocks(); +} + +void gpi2c_init(void) +{ + static int gpi2c = 1; + + if (gpi2c) { + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + gpi2c = 0; + } +} diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk new file mode 100644 index 00000000000..5368f6b2d72 --- /dev/null +++ b/arch/arm/mach-omap2/config.mk @@ -0,0 +1,53 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/arch/arm/mach-omap2/config_secure.mk + +ifdef CONFIG_SPL_BUILD +ifeq ($(CONFIG_AM33XX)$(CONFIG_TI_SECURE_DEVICE),yy) +# +# For booting from SPI use +# u-boot-spl_HS_SPI_X-LOADER to program flash +# +# On AM43XX: +# +# For booting spl from all other media use +# u-boot-spl_HS_ISSW +# +# On AM33XX: +# +# For booting spl from NAND flash use +# u-boot-spl_HS_X-LOADER +# +# For booting spl from SD/MMC/eMMC media use +# u-boot-spl_HS_MLO +# +# For booting spl over UART, USB, or Ethernet use +# u-boot-spl_HS_2ND +# +# Refer to README.ti-secure for more info +# +ALL-y += u-boot-spl_HS_ISSW +ALL-y += u-boot-spl_HS_SPI_X-LOADER +ALL-y += u-boot-spl_HS_X-LOADER +ALL-y += u-boot-spl_HS_MLO +ALL-y += u-boot-spl_HS_2ND +else +ifeq ($(CONFIG_OMAP54XX)$(CONFIG_TI_SECURE_DEVICE),yy) +ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER +else +ALL-y += MLO +ifeq ($(CONFIG_AM33XX),y) +ALL-y += MLO.byteswap +endif +endif +endif +else +ifeq ($(CONFIG_TI_SECURE_DEVICE),y) +ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER +ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img +endif +ALL-y += u-boot.img +endif diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk new file mode 100644 index 00000000000..1122439e38b --- /dev/null +++ b/arch/arm/mach-omap2/config_secure.mk @@ -0,0 +1,113 @@ +# +# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# +quiet_cmd_mkomapsecimg = MKIMAGE $@ +ifneq ($(TI_SECURE_DEV_PKG),) +ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) +ifneq ($(CONFIG_SPL_BUILD),) +cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ + $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) +else +cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ + $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) +endif +else +cmd_mkomapsecimg = echo "WARNING:" \ + "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \ + "$@ was NOT created!" +endif +else +cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ + "variable must be defined for TI secure devices. $@ was NOT created!" +endif + +ifdef CONFIG_SPL_LOAD_FIT +quiet_cmd_omapsecureimg = SECURE $@ +ifneq ($(TI_SECURE_DEV_PKG),) +ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),) +cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \ + $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) +else +cmd_omapsecureimg = echo "WARNING:" \ + "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \ + "$@ was NOT created!"; cp $< $@ +endif +else +cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ + "variable must be defined for TI secure devices." \ + "$@ was NOT created!"; cp $< $@ +endif +endif + + +# Standard X-LOADER target (QPSI, NOR flash) +u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# For MLO targets (SD card boot) the final file name that is copied to the SD +# card FAT partition must be MLO, so we make a copy of the output file to a new +# file with that name +u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + @if [ -f $@ ]; then \ + cp -f $@ MLO; \ + fi + +# Standard 2ND target (certain peripheral boot modes) +u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# Standard ULO target (certain peripheral boot modes) +u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# Standard ISSW target (certain devices, various boot modes) +u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# For SPI flash on AM335x and AM43xx, these require special byte swap handling +# so we use the SPI_X-LOADER target instead of X-LOADER and let the +# create-boot-image.sh script handle that +u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot +# file, not an SPL. In this case the mkomapsecimg command looks for a +# u-boot-HS_* prefix +u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin + $(call if_changed,mkomapsecimg) + +# For supporting the SPL loading and interpreting of FIT images whose +# components are pre-processed before being integrated into the FIT image in +# order to secure them in some way +ifdef CONFIG_SPL_LOAD_FIT + +MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ + $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) + +OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) +$(OF_LIST_TARGETS): dtbs + +%_HS.dtb: %.dtb + $(call if_changed,omapsecureimg) + $(Q)if [ -f $@ ]; then \ + cp -f $@ $<; \ + fi + +u-boot-nodtb_HS.bin: u-boot-nodtb.bin + $(call if_changed,omapsecureimg) + +u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS)) + $(call if_changed,mkimage) + $(Q)if [ -f $@ ]; then \ + cp -f $@ u-boot.img; \ + fi + +endif diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c new file mode 100644 index 00000000000..b26984e26c5 --- /dev/null +++ b/arch/arm/mach-omap2/emif-common.c @@ -0,0 +1,1504 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int emif1_enabled = -1, emif2_enabled = -1; + +void set_lpmode_selfrefresh(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 reg; + + reg = readl(&emif->emif_pwr_mgmt_ctrl); + reg &= ~EMIF_REG_LP_MODE_MASK; + reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; + reg &= ~EMIF_REG_SR_TIM_MASK; + writel(reg, &emif->emif_pwr_mgmt_ctrl); + + /* dummy read for the new SR_TIM to be loaded */ + readl(&emif->emif_pwr_mgmt_ctrl); +} + +void force_emif_self_refresh() +{ + set_lpmode_selfrefresh(EMIF1_BASE); + if (!is_dra72x()) + set_lpmode_selfrefresh(EMIF2_BASE); +} + +inline u32 emif_num(u32 base) +{ + if (base == EMIF1_BASE) + return 1; + else if (base == EMIF2_BASE) + return 2; + else + return 0; +} + +static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) +{ + u32 mr; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + if (omap_revision() == OMAP4430_ES2_0) + mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); + else + mr = readl(&emif->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), + cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif->emif_lpddr2_mode_reg_data); +} + +void emif_reset_phy(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 iodft; + + iodft = readl(&emif->emif_iodft_tlgc); + iodft |= EMIF_REG_RESET_PHY_MASK; + writel(iodft, &emif->emif_iodft_tlgc); +} + +static void do_lpddr2_init(u32 base, u32 cs) +{ + u32 mr_addr; + const struct lpddr2_mr_regs *mr_regs; + + get_lpddr2_mr_regs(&mr_regs); + /* Wait till device auto initialization is complete */ + while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); + /* + * tZQINIT = 1 us + * Enough loops assuming a maximum of 2GHz + */ + + sdelay(2000); + + set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); + set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); + + /* + * Enable refresh along with writing MR2 + * Encoding of RL in MR2 is (RL - 2) + */ + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(base, cs, mr_addr, mr_regs->mr2); + + if (mr_regs->mr3 > 0) + set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); +} + +static void lpddr2_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* Not NVM */ + clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); + + /* + * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM + * when EMIF_SDRAM_CONFIG register is written + */ + setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + + /* + * Set the SDRAM_CONFIG and PHY_CTRL for the + * un-locked frequency & default RL + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + do_ext_phy_settings(base, regs); + + do_lpddr2_init(base, CS0); + if (regs->sdram_config & EMIF_REG_EBANK_MASK) + do_lpddr2_init(base, CS1); + + writel(regs->sdram_config, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + + /* Enable refresh now */ + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + + } + +__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ +} + +void emif_update_timings(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (!is_dra7xx()) + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + else + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); + + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); + if (omap_revision() == OMAP4430_ES1_0) { + /* ES1 bug EMIF should be in force idle during freq_update */ + writel(0, &emif->emif_pwr_mgmt_ctrl); + } else { + writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); + writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); + } + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + + if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, + &emif->emif_l3_config); + } else if (omap_revision() >= OMAP4460_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + &emif->emif_l3_config); + } else { + writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, + &emif->emif_l3_config); + } +} + +#ifndef CONFIG_OMAP44XX +static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* keep sdram in self-refresh */ + writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + __udelay(130); + + /* + * Set invert_clkout (if activated)--DDR_PHYCTRL_1 + * Invert clock adds an additional half cycle delay on the + * command interface. The additional half cycle, is usually + * meant to enable leveling in the situation that DQS is later + * than CK on the board.It also helps provide some additional + * margin for leveling. + */ + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1); + + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1_shdw); + __udelay(130); + + writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ + config_data_eye_leveling_samples(base); + + /* + * Launch 8 incremental WR_LVL- to compensate for + * PHY limitation. + */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, + &emif->emif_rd_wr_lvl_ctl); + + __udelay(130); + + /* Launch Incremental leveling */ + writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); +} + +static void update_hwleveling_output(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; + u32 reg, i, phy; + + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + phy = readl(&emif->emif_ddr_phy_ctrl_1); + + /* Update PHY_REG_RDDQS_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; + if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) + for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) + for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) + for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Disable Leveling */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); +} + +static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* Clear Error Status */ + clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); + + clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); + + /* Disable refreshed before leveling */ + clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, + EMIF_REG_INITREF_DIS_MASK); + + /* Start Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + __udelay(300); + + /* Check for leveling timeout */ + if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { + printf("Leveling timeout on EMIF%d\n", emif_num(base)); + return; + } + + /* Enable refreshes after leveling */ + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + + debug("HW leveling success\n"); + /* + * Update slave ratios in EXT_PHY_CTRLx registers + * as per HW leveling output + */ + update_hwleveling_output(base, regs); +} + +static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (warm_reset()) { + emif_reset_phy(base); + writel(0x0, &emif->emif_pwr_mgmt_ctrl); + } + do_ext_phy_settings(base, regs); + + writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, + &emif->emif_sdram_ref_ctrl); + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + __udelay(1000); + + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); + + if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) + dra7_ddr3_leveling(base, regs); +} + +static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + /* + * Set SDRAM_CONFIG and PHY control registers to locked frequency + * and RL =7. As the default values of the Mode Registers are not + * defined, contents of mode Registers must be fully initialized. + * H/W takes care of this initialization + */ + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + do_ext_phy_settings(base, regs); + + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + omap5_ddr3_leveling(base, regs); +} + +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + omap5_ddr3_init(base, regs); + else + dra7_ddr3_init(base, regs); +} +#endif + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) + +/* + * Organization and refresh requirements for LPDDR2 devices of different + * types and densities. Derived from JESD209-2 section 2.4 + */ +const struct lpddr2_addressing addressing_table[] = { + /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ + {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ + {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ + {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ + {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ + {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ + {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ + {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ + {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ + {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ + {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ +}; + +static const u32 lpddr2_density_2_size_in_mbytes[] = { + 8, /* 64Mb */ + 16, /* 128Mb */ + 32, /* 256Mb */ + 64, /* 512Mb */ + 128, /* 1Gb */ + 256, /* 2Gb */ + 512, /* 4Gb */ + 1024, /* 8Gb */ + 2048, /* 16Gb */ + 4096 /* 32Gb */ +}; + +/* + * Calculate the period of DDR clock from frequency value and set the + * denominator and numerator in global variables for easy access later + */ +static void set_ddr_clk_period(u32 freq) +{ + /* + * period = 1/freq + * period_in_ns = 10^9/freq + */ + *T_num = 1000000000; + *T_den = freq; + cancel_out(T_num, T_den, 200); + +} + +/* + * Convert time in nano seconds to number of cycles of DDR clock + */ +static inline u32 ns_2_cycles(u32 ns) +{ + return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); +} + +/* + * ns_2_cycles with the difference that the time passed is 2 times the actual + * value(to avoid fractions). The cycles returned is for the original value of + * the timing parameter + */ +static inline u32 ns_x2_2_cycles(u32 ns) +{ + return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); +} + +/* + * Find addressing table index based on the device's type(S2 or S4) and + * density + */ +s8 addressing_table_index(u8 type, u8 density, u8 width) +{ + u8 index; + if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) + return -1; + + /* + * Look at the way ADDR_TABLE_INDEX* values have been defined + * in emif.h compared to LPDDR2_DENSITY_* values + * The table is layed out in the increasing order of density + * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed + * at the end + */ + if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) + index = ADDR_TABLE_INDEX1GS2; + else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) + index = ADDR_TABLE_INDEX2GS2; + else + index = density; + + debug("emif: addressing table index %d\n", index); + + return index; +} + +/* + * Find the the right timing table from the array of timing + * tables of the device using DDR clock frequency + */ +static const struct lpddr2_ac_timings *get_timings_table(const struct + lpddr2_ac_timings const *const *device_timings, + u32 freq) +{ + u32 i, temp, freq_nearest; + const struct lpddr2_ac_timings *timings = 0; + + emif_assert(freq <= MAX_LPDDR2_FREQ); + emif_assert(device_timings); + + /* + * Start with the maximum allowed frequency - that is always safe + */ + freq_nearest = MAX_LPDDR2_FREQ; + /* + * Find the timings table that has the max frequency value: + * i. Above or equal to the DDR frequency - safe + * ii. The lowest that satisfies condition (i) - optimal + */ + for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { + temp = device_timings[i]->max_freq; + if ((temp >= freq) && (temp <= freq_nearest)) { + freq_nearest = temp; + timings = device_timings[i]; + } + } + debug("emif: timings table: %d\n", freq_nearest); + return timings; +} + +/* + * Finds the value of emif_sdram_config_reg + * All parameters are programmed based on the device on CS0. + * If there is a device on CS1, it will be same as that on CS0 or + * it will be NVM. We don't support NVM yet. + * If cs1_device pointer is NULL it is assumed that there is no device + * on CS1 + */ +static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, + const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 RL) +{ + u32 config_reg = 0; + + config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; + config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << + EMIF_REG_IBANK_POS_SHIFT; + + config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; + + config_reg |= RL << EMIF_REG_CL_SHIFT; + + config_reg |= addressing->row_sz[cs0_device->io_width] << + EMIF_REG_ROWSIZE_SHIFT; + + config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; + + config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << + EMIF_REG_EBANK_SHIFT; + + config_reg |= addressing->col_sz[cs0_device->io_width] << + EMIF_REG_PAGESIZE_SHIFT; + + return config_reg; +} + +static u32 get_sdram_ref_ctrl(u32 freq, + const struct lpddr2_addressing *addressing) +{ + u32 ref_ctrl = 0, val = 0, freq_khz; + freq_khz = freq / 1000; + /* + * refresh rate to be set is 'tREFI * freq in MHz + * division by 10000 to account for khz and x10 in t_REFI_us_x10 + */ + val = addressing->t_REFI_us_x10 * freq_khz / 10000; + ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; + + return ref_ctrl; +} + +static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim1 = 0, val = 0; + val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; + tim1 |= val << EMIF_REG_T_WTR_SHIFT; + + if (addressing->num_banks == BANKS8) + val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / + (4 * (*T_num)) - 1; + else + val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; + + tim1 |= val << EMIF_REG_T_RRD_SHIFT; + + val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; + tim1 |= val << EMIF_REG_T_RC_SHIFT; + + val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; + tim1 |= val << EMIF_REG_T_RAS_SHIFT; + + val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; + tim1 |= val << EMIF_REG_T_WR_SHIFT; + + val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; + tim1 |= val << EMIF_REG_T_RCD_SHIFT; + + val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; + tim1 |= val << EMIF_REG_T_RP_SHIFT; + + return tim1; +} + +static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck) +{ + u32 tim2 = 0, val = 0; + val = max(min_tck->tCKE, timings->tCKE) - 1; + tim2 |= val << EMIF_REG_T_CKE_SHIFT; + + val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; + tim2 |= val << EMIF_REG_T_RTP_SHIFT; + + /* + * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the + * same value + */ + val = ns_2_cycles(timings->tXSR) - 1; + tim2 |= val << EMIF_REG_T_XSRD_SHIFT; + tim2 |= val << EMIF_REG_T_XSNR_SHIFT; + + val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; + tim2 |= val << EMIF_REG_T_XP_SHIFT; + + return tim2; +} + +static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim3 = 0, val = 0; + val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); + tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; + + val = ns_2_cycles(timings->tRFCab) - 1; + tim3 |= val << EMIF_REG_T_RFC_SHIFT; + + val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; + tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; + + val = ns_2_cycles(timings->tZQCS) - 1; + tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; + + val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; + tim3 |= val << EMIF_REG_T_CKESR_SHIFT; + + return tim3; +} + +static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 volt_ramp) +{ + u32 zq = 0, val = 0; + if (volt_ramp) + val = + EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / + addressing->t_REFI_us_x10; + else + val = + EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / + addressing->t_REFI_us_x10; + zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; + + zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; + + zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; + + zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; + + /* + * Assuming that two chipselects have a single calibration resistor + * If there are indeed two calibration resistors, then this flag should + * be enabled to take advantage of dual calibration feature. + * This data should ideally come from board files. But considering + * that none of the boards today have calibration resistors per CS, + * it would be an unnecessary overhead. + */ + zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; + + zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; + + zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; + + return zq; +} + +static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 is_derated) +{ + u32 alert = 0, interval; + interval = + TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; + if (is_derated) + interval *= 4; + alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; + + alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; + + alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; + + alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; + + alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; + + alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; + + return alert; +} + +static u32 get_read_idle_ctrl_reg(u8 volt_ramp) +{ + u32 idle = 0, val = 0; + if (volt_ramp) + val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; + else + /*Maximum value in normal conditions - suggested by hw team */ + val = 0x1FF; + idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; + + idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; + + return idle; +} + +static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) +{ + u32 phy = 0, val = 0; + + phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; + + if (freq <= 100000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; + else if (freq <= 200000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; + else + val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; + phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; + + /* Other fields are constant magic values. Hardcode them together */ + phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << + EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; + + return phy; +} + +static u32 get_emif_mem_size(u32 base) +{ + u32 size_mbytes = 0, temp; + struct emif_device_details dev_details; + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + u32 emif_nr = emif_num(base); + + emif_reset_phy(base); + dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, + &cs0_dev_details); + dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, + &cs1_dev_details); + emif_reset_phy(base); + + if (dev_details.cs0_device_details) { + temp = dev_details.cs0_device_details->density; + size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; + } + + if (dev_details.cs1_device_details) { + temp = dev_details.cs1_device_details->density; + size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; + } + /* convert to bytes */ + return size_mbytes << 20; +} + +/* Gets the encoding corresponding to a given DMM section size */ +u32 get_dmm_section_size_map(u32 section_size) +{ + /* + * Section size mapping: + * 0x0: 16-MiB section + * 0x1: 32-MiB section + * 0x2: 64-MiB section + * 0x3: 128-MiB section + * 0x4: 256-MiB section + * 0x5: 512-MiB section + * 0x6: 1-GiB section + * 0x7: 2-GiB section + */ + section_size >>= 24; /* divide by 16 MB */ + return log_2_n_round_down(section_size); +} + +static void emif_calculate_regs( + const struct emif_device_details *emif_dev_details, + u32 freq, struct emif_regs *regs) +{ + u32 temp, sys_freq; + const struct lpddr2_addressing *addressing; + const struct lpddr2_ac_timings *timings; + const struct lpddr2_min_tck *min_tck; + const struct lpddr2_device_details *cs0_dev_details = + emif_dev_details->cs0_device_details; + const struct lpddr2_device_details *cs1_dev_details = + emif_dev_details->cs1_device_details; + const struct lpddr2_device_timings *cs0_dev_timings = + emif_dev_details->cs0_device_timings; + + emif_assert(emif_dev_details); + emif_assert(regs); + /* + * You can not have a device on CS1 without one on CS0 + * So configuring EMIF without a device on CS0 doesn't + * make sense + */ + emif_assert(cs0_dev_details); + emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); + /* + * If there is a device on CS1 it should be same type as CS0 + * (or NVM. But NVM is not supported in this driver yet) + */ + emif_assert((cs1_dev_details == NULL) || + (cs1_dev_details->type == LPDDR2_TYPE_NVM) || + (cs0_dev_details->type == cs1_dev_details->type)); + emif_assert(freq <= MAX_LPDDR2_FREQ); + + set_ddr_clk_period(freq); + + /* + * The device on CS0 is used for all timing calculations + * There is only one set of registers for timings per EMIF. So, if the + * second CS(CS1) has a device, it should have the same timings as the + * device on CS0 + */ + timings = get_timings_table(cs0_dev_timings->ac_timings, freq); + emif_assert(timings); + min_tck = cs0_dev_timings->min_tck; + + temp = addressing_table_index(cs0_dev_details->type, + cs0_dev_details->density, + cs0_dev_details->io_width); + + emif_assert((temp >= 0)); + addressing = &(addressing_table[temp]); + emif_assert(addressing); + + sys_freq = get_sys_clk_freq(); + + regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, + cs1_dev_details, + addressing, RL_BOOT); + + regs->sdram_config = get_sdram_config_reg(cs0_dev_details, + cs1_dev_details, + addressing, RL_FINAL); + + regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); + + regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); + + regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); + + regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); + + regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); + + regs->temp_alert_config = + get_temp_alert_config(cs1_dev_details, addressing, 0); + + regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, + LPDDR2_VOLTAGE_STABLE); + + regs->emif_ddr_phy_ctlr_1_init = + get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); + + regs->emif_ddr_phy_ctlr_1 = + get_ddr_phy_ctrl_1(freq, RL_FINAL); + + regs->freq = freq; + + print_timing_reg(regs->sdram_config_init); + print_timing_reg(regs->sdram_config); + print_timing_reg(regs->ref_ctrl); + print_timing_reg(regs->sdram_tim1); + print_timing_reg(regs->sdram_tim2); + print_timing_reg(regs->sdram_tim3); + print_timing_reg(regs->read_idle_ctrl); + print_timing_reg(regs->temp_alert_config); + print_timing_reg(regs->zq_config); + print_timing_reg(regs->emif_ddr_phy_ctlr_1); + print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); +} +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +const char *get_lpddr2_type(u8 type_id) +{ + switch (type_id) { + case LPDDR2_TYPE_S4: + return "LPDDR2-S4"; + case LPDDR2_TYPE_S2: + return "LPDDR2-S2"; + default: + return NULL; + } +} + +const char *get_lpddr2_io_width(u8 width_id) +{ + switch (width_id) { + case LPDDR2_IO_WIDTH_8: + return "x8"; + case LPDDR2_IO_WIDTH_16: + return "x16"; + case LPDDR2_IO_WIDTH_32: + return "x32"; + default: + return NULL; + } +} + +const char *get_lpddr2_manufacturer(u32 manufacturer) +{ + switch (manufacturer) { + case LPDDR2_MANUFACTURER_SAMSUNG: + return "Samsung"; + case LPDDR2_MANUFACTURER_QIMONDA: + return "Qimonda"; + case LPDDR2_MANUFACTURER_ELPIDA: + return "Elpida"; + case LPDDR2_MANUFACTURER_ETRON: + return "Etron"; + case LPDDR2_MANUFACTURER_NANYA: + return "Nanya"; + case LPDDR2_MANUFACTURER_HYNIX: + return "Hynix"; + case LPDDR2_MANUFACTURER_MOSEL: + return "Mosel"; + case LPDDR2_MANUFACTURER_WINBOND: + return "Winbond"; + case LPDDR2_MANUFACTURER_ESMT: + return "ESMT"; + case LPDDR2_MANUFACTURER_SPANSION: + return "Spansion"; + case LPDDR2_MANUFACTURER_SST: + return "SST"; + case LPDDR2_MANUFACTURER_ZMOS: + return "ZMOS"; + case LPDDR2_MANUFACTURER_INTEL: + return "Intel"; + case LPDDR2_MANUFACTURER_NUMONYX: + return "Numonyx"; + case LPDDR2_MANUFACTURER_MICRON: + return "Micron"; + default: + return NULL; + } +} + +static void display_sdram_details(u32 emif_nr, u32 cs, + struct lpddr2_device_details *device) +{ + const char *mfg_str; + const char *type_str; + char density_str[10]; + u32 density; + + debug("EMIF%d CS%d\t", emif_nr, cs); + + if (!device) { + debug("None\n"); + return; + } + + mfg_str = get_lpddr2_manufacturer(device->manufacturer); + type_str = get_lpddr2_type(device->type); + + density = lpddr2_density_2_size_in_mbytes[device->density]; + if ((density / 1024 * 1024) == density) { + density /= 1024; + sprintf(density_str, "%d GB", density); + } else + sprintf(density_str, "%d MB", density); + if (mfg_str && type_str) + debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); +} + +static u8 is_lpddr2_sdram_present(u32 base, u32 cs, + struct lpddr2_device_details *lpddr2_device) +{ + u32 mr = 0, temp; + + mr = get_mr(base, cs, LPDDR2_MR0); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; + if (temp) { + /* Not SDRAM */ + return 0; + } + temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; + + if (temp) { + /* DNV supported - But DNV is only supported for NVM */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR4); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR5); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + if (!get_lpddr2_manufacturer(mr)) { + /* Manufacturer not identified */ + return 0; + } + lpddr2_device->manufacturer = mr; + + mr = get_mr(base, cs, LPDDR2_MR6); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR7); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR8); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; + if (!get_lpddr2_type(temp)) { + /* Not SDRAM */ + return 0; + } + lpddr2_device->type = temp; + + temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; + if (temp > LPDDR2_DENSITY_32Gb) { + /* Density not supported */ + return 0; + } + lpddr2_device->density = temp; + + temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; + if (!get_lpddr2_io_width(temp)) { + /* IO width unsupported value */ + return 0; + } + lpddr2_device->io_width = temp; + + /* + * If all the above tests pass we should + * have a device on this chip-select + */ + return 1; +} + +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) +{ + u32 phy; + u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (!lpddr2_dev_details) + return NULL; + + /* Do the minimum init for mode register accesses */ + if (!(running_from_sdram() || warm_reset())) { + phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); + writel(phy, &emif->emif_ddr_phy_ctrl_1); + } + + if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) + return NULL; + + display_sdram_details(emif_num(base), cs, lpddr2_dev_details); + + return lpddr2_dev_details; +} +#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ + +static void do_sdram_init(u32 base) +{ + const struct emif_regs *regs; + u32 in_sdram, emif_nr; + + debug(">>do_sdram_init() %x\n", base); + + in_sdram = running_from_sdram(); + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_reg_dump(emif_nr, ®s); + if (!regs) { + debug("EMIF: reg dump not provided\n"); + return; + } +#else + /* + * The user has not provided the register values. We need to + * calculate it based on the timings and the DDR frequency + */ + struct emif_device_details dev_details; + struct emif_regs calculated_regs; + + /* + * Get device details: + * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set + * - Obtained from user otherwise + */ + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + emif_reset_phy(base); + dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, + &cs0_dev_details); + dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, + &cs1_dev_details); + emif_reset_phy(base); + + /* Return if no devices on this EMIF */ + if (!dev_details.cs0_device_details && + !dev_details.cs1_device_details) { + return; + } + + /* + * Get device timings: + * - Default timings specified by JESD209-2 if + * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set + * - Obtained from user otherwise + */ + emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, + &dev_details.cs1_device_timings); + + /* Calculate the register values */ + emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); + regs = &calculated_regs; +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + + /* + * Initializing the DDR device can not happen from SDRAM. + * Changing the timing registers in EMIF can happen(going from one + * OPP to another) + */ + if (!in_sdram && (!warm_reset() || is_dra7xx())) { + if (emif_sdram_type(regs->sdram_config) == + EMIF_SDRAM_TYPE_LPDDR2) + lpddr2_init(base, regs); +#ifndef CONFIG_OMAP44XX + else + ddr3_init(base, regs); +#endif + } +#ifdef CONFIG_OMAP54X + if (warm_reset() && (emif_sdram_type(regs->sdram_config) == + EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { + set_lpmode_selfrefresh(base); + emif_reset_phy(base); + omap5_ddr3_leveling(base, regs); + } +#endif + + /* Write to the shadow registers */ + emif_update_timings(base, regs); + + debug("<emif_pwr_mgmt_ctrl); +} + +void dmm_init(u32 base) +{ + const struct dmm_lisa_map_regs *lisa_map_regs; + u32 i, section, valid; + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_dmm_regs(&lisa_map_regs); +#else + u32 emif1_size, emif2_size, mapped_size, section_map = 0; + u32 section_cnt, sys_addr; + struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; + + mapped_size = 0; + section_cnt = 3; + sys_addr = CONFIG_SYS_SDRAM_BASE; + emif1_size = get_emif_mem_size(EMIF1_BASE); + emif2_size = get_emif_mem_size(EMIF2_BASE); + debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); + + if (!emif1_size && !emif2_size) + return; + + /* symmetric interleaved section */ + if (emif1_size && emif2_size) { + mapped_size = min(emif1_size, emif2_size); + section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; + section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= (sys_addr >> 24) << + EMIF_SYS_ADDR_SHIFT; + section_map |= get_dmm_section_size_map(mapped_size * 2) + << EMIF_SYS_SIZE_SHIFT; + lis_map_regs_calculated.dmm_lisa_map_3 = section_map; + emif1_size -= mapped_size; + emif2_size -= mapped_size; + sys_addr += (mapped_size * 2); + section_cnt--; + } + + /* + * Single EMIF section(we can have a maximum of 1 single EMIF + * section- either EMIF1 or EMIF2 or none, but not both) + */ + if (emif1_size) { + section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; + section_map |= get_dmm_section_size_map(emif1_size) + << EMIF_SYS_SIZE_SHIFT; + /* only MSB */ + section_map |= (mapped_size >> 24) << + EMIF_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; + section_cnt--; + } + if (emif2_size) { + section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; + section_map |= get_dmm_section_size_map(emif2_size) << + EMIF_SYS_SIZE_SHIFT; + /* only MSB */ + section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; + section_cnt--; + } + + if (section_cnt == 2) { + /* Only 1 section - either symmetric or single EMIF */ + lis_map_regs_calculated.dmm_lisa_map_3 = section_map; + lis_map_regs_calculated.dmm_lisa_map_2 = 0; + lis_map_regs_calculated.dmm_lisa_map_1 = 0; + } else { + /* 2 sections - 1 symmetric, 1 single EMIF */ + lis_map_regs_calculated.dmm_lisa_map_2 = section_map; + lis_map_regs_calculated.dmm_lisa_map_1 = 0; + } + + /* TRAP for invalid TILER mappings in section 0 */ + lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; + + if (omap_revision() >= OMAP4460_ES1_0) + lis_map_regs_calculated.is_ma_present = 1; + + lisa_map_regs = &lis_map_regs_calculated; +#endif + struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)base; + + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); + + if (lisa_map_regs->is_ma_present) { + hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)MA_BASE; + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); + + setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); + } + + /* + * EMIF should be configured only when + * memory is mapped on it. Using emif1_enabled + * and emif2_enabled variables for this. + */ + emif1_enabled = 0; + emif2_enabled = 0; + for (i = 0; i < 4; i++) { + section = __raw_readl(DMM_BASE + i*4); + valid = (section & EMIF_SDRC_MAP_MASK) >> + (EMIF_SDRC_MAP_SHIFT); + if (valid == 3) { + emif1_enabled = 1; + emif2_enabled = 1; + break; + } + + if (valid == 1) + emif1_enabled = 1; + + if (valid == 2) + emif2_enabled = 1; + } +} + +static void do_bug0039_workaround(u32 base) +{ + u32 val, i, clkctrl; + struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; + const struct read_write_regs *bug_00339_regs; + u32 iterations; + u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; + u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; + + if (is_dra7xx()) + phy_status_base++; + + bug_00339_regs = get_bug_regs(&iterations); + + /* Put EMIF in to idle */ + clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); + __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); + + /* Copy the phy status registers in to phy ctrl shadow registers */ + for (i = 0; i < iterations; i++) { + val = __raw_readl(phy_status_base + + bug_00339_regs[i].read_reg - 1); + + __raw_writel(val, phy_ctrl_base + + ((bug_00339_regs[i].write_reg - 1) << 1)); + + __raw_writel(val, phy_ctrl_base + + (bug_00339_regs[i].write_reg << 1) - 1); + } + + /* Disable leveling */ + writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); + + __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); +} + +/* + * SDRAM initialization: + * SDRAM initialization has two parts: + * 1. Configuring the SDRAM device + * 2. Update the AC timings related parameters in the EMIF module + * (1) should be done only once and should not be done while we are + * running from SDRAM. + * (2) can and should be done more than once if OPP changes. + * Particularly, this may be needed when we boot without SPL and + * and using Configuration Header(CH). ROM code supports only at 50% OPP + * at boot (low power boot). So u-boot has to switch to OPP100 and update + * the frequency. So, + * Doing (1) and (2) makes sense - first time initialization + * Doing (2) and not (1) makes sense - OPP change (when using CH) + * Doing (1) and not (2) doen't make sense + * See do_sdram_init() for the details + */ +void sdram_init(void) +{ + u32 in_sdram, size_prog, size_detect; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); + + debug(">>sdram_init()\n"); + + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + in_sdram = running_from_sdram(); + debug("in_sdram = %d\n", in_sdram); + + if (!in_sdram) { + if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) + bypass_dpll((*prcm)->cm_clkmode_dpll_core); + else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) + writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); + } + + if (!in_sdram) + dmm_init(DMM_BASE); + + if (emif1_enabled) + do_sdram_init(EMIF1_BASE); + + if (emif2_enabled) + do_sdram_init(EMIF2_BASE); + + if (!(in_sdram || warm_reset())) { + if (emif1_enabled) + emif_post_init_config(EMIF1_BASE); + if (emif2_enabled) + emif_post_init_config(EMIF2_BASE); + } + + /* for the shadow registers to take effect */ + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) + freq_update_core(); + + /* Do some testing after the init */ + if (!in_sdram) { + size_prog = omap_sdram_size(); + size_prog = log_2_n_round_down(size_prog); + size_prog = (1 << size_prog); + + size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_prog); + /* Compare with the size programmed */ + if (size_detect != size_prog) { + printf("SDRAM: identified size not same as expected" + " size identified: %x expected: %x\n", + size_detect, + size_prog); + } else + debug("get_ram_size() successful"); + } + +#if defined(CONFIG_TI_SECURE_DEVICE) + /* + * On HS devices, do static EMIF firewall configuration + * but only do it if not already running in SDRAM + */ + if (!in_sdram) + if (0 != secure_emif_reserve()) + hang(); + + /* On HS devices, ensure static EMIF firewall APIs are locked */ + if (0 != secure_emif_firewall_lock()) + hang(); +#endif + + if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && + (!in_sdram && !warm_reset()) && (!is_dra7xx())) { + if (emif1_enabled) + do_bug0039_workaround(EMIF1_BASE); + if (emif2_enabled) + do_bug0039_workaround(EMIF2_BASE); + } + + debug("< + * + * Author : + * Aneesh V + * Steve Sakoman + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *) array; + + for (i = 0; i < size; i++, pad++) + writew(pad->val, base + pad->offset); +} + +static void set_mux_conf_regs(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + set_muxconf_regs(); + break; + case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: + break; + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + set_muxconf_regs(); + break; + } +} + +u32 cortex_rev(void) +{ + + unsigned int rev; + + /* Read Main ID Register (MIDR) */ + asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); + + return rev; +} + +static void omap_rev_string(void) +{ + u32 omap_rev = omap_revision(); + u32 soc_variant = (omap_rev & 0xF0000000) >> 28; + u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; + u32 major_rev = (omap_rev & 0x00000F00) >> 8; + u32 minor_rev = (omap_rev & 0x000000F0) >> 4; + + const char *sec_s; + + switch (get_device_type()) { + case TST_DEVICE: + sec_s = "TST"; + break; + case EMU_DEVICE: + sec_s = "EMU"; + break; + case HS_DEVICE: + sec_s = "HS"; + break; + case GP_DEVICE: + sec_s = "GP"; + break; + default: + sec_s = "?"; + } + + if (soc_variant) + printf("OMAP"); + else + printf("DRA"); + printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); +} + +#ifdef CONFIG_SPL_BUILD +void spl_display_print(void) +{ + omap_rev_string(); +} +#endif + +void __weak srcomp_enable(void) +{ +} + +/** + * do_board_detect() - Detect board description + * + * Function to detect board description. This is expected to be + * overridden in the SoC family board file where desired. + */ +void __weak do_board_detect(void) +{ +} + +/** + * vcores_init() - Assign omap_vcores based on board + * + * Function to pick the vcores based on board. This is expected to be + * overridden in the SoC family board file where desired. + */ +void __weak vcores_init(void) +{ +} + +void s_init(void) +{ +} + +/** + * early_system_init - Does Early system initialization. + * + * Does early system init of watchdog, muxing, andclocks + * Watchdog disable is done always. For the rest what gets done + * depends on the boot mode in which this function is executed when + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. U-Boot loaded to SDRAM by SPL + * 4. U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * Please have a look at the respective functions to see what gets + * done in each of these cases + * This function is called with SRAM stack. + */ +void early_system_init(void) +{ + init_omap_revision(); + hw_data_init(); + +#ifdef CONFIG_SPL_BUILD + if (warm_reset()) + force_emif_self_refresh(); +#endif + watchdog_init(); + set_mux_conf_regs(); +#ifdef CONFIG_SPL_BUILD + srcomp_enable(); + do_io_settings(); +#endif + setup_early_clocks(); + do_board_detect(); + vcores_init(); + prcm_init(); +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + early_system_init(); +#ifdef CONFIG_BOARD_EARLY_INIT_F + board_early_init_f(); +#endif + /* For regular u-boot sdram_init() is called from dram_init() */ + sdram_init(); +} +#endif + +int arch_cpu_init_dm(void) +{ + early_system_init(); + return 0; +} + +/* + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + */ +void wait_for_command_complete(struct watchdog *wd_base) +{ + int pending = 1; + do { + pending = readl(&wd_base->wwps); + } while (pending); +} + +/* + * Routine: watchdog_init + * Description: Shut down watch dogs + */ +void watchdog_init(void) +{ + struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; + + writel(WD_UNLOCK1, &wd2_base->wspr); + wait_for_command_complete(wd2_base); + writel(WD_UNLOCK2, &wd2_base->wspr); +} + + +/* + * This function finds the SDRAM size available in the system + * based on DMM section configurations + * This is needed because the size of memory installed may be + * different on different versions of the board + */ +u32 omap_sdram_size(void) +{ + u32 section, i, valid; + u64 sdram_start = 0, sdram_end = 0, addr, + size, total_size = 0, trap_size = 0, trap_start = 0; + + for (i = 0; i < 4; i++) { + section = __raw_readl(DMM_BASE + i*4); + valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> + (EMIF_SDRC_ADDRSPC_SHIFT); + addr = section & EMIF_SYS_ADDR_MASK; + + /* See if the address is valid */ + if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { + size = ((section & EMIF_SYS_SIZE_MASK) >> + EMIF_SYS_SIZE_SHIFT); + size = 1 << size; + size *= SZ_16M; + + if (valid != DMM_SDRC_ADDR_SPC_INVALID) { + if (!sdram_start || (addr < sdram_start)) + sdram_start = addr; + if (!sdram_end || ((addr + size) > sdram_end)) + sdram_end = addr + size; + } else { + trap_size = size; + trap_start = addr; + } + } + } + + if ((trap_start >= sdram_start) && (trap_start < sdram_end)) + total_size = (sdram_end - sdram_start) - (trap_size); + else + total_size = sdram_end - sdram_start; + + return total_size; +} + + +/* + * Routine: dram_init + * Description: sets uboots idea of sdram size + */ +int dram_init(void) +{ + sdram_init(); + gd->ram_size = omap_sdram_size(); + return 0; +} + +/* + * Print board information + */ +int checkboard(void) +{ + puts(sysinfo.board_string); + return 0; +} + +/* + * get_device_type(): tell if GP/HS/EMU/TST + */ +u32 get_device_type(void) +{ + return (readl((*ctrl)->control_status) & + (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : "); + omap_rev_string(); + + return 0; +} +#endif diff --git a/arch/arm/mach-omap2/lowlevel_init.S b/arch/arm/mach-omap2/lowlevel_init.S new file mode 100644 index 00000000000..8ce12c8e9ae --- /dev/null +++ b/arch/arm/mach-omap2/lowlevel_init.S @@ -0,0 +1,90 @@ +/* + * Board specific setup info + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +.arch_extension sec + +#ifdef CONFIG_SPL +ENTRY(save_boot_params) + ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS + str r0, [r1] + b save_boot_params_ret +ENDPROC(save_boot_params) + +#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) +ENTRY(switch_to_hypervisor) + +/* + * Switch to hypervisor mode + */ + adr r0, save_sp + str sp, [r0] + adr r1, restore_from_hyp + ldr r0, =0x102 + b omap_smc1 +restore_from_hyp: + adr r0, save_sp + ldr sp, [r0] + MRC p15, 4, R0, c1, c0, 0 + ldr r1, =0X1004 @Set cache enable bits for hypervisor mode + orr r0, r0, r1 + MCR p15, 4, R0, c1, c0, 0 + b switch_to_hypervisor_ret +save_sp: + .word 0x0 +ENDPROC(switch_to_hypervisor) +#endif +#endif + +ENTRY(omap_smc1) + push {r4-r12, lr} @ save registers - ROM code may pollute + @ our registers + mov r12, r0 @ Service + mov r0, r1 @ Argument + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + @ call ROM Code API for the service requested + pop {r4-r12, pc} +ENDPROC(omap_smc1) + +ENTRY(omap_smc_sec) + push {r4-r12, lr} @ save registers - ROM code may pollute + @ our registers + mov r6, #0xFF @ Indicate new Task call + mov r12, #0x00 @ Secure Service ID in R12 + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + + b omap_smc_sec_end @ exit at end of the service execution + nop + + @ In case of IRQ happening in Secure, then ARM will branch here. + @ At that moment, IRQ will be pending and ARM will jump to Non Secure + @ IRQ handler + mov r12, #0xFE + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + +omap_smc_sec_end: + pop {r4-r12, pc} +ENDPROC(omap_smc_sec) diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c new file mode 100644 index 00000000000..d72e82e0283 --- /dev/null +++ b/arch/arm/mach-omap2/mem-common.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Mansoor Ahamed + * + * Initial Code from: + * Manikandan Pillai + * Richard Woodruff + * Syed Mohammed Khasim + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; + +#if defined(CONFIG_NOR) +char gpmc_cs0_flash = MTD_DEV_TYPE_NOR; +#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) +char gpmc_cs0_flash = MTD_DEV_TYPE_NAND; +#elif defined(CONFIG_CMD_ONENAND) +char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; +#else +char gpmc_cs0_flash = -1; +#endif + +#if defined(CONFIG_OMAP34XX) +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(u32 cs) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); + + writel(0x0, addr + 0x400); /* clear pos A */ + writel(pattern, addr); /* pattern to pos B */ + writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = readl(addr + 0x400); /* get pos A value */ + val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ + return 0; + else + return 1; +} +#endif + +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, + u32 base, u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + +void set_gpmc_cs0(int flash_type) +{ + const u32 *gpmc_regs; + u32 base, size; +#if defined(CONFIG_NOR) + const u32 gpmc_regs_nor[GPMC_MAX_REG] = { + STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; +#endif +#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) + const u32 gpmc_regs_nand[GPMC_MAX_REG] = { + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; +#endif +#if defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, + 0 + }; +#endif + + switch (flash_type) { +#if defined(CONFIG_NOR) + case MTD_DEV_TYPE_NOR: + gpmc_regs = gpmc_regs_nor; + base = CONFIG_SYS_FLASH_BASE; + size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + GPMC_SIZE_16M))); + break; +#endif +#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) + case MTD_DEV_TYPE_NAND: + gpmc_regs = gpmc_regs_nand; + base = CONFIG_SYS_NAND_BASE; + size = GPMC_SIZE_16M; + break; +#endif +#if defined(CONFIG_CMD_ONENAND) + case MTD_DEV_TYPE_ONENAND: + gpmc_regs = gpmc_regs_onenand; + base = CONFIG_SYS_ONENAND_BASE; + size = GPMC_SIZE_128M; + break; +#endif + default: + /* disable the GPMC0 config set by ROM code */ + writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + return; + } + + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + /* global settings */ + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); + /* disable timeout, set a safe reset value */ + writel(0x00001ff0, &gpmc_cfg->timeout_control); + writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ? + 0x00000200 : 0x00000012, &gpmc_cfg->config); + + set_gpmc_cs0(gpmc_cs0_flash); +} diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c new file mode 100644 index 00000000000..b37163a4f3e --- /dev/null +++ b/arch/arm/mach-omap2/omap-cache.c @@ -0,0 +1,77 @@ +/* + * + * Common functions for OMAP4/5 based boards + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Without LPAE short descriptors are used + * Set C - Cache Bit3 + * Set B - Buffer Bit2 + * The last 2 bits set to 0b10 + * Do Not set XN bit4 + * So value is 0xe + * + * With LPAE cache configuration happens via MAIR0 register + * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. + * 0xFF maps to Cache writeback with Read and Write Allocate set + * The bits[1:0] should have the value 0b01 for the first level + * descriptor. + * So the value is 0xd + */ + +#ifdef CONFIG_ARMV7_LPAE +#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC +#else +#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK +#endif + +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_POLICY); +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig new file mode 100644 index 00000000000..7d884a237bb --- /dev/null +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -0,0 +1,154 @@ +if OMAP34XX + +config SPL_EXT_SUPPORT + default y + +config SPL_FAT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_NAND_SUPPORT + default y + +config SPL_POWER_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + +choice + prompt "OMAP3 board select" + optional + +config TARGET_AM3517_EVM + bool "AM3517 EVM" + +config TARGET_MT_VENTOUX + bool "TeeJet Mt.Ventoux" + +config TARGET_OMAP3_BEAGLE + bool "TI OMAP3 BeagleBoard" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_CM_T35 + bool "CompuLab CM-T3530 and CM-T3730 boards" + +config TARGET_CM_T3517 + bool "CompuLab CM-T3517 boards" + +config TARGET_DEVKIT8000 + bool "TimLL OMAP3 Devkit8000" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_OMAP3_EVM + bool "TI OMAP3 EVM" + +config TARGET_OMAP3_IGEP00X0 + bool "IGEP" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_OMAP3_OVERO + bool "OMAP35xx Gumstix Overo" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_OMAP3_ZOOM1 + bool "TI Zoom1" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_AM3517_CRANE + bool "am3517_crane" + +config TARGET_OMAP3_PANDORA + bool "OMAP3 Pandora" + +config TARGET_ECO5PK + bool "ECO5PK" + +config TARGET_TRICORDER + bool "Tricorder" + +config TARGET_MCX + bool "MCX" + +config TARGET_OMAP3_LOGIC + bool "OMAP3 Logic" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_NOKIA_RX51 + bool "Nokia RX51" + +config TARGET_TAO3530 + bool "TAO3530" + +config TARGET_TWISTER + bool "Twister" + +config TARGET_OMAP3_CAIRO + bool "QUIPOS CAIRO" + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_SNIPER + bool "LG Optimus Black" + select DM + select DM_SERIAL + select DM_GPIO + +endchoice + +config SYS_SOC + default "omap3" + +source "board/logicpd/am3517evm/Kconfig" +source "board/teejet/mt_ventoux/Kconfig" +source "board/ti/beagle/Kconfig" +source "board/compulab/cm_t35/Kconfig" +source "board/compulab/cm_t3517/Kconfig" +source "board/timll/devkit8000/Kconfig" +source "board/ti/evm/Kconfig" +source "board/isee/igep00x0/Kconfig" +source "board/overo/Kconfig" +source "board/logicpd/zoom1/Kconfig" +source "board/ti/am3517crane/Kconfig" +source "board/pandora/Kconfig" +source "board/8dtech/eco5pk/Kconfig" +source "board/corscience/tricorder/Kconfig" +source "board/htkw/mcx/Kconfig" +source "board/logicpd/omap3som/Kconfig" +source "board/nokia/rx51/Kconfig" +source "board/technexion/tao3530/Kconfig" +source "board/technexion/twister/Kconfig" +source "board/quipos/cairo/Kconfig" +source "board/lg/sniper/Kconfig" + +endif diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile new file mode 100644 index 00000000000..b2fce966d9a --- /dev/null +++ b/arch/arm/mach-omap2/omap3/Makefile @@ -0,0 +1,21 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := lowlevel_init.o + +obj-y += board.o +obj-y += boot.o +obj-y += clock.o +obj-y += sys_info.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o +endif + +obj-$(CONFIG_DRIVER_TI_EMAC) += emac.o +obj-$(CONFIG_EMIF4) += emif4.o +obj-$(CONFIG_SDRC) += sdrc.o +obj-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o diff --git a/arch/arm/mach-omap2/omap3/am35x_musb.c b/arch/arm/mach-omap2/omap3/am35x_musb.c new file mode 100644 index 00000000000..74dd105eb6f --- /dev/null +++ b/arch/arm/mach-omap2/omap3/am35x_musb.c @@ -0,0 +1,61 @@ +/* + * This file configures the internal USB PHY in AM35X. + * + * Copyright (C) 2012 Ilya Yanok + * + * Based on omap_phy_internal.c code from Linux by + * Hema HK + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void am35x_musb_reset(void) +{ + /* Reset the musb interface */ + clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, + 0, USBOTGSS_SW_RST); + clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, + USBOTGSS_SW_RST, 0); +} + +void am35x_musb_phy_power(u8 on) +{ + unsigned long start = get_timer(0); + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN, + CONF2_PHY_PLLON); + + debug("Waiting for PHY clock good...\n"); + while (!(readl(&am35x_scm_general_regs->devconf2) + & CONF2_PHYCLKGD)) { + + if (get_timer(start) > CONFIG_SYS_HZ / 10) { + printf("musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_PHY_PLLON, + CONF2_PHYPWRDN | CONF2_OTGPWRDN); + } +} + +void am35x_musb_clear_irq(void) +{ + clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, + 0, USBOTGSS_INT_CLR); + readl(&am35x_scm_general_regs->lvl_intr_clr); +} diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c new file mode 100644 index 00000000000..5f5597772b6 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/board.c @@ -0,0 +1,434 @@ +/* + * + * Common board functions for OMAP3 based boards. + * + * (C) Copyright 2004-2008 + * Texas Instruments, + * + * Author : + * Sunil Kumar + * Shashi Ranjan + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff + * Syed Mohammed Khasim + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Declarations */ +extern omap3_sysinfo sysinfo; +#ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_invalidate_l2_cache_secure(void); +#endif + +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata omap34xx_gpio[] = { + { 0, OMAP34XX_GPIO1_BASE }, + { 1, OMAP34XX_GPIO2_BASE }, + { 2, OMAP34XX_GPIO3_BASE }, + { 3, OMAP34XX_GPIO4_BASE }, + { 4, OMAP34XX_GPIO5_BASE }, + { 5, OMAP34XX_GPIO6_BASE }, +}; + +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &omap34xx_gpio[0] }, + { "gpio_omap", &omap34xx_gpio[1] }, + { "gpio_omap", &omap34xx_gpio[2] }, + { "gpio_omap", &omap34xx_gpio[3] }, + { "gpio_omap", &omap34xx_gpio[4] }, + { "gpio_omap", &omap34xx_gpio[5] }, +}; + +#else + +static const struct gpio_bank gpio_bank_34xx[6] = { + { (void *)OMAP34XX_GPIO1_BASE }, + { (void *)OMAP34XX_GPIO2_BASE }, + { (void *)OMAP34XX_GPIO3_BASE }, + { (void *)OMAP34XX_GPIO4_BASE }, + { (void *)OMAP34XX_GPIO5_BASE }, + { (void *)OMAP34XX_GPIO6_BASE }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; + +#endif + +/****************************************************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************************************************/ +void secure_unlock_mem(void) +{ + struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; + struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; + struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; + struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; + struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE; + + /* Protection Module Register Target APE (PM_RT) */ + writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); + writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); + writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); + writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); + + writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); + writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); + writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); + + writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); + writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); + writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); + writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2); + + /* IVA Changes */ + writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); + writel(UNLOCK_3, &pm_iva2_base->read_permission_0); + writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0); + + /* SDRC region 0 public */ + writel(UNLOCK_1, &sms_base->rg_att0); +} + +/****************************************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + *****************************************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configure non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* + * allow allocation of locked TLBs and L2 lines in NS world + * allow use of PLE registers in NS world also + */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); + + /* Enable ASA in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); +} + +/****************************************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + *****************************************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = is_running_in_sdram(); + + /* + * if GP device unlock device SRAM for general use + * secure code breaks for Secure/Emulation device - HS/E/T + */ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock_mem(); + + /* + * If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + * + * Assuming memories are unlocked by the demon who put us in SDRAM + */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/****************************************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + *****************************************************************************/ +void s_init(void) +{ + watchdog_init(); + + try_unlock_memory(); + +#ifndef CONFIG_SYS_L2CACHE_OFF + /* Invalidate L2-cache from secure mode */ + omap3_invalidate_l2_cache_secure(); +#endif + + set_muxconf_regs(); + sdelay(100); + + prcm_init(); + + per_clocks_enable(); + +#ifdef CONFIG_USB_EHCI_OMAP + ehci_clocks_enable(); +#endif +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + mem_init(); +} +#endif + +/* + * Routine: misc_init_r + * Description: A basic misc_init_r that just displays the die ID + */ +int __weak misc_init_r(void) +{ + omap_die_id_display(); + + return 0; +} + +/****************************************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + *****************************************************************************/ +static void wait_for_command_complete(struct watchdog *wd_base) +{ + int pending = 1; + do { + pending = readl(&wd_base->wwps); + } while (pending); +} + +/****************************************************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************************************************/ +void watchdog_init(void) +{ + struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* + * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + setbits_le32(&prcm_base->fclken_wkup, 0x20); + setbits_le32(&prcm_base->iclken_wkup, 0x20); + wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); + + writel(WD_UNLOCK1, &wd2_base->wspr); + wait_for_command_complete(wd2_base); + writel(WD_UNLOCK2, &wd2_base->wspr); +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void abort(void) +{ +} + +#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) +/****************************************************************************** + * OMAP3 specific command to switch between NAND HW and SW ecc + *****************************************************************************/ +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2 || argc > 3) + goto usage; + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 2) { + omap_nand_switch_ecc(1, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(1, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(1, 8); + else if (strncmp(argv[2], "bch16", 5) == 0) + omap_nand_switch_ecc(1, 16); + else + goto usage; + } + } else if (strncmp(argv[1], "sw", 2) == 0) { + if (argc == 2) { + omap_nand_switch_ecc(0, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(0, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(0, 8); + else + goto usage; + } + } else { + goto usage; + } + + return 0; + +usage: + printf ("Usage: nandecc %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + nandecc, 3, 1, do_switch_ecc, + "switch OMAP3 NAND ECC calculation algorithm", + "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming" + " and 8-bit/16-bit BCH\n" + " ecc calculation (second parameter may" + " be omitted).\n" + "nandecc sw - Switch to NAND software ecc algorithm." +); + +#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ + +#ifdef CONFIG_DISPLAY_BOARDINFO +/** + * Print board information + */ +int checkboard (void) +{ + char *mem_s ; + + if (is_mem_sdr()) + mem_s = "mSDR"; + else + mem_s = "LPDDR"; + + printf("%s + %s/%s\n", sysinfo.board_string, mem_s, + sysinfo.nand_string); + + return 0; +} +#endif /* CONFIG_DISPLAY_BOARDINFO */ + +static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) +{ + u32 i, num_params = *parameters; + u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; + + /* + * copy the parameters to an un-cached area to avoid coherency + * issues + */ + for (i = 0; i < num_params; i++) { + __raw_writel(*parameters, sram_scratch_space); + parameters++; + sram_scratch_space++; + } + + /* Now make the PPA call */ + do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); +} + +void __weak omap3_set_aux_cr_secure(u32 acr) +{ + struct emu_hal_params emu_romcode_params; + + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = acr; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); +} + +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + /* Write ACR - affects secure banked bits */ + if (get_device_type() == GP_DEVICE) + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); + else + omap3_set_aux_cr_secure(acr); + + /* Write ACR - affects non-secure banked bits - some erratas need it */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + + +#ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); + +} + +/* Invalidate the entire L2 cache from secure mode */ +static void omap3_invalidate_l2_cache_secure(void) +{ + if (get_device_type() == GP_DEVICE) { + omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); + } else { + struct emu_hal_params emu_romcode_params; + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = 0; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, + (u32 *)&emu_romcode_params); + } +} + +void v7_outer_cache_enable(void) +{ + + /* + * Set L2EN + * On some revisions L2EN bit is banked on some revisions it's not + * No harm in setting both banked bits(in fact this is required + * by an erratum) + */ + omap3_update_aux_cr(0x2, 0); +} + +void omap3_outer_cache_disable(void) +{ + /* + * Clear L2EN + * On some revisions L2EN bit is banked on some revisions it's not + * No harm in clearing both banked bits(in fact this is required + * by an erratum) + */ + omap3_update_aux_cr(0, 0x2); +} +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/mach-omap2/omap3/boot.c b/arch/arm/mach-omap2/omap3/boot.c new file mode 100644 index 00000000000..64b242b752b --- /dev/null +++ b/arch/arm/mach-omap2/omap3/boot.c @@ -0,0 +1,104 @@ +/* + * OMAP3 boot + * + * Copyright (C) 2015 Paul Kocialkowski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static u32 boot_devices[] = { + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, +}; + +u32 omap_sys_boot_device(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl(&ctrl_base->status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} + +int omap_reboot_mode(char *mode, unsigned int length) +{ + u32 reboot_mode; + char c; + + if (length < 2) + return -1; + + reboot_mode = readl((u32 *)(OMAP34XX_SCRATCHPAD + + OMAP_REBOOT_REASON_OFFSET)); + + c = (reboot_mode >> 24) & 0xff; + if (c != 'B') + return -1; + + c = (reboot_mode >> 16) & 0xff; + if (c != 'M') + return -1; + + c = reboot_mode & 0xff; + + mode[0] = c; + mode[1] = '\0'; + + return 0; +} + +int omap_reboot_mode_clear(void) +{ + writel(0, (u32 *)(OMAP34XX_SCRATCHPAD + OMAP_REBOOT_REASON_OFFSET)); + + return 0; +} + +int omap_reboot_mode_store(char *mode) +{ + u32 reboot_mode; + + reboot_mode = 'B' << 24 | 'M' << 16 | mode[0]; + + writel(reboot_mode, (u32 *)(OMAP34XX_SCRATCHPAD + + OMAP_REBOOT_REASON_OFFSET)); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c new file mode 100644 index 00000000000..006969e780b --- /dev/null +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -0,0 +1,799 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * + * Author : + * Manikandan Pillai + * + * Derived from Beagle Board and OMAP3 SDP code by + * Richard Woodruff + * Syed Mohammed Khasim + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/****************************************************************************** + * get_sys_clk_speed() - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *****************************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, cdiv, val; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct prm *prm_base = (struct prm *)PRM_BASE; + struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; + struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE; + + val = readl(&prm_base->clksrc_ctrl); + + if (val & SYSCLKDIV_2) + cdiv = 2; + else + cdiv = 1; + + /* enable timer2 */ + val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1; + + /* select sys_clk for GPT1 */ + writel(val, &prcm_base->clksel_wkup); + + /* Enable I and F Clocks for GPT1 */ + val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC; + writel(val, &prcm_base->iclken_wkup); + + val = readl(&prcm_base->fclken_wkup) | EN_GPT1; + writel(val, &prcm_base->fclken_wkup); + + writel(0, &gpt1_base->tldr); /* start counting at 0 */ + writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ + + /* enable 32kHz source, determine sys_clk via gauging */ + + /* start time in 20 cycles */ + start = 20 + readl(&s32k_base->s32k_cr); + + /* dead loop till start time */ + while (readl(&s32k_base->s32k_cr) < start); + + /* get start sys_clk count */ + cstart = readl(&gpt1_base->tcrr); + + /* wait for 40 cycles */ + while (readl(&s32k_base->s32k_cr) < (start + 20)) ; + cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + cdiff *= cdiv; + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return S38_4M; + else if (cdiff > 15200) + return S26M; + else if (cdiff > 13000) + return S24M; + else if (cdiff > 9000) + return S19_2M; + else if (cdiff > 7600) + return S13M; + else + return S12M; +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * input oscillator clock frequency. + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + switch(osc_clk) { + case S38_4M: + *sys_clkin_sel = 4; + break; + case S26M: + *sys_clkin_sel = 3; + break; + case S19_2M: + *sys_clkin_sel = 2; + break; + case S13M: + *sys_clkin_sel = 1; + break; + case S12M: + default: + *sys_clkin_sel = 0; + } +} + +/* + * OMAP34XX/35XX specific functions + */ + +static void dpll3_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_core_dpll_param(); + void (*f_lock_pll) (u32, u32, u32, u32); + int xip_safe, p0, p1, p2, p3; + + xip_safe = is_running_in_sram(); + + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; + + if (xip_safe) { + /* + * CORE DPLL + */ + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_FAST_RELOCK_BYPASS); + wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, + LDELAY); + + /* + * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't + * work. write another value and then default value. + */ + + /* CM_CLKSEL1_EMU[DIV_DPLL3] */ + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x001F0000, (CORE_M3X2 + 1) << 16) ; + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x001F0000, CORE_M3X2 << 16); + + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + clrsetbits_le32(&prcm_base->clksel1_pll, + 0xF8000000, ptr->m2 << 27); + + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x07FF0000, ptr->m << 16); + + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x00007F00, ptr->n << 8); + + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); + + /* SSI */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000F00, CORE_SSI_DIV << 8); + /* FSUSB */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000030, CORE_FUSB_DIV << 4); + /* L4 */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x0000000C, CORE_L4_DIV << 2); + /* L3 */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000003, CORE_L3_DIV); + /* GFX */ + clrsetbits_le32(&prcm_base->clksel_gfx, + 0x00000007, GFX_DIV); + /* RESET MGR */ + clrsetbits_le32(&prcm_base->clksel_wkup, + 0x00000006, WKUP_RSM << 1); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + clrsetbits_le32(&prcm_base->clken_pll, + 0x000000F0, ptr->fsel << 4); + /* LOCK MODE */ + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_LOCK); + + wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, + LDELAY); + } else if (is_running_in_flash()) { + /* + * if running from flash, jump to small relocated code + * area in SRAM. + */ + f_lock_pll = (void *) (SRAM_CLK_CODE); + + p0 = readl(&prcm_base->clken_pll); + clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); + + p1 = readl(&prcm_base->clksel1_pll); + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + clrbits_le32(&p1, 0x00000040); + + p2 = readl(&prcm_base->clksel_core); + /* SSI */ + clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); + /* FSUSB */ + clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); + /* L4 */ + clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); + /* L3 */ + clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); + + p3 = (u32)&prcm_base->idlest_ckgen; + + (*f_lock_pll) (p0, p1, p2, p3); + } +} + +static void dpll4_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_per_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); + + /* + * Errata 1.50 Workaround for OMAP3 ES1.0 only + * If using default divisors, write default divisor + 1 + * and then the actual divisor value + */ + /* M6 */ + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x1F000000, (PER_M6X2 + 1) << 24); + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x1F000000, PER_M6X2 << 24); + /* M5 */ + clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); + clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); + /* M4 */ + clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); + clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); + /* M3 */ + clrsetbits_le32(&prcm_base->clksel_dss, + 0x00001F00, (PER_M3X2 + 1) << 8); + clrsetbits_le32(&prcm_base->clksel_dss, + 0x00001F00, PER_M3X2 << 8); + /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ + clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); + clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); + /* Workaround end */ + + /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */ + clrsetbits_le32(&prcm_base->clksel2_pll, + 0x0007FF00, ptr->m << 8); + + /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ + clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); + + /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */ + clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); + + /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); + wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); +} + +static void dpll5_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_per2_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* PER2 DPLL (DPLL5) */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); + wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); + /* set M2 (usbtll_fck) */ + clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); + /* set m (11-bit multiplier) */ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); + /* set n (7-bit divider)*/ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); + /* FREQSEL */ + clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); + /* lock mode */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); + wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); +} + +static void mpu_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_mpu_dpll_param(); + + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; + + /* MPU DPLL (unlocked already) */ + + /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ + clrsetbits_le32(&prcm_base->clksel2_pll_mpu, + 0x0000001F, ptr->m2); + + /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, + 0x0007FF00, ptr->m << 8); + + /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, + 0x0000007F, ptr->n); + + /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */ + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x000000F0, ptr->fsel << 4); +} + +static void iva_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_iva_dpll_param(); + + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; + + /* IVA DPLL */ + /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ + clrsetbits_le32(&prcm_base->clken_pll_iva2, + 0x00000007, PLL_STOP); + wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); + + /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ + clrsetbits_le32(&prcm_base->clksel2_pll_iva2, + 0x0000001F, ptr->m2); + + /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, + 0x0007FF00, ptr->m << 8); + + /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, + 0x0000007F, ptr->n); + + /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */ + clrsetbits_le32(&prcm_base->clken_pll_iva2, + 0x000000F0, ptr->fsel << 4); + + /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ + clrsetbits_le32(&prcm_base->clken_pll_iva2, + 0x00000007, PLL_LOCK); + + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); +} + +/* + * OMAP3630 specific functions + */ + +static void dpll3_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); + void (*f_lock_pll) (u32, u32, u32, u32); + int xip_safe, p0, p1, p2, p3; + + xip_safe = is_running_in_sram(); + + /* Moving it to the right sysclk base */ + ptr += clk_index; + + if (xip_safe) { + /* CORE DPLL */ + + /* Select relock bypass: CM_CLKEN_PLL[0:2] */ + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_FAST_RELOCK_BYPASS); + wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, + LDELAY); + + /* CM_CLKSEL1_EMU[DIV_DPLL3] */ + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x001F0000, CORE_M3X2 << 16); + + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + clrsetbits_le32(&prcm_base->clksel1_pll, + 0xF8000000, ptr->m2 << 27); + + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x07FF0000, ptr->m << 16); + + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x00007F00, ptr->n << 8); + + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); + + /* SSI */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000F00, CORE_SSI_DIV << 8); + /* FSUSB */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000030, CORE_FUSB_DIV << 4); + /* L4 */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x0000000C, CORE_L4_DIV << 2); + /* L3 */ + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000003, CORE_L3_DIV); + /* GFX */ + clrsetbits_le32(&prcm_base->clksel_gfx, + 0x00000007, GFX_DIV_36X); + /* RESET MGR */ + clrsetbits_le32(&prcm_base->clksel_wkup, + 0x00000006, WKUP_RSM << 1); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + clrsetbits_le32(&prcm_base->clken_pll, + 0x000000F0, ptr->fsel << 4); + /* LOCK MODE */ + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_LOCK); + + wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, + LDELAY); + } else if (is_running_in_flash()) { + /* + * if running from flash, jump to small relocated code + * area in SRAM. + */ + f_lock_pll = (void *) (SRAM_CLK_CODE); + + p0 = readl(&prcm_base->clken_pll); + clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); + + p1 = readl(&prcm_base->clksel1_pll); + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + clrbits_le32(&p1, 0x00000040); + + p2 = readl(&prcm_base->clksel_core); + /* SSI */ + clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); + /* FSUSB */ + clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); + /* L4 */ + clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); + /* L3 */ + clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); + + p3 = (u32)&prcm_base->idlest_ckgen; + + (*f_lock_pll) (p0, p1, p2, p3); + } +} + +static void dpll4_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct dpll_per_36x_param *ptr; + + ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr += clk_index; + + /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); + + /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */ + clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24); + + /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ + clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); + + /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ + clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4); + + /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */ + clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8); + + /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ + clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); + + /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */ + clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8); + + /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ + clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); + + /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */ + clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12); + + /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); + wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); +} + +static void dpll5_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* PER2 DPLL (DPLL5) */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); + wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); + /* set M2 (usbtll_fck) */ + clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); + /* set m (11-bit multiplier) */ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); + /* set n (7-bit divider)*/ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); + /* lock mode */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); + wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); +} + +static void mpu_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param(); + + /* Moving to the right sysclk */ + ptr += clk_index; + + /* MPU DPLL (unlocked already */ + + /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ + clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); + + /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); + + /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); +} + +static void iva_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param(); + + /* Moving to the right sysclk */ + ptr += clk_index; + + /* IVA DPLL */ + /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ + clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); + wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); + + /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ + clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2); + + /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8); + + /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n); + + /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ + clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK); + + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk = 0, sys_clkin_sel; + u32 clk_index, sil_index = 0; + struct prm *prm_base = (struct prm *)PRM_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* + * Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + /* set input crystal speed */ + clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); + + /* If the input clock is greater than 19.2M always divide/2 */ + if (sys_clkin_sel > 2) { + /* input clock divider */ + clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); + clk_index = sys_clkin_sel / 2; + } else { + /* input clock divider */ + clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); + clk_index = sys_clkin_sel; + } + + if (get_cpu_family() == CPU_OMAP36XX) { + /* + * In warm reset conditions on OMAP36xx/AM/DM37xx + * the rom code incorrectly sets the DPLL4 clock + * input divider to /6.5. Section 3.5.3.3.3.2.1 of + * the AM/DM37x TRM explains that the /6.5 divider + * is used only when the input clock is 13MHz. + * + * If the part is in this cpu family *and* the input + * clock *is not* 13 MHz, then reset the DPLL4 clock + * input divider to /1 as it should never set to /6.5 + * in this case. + */ + if (sys_clkin_sel != 1) { /* 13 MHz */ + /* Bit 8: DPLL4_CLKINP_DIV */ + clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); + } + + /* Unlock MPU DPLL (slows things down, and needed later) */ + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, + LDELAY); + + dpll3_init_36xx(0, clk_index); + dpll4_init_36xx(0, clk_index); + dpll5_init_36xx(0, clk_index); + iva_init_36xx(0, clk_index); + mpu_init_36xx(0, clk_index); + + /* Lock MPU DPLL to set frequency */ + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, + LDELAY); + } else { + /* + * The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + if (((get_cpu_family() == CPU_OMAP34XX) + && (get_cpu_rev() >= CPU_3XX_ES20)) || + (get_cpu_family() == CPU_AM35XX)) + sil_index = 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, + LDELAY); + + dpll3_init_34xx(sil_index, clk_index); + dpll4_init_34xx(sil_index, clk_index); + dpll5_init_34xx(sil_index, clk_index); + if (get_cpu_family() != CPU_AM35XX) + iva_init_34xx(sil_index, clk_index); + + mpu_init_34xx(sil_index, clk_index); + + /* Lock MPU DPLL to set frequency */ + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, + LDELAY); + } + + /* Set up GPTimers to sys_clk source only */ + setbits_le32(&prcm_base->clksel_per, 0x000000FF); + setbits_le32(&prcm_base->clksel_wkup, 1); + + sdelay(5000); +} + +/* + * Enable usb ehci uhh, tll clocks + */ +void ehci_clocks_enable(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ + setbits_le32(&prcm_base->iclken_usbhost, 1); + /* + * Enable USBHOST_48M_FCLK (USBHOST_FCLK1) + * and USBHOST_120M_FCLK (USBHOST_FCLK2) + */ + setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); + /* Enable USBTTL_ICLK */ + setbits_le32(&prcm_base->iclken3_core, 0x00000004); + /* Enable USBTTL_FCLK */ + setbits_le32(&prcm_base->fclken3_core, 0x00000004); +} + +/****************************************************************************** + * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...) + *****************************************************************************/ +void per_clocks_enable(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* Enable GP2 timer. */ + setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ + setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ + setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ + + /* Enable GP9 timer. */ + setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ + setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */ + setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */ + +#ifdef CONFIG_SYS_NS16550 + /* Enable UART1 clocks */ + setbits_le32(&prcm_base->fclken1_core, 0x00002000); + setbits_le32(&prcm_base->iclken1_core, 0x00002000); + + /* Enable UART2 clocks */ + setbits_le32(&prcm_base->fclken1_core, 0x00004000); + setbits_le32(&prcm_base->iclken1_core, 0x00004000); + + /* UART 3 Clocks */ + setbits_le32(&prcm_base->fclken_per, 0x00000800); + setbits_le32(&prcm_base->iclken_per, 0x00000800); +#endif + +#ifdef CONFIG_OMAP3_GPIO_2 + setbits_le32(&prcm_base->fclken_per, 0x00002000); + setbits_le32(&prcm_base->iclken_per, 0x00002000); +#endif +#ifdef CONFIG_OMAP3_GPIO_3 + setbits_le32(&prcm_base->fclken_per, 0x00004000); + setbits_le32(&prcm_base->iclken_per, 0x00004000); +#endif +#ifdef CONFIG_OMAP3_GPIO_4 + setbits_le32(&prcm_base->fclken_per, 0x00008000); + setbits_le32(&prcm_base->iclken_per, 0x00008000); +#endif +#ifdef CONFIG_OMAP3_GPIO_5 + setbits_le32(&prcm_base->fclken_per, 0x00010000); + setbits_le32(&prcm_base->iclken_per, 0x00010000); +#endif +#ifdef CONFIG_OMAP3_GPIO_6 + setbits_le32(&prcm_base->fclken_per, 0x00020000); + setbits_le32(&prcm_base->iclken_per, 0x00020000); +#endif + +#ifdef CONFIG_SYS_I2C_OMAP34XX + /* Turn on all 3 I2C clocks */ + setbits_le32(&prcm_base->fclken1_core, 0x00038000); + setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ +#endif + /* Enable the ICLK for 32K Sync Timer as its used in udelay */ + setbits_le32(&prcm_base->iclken_wkup, 0x00000004); + + if (get_cpu_family() != CPU_AM35XX) + out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON); + + out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON); + out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON); + out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON); + out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON); + out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON); + out_le32(&prcm_base->fclken_dss, FCK_DSS_ON); + out_le32(&prcm_base->iclken_dss, ICK_DSS_ON); + if (get_cpu_family() != CPU_AM35XX) { + out_le32(&prcm_base->fclken_cam, FCK_CAM_ON); + out_le32(&prcm_base->iclken_cam, ICK_CAM_ON); + } + + sdelay(1000); +} diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c new file mode 100644 index 00000000000..37f4b8b4901 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/emac.c @@ -0,0 +1,29 @@ +/* + * + * DaVinci EMAC initialization. + * + * (C) Copyright 2011, Ilya Yanok, Emcraft Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + u32 reset; + + /* ensure that the module is out of reset */ + reset = readl(&am35x_scm_general_regs->ip_sw_reset); + reset &= ~CPGMACSS_SW_RST; + writel(reset, &am35x_scm_general_regs->ip_sw_reset); + + return davinci_emac_initialize(); +} diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c new file mode 100644 index 00000000000..a2aadc98169 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -0,0 +1,165 @@ +/* + * Author : + * Vaibhav Hiremath + * + * Based on mem.c and sdrc.c + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +extern omap3_sysinfo sysinfo; + +static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE; + +/* + * is_mem_sdr - + * - Return 1 if mem type in use is SDR + */ +u32 is_mem_sdr(void) +{ + return 0; +} + +/* + * get_sdr_cs_size - + * - Get size of chip select 0/1 + */ +u32 get_sdr_cs_size(u32 cs) +{ + u32 size = 0; + + /* TODO: Calculate the size based on EMIF4 configuration */ + if (cs == CS0) + size = CONFIG_SYS_CS0_SIZE; + + return size; +} + +/* + * get_sdr_cs_offset - + * - Get offset of cs from cs0 start + */ +u32 get_sdr_cs_offset(u32 cs) +{ + u32 offset = 0; + + return offset; +} + +/* + * do_emif4_init - + * - Init the emif4 module for DDR access + * - Early init routines, called from flash or SRAM. + */ +static void do_emif4_init(void) +{ + unsigned int regval; + /* Set the DDR PHY parameters in PHY ctrl registers */ + regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | + EMIF4_DDR1_EXT_STRB_DIS); + writel(regval, &emif4_base->ddr_phyctrl1); + writel(regval, &emif4_base->ddr_phyctrl1_shdw); + writel(0, &emif4_base->ddr_phyctrl2); + + /* Reset the DDR PHY and wait till completed */ + regval = readl(&emif4_base->sdram_iodft_tlgc); + regval |= (1<<10); + writel(regval, &emif4_base->sdram_iodft_tlgc); + /*Wait till that bit clears*/ + while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1); + /*Re-verify the DDR PHY status*/ + while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0); + + regval |= (1<<0); + writel(regval, &emif4_base->sdram_iodft_tlgc); + /* Set SDR timing registers */ + regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | + EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | + EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | + EMIF4_TIM1_T_RP); + writel(regval, &emif4_base->sdram_time1); + writel(regval, &emif4_base->sdram_time1_shdw); + + regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | + EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | + EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); + writel(regval, &emif4_base->sdram_time2); + writel(regval, &emif4_base->sdram_time2_shdw); + + regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); + writel(regval, &emif4_base->sdram_time3); + writel(regval, &emif4_base->sdram_time3_shdw); + + /* Set the PWR control register */ + regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | + EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); + writel(regval, &emif4_base->sdram_pwr_mgmt); + writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); + + /* Set the DDR refresh rate control register */ + regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); + writel(regval, &emif4_base->sdram_refresh_ctrl); + writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); + + /* set the SDRAM configuration register */ + regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | + EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | + EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | + EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | + EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | + EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); + writel(regval, &emif4_base->sdram_config); +} + +/* + * dram_init - + * - Sets uboots idea of sdram size + */ +int dram_init(void) +{ + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) + size1 = get_sdr_cs_size(CS1); + + gd->ram_size = size0 + size1; + return 0; +} + +void dram_init_banksize (void) +{ + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; +} + +/* + * mem_init() - + * - Initialize memory subsystem + */ +void mem_init(void) +{ + do_emif4_init(); +} diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S new file mode 100644 index 00000000000..1e587723cec --- /dev/null +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -0,0 +1,476 @@ +/* + * Board specific setup info + * + * (C) Copyright 2008 + * Texas Instruments, + * + * Initial Code by: + * Richard Woodruff + * Syed Mohammed Khasim + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * Funtion for making PPA HAL API calls in secure devices + * Input: + * R0 - Service ID + * R1 - paramer list + */ +ENTRY(do_omap3_emu_romcode_call) + PUSH {r4-r12, lr} @ Save all registers from ROM code! + MOV r12, r0 @ Copy the Secure Service ID in R12 + MOV r3, r1 @ Copy the pointer to va_list in R3 + MOV r1, #0 @ Process ID - 0 + MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer + @ to va_list in R3 + MOV r6, #0xFF @ Indicate new Task call + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c10, 5 @ DMB + .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled + @ because we use -march=armv5 + POP {r4-r12, pc} +ENDPROC(do_omap3_emu_romcode_call) + +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +ENTRY(cpy_clk_code) + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* copy from start of go_to_speed... */ + adr r2, lowlevel_init /* ... up to start of low_level_init */ +next2: + ldmia r0!, {r3 - r10} /* copy from source address [r0] */ + stmia r1!, {r3 - r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + blo next2 + mov pc, lr /* back to caller */ +ENDPROC(cpy_clk_code) + +/* *************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this + * code runs from flash before SDR is init so that should be ok. + ****************************************************************************/ +ENTRY(go_to_speed) + stmfd sp!, {r4 - r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4 - r6} + mov pc, lr /* back to caller, locked */ +ENDPROC(go_to_speed) + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +ENTRY(lowlevel_init) + ldr sp, SRAM_STACK + str ip, [sp] /* stash ip register */ + mov ip, lr /* save link reg across call */ +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) +/* + * No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ + ldr r1, =SRAM_CLK_CODE + bl cpy_clk_code +#endif /* NAND Boot */ + mov lr, ip /* restore link reg */ + ldr ip, [sp] /* restore save ip */ + /* tail-call s_init to setup pll, mux, memory */ + b s_init + +ENDPROC(lowlevel_init) + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ + +/* + * Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1 +/* ES2 */ +.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2 +/* 3410 */ +.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12 + +/* 13MHz */ +/* ES1 */ +.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1 +/* ES2 */ +.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2 +/* 3410 */ +.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1 +/* ES2 */ +.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2 +/* 3410 */ +.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2 + +/* 26MHz */ +/* ES1 */ +.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1 +/* ES2 */ +.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2 +/* 3410 */ +.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1 +/* ES2 */ +.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2 +/* 3410 */ +.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1 +/* ES2 */ +.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2 +/* 3410 */ +.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12 + +/* 13MHz */ +/* ES1 */ +.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1 +/* ES2 */ +.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2 +/* 3410 */ +.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1 +/* ES2 */ +.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2 +/* 3410 */ +.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2 + +/* 26MHz */ +/* ES1 */ +.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1 +/* ES2 */ +.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2 +/* 3410 */ +.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1 +/* ES2 */ +.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2 +/* 3410 */ +.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1 +/* ES2 */ +.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 +/* 3410 */ +.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 + +/* 13MHz */ +/* ES1 */ +.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1 +/* ES2 */ +.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 +/* 3410 */ +.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1 +/* ES2 */ +.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 +/* 3410 */ +.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 + +/* 26MHz */ +/* ES1 */ +.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1 +/* ES2 */ +.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 +/* 3410 */ +.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1 +/* ES2 */ +.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 +/* 3410 */ +.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12 + +/* 13MHz */ +.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13 + +/* 19.2MHz */ +.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2 + +/* 26MHz */ +.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26 + +/* 38.4MHz */ +.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + +/* PER2 DPLL values */ +per2_dpll_param: +/* 12MHz */ +.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12 + +/* 13MHz */ +.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13 + +/* 19.2MHz */ +.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2 + +/* 26MHz */ +.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26 + +/* 38.4MHz */ +.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 + +.globl get_per2_dpll_param +get_per2_dpll_param: + adr r0, per2_dpll_param + mov pc, lr + +/* + * Tables for 36XX/37XX devices + * + */ +mpu_36x_dpll_param: +/* 12MHz */ +.word 50, 0, 0, 1 +/* 13MHz */ +.word 600, 12, 0, 1 +/* 19.2MHz */ +.word 125, 3, 0, 1 +/* 26MHz */ +.word 300, 12, 0, 1 +/* 38.4MHz */ +.word 125, 7, 0, 1 + +iva_36x_dpll_param: +/* 12MHz */ +.word 130, 2, 0, 1 +/* 13MHz */ +.word 20, 0, 0, 1 +/* 19.2MHz */ +.word 325, 11, 0, 1 +/* 26MHz */ +.word 10, 0, 0, 1 +/* 38.4MHz */ +.word 325, 23, 0, 1 + +core_36x_dpll_param: +/* 12MHz */ +.word 100, 2, 0, 1 +/* 13MHz */ +.word 400, 12, 0, 1 +/* 19.2MHz */ +.word 375, 17, 0, 1 +/* 26MHz */ +.word 200, 12, 0, 1 +/* 38.4MHz */ +.word 375, 35, 0, 1 + +per_36x_dpll_param: +/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ +.word 12000, 360, 4, 9, 16, 5, 4, 3, 1 +.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 +.word 19200, 360, 7, 9, 16, 5, 4, 3, 1 +.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 +.word 38400, 360, 15, 9, 16, 5, 4, 3, 1 + +per2_36x_dpll_param: +/* 12MHz */ +.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 +/* 13MHz */ +.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 +/* 19.2MHz */ +.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 +/* 26MHz */ +.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 +/* 38.4MHz */ +.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 + + +ENTRY(get_36x_mpu_dpll_param) + adr r0, mpu_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_mpu_dpll_param) + +ENTRY(get_36x_iva_dpll_param) + adr r0, iva_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_iva_dpll_param) + +ENTRY(get_36x_core_dpll_param) + adr r0, core_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_core_dpll_param) + +ENTRY(get_36x_per_dpll_param) + adr r0, per_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_per_dpll_param) + +ENTRY(get_36x_per2_dpll_param) + adr r0, per2_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_per2_dpll_param) diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c new file mode 100644 index 00000000000..4f15ac9cb55 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -0,0 +1,241 @@ +/* + * Functions related to OMAP3 SDRC. + * + * This file has been created after exctracting and consolidating + * the SDRC related content from mem.c and board.c, also created + * generic init function (mem_init). + * + * Copyright (C) 2004-2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * Author : + * Vaibhav Hiremath + * + * Original implementation by (mem.c, board.c) : + * Sunil Kumar + * Shashi Ranjan + * Manikandan Pillai + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +extern omap3_sysinfo sysinfo; + +static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; + +/* + * is_mem_sdr - + * - Return 1 if mem type in use is SDR + */ +u32 is_mem_sdr(void) +{ + if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) + return 1; + return 0; +} + +/* + * make_cs1_contiguous - + * - When we have CS1 populated we want to have it mapped after cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. We could do it in the ATAG, but there really is two banks... + */ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(CS0); + size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); + +} + + +/* + * get_sdr_cs_size - + * - Get size of chip select 0/1 + */ +u32 get_sdr_cs_size(u32 cs) +{ + u32 size; + + /* get ram size field */ + size = readl(&sdrc_base->cs[cs].mcfg) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size <<= 21; /* multiply by 2 MiB to find size in MB */ + return size; +} + +/* + * get_sdr_cs_offset - + * - Get offset of cs from cs0 start + */ +u32 get_sdr_cs_offset(u32 cs) +{ + u32 offset; + + if (!cs) + return 0; + + offset = readl(&sdrc_base->cs_cfg); + offset = (offset & 15) << 27 | (offset & 0x300) << 17; + + return offset; +} + +/* + * write_sdrc_timings - + * - Takes CS and associated timings and initalize SDRAM + * - Test CS to make sure it's OK for use + */ +static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, + struct board_sdrc_timings *timings) +{ + /* Setup timings we got from the board. */ + writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); + writel(timings->ctrla, &sdrc_actim_base->ctrla); + writel(timings->ctrlb, &sdrc_actim_base->ctrlb); + writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(timings->mr, &sdrc_base->cs[cs].mr); + + /* + * Test ram in this bank + * Disable if bad or not present + */ + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); +} + +/* + * do_sdrc_init - + * - Code called once in C-Stack only context for CS0 and with early being + * true and a possible 2nd time depending on memory configuration from + * stack+global context. + */ +void do_sdrc_init(u32 cs, u32 early) +{ + struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; + struct board_sdrc_timings timings; + + sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + + /* set some default timings */ + timings.sharing = SDRC_SHARING; + + /* + * When called in the early context this may be SPL and we will + * need to set all of the timings. This ends up being board + * specific so we call a helper function to take care of this + * for us. Otherwise, to be safe, we need to copy the settings + * from the first bank to the second. We will setup CS0, + * then set cs_cfg to the appropriate value then try and + * setup CS1. + */ +#ifdef CONFIG_SPL_BUILD + /* set/modify board-specific timings */ + get_board_mem_timings(&timings); +#endif + if (early) { + /* reset sdrc controller */ + writel(SOFTRESET, &sdrc_base->sysconfig); + wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, + 12000000); + writel(0, &sdrc_base->sysconfig); + + /* setup sdrc to ball mux */ + writel(timings.sharing, &sdrc_base->sharing); + + /* Disable Power Down of CKE because of 1 CKE on combo part */ + writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, + &sdrc_base->power); + + writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); + sdelay(0x20000); +#ifdef CONFIG_SPL_BUILD + write_sdrc_timings(CS0, sdrc_actim_base0, &timings); + make_cs1_contiguous(); + write_sdrc_timings(CS1, sdrc_actim_base1, &timings); +#endif + + } + + /* + * If we aren't using SPL we have been loaded by some + * other means which may not have correctly initialized + * both CS0 and CS1 (such as some older versions of x-loader) + * so we may be asked now to setup CS1. + */ + if (cs == CS1) { + timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), + timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + timings.ctrla = readl(&sdrc_actim_base0->ctrla); + timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); + timings.mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, &timings); + } +} + +/* + * dram_init - + * - Sets uboots idea of sdram size + */ +int dram_init(void) +{ + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * We always need to have cs_cfg point at where the second + * bank would be, if present. Failure to do so can lead to + * strange situations where memory isn't detected and + * configured correctly. CS0 will already have been setup + * at this point. + */ + make_cs1_contiguous(); + do_sdrc_init(CS1, NOT_EARLY); + size1 = get_sdr_cs_size(CS1); + + gd->ram_size = size0 + size1; + + return 0; +} + +void dram_init_banksize (void) +{ + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; +} + +/* + * mem_init - + * - Init the sdrc chip, + * - Selects CS0 and CS1, + */ +void mem_init(void) +{ + /* only init up first bank here */ + do_sdrc_init(CS0, EARLY_INIT); +} diff --git a/arch/arm/mach-omap2/omap3/spl_id_nand.c b/arch/arm/mach-omap2/omap3/spl_id_nand.c new file mode 100644 index 00000000000..0e2f0a2f6d6 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/spl_id_nand.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, + * + * Author : + * Tom Rini + * + * Initial Code from: + * Richard Woodruff + * Jian Zhang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Many boards will want to know the results of the NAND_CMD_READID command + * in order to decide what to do about DDR initialization. This function + * allows us to do that very early and to pass those results back to the + * board so it can make whatever decisions need to be made. + */ +int identify_nand_chip(int *mfr, int *id) +{ + int loops = 1000; + + /* Make sure that we have setup GPMC for NAND correctly. */ + set_gpmc_cs0(MTD_DEV_TYPE_NAND); + + sdelay(2000); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + sdelay(100); + if (--loops == 0) + return 1; + } + writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); + + /* Set the address to read to 0x0 */ + writeb(0x0, &gpmc_cfg->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_cfg->cs[0].nand_dat); + *id = readb(&gpmc_cfg->cs[0].nand_dat); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c new file mode 100644 index 00000000000..6818fab253c --- /dev/null +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * + * Author : + * Manikandan Pillai + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff + * Syed Mohammed Khasim + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include /* get mem tables */ +#include +#include + +#include +#include + +extern omap3_sysinfo sysinfo; +static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + +#ifdef CONFIG_DISPLAY_CPUINFO +static char *rev_s[CPU_3XX_MAX_REV] = { + "1.0", + "2.0", + "2.1", + "3.0", + "3.1", + "UNKNOWN", + "UNKNOWN", + "3.1.2"}; + +/* this is the revision table for 37xx CPUs */ +static char *rev_s_37xx[CPU_37XX_MAX_REV] = { + "1.0", + "1.1", + "1.2"}; +#endif /* CONFIG_DISPLAY_CPUINFO */ + +void omap_die_id(unsigned int *die_id) +{ + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; + + die_id[0] = readl(&id_base->die_id_0); + die_id[1] = readl(&id_base->die_id_1); + die_id[2] = readl(&id_base->die_id_2); + die_id[3] = readl(&id_base->die_id_3); +} + +/****************************************** + * get_cpu_type(void) - extract cpu info + ******************************************/ +u32 get_cpu_type(void) +{ + return readl(&ctrl_base->ctrl_omap_stat); +} + +/****************************************** + * get_cpu_id(void) - extract cpu id + * returns 0 for ES1.0, cpuid otherwise + ******************************************/ +u32 get_cpu_id(void) +{ + struct ctrl_id *id_base; + u32 cpuid = 0; + + /* + * On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate between ES1.0 and > ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); + if ((cpuid & 0xf) == 0x0) { + return 0; + } else { + /* Decode the IDs on > ES1.0 */ + id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE; + + cpuid = readl(&id_base->idcode); + } + + return cpuid; +} + +/****************************************** + * get_cpu_family(void) - extract cpu info + ******************************************/ +u32 get_cpu_family(void) +{ + u16 hawkeye; + u32 cpu_family; + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_OMAP34XX; + + hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; + switch (hawkeye) { + case HAWKEYE_OMAP34XX: + cpu_family = CPU_OMAP34XX; + break; + case HAWKEYE_AM35XX: + cpu_family = CPU_AM35XX; + break; + case HAWKEYE_OMAP36XX: + cpu_family = CPU_OMAP36XX; + break; + default: + cpu_family = CPU_OMAP34XX; + } + + return cpu_family; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_3XX_ES10; + else + return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; +} + +/***************************************************************** + * get_sku_id(void) - read sku_id to get info on max clock rate + *****************************************************************/ +u32 get_sku_id(void) +{ + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; + return readl(&id_base->sku_id) & SKUID_CLK_MASK; +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = readl(&gpmc_cfg->cs[0].config7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return b; +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return WIDTH_16BIT; +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +#ifdef CONFIG_REVISION_TAG +u32 __weak get_board_rev(void) +{ + return 0x20; +} +#endif + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +static u32 get_base(void) +{ + u32 val; + + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return val; +} + +/******************************************************** + * is_running_in_flash() - tell if currently running in + * FLASH. + *******************************************************/ +u32 is_running_in_flash(void) +{ + if (get_base() < 4) + return 1; /* in FLASH */ + + return 0; /* running in SRAM or SDRAM */ +} + +/******************************************************** + * is_running_in_sram() - tell if currently running in + * SRAM. + *******************************************************/ +u32 is_running_in_sram(void) +{ + if (get_base() == 4) + return 1; /* in SRAM */ + + return 0; /* running in FLASH or SDRAM */ +} + +/******************************************************** + * is_running_in_sdram() - tell if currently running in + * SDRAM. + *******************************************************/ +u32 is_running_in_sdram(void) +{ + if (get_base() > 4) + return 1; /* in SDRAM */ + + return 0; /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 says mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + return (readl(&ctrl_base->status) & SYSBOOT_MASK); +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8); +} + +#ifdef CONFIG_DISPLAY_CPUINFO +/** + * Print CPU information + */ +int print_cpuinfo (void) +{ + char *cpu_family_s, *cpu_s, *sec_s, *max_clk; + + switch (get_cpu_family()) { + case CPU_OMAP34XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3503: + cpu_s = "3503"; + break; + case OMAP3515: + cpu_s = "3515"; + break; + case OMAP3525: + cpu_s = "3525"; + break; + case OMAP3530: + cpu_s = "3530"; + break; + default: + cpu_s = "35XX"; + break; + } + if ((get_cpu_rev() >= CPU_3XX_ES31) && + (get_sku_id() == SKUID_CLK_720MHZ)) + max_clk = "720 MHz"; + else + max_clk = "600 MHz"; + + break; + case CPU_AM35XX: + cpu_family_s = "AM"; + switch (get_cpu_type()) { + case AM3505: + cpu_s = "3505"; + break; + case AM3517: + cpu_s = "3517"; + break; + default: + cpu_s = "35XX"; + break; + } + max_clk = "600 Mhz"; + break; + case CPU_OMAP36XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3730: + cpu_s = "3630/3730"; + break; + default: + cpu_s = "36XX/37XX"; + break; + } + max_clk = "1 Ghz"; + break; + default: + cpu_family_s = "OMAP"; + cpu_s = "35XX"; + max_clk = "600 Mhz"; + } + + switch (get_device_type()) { + case TST_DEVICE: + sec_s = "TST"; + break; + case EMU_DEVICE: + sec_s = "EMU"; + break; + case HS_DEVICE: + sec_s = "HS"; + break; + case GP_DEVICE: + sec_s = "GP"; + break; + default: + sec_s = "?"; + } + + if (CPU_OMAP36XX == get_cpu_family()) + printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s_37xx[get_cpu_rev()], max_clk); + else + printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s[get_cpu_rev()], max_clk); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-omap2/omap4/Kconfig b/arch/arm/mach-omap2/omap4/Kconfig new file mode 100644 index 00000000000..2091dd78151 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/Kconfig @@ -0,0 +1,65 @@ +if OMAP44XX + +config SPL_EXT_SUPPORT + default y + +config SPL_FAT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_NAND_SUPPORT + default y + +config SPL_POWER_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + +config SPL_DISPLAY_PRINT + default y + +choice + prompt "OMAP4 board select" + optional + +config TARGET_DUOVERO + bool "OMAP4430 Gumstix Duovero" + +config TARGET_OMAP4_PANDA + bool "TI OMAP4 PandaBoard" + +config TARGET_OMAP4_SDP4430 + bool "TI OMAP4 SDP4430" + +config TARGET_KC1 + bool "Amazon Kindle Fire (first generation)" + +endchoice + +config SYS_SOC + default "omap4" + +source "board/gumstix/duovero/Kconfig" +source "board/ti/panda/Kconfig" +source "board/ti/sdp4430/Kconfig" +source "board/amazon/kc1/Kconfig" + +endif diff --git a/arch/arm/mach-omap2/omap4/Makefile b/arch/arm/mach-omap2/omap4/Makefile new file mode 100644 index 00000000000..564f1f632f3 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2000-2010 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += boot.o +obj-y += sdram_elpida.o +obj-y += hwinit.o +obj-y += emif.o +obj-y += prcm-regs.o +obj-y += hw_data.o diff --git a/arch/arm/mach-omap2/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c new file mode 100644 index 00000000000..7f5791e9ed6 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/boot.c @@ -0,0 +1,105 @@ +/* + * OMAP4 boot + * + * Copyright (C) 2015 Paul Kocialkowski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static u32 boot_devices[] = { + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NONE, + BOOT_DEVICE_XIPWAIT, +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} + +int omap_reboot_mode(char *mode, unsigned int length) +{ + unsigned int limit; + unsigned int i; + + if (length < 2) + return -1; + + if (!warm_reset()) + return -1; + + limit = (length < OMAP_REBOOT_REASON_SIZE) ? length : + OMAP_REBOOT_REASON_SIZE; + + for (i = 0; i < (limit - 1); i++) + mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + mode[i] = '\0'; + + return 0; +} + +int omap_reboot_mode_clear(void) +{ + writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET)); + + return 0; +} + +int omap_reboot_mode_store(char *mode) +{ + unsigned int i; + + for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++) + writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap4/emif.c b/arch/arm/mach-omap2/omap4/emif.c new file mode 100644 index 00000000000..403c3c6146e --- /dev/null +++ b/arch/arm/mach-omap2/omap4/emif.c @@ -0,0 +1,112 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; +u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; +#endif + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +/* Base AC Timing values specified by JESD209-2 for 400MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_400_mhz = { + .max_freq = 400000000, + .RL = 6, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_200_mhz = { + .max_freq = 200000000, + .RL = 3, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 20, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* + * Min tCK values specified by JESD209-2 + * Min tCK specifies the minimum duration of some AC timing parameters in terms + * of the number of cycles. If the calculated number of cycles based on the + * absolute time value is less than the min tCK value, min tCK value should + * be used instead. This typically happens at low frequencies. + */ +static const struct lpddr2_min_tck min_tck_jedec = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings const* + jedec_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_200_mhz, + &timings_jedec_400_mhz +}; + +const struct lpddr2_device_timings jedec_default_timings = { + .ac_timings = jedec_ac_timings, + .min_tck = &min_tck_jedec +}; + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Assume Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &jedec_default_timings; + *cs1_device_timings = &jedec_default_timings; +} +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c new file mode 100644 index 00000000000..02c06c15776 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/hw_data.c @@ -0,0 +1,460 @@ +/* + * + * HW data initialization for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +struct prcm_regs const **prcm = + (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = + (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* + * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF + * OMAP4460 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) + * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1200 MHz - MPU clk at 600 MHz + * OMAP4430 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES1 OPP_NOM frequency */ +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES2.X OPP_NOM frequency */ +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +struct dplls omap4430_dplls_es1 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es1_1524mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4460_dplls = { + .mpu = mpu_dpll_params_1400mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct pmic_data twl6030_4430es1 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, + .step = 12660, /* 12.66 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ +struct pmic_data twl6030 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, + .step = 12660, /* 12.66 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct pmic_data tps62361 = { + .base_offset = TPS62361_BASE_VOLT_MV, + .step = 10000, /* 10 mV represented in uV */ + .start_code = 0, + .gpio = TPS62361_VSEL0_GPIO, + .gpio_en = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct vcores_data omap4430_volts_es1 = { + .mpu.value = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030_4430es1, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030_4430es1, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030_4430es1, +}; + +struct vcores_data omap4430_volts = { + .mpu.value = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +struct vcores_data omap4460_volts = { + .mpu.value = 1203, + .mpu.addr = TPS62361_REG_ADDR_SET1, + .mpu.pmic = &tps62361, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE1, + .core.pmic = &twl6030, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ +struct vcores_data omap4470_volts = { + .mpu.value = 1202, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value = 1126, + .core.addr = SMPS_REG_ADDR_SMPS2, + .core.pmic = &twl6030, + + .mm.value = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, + .mm.pmic = &twl6030, +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, + USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + /* Enable 32 KHz clock for USB PHY */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbotg_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_clksel_usb_60mhz, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void hw_data_init(void) +{ + u32 omap_rev = omap_revision(); + + (*prcm) = &omap4_prcm; + + switch (omap_rev) { + + case OMAP4430_ES1_0: + *dplls_data = &omap4430_dplls_es1; + *omap_vcores = &omap4430_volts_es1; + break; + + case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + + case OMAP4430_ES2_1: + case OMAP4430_ES2_2: + case OMAP4430_ES2_3: + *dplls_data = &omap4430_dplls; + *omap_vcores = &omap4430_volts; + break; + + case OMAP4460_ES1_0: + case OMAP4460_ES1_1: + *dplls_data = &omap4460_dplls; + *omap_vcores = &omap4460_volts; + break; + + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } + + *ctrl = &omap4_ctrl; +} diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c new file mode 100644 index 00000000000..7c6638ca80d --- /dev/null +++ b/arch/arm/mach-omap2/omap4/hwinit.c @@ -0,0 +1,177 @@ +/* + * + * Common functions for OMAP4 based boards + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; + +static const struct gpio_bank gpio_bank_44xx[6] = { + { (void *)OMAP44XX_GPIO1_BASE }, + { (void *)OMAP44XX_GPIO2_BASE }, + { (void *)OMAP44XX_GPIO3_BASE }, + { (void *)OMAP44XX_GPIO4_BASE }, + { (void *)OMAP44XX_GPIO5_BASE }, + { (void *)OMAP44XX_GPIO6_BASE }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; + +#ifdef CONFIG_SPL_BUILD +/* + * Some tuning of IOs for optimal power and performance + */ +void do_io_settings(void) +{ + u32 lpddr2io; + + u32 omap4_rev = omap_revision(); + + if (omap4_rev == OMAP4430_ES1_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; + else if (omap4_rev == OMAP4430_ES2_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; + else + lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; + + /* EMIF1 */ + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, + (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); + + /* EMIF2 */ + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, + (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); + + /* + * Some of these settings (TRIM values) come from eFuse and are + * in turn programmed in the eFuse at manufacturing time after + * calibration of the device. Do the software over-ride only if + * the device is not correctly trimmed + */ + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_iva_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_mpu_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_core_voltage_ctrl); + } + + /* + * Over-ride the register + * i. unconditionally for all 4430 + * ii. only if un-trimmed for 4460 + */ + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); + + if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); +} +#endif /* CONFIG_SPL_BUILD */ + +/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + +void init_omap_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int arm_rev = cortex_rev(); + + switch (arm_rev) { + case MIDR_CORTEX_A9_R0P1: + *omap_si_rev = OMAP4430_ES1_0; + break; + case MIDR_CORTEX_A9_R1P2: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP4430_ES2_0; + break; + case OMAP4_CONTROL_ID_CODE_ES2_1: + *omap_si_rev = OMAP4430_ES2_1; + break; + case OMAP4_CONTROL_ID_CODE_ES2_2: + *omap_si_rev = OMAP4430_ES2_2; + break; + default: + *omap_si_rev = OMAP4430_ES2_0; + break; + } + break; + case MIDR_CORTEX_A9_R1P3: + *omap_si_rev = OMAP4430_ES2_3; + break; + case MIDR_CORTEX_A9_R2P10: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = OMAP4460_ES1_1; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_0: + default: + *omap_si_rev = OMAP4460_ES1_0; + break; + } + break; + default: + *omap_si_rev = OMAP4430_SILICON_ID_INVALID; + break; + } +} + +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); +} + +void v7_outer_cache_disable(void) +{ + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); +} +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/mach-omap2/omap4/prcm-regs.c b/arch/arm/mach-omap2/omap4/prcm-regs.c new file mode 100644 index 00000000000..2f0e1e851ac --- /dev/null +++ b/arch/arm/mach-omap2/omap4/prcm-regs.c @@ -0,0 +1,307 @@ +/* + * + * HW regs data for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +struct prcm_regs const omap4_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_m4_dpll_core = 0x4a004138, + .cm_div_m5_dpll_core = 0x4a00413c, + .cm_div_m6_dpll_core = 0x4a004140, + .cm_div_m7_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_m4_dpll_iva = 0x4a0041b8, + .cm_div_m5_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_m4_dpll_ddrphy = 0x4a004238, + .cm_div_m5_dpll_ddrphy = 0x4a00423c, + .cm_div_m6_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_m4_dpll_per = 0x4a008158, + .cm_div_m5_dpll_per = 0x4a00815c, + .cm_div_m6_dpll_per = 0x4a008160, + .cm_div_m7_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40, + .cm_ivahd_clkstctrl = 0x4a008f00, + + /* cm2.ivahd */ + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_usbphy_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4a30610c, + .cm_sys_clksel = 0x4a306110, + .cm_wkup_clkstctrl = 0x4a307800, + .cm_wkup_l4wkup_clkctrl = 0x4a307820, + .cm_wkup_wdtimer1_clkctrl = 0x4a307828, + .cm_wkup_wdtimer2_clkctrl = 0x4a307830, + .cm_wkup_gpio1_clkctrl = 0x4a307838, + .cm_wkup_gptimer1_clkctrl = 0x4a307840, + .cm_wkup_gptimer12_clkctrl = 0x4a307848, + .cm_wkup_synctimer_clkctrl = 0x4a307850, + .cm_wkup_usim_clkctrl = 0x4a307858, + .cm_wkup_sarram_clkctrl = 0x4a307860, + .cm_wkup_keyboard_clkctrl = 0x4a307878, + .cm_wkup_rtc_clkctrl = 0x4a307880, + .cm_wkup_bandgap_clkctrl = 0x4a307888, + .prm_vc_val_bypass = 0x4a307ba0, + .prm_vc_cfg_channel = 0x4a307ba4, + .prm_vc_cfg_i2c_mode = 0x4a307ba8, + .prm_vc_cfg_i2c_clk = 0x4a307bac, +}; + +struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_status = 0x4A0022C4, + .control_std_fuse_die_id_0 = 0x4A002200, + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, + .control_std_fuse_opp_bgap = 0x4a002260, + .control_status = 0x4a0022c4, + .control_ldosram_iva_voltage_ctrl = 0x4A002320, + .control_ldosram_mpu_voltage_ctrl = 0x4A002324, + .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_usbotghs_ctrl = 0x4A00233C, + .control_padconf_core_base = 0x4A100000, + .control_pbiaslite = 0x4A100600, + .control_lpddr2io1_0 = 0x4A100638, + .control_lpddr2io1_1 = 0x4A10063C, + .control_lpddr2io1_2 = 0x4A100640, + .control_lpddr2io1_3 = 0x4A100644, + .control_lpddr2io2_0 = 0x4A100648, + .control_lpddr2io2_1 = 0x4A10064C, + .control_lpddr2io2_2 = 0x4A100650, + .control_lpddr2io2_3 = 0x4A100654, + .control_efuse_1 = 0x4A100700, + .control_efuse_2 = 0x4A100704, + .control_padconf_wkup_base = 0x4A31E000, +}; diff --git a/arch/arm/mach-omap2/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c new file mode 100644 index 00000000000..78b4f09ce24 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/sdram_elpida.c @@ -0,0 +1,324 @@ +/* + * Timing and Organization details of the Elpida parts used in OMAP4 + * SDPs and Panda + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* + * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430 + * SDP and Panda. Since the parts used and geometry are identical for + * SDP and Panda for a given OMAP4 revision, this information is kept + * here instead of being in board directory. However the key functions + * exported are weakly linked so that they can be over-ridden in the board + * directory if there is a OMAP4 board in the future that uses a different + * memory device or geometry. + * + * For any new board with different memory devices over-ride one or more + * of the following functions as per the CONFIG flags you intend to enable: + * - emif_get_reg_dump() + * - emif_get_dmm_regs() + * - emif_get_device_details() + * - emif_get_device_timings() + */ + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x0000030c, + .sdram_tim1 = 0x08648311, + .sdram_tim2 = 0x101b06ca, + .sdram_tim3 = 0x0048a19f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff808 +}; + +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { + .sdram_config_init = 0x80000eb1, + .sdram_config = 0x80001ab1, + .ref_ctrl = 0x000005cd, + .sdram_tim1 = 0x10cb0622, + .sdram_tim2 = 0x20350d52, + .sdram_tim3 = 0x00b1431f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80540300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 +}; + +static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) +{ + u32 omap4_rev = omap_revision(); + + /* Same devices and geometry on both EMIFs */ + if (omap4_rev == OMAP4430_ES1_0) + *regs = &emif_regs_elpida_380_mhz_1cs; + else if (omap4_rev == OMAP4430_ES2_0) + *regs = &emif_regs_elpida_200_mhz_2cs; + else if (omap4_rev < OMAP4470_ES1_0) + *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; +} +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else if (omap_rev < OMAP4460_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); + +#else + +const struct lpddr2_device_details elpida_2G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_2Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + +const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + +struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) +{ + u32 omap_rev = omap_revision(); + + /* EMIF1 & EMIF2 have identical configuration */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ + return NULL; + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ + *lpddr2_dev_details = elpida_2G_S4_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; + } + return lpddr2_dev_details; +} + +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) + __attribute__((weak, alias("emif_get_device_details_sdp"))); + +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +static const struct lpddr2_ac_timings timings_elpida_400_mhz = { + .max_freq = 400000000, + .RL = 6, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_333_mhz = { + .max_freq = 333000000, + .RL = 5, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_200_mhz = { + .max_freq = 200000000, + .RL = 3, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 20, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_min_tck min_tck_elpida = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_elpida_200_mhz, + &timings_elpida_333_mhz, + &timings_elpida_400_mhz +}; + +const struct lpddr2_device_timings elpida_2G_S4_timings = { + .ac_timings = elpida_ac_timings, + .min_tck = &min_tck_elpida, +}; + +void emif_get_device_timings_sdp(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + u32 omap_rev = omap_revision(); + + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &elpida_2G_S4_timings; + + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + *cs1_device_timings = NULL; + else + *cs1_device_timings = &elpida_2G_S4_timings; +} + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) + __attribute__((weak, alias("emif_get_device_timings_sdp"))); + +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ + +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3, + .mr2 = 0x4, + .mr3 = -1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; + +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig new file mode 100644 index 00000000000..22259dcc5cf --- /dev/null +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -0,0 +1,94 @@ +if OMAP54XX + +config SPL_EXT_SUPPORT + default y + +config SPL_FAT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_NAND_SUPPORT + default y + +config SPL_POWER_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + +config SPL_DISPLAY_PRINT + default y + +choice + prompt "OMAP5 board select" + optional + +config TARGET_CM_T54 + bool "CompuLab CM-T54" + +config TARGET_OMAP5_UEVM + bool "TI OMAP5 uEVM board" + +config TARGET_DRA7XX_EVM + bool "TI DRA7XX" + select TI_I2C_BOARD_DETECT + select PHYS_64BIT + +config TARGET_AM57XX_EVM + bool "AM57XX" + select TI_I2C_BOARD_DETECT + +endchoice + +config SYS_SOC + default "omap5" + +config TI_SECURE_EMIF_REGION_START + hex "Reserved EMIF region start address" + depends on TI_SECURE_DEVICE + default 0x0 + help + Reserved EMIF region start address. Set to "0" to auto-select + to be at the end of the external memory region. + +config TI_SECURE_EMIF_TOTAL_REGION_SIZE + hex "Reserved EMIF region size" + depends on TI_SECURE_DEVICE + default 0x0 + help + Total reserved EMIF region size. Default is 0, which means no reserved EMIF + region on secure devices. + +config TI_SECURE_EMIF_PROTECTED_REGION_SIZE + hex "Size of protected region within reserved EMIF region" + depends on TI_SECURE_DEVICE + default 0x0 + help + This config option is used to specify the size of the portion of the total + reserved EMIF region set aside for secure OS needs that will be protected + using hardware memory firewalls. This value must be smaller than the + TI_SECURE_EMIF_TOTAL_REGION_SIZE value. + +source "board/compulab/cm_t54/Kconfig" +source "board/ti/omap5_uevm/Kconfig" +source "board/ti/dra7xx/Kconfig" +source "board/ti/am57xx/Kconfig" + +endif diff --git a/arch/arm/mach-omap2/omap5/Makefile b/arch/arm/mach-omap2/omap5/Makefile new file mode 100644 index 00000000000..0212df73c15 --- /dev/null +++ b/arch/arm/mach-omap2/omap5/Makefile @@ -0,0 +1,17 @@ +# +# (C) Copyright 2000-2010 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += boot.o +obj-y += hwinit.o +obj-y += emif.o +obj-y += sdram.o +obj-y += prcm-regs.o +obj-y += hw_data.o +obj-y += abb.o +obj-y += fdt.o +obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o +obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c new file mode 100644 index 00000000000..3bf88979e5d --- /dev/null +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -0,0 +1,57 @@ +/* + * Adaptive Body Bias programming sequence for OMAP5 family + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Andrii Tseglytskyi + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Setup LDOVBB for OMAP5. + * On OMAP5+ some ABB settings are fused. They are handled + * in the following way: + * + * 1. corresponding EFUSE register contains ABB enable bit + * and VSET value + * 2. If ABB enable bit is set to 1, than ABB should be + * enabled, otherwise ABB should be disabled + * 3. If ABB is enabled, than VSET value should be copied + * to corresponding MUX control register + */ +s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) +{ + u32 vset; + u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + + if (!is_omap54xx()) { + /* DRA7 */ + fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK; + fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK; + } + /* + * ABB parameters must be properly fused + * otherwise ABB should be disabled + */ + vset = readl(fuse); + if (!(vset & fuse_enable_mask)) + return -1; + + /* prepare VSET value for LDOVBB mux register */ + vset &= fuse_vset_mask; + vset >>= ffs(fuse_vset_mask) - 1; + vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; + vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; + + /* setup LDOVBB using fused value */ + clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap5/boot.c b/arch/arm/mach-omap2/omap5/boot.c new file mode 100644 index 00000000000..583beccad5a --- /dev/null +++ b/arch/arm/mach-omap2/omap5/boot.c @@ -0,0 +1,46 @@ +/* + * OMAP5 boot + * + * Copyright (C) 2015 Paul Kocialkowski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static u32 boot_devices[] = { +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + BOOT_DEVICE_MMC2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_SATA, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIP, + BOOT_DEVICE_SPI, + BOOT_DEVICE_SPI, +#else + BOOT_DEVICE_MMC2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_SATA, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIPWAIT, +#endif +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 4 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c new file mode 100644 index 00000000000..87987308ace --- /dev/null +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, + * + * Lokesh Vutla + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int isolate_io(u32 isolate) +{ + if (isolate) { + clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, + SDCARD_PWRDNZ); + clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, + SDCARD_BIAS_PWRDNZ); + } + + /* Override control on ISOCLKIN signal to IO pad ring. */ + clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, + PMCTRL_ISOCLK_OVERRIDE_CTRL); + if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK, + (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) + return ERR_DEISOLATE_IO << isolate; + + /* Isolate/Deisolate IO */ + clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, + isolate << CTRL_ISOLATE_SHIFT); + /* Dummy read to add delay t > 10ns */ + readl((*ctrl)->ctrl_core_sma_sw_0); + + /* Return control on ISOCLKIN to hardware */ + clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, + PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL); + if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, + 0 << PMCTRL_ISOCLK_STATUS_SHIFT, + (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) + return ERR_DEISOLATE_IO << isolate; + + return 0; +} + +static int calibrate_iodelay(u32 base) +{ + u32 reg; + + /* Configure REFCLK period */ + reg = readl(base + CFG_REG_2_OFFSET); + reg &= ~CFG_REG_REFCLK_PERIOD_MASK; + reg |= CFG_REG_REFCLK_PERIOD; + writel(reg, base + CFG_REG_2_OFFSET); + + /* Initiate Calibration */ + clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK, + CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT); + if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END, + (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) + return ERR_CALIBRATE_IODELAY; + + return 0; +} + +static int update_delay_mechanism(u32 base) +{ + /* Initiate the reload of calibrated values. */ + clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK, + CFG_REG_ROM_READ_START); + if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END, + (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) + return ERR_UPDATE_DELAY; + + return 0; +} + +static u32 calculate_delay(u32 base, u16 offset, u16 den) +{ + u16 refclk_period, dly_cnt, ref_cnt; + u32 reg, q, r; + + refclk_period = readl(base + CFG_REG_2_OFFSET) & + CFG_REG_REFCLK_PERIOD_MASK; + + reg = readl(base + offset); + dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT; + ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT; + + if (!dly_cnt || !den) + return 0; + + /* + * To avoid overflow and integer truncation, delay value + * is calculated as quotient + remainder. + */ + q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den)); + r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) / + (2 * dly_cnt * den); + + return q + r; +} + +static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde) +{ + u32 g_delay_coarse, g_delay_fine; + u32 a_delay_coarse, a_delay_fine; + u32 c_elements, f_elements; + u32 total_delay, reg = 0; + + g_delay_coarse = g_delay / 920; + g_delay_fine = ((g_delay % 920) * 10) / 60; + + a_delay_coarse = a_delay / cpde; + a_delay_fine = ((a_delay % cpde) * 10) / fpde; + + c_elements = g_delay_coarse + a_delay_coarse; + f_elements = (g_delay_fine + a_delay_fine) / 10; + + if (f_elements > 22) { + total_delay = c_elements * cpde + f_elements * fpde; + + c_elements = total_delay / cpde; + f_elements = (total_delay % cpde) / fpde; + } + + reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK; + reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK; + reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT; + reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT; + + return reg; +} + +int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, + int niodelays) +{ + struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array; + u32 reg, cpde, fpde, i; + + if (!niodelays) + return 0; + + cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET, + 88); + if (!cpde) + return ERR_CPDE; + + fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET, + 264); + if (!fpde) + return ERR_FPDE; + + for (i = 0; i < niodelays; i++, iodelay++) { + reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde, + fpde); + writel(reg, base + iodelay->offset); + } + + return 0; +} + +int __recalibrate_iodelay_start(void) +{ + int ret = 0; + + /* IO recalibration should be done only from SRAM */ + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { + puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); + return -1; + } + + /* unlock IODELAY CONFIG registers */ + writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + ret = calibrate_iodelay((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + ret = isolate_io(ISOLATE_IO); + if (ret) + goto err; + + ret = update_delay_mechanism((*ctrl)->iodelay_config_base); + +err: + return ret; +} + +void __recalibrate_iodelay_end(int ret) +{ + + /* IO recalibration should be done only from SRAM */ + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { + puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); + return; + } + + if (!ret) + ret = isolate_io(DEISOLATE_IO); + + /* lock IODELAY CONFIG registers */ + writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + /* + * UART cannot be used during IO recalibration sequence as IOs are in + * isolation. So error handling and debug prints are done after + * complete IO delay recalibration sequence + */ + switch (ret) { + case ERR_CALIBRATE_IODELAY: + puts("IODELAY: IO delay calibration sequence failed\n"); + break; + case ERR_ISOLATE_IO: + puts("IODELAY: Isolation of Device IOs failed\n"); + break; + case ERR_UPDATE_DELAY: + puts("IODELAY: Delay mechanism update with new calibrated values failed\n"); + break; + case ERR_DEISOLATE_IO: + puts("IODELAY: De-isolation of Device IOs failed\n"); + break; + case ERR_CPDE: + puts("IODELAY: CPDE calculation failed\n"); + break; + case ERR_FPDE: + puts("IODELAY: FPDE calculation failed\n"); + break; + case -1: + puts("IODELAY: Wrong Context call?\n"); + break; + default: + debug("IODELAY: IO delay recalibration successfully completed\n"); + } + + return; +} + +void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* IO recalibration should be done only from SRAM */ + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { + puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); + return; + } + + ret = __recalibrate_iodelay_start(); + if (ret) + goto err; + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + +err: + __recalibrate_iodelay_end(ret); + +} diff --git a/arch/arm/mach-omap2/omap5/emif.c b/arch/arm/mach-omap2/omap5/emif.c new file mode 100644 index 00000000000..b1203a37afc --- /dev/null +++ b/arch/arm/mach-omap2/omap5/emif.c @@ -0,0 +1,88 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V for OMAP4 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) +static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; +static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; +#endif + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +/* Base AC Timing values specified by JESD209-2 for 532MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_532_mhz = { + .max_freq = 532000000, + .RL = 8, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* + * Min tCK values specified by JESD209-2 + * Min tCK specifies the minimum duration of some AC timing parameters in terms + * of the number of cycles. If the calculated number of cycles based on the + * absolute time value is less than the min tCK value, min tCK value should + * be used instead. This typically happens at low frequencies. + */ +static const struct lpddr2_min_tck min_tck_jedec = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings const* + jedec_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_532_mhz +}; + +static const struct lpddr2_device_timings jedec_default_timings = { + .ac_timings = jedec_ac_timings, + .min_tck = &min_tck_jedec +}; + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Assume Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &jedec_default_timings; + *cs1_device_timings = NULL; +} +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c new file mode 100644 index 00000000000..da8d59bb59f --- /dev/null +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -0,0 +1,244 @@ +/* + * Copyright 2016 Texas Instruments, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_TI_SECURE_DEVICE + +/* Give zero values if not already defined */ +#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ +#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0) +#endif +#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ +#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0) +#endif + +static u32 hs_irq_skip[] = { + 8, /* Secure violation reporting interrupt */ + 15, /* One interrupt for SDMA by secure world */ + 118 /* One interrupt for Crypto DMA by secure world */ +}; + +static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd) +{ + const char *path; + int offs; + int ret; + int len, i, old_cnt, new_cnt; + u32 *temp; + const u32 *p_data; + + /* + * Increase the size of the fdt + * so we have some breathing room + */ + ret = fdt_increase_size(fdt, 512); + if (ret < 0) { + printf("Could not increase size of device tree: %s\n", + fdt_strerror(ret)); + return ret; + } + + /* Reserve IRQs that are used/needed by secure world */ + path = "/ocp/crossbar"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found.\n", path); + return 0; + } + + /* Get current entries */ + p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len); + if (p_data) + old_cnt = len / sizeof(u32); + else + old_cnt = 0; + + new_cnt = sizeof(hs_irq_skip) / + sizeof(hs_irq_skip[0]); + + /* Create new/updated skip list for HS parts */ + temp = malloc(sizeof(u32) * (old_cnt + new_cnt)); + for (i = 0; i < new_cnt; i++) + temp[i] = cpu_to_fdt32(hs_irq_skip[i]); + for (i = 0; i < old_cnt; i++) + temp[i + new_cnt] = p_data[i]; + + /* Blow away old data and set new data */ + fdt_delprop(fdt, offs, "ti,irqs-skip"); + ret = fdt_setprop(fdt, offs, "ti,irqs-skip", + temp, + (old_cnt + new_cnt) * sizeof(u32)); + free(temp); + + /* Check if the update worked */ + if (ret < 0) { + printf("Could not add ti,irqs-skip property to node %s: %s\n", + path, fdt_strerror(ret)); + return ret; + } + + return 0; +} + +static int ft_hs_disable_rng(void *fdt, bd_t *bd) +{ + const char *path; + int offs; + int ret; + + /* Make HW RNG reserved for secure world use */ + path = "/ocp/rng"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found.\n", path); + return 0; + } + ret = fdt_setprop_string(fdt, offs, + "status", "disabled"); + if (ret < 0) { + printf("Could not add status property to node %s: %s\n", + path, fdt_strerror(ret)); + return ret; + } + return 0; +} + +#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \ + (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0)) +static int ft_hs_fixup_sram(void *fdt, bd_t *bd) +{ + const char *path; + int offs; + int ret; + u32 temp[2]; + + /* + * Update SRAM reservations on secure devices. The OCMC RAM + * is always reserved for secure use from the start of that + * memory region + */ + path = "/ocp/ocmcram@40300000/sram-hs"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found.\n", path); + return 0; + } + + /* relative start offset */ + temp[0] = cpu_to_fdt32(0); + /* reservation size */ + temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ, + CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ)); + fdt_delprop(fdt, offs, "reg"); + ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32)); + if (ret < 0) { + printf("Could not add reg property to node %s: %s\n", + path, fdt_strerror(ret)); + return ret; + } + + return 0; +} +#else +static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; } +#endif + +#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0) +static int ft_hs_fixup_dram(void *fdt, bd_t *bd) +{ + const char *path, *subpath; + int offs; + u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START; + u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE; + fdt64_t temp[2]; + + /* If start address is zero, place at end of DRAM */ + if (0 == sec_mem_start) + sec_mem_start = + (CONFIG_SYS_SDRAM_BASE + + (omap_sdram_size() - sec_mem_size)); + + /* Delete any original secure_reserved node */ + path = "/reserved-memory/secure_reserved"; + offs = fdt_path_offset(fdt, path); + if (offs >= 0) + fdt_del_node(fdt, offs); + + /* Add new secure_reserved node */ + path = "/reserved-memory"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found\n", path); + path = "/"; + subpath = "reserved-memory"; + fdt_path_offset(fdt, path); + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s%s node.\n", path, subpath); + return 1; + } + path = "/reserved-memory"; + offs = fdt_path_offset(fdt, path); + } + + subpath = "secure_reserved"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s%s node.\n", path, subpath); + return 1; + } + + temp[0] = cpu_to_fdt64(((u64)sec_mem_start)); + temp[1] = cpu_to_fdt64(((u64)sec_mem_size)); + fdt_setprop_string(fdt, offs, "compatible", + "ti,dra7-secure-memory"); + fdt_setprop_string(fdt, offs, "status", "okay"); + fdt_setprop(fdt, offs, "no-map", NULL, 0); + fdt_setprop(fdt, offs, "reg", temp, sizeof(temp)); + + return 0; +} +#else +static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; } +#endif + +static void ft_hs_fixups(void *fdt, bd_t *bd) +{ + /* Check we are running on an HS/EMU device type */ + if (GP_DEVICE != get_device_type()) { + if ((ft_hs_fixup_crossbar(fdt, bd) == 0) && + (ft_hs_disable_rng(fdt, bd) == 0) && + (ft_hs_fixup_sram(fdt, bd) == 0) && + (ft_hs_fixup_dram(fdt, bd) == 0)) + return; + } else { + printf("ERROR: Incorrect device type (GP) detected!"); + } + /* Fixup failed or wrong device type */ + hang(); +} +#else +static void ft_hs_fixups(void *fdt, bd_t *bd) +{ +} +#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */ + +/* + * Place for general cpu/SoC FDT fixups. Board specific + * fixups should remain in the board files which is where + * this function should be called from. + */ +void ft_cpu_setup(void *fdt, bd_t *bd) +{ + ft_hs_fixups(fdt, bd); +} diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c new file mode 100644 index 00000000000..fc991358248 --- /dev/null +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -0,0 +1,776 @@ +/* + * + * HW data initialization for OMAP5 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct prcm_regs const **prcm = + (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = + (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; + +/* OPP HIGH FREQUENCY for ES2.0 */ +static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { + {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP NOM FREQUENCY for ES1.0 */ +static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP LOW FREQUENCY for ES1.0 */ +static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { + {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP LOW FREQUENCY for ES2.0 */ +static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { + {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ +static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { + {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ + {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ + {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ + {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ + {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { + {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { + {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { + {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { + {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +/* ABE M & N values with sysclk2(22.5792 MHz) as input */ +static const struct dpll_params + abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { + {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { + {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { + {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ + {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + +struct dplls omap5_dplls_es1 = { + .mpu = mpu_dpll_params_800mhz, + .core = core_dpll_params_2128mhz_ddr532, + .per = per_dpll_params_768mhz, + .iva = iva_dpll_params_2330mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap5_dplls_es2 = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_ddr532_es2, + .per = per_dpll_params_768mhz_es2, + .iva = iva_dpll_params_2330mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls dra7xx_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_dra7xx, + .per = per_dpll_params_768mhz_dra7xx, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_2128mhz, + .gmac = gmac_dpll_params_2000mhz, +}; + +struct dplls dra72x_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_dra7xx, + .per = per_dpll_params_768mhz_dra7xx, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_2664mhz, + .gmac = gmac_dpll_params_2000mhz, +}; + +struct pmic_data palmas = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, + .gpio_en = 0, +}; + +/* The TPS659038 and TPS65917 are software-compatible, use common struct */ +struct pmic_data tps659038 = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, + .gpio_en = 0, +}; + +struct vcores_data omap5430_volts = { + .mpu.value = VDD_MPU, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + +struct vcores_data omap5430_volts_es2 = { + .mpu.value = VDD_MPU_ES2, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .core.value = VDD_CORE_ES2, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM_ES2, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, + .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_clkstctrl, +#endif + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + (*prcm)->cm_l4per_gpio7_clkctrl, + (*prcm)->cm_l4per_gpio8_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_gmac_clkctrl, +#endif + +#ifdef CONFIG_TI_QSPI + (*prcm)->cm_l4per_qspi_clkctrl, +#endif + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Set the correct clock dividers for mmc */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); + +#ifdef CONFIG_TI_QSPI + setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); +#endif + + /* Enable SCRM OPT clocks for PER and CORE dpll */ + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_PER_MASK); + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_CORE_MASK); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + (*prcm)->cm_ipu_clkstctrl, +#endif + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + (*prcm)->cm_ipu_i2c5_clkctrl, +#else + (*prcm)->cm_l4per_i2c5_clkctrl, +#endif + (*prcm)->cm_l3init_hsusbhost_clkctrl, + (*prcm)->cm_l3init_fsusb_clkctrl, + 0 + }; + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks(void) +{ + u32 const clk_domains_edma3[] = { + 0 + }; + + u32 const clk_modules_hw_auto_edma3[] = { + (*prcm)->cm_l3main1_tptc1_clkctrl, + (*prcm)->cm_l3main1_tptc2_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_edma3[] = { + 0 + }; + + do_enable_clocks(clk_domains_edma3, + clk_modules_hw_auto_edma3, + clk_modules_explicit_en_edma3, + 1); +} + +void disable_edma3_clocks(void) +{ + u32 const clk_domains_edma3[] = { + 0 + }; + + u32 const clk_modules_disable_edma3[] = { + (*prcm)->cm_l3main1_tptc1_clkctrl, + (*prcm)->cm_l3main1_tptc2_clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_edma3, + clk_modules_disable_edma3, + 1); +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) +void enable_usb_clocks(int index) +{ + u32 cm_l3init_usb_otg_ss_clkctrl = 0; + + if (index == 0) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for USB_PHY1 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Enable 32 KHz clock for USB_PHY3 */ + if (is_dra7xx()) + setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Enable 60 MHz clock for USB2PHY2 */ + setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); + } + + u32 const clk_domains_usb[] = { + 0 + }; + + u32 const clk_modules_hw_auto_usb[] = { + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + cm_l3init_usb_otg_ss_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_usb[] = { + 0 + }; + + do_enable_clocks(clk_domains_usb, + clk_modules_hw_auto_usb, + clk_modules_explicit_en_usb, + 1); +} + +void disable_usb_clocks(int index) +{ + u32 cm_l3init_usb_otg_ss_clkctrl = 0; + + if (index == 0) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; + /* Disable 960 MHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Disable 32 KHz clock for USB_PHY1 */ + clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Disable 32 KHz clock for USB_PHY3 */ + if (is_dra7xx()) + clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; + /* Disable 960 MHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Disable 32 KHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Disable 60 MHz clock for USB2PHY2 */ + clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); + } + + u32 const clk_domains_usb[] = { + 0 + }; + + u32 const clk_modules_disable[] = { + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + cm_l3init_usb_otg_ss_clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_usb, + clk_modules_disable, + 1); +} +#endif + +const struct ctrl_ioregs ioregs_omap5430 = { + .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, +}; + +const struct ctrl_ioregs ioregs_omap5432_es1 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, +}; + +const struct ctrl_ioregs ioregs_omap5432_es2 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, +}; + +const struct ctrl_ioregs ioregs_dra7xx_es1 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x80808080, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, + .ctrl_ddrio_2 = 0x84210000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + +const struct ctrl_ioregs ioregs_dra72x_es1 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x60606080, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, + .ctrl_ddrio_2 = 0x84210000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + +const struct ctrl_ioregs ioregs_dra72x_es2 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x60606060, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x00000000, + .ctrl_ddrio_2 = 0x00000000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + +void __weak hw_data_init(void) +{ + u32 omap_rev = omap_revision(); + + switch (omap_rev) { + + case OMAP5430_ES1_0: + case OMAP5432_ES1_0: + *prcm = &omap5_es1_prcm; + *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5430_volts; + *ctrl = &omap5_ctrl; + break; + + case OMAP5430_ES2_0: + case OMAP5432_ES2_0: + *prcm = &omap5_es2_prcm; + *dplls_data = &omap5_dplls_es2; + *omap_vcores = &omap5430_volts_es2; + *ctrl = &omap5_ctrl; + break; + + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *ctrl = &dra7xx_ctrl; + break; + + case DRA722_ES1_0: + case DRA722_ES2_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra72x_dplls; + *ctrl = &dra7xx_ctrl; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } +} + +void get_ioregs(const struct ctrl_ioregs **regs) +{ + u32 omap_rev = omap_revision(); + + switch (omap_rev) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + *regs = &ioregs_omap5430; + break; + case OMAP5432_ES1_0: + *regs = &ioregs_omap5432_es1; + break; + case OMAP5432_ES2_0: + *regs = &ioregs_omap5432_es2; + break; + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + *regs = &ioregs_dra7xx_es1; + break; + case DRA722_ES1_0: + *regs = &ioregs_dra72x_es1; + break; + case DRA722_ES2_0: + *regs = &ioregs_dra72x_es2; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } +} diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c new file mode 100644 index 00000000000..e3ac8bbe952 --- /dev/null +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -0,0 +1,453 @@ +/* + * + * Functions for omap5 based boards. + * + * (C) Copyright 2011 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + * Sricharan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; + +#ifndef CONFIG_DM_GPIO +static struct gpio_bank gpio_bank_54xx[8] = { + { (void *)OMAP54XX_GPIO1_BASE }, + { (void *)OMAP54XX_GPIO2_BASE }, + { (void *)OMAP54XX_GPIO3_BASE }, + { (void *)OMAP54XX_GPIO4_BASE }, + { (void *)OMAP54XX_GPIO5_BASE }, + { (void *)OMAP54XX_GPIO6_BASE }, + { (void *)OMAP54XX_GPIO7_BASE }, + { (void *)OMAP54XX_GPIO8_BASE }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; +#endif + +void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +#ifdef CONFIG_SPL_BUILD +/* LPDDR2 specific IO settings */ +static void io_settings_lpddr2(void) +{ + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); + writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); +} + +/* DDR3 specific IO settings */ +static void io_settings_ddr3(void) +{ + u32 io_settings = 0; + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); + + writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); + + writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); + writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); + + if (!is_dra7xx()) { + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + } + + /* omap5432 does not use lpddr2 */ + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); + + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif1_sdram_config_ext); + if (!is_dra72x()) + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif2_sdram_config_ext); + + if (is_omap54xx()) { + /* Disable DLL select */ + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) + & 0xFFEFFFFF); + writel(io_settings, + (*ctrl)->control_port_emif1_sdram_config); + + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) + & 0xFFEFFFFF); + writel(io_settings, + (*ctrl)->control_port_emif2_sdram_config); + } else { + writel(ioregs->ctrl_ddr_ctrl_ext_0, + (*ctrl)->control_ddr_control_ext_0); + } +} + +/* + * Some tuning of IOs for optimal power and performance + */ +void do_io_settings(void) +{ + u32 io_settings = 0, mask = 0; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + /* Impedance settings EMMC, C2C 1,2, hsi2 */ + mask = (ds_mask << 2) | (ds_mask << 8) | + (ds_mask << 16) | (ds_mask << 18); + io_settings = readl((*ctrl)->control_smart1io_padconf_0) & + (~mask); + io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | + (ds_45_ohm << 18) | (ds_60_ohm << 2); + writel(io_settings, (*ctrl)->control_smart1io_padconf_0); + + /* Impedance settings Mcspi2 */ + mask = (ds_mask << 30); + io_settings = readl((*ctrl)->control_smart1io_padconf_1) & + (~mask); + io_settings |= (ds_60_ohm << 30); + writel(io_settings, (*ctrl)->control_smart1io_padconf_1); + + /* Impedance settings C2C 3,4 */ + mask = (ds_mask << 14) | (ds_mask << 16); + io_settings = readl((*ctrl)->control_smart1io_padconf_2) & + (~mask); + io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); + writel(io_settings, (*ctrl)->control_smart1io_padconf_2); + + /* Slew rate settings EMMC, C2C 1,2 */ + mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); + io_settings = readl((*ctrl)->control_smart2io_padconf_0) & + (~mask); + io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); + writel(io_settings, (*ctrl)->control_smart2io_padconf_0); + + /* Slew rate settings hsi2, Mcspi2 */ + mask = (sc_mask << 24) | (sc_mask << 28); + io_settings = readl((*ctrl)->control_smart2io_padconf_1) & + (~mask); + io_settings |= (sc_fast << 28) | (sc_fast << 24); + writel(io_settings, (*ctrl)->control_smart2io_padconf_1); + + /* Slew rate settings C2C 3,4 */ + mask = (sc_mask << 16) | (sc_mask << 18); + io_settings = readl((*ctrl)->control_smart2io_padconf_2) & + (~mask); + io_settings |= (sc_na << 16) | (sc_na << 18); + writel(io_settings, (*ctrl)->control_smart2io_padconf_2); + + /* impedance and slew rate settings for usb */ + mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | + (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); + io_settings = readl((*ctrl)->control_smart3io_padconf_1) & + (~mask); + io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | + (ds_60_ohm << 23) | (sc_fast << 20) | + (sc_fast << 17) | (sc_fast << 14); + writel(io_settings, (*ctrl)->control_smart3io_padconf_1); + + if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) + io_settings_lpddr2(); + else + io_settings_ddr3(); +} + +static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { + {0x45, 0x1}, /* 12 MHz */ + {-1, -1}, /* 13 MHz */ + {0x63, 0x2}, /* 16.8 MHz */ + {0x57, 0x2}, /* 19.2 MHz */ + {0x20, 0x1}, /* 26 MHz */ + {-1, -1}, /* 27 MHz */ + {0x41, 0x3} /* 38.4 MHz */ +}; + +void srcomp_enable(void) +{ + u32 srcomp_value, mul_factor, div_factor, clk_val, i; + u32 sysclk_ind = get_sys_clk_index(); + u32 omap_rev = omap_revision(); + + if (!is_omap54xx()) + return; + + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; + div_factor = srcomp_parameters[sysclk_ind].divide_factor; + + for (i = 0; i < 4; i++) { + srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= + ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); + } + + if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~PWRDWN_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + } else { + srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | + DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + while (((readl((*ctrl)->control_srcomp_east_side_wkup) & + SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + } +} +#endif + +void config_data_eye_leveling_samples(u32 emif_base) +{ + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ + if (emif_base == EMIF1_BASE) + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif1_sdram_config_ext); + else if (emif_base == EMIF2_BASE) + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif2_sdram_config_ext); +} + +void init_cpu_configuration(void) +{ + u32 l2actlr; + + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); + /* + * L2ACTLR: Ensure to enable the following: + * 3: Disable clean/evict push to external + * 4: Disable WriteUnique and WriteLineUnique transactions from master + * 8: Disable DVM/CMO message broadcast + */ + l2actlr |= 0x118; + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); +} + +void init_omap_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int rev = cortex_rev(); + + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5432_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5432_ES2_0; + break; + case OMAP5430_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5432_ES2_0; + break; + case DRA752_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA752_ES1_0; + break; + case DRA752_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = DRA752_ES1_1; + break; + case DRA752_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = DRA752_ES2_0; + break; + case DRA722_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA722_ES1_0; + break; + case DRA722_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = DRA722_ES2_0; + break; + default: + *omap_si_rev = OMAP5430_SILICON_ID_INVALID; + } + init_cpu_configuration(); +} + +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + +void reset_cpu(ulong ignored) +{ + u32 omap_rev = omap_revision(); + + /* + * WARM reset is not functional in case of OMAP5430 ES1.0 soc. + * So use cold reset in case instead. + */ + if (omap_rev == OMAP5430_ES1_0) + writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); + else + writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); +} + +u32 warm_reset(void) +{ + return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; +} + +void setup_warmreset_time(void) +{ + u32 rst_time, rst_val; + +#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC + rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC; +#else + rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC; +#endif + rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT; + + if (rst_time > RSTTIME1_MASK) + rst_time = RSTTIME1_MASK; + + rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; + rst_val |= rst_time; + writel(rst_val, (*prcm)->prm_rsttime); +} + +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); +} + +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + +#ifdef CONFIG_ARM_ERRATA_801819 + /* + * DRA72x processors are uniprocessors and DONOT have + * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency + * Extensions) Hence the erratum workaround is not applicable for + * DRA72x processors. + */ + if (is_dra72x()) + acr &= ~((0x3 << 23) | (0x3 << 25)); +#endif + omap_smc1(OMAP5_SERVICE_ACR_SET, acr); +} diff --git a/arch/arm/mach-omap2/omap5/prcm-regs.c b/arch/arm/mach-omap2/omap5/prcm-regs.c new file mode 100644 index 00000000000..b5f1d700fd8 --- /dev/null +++ b/arch/arm/mach-omap2/omap5/prcm-regs.c @@ -0,0 +1,1024 @@ +/* + * + * HW regs data for OMAP5 Soc + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct prcm_regs const omap5_es1_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + + /* cm2.core */ + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a008f00, + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_sata_clkctrl = 0x4a009388, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_gpio7_clkctrl = 0x4a009510, + .cm_l4per_gpio8_clkctrl = 0x4a009518, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4per_uart5_clkctrl = 0x4a009570, + .cm_l4per_uart6_clkctrl = 0x4a009578, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07800, + .cm_wkup_l4wkup_clkctrl = 0x4ae07820, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, + .cm_wkup_gpio1_clkctrl = 0x4ae07838, + .cm_wkup_gptimer1_clkctrl = 0x4ae07840, + .cm_wkup_gptimer12_clkctrl = 0x4ae07848, + .cm_wkup_synctimer_clkctrl = 0x4ae07850, + .cm_wkup_usim_clkctrl = 0x4ae07858, + .cm_wkup_sarram_clkctrl = 0x4ae07860, + .cm_wkup_keyboard_clkctrl = 0x4ae07878, + .cm_wkup_rtc_clkctrl = 0x4ae07880, + .cm_wkup_bandgap_clkctrl = 0x4ae07888, + .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, + .prm_rstctrl = 0x4ae07b00, + .prm_rstst = 0x4ae07b04, + .prm_rsttime = 0x4ae07b08, + .prm_vc_val_bypass = 0x4ae07ba0, + .prm_vc_cfg_i2c_mode = 0x4ae07bb4, + .prm_vc_cfg_i2c_clk = 0x4ae07bb8, + + /* SCRM stuff, used by some boards */ + .scrm_auxclk0 = 0x4ae0a310, + .scrm_auxclk1 = 0x4ae0a314, +}; + +struct omap_sys_ctrl_regs const omap5_ctrl = { + .control_status = 0x4A002134, + .control_std_fuse_die_id_0 = 0x4A002200, + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, + .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, + .control_padconf_core_base = 0x4A002800, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, + .control_wkup_ldovbb_mm_voltage_ctrl = 0x4AE0C314, + .control_padconf_wkup_base = 0x4AE0C800, + .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, + .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, + .control_padconf_mode = 0x4AE0CDA8, + .control_xtal_oscillator = 0x4AE0CDAC, + .control_i2c_2 = 0x4AE0CDB0, + .control_ckobuffer = 0x4AE0CDB4, + .control_wkup_control_spare_rw = 0x4AE0CDB8, + .control_wkup_control_spare_r = 0x4AE0CDBC, + .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, + .control_srcomp_east_side_wkup = 0x4AE0CDC4, + .control_efuse_1 = 0x4AE0CDC8, + .control_efuse_2 = 0x4AE0CDCC, + .control_efuse_3 = 0x4AE0CDD0, + .control_efuse_4 = 0x4AE0CDD4, + .control_efuse_5 = 0x4AE0CDD8, + .control_efuse_6 = 0x4AE0CDDC, + .control_efuse_7 = 0x4AE0CDE0, + .control_efuse_8 = 0x4AE0CDE4, + .control_efuse_9 = 0x4AE0CDE8, + .control_efuse_10 = 0x4AE0CDEC, + .control_efuse_11 = 0x4AE0CDF0, + .control_efuse_12 = 0x4AE0CDF4, + .control_efuse_13 = 0x4AE0CDF8, +}; + +struct omap_sys_ctrl_regs const dra7xx_ctrl = { + .control_status = 0x4A002134, + .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, + .ctrl_core_sma_sw_0 = 0x4A0023FC, + .ctrl_core_sma_sw_1 = 0x4A002534, + .control_core_mac_id_0_lo = 0x4A002514, + .control_core_mac_id_0_hi = 0x4A002518, + .control_core_mac_id_1_lo = 0x4A00251C, + .control_core_mac_id_1_hi = 0x4A002520, + .control_core_mmr_lock1 = 0x4A002540, + .control_core_mmr_lock2 = 0x4A002544, + .control_core_mmr_lock3 = 0x4A002548, + .control_core_mmr_lock4 = 0x4A00254C, + .control_core_mmr_lock5 = 0x4A002550, + .control_core_control_io1 = 0x4A002554, + .control_core_control_io2 = 0x4A002558, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_ddr_control_ext_0 = 0x4A002E88, + .control_padconf_core_base = 0x4A003400, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, + .control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470, + .control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C, + .control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154, + .control_std_fuse_die_id_0 = 0x4AE0C200, + .control_std_fuse_die_id_1 = 0x4AE0C208, + .control_std_fuse_die_id_2 = 0x4AE0C20C, + .control_std_fuse_die_id_3 = 0x4AE0C210, + .control_padconf_mode = 0x4AE0C5A0, + .control_xtal_oscillator = 0x4AE0C5A4, + .control_i2c_2 = 0x4AE0C5A8, + .control_ckobuffer = 0x4AE0C5AC, + .control_wkup_control_spare_rw = 0x4AE0C5B0, + .control_wkup_control_spare_r = 0x4AE0C5B4, + .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, + .control_srcomp_east_side_wkup = 0x4AE0C5BC, + .control_efuse_1 = 0x4AE0C5C8, + .control_efuse_2 = 0x4AE0C5CC, + .control_efuse_3 = 0x4AE0C5D0, + .control_efuse_4 = 0x4AE0C5D4, + .control_efuse_13 = 0x4AE0C5F0, + .iodelay_config_base = 0x4844A000, +}; + +struct prcm_regs const omap5_es2_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_div_h21_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_div_h24_dpll_core = 0x4a00415c, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640, + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + .cm_l4per_clkstctrl = 0x4a009000, + .cm_l4per_dynamicdep = 0x4a009008, + .cm_l4per_adc_clkctrl = 0x4a009020, + .cm_l4per_gptimer10_clkctrl = 0x4a009028, + .cm_l4per_gptimer11_clkctrl = 0x4a009030, + .cm_l4per_gptimer2_clkctrl = 0x4a009038, + .cm_l4per_gptimer3_clkctrl = 0x4a009040, + .cm_l4per_gptimer4_clkctrl = 0x4a009048, + .cm_l4per_gptimer9_clkctrl = 0x4a009050, + .cm_l4per_elm_clkctrl = 0x4a009058, + .cm_l4per_gpio2_clkctrl = 0x4a009060, + .cm_l4per_gpio3_clkctrl = 0x4a009068, + .cm_l4per_gpio4_clkctrl = 0x4a009070, + .cm_l4per_gpio5_clkctrl = 0x4a009078, + .cm_l4per_gpio6_clkctrl = 0x4a009080, + .cm_l4per_hdq1w_clkctrl = 0x4a009088, + .cm_l4per_hecc1_clkctrl = 0x4a009090, + .cm_l4per_hecc2_clkctrl = 0x4a009098, + .cm_l4per_i2c1_clkctrl = 0x4a0090a0, + .cm_l4per_i2c2_clkctrl = 0x4a0090a8, + .cm_l4per_i2c3_clkctrl = 0x4a0090b0, + .cm_l4per_i2c4_clkctrl = 0x4a0090b8, + .cm_l4per_l4per_clkctrl = 0x4a0090c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, + .cm_l4per_mgate_clkctrl = 0x4a0090e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009100, + .cm_l4per_mcspi4_clkctrl = 0x4a009108, + .cm_l4per_gpio7_clkctrl = 0x4a009110, + .cm_l4per_gpio8_clkctrl = 0x4a009118, + .cm_l4per_mmcsd3_clkctrl = 0x4a009120, + .cm_l4per_mmcsd4_clkctrl = 0x4a009128, + .cm_l4per_msprohg_clkctrl = 0x4a009130, + .cm_l4per_slimbus2_clkctrl = 0x4a009138, + .cm_l4per_uart1_clkctrl = 0x4a009140, + .cm_l4per_uart2_clkctrl = 0x4a009148, + .cm_l4per_uart3_clkctrl = 0x4a009150, + .cm_l4per_uart4_clkctrl = 0x4a009158, + .cm_l4per_mmcsd5_clkctrl = 0x4a009160, + .cm_l4per_i2c5_clkctrl = 0x4a009168, + .cm_l4per_uart5_clkctrl = 0x4a009170, + .cm_l4per_uart6_clkctrl = 0x4a009178, + .cm_l4sec_clkstctrl = 0x4a009180, + .cm_l4sec_staticdep = 0x4a009184, + .cm_l4sec_dynamicdep = 0x4a009188, + .cm_l4sec_aes1_clkctrl = 0x4a0091a0, + .cm_l4sec_aes2_clkctrl = 0x4a0091a8, + .cm_l4sec_des3des_clkctrl = 0x4a0091b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, + .cm_l4sec_rng_clkctrl = 0x4a0091c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a009200, + .cm_ivahd_ivahd_clkctrl = 0x4a009220, + .cm_ivahd_sl2_clkctrl = 0x4a009228, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009300, + .cm_cam_iss_clkctrl = 0x4a009320, + .cm_cam_fdif_clkctrl = 0x4a009328, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009400, + .cm_dss_dss_clkctrl = 0x4a009420, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009500, + .cm_sgx_sgx_clkctrl = 0x4a009520, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009600, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009628, + .cm_l3init_hsmmc2_clkctrl = 0x4a009630, + .cm_l3init_hsi_clkctrl = 0x4a009638, + .cm_l3init_hsusbhost_clkctrl = 0x4a009658, + .cm_l3init_hsusbotg_clkctrl = 0x4a009660, + .cm_l3init_hsusbtll_clkctrl = 0x4a009668, + .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_sata_clkctrl = 0x4a009688, + .cm_l3init_fsusb_clkctrl = 0x4a0096d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0, + + /* prm irqstatus regs */ + .prm_irqstatus_mpu = 0x4ae06010, + .prm_irqstatus_mpu_2 = 0x4ae06014, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07900, + .cm_wkup_l4wkup_clkctrl = 0x4ae07920, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, + .cm_wkup_gpio1_clkctrl = 0x4ae07938, + .cm_wkup_gptimer1_clkctrl = 0x4ae07940, + .cm_wkup_gptimer12_clkctrl = 0x4ae07948, + .cm_wkup_synctimer_clkctrl = 0x4ae07950, + .cm_wkup_usim_clkctrl = 0x4ae07958, + .cm_wkup_sarram_clkctrl = 0x4ae07960, + .cm_wkup_keyboard_clkctrl = 0x4ae07978, + .cm_wkup_rtc_clkctrl = 0x4ae07980, + .cm_wkup_bandgap_clkctrl = 0x4ae07988, + .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, + .prm_rstctrl = 0x4ae07c00, + .prm_rstst = 0x4ae07c04, + .prm_rsttime = 0x4ae07c08, + .prm_vc_val_bypass = 0x4ae07ca0, + .prm_vc_cfg_i2c_mode = 0x4ae07cb4, + .prm_vc_cfg_i2c_clk = 0x4ae07cb8, + + .prm_abbldo_mpu_setup = 0x4ae07cdc, + .prm_abbldo_mpu_ctrl = 0x4ae07ce0, + .prm_abbldo_mm_setup = 0x4ae07ce4, + .prm_abbldo_mm_ctrl = 0x4ae07ce8, + + /* SCRM stuff, used by some boards */ + .scrm_auxclk0 = 0x4ae0a310, + .scrm_auxclk1 = 0x4ae0a314, +}; + +struct prcm_regs const dra7xx_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a005100, + .cm_clksel_abe = 0x4a005108, + .cm_dll_ctrl = 0x4a005110, + .cm_clkmode_dpll_core = 0x4a005120, + .cm_idlest_dpll_core = 0x4a005124, + .cm_autoidle_dpll_core = 0x4a005128, + .cm_clksel_dpll_core = 0x4a00512c, + .cm_div_m2_dpll_core = 0x4a005130, + .cm_div_m3_dpll_core = 0x4a005134, + .cm_div_h11_dpll_core = 0x4a005138, + .cm_div_h12_dpll_core = 0x4a00513c, + .cm_div_h13_dpll_core = 0x4a005140, + .cm_div_h14_dpll_core = 0x4a005144, + .cm_ssc_deltamstep_dpll_core = 0x4a005148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c, + .cm_div_h21_dpll_core = 0x4a005150, + .cm_div_h22_dpllcore = 0x4a005154, + .cm_div_h23_dpll_core = 0x4a005158, + .cm_div_h24_dpll_core = 0x4a00515c, + .cm_clkmode_dpll_mpu = 0x4a005160, + .cm_idlest_dpll_mpu = 0x4a005164, + .cm_autoidle_dpll_mpu = 0x4a005168, + .cm_clksel_dpll_mpu = 0x4a00516c, + .cm_div_m2_dpll_mpu = 0x4a005170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a005188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c, + .cm_bypclk_dpll_mpu = 0x4a00519c, + .cm_clkmode_dpll_iva = 0x4a0051a0, + .cm_idlest_dpll_iva = 0x4a0051a4, + .cm_autoidle_dpll_iva = 0x4a0051a8, + .cm_clksel_dpll_iva = 0x4a0051ac, + .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc, + .cm_bypclk_dpll_iva = 0x4a0051dc, + .cm_clkmode_dpll_abe = 0x4a0051e0, + .cm_idlest_dpll_abe = 0x4a0051e4, + .cm_autoidle_dpll_abe = 0x4a0051e8, + .cm_clksel_dpll_abe = 0x4a0051ec, + .cm_div_m2_dpll_abe = 0x4a0051f0, + .cm_div_m3_dpll_abe = 0x4a0051f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a005208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c, + .cm_clkmode_dpll_ddrphy = 0x4a005210, + .cm_idlest_dpll_ddrphy = 0x4a005214, + .cm_autoidle_dpll_ddrphy = 0x4a005218, + .cm_clksel_dpll_ddrphy = 0x4a00521c, + .cm_div_m2_dpll_ddrphy = 0x4a005220, + .cm_div_h11_dpll_ddrphy = 0x4a005228, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, + .cm_clkmode_dpll_dsp = 0x4a005234, + .cm_shadow_freq_config1 = 0x4a005260, + .cm_clkmode_dpll_gmac = 0x4a0052a8, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, + .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, + .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698, + .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0, + + /* cm1.mpu */ + .cm_mpu_mpu_clkctrl = 0x4a005320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a005400, + .cm_dsp_dsp_clkctrl = 0x4a005420, + + /* cm IPU */ + .cm_ipu_clkstctrl = 0x4a005540, + .cm_ipu_i2c5_clkctrl = 0x4a005578, + + /* prm irqstatus regs */ + .prm_irqstatus_mpu = 0x4ae06010, + .prm_irqstatus_mpu_2 = 0x4ae06014, + + /* cm2.ckgen */ + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_pcie_ref = 0x4a008200, + .cm_clkmode_apll_pcie = 0x4a00821c, + .cm_idlest_apll_pcie = 0x4a008220, + .cm_div_m2_apll_pcie = 0x4a008224, + .cm_clkvcoldo_apll_pcie = 0x4a008228, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_gpmc_clkctrl = 0x4a008728, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a008f00, + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_vip1_clkctrl = 0x4a009020, + .cm_cam_vip2_clkctrl = 0x4a009028, + .cm_cam_vip3_clkctrl = 0x4a009030, + .cm_cam_lvdsrx_clkctrl = 0x4a009038, + .cm_cam_csi1_clkctrl = 0x4a009040, + .cm_cam_csi2_clkctrl = 0x4a009048, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsusbhost_clkctrl = 0x4a009340, + .cm_l3init_hsusbotg_clkctrl = 0x4a009348, + .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_sata_clkctrl = 0x4a009388, + .cm_gmac_clkstctrl = 0x4a0093c0, + .cm_gmac_gmac_clkctrl = 0x4a0093d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, + .cm_l3init_usb_otg_ss2_clkctrl = 0x4a009340, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009700, + .cm_l4per_dynamicdep = 0x4a009708, + .cm_l4per_gptimer10_clkctrl = 0x4a009728, + .cm_l4per_gptimer11_clkctrl = 0x4a009730, + .cm_l4per_gptimer2_clkctrl = 0x4a009738, + .cm_l4per_gptimer3_clkctrl = 0x4a009740, + .cm_l4per_gptimer4_clkctrl = 0x4a009748, + .cm_l4per_gptimer9_clkctrl = 0x4a009750, + .cm_l4per_elm_clkctrl = 0x4a009758, + .cm_l4per_gpio2_clkctrl = 0x4a009760, + .cm_l4per_gpio3_clkctrl = 0x4a009768, + .cm_l4per_gpio4_clkctrl = 0x4a009770, + .cm_l4per_gpio5_clkctrl = 0x4a009778, + .cm_l4per_gpio6_clkctrl = 0x4a009780, + .cm_l4per_hdq1w_clkctrl = 0x4a009788, + .cm_l4per_i2c1_clkctrl = 0x4a0097a0, + .cm_l4per_i2c2_clkctrl = 0x4a0097a8, + .cm_l4per_i2c3_clkctrl = 0x4a0097b0, + .cm_l4per_i2c4_clkctrl = 0x4a0097b8, + .cm_l4per_l4per_clkctrl = 0x4a0097c0, + .cm_l4per_mcspi1_clkctrl = 0x4a0097f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0097f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009800, + .cm_l4per_mcspi4_clkctrl = 0x4a009808, + .cm_l4per_gpio7_clkctrl = 0x4a009810, + .cm_l4per_gpio8_clkctrl = 0x4a009818, + .cm_l4per_mmcsd3_clkctrl = 0x4a009820, + .cm_l4per_mmcsd4_clkctrl = 0x4a009828, + .cm_l4per_qspi_clkctrl = 0x4a009838, + .cm_l4per_uart1_clkctrl = 0x4a009840, + .cm_l4per_uart2_clkctrl = 0x4a009848, + .cm_l4per_uart3_clkctrl = 0x4a009850, + .cm_l4per_uart4_clkctrl = 0x4a009858, + .cm_l4per_uart5_clkctrl = 0x4a009870, + .cm_l4sec_clkstctrl = 0x4a009880, + .cm_l4sec_staticdep = 0x4a009884, + .cm_l4sec_dynamicdep = 0x4a009888, + .cm_l4sec_aes1_clkctrl = 0x4a0098a0, + .cm_l4sec_aes2_clkctrl = 0x4a0098a8, + .cm_l4sec_des3des_clkctrl = 0x4a0098b0, + .cm_l4sec_rng_clkctrl = 0x4a0098c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_abe_pll_sys_clksel = 0x4ae06118, + .cm_wkup_clkstctrl = 0x4ae07800, + .cm_wkup_l4wkup_clkctrl = 0x4ae07820, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, + .cm_wkup_gpio1_clkctrl = 0x4ae07838, + .cm_wkup_gptimer1_clkctrl = 0x4ae07840, + .cm_wkup_gptimer12_clkctrl = 0x4ae07848, + .cm_wkup_sarram_clkctrl = 0x4ae07860, + .cm_wkup_keyboard_clkctrl = 0x4ae07878, + .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .prm_rstctrl = 0x4ae07d00, + .prm_rstst = 0x4ae07d04, + .prm_rsttime = 0x4ae07d08, + .prm_io_pmctrl = 0x4ae07d20, + .prm_vc_val_bypass = 0x4ae07da0, + .prm_vc_cfg_i2c_mode = 0x4ae07db4, + .prm_vc_cfg_i2c_clk = 0x4ae07db8, + + .prm_abbldo_mpu_setup = 0x4AE07DDC, + .prm_abbldo_mpu_ctrl = 0x4AE07DE0, + .prm_abbldo_iva_setup = 0x4AE07E34, + .prm_abbldo_iva_ctrl = 0x4AE07E24, + .prm_abbldo_eve_setup = 0x4AE07E30, + .prm_abbldo_eve_ctrl = 0x4AE07E20, + .prm_abbldo_gpu_setup = 0x4AE07DE4, + .prm_abbldo_gpu_ctrl = 0x4AE07DE8, + + /*l3main1 edma*/ + .cm_l3main1_tptc1_clkctrl = 0x4a008778, + .cm_l3main1_tptc2_clkctrl = 0x4a008780, +}; + +void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits) +{ + u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 : + (*ctrl)->ctrl_core_sma_sw_0; + clrsetbits_le32(reg, clear_bits, set_bits); +} diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c new file mode 100644 index 00000000000..7712923d857 --- /dev/null +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -0,0 +1,742 @@ +/* + * Timing and Organization details of the ddr device parts used in OMAP5 + * EVM + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * Sricharan R + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* + * This file provides details of the LPDDR2 SDRAM parts used on OMAP5 + * EVM. Since the parts used and geometry are identical for + * evm for a given OMAP5 revision, this information is kept + * here instead of being in board directory. However the key functions + * exported are weakly linked so that they can be over-ridden in the board + * directory if there is a OMAP5 board in the future that uses a different + * memory device or geometry. + * + * For any new board with different memory devices over-ride one or more + * of the following functions as per the CONFIG flags you intend to enable: + * - emif_get_reg_dump() + * - emif_get_dmm_regs() + * - emif_get_device_details() + * - emif_get_device_timings() + */ + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +const struct emif_regs emif_regs_532_mhz_2cs = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000081A, + .sdram_tim1 = 0x772F6873, + .sdram_tim2 = 0x304a129a, + .sdram_tim3 = 0x02f7e45f, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x000b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E28420d, + .emif_ddr_phy_ctlr_1 = 0x0E28420d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, + .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, + .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040 +}; + +const struct emif_regs emif_regs_532_mhz_2cs_es2 = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000081A, + .sdram_tim1 = 0x772F6873, + .sdram_tim2 = 0x304a129a, + .sdram_tim3 = 0x02f7e45f, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x100b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E30400d, + .emif_ddr_phy_ctlr_1 = 0x0E30400d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, + .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, + .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, + .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33, +}; + +const struct emif_regs emif_regs_266_mhz_2cs = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0x2A86B419, + .sdram_tim2 = 0x1025094A, + .sdram_tim3 = 0x026BA22F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x000b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E28420d, + .emif_ddr_phy_ctlr_1 = 0x0E28420d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x0A414829, + .emif_ddr_ext_phy_ctrl_3 = 0x14829052, + .emif_ddr_ext_phy_ctrl_4 = 0x000520A4, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040 +}; + +const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020420A, + .emif_ddr_phy_ctlr_1 = 0x0024420A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x1007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0030400A, + .emif_ddr_phy_ctlr_1 = 0x0034400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x40000305 +}; + +const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) +{ + switch (omap_revision()) { + case OMAP5430_ES1_0: + *regs = &emif_regs_532_mhz_2cs; + break; + case OMAP5432_ES1_0: + *regs = &emif_regs_ddr3_532_mhz_1cs; + break; + case OMAP5430_ES2_0: + *regs = &emif_regs_532_mhz_2cs_es2; + break; + case OMAP5432_ES2_0: + default: + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + break; + } +} + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + default: + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + break; + } + +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); +#else + +static const struct lpddr2_device_details dev_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG +}; + +static void emif_get_device_details_sdp(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) +{ + /* EMIF1 & EMIF2 have identical configuration */ + *cs0_device_details = dev_4G_S4_details; + *cs1_device_details = dev_4G_S4_details; +} + +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) + __attribute__((weak, alias("emif_get_device_details_sdp"))); + +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +const u32 ext_phy_ctrl_const_base[] = { + 0x01004010, + 0x00001004, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000001, + 0x540A8150, + 0xA81502a0, + 0x002A0540, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000077, + 0x0 +}; + +const u32 ddr3_ext_phy_ctrl_const_base_es1[] = { + 0x01004010, + 0x00001004, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x0, + 0x0, + 0x0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057, + 0x0 +}; + +const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { + 0x50D4350D, + 0x00000D43, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057, + 0x0 +}; + +/* Ext phy ctrl 1-35 regs */ +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, + 0x00980098, + 0x00340034, + 0x00350035, + 0x00340034, + 0x00310031, + 0x00340034, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00480048, + 0x004A004A, + 0x00520052, + 0x00550055, + 0x00500050, + 0x00000000, + 0x00600020, + 0x40011080, + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 +}; + +/* Ext phy ctrl 1-35 regs */ +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, + 0x00980098, + 0x00330033, + 0x00330033, + 0x002F002F, + 0x00320032, + 0x00310031, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00520052, + 0x00520052, + 0x00470047, + 0x00490049, + 0x00500050, + 0x00000000, + 0x00600020, + 0x40011080, + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 +}; + +/* Ext phy ctrl 1-35 regs */ +const u32 +dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { + 0x10040100, + 0x00A400A4, + 0x00A900A9, + 0x00B000B0, + 0x00B000B0, + 0x00A400A4, + 0x00390039, + 0x00320032, + 0x00320032, + 0x00320032, + 0x00440044, + 0x00550055, + 0x00550055, + 0x00550055, + 0x00550055, + 0x007F007F, + 0x004D004D, + 0x00430043, + 0x00560056, + 0x00540054, + 0x00600060, + 0x0, + 0x00600020, + 0x40010080, + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 +}; + +const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { + 0x04040100, + 0x006B009F, + 0x006B00A2, + 0x006B00A8, + 0x006B00A8, + 0x006B00B2, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x00600073, + 0x00600071, + 0x0060007C, + 0x0060007E, + 0x00600084, + 0x00400053, + 0x00400051, + 0x0040005C, + 0x0040005E, + 0x00400064, + 0x00800080, + 0x00800080, + 0x40010080, + 0x08102040, + 0x005B008F, + 0x005B0092, + 0x005B0098, + 0x005B0098, + 0x005B00A2, + 0x00300043, + 0x00300041, + 0x0030004C, + 0x0030004E, + 0x00300054, + 0x00000077 +}; + +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, + .mr2 = 0x6, + .mr3 = 0x1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; + +void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, + const u32 **regs, + u32 *size) +{ + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + *regs = ext_phy_ctrl_const_base; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base); + break; + case OMAP5432_ES1_0: + *regs = ddr3_ext_phy_ctrl_const_base_es1; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1); + break; + case OMAP5432_ES2_0: + *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); + break; + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + if (emif_nr == 1) { + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1); + } else { + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2); + } + break; + case DRA722_ES1_0: + *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; + *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); + break; + case DRA722_ES2_0: + *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; + *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); + break; + default: + *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); + + } +} + +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} + +static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; + const u32 *ext_phy_ctrl_const_regs; + u32 i = 0; + u32 size; + + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + for (i = 0; i < size; i++) { + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); + } +} + +static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; + const u32 *ext_phy_ctrl_const_regs; + u32 i, hw_leveling, size, phy; + + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + + hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; + phy = regs->emif_ddr_phy_ctlr_1_init; + + emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); + + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); + + /* + * Copy the predefined PHY register values + * if leveling is disabled. + */ + if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK) + for (i = 1; i < 6; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK) + for (i = 6; i < 11; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK) + for (i = 11; i < 25; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (hw_leveling) { + /* + * Write the init value for HW levling to occur + */ + for (i = 21; i < 35; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } +} + +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + do_ext_phy_settings_omap5(base, regs); + else + do_ext_phy_settings_dra7(base, regs); +} + +#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +static const struct lpddr2_ac_timings timings_jedec_532_mhz = { + .max_freq = 532000000, + .RL = 8, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_min_tck min_tck = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_532_mhz +}; + +static const struct lpddr2_device_timings dev_4G_S4_timings = { + .ac_timings = ac_timings, + .min_tck = &min_tck, +}; + +/* + * List of status registers to be controlled back to control registers + * after initial leveling + * readreg, writereg + */ +const struct read_write_regs omap5_bug_00339_regs[] = { + { 8, 5 }, + { 9, 6 }, + { 10, 7 }, + { 14, 8 }, + { 15, 9 }, + { 16, 10 }, + { 11, 2 }, + { 12, 3 }, + { 13, 4 }, + { 17, 11 }, + { 18, 12 }, + { 19, 13 }, +}; + +const struct read_write_regs dra_bug_00339_regs[] = { + { 7, 7 }, + { 8, 8 }, + { 9, 9 }, + { 10, 10 }, + { 11, 11 }, + { 12, 2 }, + { 13, 3 }, + { 14, 4 }, + { 15, 5 }, + { 16, 6 }, + { 17, 12 }, + { 18, 13 }, + { 19, 14 }, + { 20, 15 }, + { 21, 16 }, + { 22, 17 }, + { 23, 18 }, + { 24, 19 }, + { 25, 20 }, + { 26, 21} +}; + +const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + const struct read_write_regs *bug_00339_regs_ptr = NULL; + + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + bug_00339_regs_ptr = omap5_bug_00339_regs; + *iterations = sizeof(omap5_bug_00339_regs)/ + sizeof(omap5_bug_00339_regs[0]); + break; + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + case DRA722_ES1_0: + case DRA722_ES2_0: + bug_00339_regs_ptr = dra_bug_00339_regs; + *iterations = sizeof(dra_bug_00339_regs)/ + sizeof(dra_bug_00339_regs[0]); + break; + default: + printf("\n Error: UnKnown SOC"); + } + + return bug_00339_regs_ptr; +} + +void emif_get_device_timings_sdp(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &dev_4G_S4_timings; + *cs1_device_timings = &dev_4G_S4_timings; +} + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) + __attribute__((weak, alias("emif_get_device_timings_sdp"))); + +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/mach-omap2/omap5/sec-fxns.c b/arch/arm/mach-omap2/omap5/sec-fxns.c new file mode 100644 index 00000000000..33d4ea4eaca --- /dev/null +++ b/arch/arm/mach-omap2/omap5/sec-fxns.c @@ -0,0 +1,126 @@ +/* + * + * Security related functions for OMAP5 class devices + * + * (C) Copyright 2016 + * Texas Instruments, + * + * Daniel Allred + * Harinarayan Bhatta + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include +#include +#include + +/* Index for signature PPA-based TI HAL APIs */ +#define PPA_HAL_SERVICES_START_INDEX (0x200) +#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25) +#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26) +#define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27) + +static u32 get_sec_mem_start(void) +{ + u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START; + u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE; + /* + * Total reserved region is all contiguous with protected + * region coming first, followed by the non-secure region. + * If 0x0 start address is given, we simply put the reserved + * region at the end of the external DRAM. + */ + if (sec_mem_start == 0) + sec_mem_start = + (CONFIG_SYS_SDRAM_BASE + + (omap_sdram_size() - sec_mem_size)); + return sec_mem_start; +} + +int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr, + uint32_t size, uint32_t access_perm, + uint32_t initiator_perm) +{ + int result = 1; + + /* + * Call PPA HAL API to do any other general firewall + * configuration for regions 1-6 of the EMIF firewall. + */ + debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__, + region_num, start_addr, size); + + result = secure_rom_call( + PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4, + (start_addr & 0xFFFFFFF0) | (region_num & 0x0F), + size, access_perm, initiator_perm); + + if (result != 0) { + puts("Secure EMIF Firewall Setup failed!\n"); + debug("Return Value = %x\n", result); + } + + return result; +} + +#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE < \ + CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE) +#error "TI Secure EMIF: Protected size cannot be larger than total size." +#endif +int secure_emif_reserve(void) +{ + int result = 1; + u32 sec_mem_start = get_sec_mem_start(); + u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE; + + /* If there is no protected region, there is no reservation to make */ + if (sec_prot_size == 0) + return 0; + + /* + * Call PPA HAL API to reserve a chunk of EMIF SDRAM + * for secure world use. This region should be carved out + * from use by any public code. EMIF firewall region 7 + * will be used to protect this block of memory. + */ + result = secure_rom_call( + PPA_SERV_HAL_SETUP_SEC_RESVD_REGION, + 0, 0, 2, sec_mem_start, sec_prot_size); + + if (result != 0) { + puts("SDRAM Firewall: Secure memory reservation failed!\n"); + debug("Return Value = %x\n", result); + } + + return result; +} + +int secure_emif_firewall_lock(void) +{ + int result = 1; + + /* + * Call PPA HAL API to lock the EMIF firewall configurations. + * After this API is called, none of the PPA HAL APIs for + * configuring the EMIF firewalls will be usable again (that + * is, calls to those APIs will return failure and have no + * effect). + */ + + result = secure_rom_call( + PPA_SERV_HAL_LOCK_EMIF_FW, + 0, 0, 0); + + if (result != 0) { + puts("Secure EMIF Firewall Lock failed!\n"); + debug("Return Value = %x\n", result); + } + + return result; +} diff --git a/arch/arm/mach-omap2/pipe3-phy.c b/arch/arm/mach-omap2/pipe3-phy.c new file mode 100644 index 00000000000..e02e3ec23ee --- /dev/null +++ b/arch/arm/mach-omap2/pipe3-phy.c @@ -0,0 +1,231 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "pipe3-phy.h" + +/* PLLCTRL Registers */ +#define PLL_STATUS 0x00000004 +#define PLL_GO 0x00000008 +#define PLL_CONFIGURATION1 0x0000000C +#define PLL_CONFIGURATION2 0x00000010 +#define PLL_CONFIGURATION3 0x00000014 +#define PLL_CONFIGURATION4 0x00000020 + +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 10 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN BIT(16) +#define PLL_LDOPWDN BIT(15) +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +/* PHY POWER CONTROL Register */ +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE + +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 + +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 + + +#define PLL_IDLE_TIME 100 /* in milliseconds */ +#define PLL_LOCK_TIME 100 /* in milliseconds */ + +static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) +{ + return __raw_readl(addr + offset); +} + +static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, + u32 data) +{ + __raw_writel(data, addr + offset); +} + +static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 + *pipe3) +{ + u32 rate; + struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; + + rate = get_sys_clk_freq(); + + for (; dpll_map->rate; dpll_map++) { + if (rate == dpll_map->rate) + return &dpll_map->params; + } + + printf("%s: No DPLL configuration for %u Hz SYS CLK\n", + __func__, rate); + return NULL; +} + + +static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_LOCK_TIME; + + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (val & PLL_LOCK) + break; + } while (--timeout); + + if (!(val & PLL_LOCK)) { + printf("%s: DPLL failed to lock\n", __func__); + return -EBUSY; + } + + return 0; +} + +static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) +{ + u32 val; + struct pipe3_dpll_params *dpll_params; + + dpll_params = omap_pipe3_get_dpll_params(phy); + if (!dpll_params) { + printf("%s: Invalid DPLL parameters\n", __func__); + return -EINVAL; + } + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGN_MASK; + val |= dpll_params->n << PLL_REGN_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val &= ~PLL_SELFREQDCO_MASK; + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGM_MASK; + val |= dpll_params->m << PLL_REGM_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); + val &= ~PLL_REGM_F_MASK; + val |= dpll_params->mf << PLL_REGM_F_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); + val &= ~PLL_SD_MASK; + val |= dpll_params->sd << PLL_SD_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); + + omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); + + return omap_pipe3_wait_lock(phy); +} + +static void omap_control_phy_power(struct omap_pipe3 *phy, int on) +{ + u32 val, rate; + + val = readl(phy->power_reg); + + rate = get_sys_clk_freq(); + rate = rate/1000000; + + if (on) { + val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val |= rate << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + } else { + val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + } + + writel(val, phy->power_reg); +} + +int phy_pipe3_power_on(struct omap_pipe3 *phy) +{ + int ret; + u32 val; + + /* Program the DPLL only if not locked */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (!(val & PLL_LOCK)) { + ret = omap_pipe3_dpll_program(phy); + if (ret) + return ret; + } else { + /* else just bring it out of IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + if (val & PLL_IDLE) { + val &= ~PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, + PLL_CONFIGURATION2, val); + ret = omap_pipe3_wait_lock(phy); + if (ret) + return ret; + } + } + + /* Power up the PHY */ + omap_control_phy_power(phy, 1); + + return 0; +} + +int phy_pipe3_power_off(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_IDLE_TIME; + + /* Power down the PHY */ + omap_control_phy_power(phy, 0); + + /* Put DPLL in IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val |= PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + /* wait for LDO and Oscillator to power down */ + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) + break; + } while (--timeout); + + if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { + printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", + __func__, val); + return -EBUSY; + } + + return 0; +} + diff --git a/arch/arm/mach-omap2/pipe3-phy.h b/arch/arm/mach-omap2/pipe3-phy.h new file mode 100644 index 00000000000..441f49a3f97 --- /dev/null +++ b/arch/arm/mach-omap2/pipe3-phy.h @@ -0,0 +1,36 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_PIPE3_PHY_H +#define __OMAP_PIPE3_PHY_H + +struct pipe3_dpll_params { + u16 m; + u8 n; + u8 freq:3; + u8 sd; + u32 mf; +}; + +struct pipe3_dpll_map { + unsigned long rate; + struct pipe3_dpll_params params; +}; + +struct omap_pipe3 { + void __iomem *pll_ctrl_base; + void __iomem *power_reg; + struct pipe3_dpll_map *dpll_map; +}; + + +int phy_pipe3_power_on(struct omap_pipe3 *phy); +int phy_pipe3_power_off(struct omap_pipe3 *pipe3); + +#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/mach-omap2/reset.c b/arch/arm/mach-omap2/reset.c new file mode 100644 index 00000000000..91ad031ddd3 --- /dev/null +++ b/arch/arm/mach-omap2/reset.c @@ -0,0 +1,29 @@ +/* + * + * Common layer for reset related functionality of OMAP based socs. + * + * (C) Copyright 2012 + * Texas Instruments, + * + * Sricharan R + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +void __weak reset_cpu(unsigned long ignored) +{ + writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); +} + +u32 __weak warm_reset(void) +{ + return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); +} + +void __weak setup_warmreset_time(void) +{ +} diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c new file mode 100644 index 00000000000..2c2d1bce363 --- /dev/null +++ b/arch/arm/mach-omap2/sata.c @@ -0,0 +1,93 @@ +/* + * TI SATA platform driver + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "pipe3-phy.h" + +static struct pipe3_dpll_map dpll_map_sata[] = { + {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ + {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ + {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ + {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ + {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ + { }, /* Terminator */ +}; + +struct omap_pipe3 sata_phy = { + .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, + /* .power_reg is updated at runtime */ + .dpll_map = dpll_map_sata, +}; + +int init_sata(int dev) +{ + int ret; + u32 val; + + u32 const clk_domains_sata[] = { + 0 + }; + + u32 const clk_modules_hw_auto_sata[] = { + (*prcm)->cm_l3init_ocp2scp3_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_sata[] = { + (*prcm)->cm_l3init_sata_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_sata, + clk_modules_hw_auto_sata, + clk_modules_explicit_en_sata, + 0); + + /* Enable optional functional clock for SATA */ + setbits_le32((*prcm)->cm_l3init_sata_clkctrl, + SATA_CLKCTRL_OPTFCLKEN_MASK); + + sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; + + /* Power up the PHY */ + phy_pipe3_power_on(&sata_phy); + + /* Enable SATA module, No Idle, No Standby */ + val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; + writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); + + ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); + + return ret; +} + +int reset_sata(int dev) +{ + return 0; +} + +/* On OMAP platforms SATA provides the SCSI subsystem */ +void scsi_init(void) +{ + init_sata(0); + scsi_scan(1); +} + +void scsi_bus_reset(void) +{ + ahci_reset((void __iomem *)DWC_AHSATA_BASE); + ahci_init((void __iomem *)DWC_AHSATA_BASE); +} diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c new file mode 100644 index 00000000000..246a2393dab --- /dev/null +++ b/arch/arm/mach-omap2/sec-common.c @@ -0,0 +1,139 @@ +/* + * + * Common security related functions for OMAP devices + * + * (C) Copyright 2016 + * Texas Instruments, + * + * Daniel Allred + * Andreas Dannenberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include +#include +#include + +/* Index for signature verify ROM API */ +#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E) + +static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN); + +u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...) +{ + int i; + u32 num_args; + va_list ap; + + va_start(ap, flag); + + num_args = va_arg(ap, u32); + + if (num_args > 4) + return 1; + + /* Copy args to aligned args structure */ + for (i = 0; i < num_args; i++) + secure_rom_call_args[i + 1] = va_arg(ap, u32); + + secure_rom_call_args[0] = num_args; + + va_end(ap); + + /* if data cache is enabled, flush the aligned args structure */ + flush_dcache_range( + (unsigned int)&secure_rom_call_args[0], + (unsigned int)&secure_rom_call_args[0] + + roundup(sizeof(secure_rom_call_args), ARCH_DMA_MINALIGN)); + + return omap_smc_sec(service, proc_id, flag, secure_rom_call_args); +} + +static u32 find_sig_start(char *image, size_t size) +{ + char *image_end = image + size; + char *sig_start_magic = "CERT_"; + int magic_str_len = strlen(sig_start_magic); + char *ch; + + while (--image_end > image) { + if (*image_end == '_') { + ch = image_end - magic_str_len + 1; + if (!strncmp(ch, sig_start_magic, magic_str_len)) + return (u32)ch; + } + } + return 0; +} + +int secure_boot_verify_image(void **image, size_t *size) +{ + int result = 1; + u32 cert_addr, sig_addr; + size_t cert_size; + + /* Perform cache writeback on input buffer */ + flush_dcache_range( + (u32)*image, + (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); + + cert_addr = (uint32_t)*image; + sig_addr = find_sig_start((char *)*image, *size); + + if (sig_addr == 0) { + printf("No signature found in image!\n"); + result = 1; + goto auth_exit; + } + + *size = sig_addr - cert_addr; /* Subtract out the signature size */ + cert_size = *size; + + /* Check if image load address is 32-bit aligned */ + if (!IS_ALIGNED(cert_addr, 4)) { + printf("Image is not 4-byte aligned!\n"); + result = 1; + goto auth_exit; + } + + /* Image size also should be multiple of 4 */ + if (!IS_ALIGNED(cert_size, 4)) { + printf("Image size is not 4-byte aligned!\n"); + result = 1; + goto auth_exit; + } + + /* Call ROM HAL API to verify certificate signature */ + debug("%s: load_addr = %x, size = %x, sig_addr = %x\n", __func__, + cert_addr, cert_size, sig_addr); + + result = secure_rom_call( + API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0, + 4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF); +auth_exit: + if (result != 0) { + printf("Authentication failed!\n"); + printf("Return Value = %08X\n", result); + hang(); + } + + /* + * Output notification of successful authentication as well the name of + * the signing certificate used to re-assure the user that the secure + * code is being processed as expected. However suppress any such log + * output in case of building for SPL and booting via YMODEM. This is + * done to avoid disturbing the YMODEM serial protocol transactions. + */ + if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && + spl_boot_device() == BOOT_DEVICE_UART)) + printf("Authentication passed: %s\n", (char *)sig_addr); + + return result; +} diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c new file mode 100644 index 00000000000..49e3a971d96 --- /dev/null +++ b/arch/arm/mach-omap2/timer.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2008 + * Texas Instruments + * + * Richard Woodruff + * Syed Moahmmed Khasim + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; + +/* + * Nothing really to do with interrupts, just starts up a counter. + */ + +#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) +#define TIMER_OVERFLOW_VAL 0xffffffff +#define TIMER_LOAD_VAL 0 + +int timer_init(void) +{ + /* start the counter ticking up, reload value on overflow */ + writel(TIMER_LOAD_VAL, &timer_base->tldr); + /* enable timer */ + writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, + &timer_base->tclr); + + return 0; +} + +/* + * timer without interrupts + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* delay x useconds */ +void __udelay(unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&timer_base->tcrr); + + while (tmo > 0) { + now = readl(&timer_base->tcrr); + if (last > now) /* count up timer overflow */ + tmo -= TIMER_OVERFLOW_VAL - last + now + 1; + else + tmo -= now - last; + last = now; + } +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ + /* move stamp fordward with absoulte diff ticks */ + gd->arch.tbl += (now - gd->arch.lastinc); + } else { /* we have rollover of incrementer */ + gd->arch.tbl += ((TIMER_OVERFLOW_VAL / (TIMER_CLOCK / + CONFIG_SYS_HZ)) - gd->arch.lastinc) + now; + } + gd->arch.lastinc = now; + return gd->arch.tbl; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds new file mode 100644 index 00000000000..8fec715ca56 --- /dev/null +++ b/arch/arm/mach-omap2/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/armv7/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c new file mode 100644 index 00000000000..2d03ebfbd3d --- /dev/null +++ b/arch/arm/mach-omap2/utils.c @@ -0,0 +1,113 @@ +/* + * Copyright 2011 Linaro Limited + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +static void do_cancel_out(u32 *num, u32 *den, u32 factor) +{ + while (1) { + if (((*num)/factor*factor == (*num)) && + ((*den)/factor*factor == (*den))) { + (*num) /= factor; + (*den) /= factor; + } else + break; + } +} + +/* + * Cancel out the denominator and numerator of a fraction + * to get smaller numerator and denominator. + */ +void cancel_out(u32 *num, u32 *den, u32 den_limit) +{ + do_cancel_out(num, den, 2); + do_cancel_out(num, den, 3); + do_cancel_out(num, den, 5); + do_cancel_out(num, den, 7); + do_cancel_out(num, den, 11); + do_cancel_out(num, den, 13); + do_cancel_out(num, den, 17); + while ((*den) > den_limit) { + *num /= 2; + /* + * Round up the denominator so that the final fraction + * (num/den) is always <= the desired value + */ + *den = (*den + 1) / 2; + } +} + +__weak void omap_die_id(unsigned int *die_id) +{ + die_id[0] = die_id[1] = die_id[2] = die_id[3] = 0; +} + +void omap_die_id_serial(void) +{ + unsigned int die_id[4] = { 0 }; + char serial_string[17] = { 0 }; + + omap_die_id((unsigned int *)&die_id); + + if (!getenv("serial#")) { + snprintf(serial_string, sizeof(serial_string), + "%08x%08x", die_id[0], die_id[3]); + + setenv("serial#", serial_string); + } +} + +void omap_die_id_get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + unsigned long long serial; + + serial_string = getenv("serial#"); + + if (serial_string) { + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (unsigned int) (serial >> 32); + serialnr->low = (unsigned int) (serial & 0xffffffff); + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} + +void omap_die_id_usbethaddr(void) +{ + unsigned int die_id[4] = { 0 }; + unsigned char mac[6] = { 0 }; + + omap_die_id((unsigned int *)&die_id); + + if (!getenv("usbethaddr")) { + /* + * Create a fake MAC address from the processor ID code. + * First byte is 0x02 to signify locally administered. + */ + mac[0] = 0x02; + mac[1] = die_id[3] & 0xff; + mac[2] = die_id[2] & 0xff; + mac[3] = die_id[1] & 0xff; + mac[4] = die_id[0] & 0xff; + mac[5] = (die_id[0] >> 8) & 0xff; + + eth_setenv_enetaddr("usbethaddr", mac); + } +} + +void omap_die_id_display(void) +{ + unsigned int die_id[4] = { 0 }; + + omap_die_id(die_id); + + printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2], + die_id[1], die_id[0]); +} diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c new file mode 100644 index 00000000000..a68f1d145dc --- /dev/null +++ b/arch/arm/mach-omap2/vc.c @@ -0,0 +1,151 @@ +/* + * Voltage Controller implementation for OMAP + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* + * Define Master code if there are multiple masters on the I2C_SR bus. + * Normally not required + */ +#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE +#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0 +#endif + +/* Register defines and masks for VC IP Block */ +/* PRM_VC_CFG_I2C_MODE */ +#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6) +#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4) +#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3) +#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0 +#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24 +#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16 +#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24) +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +/** + * omap_vc_init() - Initialization for Voltage controller + * @speed_khz: I2C buspeed in KHz + */ +static void omap_vc_init(u16 speed_khz) +{ + u32 val; + u32 sys_clk_khz, cycles_hi, cycles_low; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + if (speed_khz > 400) { + puts("higher speed requested - throttle to 400Khz\n"); + speed_khz = 400; + } + + /* + * Setup the dedicated I2C controller for Voltage Control + * I2C clk - high period 40% low period 60% + */ + speed_khz /= 10; + cycles_hi = sys_clk_khz * 4 / speed_khz; + cycles_low = sys_clk_khz * 6 / speed_khz; + /* values to be set in register - less by 5 & 7 respectively */ + cycles_hi -= 5; + cycles_low -= 7; + val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | + (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); + writel(val, (*prcm)->prm_vc_cfg_i2c_clk); + + val = CONFIG_OMAP_VC_I2C_HS_MCODE << + PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; + /* No HS mode for now */ + val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; + writel(val, (*prcm)->prm_vc_cfg_i2c_mode); +} + +/** + * omap_vc_bypass_send_value() - Send a data using VC Bypass command + * @sa: 7 bit I2C slave address of the PMIC + * @reg_addr: I2C register address(8 bit) address in PMIC + * @reg_data: what 8 bit data to write + */ +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) +{ + /* + * Unfortunately we need to loop here instead of a defined time + * use arbitary large value + */ + u32 timeout = 0xFFFF; + u32 reg_val; + + sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK; + reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; + reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; + + /* program VC to send data */ + reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | + reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | + reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; + writel(reg_val, (*prcm)->prm_vc_val_bypass); + + /* Signal VC to send data */ + writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, + (*prcm)->prm_vc_val_bypass); + + /* Wait on VC to complete transmission */ + do { + reg_val = readl((*prcm)->prm_vc_val_bypass) & + PRM_VC_VAL_BYPASS_VALID_BIT; + if (!reg_val) + break; + + sdelay(100); + } while (--timeout); + + /* Optional: cleanup PRM_IRQSTATUS_Ax */ + /* In case we can do something about it in future.. */ + if (!timeout) + return -1; + + /* All good.. */ + return 0; +} + +void sri2c_init(void) +{ + static int sri2c = 1; + + if (sri2c) { + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + sri2c = 0; + } + return; +} diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ec70b72970e..8fa8e39f71e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -213,7 +213,7 @@ /* USB gadget RNDIS */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #endif #ifdef CONFIG_NAND diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 32aa392e8b4..16fb1ae8aa6 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -123,7 +123,7 @@ #undef CONFIG_USE_IRQ /* SPL */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 553aaa38a8c..48353e9d3d3 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -280,7 +280,7 @@ /* SPL */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #ifndef CONFIG_SPL_USBETH_SUPPORT #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 9795d4112ba..ca5bb1a77da 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -86,7 +86,7 @@ #define CONFIG_BOOTCOUNT_AM33XX #define CONFIG_SYS_BOOTCOUNT_BE -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #ifndef CONFIG_SPL_USBETH_SUPPORT #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 2f20e10eff9..2dbbd7a7757 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -281,7 +281,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index a4ae5453b2f..2178c8a68f4 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -341,6 +341,6 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 20f207c3f3a..0a6c06a4bba 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -82,7 +82,7 @@ #define FAT_ENV_FILE "uboot.env" #define CONFIG_FAT_WRITE -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* SPL USB Support */ diff --git a/include/configs/baltos.h b/include/configs/baltos.h index e69c1b63c14..8efd513f324 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -224,7 +224,7 @@ /* General network SPL, both CPSW and USB gadget RNDIS */ #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index ac47decb638..2f51e2cd5ae 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -357,7 +357,7 @@ DEFAULT_LINUX_BOOT_ENV \ /* USB gadget RNDIS */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #endif #ifdef CONFIG_NAND diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index e425cb91930..90698614d9a 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -113,6 +113,6 @@ /* General parts of the framework, required. */ #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 7eed776f62f..ae4f287e4d4 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -104,7 +104,7 @@ #define CONFIG_SYS_I2C_EEPROM_BUS 0 /* SPL */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" /* Network. */ #define CONFIG_PHY_GIGE diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 201711d987f..cbb0d0b8f33 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -300,7 +300,7 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 5ec4926dd8e..9c24ba99654 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -103,7 +103,7 @@ #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_ENV_SPI_MAX_HZ 48000000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 0662053f859..dce44387979 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -25,7 +25,7 @@ * or 64KB */ #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_STACK 0x0091FFB8 diff --git a/include/configs/kc1.h b/include/configs/kc1.h index f8078eff942..a66d462706b 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -126,7 +126,7 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2 diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 7db9e5a1dd6..d5b7dfb391d 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -316,7 +316,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index f4f4e4917a5..a5065e209d7 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -340,7 +340,7 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index ef081b259be..aff4635e90e 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -120,7 +120,7 @@ /* CPU */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #ifdef CONFIG_SPI_BOOT #define CONFIG_SPL_SPI_LOAD diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 4130f535823..f1db204910d 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -207,6 +207,6 @@ /* CPSW support */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #endif /* ! __CONFIG_PENGWYN_H */ diff --git a/include/configs/pepper.h b/include/configs/pepper.h index e99188fc43e..d9c84f27ea9 100644 --- a/include/configs/pepper.h +++ b/include/configs/pepper.h @@ -90,6 +90,6 @@ #define CONFIG_PHY_RESET_DELAY 1000 /* SPL */ -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #endif /* __CONFIG_PEPPER_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 31fcc947dde..066c24136c4 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -136,7 +136,7 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_AM33XX_BCH diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 7fada3fec0a..264279fc424 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -134,7 +134,7 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 098c9bcc6c2..6f58a97d33d 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -198,7 +198,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 861e5027754..6219a44595e 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -284,7 +284,7 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index a5dc91b3bae..9a9faebc608 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -166,7 +166,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 381e9a37175..14c254296f2 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -130,7 +130,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index d607f407fdf..0ad32353bae 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -68,7 +68,7 @@ /* SPL */ #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (64 << 20)) diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 3d2992f737d..aa17c09ce96 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -148,7 +148,7 @@ * So moving TEXT_BASE down to non-HS limit. */ #define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index b85fae39bcc..8322f645fe9 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -158,7 +158,7 @@ #define CONFIG_SPL_TEXT_BASE 0x40300000 #endif -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index fbef1f0e410..9a3d224e39e 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -315,7 +315,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -- cgit v1.3.1 From 187f9dc3f70f827fe0742d5345067fcabd1cca6b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 7 Nov 2016 21:34:55 -0500 Subject: TI: Remove CONFIG_OMAP_COMMON in favor of CONFIG_ARCH_OMAP2 With the move to arch/arm/mach-omap2 there are now very few uses of CONFIG_OMAP_COMMON and further they can all be replaced with CONFIG_ARCH_OMAP2, so do so. Signed-off-by: Tom Rini --- arch/arm/config.mk | 2 +- arch/arm/include/asm/global_data.h | 2 +- arch/arm/include/asm/ti-common/sys_proto.h | 2 +- include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/bur_am335x_common.h | 1 - include/configs/cm_t335.h | 2 -- include/configs/cm_t35.h | 1 - include/configs/cm_t3517.h | 1 - include/configs/kc1.h | 1 - include/configs/mcx.h | 1 - include/configs/nokia_rx51.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/siemens-am33x-common.h | 1 - include/configs/sniper.h | 1 - include/configs/tam3517-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 1 - include/configs/ti_armv7_omap.h | 1 - include/configs/tricorder.h | 1 - 21 files changed, 3 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 27914a95b96..008da39a6c0 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -6,7 +6,7 @@ # ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_OMAP_COMMON),) +ifneq ($(CONFIG_ARCH_OMAP2),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 10550174df4..aee87cdcbf9 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -60,7 +60,7 @@ struct arch_global_data { unsigned long tlb_allocated; #endif -#ifdef CONFIG_OMAP_COMMON +#ifdef CONFIG_ARCH_OMAP2 u32 omap_boot_device; u32 omap_boot_mode; u8 omap_ch_flags; diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h index 2bdb71cfe8e..60d1160459b 100644 --- a/arch/arm/include/asm/ti-common/sys_proto.h +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -9,7 +9,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_OMAP_COMMON +#ifdef CONFIG_ARCH_OMAP2 #define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000 #define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 2dbbd7a7757..07ef9e98e90 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -18,7 +18,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 2178c8a68f4..ad56d240c1e 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -16,7 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 90698614d9a..7afffa2ec64 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,7 +14,6 @@ /* ------------------------------------------------------------------------- */ #define CONFIG_AM33XX #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index ae4f287e4d4..8f24174a21e 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -25,8 +25,6 @@ #undef CONFIG_MAX_RAM_BANK_SIZE #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ -#define CONFIG_OMAP_COMMON - #define MACH_TYPE_CM_T335 4586 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index cbb0d0b8f33..da5a4b3fb8a 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -25,7 +25,6 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index edb52be5a83..1e2a4770275 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -15,7 +15,6 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_CM_T3517 /* working with CM-T3517 */ -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/kc1.h b/include/configs/kc1.h index a66d462706b..76f2b8b7b4a 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -31,7 +31,6 @@ #define CONFIG_OMAP #define CONFIG_OMAP4430 -#define CONFIG_OMAP_COMMON /* * Board diff --git a/include/configs/mcx.h b/include/configs/mcx.h index d5b7dfb391d..0c6b1e89fc1 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -15,7 +15,6 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index d1230a56f41..4d5265f5409 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -27,7 +27,6 @@ #define CONFIG_OMAP3430 /* which is in a 3430 */ #define CONFIG_OMAP3_RX51 /* working with RX51 */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index a5065e209d7..6388a9ccaf6 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -92,7 +92,6 @@ */ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 066c24136c4..456429694e7 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -16,7 +16,6 @@ #define CONFIG_AM33XX #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON #include diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 264279fc424..e12b1013339 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -26,7 +26,6 @@ */ #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON /* * Board diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 6f58a97d33d..ff0c60d01cf 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -15,7 +15,6 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 6219a44595e..a873e7b553d 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -19,7 +19,6 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 9a9faebc608..6a5ed196bf1 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -20,7 +20,6 @@ #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON #include diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 14c254296f2..5db4c605466 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -14,7 +14,6 @@ #define CONFIG_TI816X #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h index 7548170afcf..6d9d4b2d97a 100644 --- a/include/configs/ti_armv7_omap.h +++ b/include/configs/ti_armv7_omap.h @@ -14,7 +14,6 @@ /* Common defines for all OMAP architecture based SoCs */ #define CONFIG_OMAP -#define CONFIG_OMAP_COMMON /* I2C IP block */ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 9a3d224e39e..07a92ebcf8c 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -19,7 +19,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP_COMMON /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 -- cgit v1.3.1 From 5300a4f9336291fb713fcfaf9ea6e51b71824800 Mon Sep 17 00:00:00 2001 From: Andrew Duda Date: Tue, 8 Nov 2016 18:53:39 +0000 Subject: rsa: cosmetic: rename pad_len to key_len checksum_algo's pad_len field isn't actually used to store the length of the padding but the total length of the RSA key (msg_len + pad_len) Signed-off-by: Andrew Duda Signed-off-by: aduda Reviewed-by: Simon Glass --- include/image.h | 2 +- lib/rsa/rsa-verify.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index 2b1296c86c9..bfe10a0190c 100644 --- a/include/image.h +++ b/include/image.h @@ -1070,7 +1070,7 @@ struct image_region { struct checksum_algo { const char *name; const int checksum_len; - const int pad_len; + const int key_len; #if IMAGE_ENABLE_SIGN const EVP_MD *(*calculate_sign)(void); #endif diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 442b7695639..5418f594aec 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -84,7 +84,7 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, } padding = algo->rsa_padding; - pad_len = algo->pad_len - algo->checksum_len; + pad_len = algo->key_len - algo->checksum_len; /* Check pkcs1.5 padding bytes. */ if (memcmp(buf, padding, pad_len)) { @@ -160,7 +160,7 @@ int rsa_verify(struct image_sign_info *info, { const void *blob = info->fdt_blob; /* Reserve memory for maximum checksum-length */ - uint8_t hash[info->algo->checksum->pad_len]; + uint8_t hash[info->algo->checksum->key_len]; int ndepth, noffset; int sig_node, node; char name[100]; @@ -171,7 +171,7 @@ int rsa_verify(struct image_sign_info *info, * rsa-signature-length */ if (info->algo->checksum->checksum_len > - info->algo->checksum->pad_len) { + info->algo->checksum->key_len) { debug("%s: invlaid checksum-algorithm %s for %s\n", __func__, info->algo->checksum->name, info->algo->name); return -EINVAL; -- cgit v1.3.1 From da29f2991d75fc8aa3289407a0e686a4a22f8c9e Mon Sep 17 00:00:00 2001 From: Andrew Duda Date: Tue, 8 Nov 2016 18:53:40 +0000 Subject: rsa: Verify RSA padding programatically Padding verification was done against static SHA/RSA pair arrays which take up a lot of static memory, are mostly 0xff, and cannot be reused for additional SHA/RSA pairings. The padding can be easily computed according to PKCS#1v2.1 as: EM = 0x00 || 0x01 || PS || 0x00 || T where PS is (emLen - tLen - 3) octets of 0xff and T is DER encoding of the hash. Store DER prefix in checksum_algo and create rsa_verify_padding function to handle verification of a message for any SHA/RSA pairing. Signed-off-by: Andrew Duda Signed-off-by: aduda Reviewed-by: Simon Glass --- common/image-sig.c | 9 ++-- include/image.h | 3 +- include/u-boot/rsa-checksum.h | 4 -- include/u-boot/sha1.h | 3 ++ include/u-boot/sha256.h | 3 ++ lib/rsa/rsa-checksum.c | 121 ------------------------------------------ lib/rsa/rsa-verify.c | 38 ++++++++++++- lib/sha1.c | 5 ++ lib/sha256.c | 6 +++ 9 files changed, 61 insertions(+), 131 deletions(-) (limited to 'include') diff --git a/common/image-sig.c b/common/image-sig.c index 28f7a20cadf..008d2c56d1d 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -34,32 +34,35 @@ struct checksum_algo checksum_algos[] = { { "sha1", SHA1_SUM_LEN, + SHA1_DER_LEN, + sha1_der_prefix, RSA2048_BYTES, #if IMAGE_ENABLE_SIGN EVP_sha1, #endif hash_calculate, - padding_sha1_rsa2048, }, { "sha256", SHA256_SUM_LEN, + SHA256_DER_LEN, + sha256_der_prefix, RSA2048_BYTES, #if IMAGE_ENABLE_SIGN EVP_sha256, #endif hash_calculate, - padding_sha256_rsa2048, }, { "sha256", SHA256_SUM_LEN, + SHA256_DER_LEN, + sha256_der_prefix, RSA4096_BYTES, #if IMAGE_ENABLE_SIGN EVP_sha256, #endif hash_calculate, - padding_sha256_rsa4096, } }; diff --git a/include/image.h b/include/image.h index bfe10a0190c..de73a071d98 100644 --- a/include/image.h +++ b/include/image.h @@ -1070,6 +1070,8 @@ struct image_region { struct checksum_algo { const char *name; const int checksum_len; + const int der_len; + const uint8_t *der_prefix; const int key_len; #if IMAGE_ENABLE_SIGN const EVP_MD *(*calculate_sign)(void); @@ -1077,7 +1079,6 @@ struct checksum_algo { int (*calculate)(const char *name, const struct image_region region[], int region_count, uint8_t *checksum); - const uint8_t *rsa_padding; }; struct image_sig_algo { diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h index 3c69d85ecba..c2407202496 100644 --- a/include/u-boot/rsa-checksum.h +++ b/include/u-boot/rsa-checksum.h @@ -12,10 +12,6 @@ #include #include -extern const uint8_t padding_sha256_rsa4096[]; -extern const uint8_t padding_sha256_rsa2048[]; -extern const uint8_t padding_sha1_rsa2048[]; - /** * hash_calculate() - Calculate hash over the data * diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index b0d9ce9db9d..2634a29c20d 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -21,6 +21,9 @@ extern "C" { #define SHA1_SUM_POS -0x20 #define SHA1_SUM_LEN 20 +#define SHA1_DER_LEN 15 + +extern const uint8_t sha1_der_prefix[]; /** * \brief SHA-1 context structure diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index beadab35ffc..9aa1251789a 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -2,6 +2,9 @@ #define _SHA256_H #define SHA256_SUM_LEN 32 +#define SHA256_DER_LEN 19 + +extern const uint8_t sha256_der_prefix[]; /* Reset watchdog each time we process this many bytes */ #define CHUNKSZ_SHA256 (64 * 1024) diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c index db183ff2930..2bf28e2dafb 100644 --- a/lib/rsa/rsa-checksum.c +++ b/lib/rsa/rsa-checksum.c @@ -13,130 +13,9 @@ #include #else #include "fdt_host.h" -#include -#include #endif #include -/* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */ - -const uint8_t padding_sha256_rsa2048[RSA2048_BYTES - SHA256_SUM_LEN] = { -0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, -0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, -0x00, 0x04, 0x20 -}; - -const uint8_t padding_sha1_rsa2048[RSA2048_BYTES - SHA1_SUM_LEN] = { - 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30, - 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, - 0x05, 0x00, 0x04, 0x14 -}; - -const uint8_t padding_sha256_rsa4096[RSA4096_BYTES - SHA256_SUM_LEN] = { - 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, - 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, - 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 -}; - int hash_calculate(const char *name, const struct image_region region[], int region_count, uint8_t *checksum) diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 5418f594aec..ee8988d6463 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -24,6 +24,40 @@ /* Default public exponent for backward compatibility */ #define RSA_DEFAULT_PUBEXP 65537 +/** + * rsa_verify_padding() - Verify RSA message padding is valid + * + * Verify a RSA message's padding is consistent with PKCS1.5 + * padding as described in the RSA PKCS#1 v2.1 standard. + * + * @msg: Padded message + * @pad_len: Number of expected padding bytes + * @algo: Checksum algo structure having information on DER encoding etc. + * @return 0 on success, != 0 on failure + */ +static int rsa_verify_padding(const uint8_t *msg, const int pad_len, + struct checksum_algo *algo) +{ + int ff_len; + int ret; + + /* first byte must be 0x00 */ + ret = *msg++; + /* second byte must be 0x01 */ + ret |= *msg++ ^ 0x01; + /* next ff_len bytes must be 0xff */ + ff_len = pad_len - algo->der_len - 3; + ret |= *msg ^ 0xff; + ret |= memcmp(msg, msg+1, ff_len-1); + msg += ff_len; + /* next byte must be 0x00 */ + ret |= *msg++; + /* next der_len bytes must match der_prefix */ + ret |= memcmp(msg, algo->der_prefix, algo->der_len); + + return ret; +} + /** * rsa_verify_key() - Verify a signature against some data using RSA Key * @@ -83,11 +117,11 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, return ret; } - padding = algo->rsa_padding; pad_len = algo->key_len - algo->checksum_len; /* Check pkcs1.5 padding bytes. */ - if (memcmp(buf, padding, pad_len)) { + ret = rsa_verify_padding(buf, pad_len, algo); + if (ret) { debug("In RSAVerify(): Padding check failed!\n"); return -EINVAL; } diff --git a/lib/sha1.c b/lib/sha1.c index 72c5dea14f0..f54bb5be981 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -26,6 +26,11 @@ #include #include +const uint8_t sha1_der_prefix[SHA1_DER_LEN] = { + 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, + 0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14 +}; + /* * 32-bit integer manipulation macros (big endian) */ diff --git a/lib/sha256.c b/lib/sha256.c index bb338baefa8..7f5a3618d0d 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -15,6 +15,12 @@ #include #include +const uint8_t sha256_der_prefix[SHA256_DER_LEN] = { + 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, + 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, + 0x00, 0x04, 0x20 +}; + /* * 32-bit integer manipulation macros (big endian) */ -- cgit v1.3.1 From 0c1d74fda7c0063eeca4d8d9fa8674e6ec2ef685 Mon Sep 17 00:00:00 2001 From: Andrew Duda Date: Tue, 8 Nov 2016 18:53:41 +0000 Subject: image: Add crypto_algo struct for RSA info Cut down on the repetition of algorithm information by defining separate checksum and crypto structs. image_sig_algos are now simply pairs of unique checksum and crypto algos. Signed-off-by: Andrew Duda Signed-off-by: aduda Reviewed-by: Simon Glass --- common/image-sig.c | 46 +++++++++++++++++++++++----------------------- include/image.h | 9 +++++++-- lib/rsa/rsa-verify.c | 19 +++++++++++-------- tools/image-host.c | 9 +++++---- 4 files changed, 46 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/common/image-sig.c b/common/image-sig.c index 008d2c56d1d..8b4314de09d 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -36,7 +36,6 @@ struct checksum_algo checksum_algos[] = { SHA1_SUM_LEN, SHA1_DER_LEN, sha1_der_prefix, - RSA2048_BYTES, #if IMAGE_ENABLE_SIGN EVP_sha1, #endif @@ -47,22 +46,28 @@ struct checksum_algo checksum_algos[] = { SHA256_SUM_LEN, SHA256_DER_LEN, sha256_der_prefix, - RSA2048_BYTES, #if IMAGE_ENABLE_SIGN EVP_sha256, #endif hash_calculate, + } + +}; + +struct crypto_algo crypto_algos[] = { + { + "rsa2048", + RSA2048_BYTES, + rsa_sign, + rsa_add_verify_data, + rsa_verify, }, { - "sha256", - SHA256_SUM_LEN, - SHA256_DER_LEN, - sha256_der_prefix, + "rsa4096", RSA4096_BYTES, -#if IMAGE_ENABLE_SIGN - EVP_sha256, -#endif - hash_calculate, + rsa_sign, + rsa_add_verify_data, + rsa_verify, } }; @@ -70,24 +75,18 @@ struct checksum_algo checksum_algos[] = { struct image_sig_algo image_sig_algos[] = { { "sha1,rsa2048", - rsa_sign, - rsa_add_verify_data, - rsa_verify, + &crypto_algos[0], &checksum_algos[0], }, { "sha256,rsa2048", - rsa_sign, - rsa_add_verify_data, - rsa_verify, + &crypto_algos[0], &checksum_algos[1], }, { "sha256,rsa4096", - rsa_sign, - rsa_add_verify_data, - rsa_verify, - &checksum_algos[2], + &crypto_algos[1], + &checksum_algos[1], } }; @@ -197,7 +196,8 @@ int fit_image_check_sig(const void *fit, int noffset, const void *data, region.data = data; region.size = size; - if (info.algo->verify(&info, ®ion, 1, fit_value, fit_value_len)) { + if (info.algo->crypto->verify(&info, ®ion, 1, fit_value, + fit_value_len)) { *err_msgp = "Verification failed"; return -1; } @@ -378,8 +378,8 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode, struct image_region region[count]; fit_region_make_list(fit, fdt_regions, count, region); - if (info.algo->verify(&info, region, count, fit_value, - fit_value_len)) { + if (info.algo->crypto->verify(&info, region, count, fit_value, + fit_value_len)) { *err_msgp = "Verification failed"; return -1; } diff --git a/include/image.h b/include/image.h index de73a071d98..c3c98667381 100644 --- a/include/image.h +++ b/include/image.h @@ -1072,7 +1072,6 @@ struct checksum_algo { const int checksum_len; const int der_len; const uint8_t *der_prefix; - const int key_len; #if IMAGE_ENABLE_SIGN const EVP_MD *(*calculate_sign)(void); #endif @@ -1081,8 +1080,9 @@ struct checksum_algo { int region_count, uint8_t *checksum); }; -struct image_sig_algo { +struct crypto_algo { const char *name; /* Name of algorithm */ + const int key_len; /** * sign() - calculate and return signature for given input data @@ -1131,7 +1131,12 @@ struct image_sig_algo { int (*verify)(struct image_sign_info *info, const struct image_region region[], int region_count, uint8_t *sig, uint sig_len); +}; +struct image_sig_algo { + const char *name; + /* pointer to cryptosystem algorithm */ + struct crypto_algo *crypto; /* pointer to checksum algorithm */ struct checksum_algo *checksum; }; diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index ee8988d6463..61dc4c2e706 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -68,14 +68,14 @@ static int rsa_verify_padding(const uint8_t *msg, const int pad_len, * @sig: Signature * @sig_len: Number of bytes in signature * @hash: Pointer to the expected hash - * @algo: Checksum algo structure having information on RSA padding etc. + * @key_len: Number of bytes in rsa key + * @algo: Checksum algo structure having information on DER encoding etc. * @return 0 if verified, -ve on error */ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, const uint32_t sig_len, const uint8_t *hash, - struct checksum_algo *algo) + const uint32_t key_len, struct checksum_algo *algo) { - const uint8_t *padding; int pad_len; int ret; #if !defined(USE_HOSTCC) @@ -117,7 +117,7 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, return ret; } - pad_len = algo->key_len - algo->checksum_len; + pad_len = key_len - algo->checksum_len; /* Check pkcs1.5 padding bytes. */ ret = rsa_verify_padding(buf, pad_len, algo); @@ -183,7 +183,9 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, return -EFAULT; } - ret = rsa_verify_key(&prop, sig, sig_len, hash, info->algo->checksum); + ret = rsa_verify_key(&prop, sig, sig_len, hash, + info->algo->crypto->key_len, + info->algo->checksum); return ret; } @@ -194,7 +196,7 @@ int rsa_verify(struct image_sign_info *info, { const void *blob = info->fdt_blob; /* Reserve memory for maximum checksum-length */ - uint8_t hash[info->algo->checksum->key_len]; + uint8_t hash[info->algo->crypto->key_len]; int ndepth, noffset; int sig_node, node; char name[100]; @@ -205,9 +207,10 @@ int rsa_verify(struct image_sign_info *info, * rsa-signature-length */ if (info->algo->checksum->checksum_len > - info->algo->checksum->key_len) { + info->algo->crypto->key_len) { debug("%s: invlaid checksum-algorithm %s for %s\n", - __func__, info->algo->checksum->name, info->algo->name); + __func__, info->algo->checksum->name, + info->algo->crypto->name); return -EINVAL; } diff --git a/tools/image-host.c b/tools/image-host.c index 11046952fcf..dac85b4b747 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -213,7 +213,7 @@ static int fit_image_process_sig(const char *keydir, void *keydest, node_name = fit_get_name(fit, noffset, NULL); region.data = data; region.size = size; - ret = info.algo->sign(&info, ®ion, 1, &value, &value_len); + ret = info.algo->crypto->sign(&info, ®ion, 1, &value, &value_len); if (ret) { printf("Failed to sign '%s' signature node in '%s' image node: %d\n", node_name, image_name, ret); @@ -239,7 +239,7 @@ static int fit_image_process_sig(const char *keydir, void *keydest, info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); if (keydest) - ret = info.algo->add_verify_data(&info, keydest); + ret = info.algo->crypto->add_verify_data(&info, keydest); else return -1; @@ -588,7 +588,8 @@ static int fit_config_process_sig(const char *keydir, void *keydest, require_keys ? "conf" : NULL)) return -1; - ret = info.algo->sign(&info, region, region_count, &value, &value_len); + ret = info.algo->crypto->sign(&info, region, region_count, &value, + &value_len); free(region); if (ret) { printf("Failed to sign '%s' signature node in '%s' conf node\n", @@ -617,7 +618,7 @@ static int fit_config_process_sig(const char *keydir, void *keydest, /* Write the public key into the supplied FDT file */ if (keydest) { - ret = info.algo->add_verify_data(&info, keydest); + ret = info.algo->crypto->add_verify_data(&info, keydest); if (ret == -ENOSPC) return -ENOSPC; if (ret) { -- cgit v1.3.1 From 83dd98e012b55b494ac2bf1f9a5d66f684bfbbe8 Mon Sep 17 00:00:00 2001 From: Andrew Duda Date: Tue, 8 Nov 2016 18:53:41 +0000 Subject: image: Combine image_sig_algo with image_sign_info Remove the need to explicitly add SHA/RSA pairings. Invalid SHA/RSA pairings will still fail on verify operations when the hash length is longer than the key length. Follow the same naming scheme "checksum,crytpo" without explicitly defining the string. Indirectly adds support for "sha1,rsa4096" signing/verification. Signed-off-by: Andrew Duda Signed-off-by: aduda Reviewed-by: Simon Glass --- common/image-sig.c | 57 ++++++++++++++++++++++++++++------------------------ include/image.h | 24 ++++++++++++---------- lib/rsa/rsa-sign.c | 4 ++-- lib/rsa/rsa-verify.c | 14 ++++++------- tools/image-host.c | 16 ++++++++------- 5 files changed, 61 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/common/image-sig.c b/common/image-sig.c index 8b4314de09d..455f2b96294 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -72,32 +72,36 @@ struct crypto_algo crypto_algos[] = { }; -struct image_sig_algo image_sig_algos[] = { - { - "sha1,rsa2048", - &crypto_algos[0], - &checksum_algos[0], - }, - { - "sha256,rsa2048", - &crypto_algos[0], - &checksum_algos[1], - }, - { - "sha256,rsa4096", - &crypto_algos[1], - &checksum_algos[1], +struct checksum_algo *image_get_checksum_algo(const char *full_name) +{ + int i; + const char *name; + + for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) { + name = checksum_algos[i].name; + /* Make sure names match and next char is a comma */ + if (!strncmp(name, full_name, strlen(name)) && + full_name[strlen(name)] == ',') + return &checksum_algos[i]; } -}; + return NULL; +} -struct image_sig_algo *image_get_sig_algo(const char *name) +struct crypto_algo *image_get_crypto_algo(const char *full_name) { int i; + const char *name; + + /* Move name to after the comma */ + name = strchr(full_name, ','); + if (!name) + return NULL; + name += 1; - for (i = 0; i < ARRAY_SIZE(image_sig_algos); i++) { - if (!strcmp(image_sig_algos[i].name, name)) - return &image_sig_algos[i]; + for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) { + if (!strcmp(crypto_algos[i].name, name)) + return &crypto_algos[i]; } return NULL; @@ -161,12 +165,14 @@ static int fit_image_setup_verify(struct image_sign_info *info, info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); info->fit = (void *)fit; info->node_offset = noffset; - info->algo = image_get_sig_algo(algo_name); + info->name = algo_name; + info->checksum = image_get_checksum_algo(algo_name); + info->crypto = image_get_crypto_algo(algo_name); info->fdt_blob = gd_fdt_blob(); info->required_keynode = required_keynode; printf("%s:%s", algo_name, info->keyname); - if (!info->algo) { + if (!info->checksum || !info->crypto) { *err_msgp = "Unknown signature algorithm"; return -1; } @@ -196,8 +202,7 @@ int fit_image_check_sig(const void *fit, int noffset, const void *data, region.data = data; region.size = size; - if (info.algo->crypto->verify(&info, ®ion, 1, fit_value, - fit_value_len)) { + if (info.crypto->verify(&info, ®ion, 1, fit_value, fit_value_len)) { *err_msgp = "Verification failed"; return -1; } @@ -378,8 +383,8 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode, struct image_region region[count]; fit_region_make_list(fit, fdt_regions, count, region); - if (info.algo->crypto->verify(&info, region, count, fit_value, - fit_value_len)) { + if (info.crypto->verify(&info, region, count, fit_value, + fit_value_len)) { *err_msgp = "Verification failed"; return -1; } diff --git a/include/image.h b/include/image.h index c3c98667381..81315959fe2 100644 --- a/include/image.h +++ b/include/image.h @@ -1049,7 +1049,9 @@ struct image_sign_info { const char *keyname; /* Name of key to use */ void *fit; /* Pointer to FIT blob */ int node_offset; /* Offset of signature node */ - struct image_sig_algo *algo; /* Algorithm information */ + const char *name; /* Algorithm name */ + struct checksum_algo *checksum; /* Checksum algorithm information */ + struct crypto_algo *crypto; /* Crypto algorithm information */ const void *fdt_blob; /* FDT containing public keys */ int required_keynode; /* Node offset of key to use: -1=any */ const char *require_keys; /* Value for 'required' property */ @@ -1133,21 +1135,21 @@ struct crypto_algo { uint8_t *sig, uint sig_len); }; -struct image_sig_algo { - const char *name; - /* pointer to cryptosystem algorithm */ - struct crypto_algo *crypto; - /* pointer to checksum algorithm */ - struct checksum_algo *checksum; -}; +/** + * image_get_checksum_algo() - Look up a checksum algorithm + * + * @param full_name Name of algorithm in the form "checksum,crypto" + * @return pointer to algorithm information, or NULL if not found + */ +struct checksum_algo *image_get_checksum_algo(const char *full_name); /** - * image_get_sig_algo() - Look up a signature algortihm + * image_get_crypto_algo() - Look up a cryptosystem algorithm * - * @param name Name of algorithm + * @param full_name Name of algorithm in the form "checksum,crypto" * @return pointer to algorithm information, or NULL if not found */ -struct image_sig_algo *image_get_sig_algo(const char *name); +struct crypto_algo *image_get_crypto_algo(const char *full_name); /** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index c26f74128f2..9a092800130 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -244,7 +244,7 @@ int rsa_sign(struct image_sign_info *info, ret = rsa_get_priv_key(info->keydir, info->keyname, &rsa); if (ret) goto err_priv; - ret = rsa_sign_with_key(rsa, info->algo->checksum, region, + ret = rsa_sign_with_key(rsa, info->checksum, region, region_count, sigp, sig_len); if (ret) goto err_sign; @@ -508,7 +508,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) } if (!ret) { ret = fdt_setprop_string(keydest, node, FIT_ALGO_PROP, - info->algo->name); + info->name); } if (!ret && info->require_keys) { ret = fdt_setprop_string(keydest, node, "required", diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 61dc4c2e706..0d548f8b8f9 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -184,8 +184,7 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, } ret = rsa_verify_key(&prop, sig, sig_len, hash, - info->algo->crypto->key_len, - info->algo->checksum); + info->crypto->key_len, info->checksum); return ret; } @@ -196,7 +195,7 @@ int rsa_verify(struct image_sign_info *info, { const void *blob = info->fdt_blob; /* Reserve memory for maximum checksum-length */ - uint8_t hash[info->algo->crypto->key_len]; + uint8_t hash[info->crypto->key_len]; int ndepth, noffset; int sig_node, node; char name[100]; @@ -206,11 +205,10 @@ int rsa_verify(struct image_sign_info *info, * Verify that the checksum-length does not exceed the * rsa-signature-length */ - if (info->algo->checksum->checksum_len > - info->algo->crypto->key_len) { + if (info->checksum->checksum_len > + info->crypto->key_len) { debug("%s: invlaid checksum-algorithm %s for %s\n", - __func__, info->algo->checksum->name, - info->algo->crypto->name); + __func__, info->checksum->name, info->crypto->name); return -EINVAL; } @@ -221,7 +219,7 @@ int rsa_verify(struct image_sign_info *info, } /* Calculate checksum with checksum-algorithm */ - ret = info->algo->checksum->calculate(info->algo->checksum->name, + ret = info->checksum->calculate(info->checksum->name, region, region_count, hash); if (ret < 0) { debug("%s: Error in checksum calculation\n", __func__); diff --git a/tools/image-host.c b/tools/image-host.c index dac85b4b747..c1a01225e2b 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -166,9 +166,11 @@ static int fit_image_setup_sig(struct image_sign_info *info, info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); info->fit = fit; info->node_offset = noffset; - info->algo = image_get_sig_algo(algo_name); + info->name = algo_name; + info->checksum = image_get_checksum_algo(algo_name); + info->crypto = image_get_crypto_algo(algo_name); info->require_keys = require_keys; - if (!info->algo) { + if (!info->checksum || !info->crypto) { printf("Unsupported signature algorithm (%s) for '%s' signature node in '%s' image node\n", algo_name, node_name, image_name); return -1; @@ -213,7 +215,7 @@ static int fit_image_process_sig(const char *keydir, void *keydest, node_name = fit_get_name(fit, noffset, NULL); region.data = data; region.size = size; - ret = info.algo->crypto->sign(&info, ®ion, 1, &value, &value_len); + ret = info.crypto->sign(&info, ®ion, 1, &value, &value_len); if (ret) { printf("Failed to sign '%s' signature node in '%s' image node: %d\n", node_name, image_name, ret); @@ -239,7 +241,7 @@ static int fit_image_process_sig(const char *keydir, void *keydest, info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); if (keydest) - ret = info.algo->crypto->add_verify_data(&info, keydest); + ret = info.crypto->add_verify_data(&info, keydest); else return -1; @@ -588,8 +590,8 @@ static int fit_config_process_sig(const char *keydir, void *keydest, require_keys ? "conf" : NULL)) return -1; - ret = info.algo->crypto->sign(&info, region, region_count, &value, - &value_len); + ret = info.crypto->sign(&info, region, region_count, &value, + &value_len); free(region); if (ret) { printf("Failed to sign '%s' signature node in '%s' conf node\n", @@ -618,7 +620,7 @@ static int fit_config_process_sig(const char *keydir, void *keydest, /* Write the public key into the supplied FDT file */ if (keydest) { - ret = info.algo->crypto->add_verify_data(&info, keydest); + ret = info.crypto->add_verify_data(&info, keydest); if (ret == -ENOSPC) return -ENOSPC; if (ret) { -- cgit v1.3.1 From b15e7c172709c0bbf10d8a229986581660d2b75f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 12 Nov 2016 21:43:37 -0600 Subject: ARM: OMAP3_LOGIC: Fix SPL Memory Map for Falcon Mode The memory map defined in commit ("49c7303f0e52: OMAP3: Enable SPL on omap3_logic) was used by a copy-paste of another board without fully understanding how the map works in Falcon mode. This patch undoes the customization and uses the default SPL Memory Map for OMAP3. When building the uImage, set LOADADDR=0x82000000 and Falcon mode should properly load. Signed-off-by: Adam Ford Reviewed-by: Tom Rini --- include/configs/omap3_logic.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0827ebedfd1..301d4b20027 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -15,19 +15,6 @@ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. We use this rather than the inherited defines from - * ti_armv7_common.h for backwards compatibility. - */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #include /* -- cgit v1.3.1 From 12262340d5181cbaef1d60364bc9e7b2b632b6e6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 12 Nov 2016 22:02:37 -0600 Subject: ARM: OMAP3_LOGIC: Update MTD Partition Table The previous partition table did not support a separate device tree and the kernel size was limited to 4MB. This update shows the location of the device tree (labeled as spl-os) for those who want to use Falcon Mode or use U-Boot to store the Flattened Device Tree (FDT) to NAND without appending it to the kernel. This also grows the kernel to 6MB since 4MB was becomming tight Signed-off-by: Adam Ford Reviewed-by: Tom Rini --- include/configs/omap3_logic.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 301d4b20027..abce61ae36f 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -108,9 +108,12 @@ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ #define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\ - "1920k(u-boot),128k(u-boot-env),"\ - "4m(kernel),-(fs)" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:"\ + "512k(MLO),"\ + "1792k(u-boot),"\ + "128k(spl-os)," \ + "128k(u-boot-env),"\ + "6m(kernel),-(fs)" #endif /* Environment information */ -- cgit v1.3.1 From 95e74a3df75bf01eaf69f5c28f9aa2db6568e901 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 16 Nov 2016 18:49:16 +0530 Subject: arm: exynos7420: remove custome low level init function Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang Cc: Alison Wang Signed-off-by: Thomas Abraham Reviewed-by: Alison Wang Reviewed-by: York Sun --- arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/soc.c | 18 ++++++++++-------- include/configs/exynos7420-common.h | 1 + 3 files changed, 12 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index ce2a16f95b0..07118fc3df3 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -126,6 +126,7 @@ choice config TARGET_ESPRESSO7420 bool "ESPRESSO7420 board" select ARM64 + select ARMV8_MULTIENTRY select SUPPORT_SPL select OF_CONTROL select SPL_DISABLE_OF_CONTROL diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index f9c74686119..cf149ad1a8c 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -9,6 +9,16 @@ #include #include +#ifdef CONFIG_TARGET_ESPRESSO7420 +/* + * Exynos7420 uses CPU0 of Cluster-1 as boot CPU. Due to this, branch_if_master + * fails to identify as the boot CPU as the master CPU. As temporary workaround, + * setup the slave CPU boot address as "_main". + */ +extern void _main(void); +void *secondary_boot_addr = (void *)_main; +#endif /* CONFIG_TARGET_ESPRESSO7420 */ + void reset_cpu(ulong addr) { #ifdef CONFIG_CPU_V7 @@ -23,11 +33,3 @@ void enable_caches(void) dcache_enable(); } #endif - -#ifdef CONFIG_ARM64 -void lowlevel_init(void) -{ - armv8_switch_to_el2(); - armv8_switch_to_el1(); -} -#endif diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index f7c47094ae6..1cea74e9542 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -47,6 +47,7 @@ #define CONFIG_IRAM_BASE 0x02100000 #define CONFIG_IRAM_SIZE 0x58000 #define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) +#define CPU_RELEASE_ADDR secondary_boot_addr /* Number of CPUs available */ #define CONFIG_CORE_COUNT 0x8 -- cgit v1.3.1 From d804a5e1c369e59f23723cd21e1e422b7702a0ac Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 14 Nov 2016 21:40:25 +0100 Subject: serial: pxa: use kconfig for serial configuration Migrate the PXA serial driver to be configured via Kconfig. Signed-off-by: Marcel Ziswiler Reviewed-by: Marek Vasut --- configs/colibri_pxa270_defconfig | 1 + configs/h2200_defconfig | 1 + configs/zipitz2_defconfig | 1 + drivers/serial/Kconfig | 6 ++++++ include/configs/colibri_pxa270.h | 1 - include/configs/h2200.h | 2 -- include/configs/zipitz2.h | 1 - scripts/config_whitelist.txt | 1 - 8 files changed, 9 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 9a57041c36a..85740c21265 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig index c1b359e54d7..a47159a283d 100644 --- a/configs/h2200_defconfig +++ b/configs/h2200_defconfig @@ -24,3 +24,4 @@ CONFIG_SYS_PROMPT="> " # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set +CONFIG_PXA_SERIAL=y diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig index 8eb9be4357b..58465799547 100644 --- a/configs/zipitz2_defconfig +++ b/configs/zipitz2_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 56c024f97a1..620dd82d6b9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -407,4 +407,10 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config PXA_SERIAL + bool "PXA serial port support" + help + If you have a machine based on a Marvell XScale PXA2xx CPU you + can enable its onboard serial ports by enabling this option. + endmenu diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index e44a84729bc..b16abdc9ec9 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -43,7 +43,6 @@ /* * Serial Console Configuration */ -#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 #define CONFIG_CONS_INDEX 3 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/h2200.h b/include/configs/h2200.h index 8e77982580f..18b5488392d 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -107,8 +107,6 @@ /* * Serial port */ - -#define CONFIG_PXA_SERIAL #define CONFIG_FFUART #define CONFIG_CONS_INDEX 3 diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index ed2c9acdb1d..97dfc0e6ec1 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -49,7 +49,6 @@ * Serial Console Configuration * STUART - the lower serial port on Colibri board */ -#define CONFIG_PXA_SERIAL #define CONFIG_STUART 1 #define CONFIG_CONS_INDEX 2 #define CONFIG_BAUDRATE 115200 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index fc2a08a8566..d6b2a457b41 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3740,7 +3740,6 @@ CONFIG_PWM_IMX CONFIG_PXA_LCD CONFIG_PXA_MMC_GENERIC CONFIG_PXA_PWR_I2C -CONFIG_PXA_SERIAL CONFIG_PXA_STD_I2C CONFIG_PXA_VGA CONFIG_PXA_VIDEO -- cgit v1.3.1 From cbfa67a16b345cfb94840a41ee2fa0f728be296a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 14 Nov 2016 21:40:26 +0100 Subject: serial: pxa: integrate optional driver model handling Optional driver model handling integration. Signed-off-by: Marcel Ziswiler Reviewed-by: Marek Vasut --- drivers/serial/serial_pxa.c | 183 +++++++++++++++++++++------------- include/dm/platform_data/serial_pxa.h | 56 +++++++++++ 2 files changed, 169 insertions(+), 70 deletions(-) create mode 100644 include/dm/platform_data/serial_pxa.h (limited to 'include') diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index 1eb19ececdf..ea5971ba3ca 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -14,6 +14,9 @@ * * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) * + * Modified to add driver model (DM) support + * (C) Copyright 2016 Marcel Ziswiler + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -21,73 +24,17 @@ #include #include #include +#include +#include #include #include #include DECLARE_GLOBAL_DATA_PTR; -/* - * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can - * easily handle enabling of clock. - */ -#ifdef CONFIG_CPU_MONAHANS -#define UART_CLK_BASE CKENA_21_BTUART -#define UART_CLK_REG CKENA -#define BTUART_INDEX 0 -#define FFUART_INDEX 1 -#define STUART_INDEX 2 -#elif CONFIG_CPU_PXA25X -#define UART_CLK_BASE (1 << 4) /* HWUART */ -#define UART_CLK_REG CKEN -#define HWUART_INDEX 0 -#define STUART_INDEX 1 -#define FFUART_INDEX 2 -#define BTUART_INDEX 3 -#else /* PXA27x */ -#define UART_CLK_BASE CKEN5_STUART -#define UART_CLK_REG CKEN -#define STUART_INDEX 0 -#define FFUART_INDEX 1 -#define BTUART_INDEX 2 -#endif - -/* - * Only PXA250 has HWUART, to avoid poluting the code with more macros, - * artificially introduce this. - */ -#ifndef CONFIG_CPU_PXA25X -#define HWUART_INDEX 0xff -#endif - -static uint32_t pxa_uart_get_baud_divider(void) -{ - if (gd->baudrate == 1200) - return 768; - else if (gd->baudrate == 9600) - return 96; - else if (gd->baudrate == 19200) - return 48; - else if (gd->baudrate == 38400) - return 24; - else if (gd->baudrate == 57600) - return 16; - else if (gd->baudrate == 115200) - return 8; - else /* Unsupported baudrate */ - return 0; -} - -static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index) +static uint32_t pxa_uart_get_baud_divider(int baudrate) { - switch (uart_index) { - case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE; - case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE; - case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE; - case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE; - default: - return NULL; - } + return 921600 / baudrate; } static void pxa_uart_toggle_clock(uint32_t uart_index, int enable) @@ -110,20 +57,14 @@ static void pxa_uart_toggle_clock(uint32_t uart_index, int enable) /* * Enable clock and set baud rate, parity etc. */ -void pxa_setbrg_dev(uint32_t uart_index) +void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate) { - uint32_t divider = 0; - struct pxa_uart_regs *uart_regs; - - divider = pxa_uart_get_baud_divider(); + uint32_t divider = pxa_uart_get_baud_divider(baudrate); if (!divider) hang(); - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - hang(); - pxa_uart_toggle_clock(uart_index, 1); + pxa_uart_toggle_clock(port, 1); /* Disable interrupts and FIFOs */ writel(0, &uart_regs->ier); @@ -139,13 +80,38 @@ void pxa_setbrg_dev(uint32_t uart_index) writel(IER_UUE, &uart_regs->ier); } +#ifndef CONFIG_DM_SERIAL +static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index) +{ + switch (uart_index) { + case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE; + case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE; + case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE; + case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE; + default: + return NULL; + } +} + +/* + * Enable clock and set baud rate, parity etc. + */ +void pxa_setbrg_dev(uint32_t uart_index) +{ + struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index); + if (!uart_regs) + panic("Failed getting UART registers\n"); + + pxa_setbrg_common(uart_regs, uart_index, gd->baudrate); +} + /* * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ int pxa_init_dev(unsigned int uart_index) { - pxa_setbrg_dev (uart_index); + pxa_setbrg_dev(uart_index); return 0; } @@ -297,3 +263,80 @@ void pxa_serial_initialize(void) serial_register(&serial_stuart_device); #endif } +#endif /* CONFIG_DM_SERIAL */ + +#ifdef CONFIG_DM_SERIAL +static int pxa_serial_probe(struct udevice *dev) +{ + struct pxa_serial_platdata *plat = dev->platdata; + + pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port, + plat->baudrate); + return 0; +} + +static int pxa_serial_putc(struct udevice *dev, const char ch) +{ + struct pxa_serial_platdata *plat = dev->platdata; + struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; + + /* Wait for last character to go. */ + if (!(readl(&uart_regs->lsr) & LSR_TEMT)) + return -EAGAIN; + + writel(ch, &uart_regs->thr); + + return 0; +} + +static int pxa_serial_getc(struct udevice *dev) +{ + struct pxa_serial_platdata *plat = dev->platdata; + struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; + + /* Wait for a character to arrive. */ + if (!(readl(&uart_regs->lsr) & LSR_DR)) + return -EAGAIN; + + return readl(&uart_regs->rbr) & 0xff; +} + +int pxa_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct pxa_serial_platdata *plat = dev->platdata; + struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; + int port = plat->port; + + pxa_setbrg_common(uart_regs, port, baudrate); + + return 0; +} + +static int pxa_serial_pending(struct udevice *dev, bool input) +{ + struct pxa_serial_platdata *plat = dev->platdata; + struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; + + if (input) + return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0; + else + return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1; + + return 0; +} + +static const struct dm_serial_ops pxa_serial_ops = { + .putc = pxa_serial_putc, + .pending = pxa_serial_pending, + .getc = pxa_serial_getc, + .setbrg = pxa_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_pxa) = { + .name = "serial_pxa", + .id = UCLASS_SERIAL, + .probe = pxa_serial_probe, + .ops = &pxa_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif /* CONFIG_DM_SERIAL */ diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h new file mode 100644 index 00000000000..b19a4a6521b --- /dev/null +++ b/include/dm/platform_data/serial_pxa.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016 Marcel Ziswiler + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SERIAL_PXA_H +#define __SERIAL_PXA_H + +/* + * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can + * easily handle enabling of clock. + */ +#ifdef CONFIG_CPU_MONAHANS +#define UART_CLK_BASE CKENA_21_BTUART +#define UART_CLK_REG CKENA +#define BTUART_INDEX 0 +#define FFUART_INDEX 1 +#define STUART_INDEX 2 +#elif CONFIG_CPU_PXA25X +#define UART_CLK_BASE (1 << 4) /* HWUART */ +#define UART_CLK_REG CKEN +#define HWUART_INDEX 0 +#define STUART_INDEX 1 +#define FFUART_INDEX 2 +#define BTUART_INDEX 3 +#else /* PXA27x */ +#define UART_CLK_BASE CKEN5_STUART +#define UART_CLK_REG CKEN +#define STUART_INDEX 0 +#define FFUART_INDEX 1 +#define BTUART_INDEX 2 +#endif + +/* + * Only PXA250 has HWUART, to avoid poluting the code with more macros, + * artificially introduce this. + */ +#ifndef CONFIG_CPU_PXA25X +#define HWUART_INDEX 0xff +#endif + +/* + * struct pxa_serial_platdata - information about a PXA port + * + * @base: Uart port base register address + * @port: Uart port index, for cpu with pinmux for uart / gpio + * baudrtatre: Uart port baudrate + */ +struct pxa_serial_platdata { + struct pxa_uart_regs *base; + int port; + int baudrate; +}; + +#endif /* __SERIAL_PXA_H */ -- cgit v1.3.1 From fc127d184aea293ec415dd66e3282dba0b66c5f3 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 14 Nov 2016 21:40:27 +0100 Subject: colibri_pxa270: drop edit, elf, fpga, hush, regex et al. for space reason With em humble DM and Kconfig migraters U-Boot binary size keeps increasing. Drop a bunch of less needed stuff to save another precious 20+ KB. Signed-off-by: Marcel Ziswiler --- configs/colibri_pxa270_defconfig | 6 +++++- include/configs/colibri_pxa270.h | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 85740c21265..0b5c20dfed9 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -1,13 +1,16 @@ CONFIG_ARM=y CONFIG_TARGET_COLIBRI_PXA270=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="$ " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -16,5 +19,6 @@ CONFIG_CMD_FAT=y CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y +# CONFIG_REGEX is not set CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index b16abdc9ec9..39fd94b3de3 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -93,8 +93,8 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 +#undef CONFIG_CMDLINE_EDITING /* Saves 2.5 KB */ +#undef CONFIG_AUTO_COMPLETE /* Saves 2.5 KB */ /* * Clock Configuration -- cgit v1.3.1 From 136179bec19f4bc84227cba138214ea392a723ea Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 14 Nov 2016 21:40:28 +0100 Subject: colibri_pxa270: transition to driver model for serial Add serial platform data to board file. Enable driver model for PXA serial driver. Signed-off-by: Marcel Ziswiler --- board/toradex/colibri_pxa270/colibri_pxa270.c | 18 ++++++++++++++++-- configs/colibri_pxa270_defconfig | 2 ++ include/configs/colibri_pxa270.h | 2 -- 3 files changed, 18 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 3def0a6fd07..2e3e03a1527 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -8,10 +8,13 @@ #include #include -#include #include -#include +#include +#include #include +#include +#include +#include #include #include @@ -105,3 +108,14 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +static const struct pxa_serial_platdata serial_platdata = { + .base = (struct pxa_uart_regs *)FFUART_BASE, + .port = FFUART_INDEX, + .baudrate = CONFIG_BAUDRATE, +}; + +U_BOOT_DEVICE(pxa_serials) = { + .name = "serial_pxa", + .platdata = &serial_platdata, +}; diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 0b5c20dfed9..e0a36f13ddb 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -16,6 +16,8 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 39fd94b3de3..31eb5e9b9a4 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -43,8 +43,6 @@ /* * Serial Console Configuration */ -#define CONFIG_FFUART 1 -#define CONFIG_CONS_INDEX 3 #define CONFIG_BAUDRATE 115200 /* -- cgit v1.3.1 From f9dd8553f31817353f2a04385a1a0909df9670e4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 23 Nov 2016 09:08:47 -0800 Subject: armv7: ls1021aiot: Fixing SPL compiling issues To align with SPL change 38fed8ab and 693d4c9f, add Kconfig option CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to defconfig, and remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS. Signed-off-by: York Sun CC: Feng Li --- configs/ls1021aiot_sdcard_defconfig | 2 ++ include/configs/ls1021aiot.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 4b082ab0f96..a5a391dd816 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AIOT=y CONFIG_SPL=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" CONFIG_DM_SPI=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 182a0036031..7af4bc41dcd 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -96,7 +96,6 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 -- cgit v1.3.1 From 2f5d532f3b8a7697dc1b5700000b1e350323d50c Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 26 Oct 2016 13:42:30 +0530 Subject: power: regulator: Introduce regulator_set_value_force function In case we want to force a particular value on a regulator irrespective of the min/max constraints for testing purposes one can call regulator_set_value_force function. Signed-off-by: Keerthy Reviewed-by: Simon Glass --- cmd/regulator.c | 5 ++++- drivers/power/regulator/regulator-uclass.c | 14 ++++++++++++++ include/power/regulator.h | 10 ++++++++++ 3 files changed, 28 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/cmd/regulator.c b/cmd/regulator.c index bfea6e04b67..2ef5bc9a828 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -292,7 +292,10 @@ static int do_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_FAILURE; } - ret = regulator_set_value(dev, value); + if (!force) + ret = regulator_set_value(dev, value); + else + ret = regulator_set_value_force(dev, value); if (ret) { printf("Regulator: %s - can't set the Voltage!\n", uc_pdata->name); diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4434e36312a..d64400981fa 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -48,6 +48,20 @@ int regulator_set_value(struct udevice *dev, int uV) return ops->set_value(dev, uV); } +/* + * To be called with at most caution as there is no check + * before setting the actual voltage value. + */ +int regulator_set_value_force(struct udevice *dev, int uV) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->set_value) + return -ENOSYS; + + return ops->set_value(dev, uV); +} + int regulator_get_current(struct udevice *dev) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); diff --git a/include/power/regulator.h b/include/power/regulator.h index f47ab6740bd..1a8e5753d78 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -260,6 +260,16 @@ int regulator_get_value(struct udevice *dev); */ int regulator_set_value(struct udevice *dev, int uV); +/** + * regulator_set_value_force: set the microvoltage value of a given regulator + * without any min-,max condition check + * + * @dev - pointer to the regulator device + * @uV - the output value to set [micro Volts] + * @return - 0 on success or -errno val if fails + */ +int regulator_set_value_force(struct udevice *dev, int uV); + /** * regulator_get_current: get microampere value of a given regulator * -- cgit v1.3.1 From 1e352124b94f977fb7bbb516ea09ef345a70ee09 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 8 Nov 2016 18:13:39 +0800 Subject: config: rk3036: enable configs for USB HOST rk3036 using dwc2 usb controller, need enable relate configs for it. Signed-off-by: Kever Yang Acked-by: Simon Glass --- configs/kylin-rk3036_defconfig | 3 +++ include/configs/rk3036_common.h | 7 +++++++ 2 files changed, 10 insertions(+) (limited to 'include') diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 424cdab5693..5a8b85aee15 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -36,3 +36,6 @@ CONFIG_RAM=y CONFIG_SYSRESET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 4eef3f8cc6e..92be29e7bba 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -79,6 +79,13 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x2207 #define CONFIG_G_DNL_PRODUCT_NUM 0x310a +/* usb host */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ -- cgit v1.3.1 From 1b68283b64a7a1847410eff20886bd7bbfd8f9a6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Nov 2016 14:22:07 -0700 Subject: video: Track whether a display is in use Mark a display as in use when display_enable() is called. This can avoid a display being used by multiple video-output devices. Signed-off-by: Simon Glass --- drivers/video/display-uclass.c | 18 +++++++++++++++++- include/display.h | 10 ++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index e4763de73df..e752eb07c4d 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -23,10 +23,19 @@ int display_enable(struct udevice *dev, int panel_bpp, const struct display_timing *timing) { struct dm_display_ops *ops = display_get_ops(dev); + struct display_plat *disp_uc_plat; + int ret; if (!ops || !ops->enable) return -ENOSYS; - return ops->enable(dev, panel_bpp, timing); + ret = ops->enable(dev, panel_bpp, timing); + if (ret) + return ret; + + disp_uc_plat = dev_get_uclass_platdata(dev); + disp_uc_plat->in_use = true; + + return 0; } int display_read_timing(struct udevice *dev, struct display_timing *timing) @@ -48,6 +57,13 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing) return edid_get_timing(buf, ret, timing, &panel_bits_per_colour); } +bool display_in_use(struct udevice *dev) +{ + struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); + + return disp_uc_plat->in_use; +} + UCLASS_DRIVER(display) = { .id = UCLASS_DISPLAY, .name = "display", diff --git a/include/display.h b/include/display.h index b1c476628b4..d0a08d4aaa8 100644 --- a/include/display.h +++ b/include/display.h @@ -16,10 +16,12 @@ struct display_timing; * @source_id: ID for the source of the display data, typically a video * controller * @src_dev: Source device providing the video + * @in_use: Display is being used */ struct display_plat { int source_id; struct udevice *src_dev; + bool in_use; }; /** @@ -41,6 +43,14 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing); int display_enable(struct udevice *dev, int panel_bpp, const struct display_timing *timing); +/** + * display_in_use() - Check if a display is in use by any device + * + * @return true if the device is in use (display_enable() has been called + * successfully), else false + */ +bool display_in_use(struct udevice *dev); + struct dm_display_ops { /** * read_timing() - Read information directly -- cgit v1.3.1 From 5e9b15034b9e38a6908610229788cf0746d138fc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 13 Nov 2016 14:22:10 -0700 Subject: rockchip: Rename jerry files to veyron At present we have a single rk3288-based Chromebook: chromebook_jerry. But all such Chromebooks can use the same binary with only device-tree differences. The family name is 'veyron', so rename the files accordingly. Also update the device-tree filename since this currently differs from Linux. Signed-off-by: Simon Glass --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/rk3288-jerry.dts | 203 ------------------------------ arch/arm/dts/rk3288-veyron-jerry.dts | 203 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 2 +- board/google/chromebook_jerry/Kconfig | 15 --- board/google/chromebook_jerry/MAINTAINERS | 6 - board/google/chromebook_jerry/Makefile | 7 -- board/google/chromebook_jerry/jerry.c | 7 -- board/google/veyron/Kconfig | 15 +++ board/google/veyron/MAINTAINERS | 6 + board/google/veyron/Makefile | 7 ++ board/google/veyron/veyron.c | 7 ++ configs/chromebook_jerry_defconfig | 2 +- include/configs/chromebook_jerry.h | 27 ---- include/configs/veyron.h | 27 ++++ 15 files changed, 268 insertions(+), 268 deletions(-) delete mode 100644 arch/arm/dts/rk3288-jerry.dts create mode 100644 arch/arm/dts/rk3288-veyron-jerry.dts delete mode 100644 board/google/chromebook_jerry/Kconfig delete mode 100644 board/google/chromebook_jerry/MAINTAINERS delete mode 100644 board/google/chromebook_jerry/Makefile delete mode 100644 board/google/chromebook_jerry/jerry.c create mode 100644 board/google/veyron/Kconfig create mode 100644 board/google/veyron/MAINTAINERS create mode 100644 board/google/veyron/Makefile create mode 100644 board/google/veyron/veyron.c delete mode 100644 include/configs/chromebook_jerry.h create mode 100644 include/configs/veyron.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cba7919c580..a345018510a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -30,7 +30,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-sdk.dtb \ rk3288-firefly.dtb \ - rk3288-jerry.dtb \ + rk3288-veyron-jerry.dtb \ rk3288-rock2-square.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-jerry.dts deleted file mode 100644 index da37ea8e7ad..00000000000 --- a/arch/arm/dts/rk3288-jerry.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Google Veyron Jerry Rev 3+ board device tree source - * - * Copyright 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jerry"; - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - panel_regulator: panel-regualtor { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; -}; - -&gpio_keys { - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&panel { - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "mic_vcc"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&sdmmc { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; - disable-wp; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&edp { - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - edp { - edp_hpd: edp_hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; - }; - }; - - emmc { - /* Make sure eMMC is not in reset */ - emmc_deassert_reset: emmc-deassert-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&i2c4 { - status = "okay"; - - /* - * Trackpad pin control is shared between Elan and Synaptics devices - * so we have to pull it up to the bus level. - */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer &trackpad_int>; - - trackpad@15 { - compatible = "elan,i2c_touchpad"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - /* - * Remove the inherited pinctrl settings to avoid clashing - * with bus-wide ones. - */ - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - reg = <0x15>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; - - trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts new file mode 100644 index 00000000000..da37ea8e7ad --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -0,0 +1,203 @@ +/* + * Google Veyron Jerry Rev 3+ board device tree source + * + * Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Jerry"; + compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", + "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", + "google,veyron-jerry-rev3", "google,veyron-jerry", + "google,veyron", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + panel_regulator: panel-regualtor { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&gpio_keys { + power { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; +}; + +&backlight { + power-supply = <&backlight_regulator>; +}; + +&panel { + power-supply= <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; + + regulators { + mic_vcc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "mic_vcc"; + regulator-suspend-mem-disabled; + }; + }; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; + disable-wp; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&edp { + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp_hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + + emmc { + /* Make sure eMMC is not in reset */ + emmc_deassert_reset: emmc-deassert-reset { + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /* + * Trackpad pin control is shared between Elan and Synaptics devices + * so we have to pull it up to the bus level. + */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer &trackpad_int>; + + trackpad@15 { + compatible = "elan,i2c_touchpad"; + interrupt-parent = <&gpio7>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + /* + * Remove the inherited pinctrl settings to avoid clashing + * with bus-wide ones. + */ + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + reg = <0x15>; + vcc-supply = <&vcc33_io>; + wakeup-source; + }; + + trackpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&gpio7>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + vcc-supply = <&vcc33_io>; + wakeup-source; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index c53d2e20337..30c557b8a3a 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -88,7 +88,7 @@ source "board/chipspark/popmetal_rk3288/Kconfig" source "board/firefly/firefly-rk3288/Kconfig" -source "board/google/chromebook_jerry/Kconfig" +source "board/google/veyron/Kconfig" source "board/radxa/rock2/Kconfig" diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/chromebook_jerry/Kconfig deleted file mode 100644 index 36405138b57..00000000000 --- a/board/google/chromebook_jerry/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_CHROMEBOOK_JERRY - -config SYS_BOARD - default "chromebook_jerry" - -config SYS_VENDOR - default "google" - -config SYS_CONFIG_NAME - default "chromebook_jerry" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - -endif diff --git a/board/google/chromebook_jerry/MAINTAINERS b/board/google/chromebook_jerry/MAINTAINERS deleted file mode 100644 index b01b6cd4194..00000000000 --- a/board/google/chromebook_jerry/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CHROMEBOOK JERRY BOARD -M: Simon Glass -S: Maintained -F: board/google/chromebook_jerry/ -F: include/configs/chromebook_jerry.h -F: configs/chromebook_jerry_defconfig diff --git a/board/google/chromebook_jerry/Makefile b/board/google/chromebook_jerry/Makefile deleted file mode 100644 index d29a063dcdd..00000000000 --- a/board/google/chromebook_jerry/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2015 Google, Inc -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += jerry.o diff --git a/board/google/chromebook_jerry/jerry.c b/board/google/chromebook_jerry/jerry.c deleted file mode 100644 index 5119e954550..00000000000 --- a/board/google/chromebook_jerry/jerry.c +++ /dev/null @@ -1,7 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig new file mode 100644 index 00000000000..b1f51ce33db --- /dev/null +++ b/board/google/veyron/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_JERRY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS new file mode 100644 index 00000000000..d641eed66ad --- /dev/null +++ b/board/google/veyron/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK JERRY BOARD +M: Simon Glass +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebook_jerry_defconfig diff --git a/board/google/veyron/Makefile b/board/google/veyron/Makefile new file mode 100644 index 00000000000..98683579dbe --- /dev/null +++ b/board/google/veyron/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += veyron.o diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c new file mode 100644 index 00000000000..5119e954550 --- /dev/null +++ b/board/google/veyron/veyron.c @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 6f4ae183475..46df1a66251 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -7,7 +7,7 @@ CONFIG_TARGET_CHROMEBOOK_JERRY=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry" +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h deleted file mode 100644 index b15cc26bebc..00000000000 --- a/include/configs/chromebook_jerry.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#include - -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPI_FLASH_GIGADEVICE - -#define CONFIG_CMD_SF_TEST - -#define CONFIG_KEYBOARD - -#define CONFIG_SYS_WHITE_ON_BLACK - -#endif diff --git a/include/configs/veyron.h b/include/configs/veyron.h new file mode 100644 index 00000000000..b15cc26bebc --- /dev/null +++ b/include/configs/veyron.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPI_FLASH_GIGADEVICE + +#define CONFIG_CMD_SF_TEST + +#define CONFIG_KEYBOARD + +#define CONFIG_SYS_WHITE_ON_BLACK + +#endif -- cgit v1.3.1 From 6b388f0bed0e3d021128b4fc3c41da4572984e3b Mon Sep 17 00:00:00 2001 From: Jacob Chen Date: Tue, 15 Nov 2016 16:55:27 +0800 Subject: rockchip: configs: correct partitions 'boot' size It should be 112M, to make rootfs start at 0x40000 Signed-off-by: Jacob Chen Acked-by: Simon Glass --- include/configs/rockchip-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 7ca1696a163..9ec71c4baaa 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -27,7 +27,7 @@ "name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \ "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \ "name=atf,size=4M,uuid=${uuid_gpt_atf};" \ - "name=boot,size=128M,bootable,uuid=${uuid_gpt_boot};" \ + "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \ #endif -- cgit v1.3.1 From ae042beb746fafbd499dbe6093c357a4d94a4aba Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Sat, 5 Nov 2016 20:51:11 +0100 Subject: sunxi: mmc: Set CONFIG_SYS_MMC_MAX_DEVICE Set CONFIG_SYS_MMC_MAX_DEVICE to 4 for sunxi SoC. This define is needed in the API code. Signed-off-by: Emmanuel Vadot Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 2e02f8cd185..b0bfc0dfd7d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -145,6 +145,7 @@ #define CONFIG_MMC_SUNXI_SLOT 0 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ +#define CONFIG_SYS_MMC_MAX_DEVICE 4 #endif /* 64MB of malloc() pool */ -- cgit v1.3.1 From b891d01038abcc8b25f12e1b91ff889b06eb07a2 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 16 Nov 2016 17:49:23 +0100 Subject: apalis/colibri_imx7/pxa270/t20/t30/vf: integrate config block handling With our common code in place actually make use of it across all our modules. Signed-off-by: Marcel Ziswiler Acked-by: Max Krummenacher --- board/toradex/apalis_t30/Kconfig | 18 ++++++++++++++++++ board/toradex/apalis_t30/apalis_t30.c | 12 +++++++++++- board/toradex/colibri_imx7/Kconfig | 16 ++++++++++++++++ board/toradex/colibri_pxa270/Kconfig | 11 +++++++++++ board/toradex/colibri_pxa270/colibri_pxa270.c | 8 ++++++++ board/toradex/colibri_t20/Kconfig | 11 +++++++++++ board/toradex/colibri_t20/colibri_t20.c | 13 +++++++++++++ board/toradex/colibri_t30/Kconfig | 18 ++++++++++++++++++ board/toradex/colibri_t30/colibri_t30.c | 9 ++++++++- board/toradex/colibri_vf/Kconfig | 14 ++++++++++++++ configs/colibri_vf_defconfig | 1 + include/configs/apalis_t30.h | 4 ++-- include/configs/colibri_imx7.h | 6 +++++- include/configs/colibri_pxa270.h | 6 +++++- include/configs/colibri_t20.h | 2 +- include/configs/colibri_t30.h | 4 ++-- include/configs/colibri_vf.h | 6 ++++-- 17 files changed, 148 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig index f1dcda59275..16224daa120 100644 --- a/board/toradex/apalis_t30/Kconfig +++ b/board/toradex/apalis_t30/Kconfig @@ -9,4 +9,22 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "apalis_t30" +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + endif diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 3f56971a13b..3d834910706 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * Marcel Ziswiler * * SPDX-License-Identifier: GPL-2.0+ @@ -17,6 +17,8 @@ #include "pinmux-config-apalis_t30.h" +DECLARE_GLOBAL_DATA_PTR; + #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 @@ -29,6 +31,14 @@ int arch_misc_init(void) return 0; } +int checkboard(void) +{ + printf("Model: Toradex Apalis T30 %dGB\n", + (gd->ram_size == 0x40000000) ? 1 : 2); + + return 0; +} + /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig index 7bba26b90dd..414a600eefb 100644 --- a/board/toradex/colibri_imx7/Kconfig +++ b/board/toradex/colibri_imx7/Kconfig @@ -16,5 +16,21 @@ config COLIBRI_IMX7_EXT_PHYCLK clock source. default y +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NAND + default y + +config TDX_CFG_BLOCK_OFFSET + default "2048" + +config TDX_CFG_BLOCK_OFFSET2 + default "133120" + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig index 949407a0423..f646baa3f05 100644 --- a/board/toradex/colibri_pxa270/Kconfig +++ b/board/toradex/colibri_pxa270/Kconfig @@ -9,4 +9,15 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "colibri_pxa270" +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NOR + default y + +config TDX_CFG_BLOCK_OFFSET + default "262144" + +source "board/toradex/common/Kconfig" + endif diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 2e3e03a1527..932b90014ba 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -2,6 +2,7 @@ * Toradex Colibri PXA270 Support * * Copyright (C) 2010 Marek Vasut + * Copyright (C) 2016 Marcel Ziswiler * * SPDX-License-Identifier: GPL-2.0+ */ @@ -35,6 +36,13 @@ int board_init(void) return 0; } +int checkboard(void) +{ + puts("Model: Toradex Colibri PXA270\n"); + + return 0; +} + int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig index 7f373b2d26b..a43acddb801 100644 --- a/board/toradex/colibri_t20/Kconfig +++ b/board/toradex/colibri_t20/Kconfig @@ -9,4 +9,15 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "colibri_t20" +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NAND + default y + +config TDX_CFG_BLOCK_OFFSET + default "3145728" + +source "board/toradex/common/Kconfig" + endif diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 68fbf495798..01b55be763d 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -14,6 +14,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; #define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 @@ -61,6 +64,16 @@ int arch_misc_init(void) return 0; } +int checkboard(void) +{ + printf("Model: Toradex Colibri T20 %dMB V%s\n", + (gd->ram_size == 0x10000000) ? 256 : 512, + (nand_info[0]->erasesize >> 10 == 512) ? + ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A"); + + return 0; +} + #ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig index 3e436a2d3fd..68ef82b099d 100644 --- a/board/toradex/colibri_t30/Kconfig +++ b/board/toradex/colibri_t30/Kconfig @@ -9,4 +9,22 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "colibri_t30" +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + endif diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index e32362a93a6..707d07e2dfc 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 + * (C) Copyright 2014-2016 * Stefan Agner * * SPDX-License-Identifier: GPL-2.0+ @@ -24,6 +24,13 @@ int arch_misc_init(void) return 0; } +int checkboard(void) +{ + puts("Model: Toradex Colibri T30 1GB\n"); + + return 0; +} + /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig index 2c3cb307fd2..bf9bb0146e5 100644 --- a/board/toradex/colibri_vf/Kconfig +++ b/board/toradex/colibri_vf/Kconfig @@ -15,4 +15,18 @@ config SYS_SOC config SYS_CONFIG_NAME default "colibri_vf" +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NAND + default y + +config TDX_CFG_BLOCK_OFFSET + default "2048" + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +source "board/toradex/common/Kconfig" + endif diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 1020e44c112..54d35815d5e 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -4,6 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Colibri VFxx # " CONFIG_CMD_BOOTZ=y diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index d38302d6c42..069ed20427b 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015 Marcel Ziswiler + * Copyright (c) 2014-2016 Marcel Ziswiler * * Configuration settings for the Toradex Apalis T30 modules. * @@ -16,7 +16,7 @@ #define CONFIG_ARCH_MISC_INIT /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30" +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 309aef8405c..5ce0a34a5d1 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -21,10 +21,14 @@ /*#define CONFIG_DBG_MONITOR*/ #define PHYS_SDRAM_SIZE SZ_512M +#define CONFIG_ARCH_MISC_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT -#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 31eb5e9b9a4..51f78779080 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -2,7 +2,7 @@ * Toradex Colibri PXA270 configuration file * * Copyright (C) 2010 Marek Vasut - * Copyright (C) 2015 Marcel Ziswiler + * Copyright (C) 2015-2016 Marcel Ziswiler * * SPDX-License-Identifier: GPL-2.0+ */ @@ -21,10 +21,14 @@ /* We will never enable dcache because we have to setup MMU first */ #define CONFIG_SYS_DCACHE_OFF +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ + /* * Environment settings */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 46349896d77..6a528690268 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -14,7 +14,7 @@ #define CONFIG_ARCH_MISC_INIT /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20" +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index e2a2549fb65..1ab5c41dad2 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015 Stefan Agner + * Copyright (c) 2013-2016 Stefan Agner * * Configuration settings for the Toradex Colibri T30 modules. * @@ -16,7 +16,7 @@ #define CONFIG_ARCH_MISC_INIT /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30" +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index be773a311ae..0e622fb5e32 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -1,7 +1,7 @@ /* - * Copyright 2015 Toradex, Inc. + * Copyright 2015-2016 Toradex, Inc. * - * Configuration settings for the Toradex VF50/VF61 module. + * Configuration settings for the Toradex VF50/VF61 modules. * * Based on vf610twr.h: * Copyright 2013 Freescale Semiconductor, Inc. @@ -21,6 +21,7 @@ #define CONFIG_SYS_FSL_CLK #define CONFIG_ARCH_MISC_INIT +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -36,6 +37,7 @@ /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_BAUDRATE 115200 -- cgit v1.3.1 From 74b19ad1c180fe32a01bccc35b0be1425132d927 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 16 Nov 2016 17:49:24 +0100 Subject: apalis/colibri_t30: move environment location Now with the config block handling in place move the U-Boot environment location before the config block at the end of 1st "boot sector" as deployed during production using our downstream BSP. Signed-off-by: Marcel Ziswiler Acked-by: Max Krummenacher --- include/configs/apalis_t30.h | 7 ++++--- include/configs/colibri_t30.h | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 069ed20427b..f2a24c11de8 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -32,11 +32,12 @@ #define CONFIG_GENERIC_MMC #define CONFIG_TEGRA_MMC -/* Environment in eMMC, at the end of 2nd "boot sector" */ +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_SYS_MMC_ENV_PART 1 /* USB host support */ #define CONFIG_USB_EHCI diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 1ab5c41dad2..e8b3f99f532 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -32,11 +32,12 @@ #define CONFIG_GENERIC_MMC #define CONFIG_TEGRA_MMC -/* Environment in eMMC, at the end of 2nd "boot sector" */ +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_SYS_MMC_ENV_PART 1 /* USB host support */ #define CONFIG_USB_EHCI -- cgit v1.3.1 From 877ea607a8e07a9ed308e44a58e8e2b9028f01f2 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 16 Nov 2016 17:49:25 +0100 Subject: colibri_vf: usb gadget: toradex pid is now set generically remove now unused CONFIG_TRDX_PID_XXX Signed-off-by: Marcel Ziswiler Acked-by: Stefan Agner Acked-by: Max Krummenacher --- board/toradex/colibri_vf/colibri_vf.c | 16 ---------------- include/configs/colibri_vf.h | 7 ------- scripts/config_whitelist.txt | 5 ----- 3 files changed, 28 deletions(-) (limited to 'include') diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index c65ccb3fd76..e65d9c35580 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -528,22 +528,6 @@ int checkboard(void) return 0; } -int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) -{ - unsigned short usb_pid; - - put_unaligned(CONFIG_TRDX_VID, &dev->idVendor); - - if (is_colibri_vf61()) - usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT; - else - usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT; - - put_unaligned(usb_pid, &dev->idProduct); - - return 0; -} - #ifdef CONFIG_USB_EHCI_VF int board_ehci_hcd_init(int port) { diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 0e622fb5e32..0cd77fff51a 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -208,13 +208,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -/* USB Client Support */ -#define CONFIG_TRDX_VID 0x1B67 -#define CONFIG_TRDX_PID_COLIBRI_VF50 0x0016 -#define CONFIG_TRDX_PID_COLIBRI_VF61 0x0017 -#define CONFIG_TRDX_PID_COLIBRI_VF61IT 0x0018 -#define CONFIG_TRDX_PID_COLIBRI_VF50IT 0x0019 - /* USB DFU */ #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 9851251fa42..d0b5e7f3e4a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7981,11 +7981,6 @@ CONFIG_TRACE_EARLY_ADDR CONFIG_TRACE_EARLY_SIZE CONFIG_TRAILBLAZER CONFIG_TRATS -CONFIG_TRDX_PID_COLIBRI_VF50 -CONFIG_TRDX_PID_COLIBRI_VF50IT -CONFIG_TRDX_PID_COLIBRI_VF61 -CONFIG_TRDX_PID_COLIBRI_VF61IT -CONFIG_TRDX_VID CONFIG_TSEC CONFIG_TSEC1 CONFIG_TSEC1_NAME -- cgit v1.3.1 From ca388143ce87e5b1ae6c3b5eb41fcf8bcecdc0dd Mon Sep 17 00:00:00 2001 From: "mario.six@gdsys.cc" Date: Fri, 18 Nov 2016 14:40:37 +0100 Subject: linux/compat.h: Properly implement ndelay fallback Commit c68c62 ("i2c: mvtwsi: Make delay times frequency-dependent") extensively used the ndelay function with a calculated parameter which is dependant on the configured frequency of the I2C bus. If standard speed is employed, the parameter is usually 10000 (10000ns period length for 100kHz frequency). But, since the arm architecture does not implement a proper version of ndelay, the fallback default from include/linux/compat.h is used, which defines every ndelay as udelay(1). This causes problems for slower speeds on arm, since the delay time is now 9us too short for the desired frequency, which leads to random failures of the I2C interface. To remedy this, we implement a proper, parameter-aware ndelay fallback for architectures that don't implement a real ndelay function. Reported-By: Jason Brown To: Tom Rini To: Heiko Schocher Signed-off-by: Mario Six --- include/linux/compat.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/compat.h b/include/linux/compat.h index c7fd649f5ea..533983faffc 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -15,7 +15,7 @@ struct p_current{ extern struct p_current *current; -#define ndelay(x) udelay(1) +#define ndelay(x) udelay((x) < 1000 ? 1 : (x)/1000) #define dev_dbg(dev, fmt, args...) \ debug(fmt, ##args) -- cgit v1.3.1 From ac34286647a3404a63a7d48644d0d577698c42e2 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 18 Nov 2016 11:56:15 -0600 Subject: keystone2: Move target selection to Kconfig The config option TARGET_K2x_EVM is set by the k2x defconfigs to pick a board target, but the header configs also set K2x_EVM. This config is redundant, remove it and use TARGET_K2x_EVM everywhere in its place. Signed-off-by: Andrew F. Davis Reviewed-by: Lokesh Vutla --- arch/arm/mach-keystone/Makefile | 4 ++-- board/ti/ks2_evm/Makefile | 18 +++++++++--------- include/configs/k2e_evm.h | 1 - include/configs/k2g_evm.h | 1 - include/configs/k2hk_evm.h | 1 - include/configs/k2l_evm.h | 1 - 6 files changed, 11 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index b2ffe5bc2f2..8253a3bcc11 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -18,5 +18,5 @@ endif obj-y += msmc.o obj-y += ddr3.o obj-y += keystone.o -obj-$(CONFIG_K2E_EVM) += ddr3_spd.o -obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o +obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_spd.o +obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_spd.o diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 7ef2d2bff5a..879f8b59835 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -6,12 +6,12 @@ # obj-y += board.o -obj-$(CONFIG_K2HK_EVM) += board_k2hk.o -obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o -obj-$(CONFIG_K2E_EVM) += board_k2e.o -obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o -obj-$(CONFIG_K2L_EVM) += board_k2l.o -obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o -obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o -obj-$(CONFIG_K2G_EVM) += board_k2g.o -obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o +obj-$(CONFIG_TARGET_K2HK_EVM) += board_k2hk.o +obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_k2hk.o +obj-$(CONFIG_TARGET_K2E_EVM) += board_k2e.o +obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_k2e.o +obj-$(CONFIG_TARGET_K2L_EVM) += board_k2l.o +obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_k2l.o +obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_cfg.o +obj-$(CONFIG_TARGET_K2G_EVM) += board_k2g.o +obj-$(CONFIG_TARGET_K2G_EVM) += ddr3_k2g.o diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 8d6471ae886..777f22540af 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -12,7 +12,6 @@ /* Platform type */ #define CONFIG_SOC_K2E -#define CONFIG_K2E_EVM /* U-Boot general configuration */ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index a14544526c7..2da0d8dd7f0 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -12,7 +12,6 @@ /* Platform type */ #define CONFIG_SOC_K2G -#define CONFIG_K2G_EVM /* U-Boot general configuration */ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 913d4545b81..4adb119b306 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -12,7 +12,6 @@ /* Platform type */ #define CONFIG_SOC_K2HK -#define CONFIG_K2HK_EVM /* U-Boot general configuration */ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 395e61c21d5..9bdd56570be 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -12,7 +12,6 @@ /* Platform type */ #define CONFIG_SOC_K2L -#define CONFIG_K2L_EVM /* U-Boot general configuration */ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ -- cgit v1.3.1 From 979a1f8b21aded450d34bddbc99804f7e6489622 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 18 Nov 2016 11:56:16 -0600 Subject: ti_armv7_keystone2: env: Add NFS loading support for PMMC and MON NFS loading support has been added to the default environment for most boot components, as PMMC and MON loading were added later they did not originally get the NFS commands added, add these now. Signed-off-by: Andrew F. Davis Reviewed-by: Lokesh Vutla --- include/configs/ti_armv7_keystone2.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 7e365aa6c60..cfb4b30da79 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -220,6 +220,8 @@ "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \ "run set_rd_spec\0" \ + "init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \ + "run set_rd_spec\0" \ "init_fw_rd_ramfs=setenv rd_spec -\0" \ "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \ "run set_rd_spec\0" \ @@ -228,6 +230,7 @@ "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \ "dev_pmmc=0\0" \ "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \ + "get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \ "get_pmmc_ramfs=run get_pmmc_net\0" \ "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \ "${bootdir}/${name_pmmc}\0" \ -- cgit v1.3.1 From 5991703e88f320767d9390d64a6a9bd62560696b Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 21 Nov 2016 10:58:52 -0800 Subject: spl: dfu: move DFU Kconfig to SPL Kconfig The DFU Kconfig menu entries should be part of the SPL Kconfig file. Also avoid using the top level Makefile by moving the config dependent build artifacts to the driver/ and driver/usb/gadget/ Makfiles. With that, DFU can be built again in SPL if CONFIG_SPL_DFU_SUPPORT is enabled. Fixes: 6ad6102246d8 ("usb:gadget: Disallow DFU in SPL for now") Signed-off-by: Stefan Agner Reviewed-by: Simon Glass Acked-by: Lukasz Majewski --- Kconfig | 27 --------------------------- common/spl/Kconfig | 26 ++++++++++++++++++++++++++ drivers/Makefile | 3 +++ drivers/usb/gadget/Makefile | 8 ++++++-- include/configs/dra7xx_evm.h | 1 - scripts/Makefile.spl | 3 --- 6 files changed, 35 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index f3a9f73dd0f..529858a79da 100644 --- a/Kconfig +++ b/Kconfig @@ -292,33 +292,6 @@ config FIT_IMAGE_POST_PROCESS injected into the FIT creation (i.e. the blobs would have been pre- processed before being added to the FIT image). -config SPL_DFU_SUPPORT - bool "Enable SPL with DFU to load binaries to memory device" - depends on USB - help - Currently the SPL does not have capability to load the - binaries or boot images to boot devices like ram,eMMC,SPI,etc. - This feature enables the DFU (Device Firmware Upgarde) in SPL with - RAM memory device support. The ROM code will load and execute - the SPL built with dfu. The user can load binaries (u-boot/kernel) to - selected device partition from host-pc using dfu-utils. - This feature will be useful to flash the binaries to factory - or bare-metal boards using USB interface. - -choice - bool "DFU device selection" - depends on SPL_DFU_SUPPORT - -config SPL_DFU_RAM - bool "RAM device" - depends on SPL_DFU_SUPPORT - help - select RAM/DDR memory device for loading binary images - (u-boot/kernel) to the selected device partition using - DFU and execute the u-boot/kernel from RAM. - -endchoice - config SYS_CLK_FREQ depends on ARC || ARCH_SUNXI int "CPU clock frequency" diff --git a/common/spl/Kconfig b/common/spl/Kconfig index df9e0ce68f9..77eadf92fe0 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -524,6 +524,32 @@ config SPL_USB_SUPPORT config options. This enables loading from USB using a configured device. +config SPL_DFU_SUPPORT + bool "Support DFU (Device Firmware Upgarde)" + depends on SPL + select SPL_HASH_SUPPORT + help + This feature enables the DFU (Device Firmware Upgarde) in SPL with + RAM memory device support. The ROM code will load and execute + the SPL built with dfu. The user can load binaries (u-boot/kernel) to + selected device partition from host-pc using dfu-utils. + This feature is useful to flash the binaries to factory or bare-metal + boards using USB interface. + +choice + bool "DFU device selection" + depends on SPL_DFU_SUPPORT + +config SPL_DFU_RAM + bool "RAM device" + depends on SPL_DFU_SUPPORT + help + select RAM/DDR memory device for loading binary images + (u-boot/kernel) to the selected device partition using + DFU and execute the u-boot/kernel from RAM. + +endchoice + config SPL_WATCHDOG_SUPPORT bool "Support watchdog drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 761d0b3e85b..40aba582629 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,6 +34,9 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/ +obj-$(CONFIG_SPL_DFU_SUPPORT) += usb/gadget/ +obj-$(CONFIG_SPL_DFU_SUPPORT) += usb/gadget/udc/ +obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index acc9964e232..5b18e8c1950 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -8,6 +8,10 @@ obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_DFU_SUPPORT) += f_dfu.o +endif + # new USB gadget layer dependencies ifdef CONFIG_USB_GADGET obj-$(CONFIG_USB_GADGET_AT91) += at91_udc.o @@ -18,13 +22,13 @@ obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o -obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o -endif obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o endif +endif ifdef CONFIG_USB_ETHER obj-y += ether.o obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 1834d04afde..75a78542045 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -134,7 +134,6 @@ #undef CONFIG_CMD_BOOTD #ifdef CONFIG_SPL_DFU_SUPPORT #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 -#define CONFIG_SPL_HASH_SUPPORT #define DFU_ALT_INFO_RAM \ "dfu_alt_info_ram=" \ "kernel ram 0x80200000 0x4000000;" \ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 03a2f061a46..23b3997076f 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -66,9 +66,6 @@ endif libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ libs-y += drivers/ -libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/dfu/ -libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/gadget/ -libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/gadget/udc/ libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/dwc3/ libs-y += dts/ libs-y += fs/ -- cgit v1.3.1