From 1fae23899c7d6a7f44dec6a963d6c74ce5fe5c19 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 2 Dec 2019 20:40:28 -0300 Subject: warp7: Fix U-Boot corruption after saving the environment U-Boot binary has grown in such a way that it goes beyond the reserved area for the environment variables. Running "saveenv" followed by a "reset" causes U-Boot to hang because of this overlap. Fix this problem by increasing the CONFIG_ENV_OFFSET size. Also, in order to prevent this same problem in the future, use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time. CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare CONFIG_ENV_OFFSET with its direct value instead. Signed-off-by: Fabio Estevam Acked-by: Pierre-Jean Texier Tested-by: Pierre-Jean Texier Acked-by: Joris Offouga Tested-by: Joris Offouga --- include/configs/warp7.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 9a82581c5f3..da894ec0ca0 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -125,6 +125,19 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* + * Environment starts at CONFIG_ENV_OFFSET= 0xC0000 = 768k = 768*1024 = 786432 + * + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 + /* I2C configs */ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 -- cgit v1.3.1 From 949b5a969d107613b61a1e5eaf9e43c75a97f42c Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 3 Dec 2019 14:04:46 +0200 Subject: common: fdt_support: add support for setting usable memory Add support for setting linux,usable-memory property in the memory node of device tree for the kernel [1]. This property holds a base address and size, describing a limited region in which memory may be considered available for use by the kernel. Memory outside of this range is not available for use. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/chosen.txt Signed-off-by: Igor Opaniuk Signed-off-by: Sanchayan Maity Signed-off-by: Stefan Agner Reviewed-by: Oleksandr Suvorov --- common/fdt_support.c | 35 +++++++++++++++++++++++++++++++++++ include/fdt_support.h | 1 + 2 files changed, 36 insertions(+) (limited to 'include') diff --git a/common/fdt_support.c b/common/fdt_support.c index 68343990395..02cf5c6241b 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -467,6 +467,41 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) } return 0; } + +int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int areas) +{ + int err, nodeoffset; + int len; + u8 tmp[8 * 16]; /* Up to 64-bit address + 64-bit size */ + + if (areas > 8) { + printf("%s: num areas %d exceeds hardcoded limit %d\n", + __func__, areas, 8); + return -1; + } + + err = fdt_check_header(blob); + if (err < 0) { + printf("%s: %s\n", __func__, fdt_strerror(err)); + return err; + } + + /* find or create "/memory" node. */ + nodeoffset = fdt_find_or_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + return nodeoffset; + + len = fdt_pack_reg(blob, tmp, start, size, areas); + + err = fdt_setprop(blob, nodeoffset, "linux,usable-memory", tmp, len); + if (err < 0) { + printf("WARNING: could not set %s %s.\n", + "reg", fdt_strerror(err)); + return err; + } + + return 0; +} #endif int fdt_fixup_memory(void *blob, u64 start, u64 size) diff --git a/include/fdt_support.h b/include/fdt_support.h index cefb2b2cce2..2286ea77939 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -94,6 +94,7 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size); */ #ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks); +int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int banks); #else static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) -- cgit v1.3.1 From 7d84f4469f1e3956e8adf4c201df1b5fec435916 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Nov 2019 09:39:08 +0100 Subject: ARM: imx: vining2000: Convert to SPL framework In preparation for use of DDR DRAM fine-tuning upon boot, convert the board to SPL framework instead of using DCD tables to bring up DRAM and pinmux. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Silvio Fricke Cc: Stefano Babic --- arch/arm/mach-imx/mx6/Kconfig | 1 + board/softing/vining_2000/vining_2000.c | 182 ++++++++++++++++++++++++++++++++ configs/vining_2000_defconfig | 12 ++- include/configs/vining_2000.h | 4 + 4 files changed, 198 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 607210520fd..ef816a24ffa 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000 select DM select DM_THERMAL select MX6SX + select SUPPORT_SPL imply CMD_DM config TARGET_WANDBOARD diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index 78692e92408..9ac17f78e73 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -433,3 +433,185 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include + +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR }; + +static iomux_v3_cfg_t const uart_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void vining2000_spl_setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +int board_mmc_init(bd_t *bis) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000028, + .dram_cas = 0x00000028, + .dram_odt0 = 0x00000028, + .dram_odt1 = 0x00000028, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000028, +}; + +const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000028, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_ctlds = 0x00000028, + .grp_ddr_type = 0x000c0000, + .grp_ddrmode = 0x00020000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x0022001C, + .p0_mpwldectrl1 = 0x001F001A, + .p0_mpdgctrl0 = 0x01380134, + .p0_mpdgctrl1 = 0x0124011C, + .p0_mprddlctl = 0x42404444, + .p0_mpwrdlctl = 0x36383C38, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1391, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */ + writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */ + writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */ + writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */ + writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */ + writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */ + writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */ +} + +static void vining2000_spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width / 32, + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* RTT_wr = RZQ/4 */ + .rtt_nom = 1, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux setup */ + vining2000_spl_setup_iomux_uart(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + vining2000_spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 32ef01b6399..4f9f5381894 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -1,18 +1,29 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TARGET_SOFTING_VINING_2000=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg" CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -53,7 +64,6 @@ CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y -CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 54c8c2f62ef..377406f842f 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -91,4 +91,8 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ #endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 26822fd23cb1cf5eebe88547d879c01756228748 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Nov 2019 09:39:10 +0100 Subject: ARM: imx: vining2000: Convert to ethernet DM Convert the board to ethernet DM support. Adjust board file accordingly, as the board_eth_init() contains custom clock configuration required for this board to work. Furthermore, enable FEC1 clock to make FEC1 work as well. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Silvio Fricke Cc: Stefano Babic --- board/softing/vining_2000/vining_2000.c | 38 +++++---------------------------- configs/vining_2000_defconfig | 3 +++ include/configs/vining_2000.h | 2 -- 3 files changed, 8 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index c6aee4ee2b0..b6f1415bb5a 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -72,42 +72,23 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) | - MUX_MODE_SION, - /* LAN8720 PHY Reset */ - MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static iomux_v3_cfg_t const pwm_led_pads[] = { MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */ MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */ MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */ }; -#define PHY_RESET IMX_GPIO_NR(5, 9) - -int board_eth_init(bd_t *bis) +static int board_net_init(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; unsigned char eth1addr[6]; + int ret; - /* just to get secound mac address */ + /* just to get second mac address */ imx_get_mac_from_fuse(1, eth1addr); if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) eth_env_set_enetaddr("eth1addr", eth1addr); - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - /* * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by @@ -123,15 +104,7 @@ int board_eth_init(bd_t *bis) if (ret) goto eth_fail; - /* reset phy */ - gpio_request(PHY_RESET, "PHY-reset"); - gpio_direction_output(PHY_RESET, 0); - mdelay(16); - gpio_set_value(PHY_RESET, 1); - mdelay(1); - - ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, - IMX_FEC_BASE); + ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) goto eth_fail; @@ -139,7 +112,6 @@ int board_eth_init(bd_t *bis) eth_fail: printf("FEC MXC: %s:failed (%i)\n", __func__, ret); - gpio_set_value(PHY_RESET, 0); return ret; } @@ -424,7 +396,7 @@ int board_init(void) setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif - return 0; + return board_net_init(); } int checkboard(void) diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 512c15baf80..df09cfedb93 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -59,6 +59,9 @@ CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 377406f842f..0c0baf27385 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -58,8 +58,6 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ -#define CONFIG_FEC_MXC - #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 -- cgit v1.3.1 From 5c1c7c1ef81503ccae531704ac9dbd8cb41e5b49 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 21 Oct 2019 17:31:53 +0200 Subject: imx: imx8qxp_mek: increase buffer sizes and args number The default value of CONFIG_SYS_CBSIZE is too small when we need to input long commands or when using long kernel command line. The default value of CONFIG_SYS_MAXARGS is too small to add a long command line, and the kernel might not boot as intended without the complete bootargs. Increase argument buffer sizes and the number of arguments. Signed-off-by: Anatolij Gustschin Reviewed-by: Peng Fan --- include/configs/imx8qxp_mek.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index cb39bcdebf5..81ac4b52f3b 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -196,4 +196,9 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define FEC_QUIRK_ENET_MAC +/* Misc configuration */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + #endif /* __IMX8QXP_MEK_H */ -- cgit v1.3.1