From 2f1c8b29f08e4b1915c533662479342ef1d14a51 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Tue, 10 Feb 2026 11:40:31 -0600
Subject: Squashed 'dts/upstream/' changes from 08831944f4e7..258d5b0e2447

258d5b0e2447 Merge tag 'v6.19-dts-raw'
86af5e1bcfa6 Merge tag 'sound-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
7926bd58a9e6 ASoC: dt-bindings: ti,tlv320aic3x: Add compatible string ti,tlv320aic23
1f9a05ba82aa Merge tag 'v6.19-rc8-dts-raw'
a1331106ed0e Merge tag 'sound-6.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
1f3b793812ad Merge tag 'pinctrl-v6.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
83d4f0ccb003 dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: fix 'usb32_drvvbus0' group name
8330000d64b9 Merge tag 'v6.19-rc7-dts-raw'
e1c8a6586b9e Merge tag 'char-misc-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
9d7f49814a08 Merge tag 'drm-fixes-2026-01-23' of https://gitlab.freedesktop.org/drm/kernel
33e10575ba67 Merge tag 'mediatek-drm-fixes-20260119' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes
502e301bd09b Merge tag 'soc-fixes-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
77cb239b1bd2 Merge tag 'qcom-arm64-fixes-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
7f4c4555bace Merge tag 'v6.19-rc6-dts-raw'
877a96726500 dt-bindings: display: mediatek: Fix typo 'hardwares' to 'hardware'
164dd16eee3f ASoC: dt-bindings: fsl,sai: Add support for i.MX952 platform
a206091d6bb4 Merge tag 'phy-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
0f012bccce3a Merge tag 'usb-6.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
d0b33b5b8f70 Merge tag 'i2c-for-6.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
9636e6e27a46 Merge tag 'loongarch-fixes-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
1181e2804bc4 LoongArch: dts: loongson-2k1000: Fix i2c-gpio node names
03efda1ffbf8 LoongArch: dts: loongson-2k2000: Add default interrupt controller address cells
3a83a163ea30 LoongArch: dts: loongson-2k1000: Add default interrupt controller address cells
a11729816e99 LoongArch: dts: loongson-2k0500: Add default interrupt controller address cells
523b55566cd5 LoongArch: dts: Describe PCI sideband IRQ through interrupt-extended
194463f5b49c Merge tag 'sound-6.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
d8169cba2a74 Merge tag 'icc-6.19-rc6' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-linus
2f9163f99b22 Merge tag 'v6.19-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
58af343bca3c Merge tag 'at91-fixes-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes
49b8d68a25d7 Revert "arm64: tegra: Add interconnect properties for Tegra210"
2748575beb27 ASoC: rt5640: Fix duplicate clock properties in DT binding
be9fcab781f7 ASoC: Fix sdw_utils calling wrong codec init callbacks
45fc8146dea3 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
62eee78f7ba7 ASoC: dt-bindings: realtek,rt5640: Various fixes
f92c6f41e54e dt-bindings: i2c: brcm,iproc-i2c: Allow 2 reg entries for brcm,iproc-nic-i2c
572c414fb856 Merge tag 'v6.19-rc5-dts-raw'
29dd1e5883e6 ASoC: dt-bindings: rockchip-spdif: Allow "port" node
99c313ffb090 ASoC: dt-bindings: realtek,rt5640: Allow 7 for realtek,jack-detect-source
01d8ff76dd16 ASoC: dt-bindings: realtek,rt5640: Add missing properties/node
bba647abc3d4 treewide: Update email address
bea77a103df4 Merge tag 'soc-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
62eb1ba19c9f arm64: dts: rockchip: Drop unsupported properties
8f4c82a56b75 arm64: dts: rockchip: Fix gpio pinctrl node names
e1afff67bb26 arm64: dts: rockchip: Fix pinctrl property typo on rk3326-odroid-go3
abc7ff4fa7cc arm64: dts: rockchip: Drop "sitronix,st7789v" fallback compatible from rk3568-wolfvision
2eacc2e311e5 ASoC: dt-bindings: realtek,rt5640: Document port node
8dcd926c2349 ASoC: dt-bindings: realtek,rt5640: Update jack-detect
60fd2fe95a61 ASoC: dt-bindings: realtek,rt5640: Document mclk
8f283674df60 ARM: dts: microchip: sama7d65: fix size-cells property for i2c3
a4a74fdd79d7 ARM: dts: microchip: sama7d65: fix the ranges property for flx9
768bc98f0c73 arm64: dts: hisilicon: hikey960: Drop "snps,gctl-reset-quirk" and "snps,tx_de_emphasis*" properties
66ca60cee08d Merge tag 'imx-fixes-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
f2ae6fb8d2bd Merge tag 'arm-soc/for-6.19/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
7417cdaa2912 dt-bindings: usb: qcom,dwc3: Correct MSM8994 interrupts
a4f29bd59e2a dt-bindings: usb: qcom,dwc3: Correct IPQ5018 interrupts
19e6816f1350 arm64: dts: rockchip: Fix wrong register range of rk3576 gpu
1e400df21c02 arm64: dts: rockchip: Configure MCLK for analog sound on NanoPi M5
8c9a93b38ec0 arm64: dts: rockchip: Fix headphones widget name on NanoPi M5
1bfe67dbe5bb ASoC: codecs: wsa88xx: fix codec initialisation
1412489cfbd5 ASoC: dt-bindings: everest,es8316: Add interrupt support
461f7cf8be63 scsi: ufs: dt-bindings: Fix several grammar errors
4d3756633c63 ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290
81b662a43c49 Merge tag 'v6.19-rc3-dts-raw'
19c1bd2813e7 arm64: dts: mba8mx: Fix Ethernet PHY IRQ support
4ed668fdaf40 arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart
12b18bdb44b3 arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM
eb06a9096fef arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells
021df8e41fee arm64: dts: freescale: moduline-display: fix compatible
93e9aa7a1669 dt-bindings: arm: fsl: moduline-display: fix compatible
a588078496ba ARM: dts: imx6q-ba16: fix RTC interrupt level
d2ba45091bab arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position
2d7ef734fa23 arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt
4b75c0253167 arm64: dts: add off-on-delay-us for usdhc2 regulator
c02d054fa126 arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level
a0acfe0b87c5 ARM: dts: nxp: imx: Fix mc13xxx LED node names
1dd510906b1b arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP
1006ba3a4e50 Merge tag 'riscv-for-linus-6.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
d9aad3641f09 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for qcs8300
08a8dbe8ea5d Merge tag 'v6.19-rc2-dts-raw'
32a7dfc2a476 arm64: dts: rockchip: remove redundant max-link-speed from nanopi-r4s
d192b24273e0 arm64: dts: rockchip: remove dangerous max-link-speed from helios64
e7792596b75b arm64: dts: rockchip: fix unit-address for RK3588 NPU's core1 and core2's IOMMU
03ab33a3ea96 arm64: dts: rockchip: Fix wifi interrupts flag on Sakura Pi RK3308B
7d3e6b50f8c0 Merge tag 'ti-k3-dt-fixes-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/fixes
11efdf36dfc0 spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers
a6b2fb534f29 Merge tag 'input-for-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
5dbdc4ae9355 Merge tag 'i2c-for-6.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
8639177dffeb Merge tag 'spi-fix-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
17c33897cd62 Merge tag 'mmc-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
afb7d1a01985 arm64: dts: broadcom: rp1: drop RP1 overlay
50528aeede8d arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topology
7b7100699630 dt-bindings: misc: pci1de4,1: add required reg property for endpoint
2f0f22b271f4 dt-bindings: interconnect: qcom,sa8775p-rpmh: Fix incorrectly added reg and clocks
7a9fcf6ab8f2 dt-bindings: riscv: add Zilsd and Zclsd extension descriptions
cc436e4bc50c Input: add ABS_SND_PROFILE
faad43a2fb2a spi: dt-bindings: snps,dw-abp-ssi: Allow up to 16 chip-selects
584de0162a57 dt-bindings: i2c: qcom-cci: Document SM8750 compatible
b8509bd4f32a dt-bindings: i2c: dw: Add Mobileye I2C controllers
dd8343780c17 arm64: dts: qcom: sm8650: Fix compile warnings in USB controller node
d891d1e44d3e arm64: dts: qcom: sm8550: Fix compile warnings in USB controller node
cb861cf39009 arm64: dts: qcom: sc8280xp: Add missing VDD_MXC links
e930c3218822 dt-bindings: power: qcom,rpmpd: Add SC8280XP_MXC_AO
1627e784e086 arm64: dts qcom: sdm845-oneplus-enchilada: Specify panel name within the compatible
56b2a3870e60 arm64: dts: qcom: talos: Correct UFS clocks ordering
a7ac0ad91575 dt-bindings: Updates Linus Walleij's mail address
2143a2a3696b dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3U
5ec0ea9129e0 dt-bindings: clock: sprd,sc9860-clk: Allow "reg" for gate clocks
118700447365 dt-bindings: display/ti: Simplify dma-coherent property
c769e2c753c5 ARM: dts: ixp4xx: Fix up Actiontec MI424WR DTS files
35f2008fe122 arm64: dts: ti: k3-am62-lp-sk-nand: Rename pinctrls to fix schema warnings
c62f0039d689 arm64: dts: ti: k3-am642-phyboard-electra-x27-gpio1-spi1-uart3: Fix schema warnings
584f2cf7a1d8 arm64: dts: ti: k3-am642-phyboard-electra-peb-c-010: Fix icssg-prueth schema warning
c3ccb7a83fcf arm64: dts: rockchip: Fix voltage threshold for volume keys for Pinephone Pro
628d2318ea83 dt-bindings: mmc: sdhci-of-aspeed: Switch ref to sdhci-common.yaml
646e03d391d2 Merge tag 'v6.19-rc1-dts-raw'
27e4159cadfc Merge tag 'rtc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
56e0cdaf295b Merge tag 'soundwire-6.19-rc1_updated' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire
7b5150ead399 Merge tag 'sound-fix-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
3d0dabf47b0f Merge tag 'asoc-fix-v6.19-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
f0f0934250b6 Merge tag 'input-for-v6.19-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
e2edeb14808f Merge tag 'i2c-for-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
6a443624d1cf Merge branch 'next' into for-linus
30e39af54e44 Merge tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
f5fad51ae2d8 dt-bindings: rtc: Add Apple SMC RTC
cfd5b64c715b Merge tag 'dmaengine-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
bf630f2ac706 Merge tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
4c7e2e0b8f26 dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support
9fb50b526fb0 Merge tag 'i2c-host-6.19-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
e27e9cf06665 dt-bindings: soundwire: qcom: Document v3.1.0 version of IP block
9249f0d52630 dt-bindings: soundwire: qcom: deprecate qcom,din/out-ports
b3eae11a0c46 Merge tag 'i3c/for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
3c339b1de131 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
e6efd6183089 ALSA: hda: dt-bindings: add CIX IPBLOQ HDA controller support
3f18f200ae0c Merge tag 'usb-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
10d06d57c9c1 Merge tag 'tty-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
f0da425ddb66 Merge tag 'char-misc-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
947229d06868 Merge tag 'linux-watchdog-6.19-rc1' of git://www.linux-watchdog.org/linux-watchdog
402fe30160ad Merge tag 'rproc-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
5d7ed5b55b1d Merge tag 'for-linus-6.19-1' of https://github.com/cminyard/linux-ipmi
28dbe2f83d26 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
87dc53e08620 Merge tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
925ae13a2bc0 Merge tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
15ee02f5bb4f Merge tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
acaf7715ccdc Merge tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
2226fdf89832 Merge tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
b3efeb8fd0a4 Merge tag 'powerpc-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
1007eb4a119f Merge tag 'mm-stable-2025-12-03-21-26' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
2daf1f09b739 Merge tag 'samsung-dt-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
21ffee4e251b Merge tag 'ata-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
9ef7d05e4c00 Merge tag 'iommu-updates-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
d65bb5ca843f Merge tag 'pci-v6.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
1e581e9ba93d Merge tag 'for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
91b1b0270bd7 Merge tag 'devicetree-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
d84b6399f857 Merge tag 'backlight-next-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
ff977c9fe689 Merge tag 'leds-next-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
24c5fe1d1482 Merge tag 'mfd-next-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
d53721d1dc98 Merge tag 'mmc-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
cf41b8a9c709 Merge tag 'pmdomain-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
7118ea488296 Merge tag 'gpio-updates-for-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
33a751c4ea8b Merge tag 'hwmon-for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
de27e96c19f9 Merge tag 'gnss-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss
d1d1ebe68816 Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
f87b749b52ff Merge tag 'regulator-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
59244e8baa96 Merge tag 'mtd/for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
327ef46abee0 Merge tag 'pwm/for-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
e1c0999f1e4f Merge tag 'sound-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
eba9eb3da2ab Merge tag 'drm-next-2025-12-03' of https://gitlab.freedesktop.org/drm/kernel
b4a84bb51adf Merge tag 'media/v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
665df3b38f4a Merge tag 'net-next-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
9fc6be695aed Merge branch 'pci/pwrctrl-tc9563'
4713187ca3d3 Merge branch 'pci/controller/spacemit-k1'
9066544f73d0 Merge branch 'pci/controller/sky1'
426ebab3fd95 Merge branch 'pci/controller/s32g'
64f76bf74cd4 Merge branch 'pci/controller/rzg3s-host'
7454f63455a2 Merge branch 'pci/controller/meson'
a1e964ed98bb Merge branch 'pci/controller/mediatek'
e66fd046960f Merge tag 'v6.19-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
67b6a50dea72 Merge branches 'clk-visconti', 'clk-imx', 'clk-microchip', 'clk-rockchip' and 'clk-qcom' into clk-next
e734d4fea59a Merge branches 'clk-socfpga', 'clk-renesas', 'clk-cleanup', 'clk-samsung' and 'clk-mediatek' into clk-next
7bc21d0fa237 dt-bindings: thermal: qcom-tsens: Remove invalid tab character
45eb0cc65e37 dt-bindings: kbuild: Skip validating empty examples
4c6c05eb5803 ASoC: dt-bindings: cirrus,cs42xx8: Reference common DAI properties
a195e4c3af14 Merge tag 'thermal-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
3040d09fb438 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
afac25a15bea dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings
dcf01056aed3 dt-bindings: PCI: s32g: Add NXP S32G PCIe controller
b17fed158404 Merge tag 'timers-clocksource-2025-11-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
c235f1f4f597 Merge tag 'irq-drivers-2025-11-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
2e605626e9e8 Merge tag 'drm-misc-next-2025-12-01-1' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
3b6d4bb205e6 dt-bindings: net: Convert Marvell 8897/8997 bindings to DT schema
e642d5c2d72c dt-bindings: interrupt-controller: brcm,bcm2836-l1-intc: Drop interrupt-controller requirement
779cd90b5b01 dt-bindings: display: Fix brcm,bcm2835-hvs bindings for BCM2712
27f4390e983c dt-bindings: display: bcm2711-hdmi: Add interrupt details for BCM2712
62f947f140b2 Merge tag 'nand/for-6.19' into mtd/next
8ee23f5c68c1 Merge tag 'at24-updates-for-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
cb73a7eadaf4 Merge tag 'wireless-next-2025-11-27' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
ea2ef0c1a161 Merge tag 'thermal-v6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
503164b9b572 Merge branches 'arm/smmu/updates', 'arm/smmu/bindings', 'mediatek', 'nvidia/tegra', 'intel/vt-d', 'amd/amd-vi' and 'core' into next
bca9cb69cc0c Merge tag 'cache-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers-late
9989f1b5ef18 Merge tag 'soc-drivers-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers-late
957f13aa92ac Merge tag 'amlogic-drivers-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers-late
0c49a8219b2d Merge tag 'riscv-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
42def4dee20b arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1
be6fcd8a94cd Merge tag 'amlogic-arm64-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
8dc6331b6ab8 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
bccc1bbfdc87 spi: airoha: add support of en7523 SoC (for 6.19)
c3664ef11fab ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend
510f660b77dd ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend
8ca4e76f8ff8 ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend
ae09f216c8d7 ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend
ae259268b06d spi: dt-bindings: airoha: add compatible for EN7523
c1daad24ada3 spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
e3d8f318594e ASoC: stm32: sai: fix device and OF node leaks on
c3562d7dcd24 regulator: Use container_of_const() when all types are
e058859659c0 dt-bindings: remoteproc: qcom: adsp: Add SDM660 CDSP compatible
885f1168d331 dt-bindings: remoteproc: qcom: adsp: Add missing constrains for SDM660 ADSP
8fa38ed9186e dt-bindings: remoteproc: qcom,sc8280xp-pas: Fix CDSP power desc
be01d536023e dt-bindings: remoteproc: qcom,adsp: Make msm8974 use CX as power domain
3b9c9ed9e0d2 dt-bindings: thermal: fsl,imx91-tmu: add bindings for NXP i.MX91 thermal module
b94cdc0fec55 dt-bindings: thermal: tsens: Add QCS8300 compatible
e31d041fd7c2 dt-bindings: slimbus: fix warning from example
35d8e6a51e12 spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
dc2e0509db05 dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
75baefb7a2ba LoongArch: dts: Add uart new compatible string
8688bf5ec663 dt-bindings: serial: 8250: Add Loongson uart compatible
88edb93f367a dt-bindings: can: mpfs: document resets
aa07baeaf06b dt-bindings: timer: Add Realtek SYSTIMER
a67190264f14 arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
666783f57d99 arm64: dts: Add gpio_intc node for Amlogic S7D SoCs
b02eae55621e arm64: dts: Add gpio_intc node for Amlogic S7 SoCs
0be5b36d2ae9 arm64: dts: Add gpio_intc node for Amlogic S6 SoCs
1dc7c0a79667 arm64: dts: amlogic: s7d: add ao secure node
d4f66f2822e8 arm64: dts: amlogic: s7: add ao secure node
5f577eeae924 arm64: dts: amlogic: s6: add ao secure node
2ce6173652f6 arm64: dts: amlogic: Fix the register name of the 'DBI' region
4698f107b016 dts: arm64: amlogic: add a5 pinctrl node
e2eda8a9ed94 arm64: dts: amlogic: s7d: add power domain controller node
cabd4784af63 arm64: dts: amlogic: s7: add power domain controller node
e0f9ec95b9f8 arm64: dts: amlogic: s6: add power domain controller node
1edfd33d8ced dts: arm64: amlogic: Add ISP related nodes for C3
ea8ce9294888 arm64: dts: meson: add initial device-tree for Tanix TX9 Pro
ac2ffc666cd0 dt-bindings: arm: amlogic: add support for Tanix TX9 Pro
ca39a8e36acb riscv: dts: starfive: add Orange Pi RV
19644ea3243c dt-bindings: riscv: starfive: add xunlong,orangepi-rv
b4e52d094636 riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
fa1b407dfcd9 riscv: dts: starfive: Add VisionFive 2 Lite board device tree
637ceb101cf6 riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
dd59c2ed03a6 riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts
6302fde4f7e1 dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board
1edc03b33bfb dt-bindings: thermal: qcom-tsens: make ipq5018 tsens standalone compatible
9af0cc785f53 Merge tag 'mtk-soc-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
ac0dcd6fc5a3 Merge tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux into soc/drivers
03fa0385ca4f Merge tag 'stm32-bus-firewall-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/drivers
8a85184e1f55 Merge tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
cd791d129e96 dt-bindings: leds: backlight: Add Awinic AW99706 backlight
7632e73179a0 dt-bindings: net: aspeed: add AST2700 MDIO compatible
d40dcf4b9d68 Merge tag 'v6.19-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
2cb74bad23ce arm64: dts: sprd: sc9860: Simplify clock nodes
36d689c4027d dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding
96a83489222a dt-bindings: riscv: Add Svrsw60t59b extension description
982f68da8a3d Add RSPI support for RZ/T2H and RZ/N2H
c80b3bca7be0 dt-bindings: nvmem: imx-ocotp: Add support for i.MX94
8542c736263a dt-bindings: nvmem: don't check node names
9c21064bfd86 dt-bindings: nvmem: mediatek: efuse: Add compatible for MT8189 SoC
1593044c1f15 nvmem: layouts: u-boot-env: add optional "env-size" property
8262ef54b942 dt-bindings: nvmem: Support MediaTek MT8189 evb board efuse
62073706aa64 dt-bindings: nvmem: qfprom: Add sa8775p compatible
e3efb3c7eaa2 dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
3307f4e54c72 dt-bindings: display: bridge: simple: document the ASL CS5263 DP-to-HDMI bridge
439446caa7ea dt-bindings: vendor-prefixes: Add ASL Xiamen Technology
2ae40b561c2f Merge tag 'icc-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
397b18ab014e Merge tag 'coresight-next-v6.19' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
06f9e8161227 dt-bindings: perf: fsl-imx-ddr: Add compatible string for i.MX8QM, i.MX8QXP and i.MX8DXL
af6d2b3f535a spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
119fadd043fa dt-bindings: net: wireless: mt76: introduce backoff limit properties
b4f15e7bbec7 dt-bindings: net: wireless: mt76: Document power-limits country property
516951213a82 dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
1ce3fdf42052 riscv: dts: sifive: unmatched: Add PWM controlled fans
8419e857f922 arm64: dts: rockchip: enable RTC for 100ASK DshanPi A1
c1ce151f2d89 arm64: dts: rockchip: enable USB for 100ASK DshanPi A1
905c343ea51e arm64: dts: rockchip: enable button for 100ASK DshanPi A1
3b4c7ee4f4a4 arm64: dts: rockchip: add mmc aliases for 100ASK DshanPi A1
c4f99ac39c86 arm64: dts: rockchip: remove mmc max-frequency for 100ASK DshanPi A1
b4ace70320a8 arm64: dts: rockchip: Enable i2c2 on Orange Pi 3B
475a7b9f0c5f Merge tag 'imx-bindings-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
1c7d5b0fe443 Merge tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc
ee2c440c1a92 Merge branch 'bst/newsoc' into soc/newsoc
62bf720c5492 arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board
7c361f9c44c3 dt-bindings: arm: add Black Sesame Technologies (bst) SoC
f9b990014b47 dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd.
a0eadb246ed9 Merge tag 'ti-k3-dt-for-v6.19-part2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
cb9bfe671786 Merge tag 'mvebu-dt64-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
1f4a6049f1a0 Merge tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux into soc/dt
847305c3f24f Merge tag 'cix-dt-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt
a42a3c0e98cb Merge tag 'stm32-dt-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
89606ecdb119 Merge tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
1152f849175c Merge tag 'v6.19-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
5fcfc4228157 dt-bindings: hwmon: Add AST2700 compatible
84daef868f58 regulator: Add FP9931/JD9930
68a2e8036bb8 Merge tag 'qcom-arm64-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
e6e8e730c23f Merge tag 'qcom-arm32-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
6bf0faceba14 Merge tag 'omap-for-v6.19/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
f308c050d073 Merge tag 'at91-dt-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
1c7070035b64 Merge tag 'ti-k3-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
d995ab655e56 Merge tag 'socfpga_dts_updates_for_v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
fdc2d78b6b57 Merge tag 'imx-dt64-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
e00f7dd389c0 Merge tag 'imx-dt-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
ba629d597781 Merge tag 'sunxi-dt-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
be66cf860cd8 Merge tag 'tegra-for-6.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
5cd421e3123a Merge tag 'tegra-for-6.19-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
73630f133169 Merge tag 'tegra-for-6.19-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
17ba8d90c389 Merge tag 'renesas-dts-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
976b62289967 Merge tag 'spacemit-dt-for-6.19-1' of https://github.com/spacemit-com/linux into soc/dt
9e991b69b124 Merge tag 'mtk-dts64-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
7b3786b89af4 Merge tag 'mtk-dts32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
fcd4c5826841 Merge tag 'samsung-dt64-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
8fa9835cc7d3 Merge tag 'thead-dt-for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
befe612beffe Merge tag 'renesas-dts-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
f62c1c632762 Merge tag 'aspeed-6.19-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
f09303a5f3d8 Merge tag 'pxa1908-dt-for-6.19' of https://gitlab.com/pxa1908-mainline/linux into soc/dt
4b052167e82b Merge tag 'tenstorrent-dt-for-v6.19' of https://github.com/tenstorrent/linux into soc/newsoc
4d25e1ef679c dt-bindings: display: bridge: it66121: Add compatible string for IT66122
d7255c887d1f Merge tag 'iio-for-6.19a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
821703b3fa8d Merge tag 'fpga-for-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next
bf0cafb99229 dt-bindings: usb: ti,hd3ss3220: Add support for VBUS based on ID state
abdaf4f60231 dt-bindings: usb: dwc3-xilinx: Describe the reset constraint for the versal platform
9673f2075ccb dt-bindings: usb: Add ESWIN EIC7700 USB controller
659aa44f8ffa dt-bindings: usb: qcom,snps-dwc3: Add Kaanapali compatible
653c0274785c dt-bindings: usb: Support MediaTek MT8189 xhci
80eb8105c80e dt-bindings: usb: renesas,rzg3e-xhci: Add RZ/V2H(P) and RZ/V2N support
8a2bef78dfaa dt-bindings: dma: xilinx: Simplify dma-coherent property
dbe7a1baff4f arm64: dts: ti: k3-am62l: Fix unit address of cbass_wakeup
50b0c8ca35e1 arm64: dts: ti: k3-j721e-sk: Fix pinmux for pin Y1 used by power regulator
4d24edb84c16 dt-bindings: clock: tmpv770x: Add VIIF clocks
b843d215bd17 dt-bindings: clock: tmpv770x: Remove definition of number of clocks
3c654987d49a Merge tag 'drm-msm-next-2025-11-18' of https://gitlab.freedesktop.org/drm/msm into drm-next
abb868616dad Merge tag 'v6.18-rc6' into drm-next
809b1a45339a arm64: dts: rockchip: Use default-state for power LED for Radxa boards
74649d601935 arm64: dts: rockchip: fix PCIe 3.3V regulator voltage on 9Tripod X3568 v4
414cc22b2e8a arm64: dts: rockchip: Add power-domain to RK3368 VOP controller
31d944f6636d arm64: dts: rockchip: Add power-domain to RK3368 DSI controller
91301f53e61f arm64: dts: rockchip: Add host wake pin for wifi on Indiedroid Nova
178af26ba893 arm64: dts: rockchip: Correct pinctrl for pcie for Indiedroid Nova
92d7b7ba7ec9 arm64: dts: rockchip: Define regulator for pcie2x1l2 on Indiedroid Nova
b2f6ba0024ca arm64: dts: rockchip: Add clk32k_in for Indiedroid Nova
6cfd5ebf93a9 arm64: dts: rockchip: Add Asus Tinker Board 3 and 3S device tree
9d6bdf2add09 dt-bindings: arm: rockchip: Add Asus Tinker Board 3/3S
f8483f137f15 dt-bindings: arm: rockchip: merge Asus Tinker and Tinker S
a114eb34ab17 dt-bindings: clock, reset: Add support for rv1126b
be3ad0fe4738 arm64: dts: rockchip: add QNAP TS233 devicetree
b357befcca9e dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices
8cf4cbd14444 arm64: dts: rockchip: move common qnap tsx33 parts to dtsi
51b234a762b6 arm64: dts: rockchip: describe mcu eeprom cells on rk3568-ts433
0ac36d180d89 arm64: dts: rockchip: move cpu_thermal node to the correct position
61d39464221f Merge tag 'reset-gpio-for-v6.19' of https://git.pengutronix.de/git/pza/linux into gpio/for-next
0c1be8e245f6 dt-bindings: trivial-devices: add arduino spi mcu interface
09f7d02b9f57 dt-bindings: eeprom: at25: Add Anvo ANV32C81W
73627ae69a22 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
64a97f3e7c19 dt-bindings: phy: imx8mq-usb: add alternate reference clock
658e897aba6d dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
33a067a7e937 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Restrict resets per each device
fc854f0d2f2d dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex
a2f3bf32847f dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
47a1deb97c0c dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506
2ada82eb2d15 dt-bindings: regulator: Add Fitipower FP9931/JD9930
90ea4a71161b dt-bindings: vendor-prefixes: Add Fitipower
5245f5ac59aa dt-bindings: phy: mediatek,tphy: Add support for MT7981
91f5d43be553 dt-bindings: gnss: fix timepulse description
d111d9ffd51e dt-bindings: gnss: u-blox: use lowercase company name
c1b748c776fb dt-bindings: gnss: u-blox: use open-drain reset and safeboot in example
16044ae73ebc dt-bindings: mfd: syscon: Add mt7981-topmisc
bf22a3e79541 Merge patch series "Add OP-TEE based RPMB driver for UFS devices"
9aa6f623b5bb dt-bindings: leds: qcom-lpg: Explain standalone PWM usage
741187978880 dt-bindings: mfd: fsl,mc13xxx: Fix LEDs node schema
9f5151da8413 dt-bindings: mfd: Document syscons falling back to atmel,sama5d2-sfrbu
9a0a098b3f78 dt-bindings: mfd: Document control-scb and sysreg-scb on pic64gx
96b2107be862 ASoC: dt-bindings: ti,tas2781: Add TAS2568/2574/5806M/5806MD/5830 support
a21483bb0da9 dt-bindings: mfd: Convert dlg,da9052-i2c.txt to yaml format
5c870b1ef99a dt-bindings: leds: pwm: Add enable-gpios property
f187d76d9095 Merge branch 6.18/scsi-fixes into 6.19/scsi-staging
153d94e4ee05 dt-bindings: net: mediatek,net: Correct bindings for MT7981
8928546dd85d dt-bindings: fpga: Convert lattice,ice40-fpga-mgr to DT schema
5a89f268ab58 dt-bindings: interrupt-controller: sifive,plic: Add pic64gx compatibility
dcb91b5de537 pmdomain: Merge branch dt into next
76009839f6f9 dt-bindings: riscv: Add Zalasr ISA extension description
f92a9318f15d dt-bindings: panel: Convert Samsung SOFEF00 DDIC into standalone yaml
a8c7599e3488 dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa
bbd8b9f0489e dt-bindings: panel: lvds: add Winstar WF70A8SYJHLNGA
23af80d1106e dt-bindings: display: panel: ronbo,rb070d30: panel-common ref
aae0418c06fd dt-bindings: display: simple: Add Raystar RFF500F-AWH-DNN panel
cf3124e734e5 dt-bindings: vendor-prefixes: Add Raystar Optronics, Inc
99a807c555fc dt-bindings: display: panel: document Samsung LTL106AL01 simple panel
7677716156e4 dt-bindings: display: panel: properly document LG LD070WX3 panel
6768271ceab8 dt-bindings: arm: amlogic: meson-gx-ao-secure: support more SoCs
27a4e818ccab dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline
73303d1b7482 dt-bindings: interconnect: qcom,sm6350-rpmh: Add clocks for QoS
9cef1486f7a3 dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group
1eb93400d8fb dt-bindings: net: cdns,macb: Add pic64gx compatibility
6fc3d0e32680 Merge branch 'icc-kaanapali' into icc-next
6e1745a06e11 dt-bindings: interconnect: qcom-bwmon: Document Kaanapali BWMONs
8afbee7fb9c6 dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
4bf0906e99f4 dt-bindings: clock: qcom: Add SM8750 video clock controller
791b28dba67f regulator: dt-bindings: pca9540: add debounce timer configuration
d777ba4b6f11 ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document
1c9f3266842c ASoC: dt-bindings: mediatek,mt8189-afe-pcm: add audio afe document
0a144023c2ae dt-bindings: PCI: Add binding for Toshiba TC9563 PCIe switch
a48ca996669f phy: Add Renesas RZ/G3E USB3.0 PHY driver
31cf40de4a70 dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
8ad4d2f8b4d3 dt-bindings: display/msm/gmu: Add Adreno X2-85 GMU
a4556a04308c dt-bindings: display/msm/gmu: Add Adreno 840 GMU
232d41799461 dt-bindings: arm-smmu: Add Kaanapali and Glymur GPU SMMU
44e94a7bb545 dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
45073b83681b dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
94155e664cb6 dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
1c2ca5e20aaf dt-bindings: reset: eswin: Documentation for eic7700 SoC
330187a685b2 dt-bindings: reset: microchip: Add LAN969x support
dfbaca5ddb49 dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset
9eeeb5b1e189 dt-bindings: mmc: am654: Simplify dma-coherent property
41d0d821f910 dt-bindings: gpio: mpfs-gpio: Add pic64gx GPIO compatibility
4a3c809a374f dt-bindings: net: sophgo,sg2044-dwmac: add phy mode restriction
34eac94c14f4 riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2
895094a6b909 riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1
42aa02b43aba riscv: dts: sophgo: Enable SPI NOR node for PioneerBox
e071667235dd riscv: dts: sophgo: Add SPI NOR node for SG2042
8a287a1254cb dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
92f39cb09721 dt-bindings: dma: Convert apm,xgene-storm-dma to DT schema
80a1b765a6b0 dt-bindings: thermal: Drop db8500-thermal.txt
3f1d3a7a1303 dt-bindings: thermal: Convert brcm,sr-thermal to DT schema
baf16afa270a dt-bindings: thermal: Convert amazon,al-thermal to DT schema
12d256bc958b docs: dt-bindings: Extend the ordering list with a blank newline before status
5454d8c7d48b dt-bindings: Remove extra blank lines
79d1eee5a642 dt-bindings: Update Krzysztof Kozlowski's email
78e664b9bedd dt-bindings: nvmem: Convert brcm,ocotp to DT schema
30b19e16838e dt-bindings: media: Convert MediaTek mt8173-mdp bindings to DT schema
1ecff1b5d97a dt-bindings: arm: Add missing LGE SoC platforms
f0149f32417d dt-bindings: arm: Add missing AMD Seattle SoC platforms
42c040758581 dt-bindings: arm: Add missing APM X-Gene SoC platforms
714f17eb3a07 dt-bindings: Fix inconsistent quoting
d2be601fa068 dt-bindings: power: Convert Actions Owl SPS to DT schema
e9f1d193115b dt-bindings: gpu: mali-bifrost: Add compatible for MT8365 SoC
0163fae2f4c8 MAINTAINERS: Change Altera socfpga-ecc-manager.yaml maintainer
b6e747808e0e dt-bindings: bus: don't check node names
f7c62ed77b90 dt-bindings: fix redundant quotes on fsl,imx6q-vdoa.yaml
72e07bcbc589 dt-bindings: interrupt-controller: fsl,irqsteer: Add i.MX95 support
44505dd775b0 dt-bindings: arm: Convert Marvell AP80x System Controller to DT schema
485abf9dd94f dt-bindings: arm: Convert Marvell CP110 System Controller to DT schema
f53b234dbd24 dt-bindings: bus: Convert cznic,moxtet to DT schema
d5062ce32326 dt-bindings: pci: spacemit: Introduce PCIe host controller
d9011360a03a dt-bindings: PCI: qcom,pcie-x1e80100: Add missing required power-domains and resets
f310780ef807 dt-bindings: PCI: qcom,pcie-sm8550: Add missing required power-domains and resets
568d5185d173 dt-bindings: PCI: qcom,pcie-sm8450: Add missing required power-domains and resets
50f9f9b01386 dt-bindings: PCI: qcom,pcie-sm8350: Add missing required power-domains and resets
5bd25da87978 dt-bindings: PCI: qcom,pcie-sm8250: Add missing required power-domains and resets
d4a081066054 dt-bindings: PCI: qcom,pcie-sm8150: Add missing required power-domains and resets
a35f401ba1d8 dt-bindings: PCI: qcom,pcie-sc8280xp: Add missing required power-domains and resets
0ad4390bebdb dt-bindings: PCI: qcom,pcie-sc7280: Add missing required power-domains and resets
4cd1ae7b0b2e dt-bindings: PCI: qcom,pcie-sa8775p: Add missing required power-domains and resets
bc3c3a3dafcb arm64: dts: socfpga: agilex5: update qspi partitions for 013b board
f7e4ad742226 arm64: dts: freescale: add Toradex SMARC iMX95
f44dc730947d dt-bindings: arm: fsl: add Toradex SMARC iMX95
24203917e2fd riscv: dts: sophgo: Add USB support for cv18xx
d0a184e33dfd riscv: dts: sophgo: Add syscon node for cv18xx
a41983953178 dt-bindings: soc: sophgo: add TOP syscon for CV18XX/SG200X series SoC
b821bd7c321c arm64: dts: cix: add a compatible string for the cix sky1 SoC
886201218018 arm64: dts: cix: Enable PCIe on the Orion O6 board
e81c86872798 arm64: dts: cix: Add PCIe Root Complex on sky1
b4dd2af28ef7 arm64: dts: freescale: tqma9352: Add vcc-supply for spi-nor
9c68fefce2ac arm64: dts: mb-smarc-2: Add MicIn routing
a9ac5f4fc07c arm64: dts: mba8xx: Add MicIn routing
7cdabf33c783 arm64: dts: mba8mx: Add MicIn routing
e761c431bc8b arm64: dts: imx8mp: make 'dsp' node depend on 'aips5'
36e5fb59fa0e arm64: dts: imx8mp: convert 'aips5' to 'aipstz5'
65178037df21 arm64: dts: imx8mp-skov: add Rev.C HDMI support
b2591965d718 arm64: dts: imx8mp: Add missing LED enumerators for DH electronics i.MX8M Plus DHCOM on PDK2
8f369bc914dd arm64: dts: freescale: Add GMAC Ethernet for S32G2 EVB and RDB2 and S32G3 RDB3
071baf8fc95e arm64: dts: imx8qm-apalis: add pwm used by the backlight
e1b080329b4f arm64: dts: imx95-tqma9596sa-mb-smarc-2: add aliases for SPI
1120cc74c831 arm64: dts: imx95-tqma9596sa-mb-smarc-2: remove superfluous line
fec380ea8019 arm64: dts: imx95-tqma9596sa-mb-smarc-2: mark LPUART1 as reserved
c5c3abab4ed0 arm64: dts: imx95-tqma9596sa-mb-smarc-2: Add MicIn routing
da5988db69cf arm64: dts: imx95-tqma9596sa: add EEPROM pagesize
1cc13350904d arm64: dts: imx95-tqma9596sa: whitespace fixes
b81b19e833c6 arm64: dts: imx95-tqma9596sa: add gpio bus recovery for i2c
f3834bb20801 arm64: dts: imx95-tqma9596sa: remove superfluous pinmux for usdhci
a962997f532a arm64: dts: imx95-tqma9596sa: remove superfluous pinmux for i2c
25a2b79cb1ff arm64: dts: imx95-tqma9596sa: remove superfluous pinmux for flexspi
c332324a7bdf arm64: dts: imx95-tqma9596sa: update pcie config
952658c10446 arm64: dts: imx95-tqma9596sa: move pcie config to SOM
1c4bf14d7860 arm64: dts: imx95-tqma9596sa: move sai config to SOM
a1aa7d2f1fc0 arm64: dts: imx95-tqma9596sa: move USDHC2 config to SOM
4f9bad95e130 arm64: dts: imx95-tqma9596sa: move lpspi3 pinctrl to SOM
3e0c2e4bf8f9 arm64: dts: imx95-tqma9596sa: move flexcan pinctrl to SOM
8ee5d35c2d88 arm64: dts: imx95-tqma9596sa: increase flexspi slew rate
4632f3053a2b arm64: dts: imx95-tqma9596sa: reduce maximum FlexSPI frequency to 66MHz
e43c77b56a39 arm64: dts: imx95-tqma9596sa: fix TPM5 pinctrl node name
177c9d1dd92a spi: dt-bindings: aspeed,ast2600-fmc: Add AST2700 SoC support
c0fc41d867a9 ARM: dts: imx6qdl: make VAR-SOM SoM SoC-agnostic
3b409a511bf3 dt-bindings: arm: fsl: add Skov Rev.C HDMI support
b523a045dfd0 ARM: dts: imx6dl-yapp4: Model the RGB LED as a single multi-led part
687cae3410bc ARM: dts: imx6dl-yapp43: Enable pwm-beeper on boards with speaker
a116e20574fe dt-bindings: display: bridge: simple: document the Parade PS185HDM DP-to-HDMI bridge
64a7ad775ee3 arm64: dts: freescale: imx93-var-som: Add support for ADS7846 touchscreen
93e6908cead5 arm64: dts: freescale: imx93-var-som: Add support for WM8904 audio codec
de57aeea59d5 arm64: dts: freescale: imx93-var-som: Add PMIC support
30c87f150c23 arm64: dts: freescale: imx93-var-som: Add WiFi and Bluetooth support
4206d8a8eaff arm64: dts: imx8qxp-mek: change space with tab
bde1ec894e46 arm64: dts: imx8qxp-mek: Add lpuart1 to support the M.2 PCIE9098 bluetooth
7103aaff26d3 arm64: dts: imx8: add edma error interrupt support
a11dc4d5eb5d arm64: dts: imx8qxp-mek: add fec2 support
e6b0301a978d arm64: dts: imx8qxp-mek: add phandle ocotp mac-address for fec
8cc19662721d arm64: dts: imx8qxp-mek: add flexspi and flash
33b42350e3e1 arm64: dts: imx8qxp-mek: update usdhc1 clock to 400Mhz
b16e4c203bc5 arm64: dts: imx8qxp-mek: add state_100mhz and state_200mhz for usdhc
81bfde80b832 arm64: dts: imx8qxp: add wakeup source for power-key
169514b110ec arm64: dts: imx8qxp: add MAC address in ocotp
384828b1980e arm64: dts: imx8qm-mek: replace space with tab
4ddd8dcf7125 arm64: dts: imx8qm-mek: add usbotg1 and related nodes
4686539bb6a7 arm64: dts: imx8qm-mek: add pmic thermal-zones
d54d0eb6eb83 arm64: dts: imx8qm: add label thermal_zones
fe85e148d94c arm64: dts: imx8qm-mek: add lpuart1 and bluetooth node
48718befedf5 arm64: dts: imx8qm-mek: assign double SD bus frequency for usdhc1
23474fe74dfb arm64: dts: imx8qm-mek: add state_100mhz and state_200mhz for usdhc
299681fd1f8c ARM: dts: imx: e70k02: add sy7636
4a5c1fc96897 arm64: dts: freescale: imx93-phyboard-nash: Add pwm-fan overlay
82783b5af672 arm64: dts: freescale: imx93-phyboard-nash: Add jtag overlay
ba959ed037e6 arm64: dts: imx8mm-phyboard-polis-peb-av-10: Fix audio codec reset pin ctl
a1c7d8335111 arm64: dts: imx8mm-phyboard-polis-peb-av-10-ph128800t006
be8b70732148 arm64: dts: imx8mm-phyboard-polis-peb-av-10: split display configuration
d9d6c3efcbe8 arm64: dts: imx8mm-phyboard-polis-peb-av-10: reorder properties to match dts coding style
15c3079a99e2 arm64: dts: imx8mm-phyboard-polis: move mipi bridge to som
2d80f3d2c1f3 arm64: dts: imx8mm-phyboard-polis: Use GPL-2.0-or-later OR MIT
b508119789a6 arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support
b21957dbcdca dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board
a1341c3df941 ARM: dts: imx28-amarula-rmm: add I2S audio
15e0e51ee250 arm64: dts: imx8-apalis: use startup-delay-us for wifi regulator
6983f4327e80 arm64: dts: imx8-apalis: rename wifi regulator
a3ce44ee240a arm64: dts: imx8-apalis: specify adc reference voltage regulator
ad4be8fcb243 arm64: dts: imx8-apalis: add thermal nodes
c7bdf580a894 arm64: dts: imx8-apalis: cleanup todo
f1d75d7d918c arm64: dts: imx8mp-evk: enable hdmi_pai device
84504fc99061 arm64: dts: imx8mp: Add hdmi parallel audio interface node
784e90c877c9 arm64: dts: rockchip: add vicap node to rk356x
45ae000930c4 arm64: dts: rockchip: add the vip node to px30
9e325867cd98 arm64: dts: rockchip: fixes audio for 100ASK DshanPi A1
cbbc75134a48 arm64: dts: rockchip: fixes vcc3v3_s0 supply for 100ASK DshanPi A1
7c29d507dbbb dt-bindings: iio: accel: adxl380: add new supported parts
81827902832f dt-bindings: watchdog: airoha: Add support for Airoha AN7583 SoC
fc33de070173 dt-bindings: watchdog: lantiq,wdt: convert bindings to dtschema
c5a9b7111f76 dt-bindings: watchdog: Add RK3506 compatible
c290f5cf2179 dt-bindings: watchdog: Document Qualcomm Kaanapali watchdog
26cdede7a15d dt-bindings: watchdog: loongson,ls1x-wdt: Add ls2k0300-wdt compatible
b6f69b567679 dt-bindings: watchdog: Support MediaTek MT8189 wdt
a8de67951fb6 dt-bindings: watchdog: mediatek,mtk-wdt: Add compatible for MT8189 SoC
5c10980d1177 dt-bindings: mfd: rohm,bd96801-pmic: Correct timeout-sec length and reference watchdog schema
e5fba877f7e2 dt-bindings: watchdog: Allow node names named 'pmic'
738d8e109d64 dt-bindings: watchdog: Restrict timeout-sec to one number
961eff22aab4 dt-bindings: watchdog: Add Renesas WWDT
19fe640b8aca dt-bindings: watchdog: Convert marvell,orion-wdt to DT schema
76c438848672 dt-bindings: watchdog: Convert TI OMAP to DT schema
4b9bb7a46086 dt-bindings: watchdog: aspeed,ast2400-wdt: Add support for AST2700
e1fd070747fc dt-bindings: watchdog: renesas,wdt: add SWDT exception for V3H
4878af2d1ead dt-bindings: watchdog: factor out RZ/V2H(P) watchdog
4b185dc7e820 dt-bindings: watchdog: factor out RZ/G2L watchdog
14ff05a1690e dt-bindings: watchdog: factor out RZ/N1 watchdog
a2103c7687ee dt-bindings: watchdog: factor out RZ/A watchdog
5352fe610057 ARM: dts: microchip: sama5d2: fix spi flexcom fifo size to 32
07d29e30ad80 media: dt-bindings: add rockchip rk3568 vicap
d9444993395e media: dt-bindings: add rockchip px30 vip
565440f0cc45 media: dt-bindings: video-interfaces: add defines for sampling modes
6ba644a81955 arm64: tegra: Remove OTG ID GPIO from Jetson TX2 NX
758b19af7890 arm64: tegra: Set USB Micro-B port to OTG mode on P3450
33d56059e2c2 arm64: tegra: Add NVJPG node for Tegra210 platforms
43fbf4ea5469 arm64: tegra: Add Tegra210 NVJPG power-domain node
910f3b671adf arm64: tegra: Add interrupts for Tegra234 USB wake events
db68873794ec arm64: tegra: Add reserved-memory node for P2180
17aad4a020ce arm64: tegra: Add reserved-memory node for P3450
a8b24f03260e arm64: tegra: Enable NVDEC and NVENC on Tegra210
f632c44f37f2 arm64: tegra: Fix APB DMA controller node name
4917ceb42388 arm64: tegra: Add default GIC address cells on Tegra210
658bc32eb797 arm64: tegra: Add default GIC address cells on Tegra194
9d25ce66a15d arm64: tegra: Add default GIC address cells on Tegra186
a258475804cb arm64: tegra: Add default GIC address cells on Tegra132
228b5e06c593 arm64: tegra: Add OPP tables on Tegra210
5ea78e0e8671 arm64: tegra: Add interconnect properties for Tegra210
839310433a9f arm64: tegra: Add ACTMON on Tegra210
1838c2a08873 dt-bindings: display: rk3588-dw-hdmi-qp: Add frl-enable-gpios property
83157beae5b2 dt-bindings: usb: Add wake-up support for Tegra234 XUSB host controller
de6465d43bbb dt-bindings: devfreq: tegra30-actmon: Add Tegra124 fallback for Tegra210
4a4e9db281af ARM: tegra: Add device-tree for Xiaomi Mi Pad (A0101)
d470c42b37ef ASoC: codecs: lpass-macro: complete sm6115 support
48a4dab67b3a Add support for Microchip CoreSPI Controller
db813e1c4f96 arm64: tegra: Add device-tree node for NVVRS RTC
43646425739f arm64: dts: qcom: sdx75: Add missing usb-role-switch property
0046125aff8d arm64: dts: qcom: sdx75: Flatten usb controller node
8fb58f9720e1 arm64: tegra: Move avdd-dsi-csi-supply into CSI node
5646f369cabe arm64: tegra: Drop redundant clock and reset names from TSEC node
54138b2c8943 arm64: tegra: Move HDA into the correct bus
1aef80d04475 dt-bindings: display: msm: sm6150-mdss: Fix example indentation and OPP values
bfb09fe71b7c dt-bindings: display: msm: sm6150-mdss: Add DisplayPort controller
34f6333b5a63 dt-bindings: display/msm: dp-controller: Add SM6150
62f1ecd608b4 dt-bindings: display/msm: Document MDSS on QCS8300
f1c4a05f9337 dt-bindings: display/msm: dp-controller: document QCS8300 compatible
4295a206a7fc dt-bindings: display/msm: Document the DPU for QCS8300
4c1dfb6df3c4 dt-bindings: display: msm: Document the Glymur DiplayPort controller
7d8c41d1c23d dt-bindings: display: msm: Document the Glymur Display Processing Unit
ce766d6a6b54 dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem
f685ad520150 dt-bindings: display/msm: Reference DAI schema for DAI properties
6392d36aec9c dt-bindings: display: tegra: Document Tegra20 and Tegra30 CSI
0e16f393943f ARM: tegra: add CSI nodes for Tegra20 and Tegra30
727a974c10d1 arm64: dts: qcom: HAMOA-IOT-SOM: Unreserve GPIOs blocking SPI11 access
28d12ee2f8b4 arm64: dts: qcom: qrb2210-rb1: Fix UART3 wakeup IRQ storm
ddc23da76bf5 Revert "arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature"
e62101b57a70 dt-bindings: media: Add bindings for the RZ/V2H(P) IVC block
23664bb4e425 dt-bindings: media: Add bindings for ARM mali-c55
ce7ce0a595c8 spi-cadence: support transmission with
11743ce9a449 ARM: tegra: Add missing HOST1X device nodes on Tegra124
31c5e1d1feda ARM: tegra: Add missing HOST1X device nodes on Tegra114
9e3df043b918 dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+
9b8b66caebcf spi: dt-binding: document Microchip CoreSPI
45675908e58b dt-bindings: gnss: u-blox: add safeboot gpio
139f294b1b0d arm64: dts: socfpga: add Agilex3 board
2e90f2a4386d dt-bindings: intel: Add Agilex3 SoCFPGA board
d955a41e2561 ARM: dts: microchip: sama7g5: fix uart fifo size to 32
f224b1698a1e ARM: dts: microchip: sama7d65: fix uart fifo size to 32
b8f22628fe7a arm64: dts: st: set RIFSC as an access controller on stm32mp21x platforms
27a23e8ecdbe dt-bindings: bus: add stm32mp21 RIFSC compatible
52239210bb6c ARM: dts: stm32: add the IWDG2 interrupt line in stm32mp131.dtsi
ffcc0c6632b4 ARM: dts: stm32: enable the ARM SMC watchdog node in stm32mp135f-dk
11dfa739cbe3 ARM: dts: stm32: add the ARM SMC watchdog in stm32mp131.dtsi
0f78f2076b69 ARM: dts: stm32: add iwdg1 node in stm32mp131.dtsi
75a351ebe368 arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi
f62c09d7adef arm64: dts: st: Add memory-region-names property for stm32mp257f-ev1
b4d166d64dad dt-bindings: clock: airoha: Add reset support to EN7523 clock binding
06c7d9a3f07b Merge tag 'samsung-clk-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
bd904ecdbb4b arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1
e809fc72cff5 arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1
6e2bd24ddde7 arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boards
e1b4137b6bbc ARM: dts: rockchip: move edp assigned-clocks to edp node on rk3288
996efa4fc382 arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4
80449de0ed3d arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid Nova
19c0ede3d547 arm64: dts: rockchip: add eMMC CQE support for rk3588
c3f1daa78ec6 arm64: dts: rockchip: enable HDMI audio on Rock 5 ITX
d4428212ee8a arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3C
40612ce62a28 arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5A
7d9f2c89d37e arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5A
2b85b8aa6b7e arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356x
08c60813d54c arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 board
fe55570af4dc arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5T
f37dc939fe8c arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5C
169813078cc1 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
694cae13fd67 arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
51363c1aaf84 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC
530e23ad2bc3 arm64: dts: renesas: r9a09g057: Add RTC node
5872792a6798 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add NMI pushbutton support
35dfec24ab40 arm64: dts: renesas: rzg3s-smarc: Enable USB support
cc85f0202f38 arm64: dts: renesas: r9a08g045: Add USB support
eea5a7cc9f8f arm64: dts: renesas: r9a09g057: Add TSU nodes
223849acd4a6 Merge tag 'renesas-r9a09g057-dt-binding-defs-tag5' into renesas-clk-for-v6.19
bd95d5b58cb4 dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks
e20f945cfe6f dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks
eb1dacf061e4 dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC
c4d64b3f9ede ASoC: dt-bindings: qcom,lpass-va-macro: Add sm6115 LPASS VA
d8eb3c69bcc9 ASoC: dt-bindings: qcom,lpass-va-macro: re-arrange clock-names
0f66639319d2 ASoC: dt-bindings: qcom,lpass-rx-macro: Add sm6115 LPASS RX
3b04c96ccafd arm64: dts: ti: k3-am62l: add initial reference board file
b41c1c136ad0 arm64: dts: ti: k3-am62l: add initial infrastructure
6bac1dc26d74 dt-bindings: arm: ti: Add binding for AM62L SoCs
f8b7b7c8fa6e arm64: dts: ti: am69-aquila: Add Clover
cf5623cc6067 arm64: dts: ti: Add Aquila AM69 Support
35d9c13f543e dt-bindings: arm: ti: add Toradex Aquila AM69
f0aecc597d93 dt-bindings: mfd: twl: Enable power button also for TWL603X
c8a3fb4347ca dt-bindings: mfd: qcom-spmi-pmic: Document PM7550 PMIC
fa4b5be168e6 dt-bindings: leds: qcom,spmi-flash-led: Add PM7550
174774eb10d7 dt-bindings: mfd: qcom,spmi-pmic: Document PMIV0104
811dfe84d706 dt-bindings: interrupt-controller: Add support for Amlogic S6 S7 and S7D SoCs
3d8da57fa556 Merge tag 'linux-can-next-for-6.19-20251112-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
c96aebd9a91a dt-bindings: media: i2c: document Sony IMX111 CMOS sensor
999822b71aff dt-bindings: pwm: thead: Add T-HEAD TH1520 PWM controller
6c18ca8f0a37 dt-bindings: hwmon: ST TSC1641 power monitor
b13283f94d34 arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers
f2ee8bb754e3 dt-bindings: can: mcp251xfd: add gpio-controller property
370891f09140 riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
67c9af27639e riscv: dts: Add initial Anlogic DR1V90 SoC device tree
aeb594b5a685 dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
d66c2de98f4a dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
a65c72da603b dt-bindings: riscv: Add Anlogic DR1V90
6c4aa02a0280 dt-bindings: riscv: Add Nuclei UX900 compatibles
a3ce3aefa2de dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
880f989fec96 spi: dt-bindings: nuvoton,npcm-pspi: Convert to DT schema
5f77273b97ea phy: phy-can-transceiver: Support TJA1048/TJA1051
59aced147ba6 dt-bindings: phy: ti,tcan104x-can: Document NXP TJA105X/1048
959608f393bf riscv: dts: spacemit: define all missing I2C controller nodes
944c1e6cbe1d riscv: dts: spacemit: reorder i2c2 node
f3900bf8f07f ARM: dts: renesas: r9a06g032: Add the ADC device
8e79984a46dd riscv: dts: spacemit: Add OrangePi R2S board device tree
b714954b298f dt-bindings: riscv: spacemit: Add OrangePi R2S board
4c493939154f arm64: dts: renesas: r9a09g087: Add GMAC nodes
6a17bec91b25 arm64: dts: renesas: r9a09g077: Add GMAC nodes
451e0117a8d2 arm64: dts: renesas: r9a09g087: Add ETHSS node
e5b2d87b50af arm64: dts: renesas: r9a09g077: Add ETHSS node
eb0bca984e50 arm64: dts: imx95-19x19-evk: Add vpcie3v3aux regulator for PCIe[0,1]
c9d07235dae5 arm64: dts: imx95-15x15-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
dc40e5294a5c arm64: dts: imx8qxp-mek: Add vpcie3v3aux regulator for PCIe M.2 connector
e1c5860f6c42 arm64: dts: imx8qm-mek: Add vpcie3v3aux regulator for PCIe M.2 connector
94b0472e531c arm64: dts: imx8mq-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
791dc9b583e0 arm64: dts: imx8mp-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
fe87aa8cc341 arm64: dts: imx8dxl-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
0348c402ba40 arm64: dts: imx8qxp-mek: Add supports-clkreq property to PCIe M.2 port
545a5de75989 arm64: dts: imx8qm-mek: Add supports-clkreq property to PCIe M.2 port
965b60e9f697 arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 port
94294e87099e arm64: dts: imx8mp-evk: Add supports-clkreq property to PCIe M.2 port
a94ba71aedb0 arm64: dts: imx8mm-evk: Add supports-clkreq property to PCIe M.2 port
c6d7be76d975 arm64: dts: imx95-19x19-evk: Add supports-clkreq property to PCIe M.2 port
cd5ad40ee67c arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port
bc3af4662a76 dt-bindings: interrupt-controller: aspeed,ast2700: Correct #interrupt-cells and interrupts count
44eb72cb02c0 dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
e6774748b5c0 dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
165cd4cd02b1 dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
bfde832259a7 ARM: dts: ti/omap: fix incorrect compatible string in internal eeprom node
ffffcf0ae72f riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire
6f9bafdfa9aa dt-bindings: mmc: socionext,milbeaut-m10v-sdhci-3.0: convert to DT schema
ef9c91463d76 dt-bindings: mmc: ti,da830-mmc: convert to DT schema
65b41a687258 dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin EIC7700
33d80f762b2d dt-bindings: clock: document 8ULP's SIM LPAV
e4a974a978df arm64: dts: imx8mp-debix-model-a: Fix ethernet PHY address
1cc479b8181e Merge tag 'v6.18-rc5' into media-next
e0a3348a0175 powerpc: p2020: Rename wdt@ nodes to watchdog@
9bef9eca6b60 powerpc: 86xx: Rename wdt@ nodes to watchdog@
1b3e7e46421d powerpc: 83xx: Rename wdt@ nodes to watchdog@
cec853da4161 powerpc: 512x: Rename wdt@ node to watchdog@
fa6d3cd14145 ARM: dts: imx: add vdd-supply and vddio-supply for fsl,mpl3115
80df183c235d arm64: dts: imx8: add vdd-supply and vddio-supply for fsl,mpl3115
f156ed063f96 arm64: dts: imx8dxl-ss-conn: delete usb3_lpcg node
e5d5825c25e1 arm64: dts: imx8-ss-conn: add missed clock enet_2x_txclk for fec[1,2]
aacc170c975a arm64: dts: imx8-ss-conn: add fsl,tuning-step for usdhc1 and usdhc2
6b094d96a895 arm64: dts: imx8: add default clock rate for usdhc
cb9d655e4be2 arm64: dts: imx8dxl-evk: add state_100mhz and state_200mhz for usdhc
f0676e7d5c3d arm64: dts: imx8dxl-evk: add bt information for lpuart1
e61b7cd15fb0 arm64: dts: socfpga: Add Agilex5 SVC node with memory region
317194944561 dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
581d37a034b2 dt-bindings: pinctrl: mt7988: allow gpio-hogs
41d45921ba23 dt-bindings: pinctrl: Add rk3506 pinctrl support
4714e545f9b9 Merge tag 'samsung-pinctrl-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
c4891745f29b Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports"
c0945b130f16 arm64/arm: dts: marvell: Rename "nand-rb" pinctrl node names
c7b2578cb013 ASoC: dt-bindings: consolidate simple audio codec to trivial-codec.yaml
cf1766dd0091 dt-bindings: thermal: qcom-tsens: document the Kaanapali Temperature Sensor
63dfc996809c dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2H TSU
d908463ec841 dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2N SoC
ebc42f8f49e9 arm64: dts: renesas: r8a779a0: Add GE7800 GPU node
c550cc93ff01 Merge tag 'renesas-r8a779a0-dt-binding-defs-tag2' into renesas-dts-for-v6.19
74effb337835 dt-bindings: pinctrl: Convert sprd,sc9860-pinctrl to DT schema
07efc512740a arm64: dts: renesas: r8a77965: Add GE7800 GPU node
2f92e6db952b Merge tag 'renesas-r8a779a0-dt-binding-defs-tag2' into renesas-clk-for-v6.19
0341928249a6 dt-bindings: clock: r8a779a0: Add ZG core clock
91eb564e0cd9 ARM: dts: stm32: lxa: drop unnecessary vusb_d/a-supply
c0908822f49c ARM: dts: stm32: stm32mp157c-phycore: Fix STMPE811 touchscreen node properties
0f8b3a233d72 arm64: dts: imx8mp: Specify the number of channels for CSI-2 receivers
b15f424db152 dt-bindings: fpga: update link for Altera's and AMD partial recon
ca7576ae569b dt-bindings: PCI: amlogic: Fix the register name of the DBI region
a1d501cb37b5 dt-bindings: firmware: svc: Add IOMMU support for Agilex5
fb6214502871 dt-bindings: iio: dac: Document AD5446 and similar devices
ecc3b75bb3fc dt-bindings: iio: adc: Add the Renesas RZ/N1 ADC
caf6bea7606f dt-bindings: iio: adc: Add AST2700 ADC compatible strings
942d4eb683a0 dt-bindings: iio: imu: mpu6050: remove interrupts from required list
96a269a4da9e dt-bindings: iio: adc: Support MediaTek MT8189 evb board auxadc
ce984450345b dt-bindings: iio: pressure: Add Aosong adp810
e15db7905b3d dt-bindings: iio: adc: Add rockchip,rk3506-saradc variant
d6628be8e132 dt-bindings: iio: adc: adi,ad4080: add support for AD4087
af14401bb0fa dt-bindings: iio: adc: adi,ad4080: add support for AD4086
eb408941f8d5 dt-bindings: iio: adc: adi,ad4080: add support for AD4083
8b7a7c98fea1 dt-bindings: i3c: snps: Add Altera SoCFPGA compatible
b76955f2e397 scsi: dt-bindings: phy: mediatek,ufs-phy: Update maintainer information in mediatek,ufs-phy.yaml
a81c9cbe5061 riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3
5e6246581385 spi: enable the SpacemiT K1 SoC QSPI
f2ed1c157d00 arm64: dts: rockchip: Add devicetree for the 9Tripod X3568 v4
a1831f5c60bd dt-bindings: rtc: Document NVIDIA VRS RTC
7512740ecee8 dt-bindings: arm: rockchip: Add 9Tripod X3568 series
e94d6f97494e dt-bindings: vendor-prefixes: Add 9Tripod
94c2990b6e11 arm64: dts: rockchip: Fix USB Type-C host mode for Radxa ROCK 5B+/5T
092cae17b389 arm64: dts: rockchip: Fix DMA for Indiedroid Nova Bluetooth
5bea16ef2463 arm64: dts: rockchip: Enable HS400 for Indiedroid Nova
0ef462775df4 arm64: dts: rockchip: enable NPU on Indiedroid Nova
c3ec5509f06f arm64: dts: rockchip: Add device type for Indiedroid Nova.
d147583e2431 arm64: dts: rockchip: enable NPU on Gameforce Ace
c9b9272bfab1 dt-bindings: net: dsa: lantiq,gswip: add support for MaxLinear GSW1xx switches
8e6721303b1f dt-bindings: net: dsa: lantiq,gswip: add support for MII delay properties
7c96439c122d dt-bindings: net: dsa: lantiq,gswip: add MaxLinear RMII refclk output property
9a11311b761b dt-bindings: rtc: Add support for ATCRTC100 RTC
6a01c45fa68a arm64: dts: qcom: kodiak: add coresight nodes
e49c41af34af Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
ddc4b2e73f78 spi: dt-bindings: fsl-qspi: add optional resets
4b2bcb916547 spi: dt-bindings: fsl-qspi: support SpacemiT K1
f6bcbcc967b1 dt-bindings: mfd: tps65910: Make interrupt properties optional
7aa67f890143 dt-bindings: mfd: dlg,da9063: Allow wakeup-source property
dcc5a87c2079 dt-bindings: mfd: Add Renesas R2A11302FT PMIC
c04fc784a99a dt-bindings: max77705: Add interrupt-controller property
181094e7a45c dt-bindings: mfd: sy7636a: Add missing GPIO pins and supply
c35a8eb35d1d riscv: dts: spacemit: add MusePi Pro board device tree
f8d41eff86e9 dt-bindings: riscv: spacemit: add MusePi Pro board
a80170255b5f media: dt-bindings: Add qcom,msm8939-camss
7b13e9d1d247 dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
ef694ddae0fb media: dt-bindings: qcom,x1e80100-camss: Fix typo in CSIPHY supply description
91e41f80bef1 dt-bindings: arm: document the static TPDM compatible
ead95c786898 Add support MT6316/6363/MT6373 PMICs regulators
26712421177f ASoC: qcom: q6dsp: fixes and updates
3914f5a0b1b6 arm64: dts: cix: Add pinctrl nodes for sky1
17de2a68d255 arm64: dts: cix: add DT nodes for SPI
3027b0861700 arm64: dts: mediatek: mt7981b-openwrt-one: Enable software leds
0c56eaffd6ce arm64: dts: mediatek: mt7981b-openwrt-one: Enable SPI NOR
cb424b084de7 arm64: dts: mediatek: mt7988a-bpi-r4pro: Add mmc overlays
9ca5ff43e737 arm64: dts: mediatek: mt7988a-bpi-r4-pro: Add PCIe overlays
7db00d319f92 arm64: dts: mediatek: mt7988: Add devicetree for BananaPi R4 Pro
acce3c7adc50 arm64: dts: mediatek: mt7988: Disable 2.5G phy and enable at board layer
ee4e3402c515 dt-bindings: crypto: qcom-qce: Document the kaanapli crypto engine
e0aa31703e8d dt-bindings: crypto: qcom,prng: Document kaanapali RNG
ab943f64fd0b arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files
b1a75e84b57e arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable it in board file
435113195e7c arm64: dts: ti: k3-j7200: disable "mcu_cpsw" in SoC file and enable in board file
7e621a93fb16 arm64: dts: ti: k3-am65: disable "mcu_cpsw" in SoC file and enable in board file
4403e5ae4405 arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file
645d8be2c730 arm64: dts: ti: k3-am62p5-sk: Set wakeup-source system-states
72c2be9c4207 arm64: dts: ti: k3-am62a7-sk: Set wakeup-source system-states
6d260cb30ad5 arm64: dts: ti: k3-am62-lp-sk: Set wakeup-source system-states
175de68e5f12 arm64: dts: ti: k3-am62p: Define possible system states
ed2894580c83 arm64: dts: ti: k3-am62a: Define possible system states
38d04be7cefa arm64: dts: ti: k3-am62: Define possible system states
d80b6bfa999f arm64: dts: ti: k3-am62p-j722s-common-main: move audio_refclk here
2dbdc38e696d arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports
83b392d1e5c6 arm64: dts: ti: k3-am642-tqma64xxl: add boot phase tags
08a4b299a12c dt-bindings: ethernet: eswin: fix yaml schema issues
927616100ca4 ARM: dts: omap: am335x-mba335x: Fix stray '/*' in comment
0c0014560c5f ARM: dts: omap: am335x-tqma335x/mba335x: Fix MicIn routing
5c681a9e3adf arm64: dts: rockchip: add missing clocks for cpu cores on rk356x
97dcca9fe134 arm64: dts: rockchip: use SCMI clock id for cpu clock on rk356x
59fde8ef5698 Merge branch 'v6.19-shared/clkids' into v6.19-armsoc/dts64
17f66773d6d8 dt-bindings: clock: rk3568: Drop CLK_NR_CLKS define
f84e07c41639 dt-bindings: clock: rk3568: Add SCMI clock ids
500efad7da39 arm64: tegra: Add pinctrl definitions for pcie-ep nodes
a134f00e3044 dt-bindings: regulator: Document MediaTek MT6363 PMIC Regulators
7ff2b92c949f dt-bindings: regulator: Document MediaTek MT6316 PMIC Regulators
f96d8ae74c7a dt-bindings: arm: mediatek: add BPI-R4 Pro board
d4ec127b408b dt-bindings: soc: bcm: Add bcm2712 compatible
738fc3f3c8ac ASoC: dt-bindings: ti,pcm1862: convert to dtschema
ec656263dbe3 spi: tegra210-quad: Improve timeout handling under
4349e09d15eb dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car M3-N
dbd373fd3caa dt-bindings: gpu: img,powervr-rogue: Keep lists sorted alphabetically
c5a04455a88a arm64: dts: mediatek: Add GCE header for MT8196
cc7dcad983ca arm64: dts: mediatek: mt7981b: Add reserved memory for TF-A
9a91e9c56c45 arm64: dts: mediatek: mt7981b: Configure UART0 pinmux
c4694545a423 arm64: dts: exynos7870-j6lte: enable display panel support
1631cd902a2a arm64: dts: exynos7870-a2corelte: enable display panel support
6fc9ade933a7 arm64: dts: exynos7870-on7xelte: enable display panel support
f01008a3e9a9 arm64: dts: exynos7870: add DSI support
8fba0c0b6330 dt-bindings: soc: samsung: exynos-pmu: allow mipi-phy subnode for Exynos7870 PMU
0b212c0b95b9 dt-bindings: net: ethernet-phy: clarify when compatible must specify PHY ID
f6e735d87138 dt-bindings: mmc: ti,omap2430-sdhci: convert to DT schema
9e99089ec779 arm: dts: ti: omap: Drop unnecessary properties for SDHCI node
d3b82351d536 arm: dts: ti: omap: am335x-pepper: Fix vmmc-supply property typo
34477bd6e9f1 ARM: dts: omap3: n900: Correct obsolete TWL4030 power compatible
942392136792 ARM: dts: omap3: beagle-xm: Correct obsolete TWL4030 power compatible
07593f812d8c ARM: dts: omap: Add support for TQMa335x/MBa335x
78b7c57a8fc3 ARM: dts: omap: AM33xx: add cpu label
e93a592c5d05 dt-bindings: omap: add AM335x-based TQMa335x SOM and MBa335x board
6784d030d57f ARM: dts: am335x-netcom-plus-2xx: add missing GPIO labels
749693aac072 ARM: dts: ti: omap: am335x-baltos: add a regulator for the mPCIe slot
c0b1648ea64b ARM: dts: omap: rework Baltos LED nodes
fc35df111354 ARM: dts: am33xx: Add missing serial console speed
f7a3b0a77529 arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
12b8a2c4b8d3 arm64: dts: socfpga: agilex5: Add L2 and L3 cache
62aed6e4308f arm64: dts: socfpga: agilex5: fix CHECK_DTBS warning for NAND
dbfe4282d641 ASoC: dt-bindings: ti,tas2781: Add TAS5822 support
a190c674be61 regulator: pf9453: optimize PMIC PF9453 driver
f0cdbc07561c dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC
873f8b175a7f Merge branch '20251030-gcc_kaanapali-v2-v2-3-a774a587af6f@oss.qualcomm.com' into clk-for-6.19
f2336647c42a dt-bindings: clock: qcom: Add Kaanapali Global clock controller
178ac5fbcdba dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller
a155addec4bc dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali
ab93399047d9 arm64: dts: qcom: sdm845-oneplus: Describe TE gpio
ab0a6e8d81c7 arm64: dts: qcom: sdm845-oneplus: Implement panel sleep pinctrl
23b58cd515a4 arm64: dts: qcom: sdm845-oneplus: Group panel pinctrl
34ddf2b19089 arm64: dts: qcom: sdm845-oneplus: Update compatbible and add DDIC supplies
dab1c0feb8a2 dt-bindings: arm: qcom,ids: Add SoC ID for QCS6490
8b38fbfc2927 arm64: dts: qcom: qcs6490-rb3gen2: Rename vph-pwr regulator node
c87be9cd7a34 dt-bindings: arm-smmu: Add compatible for Kaanapali and Glymur SoCs
ea56d5995a46 dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant
9ff301276c96 arm64: dts: imx95: Describe Mali G310 GPU
332be95c7f79 dt-bindings: gpu: mali-valhall-csf: Document i.MX95 support
d5bfeb3442e5 media: dt-bindings: nxp,imx8-isi: Add i.MX91 ISI compatible string
7e7a5bfdc7fa arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to "pcie1_ctrl"
f8bb8fd07d23 arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to SERDES0
55c5638e4aef arm64: dts: ti: k3-j784s4-evm-pcie0-pcie1-ep: Add boot phase tag to "pcie1_ep"
41b4706fac88 media: dt-bindings: rockchip,vdec: Add RK3288 compatible
f178906c7fd7 scsi: ufs: dt-bindings: mediatek,ufs: Update maintainer information in mediatek,ufs.yaml
e87084d1b8ac dt-bindings: power: supply: Add Richtek RT9756 smart cap divider charger
2e0a34e4debd ARM: dts: qcom: msm8226-samsung-ms013g: add simple-framebuffer
3ee9215add65 arm64: dts: qcom: qcm6490-fairphone-fp5: Add UW cam actuator
8422138d3d7b arm64: dts: qcom: qcm6490-fairphone-fp5: Enable CCI pull-up
289ebfdb6142 ARM: dts: qcom: msm8960: rename msmgpio node to tlmm
b37af7d09a41 ARM: dts: qcom: msm8960: add I2C nodes for gsbi1 and gsbi8
b79770f72de5 ARM: dts: qcom: msm8960: add I2C nodes for gsbi10 and gsbi12
fdd6c13fa1ee ARM: dts: qcom: msm8960: inline qcom-msm8960-pins.dtsi
dcc2bc922e6d ARM: dts: qcom: msm8960: reorder nodes and properties
177c437ec5c8 arm64: dts: qcom: sm8750: Add USB support for SM8750 QRD platform
886f067dc029 arm64: dts: qcom: sm8750: Add USB support for SM8750 MTP platform
909978e5540e arm64: dts: qcom: sm8750: Add USB support to SM8750 SoCs
d05857b95bcf dt-bindings: clk: microchip: mpfs: remove first reg region
e71b1c73e548 riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
236ce5a49538 riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
7eb230c2706e riscv: sophgo: dts: enable PCIe for PioneerBox
0537c1f46d01 riscv: sophgo: dts: add PCIe controllers for SG2042
05eca33887cb dt-bindings: pse-pd: ti,tps23881: Add TPS23881B
38e6f7cd300f ARM: dts: rockchip: Add spi_flash label to rk3288-veyron
faefae4ca217 ARM: dts: rockchip: Remove mshc aliases from RK3288
e197e2ac01bb ARM: dts: rockchip: Adapt tps65910 nodes on RK3066 boards
367b203fafa6 arm64: dts: socfpga: agilex5: add support for 013b board
397229f88b25 dt-bindings: intel: Add Agilex5 SoCFPGA 013b board
836b8fdc8a21 dt-bindings: gpu: img,powervr-rogue: Drop duplicate newline
9cec920289e7 dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Kaanapali SoC
14ee982b55ba Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
6a4ad565c309 dt-bindings: display: panel: Add Tianma TL121BVMS07-00 panel
a30f08bec64b riscv: dts: thead: Add reset controllers of more subsystems for TH1520
18c89b99d621 dt-bindings: crypto: amd,ccp-seattle-v1a: Allow 'iommus' property
d007a0a12f1f arm64: dts: renesas: sparrow-hawk: Fix full-size DP connector node name and labels
25aa9fcceebd Merge branch 'icc-sa8775p' into icc-next
7dfae837db8f Merge branch 'icc-sdx75' into icc-next
87b4f902050f dt-bindings: interconnect: qcom: Drop QPIC_CORE IDs
61ffca74972e dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p
ca628f2d40b0 arm64: dts: qcom: msm8996: add interconnect paths to USB2 controller
adc58b68bbfd arm64: dts: socfpga: agilex5: add VGIC maintenance interrupt
f6d4eb2e9948 arm64: dts: socfpga: agilex: fix dtbs_check warning for NAND
ebebf24e00f9 arm64: dts: socfpga: agilex: fix dtbs_check warning for clock manager
8631a889da8a arm64: dts: socfpga: stratix10-swvp: fix dtbs_check warnings swvp
2daef772ee87 arm64: tegra: Add NVIDIA Jetson Nano 2GB Developer Kit support
0f4c9afaa1e6 arm64: tegra: Add Tegra264 audio support
4621fef13302 arm64: tegra: Add Tegra186 pin controllers
5a653790513c Merge branch 'for-6.19/dt-bindings' into for-6.19/arm64/dt
ea573761ab27 dt-bindings: arm: tegra: Document Jetson Nano Devkits
21aa9acf8fd6 arm64: dts: qcom: rename x1p42100 to purwa
9c124deb1706 arm64: dts: qcom: rename sc7280 to kodiak
34f4141267d9 arm64: dts: qcom: rename qcm2290 to agatti
61c3825e7b71 Merge branch 'arm64-fixes-for-6.18' into HEAD
c9b470c0f0aa arm64: dts: qcom: add gpu_zap_shader label
5419d052f8ca arm64: dts: qcom: sc7180: add gpu_zap_shader label
c821ea8a1fc1 arm64: dts: qcom: sm8250: drop duplicate memory-region defs
9ebd306dc980 arm64: dts: qcom: sc8280xp: create common zap-shader node
bad596928bdd arm64: dts: qcom: sc8180x: create common zap-shader node
063aaf9d0ba1 arm64: dts: qcom: sdm845: create common zap-shader node
bfc31cf752e3 arm64: dts: qcom: sdm670: create common zap-shader node
cf2a2074d1f7 arm64: dts: ti: k3-am62d2-evm: Remove unused ospi0 chip select pins
1c3cef64cdf1 arm64: dts: ti: k3-j784s4: Fix I2C pinmux pull configuration
a24ba1ad5b77 arm64: dts: ti: k3-am68-phycore-som: Add pmic label
9b486b4b44c1 arm64: dts: ti: k3-am642-evm: Add DMA support for TSCADC
8fc50ca84b12 arm64: dts: ti: var-som-am62p: Add support for ADS7846 touchscreen
d4d79e58e61e arm64: dts: ti: var-som-am62p: Add support for WM8904 audio codec
77b7ed6c043d arm64: dts: ti: var-som-am62p: Refactor IPC configuration into common dtsi
578eb2e30594 arm64: dts: ti: k3-am62d2-evm: Enable PMIC
f2475f7b2859 arm64: dts: ti: k3-am62d2-evm: Fix PMIC padconfig
05b8a606c27b arm64: dts: ti: k3-am62d2-evm: Fix regulator properties
81c8f1a1a794 arm64: dts: ti: sa67: add overlay for the ADS2 carrier
f9f296f96ac6 arm64: dts: ti: Add support for Kontron SMARC-sAM67
2f2457c617e9 dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module
920570c4c314 arm64: dts: ti: k3-j722s-main: fix the audio refclk source
dde857544006 arm64: dts: ti: k3-j722s-evm: explicitly use PLL1_HSDIV6 audio refclk
5857f9c2eaa9 dt-bindings: i2c: qcom-cci: Document Kaanapali compatible
984d12bdd1c5 dt-bindings: i2c: qcom-cci: Document msm8953 compatible
5abea6a92807 ARM: dts: sti: remove useless cells fields
8fa60eeee56d ARM: dts: sti: extract display subsystem out of soc
e1fa0f943b27 dt-bindings: soc: mediatek: pwrap: Add compatible for MT8189 SoC
a83061721009 scsi: ufs: dt-bindings: qcom: Drop redundant "reg" constraints
a25de645f4a6 Merge patch series "ufs: Add support for AMD Versal Gen2 UFS"
8ed788fef493 scsi: ufs: dt-bindings: amd-versal2: Add UFS Host Controller for AMD Versal Gen 2 SoC
c0141392dbec dt-bindings: net: enetc: add compatible string for ENETC with pseduo MAC
edf9348fb52f dt-bindings: net: netc-blk-ctrl: add compatible string for i.MX94 platforms
1a01e2ae483e dt-bindings: display: panel: document Synaptics TDDI panel
e26b0907e225 dt-bindings: display: bridge: renesas,dsi-csi2-tx: Align panel example with ili9881c binding
388395195887 dt-bindings: display: panel: samsung,atna33xc20: Document ATNA60CL08
a3ae79d93700 dt-bindings: panel: Add Samsung S6E3FC2X01 DDIC with panel
a99f938f5aa5 ASoC: dt-bindings: cirrus,cs4271: Document mclk clock
d01c58aafc2f arm64: dts: qcom: Add display support for QCS615 RIDE board
39d0f55a7a15 arm64: dts: qcom: Add display support for QCS615
efa5b9f2bc1d arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default
7f1f96dffacd arm64: dts: qcom: qcs615-ride: Update 'model' string for qcs615 ride
00eefa218713 dt-bindings: soc: qcom,aoss-qmp: Document the Glymur AOSS side channel
49d55ebca38e dt-bindings: soc: qcom,aoss-qmp: Document the Kaanapali AOSS channel
41e853fcc233 media: dt-bindings: vd55g1: Add vd65g4 compatible
e3a1f4e91b52 media: dt-bindings: video-interfaces: add video-interfaces.h information
6f18a887c3ba dt-bindings: media: convert nxp,tda1997x.txt to yaml format
1bb72b82d0cb dt-bindings: media: Convert ti,tvp5150.txt to yaml format.
c32a348b4e89 dt-bindings: media: i2c: dw9719: Document DW9800K
16bc12b73ca9 dt-bindings: media: i2c: Add DW9718S, DW9719 and DW9761 VCM
a245812e8691 dt-bindings: eeprom: at24: Add compatible for Belling BL24S64
73aa608e5cdd arm64: dts: ti: k3-am62: Add RNG node
3af25a3096ce arm64: dts: qcom: ipq5424: Add NSS clock controller node
6b3564ee6089 Merge branch '20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com' into HEAD
4a20798bd143 arm64: dts: allwinner: a523: Add SPDIF TX pin on PB and PI pins
f08405274eb4 arm64: dts: allwinner: a523: Add I2S2 pins on PI pin group
eb693907e112 arm64: dts: allwinner: a523: Add device nodes for I2S controllers
9fb90441e76e arm64: dts: allwinner: a523: Add device node for SPDIF block
629b2d2ecaf9 arm64: dts: allwinner: a523: Add DMA controller device nodes
86e58381d607 dt-bindings: dma: allwinner,sun50i-a64-dma: Add compatibles for A523
c512574ca614 arm64: dts: allwinner: h616: add NAND controller
77523862c4c5 dt-bindings: mtd: sunxi: Add H616 compatible
324d8c8e85d5 dt-bindings: mtd: physmap: add 'clocks' and 'power-domains'
564e76e7bc36 dt-bindings: usb: qcom,snps-dwc3: Add Glymur compatible
cd3e933059f3 Add support for Cirrus Logic CS530x DAC and CODEC
3df1f2221f07 allwinner: a523: Enable I2S and SPDIF TX
a5377911b626 Sndcard compatible for qrb2210/qcm2290
77e5482e2dd7 ALSA: cs35l56: Add support for factory calibration
6f315594e8b8 dt-bindings: serial: snps-dw-apb-uart: Add support for rk3506
f236f03d3035 dt-bindings: net: cdns,macb: add Mobileye EyeQ5 ethernet interface
9c23d9831da2 regulator: pca9450: add input supply links
1750f654206b dt-bindings: pinctrl: stm32: Support I/O synchronization parameters
69c3999354e0 dt-bindings: pinctrl: stm32: Use properties from pincfg-node.yaml
82ffff1efbbd dt-bindings: pincfg-node: Add properties 'skew-delay-{in,out}put-ps'
3ab76ecf5d1d riscv: dts: thead: Add PWM fan and thermal control
92326f084155 riscv: dts: thead: Add PWM controller node
f93c62890c2f arm64: dts: layerscape: add dma-coherent for usb node
5d64b5538e7a arm64: dts: renesas: r8a77961: Add GX6250 GPU node
40c1f83b79c8 arm64: dts: renesas: r8a77960: Add GX6250 GPU node
2a38b90ab47d ARM: dts: renesas: kzm9g: Name interrupts for accelerometer
3600f22b4dce arm64: dts: renesas: r9a09g087: Add Cortex-A55 PMU node
4b70c7338153 arm64: dts: renesas: r9a09g077: Add Cortex-A55 PMU node
3eab62e16cf4 arm64: dts: renesas: r9a09g056: Add Cortex-A55 PMU node
d0735048dea8 arm64: dts: renesas: r9a09g057: Add Cortex-A55 PMU node
fce29fd9a4ce ARM: dts: renesas: r9a06g032-rzn1d400-db: Drop invalid #cells properties
bd7825128485 arm64: dts: renesas: v3msk: Enable watchdog timer
8d6bae4f60f4 arm64: dts: renesas: r8a779h0: Add SWDT node
7484014c3c4c arm64: dts: renesas: r8a779g0: Add SWDT node
4b23d2623005 arm64: dts: renesas: r8a779f0: Add SWDT node
5f594d110e49 arm64: dts: renesas: r8a779a0: Add SWDT node
e1b992a8f519 arm64: dts: renesas: rzt2h/rzn2h-evk: Enable ADCs
f3de712c04d1 arm64: dts: renesas: r9a09g087: Add ADCs support
5131a6b6c5c7 arm64: dts: renesas: r9a09g077: Add ADCs support
5a2064c8ab3a ARM: dts: renesas: koelsch: Update ADV7180 binding
e75c78162e9f ARM: dts: renesas: r9a06g032: Move interrupt-parent to root node
e51d601a098a ARM: dts: renesas: r8a7794: Move interrupt-parent to root node
7cf03360c5b2 ARM: dts: renesas: r8a7793: Move interrupt-parent to root node
778194b83c15 ARM: dts: renesas: r8a7792: Move interrupt-parent to root node
4480cc808c88 ARM: dts: renesas: r8a7791: Move interrupt-parent to root node
f64ab8fae780 ARM: dts: renesas: r8a7790: Move interrupt-parent to root node
1d0ee5b34647 ARM: dts: renesas: r8a77470: Move interrupt-parent to root node
86dc112b20af ARM: dts: renesas: r8a7745: Move interrupt-parent to root node
3633ac3370a1 ARM: dts: renesas: r8a7744: Move interrupt-parent to root node
f18600a1c85f ARM: dts: renesas: r8a7743: Move interrupt-parent to root node
ef1cc272bcf3 ARM: dts: renesas: r8a7742: Move interrupt-parent to root node
f14a0e86b59b ARM: dts: renesas: r7s9210: Remove duplicate interrupt-parent
1e6ac2e6c088 ARM: dts: renesas: r7s72100: Move interrupt-parent to root node
2675e3c01c37 ARM: dts: renesas: gose: Remove superfluous port property
1a26b3bfea7c arm64: dts: renesas: eagle/v3msk: Mark SWDT as reserved
bf7e47f24b8e arm64: dts: renesas: ebisu: Mark SWDT as reserved
0b3d6a57b158 arm64: dts: renesas: draak: Mark SWDT as reserved
6fb2f2c3313a arm64: dts: renesas: ulcb: Mark SWDT as reserved
6918022f6f3c arm64: dts: renesas: salvator-common: Mark SWDT as reserved
f5cd87fe3ecc arm64: dts: renesas: r8a77995: Add SWDT node
262967098387 arm64: dts: renesas: r8a77990: Add SWDT node
6fbb54700b9d arm64: dts: renesas: r8a77970: Add SWDT node
48ecc636433e arm64: dts: renesas: r8a77965: Add SWDT node
1e7c5169d327 arm64: dts: renesas: r8a77961: Add SWDT node
3707f6099025 arm64: dts: renesas: r8a77960: Add SWDT node
b362a6bee083 arm64: dts: renesas: r8a77951: Add SWDT node
9ded9a2cbc9c arm64: dts: renesas: r9a09g087: Move interrupt-parent to root node
f9cfb3e3bc73 arm64: dts: renesas: r9a09g077: Move interrupt-parent to root node
d9c57630c6aa arm64: dts: renesas: r9a09g057: Move interrupt-parent to root node
fb1eaac90154 arm64: dts: renesas: r9a09g056: Move interrupt-parent to root node
a747b04edcd9 arm64: dts: renesas: r9a09g047: Move interrupt-parent to root node
6fa015d9c3f2 arm64: dts: renesas: r9a09g011: Move interrupt-parent to root node
86b4aff5751e arm64: dts: renesas: r9a08g045: Move interrupt-parent to root node
556f38414a3b arm64: dts: renesas: r9a07g054: Move interrupt-parent to root node
639171af00d0 arm64: dts: renesas: r9a07g044: Move interrupt-parent to root node
858f8626358b arm64: dts: renesas: r9a07g043u: Move interrupt-parent to root node
f774aa1d08e2 arm64: dts: renesas: r8a779h0: Move interrupt-parent to root node
1ea98c466faf arm64: dts: renesas: r8a779g0: Move interrupt-parent to root node
ff2e3e4aaa25 arm64: dts: renesas: r8a779f0: Move interrupt-parent to root node
410f62158740 arm64: dts: renesas: r8a779a0: Move interrupt-parent to root node
85635a7585eb arm64: dts: renesas: r8a77995: Move interrupt-parent to root node
ec38de19029b arm64: dts: renesas: r8a77990: Move interrupt-parent to root node
22c9131d5d5b arm64: dts: renesas: r8a77980: Move interrupt-parent to root node
fce325d2e138 arm64: dts: renesas: r8a77970: Move interrupt-parent to root node
17445f73c0d8 arm64: dts: renesas: r8a77965: Move interrupt-parent to root node
8619b9b0a4fa arm64: dts: renesas: r8a77961: Move interrupt-parent to root node
f8e6053c4851 arm64: dts: renesas: r8a77960: Move interrupt-parent to root node
c2edd1209006 arm64: dts: renesas: r8a77951: Move interrupt-parent to root node
0351e614dd34 arm64: dts: renesas: r8a774e1: Move interrupt-parent to root node
8e73e259fa80 arm64: dts: renesas: r8a774c0: Move interrupt-parent to root node
04abba2eacb9 arm64: dts: renesas: r8a774b1: Move interrupt-parent to root node
6f4c8b1124d7 arm64: dts: renesas: r8a774a1: Move interrupt-parent to root node
8196cc3a589a arm64: dts: renesas: r8a78000: Add initial Ironhide board support
ad2815fdc4ea arm64: dts: renesas: Add R8A78000 SoC support
a5c4ba64ebd6 arm64: dts: qcom: x1e80100-crd: Add charge limit nvmem
7f1da07b52e2 arm64: dts: qcom: qcm2290: Fix camss register prop ordering
f3ff1b8f8aa9 dt-bindings: firmware: qcom,scm: Document Glymur scm
26fba680b4f4 arm64: dts: qcom: qcs615-ride: Set drive strength for wlan-en-state pin
e8b5084bb178 arm64: dts: qcom: sc8280xp-x13s: enable camera privacy indicator
b338fff9357f dt-bindings: net: phy: vsc8531: Convert to DT schema
8a739271313b dt-bindings: pinctrl: Add cix,sky1-pinctrl
ce953a44dcd9 arm64: dts: qcom: ipq5424: add cooling maps for CPU thermal zones
553396e497bf arm64: dts: qcom: sm6350: Add interconnect support to UFS
a17d0bf21c18 arm64: dts: qcom: sm6350: Add OPP table support to UFSHC
06f96f6e3f2b arm64: dts: qcom: sm6350: Fix wrong order of freq-table-hz for UFS
61c6439b6bc1 dt-bindings: arm: qcom,ids: Add SoC ID for SM8850
d9f147419b5b arm64: dts: qcom: qrb2210-rb1: add HDMI/I2S audio playback support
2af5e843fe07 arm64: dts: qcom: qcm2290: add LPASS LPI pin controller
dab83d4b818a arm64: dts: qcom: qcm2290: add APR and its services
846ffd24b0ae arm64: dts: qcom: sdm845-shift-axolotl: fix touchscreen properties
a66d0dcb8a9a ASoC: dt-bindings: allwinner,sun4i-a10-spdif: Add compatible for A523
cb615a5e9bb2 ASoC: dt-bindings: allwinner,sun4i-a10-i2s: Add compatible for A523
b72c88370dcb arm64: dts: qcom: sdm845: Define guard pages within the rmtfs region
0eb7d62ca4ba arm64: dts: qcom: sdm845-shift-axolotl: Drop address and size cells from panel
0f6c690a07a4 arm64: dts: qcom: sdx75: Fix the USB interrupt entry order
1e17e46c1744 arm64: dts: qcom: lemans: Align ethernet interconnect-names with schema
bce459232f9e arm64: dts: qcom: lemans-evk: Enable AMC6821 fan controller
1c37e39d87df arm64: dts: qcom: lemans-pmics: enable rtc
002acc3e151c arm64: dts: qcom: sm8250-samsung-common: correct reserved pins
38885ff0ca7d arm64: dts: qcom: sdm845-starqltechn: Fix i2c-gpio node name
8f9599036bc8 arm64: dts: qcom: lemans-evk: Add resin key code for PMM8654AU
ce7c41efa420 arm64: dts: qcom: Add Xiaomi Redmi 3S
77fc01dd97a0 dt-bindings: arm: qcom: Add Xiaomi Redmi 3S
73bef8d84a3e arm64: dts: qcom: Add initial support for MSM8937
c636626d1f66 arm64: dts: qcom: sm8550-hdk: Add SM8550-HDK Rear Camera Card overlay
134c3bf3beee arm64: dts: qcom: sm8550-qrd: Enable CAMSS and S5K3M5 camera sensor
aeb7314b94a4 arm64: dts: qcom: sm8550: Add description of MCLK pins
9d2a45d9c3d0 arm64: dts: qcom: sc8280xp: Fix shifted GPI DMA channels
5cf059e61901 arm64: dts: qcom: x1e80100: Add opp-level to indicate PCIe data rates
6b1c470fa75f arm64: dts: qcom: sm8650: Add opp-level to indicate PCIe data rates
33e269bcdd48 arm64: dts: qcom: sm8550: Add opp-level to indicate PCIe data rates
ffc37943915f arm64: dts: qcom: sm8450: Add opp-level to indicate PCIe data rates
09f65a74159b arm64: dts: qcom: x1-dell-thena: remove dp data-lanes
a190145862c7 arm64: dts: qcom: x1-dell-thena: Add missing pinctrl for eDP HPD
1cb903bedab5 arm64: dts: qcom: x1e80100: Move CPU idle states to their respective PSCI PDs
9eb67c3942f1 arm64: dts: qcom: hamoa-iot-evk: Fix 4-speaker playback support
40c06e2b653c arm64: dts: qcom: x1e80100: Describe the full 'link' region of DP hosts
e23c6d3824ce arm64: dts: qcom: qcm2290: Add uart1 and uart5 nodes
874df1b982c6 arm64: dts: qcom: qcm2290: Fix uart3 QUP interconnect
7e39134d5c72 arm64: dts: qcom: qcm6490-shift-otter: Enable venus node
270a5cdf60f0 arm64: dts: qcom: qcm6490-shift-otter: Enable RGB LED
d02db545eae6 arm64: dts: qcom: qcm6490-shift-otter: Enable flash LED
8f65c9da4d18 arm64: dts: qcom: qcm6490-shift-otter: Add missing reserved-memory
d775d76c6f97 arm64: dts: qcom: qcm6490-shift-otter: Remove thermal zone polling delays
aa94b43260b9 arm64: dts: qcom: qcm6490-shift-otter: Fix sorting and indentation
f8e32d2c41f8 arm64: dts: qcom: msm8939-asus-z00t: add initial device tree
13ad390ba838 dt-bindings: arm: qcom: Add Asus ZenFone 2 Laser/Selfie
0188f96058a8 arm64: dts: qcom: Add support for Huawei MateBook E 2019
539d085102fb dt-bindings: arm: qcom: Document Huawei MateBook E 2019
d88c8861d076 arm64: dts: qcom: sm8750-mtp: move PCIe GPIOs to pcieport0 node
69e68f3eedf1 arm64: dts: qcom: sm8650: set ufs as dma coherent
f5e38a286701 arm64: dts: qcom: sm7325-nothing-spacewar: Use correct compatible for audiocc
df3c03535652 arm64: dts: qcom: qcm6490-shift-otter: Use correct compatible for audiocc
95f0b38e6e19 arm64: dts: qcom: qcm6490-fairphone-fp5: Use correct compatible for audiocc
9320ad1b0b6a arm64: dts: qcom: qcm6490-fairphone-fp5: Add VTOF_LDO_2P8 regulator
a90d8864afc4 arm64: dts: qcom: qcm6490-fairphone-fp5: Add supplies to simple-fb node
8a37222312e9 arm64: dts: qcom: sm8250: Add MDSS_CORE reset to mdss
a0bceae1a0ff arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A
c0fed9e3cf30 dt-bindings: arm: qcom: Add Radxa Dragon Q6A
1685c95f0af9 arm64: dts: qcom: x1e80100-asus-zenbook-a14: Enable WiFi, Bluetooth
e91acc9ac35f arm64: dts: qcom: Rework X1-based Asus Zenbook A14's displays
3ce765c2fd6e dt-bindings: arm: qcom: Add Asus Zenbook A14 UX3407QA LCD/OLED variants
050044532eec arm64: dts: qcom: sdm845-oneplus: Correct gpio used for slider
207a134b4b6b arm64: dts: qcom: sdm845-starqltechn: fix max77705 interrupts
f3c6cd937568 arm64: dts: qcom: sdm845-starqltechn: remove (address|size)-cells
3e6a898ef6dc arm64: dts: qcom: qcm6490-fairphone-fp5: Add vibrator support
8310fbfb41f2 arm64: dts: qcom: monaco-evk: Add firmware-name to QUPv3 nodes
1d10c0210fc4 arm64: dts: qcom: lemans-evk: Add firmware-name to QUPv3 nodes
1ee7ca058242 arm64: dts: qcom: qcs6490-rb3gen2: Add firmware-name to QUPv3 nodes
4454c4ce0ec0 arm64: dts: qcom: msm8916-longcheer-l8910: Add touchscreen
274cf9dcd23e arm64: dts: qcom: qcs6490-rb3gen2: Update regulator settings
9b944759802c arm64: dts: qcom: sm6350: Add MDSS_CORE reset to mdss
e5898f14d13f arm64: dts: qcom: qcs8300-pmics: Remove 'allow-set-time' property
bcd976a0fccb arm64: dts: qcom: rename sm6150 to talos
11ba2e023ba2 arm64: dts: qcom: rename x1e80100 to hamoa
ba699b542674 arm64: dts: qcom: rename qcs8300 to monaco
3b4a09175eca arm64: dts: qcom: sm6375: add refgen regulator
4001d8c67d97 arm64: dts: qcom: sc8280xp: add refgen regulator
c4be6e56fd0c arm64: dts: qcom: qcs8300: add refgen regulator
f6836d933888 arm64: dts: qcom: sm8250: add refgen regulator and use it for DSI
28d8edc9a748 arm64: dts: qcom: sm8150: add refgen regulator and use it for DSI
16067e4bf443 arm64: dts: qcom: sm6350: add refgen regulator and use it for DSI
80c79d2acc90 arm64: dts: qcom: sdm845: add refgen regulator and use it for DSI
bda9f75a892b arm64: dts: qcom: sdm670: add refgen regulator and use it for DSI
b8ace3e6ecdb arm64: dts: qcom: sc8180x: add refgen regulator and use it for DSI
b538811379ac arm64: dts: qcom: sc7280: add refgen regulator and use it for DSI
b19ee0665250 arm64: dts: qcom: sc7180: add refgen regulator and use it for DSI
1f101c50212e arm64: dts: qcom: lemans: add refgen regulator and use it for DSI
439d1c76437d arm64: dts: qcom: lemans: move USB PHYs to a proper place
e9fcf9e5f564 arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature
34b2832b6844 arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3
5436a604fa71 arm64: dts: qcom: lemans-evk-camera: Add DT overlay
1d729fa64cca dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+
6c341a4fdfdf arm64: dts: qcom: lemans: Add missing quirk for HS only USB controller
56542dbdfeff arm64: dts: qcom: x1e80100: Add missing quirk for HS only USB controller
112769f4d430 arm64: dts: qcom: x1e80100: Fix compile warnings for USB HS controller
b832bda21981 regulator: dt-bindings: nxp,pca9450: document input supplies
961a5a4ee941 dt-bindings: i2c: i2c-rk3x: Add compatible string for RK3506
165f06e79c8b dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU
35dfa89afd17 ASoC: dt-bindings: sound: cirrus: cs530x: Add SPI bus support
d11c98dfcc39 ASoC: dt-bindings: sound: cirrus: cs530x: Add cs530x
ba201aaeb06f ASoC: dt-bindings: qcom,sm8250: add QRB2210 soundcard
fe51b3ea5218 arm64: dts: mediatek: mt8365-evk: Enable GPU support
3bde7c2a848e arm64: dts: mediatek: mt8365: Add GPU support
870d1f398ffe arm64: dts: mediatek: mt8395-genio-1200-evk: Describe CPU supplies
8d72b4f42dfe arm64: dts: ti: k3-am625: Add OLDI support
16d76dfddbf7 arm64: dts: ti: k3-am62: Add support for AM625 OLDI IO Control
6c6bdc4cbf5f Merge tag 'v6.18-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
ebdc24c72b4a Merge 6.18-rc3 into usb-next
7ed3b2e5599f Merge 6.18-rc3 into tty-next
85d911015f1d ARM: dts: imx7ulp: remove bias-pull-up
d5145a78e6cc ARM: dts: remove undocumented clock-names for ov5642
ddb3ea4100b0 ARM: dts: add device_type for memory node
0f41d0289279 ARM: dts: Add bus type for parallel ov5640
174745c222ef ARM: dts: imx6q-cm-fx6.dts: add supplies for wm8731
3e901f54959a ARM: dts: imx6qdl-skov-cpu fix typo interrupt
715eae8f8946 ARM: dts: imx: remove redundant linux,phandle
eb2938ae945f ARM: dts: imx6ull-dhcom-pdk2: rename power-supply to vcc-supply for touchscreen
68481171e694 ARM: dts: imx: add power-supply for lcd panel
607a34b4e1e6 arm64: dts: imx8mp pollux: add displays for expansion board
c756cb2157c8 arm64: dts: imx8mp pollux: add expansion board overlay
35124f689bec arm64: dts: imx8mp pollux: add display overlays
0a5af52fdc35 arm64: dts: im8mp-phy{board,core}: update license
5f3cbbd812e4 ARM: dts: imx6qdl-nitrogen6_max: rename i2c<n>mux to i2c
148d78f5d7c7 ARM: dts: imx6ull-phytec-tauri: remove extra space before jedec,spi-nor
68ba173bfb63 ARM: dts: imx6q-utilite-pro: add missing required property for pci
6bb0e10cbed6 ARM: dts: imx6-tbs2910: rename ir_recv to ir-receiver
0dc65554d185 ARM: dts: imx6: remove pinctrl-name if pinctrl-0 doesn't exist
c23f78848bcb ARM: dts: imx6: change voltage-divider's io-channel-cells to 1
dd16c95859a6 ARM: dts: imx6: remove gpio suffix for regulator
6eeb760dff1b ARM: dts: imx6qdl-ts4900: rename ngpio to ngpios
f34022e3a289 ARM: dts: imx6: rename m95m02 to eeprom
fc53cfa02a15 ARM: dts: imx6: rename touch-thermal0 to touch-0-thermal
593b1adbf865 ARM: dts: imx6: rename stmpgpio to gpio
71a312e89dcc arm64: dts: ls1046a-qds: describe the two on-board SFP+ cages
57e788cb9463 arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages
ea857479f1a7 arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller
4e6379390201 arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO controllers
22c9aab9e72b dt-bindings: fsl,fpga-qixis: describe the gpio child node found on LS1046AQDS
f9717289fab3 dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA
0f2d30c5a87b arm64: dts: add Protonic PRT8ML board
44f5dafee9e3 dt-bindings: arm: fsl: Add Protonic PRT8ML
48b60fcae7c0 arm64: dts: imx8mp: add cpuidle cooling device to the alert trip point
ac037306a1e0 arm64: dts: imx8mp: add idle cooling devices to cpu core
8ae263a3064e ARM: dts: imx53: enable PMIC RTC on imx53-qsrb
3c4726b98664 arm64: dts: ti: k3-am62p: Fix memory ranges for GPU
b35d9493bad5 ARM: dts: imx6q-evi: fix rtc compatible
ea69deb91420 arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pin
484223e39d97 arm64: dts: imx8mm-phyboard-polis-rdk: Add USB1 OC pin configuration
72eec38ebcaa arm64: dts: freescale: add initial support for i.MX 95 Verdin Evaluation Kit (EVK)
ee59ce8ff430 dt-bindings: arm: imx: document i.MX 95 Verdin Evaluation Kit (EVK)
9ef8ce8481ec dt-bindings: PCI: Update the email address for Manivannan Sadhasivam
56e26298a815 dt-bindings: PCI: amlogic,axg-pcie: Fix select schema
564dfd1f9ca2 dt-bindings: net: rockchip-dwmac: Add compatible string for RK3506
3087358ee09d dt-bindings: net: snps,dwmac: Sync list of Rockchip compatibles
c89e1fcfec10 dt-bindings: net: snps,dwmac: move rk3399 line to its correct position
e461194da4c0 dt-bindings: npu: Add Arm Ethos-U65/U85
353531f35075 dt-bindings: interrupt-controller: Add UltraRISC DP1000 PLIC
de06ea816986 dt-bindings: vendor-prefixes: Add UltraRISC
d3a1e4d484df dt-bindings: power: Add MT8196 GPU frequency control binding
3b73948a0445 Merge drm/drm-next into drm-misc-next
d0b25ecc26d8 dt-bindings: usb: qcom,snps-dwc3: Add the SM8750 compatible
8670949a158f Merge tag 'drm-misc-next-2025-10-21' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
70dcade11be9 dt-bindings: pinctrl: document polarfire soc iomux0 pinmux
88c915d35256 dt-bindings: pinctrl: document pic64gx "gpio2" pinmux
274812ffbf96 Merge tag 'mpfs-pinctrl-binding-base' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into devel
6d5dde245bd9 riscv: dts: spacemit: add Ethernet and PDMA to OrangePi RV2
fad36d25ccb5 arm64: dts: socfpga: move sdmmc-ecc to the base DTSI file
2aa19bd6f8e7 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
7e30f13a4210 dt-bindings: pinctrl: toshiba,visconti: Drop redundant functions type
ed8370fc0299 spi: dt-bindings: don't check node names
daf129bdd941 regulator: dt-bindings: qcom,rpmh: Add support for PMR735D
3656e3bf4601 dt-bindings: ata: snps,dwc-ahci: Allow 'iommus' property
813d439f1b42 dt-bindings: cache: qcom,llcc: Document the Kaanapali LLCC
57e1b975973d Merge branch '20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com' into clk-for-6.19
5e2ad3a0682d dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC
c1274eab7600 dt-bindings: clock: gcc-ipq5424: Add definition for GPLL0_OUT_AUX
4c53f926cad9 dt-bindings: interconnect: Add Qualcomm IPQ5424 NSSNOC IDs
8c2e14302656 dt-bindings: clock: Add "#interconnect-cells" property in IPQ9574 example
e6c83903067c Merge branch '20250919-sm7150-dispcc-fixes-v1-1-308ad47c5fce@mainlining.org' into clk-for-6.19
a0d2382fd32f dt-bindings: clock: sm7150-dispcc: Add MDSS_CORE reset
dff7e409efcf Merge branch '20250919-sm6350-mdss-reset-v1-1-48dcac917c73@fairphone.com' into arm64-for-6.19
574132b74852 Merge branch '20250919-sm6350-mdss-reset-v1-1-48dcac917c73@fairphone.com' into clk-for-6.19
01ad74a84bdd dt-bindings: clock: dispcc-sm6350: Add MDSS_CORE & MDSS_RSCC resets
e80ee5280f2d dt-bindings: touchscreen: consolidate simple touch controller to trivial-touch.yaml
903eedf389dc dt-bindings: touchscreen: trivial-touch: add reset-gpios and wakeup-source
f4a1045b920f dt-bindings: pinctrl: Convert bitmain,bm1880-pinctrl to DT schema
eb7e4aa25cb3 dt-bindings: pinctrl: Convert brcm,ns2-pinmux to DT schema
fd689ccf7274 dt-bindings: pinctrl: Convert actions,s900-pinctrl to DT schema
b7e0432846be dt-bindings: pinctrl: Convert actions,s700-pinctrl to DT schema
c08920cec98b dt-bindings: power: rockchip: Add support for RV1126B
b3b23a0f8683 dt-bindings: power: Add support for MT8196 power controllers
51b5174e9573 dt-bindings: serial: samsung: add samsung,exynos8890-uart compatible
c1bff4d3d777 dt-bindings: serial: samsung: Add compatible for ARTPEC-9 SoC
ee20506ba653 dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for RK3506
15362ce0af90 dt-bindings: usb: Add Apple dwc3
870762c4b8c1 dt-bindings: display: bridge: renesas,dsi-csi2-tx: Allow panel@ subnode
8e8fce1d076f dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatibles
73c95b080395 dt-bindings: soc: samsung: exynos-sysreg: add power-domains
d94084d540c3 dt-bindings: net: dsa: yt921x: Add Motorcomm YT921x switch support
7bc3013c4655 arm64: dts: exynos: gs101: fix sysreg_apm reg property
262938d64ab3 arm64: dts: exynos: gs101: fix clock module unit reg sizes
742ec6e8cf66 arm64: dts: exynos: gs101: add sysreg_misc and sysreg_hsi0 nodes
aefc60f54563 ASoC: spacemit: add i2s support to K1 SoC
de9b11f211ce ASoC: amd: ps: Propagate the PCI subsystem Vendor and
a1defb29d354 dt-bindings: mfd: Add binding for the PF1550 PMIC
83900b0792b2 ASoC: dt-bindings: don't check node names
2711a23f210f dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC
3de404ea2c48 dt-bindings: gpu: img,powervr-rogue: Rework the allOf section
f79a526c7eec dt-bindings: gpu: img,powervr-rogue: Drop useless power domains items
b481980f951e dt-bindings: power: qcom,rpmpd: add new RPMH levels
31cd44b77157 dt-bindings: power: qcom,rpmpd: document the Kaanapali RPMh Power Domains
bc3762fb2bb0 dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host controller
10fec8c27b19 dt-bindings: mmc: sdhci-msm: Add sm8750 compatible
901a61837701 dt-bindings: mmc: sdhci-msm: Add Kaanapali compatible
aa1a3d8bbd02 dt-bindings: net: airoha: Add AN7583 support
02d547c81f79 dt-bindings: leds: Add default-brightness property to common.yaml
60994a5eb151 dt-bindings: leds: arc,arc2c0608: Convert to DT Schema
ef7ee3e02ec4 arm64: dts: imx: correct the flexspi compatible string to match with yaml
e007824d979b arm64: dts: imx95-15x15-evk: add fan-supply property for pwm-fan
46223f4e5cc9 arm64: dts: imx8mp-venice-gw702x: remove off-board sdhc1
6222712cae1c arm64: dts: imx8mp-venice-gw702x: remove off-board uart
65f4ea01f12f arm64: dts: imx8mm-venice-gw72xx: remove unused sdhc1 pinctrl
4240fdaa89f9 arm64: dts: imx8mm-venice-gw700x: reduce RGMII CLK drive strength
ce03cd9563a7 arm64: dts: imx8mp-venice-gw702x: reduce RGMII CLK drive strength
8e9570de34c6 arm64: dts: imx8m{m,n,p}-venice: disable unused clk output for TI PHY
e8dcc0e79ee7 arm64: dts: freescale: imx8mp-venice-gw7905-2x: remove duplicate usdhc1 props
bb72e91975a0 Merge tag 'drm-misc-next-2025-10-02' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
74373cb6b8ae arm64: dts: ten64: add board controller binding
3b72f372df94 dt-bindings: embedded-controller: add Traverse Ten64 board controller
4b9661b5f088 dt-bindings: PCI: mediatek: Add support for Airoha AN7583
fd426bae943f dt-bindings: PCI: mediatek: Convert to YAML schema
9388bfa2880c dt-bindings: iio: imu: smi330: Add binding
0835a5946289 dt-bindings: iio: adc: add max14001
b126aa2dfe6e dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards
d25b5eda5c0e ARM: dts: socfpga: add Enclustra SoM dts files
a9475067dc8d dt-bindings: altera: removal of generic PE1 dts
789bd393c476 ARM: dts: socfpga: removal of generic PE1 dts
41d2b099ebe8 dt-bindings: altera: add Mercury AA1 variants
ee980ead62bd ARM: dts: socfpga: add Mercury AA1 variants
eeef84c9b00c dt-bindings: altera: add binding for Mercury+ SA2
4391b4a2c127 ARM: dts: socfpga: add Enclustra Mercury+ SA2
5adcaa96564e dt-bindings: altera: add Enclustra Mercury SA1
88ad7b46fa60 ARM: dts: socfpga: add Enclustra Mercury SA1
568ac017e71f ARM: dts: socfpga: add Enclustra base-board dtsi
3f63d5d4e2fe ARM: dts: socfpga: add Enclustra boot-mode dtsi
8dd08d78f5ba scsi: ufs: dt-bindings: exynos: Add power-domains
a31096a8a288 arm64: dts: socfpga: agilex5: Add SMMU nodes
712b3762e99d dt-bindings: dma: snps,dw-axi-dmac: Add iommu property
88779b6f6179 dt-bindings: mtd: cdns,hp-nfc: Add iommu property
d30281d77a66 arm64: dts: rockchip: add DTs for 100ASK DShanPi A1
8b4e22665c32 dt-bindings: arm: rockchip: Add 100ASK DShanPi A1
beccd172fb12 arm64: dts: rockchip: add LinkEase EasePi R1
32d764c25448 dt-bindings: arm: rockchip: Add LinkEase EasePi R1
d0a76d134dcb dt-bindings: vendor-prefixes: Document LinkEase
0b9924f364f6 arm64: dts: freescale: debix-som-a-bmb-08: Enable HDMI output
1e9491ba3fe4 arm64: dts: freescale: imx93-phyboard-segin: Add USB vbus regulators
619db2da8f51 arm64: dts: freescale: imx93-phyboard-nash: Add USB vbus regulators
e77e2a381abb arm64: dts: tqma8mpql-mba8mpxl: Add MicIn routing
a2c00e37686e dt-bindings: soc: imx-iomuxc-gpr: Document the CSI mux
d11fba2f0f17 arm64: dts: rockchip: Enable PCIe controller on Radxa E20C
69fce4d52f9f arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
cf6998f0b7f9 arm64: dts: imx94: add DDR Perf Monitor node
925d21a88835 arm64: dts: imx8mp-skov: support new 10" panel board
c7123d625cba dt-bindings: arm: fsl: add compatible for Skov i.MX8MP variant
76be70ea2b33 ARM: dts: imx53-usbarmory: Replace license text comment with SPDX identifier
5fc73024ccf0 arm64: dts: fsl-lx2160a: include rev2 chip's dts
f6d5355371bd arm64: dts: exynos: gs101: add OPPs
a80f7ab256b0 arm64: dts: exynos: gs101: add CPU clocks
711c54551c62 arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol node
d6e19a329ed6 Merge branch 'for-v6.19/clk-dt-bindings' into next/dt64
c7c9ffbb33d9 dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks
f5583b767710 ASoC: dt-bindings: Add bindings for SpacemiT K1
909d59ae9fd3 dt-bindings: iio: health: max30100: Add LED pulse-width property
1264b75b4365 dt-bindings: iio: accel: adxl345: document second interrupt
a0bc29fad0f8 dt-bindings: iio: adc: adi,ad4080: add support for AD4081
2b181b4c0b81 dt-bindings: iio: adc: adi,ad4080: add support for AD4084
45ec10b5820b dt-bindings: iio: imu: Add inv_icm45600
b8481383370e dt-bindings: iio: Add Infineon DPS310 sensor documentation
dbfe8a35702d dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
3fe2b604fd9f dt-bindings: iio: pressure: add binding for mpl3115
413ce13e8678 dt-bindings: PCI: qcom,pcie-sm8550: Add Kaanapali compatible
837261883d7a dt-bindings: PCI: dwc: rockchip: Add RK3528 variant
8b3571906f1a riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards
342bd1ea47ef dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible
d08900ec8d28 dt-bindings: timers: Add Tenstorrent Blackhole compatible
6156a10bd0f0 dt-bindings: riscv: cpus: Add SiFive X280 compatible
44d0b8da095d dt-bindings: riscv: Add Tenstorrent Blackhole compatible
e83a4993fcd2 dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC
62dab43e8d3e dt-bindings: samsung: exynos-sysreg: add exynos7870 sysregs
203b184e5696 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos8890-chipid compatible
ba1005cb8e45 dt-bindings: soc: samsung: exynos-pmu: add exynos8890 compatible
5a2537ff3afc dt-bindings: input: ti,twl4030-keypad: convert to DT schema
4ea1863701a5 dt-bindings: input: Convert MELFAS MIP4 Touchscreen to DT schema
bb443e84f228 dt-bindings: touchscreen: move ar1021.txt to trivial-touch.yaml
785c3bb8f977 dt-bindings: touchscreen: rename maxim,max11801.yaml to trivial-touch.yaml
a7c727b8bb5c arm64: dts: qcom: apq8096-db820c: Specify zap shader location
2467229e34f2 arm64: dts: qcom: pmi8950: Fix VADC channel scaling factors
a033b5e6ee0b arm64: dts: qcom: pmi8950: Add missing VADC channels
b203038f0b2d arm64: dts: qcom: msm8916-samsung-rossa: Move touchscreen to common device tree
498c31cf533e arm64: dts: qcom: x1e80100: Extend the gcc input clock list
aaf0eb44f62c arm64: dts: qcom: ipq5424: correct the TF-A reserved memory to 512K
c22b68ceed52 dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets
08b0c2e63639 riscv: dts: thead: add zfh for th1520
1459e59d133c riscv: dts: thead: add ziccrse for th1520
6e8a600bf08b riscv: dts: thead: add xtheadvector to the th1520 devicetree
0aec2563cf98 spi: airoha: driver fixes & improvements
329d7e37392f rpmh-regulators: Update rpmh-regulator driver and
1bb48f39eb71 dt-bindings: can: m_can: Add wakeup properties
db2e58334671 dt-bindings: crypto: qcom,inline-crypto-engine: Document the kaanapali ICE
602c8138dfcc dt-bindings: rng: microchip,pic32-rng: convert to DT schema
bea471a313df ARM: dts: aspeed: santabarbara: Add eeprom device node for PRoT module
570aff914512 ARM: dts: aspeed: santabarbara: Add AMD APML interface support
5120b30e949c ARM: dts: aspeed: santabarbara: Add gpio line name
5039a83f35a2 ARM: dts: aspeed: santabarbara: Add bmc_ready_noled Led
99c9978a1748 ARM: dts: aspeed: santabarbara: Enable MCTP for frontend NIC
b8479e7e3097 ARM: dts: aspeed: santabarbara: Add sensor support for extension boards
3b6d4a3434a2 ARM: dts: aspeed: santabarbara: Add blank lines between nodes for readability
10d1e5ab47c4 ARM: dts: aspeed: yosemite5: Add Meta Yosemite5 BMC
3869760104cc dt-bindings: arm: aspeed: add Meta Yosemite5 board
902faf7dc83d dt-bindings: net: cdns,macb: sort compatibles
1fd8f6d28ecc dt-bindings: net: qcom: ethernet: Add interconnect properties
29b03ff4efb4 dt-bindings: ethernet: eswin: Document for EIC7700 SoC
1a9e02a5ba9a dt-bindings: trivial-devices: add ADT7410, ADT7420 and ADT7422
21f24b5c2c85 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
bc10f2921dff ASoC: dt-bindings: qcom: Add Kaanapali LPASS macro codecs
f2999cde47ab ASoC: dt-bindings: qcom,sm8250: Add kaanapali sound card
400e68008bf8 dt-bindings: gpio: add QIXIS FPGA based GPIO controller
664a89ff08e2 dt-bindings: net: Convert amd,xgbe-seattle-v1a to DT schema
37d5df40c20f dt-bindings: power: Add power domain IDs for Tegra264
32fe568870f5 dt-bindings: net: airoha: npu: Add AN7583 support
d0cbb14794cc regulator: dt-bindings: rpmh-regulator: Update pmic-id DT prop info for new CMD-DB
332ab6ff5bd9 regulator: dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102
80c52ef03bf6 dt-bindings: trivial-devices: add mps,mp9945
555a8f7e561c dt-bindings: hwmon: Convert apm,xgene-slimpro-hwmon to DT schema
3e3728a86078 dt-bindings: hwmon: pmbus/max17616: Add SMBALERT interrupt property
c4b205751635 dt-bindings: hwmon: max31790: Use addressed fan nodes
7ef6c454b451 dt-bindings: hwmon: Move max31785 compatibles to max31790 document
b69a6c81f405 dt-bindings: hwmon: ntc-thermistor: Add Murata ncp18wm474 NTC
c834398179f4 dt-bindings: net: dsa: nxp,sja1105: Add optional clock
644b93e866c7 Add tegra264 audio device tree support
0ec749fb373a arm64: dts: agilex5: Add GMAC0 node for NAND daughter card
83382381673f arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
e8d8cde97152 arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
12b57453cef9 arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
0e93d911fccc arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
1ae49870f90e dt-bindings: ipmi: Convert aspeed,ast2400-ibt-bmc to DT schema
f6b10b7175fd dt-bindings: ipmi: Convert nuvoton,npcm750-kcs-bmc to DT schema
3fc4bd923e76 dt-bindings: mailbox: Convert apm,xgene-slimpro-mbox to DT schema
8c646578a134 arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2
e30e000e6226 arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R76S
f2a43b9d7c62 dt-bindings: arm: rockchip: Add FriendlyElec NanoPi R76S
68690d18452f arm64: dts: rockchip: Add DSI for RK3368
b8af69717fd7 arm64: dts: rockchip: Add D-PHY for RK3368
81fb39a4f81f arm64: dts: rockchip: Add display subsystem for RK3368
8d8500da1eda media: doc/dt-bindings: remove support of stih407-c8sectpfe
9c5c2835937e media: include: remove c8sectpfe header
8ea2c52474e0 media: dt-bindings: snps,dw-hdmi-rx.yaml: Updated maintainers entry
c949d4277f9b dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3368 DSI
7a3284df2742 ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623
1f3b19b7000c dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks
d506d2c5bc30 riscv: dts: spacemit: add i2c aliases on BPI-F3
5f0a3e9074eb riscv: dts: spacemit: add 24c02 eeprom on BPI-F3
ff2e9131fac8 riscv: dts: spacemit: enable the i2c2 adapter on BPI-F3
9cac0efe017c riscv: dts: spacemit: define regulator constraints
1e07287891e5 riscv: dts: spacemit: define fixed regulators
3539906b382a riscv: dts: spacemit: enable the i2c8 adapter
60cbd15ae8f3 riscv: dts: spacemit: add UART pinctrl combinations
8e83318cecb9 dt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add QCM2290 compatible
087950d167d4 dt-bindings: sound: Update ADMAIF bindings for tegra264
14fc96f63628 spi: dt-bindings: spi-qpic-snand: Add IPQ5332 compatible
25a483f7c268 spi: dt-bindings: spi-qpic-snand: Add IPQ5424 compatible
d89aba1eea74 regulator: dt-bindings: Convert Dialog DA9211 Regulators to DT schema
17d7d294647f ASoC: dt-bindings: ti,tas2781: Add TAS5802, TAS5815, and TAS5828
5339e856d177 dt-bindings: pinctrl: describe Kaanapali TLMM
30d885ac61bc dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema
af335c4fcfcf dt-bindings: pinctrl: Convert Marvell Berlin pinctrl to DT schema
c33aa0df67da dt-bindings: pinctrl: qcom,pmic-gpio: Add GPIO bindings for Glymur PMICs
8421e716c562 dt-bindings: pinctrl: qcom: msm8960: rename msmgpio node to tlmm
cec5d30b9218 arm64: dts: mediatek: Add MT6878 pinmux macro header file
8ff8abc243b1 arm64: dts: marvell: pxa1908: Add power domains
d1d6fb81600c arm64: dts: marvell: samsung,coreprimevelte: Add USB connector
6ace4d24b710 arm64: dts: marvell: samsung,coreprimevelte: Fill in memory node
0bd2fe9388e7 arm64: dts: marvell: samsung,coreprimevelte: Drop some reserved memory
437faeb5dc32 arm64: dts: marvell: pxa1908: Move ramoops to SoC dtsi
a5ec1282225a arm64: dts: marvell: samsung,coreprimevelte: Add vibrator
825b97e09055 arm64: dts: marvell: pxa1908: Add PWMs
d12ad2275710 arm64: dts: marvell: samsung,coreprimevelte: Enable eMMC
5eb80d9b8334 arm64: dts: marvell: samsung,coreprimevelte: Correct CD GPIO
79c3335d081e arm64: dts: marvell: samsung,coreprimevelte: Add backlight
d8cff2a968db arm64: dts: samsung,coreprimevelte: add SDIO
c9c39f4b16db arm64: dts: samsung,coreprimevelte: add touchscreen
244e7d122482 arm64: dts: samsung,coreprimevelte: add PMIC
74977c1c5640 dt-bindings: pinctrl: pinctrl-single: add ti,am62l-padconf compatible
8536868c9e4b Merge existing fixes from spi/for-6.18 into new branch
82db9f09b4b6 dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings
adfa91a58551 ARM: dts: mediatek: add basic support for Alcatel yarisxl board
f11c24e9a047 dt-bindings: arm: mediatek: Add MT6582 yarisxl
dce0e0e0bbf2 ARM: dts: mediatek: mt6582: add enable-method property to cpus
f7589557ab13 ARM: dts: mediatek: mt6582: add clock-names property to uart nodes
323f4d815507 ARM: dts: mediatek: mt6582: add mt6582 compatible to timer
097db3c6ea28 ARM: dts: mediatek: mt6582: remove compatible property from root node
9c27442063f2 ARM: dts: mediatek: mt6582: sort nodes and properties
403c1b4d6187 ARM: dts: mediatek: mt6582: move MMIO devices under soc node
11992a913b29 arm64: dts: mediatek: mt7986-bpi-r3: Change fan PWM value for mid speed
4ce0371faeb8 arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510
b6d0d55c25d2 arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700
42ddada8731b arm64: dts: renesas: eagle-function-expansion: Add eMMC support
e169da7bbac7 arm64: dts: mediatek: mt7988a: add 'soc-uuid' cell to efuse
081477510a84 arm64: dts: mediatek: mt7981b: add 'soc-uuid' cell to efuse
2a5e801a8272 arm64: dts: mediatek: mt7986a: add 'soc-uuid' cell to efuse
60bdcb59f1c1 arm64: dts: mediatek: mt7622: add 'soc-uuid' cell to efuse
02a0322e30a5 arm64: dts: mediatek: mt7981b: OpenWrt One: set console UART to 115200
858ad1454d88 arm64: dts: mediatek: mt7981b: add labels for UART0/1/2 nodes
297ef620f3c0 arm64: dts: mediatek: add device-tree for Genio 1200 EVK UFS board
44309731e2c5 arm64: dts: mediatek: mt8395-genio-1200-evk: Move common parts to dtsi
902fc9e1b202 dt-bindings: arm64: mediatek: add mt8395-evk-ufs board
bc577dfaf7ac arm64: dts: renesas: v3[mh]sk: Remove wrong sound property in HDMI encoder node
a37f90d51a48 arm64: dts: renesas: r9a09g047: Add TSU node
18bc8de38388 arm64: dts: renesas: sparrow-hawk: Add overlay for Argon40 fan HAT
e9ed5f73aee7 arm64: dts: renesas: sparrow-hawk: Add overlay for RPi Display 2
551f6fd1b254 arm64: dts: renesas: rzg2l-smarc: Drop clock-frequency from camera sensor node
a95b8d0c4143 arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Drop clock-frequency from camera sensor node
fc62ff7a6276 arm64: dts: mt8183: Rename nodes to match audiosys DT schema
fe6ec06b8913 arm64: dts: renesas: r9a08g045: Add TSU node
4c6e278b8c7b arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port
ee6712b604fb arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port
51bdb4009541 arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port
b50b60ea0e2d arm64: dts: allwinner: a523: Add GMAC200 ethernet controller
c5b47b1bac1d dt-bindings: iio: accel: bosch,bma220 set irq type in example block
0ef2548ab75c dt-bindings: iio: accel: bosch,bma220 setup SPI clock mode
f9181a88c0d0 dt-bindings: iio: accel: bosch,bma220 cleanup typo
c62d62a9c011 dt-bindings: usb: samsung,exynos-dwc3 add exynos8890 compatible
b611d5ed78b9 dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
a67b395e0945 Merge drm/drm-next into drm-misc-next
0402ea10786c dt-bindings: usb: add missed compatible string for arm64 layerscape
705a2538aa2b dt-bindings: usb: usbmisc-imx: add fsl,imx94-usbmisc compatible
95525b59b0f5 dt-bindings: usb: xhci: Add "generic-xhci" compatible for Marvell Armada 37xx/8k
859d85310dba dt-bindings: usb: xhci: Allow "iommus" and "dr_mode" properties
7a5d9bd5d6eb dt-bindings: usb: samsung,exynos-dwc3: add power-domains
2186f5c4ca2e dt-bindings: usb: ehci: Add Aspeed AST2700 compatible
69e3266e824a dt-bindings: usb: uhci: Add Aspeed AST2700 compatible
dae59b5bafa2 dt-bindings: usb: uhci: Add reset property
04df665d29d4 arm64: dts: exynos: gs101-pixel-common: add node for s2mpg10 / clock
9dae447565fa dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC
1b965b552c12 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos9610 compatible
b81e4bfd908f arm64: dts: exynos990: Add sysreg nodes for PERIC0 and PERIC1
8743323f41e6 dt-bindings: soc: samsung: exynos-sysreg: Add Exynos990 PERIC0/1 compatibles
bde5aa415166 ARM: dts: aspeed: clemente: Add HDD LED GPIO
6a4065eec872 ARM: dts: aspeed: Fix max31785 fan properties
9c59a4511400 ARM: dts: aspeed: Add Balcones system
a7ffeb0bbecb dt-bindings: arm: aspeed: add IBM Bonnell board
1dff0225f2eb dt-bindings: arm: aspeed: add IBM Balcones board
a94432ea0d05 ARM: dts: aspeed: harma: Add MCTP I2C controller node
0ecac01f7e2f ARM: dts: aspeed: yosemite4: allocate ramoops for kernel panic
fa4c4abc31e9 ARM: dts: aspeed: clemente: add shunt-resistor-micro-ohms for LM5066i
894131aa1c07 arm64: dts: exynosautov920: add CMU_MFC clock DT nodes
5b2dc2a4f513 arm64: dts: exynosautov920: add CMU_M2M clock DT nodes
ed22b3fc82cb dt-bindings: clock: exynosautov920: add mfc clock definitions
b4a0f0e50ace dt-bindings: clock: exynosautov920: add m2m clock definitions
a340e0384505 dt-bindings: clock: google,gs101-clock: add power-domains
60751811d057 arm64: dts: exynos7870-on7xelte: add bus-width to mmc0 node
b7ee917ada06 arm64: dts: exynos7870-j6lte: add bus-width to mmc0 node
85cfceeeaf29 arm64: dts: exynos7870-a2corelte: add bus-width to mmc0 node
c8f9ea7b573d dt-bindings: pinctrl: samsung: add exynos8890-wakeup-eint compatible
40ec0056b055 dt-bindings: pinctrl: samsung: add exynos8890 compatible
90cbd1d5164a dt-bindings: hwmon: pmbus: add max17616
15ef2fa902bf dt-bindings: hwmon: Add MPS mp2925 and mp2929
332bd559bc71 dt-bindings: gpu: mali-valhall: make mali-supply optional
3810fc1b5cb9 dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible
13b095bf2ae0 dt-bindings: display: panel: document Sharp LQ079L1SX01 panel
9e7d02b705d0 dt-bindings: ili9881c: Allow port subnode
061a6134b73c dt-bindings: ili9881c: Document 5" Raspberry Pi 720x1280
4e3144729da1 dt-bindings: display: simple: Add JuTouch JT101TM023 panel
5bbeb3d7be6a dt-bindings: vendor-prefixes: Add JuTouch Technology Co, Ltd
ba2c3245f772 dt-bindings: display: imx: add HDMI PAI for i.MX8MP

git-subtree-dir: dts/upstream
git-subtree-split: 258d5b0e2447a2a0eb5a910fc7338141e206a5af
---
 include/dt-bindings/arm/qcom,ids.h                 |   2 +
 include/dt-bindings/clock/google,gs101-acpm.h      |  26 ++
 include/dt-bindings/clock/imx8ulp-clock.h          |   5 +
 include/dt-bindings/clock/qcom,dispcc-sm6350.h     |   4 +
 include/dt-bindings/clock/qcom,ipq5424-gcc.h       |   3 +-
 include/dt-bindings/clock/qcom,ipq5424-nsscc.h     |  65 ++++
 include/dt-bindings/clock/qcom,kaanapali-gcc.h     | 241 ++++++++++++
 include/dt-bindings/clock/qcom,mmcc-sdm660.h       |   1 +
 include/dt-bindings/clock/qcom,sm7150-dispcc.h     |   3 +
 include/dt-bindings/clock/qcom,sm8750-videocc.h    |  40 ++
 include/dt-bindings/clock/qcom,x1e80100-dispcc.h   |   3 +
 include/dt-bindings/clock/qcom,x1e80100-gcc.h      |  61 ++++
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h      |   1 +
 include/dt-bindings/clock/renesas,r9a09g047-cpg.h  |   2 +
 include/dt-bindings/clock/renesas,r9a09g056-cpg.h  |   2 +
 include/dt-bindings/clock/renesas,r9a09g057-cpg.h  |   4 +
 include/dt-bindings/clock/rk3568-cru.h             |   6 +-
 include/dt-bindings/clock/rockchip,rk3506-cru.h    | 285 +++++++++++++++
 include/dt-bindings/clock/rockchip,rv1126b-cru.h   | 392 ++++++++++++++++++++
 include/dt-bindings/clock/samsung,exynosautov920.h |  10 +
 include/dt-bindings/clock/toshiba,tmpv770x.h       |  14 +-
 include/dt-bindings/input/linux-event-codes.h      |   9 +
 include/dt-bindings/interconnect/qcom,ipq5424.h    |  33 ++
 .../dt-bindings/interconnect/qcom,kaanapali-rpmh.h | 149 ++++++++
 include/dt-bindings/interconnect/qcom,sdx75.h      |   2 -
 include/dt-bindings/media/c8sectpfe.h              |  13 -
 include/dt-bindings/media/video-interfaces.h       |   4 +
 .../memory/mediatek,mt8189-memory-port.h           | 283 ++++++++++++++
 include/dt-bindings/power/mediatek,mt8196-power.h  |  58 +++
 include/dt-bindings/power/nvidia,tegra264-bpmp.h   |  24 ++
 include/dt-bindings/power/qcom,rpmhpd.h            |   4 +
 .../power/rockchip,rv1126b-power-controller.h      |  17 +
 include/dt-bindings/reset/airoha,en7523-reset.h    |  61 ++++
 include/dt-bindings/reset/eswin,eic7700-reset.h    | 298 +++++++++++++++
 include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h   |  16 +
 include/dt-bindings/reset/qcom,ipq5424-nsscc.h     |  46 +++
 include/dt-bindings/reset/rockchip,rk3506-cru.h    | 211 +++++++++++
 include/dt-bindings/reset/rockchip,rv1126b-cru.h   | 405 +++++++++++++++++++++
 include/dt-bindings/reset/thead,th1520-reset.h     | 219 ++++++++++-
 include/dt-bindings/reset/toshiba,tmpv770x.h       |   9 +-
 include/dt-bindings/watchdog/aspeed-wdt.h          | 138 +++++++
 41 files changed, 3145 insertions(+), 24 deletions(-)
 create mode 100644 include/dt-bindings/clock/google,gs101-acpm.h
 create mode 100644 include/dt-bindings/clock/qcom,ipq5424-nsscc.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-gcc.h
 create mode 100644 include/dt-bindings/clock/qcom,sm8750-videocc.h
 create mode 100644 include/dt-bindings/clock/rockchip,rk3506-cru.h
 create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h
 create mode 100644 include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h
 delete mode 100644 include/dt-bindings/media/c8sectpfe.h
 create mode 100644 include/dt-bindings/memory/mediatek,mt8189-memory-port.h
 create mode 100644 include/dt-bindings/power/mediatek,mt8196-power.h
 create mode 100644 include/dt-bindings/power/nvidia,tegra264-bpmp.h
 create mode 100644 include/dt-bindings/power/rockchip,rv1126b-power-controller.h
 create mode 100644 include/dt-bindings/reset/airoha,en7523-reset.h
 create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h
 create mode 100644 include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
 create mode 100644 include/dt-bindings/reset/qcom,ipq5424-nsscc.h
 create mode 100644 include/dt-bindings/reset/rockchip,rk3506-cru.h
 create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h

(limited to 'include')

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index cb8ce53146f..8776844e0ee 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -240,6 +240,7 @@
 #define QCOM_ID_SC7280			487
 #define QCOM_ID_SC7180P			495
 #define QCOM_ID_QCM6490			497
+#define QCOM_ID_QCS6490			498
 #define QCOM_ID_SM7325P			499
 #define QCOM_ID_IPQ5000			503
 #define QCOM_ID_IPQ0509			504
@@ -286,6 +287,7 @@
 #define QCOM_ID_IPQ5424			651
 #define QCOM_ID_QCM6690			657
 #define QCOM_ID_QCS6690			658
+#define QCOM_ID_SM8850			660
 #define QCOM_ID_IPQ5404			671
 #define QCOM_ID_QCS9100			667
 #define QCOM_ID_QCS8300			674
diff --git a/include/dt-bindings/clock/google,gs101-acpm.h b/include/dt-bindings/clock/google,gs101-acpm.h
new file mode 100644
index 00000000000..e2ba89e09fa
--- /dev/null
+++ b/include/dt-bindings/clock/google,gs101-acpm.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025 Linaro Ltd.
+ *
+ * Device Tree binding constants for Google gs101 ACPM clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H
+
+#define GS101_CLK_ACPM_DVFS_MIF				0
+#define GS101_CLK_ACPM_DVFS_INT				1
+#define GS101_CLK_ACPM_DVFS_CPUCL0			2
+#define GS101_CLK_ACPM_DVFS_CPUCL1			3
+#define GS101_CLK_ACPM_DVFS_CPUCL2			4
+#define GS101_CLK_ACPM_DVFS_G3D				5
+#define GS101_CLK_ACPM_DVFS_G3DL2			6
+#define GS101_CLK_ACPM_DVFS_TPU				7
+#define GS101_CLK_ACPM_DVFS_INTCAM			8
+#define GS101_CLK_ACPM_DVFS_TNR				9
+#define GS101_CLK_ACPM_DVFS_CAM				10
+#define GS101_CLK_ACPM_DVFS_MFC				11
+#define GS101_CLK_ACPM_DVFS_DISP			12
+#define GS101_CLK_ACPM_DVFS_BO				13
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
index 827404fadf5..c62d84d093a 100644
--- a/include/dt-bindings/clock/imx8ulp-clock.h
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -255,4 +255,9 @@
 
 #define IMX8ULP_CLK_PCC5_END		56
 
+/* LPAV SIM */
+#define IMX8ULP_CLK_SIM_LPAV_HIFI_CORE		0
+#define IMX8ULP_CLK_SIM_LPAV_HIFI_PBCLK		1
+#define IMX8ULP_CLK_SIM_LPAV_HIFI_PLAT		2
+
 #endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6350.h b/include/dt-bindings/clock/qcom,dispcc-sm6350.h
index cb54aae2723..61426a80e62 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sm6350.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm6350.h
@@ -42,6 +42,10 @@
 #define DISP_CC_SLEEP_CLK			31
 #define DISP_CC_XO_CLK				32
 
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR			0
+#define DISP_CC_MDSS_RSCC_BCR			1
+
 /* GDSCs */
 #define MDSS_GDSC				0
 
diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bindings/clock/qcom,ipq5424-gcc.h
index c15ad16923b..3ae33a0fa00 100644
--- a/include/dt-bindings/clock/qcom,ipq5424-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 /*
  * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  */
 
 #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
@@ -152,5 +152,6 @@
 #define GCC_PCIE3_RCHNG_CLK			143
 #define GCC_IM_SLEEP_CLK			144
 #define GCC_XO_CLK				145
+#define GPLL0_OUT_AUX				146
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,ipq5424-nsscc.h b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h
new file mode 100644
index 00000000000..eeae0dc3804
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
+#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
+
+/* NSS_CC clocks */
+#define NSS_CC_CE_APB_CLK					0
+#define NSS_CC_CE_AXI_CLK					1
+#define NSS_CC_CE_CLK_SRC					2
+#define NSS_CC_CFG_CLK_SRC					3
+#define NSS_CC_DEBUG_CLK					4
+#define NSS_CC_EIP_BFDCD_CLK_SRC				5
+#define NSS_CC_EIP_CLK						6
+#define NSS_CC_NSS_CSR_CLK					7
+#define NSS_CC_NSSNOC_CE_APB_CLK				8
+#define NSS_CC_NSSNOC_CE_AXI_CLK				9
+#define NSS_CC_NSSNOC_EIP_CLK					10
+#define NSS_CC_NSSNOC_NSS_CSR_CLK				11
+#define NSS_CC_NSSNOC_PPE_CFG_CLK				12
+#define NSS_CC_NSSNOC_PPE_CLK					13
+#define NSS_CC_PORT1_MAC_CLK					14
+#define NSS_CC_PORT1_RX_CLK					15
+#define NSS_CC_PORT1_RX_CLK_SRC					16
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC				17
+#define NSS_CC_PORT1_TX_CLK					18
+#define NSS_CC_PORT1_TX_CLK_SRC					19
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC				20
+#define NSS_CC_PORT2_MAC_CLK					21
+#define NSS_CC_PORT2_RX_CLK					22
+#define NSS_CC_PORT2_RX_CLK_SRC					23
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC				24
+#define NSS_CC_PORT2_TX_CLK					25
+#define NSS_CC_PORT2_TX_CLK_SRC					26
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC				27
+#define NSS_CC_PORT3_MAC_CLK					28
+#define NSS_CC_PORT3_RX_CLK					29
+#define NSS_CC_PORT3_RX_CLK_SRC					30
+#define NSS_CC_PORT3_RX_DIV_CLK_SRC				31
+#define NSS_CC_PORT3_TX_CLK					32
+#define NSS_CC_PORT3_TX_CLK_SRC					33
+#define NSS_CC_PORT3_TX_DIV_CLK_SRC				34
+#define NSS_CC_PPE_CLK_SRC					35
+#define NSS_CC_PPE_EDMA_CFG_CLK					36
+#define NSS_CC_PPE_EDMA_CLK					37
+#define NSS_CC_PPE_SWITCH_BTQ_CLK				38
+#define NSS_CC_PPE_SWITCH_CFG_CLK				39
+#define NSS_CC_PPE_SWITCH_CLK					40
+#define NSS_CC_PPE_SWITCH_IPE_CLK				41
+#define NSS_CC_UNIPHY_PORT1_RX_CLK				42
+#define NSS_CC_UNIPHY_PORT1_TX_CLK				43
+#define NSS_CC_UNIPHY_PORT2_RX_CLK				44
+#define NSS_CC_UNIPHY_PORT2_TX_CLK				45
+#define NSS_CC_UNIPHY_PORT3_RX_CLK				46
+#define NSS_CC_UNIPHY_PORT3_TX_CLK				47
+#define NSS_CC_XGMAC0_PTP_REF_CLK				48
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC			49
+#define NSS_CC_XGMAC1_PTP_REF_CLK				50
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC			51
+#define NSS_CC_XGMAC2_PTP_REF_CLK				52
+#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC			53
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kaanapali-gcc.h b/include/dt-bindings/clock/qcom,kaanapali-gcc.h
new file mode 100644
index 00000000000..890e48709f0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-gcc.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				2
+#define GCC_BOOT_ROM_AHB_CLK					3
+#define GCC_CAM_BIST_MCLK_AHB_CLK				4
+#define GCC_CAMERA_AHB_CLK					5
+#define GCC_CAMERA_HF_AXI_CLK					6
+#define GCC_CAMERA_SF_AXI_CLK					7
+#define GCC_CAMERA_XO_CLK					8
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				9
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				10
+#define GCC_CNOC_PCIE_SF_AXI_CLK				11
+#define GCC_DDRSS_PCIE_SF_QTB_CLK				12
+#define GCC_QMIP_CAMERA_CMD_AHB_CLK				13
+#define GCC_DISP_HF_AXI_CLK					14
+#define GCC_DISP_SF_AXI_CLK					15
+#define GCC_EVA_AHB_CLK						16
+#define GCC_EVA_AXI0_CLK					17
+#define GCC_EVA_AXI0C_CLK					18
+#define GCC_EVA_XO_CLK						19
+#define GCC_GP1_CLK						20
+#define GCC_GP1_CLK_SRC						21
+#define GCC_GP2_CLK						22
+#define GCC_GP2_CLK_SRC						23
+#define GCC_GP3_CLK						24
+#define GCC_GP3_CLK_SRC						25
+#define GCC_GPLL0						26
+#define GCC_GPLL0_OUT_EVEN					27
+#define GCC_GPLL1						28
+#define GCC_GPLL4						29
+#define GCC_GPLL7						30
+#define GCC_GPLL9						31
+#define GCC_GPU_CFG_AHB_CLK					32
+#define GCC_GPU_GEMNOC_GFX_CLK					33
+#define GCC_GPU_GPLL0_CLK_SRC					34
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				35
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				36
+#define GCC_QMIP_GPU_AHB_CLK					37
+#define GCC_PCIE_0_AUX_CLK					38
+#define GCC_PCIE_0_AUX_CLK_SRC					39
+#define GCC_PCIE_0_CFG_AHB_CLK					40
+#define GCC_PCIE_0_MSTR_AXI_CLK					41
+#define GCC_PCIE_0_PHY_AUX_CLK					42
+#define GCC_PCIE_0_PHY_AUX_CLK_SRC				43
+#define GCC_PCIE_0_PHY_RCHNG_CLK				44
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				45
+#define GCC_PCIE_0_PIPE_CLK					46
+#define GCC_PCIE_0_PIPE_CLK_SRC					47
+#define GCC_PCIE_0_SLV_AXI_CLK					48
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				49
+#define GCC_PCIE_RSCC_CFG_AHB_CLK				50
+#define GCC_PCIE_RSCC_XO_CLK					51
+#define GCC_PDM2_CLK						52
+#define GCC_PDM2_CLK_SRC					53
+#define GCC_PDM_AHB_CLK						54
+#define GCC_PDM_XO4_CLK						55
+#define GCC_QUPV3_I2C_CORE_CLK					56
+#define GCC_QUPV3_I2C_S0_CLK					57
+#define GCC_QUPV3_I2C_S0_CLK_SRC				58
+#define GCC_QUPV3_I2C_S1_CLK					59
+#define GCC_QUPV3_I2C_S1_CLK_SRC				60
+#define GCC_QUPV3_I2C_S2_CLK					61
+#define GCC_QUPV3_I2C_S2_CLK_SRC				62
+#define GCC_QUPV3_I2C_S3_CLK					63
+#define GCC_QUPV3_I2C_S3_CLK_SRC				64
+#define GCC_QUPV3_I2C_S4_CLK					65
+#define GCC_QUPV3_I2C_S4_CLK_SRC				66
+#define GCC_QUPV3_I2C_S_AHB_CLK					67
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				68
+#define GCC_QUPV3_WRAP1_CORE_CLK				69
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				70
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			71
+#define GCC_QUPV3_WRAP1_S0_CLK					72
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				73
+#define GCC_QUPV3_WRAP1_S1_CLK					74
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				75
+#define GCC_QUPV3_WRAP1_S2_CLK					76
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				77
+#define GCC_QUPV3_WRAP1_S3_CLK					78
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				79
+#define GCC_QUPV3_WRAP1_S4_CLK					80
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				81
+#define GCC_QUPV3_WRAP1_S5_CLK					82
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				83
+#define GCC_QUPV3_WRAP1_S6_CLK					84
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				85
+#define GCC_QUPV3_WRAP1_S7_CLK					86
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				87
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				88
+#define GCC_QUPV3_WRAP2_CORE_CLK				89
+#define GCC_QUPV3_WRAP2_S0_CLK					90
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				91
+#define GCC_QUPV3_WRAP2_S1_CLK					92
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				93
+#define GCC_QUPV3_WRAP2_S2_CLK					94
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				95
+#define GCC_QUPV3_WRAP2_S3_CLK					96
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				97
+#define GCC_QUPV3_WRAP2_S4_CLK					98
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				99
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK				100
+#define GCC_QUPV3_WRAP3_CORE_CLK				101
+#define GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC			102
+#define GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK				103
+#define GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK				104
+#define GCC_QUPV3_WRAP3_S0_CLK					105
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC				106
+#define GCC_QUPV3_WRAP3_S1_CLK					107
+#define GCC_QUPV3_WRAP3_S1_CLK_SRC				108
+#define GCC_QUPV3_WRAP3_S2_CLK					109
+#define GCC_QUPV3_WRAP3_S2_CLK_SRC				110
+#define GCC_QUPV3_WRAP3_S3_CLK					111
+#define GCC_QUPV3_WRAP3_S3_CLK_SRC				112
+#define GCC_QUPV3_WRAP3_S4_CLK					113
+#define GCC_QUPV3_WRAP3_S4_CLK_SRC				114
+#define GCC_QUPV3_WRAP3_S5_CLK					115
+#define GCC_QUPV3_WRAP3_S5_CLK_SRC				116
+#define GCC_QUPV3_WRAP4_CORE_2X_CLK				117
+#define GCC_QUPV3_WRAP4_CORE_CLK				118
+#define GCC_QUPV3_WRAP4_S0_CLK					119
+#define GCC_QUPV3_WRAP4_S0_CLK_SRC				120
+#define GCC_QUPV3_WRAP4_S1_CLK					121
+#define GCC_QUPV3_WRAP4_S1_CLK_SRC				122
+#define GCC_QUPV3_WRAP4_S2_CLK					123
+#define GCC_QUPV3_WRAP4_S2_CLK_SRC				124
+#define GCC_QUPV3_WRAP4_S3_CLK					125
+#define GCC_QUPV3_WRAP4_S3_CLK_SRC				126
+#define GCC_QUPV3_WRAP4_S4_CLK					127
+#define GCC_QUPV3_WRAP4_S4_CLK_SRC				128
+#define GCC_QUPV3_WRAP_1_M_AXI_CLK				129
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				130
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				131
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				132
+#define GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK				133
+#define GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK				134
+#define GCC_QUPV3_WRAP_3_M_AHB_CLK				135
+#define GCC_QUPV3_WRAP_3_S_AHB_CLK				136
+#define GCC_QUPV3_WRAP_4_M_AHB_CLK				137
+#define GCC_QUPV3_WRAP_4_S_AHB_CLK				138
+#define GCC_SDCC2_AHB_CLK					139
+#define GCC_SDCC2_APPS_CLK					140
+#define GCC_SDCC2_APPS_CLK_SRC					141
+#define GCC_SDCC4_AHB_CLK					142
+#define GCC_SDCC4_APPS_CLK					143
+#define GCC_SDCC4_APPS_CLK_SRC					144
+#define GCC_UFS_PHY_AHB_CLK					145
+#define GCC_UFS_PHY_AXI_CLK					146
+#define GCC_UFS_PHY_AXI_CLK_SRC					147
+#define GCC_UFS_PHY_ICE_CORE_CLK				148
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				149
+#define GCC_UFS_PHY_PHY_AUX_CLK					150
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				151
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				152
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				153
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				154
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				155
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				156
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				157
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				158
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				159
+#define GCC_USB30_PRIM_MASTER_CLK				160
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				161
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				162
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			163
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		164
+#define GCC_USB30_PRIM_SLEEP_CLK				165
+#define GCC_USB3_PRIM_PHY_AUX_CLK				166
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				167
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				168
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				169
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				170
+#define GCC_VIDEO_AHB_CLK					171
+#define GCC_VIDEO_AXI0_CLK					172
+#define GCC_VIDEO_AXI1_CLK					173
+#define GCC_VIDEO_XO_CLK					174
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				175
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				176
+#define GCC_QMIP_DISP_DCP_SF_AHB_CLK				177
+#define GCC_QMIP_PCIE_AHB_CLK					178
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				179
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				180
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				181
+#define GCC_DISP_AHB_CLK					182
+
+/* GCC power domains */
+#define GCC_PCIE_0_GDSC						0
+#define GCC_PCIE_0_PHY_GDSC					1
+#define GCC_UFS_MEM_PHY_GDSC					2
+#define GCC_UFS_PHY_GDSC					3
+#define GCC_USB30_PRIM_GDSC					4
+#define GCC_USB3_PHY_GDSC					5
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_EVA_AXI0_CLK_ARES					2
+#define GCC_EVA_AXI0C_CLK_ARES					3
+#define GCC_EVA_BCR						4
+#define GCC_GPU_BCR						5
+#define GCC_PCIE_0_BCR						6
+#define GCC_PCIE_0_LINK_DOWN_BCR				7
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				8
+#define GCC_PCIE_0_PHY_BCR					9
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			10
+#define GCC_PCIE_PHY_BCR					11
+#define GCC_PCIE_PHY_CFG_AHB_BCR				12
+#define GCC_PCIE_PHY_COM_BCR					13
+#define GCC_PCIE_RSCC_BCR					14
+#define GCC_PDM_BCR						15
+#define GCC_QUPV3_WRAPPER_1_BCR					16
+#define GCC_QUPV3_WRAPPER_2_BCR					17
+#define GCC_QUPV3_WRAPPER_3_BCR					18
+#define GCC_QUPV3_WRAPPER_4_BCR					19
+#define GCC_QUPV3_WRAPPER_I2C_BCR				20
+#define GCC_QUSB2PHY_PRIM_BCR					21
+#define GCC_QUSB2PHY_SEC_BCR					22
+#define GCC_SDCC2_BCR						23
+#define GCC_SDCC4_BCR						24
+#define GCC_UFS_PHY_BCR						25
+#define GCC_USB30_PRIM_BCR					26
+#define GCC_USB3_DP_PHY_PRIM_BCR				27
+#define GCC_USB3_DP_PHY_SEC_BCR					28
+#define GCC_USB3_PHY_PRIM_BCR					29
+#define GCC_USB3_PHY_SEC_BCR					30
+#define GCC_USB3PHY_PHY_PRIM_BCR				31
+#define GCC_USB3PHY_PHY_SEC_BCR					32
+#define GCC_VIDEO_AXI0_CLK_ARES					33
+#define GCC_VIDEO_AXI1_CLK_ARES					34
+#define GCC_VIDEO_BCR						35
+#define GCC_VIDEO_XO_CLK_ARES					36
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-sdm660.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h
index f9dbc21cb5c..ee2a89dae72 100644
--- a/include/dt-bindings/clock/qcom,mmcc-sdm660.h
+++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h
@@ -157,6 +157,7 @@
 #define BIMC_SMMU_GDSC							7
 
 #define CAMSS_MICRO_BCR				 0
+#define MDSS_BCR				1
 
 #endif
 
diff --git a/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
index fc1fefe8fd7..1e4e6432d50 100644
--- a/include/dt-bindings/clock/qcom,sm7150-dispcc.h
+++ b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
@@ -53,6 +53,9 @@
 #define DISPCC_SLEEP_CLK			41
 #define DISPCC_SLEEP_CLK_SRC			42
 
+/* DISPCC resets */
+#define DISPCC_MDSS_CORE_BCR			0
+
 /* DISPCC GDSCR */
 #define MDSS_GDSC				0
 
diff --git a/include/dt-bindings/clock/qcom,sm8750-videocc.h b/include/dt-bindings/clock/qcom,sm8750-videocc.h
new file mode 100644
index 00000000000..f3bfa2ba516
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8750-videocc.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK					0
+#define VIDEO_CC_AHB_CLK_SRC					1
+#define VIDEO_CC_MVS0_CLK					2
+#define VIDEO_CC_MVS0_CLK_SRC					3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC				4
+#define VIDEO_CC_MVS0_FREERUN_CLK				5
+#define VIDEO_CC_MVS0_SHIFT_CLK					6
+#define VIDEO_CC_MVS0C_CLK					7
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				8
+#define VIDEO_CC_MVS0C_FREERUN_CLK				9
+#define VIDEO_CC_MVS0C_SHIFT_CLK				10
+#define VIDEO_CC_PLL0						11
+#define VIDEO_CC_SLEEP_CLK					12
+#define VIDEO_CC_SLEEP_CLK_SRC					13
+#define VIDEO_CC_XO_CLK						14
+#define VIDEO_CC_XO_CLK_SRC					15
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC					0
+#define VIDEO_CC_MVS0C_GDSC					1
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR					0
+#define VIDEO_CC_MVS0_BCR					1
+#define VIDEO_CC_MVS0C_CLK_ARES					2
+#define VIDEO_CC_MVS0C_BCR					3
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES				4
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES				5
+#define VIDEO_CC_XO_CLK_ARES					6
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,x1e80100-dispcc.h b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h
index d4a83e4fd0d..49b3a9e5ce4 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-dispcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h
@@ -90,6 +90,9 @@
 #define DISP_CC_MDSS_CORE_BCR					0
 #define DISP_CC_MDSS_CORE_INT2_BCR				1
 #define DISP_CC_MDSS_RSCC_BCR					2
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK_ARES	3
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK_ARES	4
+#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK_ARES	5
 
 /* DISP_CC GDSCR */
 #define MDSS_GDSC						0
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 710c340f24a..62aa1242559 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -363,6 +363,30 @@
 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				353
 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				354
 #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC				355
+#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC				356
+#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC				357
+#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC				358
+#define GCC_USB4_0_PHY_DP0_CLK_SRC				359
+#define GCC_USB4_0_PHY_DP1_CLK_SRC				360
+#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC			361
+#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC			362
+#define GCC_USB4_0_PHY_RX0_CLK_SRC				363
+#define GCC_USB4_0_PHY_RX1_CLK_SRC				364
+#define GCC_USB4_0_PHY_SYS_CLK_SRC				365
+#define GCC_USB4_1_PHY_DP0_CLK_SRC				366
+#define GCC_USB4_1_PHY_DP1_CLK_SRC				367
+#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC			368
+#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC			369
+#define GCC_USB4_1_PHY_RX0_CLK_SRC				370
+#define GCC_USB4_1_PHY_RX1_CLK_SRC				371
+#define GCC_USB4_1_PHY_SYS_CLK_SRC				372
+#define GCC_USB4_2_PHY_DP0_CLK_SRC				373
+#define GCC_USB4_2_PHY_DP1_CLK_SRC				374
+#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC			375
+#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC			376
+#define GCC_USB4_2_PHY_RX0_CLK_SRC				377
+#define GCC_USB4_2_PHY_RX1_CLK_SRC				378
+#define GCC_USB4_2_PHY_SYS_CLK_SRC				379
 
 /* GCC power domains */
 #define GCC_PCIE_0_TUNNEL_GDSC					0
@@ -484,4 +508,41 @@
 #define GCC_VIDEO_BCR						87
 #define GCC_VIDEO_AXI0_CLK_ARES					88
 #define GCC_VIDEO_AXI1_CLK_ARES					89
+#define GCC_USB4_0_MISC_USB4_SYS_BCR				90
+#define GCC_USB4_0_MISC_RX_CLK_0_BCR				91
+#define GCC_USB4_0_MISC_RX_CLK_1_BCR				92
+#define GCC_USB4_0_MISC_USB_PIPE_BCR				93
+#define GCC_USB4_0_MISC_PCIE_PIPE_BCR				94
+#define GCC_USB4_0_MISC_TMU_BCR					95
+#define GCC_USB4_0_MISC_SB_IF_BCR				96
+#define GCC_USB4_0_MISC_HIA_MSTR_BCR				97
+#define GCC_USB4_0_MISC_AHB_BCR					98
+#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR			99
+#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR			100
+#define GCC_USB4_1_MISC_USB4_SYS_BCR				101
+#define GCC_USB4_1_MISC_RX_CLK_0_BCR				102
+#define GCC_USB4_1_MISC_RX_CLK_1_BCR				103
+#define GCC_USB4_1_MISC_USB_PIPE_BCR				104
+#define GCC_USB4_1_MISC_PCIE_PIPE_BCR				105
+#define GCC_USB4_1_MISC_TMU_BCR					106
+#define GCC_USB4_1_MISC_SB_IF_BCR				107
+#define GCC_USB4_1_MISC_HIA_MSTR_BCR				108
+#define GCC_USB4_1_MISC_AHB_BCR					109
+#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR			110
+#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR			111
+#define GCC_USB4_2_MISC_USB4_SYS_BCR				112
+#define GCC_USB4_2_MISC_RX_CLK_0_BCR				113
+#define GCC_USB4_2_MISC_RX_CLK_1_BCR				114
+#define GCC_USB4_2_MISC_USB_PIPE_BCR				115
+#define GCC_USB4_2_MISC_PCIE_PIPE_BCR				116
+#define GCC_USB4_2_MISC_TMU_BCR					117
+#define GCC_USB4_2_MISC_SB_IF_BCR				118
+#define GCC_USB4_2_MISC_HIA_MSTR_BCR				119
+#define GCC_USB4_2_MISC_AHB_BCR					120
+#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR			121
+#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR			122
+#define GCC_USB4PHY_PHY_PRIM_BCR				123
+#define GCC_USB4PHY_PHY_SEC_BCR					124
+#define GCC_USB4PHY_PHY_TERT_BCR				125
+
 #endif
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
index f1d737ca7ca..124a6b8856d 100644
--- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -51,5 +51,6 @@
 #define R8A779A0_CLK_CBFUSA		40
 #define R8A779A0_CLK_R			41
 #define R8A779A0_CLK_OSC		42
+#define R8A779A0_CLK_ZG			43
 
 #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index f165df8a6f5..dab24740de3 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -22,5 +22,7 @@
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
 #define R9A09G047_USB3_0_REF_ALT_CLK_P		12
 #define R9A09G047_USB3_0_CLKCORE		13
+#define R9A09G047_USB2_0_CLK_CORE0		14
+#define R9A09G047_USB2_0_CLK_CORE1		15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
index a9af5af9e3a..234dcf4f0f9 100644
--- a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
@@ -21,5 +21,7 @@
 #define R9A09G056_GBETH_0_CLK_PTP_REF_I		10
 #define R9A09G056_GBETH_1_CLK_PTP_REF_I		11
 #define R9A09G056_SPI_CLK_SPI			12
+#define R9A09G056_USB3_0_REF_ALT_CLK_P		13
+#define R9A09G056_USB3_0_CLKCORE		14
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
index 5346a898ab6..f91d7f72922 100644
--- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -22,5 +22,9 @@
 #define R9A09G057_GBETH_0_CLK_PTP_REF_I		11
 #define R9A09G057_GBETH_1_CLK_PTP_REF_I		12
 #define R9A09G057_SPI_CLK_SPI			13
+#define R9A09G057_USB3_0_REF_ALT_CLK_P		14
+#define R9A09G057_USB3_0_CLKCORE		15
+#define R9A09G057_USB3_1_REF_ALT_CLK_P		16
+#define R9A09G057_USB3_1_CLKCORE		17
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
index 5263085c5b2..1e0aef8a645 100644
--- a/include/dt-bindings/clock/rk3568-cru.h
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -483,7 +483,11 @@
 
 #define PCLK_CORE_PVTM		450
 
-#define CLK_NR_CLKS		(PCLK_CORE_PVTM + 1)
+/* scmi-clocks indices */
+
+#define SCMI_CLK_CPU		0
+#define SCMI_CLK_GPU		1
+#define SCMI_CLK_NPU		2
 
 /* pmu soft-reset indices */
 /* pmucru_softrst_con0 */
diff --git a/include/dt-bindings/clock/rockchip,rk3506-cru.h b/include/dt-bindings/clock/rockchip,rk3506-cru.h
new file mode 100644
index 00000000000..71d7dda23cc
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3506-cru.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
+
+/* cru plls */
+#define PLL_GPLL			0
+#define PLL_V0PLL			1
+#define PLL_V1PLL			2
+
+/* cru-clocks indices */
+#define ARMCLK				3
+#define CLK_DDR				4
+#define XIN24M_GATE			5
+#define CLK_GPLL_GATE			6
+#define CLK_V0PLL_GATE			7
+#define CLK_V1PLL_GATE			8
+#define CLK_GPLL_DIV			9
+#define CLK_GPLL_DIV_100M		10
+#define CLK_V0PLL_DIV			11
+#define CLK_V1PLL_DIV			12
+#define CLK_INT_VOICE_MATRIX0		13
+#define CLK_INT_VOICE_MATRIX1		14
+#define CLK_INT_VOICE_MATRIX2		15
+#define CLK_FRAC_UART_MATRIX0_MUX	16
+#define CLK_FRAC_UART_MATRIX1_MUX	17
+#define CLK_FRAC_VOICE_MATRIX0_MUX	18
+#define CLK_FRAC_VOICE_MATRIX1_MUX	19
+#define CLK_FRAC_COMMON_MATRIX0_MUX	20
+#define CLK_FRAC_COMMON_MATRIX1_MUX	21
+#define CLK_FRAC_COMMON_MATRIX2_MUX	22
+#define CLK_FRAC_UART_MATRIX0		23
+#define CLK_FRAC_UART_MATRIX1		24
+#define CLK_FRAC_VOICE_MATRIX0		25
+#define CLK_FRAC_VOICE_MATRIX1		26
+#define CLK_FRAC_COMMON_MATRIX0		27
+#define CLK_FRAC_COMMON_MATRIX1		28
+#define CLK_FRAC_COMMON_MATRIX2		29
+#define CLK_REF_USBPHY_TOP		30
+#define CLK_REF_DPHY_TOP		31
+#define ACLK_CORE_ROOT			32
+#define PCLK_CORE_ROOT			33
+#define PCLK_DBG			34
+#define PCLK_CORE_GRF			35
+#define PCLK_CORE_CRU			36
+#define CLK_CORE_EMA_DETECT		37
+#define CLK_REF_PVTPLL_CORE		38
+#define PCLK_GPIO1			39
+#define DBCLK_GPIO1			40
+#define ACLK_CORE_PERI_ROOT		41
+#define HCLK_CORE_PERI_ROOT		42
+#define PCLK_CORE_PERI_ROOT		43
+#define CLK_DSMC			44
+#define ACLK_DSMC			45
+#define PCLK_DSMC			46
+#define CLK_FLEXBUS_TX			47
+#define CLK_FLEXBUS_RX			48
+#define ACLK_FLEXBUS			49
+#define HCLK_FLEXBUS			50
+#define ACLK_DSMC_SLV			51
+#define HCLK_DSMC_SLV			52
+#define ACLK_BUS_ROOT			53
+#define HCLK_BUS_ROOT			54
+#define PCLK_BUS_ROOT			55
+#define ACLK_SYSRAM			56
+#define HCLK_SYSRAM			57
+#define ACLK_DMAC0			58
+#define ACLK_DMAC1			59
+#define HCLK_M0				60
+#define PCLK_BUS_GRF			61
+#define PCLK_TIMER			62
+#define CLK_TIMER0_CH0			63
+#define CLK_TIMER0_CH1			64
+#define CLK_TIMER0_CH2			65
+#define CLK_TIMER0_CH3			66
+#define CLK_TIMER0_CH4			67
+#define CLK_TIMER0_CH5			68
+#define PCLK_WDT0			69
+#define TCLK_WDT0			70
+#define PCLK_WDT1			71
+#define TCLK_WDT1			72
+#define PCLK_MAILBOX			73
+#define PCLK_INTMUX			74
+#define PCLK_SPINLOCK			75
+#define PCLK_DDRC			76
+#define HCLK_DDRPHY			77
+#define PCLK_DDRMON			78
+#define CLK_DDRMON_OSC			79
+#define PCLK_STDBY			80
+#define HCLK_USBOTG0			81
+#define HCLK_USBOTG0_PMU		82
+#define CLK_USBOTG0_ADP			83
+#define HCLK_USBOTG1			84
+#define HCLK_USBOTG1_PMU		85
+#define CLK_USBOTG1_ADP			86
+#define PCLK_USBPHY			87
+#define ACLK_DMA2DDR			88
+#define PCLK_DMA2DDR			89
+#define STCLK_M0			90
+#define CLK_DDRPHY			91
+#define CLK_DDRC_SRC			92
+#define ACLK_DDRC_0			93
+#define ACLK_DDRC_1			94
+#define CLK_DDRC			95
+#define CLK_DDRMON			96
+#define HCLK_LSPERI_ROOT		97
+#define PCLK_LSPERI_ROOT		98
+#define PCLK_UART0			99
+#define PCLK_UART1			100
+#define PCLK_UART2			101
+#define PCLK_UART3			102
+#define PCLK_UART4			103
+#define SCLK_UART0			104
+#define SCLK_UART1			105
+#define SCLK_UART2			106
+#define SCLK_UART3			107
+#define SCLK_UART4			108
+#define PCLK_I2C0			109
+#define CLK_I2C0			110
+#define PCLK_I2C1			111
+#define CLK_I2C1			112
+#define PCLK_I2C2			113
+#define CLK_I2C2			114
+#define PCLK_PWM1			115
+#define CLK_PWM1			116
+#define CLK_OSC_PWM1			117
+#define CLK_RC_PWM1			118
+#define CLK_FREQ_PWM1			119
+#define CLK_COUNTER_PWM1		120
+#define PCLK_SPI0			121
+#define CLK_SPI0			122
+#define PCLK_SPI1			123
+#define CLK_SPI1			124
+#define PCLK_GPIO2			125
+#define DBCLK_GPIO2			126
+#define PCLK_GPIO3			127
+#define DBCLK_GPIO3			128
+#define PCLK_GPIO4			129
+#define DBCLK_GPIO4			130
+#define HCLK_CAN0			131
+#define CLK_CAN0			132
+#define HCLK_CAN1			133
+#define CLK_CAN1			134
+#define HCLK_PDM			135
+#define MCLK_PDM			136
+#define CLKOUT_PDM			137
+#define MCLK_SPDIFTX			138
+#define HCLK_SPDIFTX			139
+#define HCLK_SPDIFRX			140
+#define MCLK_SPDIFRX			141
+#define MCLK_SAI0			142
+#define HCLK_SAI0			143
+#define MCLK_OUT_SAI0			144
+#define MCLK_SAI1			145
+#define HCLK_SAI1			146
+#define MCLK_OUT_SAI1			147
+#define HCLK_ASRC0			148
+#define CLK_ASRC0			149
+#define HCLK_ASRC1			150
+#define CLK_ASRC1			151
+#define PCLK_CRU			152
+#define PCLK_PMU_ROOT			153
+#define MCLK_ASRC0			154
+#define MCLK_ASRC1			155
+#define MCLK_ASRC2			156
+#define MCLK_ASRC3			157
+#define LRCK_ASRC0_SRC			158
+#define LRCK_ASRC0_DST			159
+#define LRCK_ASRC1_SRC			160
+#define LRCK_ASRC1_DST			161
+#define ACLK_HSPERI_ROOT		162
+#define HCLK_HSPERI_ROOT		163
+#define PCLK_HSPERI_ROOT		164
+#define CCLK_SRC_SDMMC			165
+#define HCLK_SDMMC			166
+#define HCLK_FSPI			167
+#define SCLK_FSPI			168
+#define PCLK_SPI2			169
+#define ACLK_MAC0			170
+#define ACLK_MAC1			171
+#define PCLK_MAC0			172
+#define PCLK_MAC1			173
+#define CLK_MAC_ROOT			174
+#define CLK_MAC0			175
+#define CLK_MAC1			176
+#define MCLK_SAI2			177
+#define HCLK_SAI2			178
+#define MCLK_OUT_SAI2			179
+#define MCLK_SAI3_SRC			180
+#define HCLK_SAI3			181
+#define MCLK_SAI3			182
+#define MCLK_OUT_SAI3			183
+#define MCLK_SAI4_SRC			184
+#define HCLK_SAI4			185
+#define MCLK_SAI4			186
+#define HCLK_DSM			187
+#define MCLK_DSM			188
+#define PCLK_AUDIO_ADC			189
+#define MCLK_AUDIO_ADC			190
+#define MCLK_AUDIO_ADC_DIV4		191
+#define PCLK_SARADC			192
+#define CLK_SARADC			193
+#define PCLK_OTPC_NS			194
+#define CLK_SBPI_OTPC_NS		195
+#define CLK_USER_OTPC_NS		196
+#define PCLK_UART5			197
+#define SCLK_UART5			198
+#define PCLK_GPIO234_IOC		199
+#define CLK_MAC_PTP_ROOT		200
+#define CLK_MAC0_PTP			201
+#define CLK_MAC1_PTP			202
+#define CLK_SPI2			203
+#define ACLK_VIO_ROOT			204
+#define HCLK_VIO_ROOT			205
+#define PCLK_VIO_ROOT			206
+#define HCLK_RGA			207
+#define ACLK_RGA			208
+#define CLK_CORE_RGA			209
+#define ACLK_VOP			210
+#define HCLK_VOP			211
+#define DCLK_VOP			212
+#define PCLK_DPHY			213
+#define PCLK_DSI_HOST			214
+#define PCLK_TSADC			215
+#define CLK_TSADC			216
+#define CLK_TSADC_TSEN			217
+#define PCLK_GPIO1_IOC			218
+#define PCLK_OTPC_S			219
+#define CLK_SBPI_OTPC_S			220
+#define CLK_USER_OTPC_S			221
+#define PCLK_OTP_MASK			222
+#define PCLK_KEYREADER			223
+#define HCLK_BOOTROM			224
+#define PCLK_DDR_SERVICE		225
+#define HCLK_CRYPTO_S			226
+#define HCLK_KEYLAD			227
+#define CLK_CORE_CRYPTO			228
+#define CLK_PKA_CRYPTO			229
+#define CLK_CORE_CRYPTO_S		230
+#define CLK_PKA_CRYPTO_S		231
+#define ACLK_CRYPTO_S			232
+#define HCLK_RNG_S			233
+#define CLK_CORE_CRYPTO_NS		234
+#define CLK_PKA_CRYPTO_NS		235
+#define ACLK_CRYPTO_NS			236
+#define HCLK_CRYPTO_NS			237
+#define HCLK_RNG			238
+#define CLK_PMU				239
+#define PCLK_PMU			240
+#define CLK_PMU_32K			241
+#define PCLK_PMU_CRU			242
+#define PCLK_PMU_GRF			243
+#define PCLK_GPIO0_IOC			244
+#define PCLK_GPIO0			245
+#define DBCLK_GPIO0			246
+#define PCLK_GPIO1_SHADOW		247
+#define DBCLK_GPIO1_SHADOW		248
+#define PCLK_PMU_HP_TIMER		249
+#define CLK_PMU_HP_TIMER		250
+#define CLK_PMU_HP_TIMER_32K		251
+#define PCLK_PWM0			252
+#define CLK_PWM0			253
+#define CLK_OSC_PWM0			254
+#define CLK_RC_PWM0			255
+#define CLK_MAC_OUT			256
+#define CLK_REF_OUT0			257
+#define CLK_REF_OUT1			258
+#define CLK_32K_FRAC			259
+#define CLK_32K_RC			260
+#define CLK_32K				261
+#define CLK_32K_PMU			262
+#define PCLK_TOUCH_KEY			263
+#define CLK_TOUCH_KEY			264
+#define CLK_REF_PHY_PLL			265
+#define CLK_REF_PHY_PMU_MUX		266
+#define CLK_WIFI_OUT			267
+#define CLK_V0PLL_REF			268
+#define CLK_V1PLL_REF			269
+#define CLK_32K_FRAC_MUX		270
+
+#endif
diff --git a/include/dt-bindings/clock/rockchip,rv1126b-cru.h b/include/dt-bindings/clock/rockchip,rv1126b-cru.h
new file mode 100644
index 00000000000..721d50a1419
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1126b-cru.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
+
+/* pll clocks */
+#define PLL_GPLL				0
+#define PLL_CPLL				1
+#define PLL_AUPLL				2
+#define ARMCLK					3
+#define SCLK_DDR				4
+
+/* clk (clocks) */
+#define CLK_CPLL_DIV20				5
+#define CLK_CPLL_DIV10				6
+#define CLK_CPLL_DIV8				7
+#define CLK_GPLL_DIV8				8
+#define CLK_GPLL_DIV6				9
+#define CLK_GPLL_DIV4				10
+#define CLK_CPLL_DIV3				11
+#define CLK_GPLL_DIV3				12
+#define CLK_CPLL_DIV2				13
+#define CLK_GPLL_DIV2				14
+#define CLK_CM_FRAC0				15
+#define CLK_CM_FRAC1				16
+#define CLK_CM_FRAC2				17
+#define CLK_UART_FRAC0				18
+#define CLK_UART_FRAC1				19
+#define CLK_AUDIO_FRAC0				20
+#define CLK_AUDIO_FRAC1				21
+#define CLK_AUDIO_INT0				22
+#define CLK_AUDIO_INT1				23
+#define SCLK_UART0_SRC				24
+#define SCLK_UART1				25
+#define SCLK_UART2				26
+#define SCLK_UART3				27
+#define SCLK_UART4				28
+#define SCLK_UART5				29
+#define SCLK_UART6				30
+#define SCLK_UART7				31
+#define MCLK_SAI0				32
+#define MCLK_SAI1				33
+#define MCLK_SAI2				34
+#define MCLK_PDM				35
+#define CLKOUT_PDM				36
+#define MCLK_ASRC0				37
+#define MCLK_ASRC1				38
+#define MCLK_ASRC2				39
+#define MCLK_ASRC3				40
+#define CLK_ASRC0				41
+#define CLK_ASRC1				42
+#define CLK_CORE_PLL				43
+#define CLK_NPU_PLL				44
+#define CLK_VEPU_PLL				45
+#define CLK_ISP_PLL				46
+#define CLK_AISP_PLL				47
+#define CLK_SARADC0_SRC				48
+#define CLK_SARADC1_SRC				49
+#define CLK_SARADC2_SRC				50
+#define HCLK_NPU_ROOT				51
+#define PCLK_NPU_ROOT				52
+#define ACLK_VEPU_ROOT				53
+#define HCLK_VEPU_ROOT				54
+#define PCLK_VEPU_ROOT				55
+#define CLK_CORE_RGA_SRC			56
+#define ACLK_GMAC_ROOT				57
+#define ACLK_VI_ROOT				58
+#define HCLK_VI_ROOT				59
+#define PCLK_VI_ROOT				60
+#define DCLK_VICAP_ROOT				61
+#define CLK_SYS_DSMC_ROOT			62
+#define ACLK_VDO_ROOT				63
+#define ACLK_RKVDEC_ROOT			64
+#define HCLK_VDO_ROOT				65
+#define PCLK_VDO_ROOT				66
+#define DCLK_OOC_SRC				67
+#define DCLK_VOP				68
+#define DCLK_DECOM_SRC				69
+#define PCLK_DDR_ROOT				70
+#define ACLK_SYSMEM_SRC				71
+#define ACLK_TOP_ROOT				72
+#define ACLK_BUS_ROOT				73
+#define HCLK_BUS_ROOT				74
+#define PCLK_BUS_ROOT				75
+#define CCLK_SDMMC0				76
+#define CCLK_SDMMC1				77
+#define CCLK_EMMC				78
+#define SCLK_2X_FSPI0				79
+#define CLK_GMAC_PTP_REF_SRC			80
+#define CLK_GMAC_125M				81
+#define CLK_TIMER_ROOT				82
+#define TCLK_WDT_NS_SRC				83
+#define TCLK_WDT_S_SRC				84
+#define TCLK_WDT_HPMCU				85
+#define CLK_CAN0				86
+#define CLK_CAN1				87
+#define PCLK_PERI_ROOT				88
+#define ACLK_PERI_ROOT				89
+#define CLK_I2C_BUS_SRC				90
+#define CLK_SPI0				91
+#define CLK_SPI1				92
+#define BUSCLK_PMU_SRC				93
+#define CLK_PWM0				94
+#define CLK_PWM2				95
+#define CLK_PWM3				96
+#define CLK_PKA_RKCE_SRC			97
+#define ACLK_RKCE_SRC				98
+#define ACLK_VCP_ROOT				99
+#define HCLK_VCP_ROOT				100
+#define PCLK_VCP_ROOT				101
+#define CLK_CORE_FEC_SRC			102
+#define CLK_CORE_AVSP_SRC			103
+#define CLK_50M_GMAC_IOBUF_VI			104
+#define PCLK_TOP_ROOT				105
+#define CLK_MIPI0_OUT2IO			106
+#define CLK_MIPI1_OUT2IO			107
+#define CLK_MIPI2_OUT2IO			108
+#define CLK_MIPI3_OUT2IO			109
+#define CLK_CIF_OUT2IO				110
+#define CLK_MAC_OUT2IO				111
+#define MCLK_SAI0_OUT2IO			112
+#define MCLK_SAI1_OUT2IO			113
+#define MCLK_SAI2_OUT2IO			114
+#define CLK_CM_FRAC0_SRC			115
+#define CLK_CM_FRAC1_SRC			116
+#define CLK_CM_FRAC2_SRC			117
+#define CLK_UART_FRAC0_SRC			118
+#define CLK_UART_FRAC1_SRC			119
+#define CLK_AUDIO_FRAC0_SRC			120
+#define CLK_AUDIO_FRAC1_SRC			121
+#define ACLK_NPU_ROOT				122
+#define HCLK_RKNN				123
+#define ACLK_RKNN				124
+#define PCLK_GPIO3				125
+#define DBCLK_GPIO3				126
+#define PCLK_IOC_VCCIO3				127
+#define PCLK_SARADC0				128
+#define CLK_SARADC0				129
+#define HCLK_SDMMC1				130
+#define HCLK_VEPU				131
+#define ACLK_VEPU				132
+#define CLK_CORE_VEPU				133
+#define HCLK_FEC				134
+#define ACLK_FEC				135
+#define CLK_CORE_FEC				136
+#define HCLK_AVSP				137
+#define ACLK_AVSP				138
+#define BUSCLK_PMU1_ROOT			139
+#define HCLK_AISP				140
+#define ACLK_AISP				141
+#define CLK_CORE_AISP				142
+#define CLK_CORE_ISP_ROOT			143
+#define PCLK_DSMC				144
+#define ACLK_DSMC				145
+#define HCLK_CAN0				146
+#define HCLK_CAN1				147
+#define PCLK_GPIO2				148
+#define DBCLK_GPIO2				149
+#define PCLK_GPIO4				150
+#define DBCLK_GPIO4				151
+#define PCLK_GPIO5				152
+#define DBCLK_GPIO5				153
+#define PCLK_GPIO6				154
+#define DBCLK_GPIO6				155
+#define PCLK_GPIO7				156
+#define DBCLK_GPIO7				157
+#define PCLK_IOC_VCCIO2				158
+#define PCLK_IOC_VCCIO4				159
+#define PCLK_IOC_VCCIO5				160
+#define PCLK_IOC_VCCIO6				161
+#define PCLK_IOC_VCCIO7				162
+#define HCLK_ISP				163
+#define ACLK_ISP				164
+#define CLK_CORE_ISP				165
+#define HCLK_VICAP				166
+#define ACLK_VICAP				167
+#define DCLK_VICAP				168
+#define ISP0CLK_VICAP				169
+#define HCLK_VPSS				170
+#define ACLK_VPSS				171
+#define CLK_CORE_VPSS				172
+#define PCLK_CSI2HOST0				173
+#define DCLK_CSI2HOST0				174
+#define PCLK_CSI2HOST1				175
+#define DCLK_CSI2HOST1				176
+#define PCLK_CSI2HOST2				177
+#define DCLK_CSI2HOST2				178
+#define PCLK_CSI2HOST3				179
+#define DCLK_CSI2HOST3				180
+#define HCLK_SDMMC0				181
+#define ACLK_GMAC				182
+#define PCLK_GMAC				183
+#define CLK_GMAC_PTP_REF			184
+#define PCLK_CSIPHY0				185
+#define PCLK_CSIPHY1				186
+#define PCLK_MACPHY				187
+#define PCLK_SARADC1				188
+#define CLK_SARADC1				189
+#define PCLK_SARADC2				190
+#define CLK_SARADC2				191
+#define ACLK_RKVDEC				192
+#define HCLK_RKVDEC				193
+#define CLK_HEVC_CA_RKVDEC			194
+#define ACLK_VOP				195
+#define HCLK_VOP				196
+#define HCLK_RKJPEG				197
+#define ACLK_RKJPEG				198
+#define ACLK_RKMMU_DECOM			199
+#define HCLK_RKMMU_DECOM			200
+#define DCLK_DECOM				201
+#define ACLK_DECOM				202
+#define PCLK_DECOM				203
+#define PCLK_MIPI_DSI				204
+#define PCLK_DSIPHY				205
+#define ACLK_OOC				206
+#define ACLK_SYSMEM				207
+#define PCLK_DDRC				208
+#define PCLK_DDRMON				209
+#define CLK_TIMER_DDRMON			210
+#define PCLK_DFICTRL				211
+#define PCLK_DDRPHY				212
+#define PCLK_DMA2DDR				213
+#define CLK_RCOSC_SRC				214
+#define BUSCLK_PMU_MUX				215
+#define BUSCLK_PMU_ROOT				216
+#define PCLK_PMU				217
+#define CLK_XIN_RC_DIV				218
+#define CLK_32K					219
+#define PCLK_PMU_GPIO0				220
+#define DBCLK_PMU_GPIO0				221
+#define PCLK_PMU_HP_TIMER			222
+#define CLK_PMU_HP_TIMER			223
+#define CLK_PMU_32K_HP_TIMER			224
+#define PCLK_PWM1				225
+#define CLK_PWM1				226
+#define CLK_OSC_PWM1				227
+#define CLK_RC_PWM1				228
+#define CLK_FREQ_PWM1				229
+#define CLK_COUNTER_PWM1			230
+#define PCLK_I2C2				231
+#define CLK_I2C2				232
+#define PCLK_UART0				233
+#define SCLK_UART0				234
+#define PCLK_RCOSC_CTRL				235
+#define CLK_OSC_RCOSC_CTRL			236
+#define CLK_REF_RCOSC_CTRL			237
+#define PCLK_IOC_PMUIO0				238
+#define CLK_REFOUT				239
+#define CLK_PREROLL				240
+#define CLK_PREROLL_32K				241
+#define HCLK_PMU_SRAM				242
+#define PCLK_WDT_LPMCU				243
+#define TCLK_WDT_LPMCU				244
+#define CLK_LPMCU				245
+#define CLK_LPMCU_RTC				246
+#define PCLK_LPMCU_MAILBOX			247
+#define HCLK_OOC				248
+#define PCLK_SPI2AHB				249
+#define HCLK_SPI2AHB				250
+#define HCLK_FSPI1				251
+#define HCLK_XIP_FSPI1				252
+#define SCLK_1X_FSPI1				253
+#define PCLK_IOC_PMUIO1				254
+#define PCLK_AUDIO_ADC_PMU			255
+#define MCLK_AUDIO_ADC_PMU			256
+#define MCLK_AUDIO_ADC_DIV4_PMU			257
+#define MCLK_LPSAI				258
+#define ACLK_GIC400				259
+#define PCLK_WDT_NS				260
+#define TCLK_WDT_NS				261
+#define PCLK_WDT_HPMCU				262
+#define HCLK_CACHE				263
+#define PCLK_HPMCU_MAILBOX			264
+#define PCLK_HPMCU_INTMUX			265
+#define CLK_HPMCU				266
+#define CLK_HPMCU_RTC				267
+#define PCLK_RKDMA				268
+#define ACLK_RKDMA				269
+#define PCLK_DCF				270
+#define ACLK_DCF				271
+#define HCLK_RGA				272
+#define ACLK_RGA				273
+#define CLK_CORE_RGA				274
+#define PCLK_TIMER				275
+#define CLK_TIMER0				276
+#define CLK_TIMER1				277
+#define CLK_TIMER2				278
+#define CLK_TIMER3				279
+#define CLK_TIMER4				280
+#define CLK_TIMER5				281
+#define PCLK_I2C0				282
+#define CLK_I2C0				283
+#define PCLK_I2C1				284
+#define CLK_I2C1				285
+#define PCLK_I2C3				286
+#define CLK_I2C3				287
+#define PCLK_I2C4				288
+#define CLK_I2C4				289
+#define PCLK_I2C5				290
+#define CLK_I2C5				291
+#define PCLK_SPI0				292
+#define PCLK_SPI1				293
+#define PCLK_PWM0				294
+#define CLK_OSC_PWM0				295
+#define CLK_RC_PWM0				296
+#define PCLK_PWM2				297
+#define CLK_OSC_PWM2				298
+#define CLK_RC_PWM2				299
+#define PCLK_PWM3				300
+#define CLK_OSC_PWM3				301
+#define CLK_RC_PWM3				302
+#define PCLK_UART1				303
+#define PCLK_UART2				304
+#define PCLK_UART3				305
+#define PCLK_UART4				306
+#define PCLK_UART5				307
+#define PCLK_UART6				308
+#define PCLK_UART7				309
+#define PCLK_TSADC				310
+#define CLK_TSADC				311
+#define HCLK_SAI0				312
+#define HCLK_SAI1				313
+#define HCLK_SAI2				314
+#define HCLK_RKDSM				315
+#define MCLK_RKDSM				316
+#define HCLK_PDM				317
+#define HCLK_ASRC0				318
+#define HCLK_ASRC1				319
+#define PCLK_AUDIO_ADC_BUS			320
+#define MCLK_AUDIO_ADC_BUS			321
+#define MCLK_AUDIO_ADC_DIV4_BUS			322
+#define PCLK_RKCE				323
+#define HCLK_NS_RKCE				324
+#define PCLK_OTPC_NS				325
+#define CLK_SBPI_OTPC_NS			326
+#define CLK_USER_OTPC_NS			327
+#define CLK_OTPC_ARB				328
+#define PCLK_OTP_MASK				329
+#define CLK_TSADC_PHYCTRL			330
+#define LRCK_SRC_ASRC0				331
+#define LRCK_DST_ASRC0				332
+#define LRCK_SRC_ASRC1				333
+#define LRCK_DST_ASRC1				334
+#define PCLK_KEY_READER				335
+#define ACLK_NSRKCE				336
+#define CLK_PKA_NSRKCE				337
+#define PCLK_RTC_ROOT				338
+#define PCLK_GPIO1				339
+#define DBCLK_GPIO1				340
+#define PCLK_IOC_VCCIO1				341
+#define ACLK_USB3OTG				342
+#define CLK_REF_USB3OTG				343
+#define CLK_SUSPEND_USB3OTG			344
+#define HCLK_USB2HOST				345
+#define HCLK_ARB_USB2HOST			346
+#define PCLK_RTC_TEST				347
+#define HCLK_EMMC				348
+#define HCLK_FSPI0				349
+#define HCLK_XIP_FSPI0				350
+#define PCLK_PIPEPHY				351
+#define PCLK_USB2PHY				352
+#define CLK_REF_PIPEPHY_CPLL_SRC		353
+#define CLK_REF_PIPEPHY				354
+#define HCLK_VPSL				355
+#define ACLK_VPSL				356
+#define CLK_CORE_VPSL				357
+#define CLK_MACPHY				358
+#define HCLK_RKRNG_NS				359
+#define HCLK_RKRNG_S_NS				360
+#define CLK_AISP_PLL_SRC			361
+
+/* secure clks */
+#define CLK_USER_OTPC_S				362
+#define CLK_SBPI_OTPC_S				363
+#define PCLK_OTPC_S				364
+#define PCLK_KEY_READER_S			365
+#define HCLK_KL_RKCE_S				366
+#define HCLK_RKCE_S				367
+#define PCLK_WDT_S				368
+#define TCLK_WDT_S				369
+#define CLK_STIMER0				370
+#define CLK_STIMER1				371
+#define PLK_STIMER				372
+#define HCLK_RKRNG_S				373
+#define CLK_PKA_RKCE_S				374
+#define ACLK_RKCE_S				375
+
+#endif
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 93e6233d135..970d05167fc 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -295,4 +295,14 @@
 #define CLK_DOUT_HSI2_ETHERNET          6
 #define CLK_DOUT_HSI2_ETHERNET_PTP      7
 
+/* CMU_M2M */
+#define CLK_MOUT_M2M_JPEG_USER          1
+#define CLK_MOUT_M2M_NOC_USER           2
+#define CLK_DOUT_M2M_NOCP               3
+
+/* CMU_MFC */
+#define CLK_MOUT_MFC_MFC_USER           1
+#define CLK_MOUT_MFC_WFD_USER           2
+#define CLK_DOUT_MFC_NOCP               3
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
diff --git a/include/dt-bindings/clock/toshiba,tmpv770x.h b/include/dt-bindings/clock/toshiba,tmpv770x.h
index 5fce713001f..a36c8926668 100644
--- a/include/dt-bindings/clock/toshiba,tmpv770x.h
+++ b/include/dt-bindings/clock/toshiba,tmpv770x.h
@@ -11,7 +11,6 @@
 #define TMPV770X_PLL_PIDDRCPLL		4
 #define TMPV770X_PLL_PIVOIFPLL		5
 #define TMPV770X_PLL_PIIMGERPLL		6
-#define TMPV770X_NR_PLL		7
 
 /* Clocks */
 #define TMPV770X_CLK_PIPLL1_DIV1	0
@@ -141,7 +140,9 @@
 #define TMPV770X_CLK_PIREFCLK		124
 #define TMPV770X_CLK_SBUS		125
 #define TMPV770X_CLK_BUSLCK		126
-#define TMPV770X_NR_CLK			127
+#define TMPV770X_CLK_VIIFBS1_L2ISP	127
+#define TMPV770X_CLK_VIIFBS1_L1ISP	128
+#define TMPV770X_CLK_VIIFBS1_PROC	129
 
 /* Reset */
 #define TMPV770X_RESET_PIETHER_2P5M	0
@@ -176,6 +177,13 @@
 #define TMPV770X_RESET_PIPCMIF		29
 #define TMPV770X_RESET_PICKMON		30
 #define TMPV770X_RESET_SBUSCLK		31
-#define TMPV770X_NR_RESET		32
+#define TMPV770X_RESET_VIIFBS0		32
+#define TMPV770X_RESET_VIIFBS0_APB	33
+#define TMPV770X_RESET_VIIFBS0_L2ISP	34
+#define TMPV770X_RESET_VIIFBS0_L1ISP	35
+#define TMPV770X_RESET_VIIFBS1		36
+#define TMPV770X_RESET_VIIFBS1_APB	37
+#define TMPV770X_RESET_VIIFBS1_L2ISP	38
+#define TMPV770X_RESET_VIIFBS1_L1ISP	39
 
 #endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
index 30f3c9eaafa..4bdb6a16598 100644
--- a/include/dt-bindings/input/linux-event-codes.h
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -891,6 +891,7 @@
 
 #define ABS_VOLUME		0x20
 #define ABS_PROFILE		0x21
+#define ABS_SND_PROFILE		0x22
 
 #define ABS_MISC		0x28
 
@@ -1000,4 +1001,12 @@
 #define SND_MAX			0x07
 #define SND_CNT			(SND_MAX+1)
 
+/*
+ * ABS_SND_PROFILE values
+ */
+
+#define SND_PROFILE_SILENT	0x00
+#define SND_PROFILE_VIBRATE	0x01
+#define SND_PROFILE_RING	0x02
+
 #endif
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
index afd7e0683a2..07b786bee7d 100644
--- a/include/dt-bindings/interconnect/qcom,ipq5424.h
+++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -20,8 +20,41 @@
 #define SLAVE_CNOC_PCIE3		15
 #define MASTER_CNOC_USB			16
 #define SLAVE_CNOC_USB			17
+#define MASTER_NSSNOC_NSSCC		18
+#define SLAVE_NSSNOC_NSSCC		19
+#define MASTER_NSSNOC_SNOC_0		20
+#define SLAVE_NSSNOC_SNOC_0		21
+#define MASTER_NSSNOC_SNOC_1		22
+#define SLAVE_NSSNOC_SNOC_1		23
+#define MASTER_NSSNOC_PCNOC_1		24
+#define SLAVE_NSSNOC_PCNOC_1		25
+#define MASTER_NSSNOC_QOSGEN_REF	26
+#define SLAVE_NSSNOC_QOSGEN_REF		27
+#define MASTER_NSSNOC_TIMEOUT_REF	28
+#define SLAVE_NSSNOC_TIMEOUT_REF	29
+#define MASTER_NSSNOC_XO_DCD		30
+#define SLAVE_NSSNOC_XO_DCD		31
+#define MASTER_NSSNOC_ATB		32
+#define SLAVE_NSSNOC_ATB		33
+#define MASTER_CNOC_LPASS_CFG		34
+#define SLAVE_CNOC_LPASS_CFG		35
+#define MASTER_SNOC_LPASS		36
+#define SLAVE_SNOC_LPASS		37
 
 #define MASTER_CPU			0
 #define SLAVE_L3			1
 
+#define MASTER_NSSNOC_PPE		0
+#define SLAVE_NSSNOC_PPE		1
+#define MASTER_NSSNOC_PPE_CFG		2
+#define SLAVE_NSSNOC_PPE_CFG		3
+#define MASTER_NSSNOC_NSS_CSR		4
+#define SLAVE_NSSNOC_NSS_CSR		5
+#define MASTER_NSSNOC_CE_AXI		6
+#define SLAVE_NSSNOC_CE_AXI		7
+#define MASTER_NSSNOC_CE_APB		8
+#define SLAVE_NSSNOC_CE_APB		9
+#define MASTER_NSSNOC_EIP		10
+#define SLAVE_NSSNOC_EIP		11
+
 #endif /* INTERCONNECT_QCOM_IPQ5424_H */
diff --git a/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h b/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h
new file mode 100644
index 00000000000..dde3f9abd67
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H
+
+#define MASTER_QSPI_0				0
+#define MASTER_CRYPTO				1
+#define MASTER_QUP_1				2
+#define MASTER_SDCC_4				3
+#define MASTER_UFS_MEM				4
+#define MASTER_USB3				5
+#define MASTER_QUP_2				6
+#define MASTER_QUP_3				7
+#define MASTER_QUP_4				8
+#define MASTER_IPA				9
+#define MASTER_SOCCP_PROC			10
+#define MASTER_SP				11
+#define MASTER_QDSS_ETR				12
+#define MASTER_QDSS_ETR_1			13
+#define MASTER_SDCC_2				14
+#define SLAVE_A1NOC_SNOC			15
+#define SLAVE_A2NOC_SNOC			16
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define MASTER_QUP_CORE_2			2
+#define MASTER_QUP_CORE_3			3
+#define MASTER_QUP_CORE_4			4
+#define SLAVE_QUP_CORE_0			5
+#define SLAVE_QUP_CORE_1			6
+#define SLAVE_QUP_CORE_2			7
+#define SLAVE_QUP_CORE_3			8
+#define SLAVE_QUP_CORE_4			9
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_CAMERA_CFG			3
+#define SLAVE_CLK_CTL				4
+#define SLAVE_CRYPTO_0_CFG			5
+#define SLAVE_DISPLAY_CFG			6
+#define SLAVE_EVA_CFG				7
+#define SLAVE_GFX3D_CFG				8
+#define SLAVE_I2C				9
+#define SLAVE_I3C_IBI0_CFG			10
+#define SLAVE_I3C_IBI1_CFG			11
+#define SLAVE_IMEM_CFG				12
+#define SLAVE_IPC_ROUTER_CFG			13
+#define SLAVE_CNOC_MSS				14
+#define SLAVE_PCIE_CFG				15
+#define SLAVE_PRNG				16
+#define SLAVE_QDSS_CFG				17
+#define SLAVE_QSPI_0				18
+#define SLAVE_QUP_1				19
+#define SLAVE_QUP_2				20
+#define SLAVE_QUP_3				21
+#define SLAVE_QUP_4				22
+#define SLAVE_SDCC_2				23
+#define SLAVE_SDCC_4				24
+#define SLAVE_SPSS_CFG				25
+#define SLAVE_TCSR				26
+#define SLAVE_TLMM				27
+#define SLAVE_UFS_MEM_CFG			28
+#define SLAVE_USB3				29
+#define SLAVE_VENUS_CFG				30
+#define SLAVE_VSENSE_CTRL_CFG			31
+#define SLAVE_CNOC_MNOC_CFG			32
+#define SLAVE_PCIE_ANOC_CFG			33
+#define SLAVE_QDSS_STM				34
+#define SLAVE_TCU				35
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_IPA_CFG				3
+#define SLAVE_IPC_ROUTER_FENCE			4
+#define SLAVE_SOCCP				5
+#define SLAVE_TME_CFG				6
+#define SLAVE_APPSS				7
+#define SLAVE_CNOC_CFG				8
+#define SLAVE_DDRSS_CFG				9
+#define SLAVE_BOOT_IMEM				10
+#define SLAVE_IMEM				11
+#define SLAVE_PCIE_0				12
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_APPSS_PROC			2
+#define MASTER_GFX3D				3
+#define MASTER_LPASS_GEM_NOC			4
+#define MASTER_MSS_PROC				5
+#define MASTER_MNOC_HF_MEM_NOC			6
+#define MASTER_MNOC_SF_MEM_NOC			7
+#define MASTER_COMPUTE_NOC			8
+#define MASTER_ANOC_PCIE_GEM_NOC		9
+#define MASTER_QPACE				10
+#define MASTER_SNOC_SF_MEM_NOC			11
+#define MASTER_WLAN_Q6				12
+#define MASTER_GIC				13
+#define SLAVE_GEM_NOC_CNOC			14
+#define SLAVE_LLCC				15
+#define SLAVE_MEM_NOC_PCIE_SNOC			16
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_NRT_ICP_SF		1
+#define MASTER_CAMNOC_RT_CDM_SF			2
+#define MASTER_CAMNOC_SF			3
+#define MASTER_MDP				4
+#define MASTER_MDSS_DCP				5
+#define MASTER_CDSP_HCP				6
+#define MASTER_VIDEO_CV_PROC			7
+#define MASTER_VIDEO_EVA			8
+#define MASTER_VIDEO_MVP			9
+#define MASTER_VIDEO_V_PROC			10
+#define MASTER_CNOC_MNOC_CFG			11
+#define SLAVE_MNOC_HF_MEM_NOC			12
+#define SLAVE_MNOC_SF_MEM_NOC			13
+#define SLAVE_SERVICE_MNOC			14
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_ANOC_CFG			0
+#define MASTER_PCIE_0				1
+#define SLAVE_ANOC_PCIE_GEM_NOC			2
+#define SLAVE_SERVICE_PCIE_ANOC			3
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define MASTER_APSS_NOC				2
+#define MASTER_CNOC_SNOC			3
+#define SLAVE_SNOC_GEM_NOC_SF			4
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,sdx75.h b/include/dt-bindings/interconnect/qcom,sdx75.h
index e903f5f3dd8..0e19ee8f168 100644
--- a/include/dt-bindings/interconnect/qcom,sdx75.h
+++ b/include/dt-bindings/interconnect/qcom,sdx75.h
@@ -6,9 +6,7 @@
 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
 #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
 
-#define MASTER_QPIC_CORE		0
 #define MASTER_QUP_CORE_0		1
-#define SLAVE_QPIC_CORE			2
 #define SLAVE_QUP_CORE_0		3
 
 #define MASTER_LLCC			0
diff --git a/include/dt-bindings/media/c8sectpfe.h b/include/dt-bindings/media/c8sectpfe.h
deleted file mode 100644
index 6b1fb6f5413..00000000000
--- a/include/dt-bindings/media/c8sectpfe.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_C8SECTPFE_H
-#define __DT_C8SECTPFE_H
-
-#define STV0367_TDA18212_NIMA_1	0
-#define STV0367_TDA18212_NIMA_2	1
-#define STV0367_TDA18212_NIMB_1	2
-#define STV0367_TDA18212_NIMB_2	3
-
-#define STV0903_6110_LNB24_NIMA	4
-#define STV0903_6110_LNB24_NIMB	5
-
-#endif /* __DT_C8SECTPFE_H */
diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h
index 88b9d05d807..0b19c9b2e62 100644
--- a/include/dt-bindings/media/video-interfaces.h
+++ b/include/dt-bindings/media/video-interfaces.h
@@ -20,4 +20,8 @@
 #define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB	4
 #define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA	5
 
+#define MEDIA_PCLK_SAMPLE_FALLING_EDGE		0
+#define MEDIA_PCLK_SAMPLE_RISING_EDGE		1
+#define MEDIA_PCLK_SAMPLE_DUAL_EDGE		2
+
 #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
diff --git a/include/dt-bindings/memory/mediatek,mt8189-memory-port.h b/include/dt-bindings/memory/mediatek,mt8189-memory-port.h
new file mode 100644
index 00000000000..849fead3d0f
--- /dev/null
+++ b/include/dt-bindings/memory/mediatek,mt8189-memory-port.h
@@ -0,0 +1,283 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Zhengnan chen <zhengnan.chen@mediatek.com>
+ */
+#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_
+#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+#define SMI_L0_ID		(0)
+#define SMI_L1_ID		(1)
+#define SMI_L2_ID		(2)
+#define SMI_L4_ID		(3)
+#define SMI_L7_ID		(4)
+#define SMI_L9_ID		(5)
+#define SMI_L11_ID		(6)
+#define SMI_L13_ID		(7)
+#define SMI_L14_ID		(8)
+#define SMI_L16_ID		(9)
+#define SMI_L17_ID		(10)
+#define SMI_L19_ID		(11)
+#define SMI_L20_ID		(12)
+
+/*
+ * MM IOMMU supports 16GB dma address. We separate it to four ranges:
+ * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
+ * locate in anyone region. BUT:
+ * a) Make sure all the ports inside a larb are in one range.
+ * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
+ *
+ * This is the suggested mapping in this SoC:
+ *
+ * modules		dma-address-region	larbs-ports
+ * disp/mdp		0 ~ 4G			larb0/1/2
+ * vcodec		4G ~ 8G                 larb4/7
+ * imgsys/cam/ipesys	8G ~ 12G                the other larbs.
+ * N/A			12G ~ 16G
+ */
+
+/* Larb0 -- disp */
+#define M4U_L0_P0_DISP_OVL0_4L_HDR		MTK_M4U_ID(SMI_L0_ID, 0)
+#define M4U_L0_P1_DISP_OVL0_4L_RDMA0		MTK_M4U_ID(SMI_L0_ID, 1)
+#define M4U_L0_P2_DISP_OVL1_4L_RDMA1		MTK_M4U_ID(SMI_L0_ID, 2)
+#define M4U_L0_P3_DISP_OVL0_4L_RDMA2		MTK_M4U_ID(SMI_L0_ID, 3)
+#define M4U_L0_P4_DISP_OVL1_4L_RDMA3		MTK_M4U_ID(SMI_L0_ID, 4)
+#define M4U_L0_P5_DISP_RDMA0			MTK_M4U_ID(SMI_L0_ID, 5)
+#define M4U_L0_P6_DISP_WDMA0			MTK_M4U_ID(SMI_L0_ID, 6)
+#define M4U_L0_P7_DISP_FAKE_ENG0		MTK_M4U_ID(SMI_L0_ID, 7)
+
+/* Larb1 -- disp */
+#define M4U_L1_P0_DISP_OVL1_4L_HDR		MTK_M4U_ID(SMI_L1_ID, 0)
+#define M4U_L1_P1_DISP_OVL1_4L_RDMA0		MTK_M4U_ID(SMI_L1_ID, 1)
+#define M4U_L1_P2_DISP_OVL0_4L_RDMA1		MTK_M4U_ID(SMI_L1_ID, 2)
+#define M4U_L1_P3_DISP_OVL1_4L_RDMA2		MTK_M4U_ID(SMI_L1_ID, 3)
+#define M4U_L1_P4_DISP_OVL0_4L_RDMA3		MTK_M4U_ID(SMI_L1_ID, 4)
+#define M4U_L1_P5_DISP_RDMA1			MTK_M4U_ID(SMI_L1_ID, 5)
+#define M4U_L1_P6_DISP_WDMA1			MTK_M4U_ID(SMI_L1_ID, 6)
+#define M4U_L1_P7_DISP_FAKE_ENG1		MTK_M4U_ID(SMI_L1_ID, 7)
+
+/* Larb2 -- mmlsys(mdp) */
+#define M4U_L2_P0_MDP_RDMA0			MTK_M4U_ID(SMI_L2_ID, 0)
+#define M4U_L2_P1_MDP_RDMA1			MTK_M4U_ID(SMI_L2_ID, 1)
+#define M4U_L2_P2_MDP_WROT0			MTK_M4U_ID(SMI_L2_ID, 2)
+#define M4U_L2_P3_MDP_WROT1			MTK_M4U_ID(SMI_L2_ID, 3)
+#define M4U_L2_P4_MDP_DUMMY0			MTK_M4U_ID(SMI_L2_ID, 4)
+#define M4U_L2_P5_MDP_DUMMY1			MTK_M4U_ID(SMI_L2_ID, 5)
+#define M4U_L2_P6_MDP_RDMA2			MTK_M4U_ID(SMI_L2_ID, 6)
+#define M4U_L2_P7_MDP_RDMA3			MTK_M4U_ID(SMI_L2_ID, 7)
+#define M4U_L2_P8_MDP_WROT2			MTK_M4U_ID(SMI_L2_ID, 8)
+#define M4U_L2_P9_MDP_WROT3			MTK_M4U_ID(SMI_L2_ID, 9)
+#define M4U_L2_P10_DISP_FAKE0			MTK_M4U_ID(SMI_L2_ID, 10)
+
+/* Larb3: null */
+
+/* Larb4 -- vdec */
+#define M4U_L4_P0_HW_VDEC_MC_EXT		MTK_M4U_ID(SMI_L4_ID, 0)
+#define M4U_L4_P1_HW_VDEC_UFO_EXT		MTK_M4U_ID(SMI_L4_ID, 1)
+#define M4U_L4_P2_HW_VDEC_PP_EXT		MTK_M4U_ID(SMI_L4_ID, 2)
+#define M4U_L4_P3_HW_VDEC_PRED_RD_EXT		MTK_M4U_ID(SMI_L4_ID, 3)
+#define M4U_L4_P4_HW_VDEC_PRED_WR_EXT		MTK_M4U_ID(SMI_L4_ID, 4)
+#define M4U_L4_P5_HW_VDEC_PPWRAP_EXT		MTK_M4U_ID(SMI_L4_ID, 5)
+#define M4U_L4_P6_HW_VDEC_TILE_EXT		MTK_M4U_ID(SMI_L4_ID, 6)
+#define M4U_L4_P7_HW_VDEC_VLD_EXT		MTK_M4U_ID(SMI_L4_ID, 7)
+#define M4U_L4_P8_HW_VDEC_VLD2_EXT		MTK_M4U_ID(SMI_L4_ID, 8)
+#define M4U_L4_P9_HW_VDEC_AVC_MV_EXT		MTK_M4U_ID(SMI_L4_ID, 9)
+#define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(SMI_L4_ID, 10)
+#define M4U_L4_P11_HW_VDEC_UFO_ENC_EXT		MTK_M4U_ID(SMI_L4_ID, 11)
+
+/* Larb5: null */
+
+/* Larb6: null */
+
+/* Larb7 -- venc */
+#define M4U_L7_P0_VENC_RCPU			MTK_M4U_ID(SMI_L7_ID, 0)
+#define M4U_L7_P1_VENC_REC			MTK_M4U_ID(SMI_L7_ID, 1)
+#define M4U_L7_P2_VENC_BSDMA			MTK_M4U_ID(SMI_L7_ID, 2)
+#define M4U_L7_P3_VENC_SV_COMV			MTK_M4U_ID(SMI_L7_ID, 3)
+#define M4U_L7_P4_VENC_RD_COMV			MTK_M4U_ID(SMI_L7_ID, 4)
+#define M4U_L7_P5_JPGENC_Y_RDMA			MTK_M4U_ID(SMI_L7_ID, 5)
+#define M4U_L7_P6_JPGENC_C_RDMA			MTK_M4U_ID(SMI_L7_ID, 6)
+#define M4U_L7_P7_JPGENC_Q_RDMA			MTK_M4U_ID(SMI_L7_ID, 7)
+#define M4U_L7_P8_VENC_SUB_W_LUMA		MTK_M4U_ID(SMI_L7_ID, 8)
+#define M4U_L7_P9_JPGENC_BSDMA			MTK_M4U_ID(SMI_L7_ID, 9)
+#define M4U_L7_P10_VENC_CUR_LUMA		MTK_M4U_ID(SMI_L7_ID, 10)
+#define M4U_L7_P11_VENC_CUR_CHROMA		MTK_M4U_ID(SMI_L7_ID, 11)
+#define M4U_L7_P12_VENC_REF_LUMA		MTK_M4U_ID(SMI_L7_ID, 12)
+#define M4U_L7_P13_VENC_REF_CHROMA		MTK_M4U_ID(SMI_L7_ID, 13)
+#define M4U_L7_P14_VENC_SUB_R_LUMA		MTK_M4U_ID(SMI_L7_ID, 14)
+#define M4U_L7_P15_JPGDEC_WDMA			MTK_M4U_ID(SMI_L7_ID, 15)
+#define M4U_L7_P16_JPGDEC_BSDMA			MTK_M4U_ID(SMI_L7_ID, 16)
+#define M4U_L7_P17_JPGDEC_HUFF_OFFSET		MTK_M4U_ID(SMI_L7_ID, 17)
+
+/* Larb8: null */
+
+/* Larb9 --imgsys */
+#define M4U_L9_P0_IMGI_D1			MTK_M4U_ID(SMI_L9_ID, 0)
+#define M4U_L9_P1_IMGBI_D1			MTK_M4U_ID(SMI_L9_ID, 1)
+#define M4U_L9_P2_DMGI_D1			MTK_M4U_ID(SMI_L9_ID, 2)
+#define M4U_L9_P3_DEPI_D1			MTK_M4U_ID(SMI_L9_ID, 3)
+#define M4U_L9_P4_LCE_D1			MTK_M4U_ID(SMI_L9_ID, 4)
+#define M4U_L9_P5_SMTI_D1			MTK_M4U_ID(SMI_L9_ID, 5)
+#define M4U_L9_P6_SMTO_D2			MTK_M4U_ID(SMI_L9_ID, 6)
+#define M4U_L9_P7_SMTO_D1			MTK_M4U_ID(SMI_L9_ID, 7)
+#define M4U_L9_P8_CRZO_D1			MTK_M4U_ID(SMI_L9_ID, 8)
+#define M4U_L9_P9_IMG3O_D1			MTK_M4U_ID(SMI_L9_ID, 9)
+#define M4U_L9_P10_VIPI_D1			MTK_M4U_ID(SMI_L9_ID, 10)
+#define M4U_L9_P11_SMTI_D5			MTK_M4U_ID(SMI_L9_ID, 11)
+#define M4U_L9_P12_TIMGO_D1			MTK_M4U_ID(SMI_L9_ID, 12)
+#define M4U_L9_P13_UFBC_W0			MTK_M4U_ID(SMI_L9_ID, 13)
+#define M4U_L9_P14_UFBC_R0			MTK_M4U_ID(SMI_L9_ID, 14)
+#define M4U_L9_P15_WPE_RDMA1			MTK_M4U_ID(SMI_L9_ID, 15)
+#define M4U_L9_P16_WPE_RDMA0			MTK_M4U_ID(SMI_L9_ID, 16)
+#define M4U_L9_P17_WPE_WDMA			MTK_M4U_ID(SMI_L9_ID, 17)
+#define M4U_L9_P18_MFB_RDMA0			MTK_M4U_ID(SMI_L9_ID, 18)
+#define M4U_L9_P19_MFB_RDMA1			MTK_M4U_ID(SMI_L9_ID, 19)
+#define M4U_L9_P20_MFB_RDMA2			MTK_M4U_ID(SMI_L9_ID, 20)
+#define M4U_L9_P21_MFB_RDMA3			MTK_M4U_ID(SMI_L9_ID, 21)
+#define M4U_L9_P22_MFB_RDMA4			MTK_M4U_ID(SMI_L9_ID, 22)
+#define M4U_L9_P23_MFB_RDMA5			MTK_M4U_ID(SMI_L9_ID, 23)
+#define M4U_L9_P24_MFB_WDMA0			MTK_M4U_ID(SMI_L9_ID, 24)
+#define M4U_L9_P25_MFB_WDMA1			MTK_M4U_ID(SMI_L9_ID, 25)
+#define M4U_L9_P26_RESERVE6			MTK_M4U_ID(SMI_L9_ID, 26)
+#define M4U_L9_P27_RESERVE7			MTK_M4U_ID(SMI_L9_ID, 27)
+#define M4U_L9_P28_RESERVE8			MTK_M4U_ID(SMI_L9_ID, 28)
+
+/* Larb10: null */
+
+/* Larb11 -- imgsys */
+#define M4U_L11_P0_IMGI_D1			MTK_M4U_ID(SMI_L11_ID, 0)
+#define M4U_L11_P1_IMGBI_D1			MTK_M4U_ID(SMI_L11_ID, 1)
+#define M4U_L11_P2_DMGI_D1			MTK_M4U_ID(SMI_L11_ID, 2)
+#define M4U_L11_P3_DEPI_D1			MTK_M4U_ID(SMI_L11_ID, 3)
+#define M4U_L11_P4_LCE_D1			MTK_M4U_ID(SMI_L11_ID, 4)
+#define M4U_L11_P5_SMTI_D1			MTK_M4U_ID(SMI_L11_ID, 5)
+#define M4U_L11_P6_SMTO_D2			MTK_M4U_ID(SMI_L11_ID, 6)
+#define M4U_L11_P7_SMTO_D1			MTK_M4U_ID(SMI_L11_ID, 7)
+#define M4U_L11_P8_CRZO_D1			MTK_M4U_ID(SMI_L11_ID, 8)
+#define M4U_L11_P9_IMG3O_D1			MTK_M4U_ID(SMI_L11_ID, 9)
+#define M4U_L11_P10_VIPI_D1			MTK_M4U_ID(SMI_L11_ID, 10)
+#define M4U_L11_P11_SMTI_D5			MTK_M4U_ID(SMI_L11_ID, 11)
+#define M4U_L11_P12_TIMGO_D1			MTK_M4U_ID(SMI_L11_ID, 12)
+#define M4U_L11_P13_UFBC_W0			MTK_M4U_ID(SMI_L11_ID, 13)
+#define M4U_L11_P14_UFBC_R0			MTK_M4U_ID(SMI_L11_ID, 14)
+#define M4U_L11_P15_WPE_RDMA1			MTK_M4U_ID(SMI_L11_ID, 15)
+#define M4U_L11_P16_WPE_RDMA0			MTK_M4U_ID(SMI_L11_ID, 16)
+#define M4U_L11_P17_WPE_WDMA			MTK_M4U_ID(SMI_L11_ID, 17)
+#define M4U_L11_P18_MFB_RDMA0			MTK_M4U_ID(SMI_L11_ID, 18)
+#define M4U_L11_P19_MFB_RDMA1			MTK_M4U_ID(SMI_L11_ID, 19)
+#define M4U_L11_P20_MFB_RDMA2			MTK_M4U_ID(SMI_L11_ID, 20)
+#define M4U_L11_P21_MFB_RDMA3			MTK_M4U_ID(SMI_L11_ID, 21)
+#define M4U_L11_P22_MFB_RDMA4			MTK_M4U_ID(SMI_L11_ID, 22)
+#define M4U_L11_P23_MFB_RDMA5			MTK_M4U_ID(SMI_L11_ID, 23)
+#define M4U_L11_P24_MFB_WDMA0			MTK_M4U_ID(SMI_L11_ID, 24)
+#define M4U_L11_P25_MFB_WDMA1			MTK_M4U_ID(SMI_L11_ID, 25)
+#define M4U_L11_P26_RESERVE6			MTK_M4U_ID(SMI_L11_ID, 26)
+#define M4U_L11_P27_RESERVE7			MTK_M4U_ID(SMI_L11_ID, 27)
+#define M4U_L11_P28_RESERVE8			MTK_M4U_ID(SMI_L11_ID, 28)
+
+/* Larb12: null */
+
+/* Larb13 -- cam */
+#define M4U_L13_P0_MRAWI			MTK_M4U_ID(SMI_L13_ID, 0)
+#define M4U_L13_P1_MRAWO_0			MTK_M4U_ID(SMI_L13_ID, 1)
+#define M4U_L13_P2_MRAWO_1			MTK_M4U_ID(SMI_L13_ID, 2)
+#define M4U_L13_P3_CAMSV_1			MTK_M4U_ID(SMI_L13_ID, 3)
+#define M4U_L13_P4_CAMSV_2			MTK_M4U_ID(SMI_L13_ID, 4)
+#define M4U_L13_P5_CAMSV_3			MTK_M4U_ID(SMI_L13_ID, 5)
+#define M4U_L13_P6_CAMSV_4			MTK_M4U_ID(SMI_L13_ID, 6)
+#define M4U_L13_P7_CAMSV_5			MTK_M4U_ID(SMI_L13_ID, 7)
+#define M4U_L13_P8_CAMSV_6			MTK_M4U_ID(SMI_L13_ID, 8)
+#define M4U_L13_P9_CCUI				MTK_M4U_ID(SMI_L13_ID, 9)
+#define M4U_L13_P10_CCUO			MTK_M4U_ID(SMI_L13_ID, 10)
+#define M4U_L13_P11_FAKE			MTK_M4U_ID(SMI_L13_ID, 11)
+#define M4U_L13_P12_PDAI_0			MTK_M4U_ID(SMI_L13_ID, 12)
+#define M4U_L13_P13_PDAI_1			MTK_M4U_ID(SMI_L13_ID, 13)
+#define M4U_L13_P14_PDAO			MTK_M4U_ID(SMI_L13_ID, 14)
+
+/* Larb14 -- cam */
+#define M4U_L14_P0_RESERVE			MTK_M4U_ID(SMI_L14_ID, 0)
+#define M4U_L14_P1_RESERVE			MTK_M4U_ID(SMI_L14_ID, 1)
+#define M4U_L14_P2_RESERVE			MTK_M4U_ID(SMI_L14_ID, 2)
+#define M4U_L14_P3_CAMSV_0			MTK_M4U_ID(SMI_L14_ID, 3)
+#define M4U_L14_P4_CCUI				MTK_M4U_ID(SMI_L14_ID, 4)
+#define M4U_L14_P5_CCUO				MTK_M4U_ID(SMI_L14_ID, 5)
+#define M4U_L14_P6_CAMSV_7			MTK_M4U_ID(SMI_L14_ID, 6)
+#define M4U_L14_P7_CAMSV_8			MTK_M4U_ID(SMI_L14_ID, 7)
+#define M4U_L14_P8_CAMSV_9			MTK_M4U_ID(SMI_L14_ID, 8)
+#define M4U_L14_P9_CAMSV_10			MTK_M4U_ID(SMI_L14_ID, 9)
+
+/* Larb15: null */
+
+/* Larb16 -- cam */
+#define M4U_L16_P0_IMGO_R1_A			MTK_M4U_ID(SMI_L16_ID, 0)
+#define M4U_L16_P1_RRZO_R1_A			MTK_M4U_ID(SMI_L16_ID, 1)
+#define M4U_L16_P2_CQI_R1_A			MTK_M4U_ID(SMI_L16_ID, 2)
+#define M4U_L16_P3_BPCI_R1_A			MTK_M4U_ID(SMI_L16_ID, 3)
+#define M4U_L16_P4_YUVO_R1_A			MTK_M4U_ID(SMI_L16_ID, 4)
+#define M4U_L16_P5_UFDI_R2_A			MTK_M4U_ID(SMI_L16_ID, 5)
+#define M4U_L16_P6_RAWI_R2_A			MTK_M4U_ID(SMI_L16_ID, 6)
+#define M4U_L16_P7_RAWI_R3_A			MTK_M4U_ID(SMI_L16_ID, 7)
+#define M4U_L16_P8_AAO_R1_A			MTK_M4U_ID(SMI_L16_ID, 8)
+#define M4U_L16_P9_AFO_R1_A			MTK_M4U_ID(SMI_L16_ID, 9)
+#define M4U_L16_P10_FLKO_R1_A			MTK_M4U_ID(SMI_L16_ID, 10)
+#define M4U_L16_P11_LCESO_R1_A			MTK_M4U_ID(SMI_L16_ID, 11)
+#define M4U_L16_P12_CRZO_R1_A			MTK_M4U_ID(SMI_L16_ID, 12)
+#define M4U_L16_P13_LTMSO_R1_A			MTK_M4U_ID(SMI_L16_ID, 13)
+#define M4U_L16_P14_RSSO_R1_A			MTK_M4U_ID(SMI_L16_ID, 14)
+#define M4U_L16_P15_AAHO_R1_A			MTK_M4U_ID(SMI_L16_ID, 15)
+#define M4U_L16_P16_LSCI_R1_A			MTK_M4U_ID(SMI_L16_ID, 16)
+
+/* Larb17 -- cam */
+#define M4U_L17_P0_IMGO_R1_B			MTK_M4U_ID(SMI_L17_ID, 0)
+#define M4U_L17_P1_RRZO_R1_B			MTK_M4U_ID(SMI_L17_ID, 1)
+#define M4U_L17_P2_CQI_R1_B			MTK_M4U_ID(SMI_L17_ID, 2)
+#define M4U_L17_P3_BPCI_R1_B			MTK_M4U_ID(SMI_L17_ID, 3)
+#define M4U_L17_P4_YUVO_R1_B			MTK_M4U_ID(SMI_L17_ID, 4)
+#define M4U_L17_P5_UFDI_R2_B			MTK_M4U_ID(SMI_L17_ID, 5)
+#define M4U_L17_P6_RAWI_R2_B			MTK_M4U_ID(SMI_L17_ID, 6)
+#define M4U_L17_P7_RAWI_R3_B			MTK_M4U_ID(SMI_L17_ID, 7)
+#define M4U_L17_P8_AAO_R1_B			MTK_M4U_ID(SMI_L17_ID, 8)
+#define M4U_L17_P9_AFO_R1_B			MTK_M4U_ID(SMI_L17_ID, 9)
+#define M4U_L17_P10_FLKO_R1_B			MTK_M4U_ID(SMI_L17_ID, 10)
+#define M4U_L17_P11_LCESO_R1_B			MTK_M4U_ID(SMI_L17_ID, 11)
+#define M4U_L17_P12_CRZO_R1_B			MTK_M4U_ID(SMI_L17_ID, 12)
+#define M4U_L17_P13_LTMSO_R1_B			MTK_M4U_ID(SMI_L17_ID, 13)
+#define M4U_L17_P14_RSSO_R1_B			MTK_M4U_ID(SMI_L17_ID, 14)
+#define M4U_L17_P15_AAHO_R1_B			MTK_M4U_ID(SMI_L17_ID, 15)
+#define M4U_L17_P16_LSCI_R1_B			MTK_M4U_ID(SMI_L17_ID, 16)
+
+/* Larb19 -- ipesys */
+#define M4U_L19_P0_DVS_RDMA			MTK_M4U_ID(SMI_L19_ID, 0)
+#define M4U_L19_P1_DVS_WDMA			MTK_M4U_ID(SMI_L19_ID, 1)
+#define M4U_L19_P2_DVP_RDMA			MTK_M4U_ID(SMI_L19_ID, 2)
+#define M4U_L19_P3_DVP_WDMA			MTK_M4U_ID(SMI_L19_ID, 3)
+
+/* Larb20 -- ipesys */
+#define M4U_L20_P0_FDVT_RDA_0			MTK_M4U_ID(SMI_L20_ID, 0)
+#define M4U_L20_P1_FDVT_RDB_0			MTK_M4U_ID(SMI_L20_ID, 1)
+#define M4U_L20_P2_FDVT_WRA_0			MTK_M4U_ID(SMI_L20_ID, 2)
+#define M4U_L20_P3_FDVT_WRB_0			MTK_M4U_ID(SMI_L20_ID, 3)
+#define M4U_L20_P4_RSC_RDMA			MTK_M4U_ID(SMI_L20_ID, 4)
+#define M4U_L20_P5_RSC_WDMA			MTK_M4U_ID(SMI_L20_ID, 5)
+
+/* fake larb21 for gce */
+#define M4U_L21_GCE_DM				MTK_M4U_ID(21, 0)
+#define M4U_L21_GCE_MM				MTK_M4U_ID(21, 1)
+
+/* fake larb & port for svp and dual svp and wfd */
+#define M4U_PORT_SVP_HEAP			MTK_M4U_ID(22, 0)
+#define M4U_PORT_DUAL_SVP_HEAP			MTK_M4U_ID(22, 1)
+#define M4U_PORT_WFD_HEAP			MTK_M4U_ID(22, 2)
+
+/* fake larb0 for apu */
+#define M4U_L0_APU_DATA				MTK_M4U_ID(0, 0)
+#define M4U_L0_APU_CODE				MTK_M4U_ID(0, 1)
+#define M4U_L0_APU_SECURE			MTK_M4U_ID(0, 2)
+#define M4U_L0_APU_VLM				MTK_M4U_ID(0, 3)
+
+/* infra/peri */
+#define IFR_IOMMU_PORT_PCIE_0			MTK_IFAIOMMU_PERI_ID(0, 26)
+
+#endif
diff --git a/include/dt-bindings/power/mediatek,mt8196-power.h b/include/dt-bindings/power/mediatek,mt8196-power.h
new file mode 100644
index 00000000000..0f622a93c80
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8196-power.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H
+#define _DT_BINDINGS_POWER_MT8196_POWER_H
+
+/* SCPSYS Secure Power Manager - Direct Control */
+#define MT8196_POWER_DOMAIN_MD				0
+#define MT8196_POWER_DOMAIN_CONN			1
+#define MT8196_POWER_DOMAIN_SSUSB_P0			2
+#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0		3
+#define MT8196_POWER_DOMAIN_SSUSB_P1			4
+#define MT8196_POWER_DOMAIN_SSUSB_P23			5
+#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2		6
+#define MT8196_POWER_DOMAIN_PEXTP_MAC0			7
+#define MT8196_POWER_DOMAIN_PEXTP_MAC1			8
+#define MT8196_POWER_DOMAIN_PEXTP_MAC2			9
+#define MT8196_POWER_DOMAIN_PEXTP_PHY0			10
+#define MT8196_POWER_DOMAIN_PEXTP_PHY1			11
+#define MT8196_POWER_DOMAIN_PEXTP_PHY2			12
+#define MT8196_POWER_DOMAIN_AUDIO			13
+#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT		14
+#define MT8196_POWER_DOMAIN_ADSP_INFRA			15
+#define MT8196_POWER_DOMAIN_ADSP_AO			16
+
+/* SCPSYS Secure Power Manager - HW Voter */
+#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT		0
+#define MT8196_POWER_DOMAIN_SSR				1
+
+/* HFRPSYS MultiMedia Power Control (MMPC) - HW Voter */
+#define MT8196_POWER_DOMAIN_VDE0			0
+#define MT8196_POWER_DOMAIN_VDE1			1
+#define MT8196_POWER_DOMAIN_VDE_VCORE0			2
+#define MT8196_POWER_DOMAIN_VEN0			3
+#define MT8196_POWER_DOMAIN_VEN1			4
+#define MT8196_POWER_DOMAIN_VEN2			5
+#define MT8196_POWER_DOMAIN_DISP_VCORE			6
+#define MT8196_POWER_DOMAIN_DIS0_DORMANT		7
+#define MT8196_POWER_DOMAIN_DIS1_DORMANT		8
+#define MT8196_POWER_DOMAIN_OVL0_DORMANT		9
+#define MT8196_POWER_DOMAIN_OVL1_DORMANT		10
+#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT		11
+#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT		12
+#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN		13
+#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN		14
+#define MT8196_POWER_DOMAIN_MM_INFRA0			15
+#define MT8196_POWER_DOMAIN_MM_INFRA1			16
+#define MT8196_POWER_DOMAIN_MM_INFRA_AO			17
+#define MT8196_POWER_DOMAIN_CSI_BS_RX			18
+#define MT8196_POWER_DOMAIN_CSI_LS_RX			19
+#define MT8196_POWER_DOMAIN_DSI_PHY0			20
+#define MT8196_POWER_DOMAIN_DSI_PHY1			21
+#define MT8196_POWER_DOMAIN_DSI_PHY2			22
+
+#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */
diff --git a/include/dt-bindings/power/nvidia,tegra264-bpmp.h b/include/dt-bindings/power/nvidia,tegra264-bpmp.h
new file mode 100644
index 00000000000..2eef4a2a02b
--- /dev/null
+++ b/include/dt-bindings/power/nvidia,tegra264-bpmp.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)  */
+/* Copyright (c) 2022-2024, NVIDIA CORPORATION.  All rights reserved. */
+
+#ifndef DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H
+#define DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H
+
+#define TEGRA264_POWER_DOMAIN_DISP	1
+#define TEGRA264_POWER_DOMAIN_AUD	2
+/* reserved 3:9 */
+#define TEGRA264_POWER_DOMAIN_XUSB_SS	10
+#define TEGRA264_POWER_DOMAIN_XUSB_DEV	11
+#define TEGRA264_POWER_DOMAIN_XUSB_HOST	12
+#define TEGRA264_POWER_DOMAIN_MGBE0	13
+#define TEGRA264_POWER_DOMAIN_MGBE1	14
+#define TEGRA264_POWER_DOMAIN_MGBE2	15
+#define TEGRA264_POWER_DOMAIN_MGBE3	16
+#define TEGRA264_POWER_DOMAIN_VI	17
+#define TEGRA264_POWER_DOMAIN_VIC	18
+#define TEGRA264_POWER_DOMAIN_ISP0	19
+#define TEGRA264_POWER_DOMAIN_ISP1	20
+#define TEGRA264_POWER_DOMAIN_PVA0	21
+#define TEGRA264_POWER_DOMAIN_GPU	22
+
+#endif /* DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H */
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index 73cceb88953..06851363ae0 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -33,11 +33,14 @@
 #define RPMH_REGULATOR_LEVEL_RETENTION		16
 #define RPMH_REGULATOR_LEVEL_MIN_SVS		48
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D3		50
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1	51
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1	54
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
 #define RPMH_REGULATOR_LEVEL_LOW_SVS		64
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_P1		72
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_L0		76
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_L1		80
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_L2		96
 #define RPMH_REGULATOR_LEVEL_SVS		128
@@ -261,5 +264,6 @@
 #define SC8280XP_NSP		13
 #define SC8280XP_QPHY		14
 #define SC8280XP_XO		15
+#define SC8280XP_MXC_AO		16
 
 #endif
diff --git a/include/dt-bindings/power/rockchip,rv1126b-power-controller.h b/include/dt-bindings/power/rockchip,rv1126b-power-controller.h
new file mode 100644
index 00000000000..48ea87a4423
--- /dev/null
+++ b/include/dt-bindings/power/rockchip,rv1126b-power-controller.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
+#define __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
+
+/* VD_NPU */
+#define RV1126B_PD_NPU		0
+
+/* VD_LOGIC */
+#define RV1126B_PD_VDO		1
+#define RV1126B_PD_AIISP	2
+
+#endif
diff --git a/include/dt-bindings/reset/airoha,en7523-reset.h b/include/dt-bindings/reset/airoha,en7523-reset.h
new file mode 100644
index 00000000000..211e8a23a21
--- /dev/null
+++ b/include/dt-bindings/reset/airoha,en7523-reset.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2024 iopsys Software Solutions AB.
+ * Copyright (C) 2025 Genexis AB.
+ *
+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+ *
+ * based on
+ *   include/dt-bindings/reset/airoha,en7581-reset.h
+ * by Lorenzo Bianconi <lorenzo@kernel.org>
+ */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_
+
+/* RST_CTRL2 */
+#define EN7523_XPON_PHY_RST		 0
+#define EN7523_XSI_MAC_RST		 1
+#define EN7523_XSI_PHY_RST		 2
+#define EN7523_NPU_RST			 3
+#define EN7523_I2S_RST			 4
+#define EN7523_TRNG_RST			 5
+#define EN7523_TRNG_MSTART_RST		 6
+#define EN7523_DUAL_HSI0_RST		 7
+#define EN7523_DUAL_HSI1_RST		 8
+#define EN7523_HSI_RST			 9
+#define EN7523_DUAL_HSI0_MAC_RST	10
+#define EN7523_DUAL_HSI1_MAC_RST	11
+#define EN7523_HSI_MAC_RST		12
+#define EN7523_WDMA_RST			13
+#define EN7523_WOE0_RST			14
+#define EN7523_WOE1_RST			15
+#define EN7523_HSDMA_RST		16
+#define EN7523_I2C2RBUS_RST		17
+#define EN7523_TDMA_RST			18
+/* RST_CTRL1 */
+#define EN7523_PCM1_ZSI_ISI_RST		19
+#define EN7523_FE_PDMA_RST		20
+#define EN7523_FE_QDMA_RST		21
+#define EN7523_PCM_SPIWP_RST		22
+#define EN7523_CRYPTO_RST		23
+#define EN7523_TIMER_RST		24
+#define EN7523_PCM1_RST			25
+#define EN7523_UART_RST			26
+#define EN7523_GPIO_RST			27
+#define EN7523_GDMA_RST			28
+#define EN7523_I2C_MASTER_RST		29
+#define EN7523_PCM2_ZSI_ISI_RST		30
+#define EN7523_SFC_RST			31
+#define EN7523_UART2_RST		32
+#define EN7523_GDMP_RST			33
+#define EN7523_FE_RST			34
+#define EN7523_USB_HOST_P0_RST		35
+#define EN7523_GSW_RST			36
+#define EN7523_SFC2_PCM_RST		37
+#define EN7523_PCIE0_RST		38
+#define EN7523_PCIE1_RST		39
+#define EN7523_PCIE_HB_RST		40
+#define EN7523_XPON_MAC_RST		41
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ */
diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-bindings/reset/eswin,eic7700-reset.h
new file mode 100644
index 00000000000..a370c9f7430
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-reset.h
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 reset controller.
+ *
+ * Authors:
+ *	Yifeng Huang <huangyifeng@eswincomputing.com>
+ *	Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef __DT_ESWIN_EIC7700_RESET_H__
+#define __DT_ESWIN_EIC7700_RESET_H__
+
+#define EIC7700_RESET_NOC_NSP		0
+#define EIC7700_RESET_NOC_CFG		1
+#define EIC7700_RESET_RNOC_NSP		2
+#define EIC7700_RESET_SNOC_TCU		3
+#define EIC7700_RESET_SNOC_U84		4
+#define EIC7700_RESET_SNOC_PCIE_XSR	5
+#define EIC7700_RESET_SNOC_PCIE_XMR	6
+#define EIC7700_RESET_SNOC_PCIE_PR	7
+#define EIC7700_RESET_SNOC_NPU		8
+#define EIC7700_RESET_SNOC_JTAG		9
+#define EIC7700_RESET_SNOC_DSP		10
+#define EIC7700_RESET_SNOC_DDRC1_P2	11
+#define EIC7700_RESET_SNOC_DDRC1_P1	12
+#define EIC7700_RESET_SNOC_DDRC0_P2	13
+#define EIC7700_RESET_SNOC_DDRC0_P1	14
+#define EIC7700_RESET_SNOC_D2D		15
+#define EIC7700_RESET_SNOC_AON		16
+#define EIC7700_RESET_GPU_AXI		17
+#define EIC7700_RESET_GPU_CFG		18
+#define EIC7700_RESET_GPU_GRAY		19
+#define EIC7700_RESET_GPU_JONES		20
+#define EIC7700_RESET_GPU_SPU		21
+#define EIC7700_RESET_DSP_AXI		22
+#define EIC7700_RESET_DSP_CFG		23
+#define EIC7700_RESET_DSP_DIV4		24
+#define EIC7700_RESET_DSP_DIV0		25
+#define EIC7700_RESET_DSP_DIV1		26
+#define EIC7700_RESET_DSP_DIV2		27
+#define EIC7700_RESET_DSP_DIV3		28
+#define EIC7700_RESET_D2D_AXI		29
+#define EIC7700_RESET_D2D_CFG		30
+#define EIC7700_RESET_D2D_PRST		31
+#define EIC7700_RESET_D2D_RAW_PCS	32
+#define EIC7700_RESET_D2D_RX		33
+#define EIC7700_RESET_D2D_TX		34
+#define EIC7700_RESET_D2D_CORE		35
+#define EIC7700_RESET_DDR1_ARST		36
+#define EIC7700_RESET_DDR1_TRACE	37
+#define EIC7700_RESET_DDR0_ARST		38
+#define EIC7700_RESET_DDR_CFG		39
+#define EIC7700_RESET_DDR0_TRACE	40
+#define EIC7700_RESET_DDR_CORE		41
+#define EIC7700_RESET_DDR_PRST		42
+#define EIC7700_RESET_TCU_AXI		43
+#define EIC7700_RESET_TCU_CFG		44
+#define EIC7700_RESET_TCU_TBU0		45
+#define EIC7700_RESET_TCU_TBU1		46
+#define EIC7700_RESET_TCU_TBU2		47
+#define EIC7700_RESET_TCU_TBU3		48
+#define EIC7700_RESET_TCU_TBU4		49
+#define EIC7700_RESET_TCU_TBU5		50
+#define EIC7700_RESET_TCU_TBU6		51
+#define EIC7700_RESET_TCU_TBU7		52
+#define EIC7700_RESET_TCU_TBU8		53
+#define EIC7700_RESET_TCU_TBU9		54
+#define EIC7700_RESET_TCU_TBU10		55
+#define EIC7700_RESET_TCU_TBU11		56
+#define EIC7700_RESET_TCU_TBU12		57
+#define EIC7700_RESET_TCU_TBU13		58
+#define EIC7700_RESET_TCU_TBU14		59
+#define EIC7700_RESET_TCU_TBU15		60
+#define EIC7700_RESET_TCU_TBU16		61
+#define EIC7700_RESET_NPU_AXI		62
+#define EIC7700_RESET_NPU_CFG		63
+#define EIC7700_RESET_NPU_CORE		64
+#define EIC7700_RESET_NPU_E31CORE	65
+#define EIC7700_RESET_NPU_E31BUS	66
+#define EIC7700_RESET_NPU_E31DBG	67
+#define EIC7700_RESET_NPU_LLC		68
+#define EIC7700_RESET_HSP_AXI		69
+#define EIC7700_RESET_HSP_CFG		70
+#define EIC7700_RESET_HSP_POR		71
+#define EIC7700_RESET_MSHC0_PHY		72
+#define EIC7700_RESET_MSHC1_PHY		73
+#define EIC7700_RESET_MSHC2_PHY		74
+#define EIC7700_RESET_MSHC0_TXRX	75
+#define EIC7700_RESET_MSHC1_TXRX	76
+#define EIC7700_RESET_MSHC2_TXRX	77
+#define EIC7700_RESET_SATA_ASIC0	78
+#define EIC7700_RESET_SATA_OOB		79
+#define EIC7700_RESET_SATA_PMALIVE	80
+#define EIC7700_RESET_SATA_RBC		81
+#define EIC7700_RESET_DMA0		82
+#define EIC7700_RESET_HSP_DMA		83
+#define EIC7700_RESET_USB0_VAUX		84
+#define EIC7700_RESET_USB1_VAUX		85
+#define EIC7700_RESET_HSP_SD1_PRST	86
+#define EIC7700_RESET_HSP_SD0_PRST	87
+#define EIC7700_RESET_HSP_EMMC_PRST	88
+#define EIC7700_RESET_HSP_DMA_PRST	89
+#define EIC7700_RESET_HSP_SD1_ARST	90
+#define EIC7700_RESET_HSP_SD0_ARST	91
+#define EIC7700_RESET_HSP_EMMC_ARST	92
+#define EIC7700_RESET_HSP_DMA_ARST	93
+#define EIC7700_RESET_HSP_ETH1_ARST	94
+#define EIC7700_RESET_HSP_ETH0_ARST	95
+#define EIC7700_RESET_SATA_ARST		96
+#define EIC7700_RESET_PCIE_CFG		97
+#define EIC7700_RESET_PCIE_POWEUP	98
+#define EIC7700_RESET_PCIE_PERST	99
+#define EIC7700_RESET_I2C0		100
+#define EIC7700_RESET_I2C1		101
+#define EIC7700_RESET_I2C2		102
+#define EIC7700_RESET_I2C3		103
+#define EIC7700_RESET_I2C4		104
+#define EIC7700_RESET_I2C5		105
+#define EIC7700_RESET_I2C6		106
+#define EIC7700_RESET_I2C7		107
+#define EIC7700_RESET_I2C8		108
+#define EIC7700_RESET_I2C9		109
+#define EIC7700_RESET_FAN		110
+#define EIC7700_RESET_PVT0		111
+#define EIC7700_RESET_PVT1		112
+#define EIC7700_RESET_MBOX0		113
+#define EIC7700_RESET_MBOX1		114
+#define EIC7700_RESET_MBOX2		115
+#define EIC7700_RESET_MBOX3		116
+#define EIC7700_RESET_MBOX4		117
+#define EIC7700_RESET_MBOX5		118
+#define EIC7700_RESET_MBOX6		119
+#define EIC7700_RESET_MBOX7		120
+#define EIC7700_RESET_MBOX8		121
+#define EIC7700_RESET_MBOX9		122
+#define EIC7700_RESET_MBOX10		123
+#define EIC7700_RESET_MBOX11		124
+#define EIC7700_RESET_MBOX12		125
+#define EIC7700_RESET_MBOX13		126
+#define EIC7700_RESET_MBOX14		127
+#define EIC7700_RESET_MBOX15		128
+#define EIC7700_RESET_UART0		129
+#define EIC7700_RESET_UART1		130
+#define EIC7700_RESET_UART2		131
+#define EIC7700_RESET_UART3		132
+#define EIC7700_RESET_UART4		133
+#define EIC7700_RESET_GPIO0		134
+#define EIC7700_RESET_GPIO1		135
+#define EIC7700_RESET_TIMER		136
+#define EIC7700_RESET_SSI0		137
+#define EIC7700_RESET_SSI1		138
+#define EIC7700_RESET_WDT0		139
+#define EIC7700_RESET_WDT1		140
+#define EIC7700_RESET_WDT2		141
+#define EIC7700_RESET_WDT3		142
+#define EIC7700_RESET_LSP_CFG		143
+#define EIC7700_RESET_U84_CORE0		144
+#define EIC7700_RESET_U84_CORE1		145
+#define EIC7700_RESET_U84_CORE2		146
+#define EIC7700_RESET_U84_CORE3		147
+#define EIC7700_RESET_U84_BUS		148
+#define EIC7700_RESET_U84_DBG		149
+#define EIC7700_RESET_U84_TRACECOM	150
+#define EIC7700_RESET_U84_TRACE0	151
+#define EIC7700_RESET_U84_TRACE1	152
+#define EIC7700_RESET_U84_TRACE2	153
+#define EIC7700_RESET_U84_TRACE3	154
+#define EIC7700_RESET_SCPU_CORE		155
+#define EIC7700_RESET_SCPU_BUS		156
+#define EIC7700_RESET_SCPU_DBG		157
+#define EIC7700_RESET_LPCPU_CORE	158
+#define EIC7700_RESET_LPCPU_BUS		159
+#define EIC7700_RESET_LPCPU_DBG		160
+#define EIC7700_RESET_VC_CFG		161
+#define EIC7700_RESET_VC_AXI		162
+#define EIC7700_RESET_VC_MONCFG		163
+#define EIC7700_RESET_JD_CFG		164
+#define EIC7700_RESET_JD_AXI		165
+#define EIC7700_RESET_JE_CFG		166
+#define EIC7700_RESET_JE_AXI		167
+#define EIC7700_RESET_VD_CFG		168
+#define EIC7700_RESET_VD_AXI		169
+#define EIC7700_RESET_VE_AXI		170
+#define EIC7700_RESET_VE_CFG		171
+#define EIC7700_RESET_G2D_CORE		172
+#define EIC7700_RESET_G2D_CFG		173
+#define EIC7700_RESET_G2D_AXI		174
+#define EIC7700_RESET_VI_AXI		175
+#define EIC7700_RESET_VI_CFG		176
+#define EIC7700_RESET_VI_DWE		177
+#define EIC7700_RESET_DVP		178
+#define EIC7700_RESET_ISP0		179
+#define EIC7700_RESET_ISP1		180
+#define EIC7700_RESET_SHUTTR0		181
+#define EIC7700_RESET_SHUTTR1		182
+#define EIC7700_RESET_SHUTTR2		183
+#define EIC7700_RESET_SHUTTR3		184
+#define EIC7700_RESET_SHUTTR4		185
+#define EIC7700_RESET_SHUTTR5		186
+#define EIC7700_RESET_VO_MIPI		187
+#define EIC7700_RESET_VO_PRST		188
+#define EIC7700_RESET_VO_HDMI_PRST	189
+#define EIC7700_RESET_VO_HDMI_PHY	190
+#define EIC7700_RESET_VO_HDMI		191
+#define EIC7700_RESET_VO_I2S		192
+#define EIC7700_RESET_VO_I2S_PRST	193
+#define EIC7700_RESET_VO_AXI		194
+#define EIC7700_RESET_VO_CFG		195
+#define EIC7700_RESET_VO_DC		196
+#define EIC7700_RESET_VO_DC_PRST	197
+#define EIC7700_RESET_BOOTSPI_HRST	198
+#define EIC7700_RESET_BOOTSPI		199
+#define EIC7700_RESET_ANO1		200
+#define EIC7700_RESET_ANO0		201
+#define EIC7700_RESET_DMA1_ARST		202
+#define EIC7700_RESET_DMA1_HRST		203
+#define EIC7700_RESET_FPRT		204
+#define EIC7700_RESET_HBLOCK		205
+#define EIC7700_RESET_SECSR		206
+#define EIC7700_RESET_OTP		207
+#define EIC7700_RESET_PKA		208
+#define EIC7700_RESET_SPACC		209
+#define EIC7700_RESET_TRNG		210
+#define EIC7700_RESET_TIMER0_0		211
+#define EIC7700_RESET_TIMER0_1		212
+#define EIC7700_RESET_TIMER0_2		213
+#define EIC7700_RESET_TIMER0_3		214
+#define EIC7700_RESET_TIMER0_4		215
+#define EIC7700_RESET_TIMER0_5		216
+#define EIC7700_RESET_TIMER0_6		217
+#define EIC7700_RESET_TIMER0_7		218
+#define EIC7700_RESET_TIMER0_N		219
+#define EIC7700_RESET_TIMER1_0		220
+#define EIC7700_RESET_TIMER1_1		221
+#define EIC7700_RESET_TIMER1_2		222
+#define EIC7700_RESET_TIMER1_3		223
+#define EIC7700_RESET_TIMER1_4		224
+#define EIC7700_RESET_TIMER1_5		225
+#define EIC7700_RESET_TIMER1_6		226
+#define EIC7700_RESET_TIMER1_7		227
+#define EIC7700_RESET_TIMER1_N		228
+#define EIC7700_RESET_TIMER2_0		229
+#define EIC7700_RESET_TIMER2_1		230
+#define EIC7700_RESET_TIMER2_2		231
+#define EIC7700_RESET_TIMER2_3		232
+#define EIC7700_RESET_TIMER2_4		233
+#define EIC7700_RESET_TIMER2_5		234
+#define EIC7700_RESET_TIMER2_6		235
+#define EIC7700_RESET_TIMER2_7		236
+#define EIC7700_RESET_TIMER2_N		237
+#define EIC7700_RESET_TIMER3_0		238
+#define EIC7700_RESET_TIMER3_1		239
+#define EIC7700_RESET_TIMER3_2		240
+#define EIC7700_RESET_TIMER3_3		241
+#define EIC7700_RESET_TIMER3_4		242
+#define EIC7700_RESET_TIMER3_5		243
+#define EIC7700_RESET_TIMER3_6		244
+#define EIC7700_RESET_TIMER3_7		245
+#define EIC7700_RESET_TIMER3_N		246
+#define EIC7700_RESET_RTC		247
+#define EIC7700_RESET_MNOC_SNOC_NSP	248
+#define EIC7700_RESET_MNOC_VC		249
+#define EIC7700_RESET_MNOC_CFG		250
+#define EIC7700_RESET_MNOC_HSP		251
+#define EIC7700_RESET_MNOC_GPU		252
+#define EIC7700_RESET_MNOC_DDRC1_P3	253
+#define EIC7700_RESET_MNOC_DDRC0_P3	254
+#define EIC7700_RESET_RNOC_VO		255
+#define EIC7700_RESET_RNOC_VI		256
+#define EIC7700_RESET_RNOC_SNOC_NSP	257
+#define EIC7700_RESET_RNOC_CFG		258
+#define EIC7700_RESET_MNOC_DDRC1_P4	259
+#define EIC7700_RESET_MNOC_DDRC0_P4	260
+#define EIC7700_RESET_CNOC_VO_CFG	261
+#define EIC7700_RESET_CNOC_VI_CFG	262
+#define EIC7700_RESET_CNOC_VC_CFG	263
+#define EIC7700_RESET_CNOC_TCU_CFG	264
+#define EIC7700_RESET_CNOC_PCIE_CFG	265
+#define EIC7700_RESET_CNOC_NPU_CFG	266
+#define EIC7700_RESET_CNOC_LSP_CFG	267
+#define EIC7700_RESET_CNOC_HSP_CFG	268
+#define EIC7700_RESET_CNOC_GPU_CFG	269
+#define EIC7700_RESET_CNOC_DSPT_CFG	270
+#define EIC7700_RESET_CNOC_DDRT1_CFG	271
+#define EIC7700_RESET_CNOC_DDRT0_CFG	272
+#define EIC7700_RESET_CNOC_D2D_CFG	273
+#define EIC7700_RESET_CNOC_CFG		274
+#define EIC7700_RESET_CNOC_CLMM_CFG	275
+#define EIC7700_RESET_CNOC_AON_CFG	276
+#define EIC7700_RESET_LNOC_CFG		277
+#define EIC7700_RESET_LNOC_NPU_LLC	278
+#define EIC7700_RESET_LNOC_DDRC1_P0	279
+#define EIC7700_RESET_LNOC_DDRC0_P0	280
+
+#endif /* __DT_ESWIN_EIC7700_RESET_H__ */
diff --git a/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h b/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
new file mode 100644
index 00000000000..adf95bb26d2
--- /dev/null
+++ b/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H
+#define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H
+
+#define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST	0
+#define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST		1
+#define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL	2
+#define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N		3
+#define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N		4
+#define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N		5
+
+#endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */
diff --git a/include/dt-bindings/reset/qcom,ipq5424-nsscc.h b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h
new file mode 100644
index 00000000000..9627e3b0ad3
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H
+#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H
+
+#define NSS_CC_CE_APB_CLK_ARES					0
+#define NSS_CC_CE_AXI_CLK_ARES					1
+#define NSS_CC_DEBUG_CLK_ARES					2
+#define NSS_CC_EIP_CLK_ARES					3
+#define NSS_CC_NSS_CSR_CLK_ARES					4
+#define NSS_CC_NSSNOC_CE_APB_CLK_ARES				5
+#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES				6
+#define NSS_CC_NSSNOC_EIP_CLK_ARES				7
+#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES				8
+#define NSS_CC_NSSNOC_PPE_CLK_ARES				9
+#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES				10
+#define NSS_CC_PORT1_MAC_CLK_ARES				11
+#define NSS_CC_PORT1_RX_CLK_ARES				12
+#define NSS_CC_PORT1_TX_CLK_ARES				13
+#define NSS_CC_PORT2_MAC_CLK_ARES				14
+#define NSS_CC_PORT2_RX_CLK_ARES				15
+#define NSS_CC_PORT2_TX_CLK_ARES				16
+#define NSS_CC_PORT3_MAC_CLK_ARES				17
+#define NSS_CC_PORT3_RX_CLK_ARES				18
+#define NSS_CC_PORT3_TX_CLK_ARES				19
+#define NSS_CC_PPE_BCR						20
+#define NSS_CC_PPE_EDMA_CLK_ARES				21
+#define NSS_CC_PPE_EDMA_CFG_CLK_ARES				22
+#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES				23
+#define NSS_CC_PPE_SWITCH_CLK_ARES				24
+#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES				25
+#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES				26
+#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES				27
+#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES				28
+#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES				29
+#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES				30
+#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES				31
+#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES				32
+#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES				33
+#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES				34
+#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES				35
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rk3506-cru.h b/include/dt-bindings/reset/rockchip,rk3506-cru.h
new file mode 100644
index 00000000000..31c0d4aa410
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3506-cru.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
+#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
+
+/* CRU-->SOFTRST_CON00 */
+#define SRST_NCOREPORESET0_AC	0
+#define SRST_NCOREPORESET1_AC	1
+#define SRST_NCOREPORESET2_AC	2
+#define SRST_NCORESET0_AC	3
+#define SRST_NCORESET1_AC	4
+#define SRST_NCORESET2_AC	5
+#define SRST_NL2RESET_AC	6
+#define SRST_A_CORE_BIU_AC	7
+#define SRST_H_M0_AC		8
+
+/* CRU-->SOFTRST_CON02 */
+#define SRST_NDBGRESET		9
+#define SRST_P_CORE_BIU		10
+#define SRST_PMU		11
+
+/* CRU-->SOFTRST_CON03 */
+#define SRST_P_DBG		12
+#define SRST_POT_DBG		13
+#define SRST_P_CORE_GRF		14
+#define SRST_CORE_EMA_DETECT	15
+#define SRST_REF_PVTPLL_CORE	16
+#define SRST_P_GPIO1		17
+#define SRST_DB_GPIO1		18
+
+/* CRU-->SOFTRST_CON04 */
+#define SRST_A_CORE_PERI_BIU	19
+#define SRST_A_DSMC		20
+#define SRST_P_DSMC		21
+#define SRST_FLEXBUS		22
+#define SRST_A_FLEXBUS		23
+#define SRST_H_FLEXBUS		24
+#define SRST_A_DSMC_SLV		25
+#define SRST_H_DSMC_SLV		26
+#define SRST_DSMC_SLV		27
+
+/* CRU-->SOFTRST_CON05 */
+#define SRST_A_BUS_BIU		28
+#define SRST_H_BUS_BIU		29
+#define SRST_P_BUS_BIU		30
+#define SRST_A_SYSRAM		31
+#define SRST_H_SYSRAM		32
+#define SRST_A_DMAC0		33
+#define SRST_A_DMAC1		34
+#define SRST_H_M0		35
+#define SRST_M0_JTAG		36
+#define SRST_H_CRYPTO		37
+
+/* CRU-->SOFTRST_CON06 */
+#define SRST_H_RNG		38
+#define SRST_P_BUS_GRF		39
+#define SRST_P_TIMER0		40
+#define SRST_TIMER0_CH0		41
+#define SRST_TIMER0_CH1		42
+#define SRST_TIMER0_CH2		43
+#define SRST_TIMER0_CH3		44
+#define SRST_TIMER0_CH4		45
+#define SRST_TIMER0_CH5		46
+#define SRST_P_WDT0		47
+#define SRST_T_WDT0		48
+#define SRST_P_WDT1		49
+#define SRST_T_WDT1		50
+#define SRST_P_MAILBOX		51
+#define SRST_P_INTMUX		52
+#define SRST_P_SPINLOCK		53
+
+/* CRU-->SOFTRST_CON07 */
+#define SRST_P_DDRC		54
+#define SRST_H_DDRPHY		55
+#define SRST_P_DDRMON		56
+#define SRST_DDRMON_OSC		57
+#define SRST_P_DDR_LPC		58
+#define SRST_H_USBOTG0		59
+#define SRST_USBOTG0_ADP	60
+#define SRST_H_USBOTG1		61
+#define SRST_USBOTG1_ADP	62
+#define SRST_P_USBPHY		63
+#define SRST_USBPHY_POR		64
+#define SRST_USBPHY_OTG0	65
+#define SRST_USBPHY_OTG1	66
+
+/* CRU-->SOFTRST_CON08 */
+#define SRST_A_DMA2DDR		67
+#define SRST_P_DMA2DDR		68
+
+/* CRU-->SOFTRST_CON09 */
+#define SRST_USBOTG0_UTMI	69
+#define SRST_USBOTG1_UTMI	70
+
+/* CRU-->SOFTRST_CON10 */
+#define SRST_A_DDRC_0		71
+#define SRST_A_DDRC_1		72
+#define SRST_A_DDR_BIU		73
+#define SRST_DDRC		74
+#define SRST_DDRMON		75
+
+/* CRU-->SOFTRST_CON11 */
+#define SRST_H_LSPERI_BIU	76
+#define SRST_P_UART0		77
+#define SRST_P_UART1		78
+#define SRST_P_UART2		79
+#define SRST_P_UART3		80
+#define SRST_P_UART4		81
+#define SRST_UART0		82
+#define SRST_UART1		83
+#define SRST_UART2		84
+#define SRST_UART3		85
+#define SRST_UART4		86
+#define SRST_P_I2C0		87
+#define SRST_I2C0		88
+
+/* CRU-->SOFTRST_CON12 */
+#define SRST_P_I2C1		89
+#define SRST_I2C1		90
+#define SRST_P_I2C2		91
+#define SRST_I2C2		92
+#define SRST_P_PWM1		93
+#define SRST_PWM1		94
+#define SRST_P_SPI0		95
+#define SRST_SPI0		96
+#define SRST_P_SPI1		97
+#define SRST_SPI1		98
+#define SRST_P_GPIO2		99
+#define SRST_DB_GPIO2		100
+
+/* CRU-->SOFTRST_CON13 */
+#define SRST_P_GPIO3		101
+#define SRST_DB_GPIO3		102
+#define SRST_P_GPIO4		103
+#define SRST_DB_GPIO4		104
+#define SRST_H_CAN0		105
+#define SRST_CAN0		106
+#define SRST_H_CAN1		107
+#define SRST_CAN1		108
+#define SRST_H_PDM		109
+#define SRST_M_PDM		110
+#define SRST_PDM		111
+#define SRST_SPDIFTX		112
+#define SRST_H_SPDIFTX		113
+#define SRST_H_SPDIFRX		114
+#define SRST_SPDIFRX		115
+#define SRST_M_SAI0		116
+
+/* CRU-->SOFTRST_CON14 */
+#define SRST_H_SAI0		117
+#define SRST_M_SAI1		118
+#define SRST_H_SAI1		119
+#define SRST_H_ASRC0		120
+#define SRST_ASRC0		121
+#define SRST_H_ASRC1		122
+#define SRST_ASRC1		123
+
+/* CRU-->SOFTRST_CON17 */
+#define SRST_H_HSPERI_BIU	124
+#define SRST_H_SDMMC		125
+#define SRST_H_FSPI		126
+#define SRST_S_FSPI		127
+#define SRST_P_SPI2		128
+#define SRST_A_MAC0		129
+#define SRST_A_MAC1		130
+
+/* CRU-->SOFTRST_CON18 */
+#define SRST_M_SAI2		131
+#define SRST_H_SAI2		132
+#define SRST_H_SAI3		133
+#define SRST_M_SAI3		134
+#define SRST_H_SAI4		135
+#define SRST_M_SAI4		136
+#define SRST_H_DSM		137
+#define SRST_M_DSM		138
+#define SRST_P_AUDIO_ADC	139
+#define SRST_M_AUDIO_ADC	140
+
+/* CRU-->SOFTRST_CON19 */
+#define SRST_P_SARADC		141
+#define SRST_SARADC		142
+#define SRST_SARADC_PHY		143
+#define SRST_P_OTPC_NS		144
+#define SRST_SBPI_OTPC_NS	145
+#define SRST_USER_OTPC_NS	146
+#define SRST_P_UART5		147
+#define SRST_UART5		148
+#define SRST_P_GPIO234_IOC	149
+
+/* CRU-->SOFTRST_CON21 */
+#define SRST_A_VIO_BIU		150
+#define SRST_H_VIO_BIU		151
+#define SRST_H_RGA		152
+#define SRST_A_RGA		153
+#define SRST_CORE_RGA		154
+#define SRST_A_VOP		155
+#define SRST_H_VOP		156
+#define SRST_VOP		157
+#define SRST_P_DPHY		158
+#define SRST_P_DSI_HOST		159
+#define SRST_P_TSADC		160
+#define SRST_TSADC		161
+
+/* CRU-->SOFTRST_CON22 */
+#define SRST_P_GPIO1_IOC	162
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rv1126b-cru.h b/include/dt-bindings/reset/rockchip,rv1126b-cru.h
new file mode 100644
index 00000000000..a7712db319d
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rv1126b-cru.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H
+
+/* ==========================list all of reset fields id=========================== */
+/* TOPCRU-->SOFTRST_CON00 */
+
+/* TOPCRU-->SOFTRST_CON15 */
+#define SRST_P_CRU				0
+#define SRST_P_CRU_BIU				1
+
+/* BUSCRU-->SOFTRST_CON00 */
+#define SRST_A_TOP_BIU				2
+#define SRST_A_RKCE_BIU				3
+#define SRST_A_BUS_BIU				4
+#define SRST_H_BUS_BIU				5
+#define SRST_P_BUS_BIU				6
+#define SRST_P_CRU_BUS				7
+#define SRST_P_SYS_GRF				8
+#define SRST_H_BOOTROM				9
+#define SRST_A_GIC400				10
+#define SRST_A_SPINLOCK				11
+#define SRST_P_WDT_NS				12
+#define SRST_T_WDT_NS				13
+
+/* BUSCRU-->SOFTRST_CON01 */
+#define SRST_P_WDT_HPMCU			14
+#define SRST_T_WDT_HPMCU			15
+#define SRST_H_CACHE				16
+#define SRST_P_HPMCU_MAILBOX			17
+#define SRST_P_HPMCU_INTMUX			18
+#define SRST_HPMCU_FULL_CLUSTER			19
+#define SRST_HPMCU_PWUP				20
+#define SRST_HPMCU_ONLY_CORE			21
+#define SRST_T_HPMCU_JTAG			22
+#define SRST_P_RKDMA				23
+#define SRST_A_RKDMA				24
+
+/* BUSCRU-->SOFTRST_CON02 */
+#define SRST_P_DCF				25
+#define SRST_A_DCF				26
+#define SRST_H_RGA				27
+#define SRST_A_RGA				28
+#define SRST_CORE_RGA				29
+#define SRST_P_TIMER				30
+#define SRST_TIMER0				31
+#define SRST_TIMER1				32
+#define SRST_TIMER2				33
+#define SRST_TIMER3				34
+#define SRST_TIMER4				35
+#define SRST_TIMER5				36
+#define SRST_A_RKCE				37
+#define SRST_PKA_RKCE				38
+#define SRST_H_RKRNG_S				39
+#define SRST_H_RKRNG_NS				40
+
+/* BUSCRU-->SOFTRST_CON03 */
+#define SRST_P_I2C0				41
+#define SRST_I2C0				42
+#define SRST_P_I2C1				43
+#define SRST_I2C1				44
+#define SRST_P_I2C3				45
+#define SRST_I2C3				46
+#define SRST_P_I2C4				47
+#define SRST_I2C4				48
+#define SRST_P_I2C5				49
+#define SRST_I2C5				50
+#define SRST_P_SPI0				51
+#define SRST_SPI0				52
+#define SRST_P_SPI1				53
+#define SRST_SPI1				54
+
+/* BUSCRU-->SOFTRST_CON04 */
+#define SRST_P_PWM0				55
+#define SRST_PWM0				56
+#define SRST_P_PWM2				57
+#define SRST_PWM2				58
+#define SRST_P_PWM3				59
+#define SRST_PWM3				60
+
+/* BUSCRU-->SOFTRST_CON05 */
+#define SRST_P_UART1				61
+#define SRST_S_UART1				62
+#define SRST_P_UART2				63
+#define SRST_S_UART2				64
+#define SRST_P_UART3				65
+#define SRST_S_UART3				66
+#define SRST_P_UART4				67
+#define SRST_S_UART4				68
+#define SRST_P_UART5				69
+#define SRST_S_UART5				70
+#define SRST_P_UART6				71
+#define SRST_S_UART6				72
+#define SRST_P_UART7				73
+#define SRST_S_UART7				74
+
+/* BUSCRU-->SOFTRST_CON06 */
+#define SRST_P_TSADC				75
+#define SRST_TSADC				76
+#define SRST_H_SAI0				77
+#define SRST_M_SAI0				78
+#define SRST_H_SAI1				79
+#define SRST_M_SAI1				80
+#define SRST_H_SAI2				81
+#define SRST_M_SAI2				82
+#define SRST_H_RKDSM				83
+#define SRST_M_RKDSM				84
+#define SRST_H_PDM				85
+#define SRST_M_PDM				86
+#define SRST_PDM				87
+
+/* BUSCRU-->SOFTRST_CON07 */
+#define SRST_H_ASRC0				88
+#define SRST_ASRC0				89
+#define SRST_H_ASRC1				90
+#define SRST_ASRC1				91
+#define SRST_P_AUDIO_ADC_BUS			92
+#define SRST_M_AUDIO_ADC_BUS			93
+#define SRST_P_RKCE				94
+#define SRST_H_NS_RKCE				95
+#define SRST_P_OTPC_NS				96
+#define SRST_SBPI_OTPC_NS			97
+#define SRST_USER_OTPC_NS			98
+#define SRST_OTPC_ARB				99
+#define SRST_P_OTP_MASK				100
+
+/* PERICRU-->SOFTRST_CON00 */
+#define SRST_A_PERI_BIU				101
+#define SRST_P_PERI_BIU				102
+#define SRST_P_RTC_BIU				103
+#define SRST_P_CRU_PERI				104
+#define SRST_P_PERI_GRF				105
+#define SRST_P_GPIO1				106
+#define SRST_DB_GPIO1				107
+#define SRST_P_IOC_VCCIO1			108
+#define SRST_A_USB3OTG				109
+#define SRST_H_USB2HOST				110
+#define SRST_H_ARB_USB2HOST			111
+#define SRST_P_RTC_TEST				112
+
+/* PERICRU-->SOFTRST_CON01 */
+#define SRST_H_EMMC				113
+#define SRST_H_FSPI0				114
+#define SRST_H_XIP_FSPI0			115
+#define SRST_S_2X_FSPI0				116
+#define SRST_UTMI_USB2HOST			117
+#define SRST_REF_PIPEPHY			118
+#define SRST_P_PIPEPHY				119
+#define SRST_P_PIPEPHY_GRF			120
+#define SRST_P_USB2PHY				121
+#define SRST_POR_USB2PHY			122
+#define SRST_OTG_USB2PHY			123
+#define SRST_HOST_USB2PHY			124
+
+/* CORECRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_CORE			125
+#define SRST_NCOREPORESET0			126
+#define SRST_NCORESET0				127
+#define SRST_NCOREPORESET1			128
+#define SRST_NCORESET1				129
+#define SRST_NCOREPORESET2			130
+#define SRST_NCORESET2				131
+#define SRST_NCOREPORESET3			132
+#define SRST_NCORESET3				133
+#define SRST_NDBGRESET				134
+#define SRST_NL2RESET				135
+
+/* CORECRU-->SOFTRST_CON01 */
+#define SRST_A_CORE_BIU				136
+#define SRST_P_CORE_BIU				137
+#define SRST_H_CORE_BIU				138
+#define SRST_P_DBG				139
+#define SRST_POT_DBG				140
+#define SRST_NT_DBG				141
+#define SRST_P_CORE_PVTPLL			142
+#define SRST_P_CRU_CORE				143
+#define SRST_P_CORE_GRF				144
+#define SRST_P_DFT2APB				145
+
+/* PMUCRU-->SOFTRST_CON00 */
+#define SRST_H_PMU_BIU				146
+#define SRST_P_PMU_GPIO0			147
+#define SRST_DB_PMU_GPIO0			148
+#define SRST_P_PMU_HP_TIMER			149
+#define SRST_PMU_HP_TIMER			150
+#define SRST_PMU_32K_HP_TIMER			151
+
+/* PMUCRU-->SOFTRST_CON01 */
+#define SRST_P_PWM1				152
+#define SRST_PWM1				153
+#define SRST_P_I2C2				154
+#define SRST_I2C2				155
+#define SRST_P_UART0				156
+#define SRST_S_UART0				157
+
+/* PMUCRU-->SOFTRST_CON02 */
+#define SRST_P_RCOSC_CTRL			158
+#define SRST_REF_RCOSC_CTRL			159
+#define SRST_P_IOC_PMUIO0			160
+#define SRST_P_CRU_PMU				161
+#define SRST_P_PMU_GRF				162
+#define SRST_PREROLL				163
+#define SRST_PREROLL_32K			164
+#define SRST_H_PMU_SRAM				165
+
+/* PMUCRU-->SOFTRST_CON03 */
+#define SRST_P_WDT_LPMCU			166
+#define SRST_T_WDT_LPMCU			167
+#define SRST_LPMCU_FULL_CLUSTER			168
+#define SRST_LPMCU_PWUP				169
+#define SRST_LPMCU_ONLY_CORE			170
+#define SRST_T_LPMCU_JTAG			171
+#define SRST_P_LPMCU_MAILBOX			172
+
+/* PMU1CRU-->SOFTRST_CON00 */
+#define SRST_P_SPI2AHB				173
+#define SRST_H_SPI2AHB				174
+#define SRST_H_FSPI1				175
+#define SRST_H_XIP_FSPI1			176
+#define SRST_S_1X_FSPI1				177
+#define SRST_P_IOC_PMUIO1			178
+#define SRST_P_CRU_PMU1				179
+#define SRST_P_AUDIO_ADC_PMU			180
+#define SRST_M_AUDIO_ADC_PMU			181
+#define SRST_H_PMU1_BIU				182
+
+/* PMU1CRU-->SOFTRST_CON01 */
+#define SRST_P_LPDMA				183
+#define SRST_A_LPDMA				184
+#define SRST_H_LPSAI				185
+#define SRST_M_LPSAI				186
+#define SRST_P_AOA_TDD				187
+#define SRST_P_AOA_FE				188
+#define SRST_P_AOA_AAD				189
+#define SRST_P_AOA_APB				190
+#define SRST_P_AOA_SRAM				191
+
+/* DDRCRU-->SOFTRST_CON00 */
+#define SRST_P_DDR_BIU				192
+#define SRST_P_DDRC				193
+#define SRST_P_DDRMON				194
+#define SRST_TIMER_DDRMON			195
+#define SRST_P_DFICTRL				196
+#define SRST_P_DDR_GRF				197
+#define SRST_P_CRU_DDR				198
+#define SRST_P_DDRPHY				199
+#define SRST_P_DMA2DDR				200
+
+/* SUBDDRCRU-->SOFTRST_CON00 */
+#define SRST_A_SYSMEM_BIU			201
+#define SRST_A_SYSMEM				202
+#define SRST_A_DDR_BIU				203
+#define SRST_A_DDRSCH0_CPU			204
+#define SRST_A_DDRSCH1_NPU			205
+#define SRST_A_DDRSCH2_POE			206
+#define SRST_A_DDRSCH3_VI			207
+#define SRST_CORE_DDRC				208
+#define SRST_DDRMON				209
+#define SRST_DFICTRL				210
+#define SRST_RS					211
+#define SRST_A_DMA2DDR				212
+#define SRST_DDRPHY				213
+
+/* VICRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_ISP			214
+#define SRST_A_GMAC_BIU				215
+#define SRST_A_VI_BIU				216
+#define SRST_H_VI_BIU				217
+#define SRST_P_VI_BIU				218
+#define SRST_P_CRU_VI				219
+#define SRST_P_VI_GRF				220
+#define SRST_P_VI_PVTPLL			221
+#define SRST_P_DSMC				222
+#define SRST_A_DSMC				223
+#define SRST_H_CAN0				224
+#define SRST_CAN0				225
+#define SRST_H_CAN1				226
+#define SRST_CAN1				227
+
+/* VICRU-->SOFTRST_CON01 */
+#define SRST_P_GPIO2				228
+#define SRST_DB_GPIO2				229
+#define SRST_P_GPIO4				230
+#define SRST_DB_GPIO4				231
+#define SRST_P_GPIO5				232
+#define SRST_DB_GPIO5				233
+#define SRST_P_GPIO6				234
+#define SRST_DB_GPIO6				235
+#define SRST_P_GPIO7				236
+#define SRST_DB_GPIO7				237
+#define SRST_P_IOC_VCCIO2			238
+#define SRST_P_IOC_VCCIO4			239
+#define SRST_P_IOC_VCCIO5			240
+#define SRST_P_IOC_VCCIO6			241
+#define SRST_P_IOC_VCCIO7			242
+
+/* VICRU-->SOFTRST_CON02 */
+#define SRST_CORE_ISP				243
+#define SRST_H_VICAP				244
+#define SRST_A_VICAP				245
+#define SRST_D_VICAP				246
+#define SRST_ISP0_VICAP				247
+#define SRST_CORE_VPSS				248
+#define SRST_CORE_VPSL				249
+#define SRST_P_CSI2HOST0			250
+#define SRST_P_CSI2HOST1			251
+#define SRST_P_CSI2HOST2			252
+#define SRST_P_CSI2HOST3			253
+#define SRST_H_SDMMC0				254
+#define SRST_A_GMAC				255
+#define SRST_P_CSIPHY0				256
+#define SRST_P_CSIPHY1				257
+
+/* VICRU-->SOFTRST_CON03 */
+#define SRST_P_MACPHY				258
+#define SRST_MACPHY				259
+#define SRST_P_SARADC1				260
+#define SRST_SARADC1				261
+#define SRST_P_SARADC2				262
+#define SRST_SARADC2				263
+
+/* VEPUCRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_VEPU			264
+#define SRST_A_VEPU_BIU				265
+#define SRST_H_VEPU_BIU				266
+#define SRST_P_VEPU_BIU				267
+#define SRST_P_CRU_VEPU				268
+#define SRST_P_VEPU_GRF				269
+#define SRST_P_GPIO3				270
+#define SRST_DB_GPIO3				271
+#define SRST_P_IOC_VCCIO3			272
+#define SRST_P_SARADC0				273
+#define SRST_SARADC0				274
+#define SRST_H_SDMMC1				275
+
+/* VEPUCRU-->SOFTRST_CON01 */
+#define SRST_P_VEPU_PVTPLL			276
+#define SRST_H_VEPU				277
+#define SRST_A_VEPU				278
+#define SRST_CORE_VEPU				279
+
+/* NPUCRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_NPU			280
+#define SRST_A_NPU_BIU				281
+#define SRST_H_NPU_BIU				282
+#define SRST_P_NPU_BIU				283
+#define SRST_P_CRU_NPU				284
+#define SRST_P_NPU_GRF				285
+#define SRST_P_NPU_PVTPLL			286
+#define SRST_H_RKNN				287
+#define SRST_A_RKNN				288
+
+/* VDOCRU-->SOFTRST_CON00 */
+#define SRST_A_RKVDEC_BIU			289
+#define SRST_A_VDO_BIU				290
+#define SRST_H_VDO_BIU				291
+#define SRST_P_VDO_BIU				292
+#define SRST_P_CRU_VDO				293
+#define SRST_P_VDO_GRF				294
+#define SRST_A_RKVDEC				295
+#define SRST_H_RKVDEC				296
+#define SRST_HEVC_CA_RKVDEC			297
+#define SRST_A_VOP				298
+#define SRST_H_VOP				299
+#define SRST_D_VOP				300
+#define SRST_A_OOC				301
+#define SRST_H_OOC				302
+#define SRST_D_OOC				303
+
+/* VDOCRU-->SOFTRST_CON01 */
+#define SRST_H_RKJPEG				304
+#define SRST_A_RKJPEG				305
+#define SRST_A_RKMMU_DECOM			306
+#define SRST_H_RKMMU_DECOM			307
+#define SRST_D_DECOM				308
+#define SRST_A_DECOM				309
+#define SRST_P_DECOM				310
+#define SRST_P_MIPI_DSI				311
+#define SRST_P_DSIPHY				312
+
+/* VCPCRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_VCP			313
+#define SRST_A_VCP_BIU				314
+#define SRST_H_VCP_BIU				315
+#define SRST_P_VCP_BIU				316
+#define SRST_P_CRU_VCP				317
+#define SRST_P_VCP_GRF				318
+#define SRST_P_VCP_PVTPLL			319
+#define SRST_A_AISP_BIU				320
+#define SRST_H_AISP_BIU				321
+#define SRST_CORE_AISP				322
+
+/* VCPCRU-->SOFTRST_CON01 */
+#define SRST_H_FEC				323
+#define SRST_A_FEC				324
+#define SRST_CORE_FEC				325
+#define SRST_H_AVSP				326
+#define SRST_A_AVSP				327
+
+#endif
diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
index ee799286c17..ba6805b6b12 100644
--- a/include/dt-bindings/reset/thead,th1520-reset.h
+++ b/include/dt-bindings/reset/thead,th1520-reset.h
@@ -7,11 +7,202 @@
 #ifndef _DT_BINDINGS_TH1520_RESET_H
 #define _DT_BINDINGS_TH1520_RESET_H
 
+/* AO Subsystem */
+#define TH1520_RESET_ID_SYSTEM		0
+#define TH1520_RESET_ID_RTC_APB		1
+#define TH1520_RESET_ID_RTC_REF		2
+#define TH1520_RESET_ID_AOGPIO_DB	3
+#define TH1520_RESET_ID_AOGPIO_APB	4
+#define TH1520_RESET_ID_AOI2C_APB	5
+#define TH1520_RESET_ID_PVT_APB		6
+#define TH1520_RESET_ID_E902_CORE	7
+#define TH1520_RESET_ID_E902_HAD	8
+#define TH1520_RESET_ID_AOTIMER_APB	9
+#define TH1520_RESET_ID_AOTIMER_CORE	10
+#define TH1520_RESET_ID_AOWDT_APB	11
+#define TH1520_RESET_ID_APSYS		12
+#define TH1520_RESET_ID_NPUSYS		13
+#define TH1520_RESET_ID_DDRSYS		14
+#define TH1520_RESET_ID_AXI_AP2CP	15
+#define TH1520_RESET_ID_AXI_CP2AP	16
+#define TH1520_RESET_ID_AXI_CP2SRAM	17
+#define TH1520_RESET_ID_AUDSYS_CORE	18
+#define TH1520_RESET_ID_AUDSYS_IOPMP	19
+#define TH1520_RESET_ID_AUDSYS		20
+#define TH1520_RESET_ID_DSP0		21
+#define TH1520_RESET_ID_DSP1		22
+#define TH1520_RESET_ID_GPU_MODULE	23
+#define TH1520_RESET_ID_VDEC		24
+#define TH1520_RESET_ID_VENC		25
+#define TH1520_RESET_ID_ADC_APB		26
+#define TH1520_RESET_ID_AUDGPIO_DB	27
+#define TH1520_RESET_ID_AUDGPIO_APB	28
+#define TH1520_RESET_ID_AOUART_IF	29
+#define TH1520_RESET_ID_AOUART_APB	30
+#define TH1520_RESET_ID_SRAM_AXI_P0	31
+#define TH1520_RESET_ID_SRAM_AXI_P1	32
+#define TH1520_RESET_ID_SRAM_AXI_P2	33
+#define TH1520_RESET_ID_SRAM_AXI_P3	34
+#define TH1520_RESET_ID_SRAM_AXI_P4	35
+#define TH1520_RESET_ID_SRAM_AXI_CORE	36
+#define TH1520_RESET_ID_SE		37
+
+/* AP Subsystem */
+#define TH1520_RESET_ID_BROM			0
+#define TH1520_RESET_ID_C910_TOP		1
+#define TH1520_RESET_ID_NPU			2
+#define TH1520_RESET_ID_WDT0			3
+#define TH1520_RESET_ID_WDT1			4
+#define TH1520_RESET_ID_C910_C0			5
+#define TH1520_RESET_ID_C910_C1			6
+#define TH1520_RESET_ID_C910_C2			7
+#define TH1520_RESET_ID_C910_C3			8
+#define TH1520_RESET_ID_CHIP_DBG_CORE		9
+#define TH1520_RESET_ID_CHIP_DBG_AXI		10
+#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI	11
+#define TH1520_RESET_ID_AXI4_CPUSYS2_APB	12
+#define TH1520_RESET_ID_X2H_CPUSYS		13
+#define TH1520_RESET_ID_AHB2_CPUSYS		14
+#define TH1520_RESET_ID_APB3_CPUSYS		15
+#define TH1520_RESET_ID_MBOX0_APB		16
+#define TH1520_RESET_ID_MBOX1_APB		17
+#define TH1520_RESET_ID_MBOX2_APB		18
+#define TH1520_RESET_ID_MBOX3_APB		19
+#define TH1520_RESET_ID_TIMER0_APB		20
+#define TH1520_RESET_ID_TIMER0_CORE		21
+#define TH1520_RESET_ID_TIMER1_APB		22
+#define TH1520_RESET_ID_TIMER1_CORE		23
+#define TH1520_RESET_ID_PERISYS_AHB		24
+#define TH1520_RESET_ID_PERISYS_APB1		25
+#define TH1520_RESET_ID_PERISYS_APB2		26
+#define TH1520_RESET_ID_GMAC0_APB		27
+#define TH1520_RESET_ID_GMAC0_AHB		28
+#define TH1520_RESET_ID_GMAC0_CLKGEN		29
+#define TH1520_RESET_ID_GMAC0_AXI		30
+#define TH1520_RESET_ID_UART0_APB		31
+#define TH1520_RESET_ID_UART0_IF		32
+#define TH1520_RESET_ID_UART1_APB		33
+#define TH1520_RESET_ID_UART1_IF		34
+#define TH1520_RESET_ID_UART2_APB		35
+#define TH1520_RESET_ID_UART2_IF		36
+#define TH1520_RESET_ID_UART3_APB		37
+#define TH1520_RESET_ID_UART3_IF		38
+#define TH1520_RESET_ID_UART4_APB		39
+#define TH1520_RESET_ID_UART4_IF		40
+#define TH1520_RESET_ID_UART5_APB		41
+#define TH1520_RESET_ID_UART5_IF		42
+#define TH1520_RESET_ID_QSPI0_IF		43
+#define TH1520_RESET_ID_QSPI0_APB		44
+#define TH1520_RESET_ID_QSPI1_IF		45
+#define TH1520_RESET_ID_QSPI1_APB		46
+#define TH1520_RESET_ID_SPI_IF			47
+#define TH1520_RESET_ID_SPI_APB			48
+#define TH1520_RESET_ID_I2C0_APB		49
+#define TH1520_RESET_ID_I2C0_CORE		50
+#define TH1520_RESET_ID_I2C1_APB		51
+#define TH1520_RESET_ID_I2C1_CORE		52
+#define TH1520_RESET_ID_I2C2_APB		53
+#define TH1520_RESET_ID_I2C2_CORE		54
+#define TH1520_RESET_ID_I2C3_APB		55
+#define TH1520_RESET_ID_I2C3_CORE		56
+#define TH1520_RESET_ID_I2C4_APB		57
+#define TH1520_RESET_ID_I2C4_CORE		58
+#define TH1520_RESET_ID_I2C5_APB		59
+#define TH1520_RESET_ID_I2C5_CORE		60
+#define TH1520_RESET_ID_GPIO0_DB		61
+#define TH1520_RESET_ID_GPIO0_APB		62
+#define TH1520_RESET_ID_GPIO1_DB		63
+#define TH1520_RESET_ID_GPIO1_APB		64
+#define TH1520_RESET_ID_GPIO2_DB		65
+#define TH1520_RESET_ID_GPIO2_APB		66
+#define TH1520_RESET_ID_PWM_COUNTER		67
+#define TH1520_RESET_ID_PWM_APB			68
+#define TH1520_RESET_ID_PADCTRL0_APB		69
+#define TH1520_RESET_ID_CPU2PERI_X2H		70
+#define TH1520_RESET_ID_CPU2AON_X2H		71
+#define TH1520_RESET_ID_AON2CPU_A2X		72
+#define TH1520_RESET_ID_NPUSYS_AXI		73
+#define TH1520_RESET_ID_NPUSYS_AXI_APB		74
+#define TH1520_RESET_ID_CPU2VP_X2P		75
+#define TH1520_RESET_ID_CPU2VI_X2H		76
+#define TH1520_RESET_ID_BMU_AXI			77
+#define TH1520_RESET_ID_BMU_APB			78
+#define TH1520_RESET_ID_DMAC_CPUSYS_AXI		79
+#define TH1520_RESET_ID_DMAC_CPUSYS_AHB		80
+#define TH1520_RESET_ID_SPINLOCK		81
+#define TH1520_RESET_ID_CFG2TEE			82
+#define TH1520_RESET_ID_DSMART			83
+#define TH1520_RESET_ID_GPIO3_DB		84
+#define TH1520_RESET_ID_GPIO3_APB		85
+#define TH1520_RESET_ID_PERI_I2S		86
+#define TH1520_RESET_ID_PERI_APB3		87
+#define TH1520_RESET_ID_PERI2PERI1_APB		88
+#define TH1520_RESET_ID_VPSYS_APB		89
+#define TH1520_RESET_ID_PERISYS_APB4		90
+#define TH1520_RESET_ID_GMAC1_APB		91
+#define TH1520_RESET_ID_GMAC1_AHB		92
+#define TH1520_RESET_ID_GMAC1_CLKGEN		93
+#define TH1520_RESET_ID_GMAC1_AXI		94
+#define TH1520_RESET_ID_GMAC_AXI		95
+#define TH1520_RESET_ID_GMAC_AXI_APB		96
+#define TH1520_RESET_ID_PADCTRL1_APB		97
+#define TH1520_RESET_ID_VOSYS_AXI		98
+#define TH1520_RESET_ID_VOSYS_AXI_APB		99
+#define TH1520_RESET_ID_VOSYS_AXI_X2X		100
+#define TH1520_RESET_ID_MISC2VP_X2X		101
+#define TH1520_RESET_ID_DSPSYS			102
+#define TH1520_RESET_ID_VISYS			103
+#define TH1520_RESET_ID_VOSYS			104
+#define TH1520_RESET_ID_VPSYS			105
+
+/* DSP Subsystem */
+#define TH1520_RESET_ID_X2X_DSP1	0
+#define TH1520_RESET_ID_X2X_DSP0	1
+#define TH1520_RESET_ID_X2X_SLAVE_DSP1	2
+#define TH1520_RESET_ID_X2X_SLAVE_DSP0	3
+#define TH1520_RESET_ID_DSP0_CORE	4
+#define TH1520_RESET_ID_DSP0_DEBUG	5
+#define TH1520_RESET_ID_DSP0_APB	6
+#define TH1520_RESET_ID_DSP1_CORE	7
+#define TH1520_RESET_ID_DSP1_DEBUG	8
+#define TH1520_RESET_ID_DSP1_APB	9
+#define TH1520_RESET_ID_DSPSYS_APB	10
+#define TH1520_RESET_ID_AXI4_DSPSYS_SLV	11
+#define TH1520_RESET_ID_AXI4_DSPSYS	12
+#define TH1520_RESET_ID_AXI4_DSP_RS	13
+
+/* MISC Subsystem */
+#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN	0
+#define TH1520_RESET_ID_EMMC			1
+#define TH1520_RESET_ID_MISCSYS_AXI		2
+#define TH1520_RESET_ID_MISCSYS_AXI_APB		3
+#define TH1520_RESET_ID_SDIO0			4
+#define TH1520_RESET_ID_SDIO1			5
+#define TH1520_RESET_ID_USB3_APB		6
+#define TH1520_RESET_ID_USB3_PHY		7
+#define TH1520_RESET_ID_USB3_VCC		8
+
+/* VI Subsystem */
+#define TH1520_RESET_ID_ISP0		0
+#define TH1520_RESET_ID_ISP1		1
+#define TH1520_RESET_ID_CSI0_APB	2
+#define TH1520_RESET_ID_CSI1_APB	3
+#define TH1520_RESET_ID_CSI2_APB	4
+#define TH1520_RESET_ID_MIPI_FIFO	5
+#define TH1520_RESET_ID_ISP_VENC_APB	6
+#define TH1520_RESET_ID_VIPRE_APB	7
+#define TH1520_RESET_ID_VIPRE_AXI	8
+#define TH1520_RESET_ID_DW200_APB	9
+#define TH1520_RESET_ID_VISYS3_AXI	10
+#define TH1520_RESET_ID_VISYS2_AXI	11
+#define TH1520_RESET_ID_VISYS1_AXI	12
+#define TH1520_RESET_ID_VISYS_AXI	13
+#define TH1520_RESET_ID_VISYS_APB	14
+#define TH1520_RESET_ID_ISP_VENC_AXI	15
+
+/* VO Subsystem */
 #define TH1520_RESET_ID_GPU		0
 #define TH1520_RESET_ID_GPU_CLKGEN	1
-#define TH1520_RESET_ID_NPU		2
-#define TH1520_RESET_ID_WDT0		3
-#define TH1520_RESET_ID_WDT1		4
 #define TH1520_RESET_ID_DPU_AHB		5
 #define TH1520_RESET_ID_DPU_AXI		6
 #define TH1520_RESET_ID_DPU_CORE	7
@@ -19,5 +210,27 @@
 #define TH1520_RESET_ID_DSI1_APB	9
 #define TH1520_RESET_ID_HDMI		10
 #define TH1520_RESET_ID_HDMI_APB	11
+#define TH1520_RESET_ID_VOAXI		12
+#define TH1520_RESET_ID_VOAXI_APB	13
+#define TH1520_RESET_ID_X2H_DPU_AXI	14
+#define TH1520_RESET_ID_X2H_DPU_AHB	15
+#define TH1520_RESET_ID_X2H_DPU1_AXI	16
+#define TH1520_RESET_ID_X2H_DPU1_AHB	17
+
+/* VP Subsystem */
+#define TH1520_RESET_ID_VPSYS_AXI_APB	0
+#define TH1520_RESET_ID_VPSYS_AXI	1
+#define TH1520_RESET_ID_FCE_APB		2
+#define TH1520_RESET_ID_FCE_CORE	3
+#define TH1520_RESET_ID_FCE_X2X_MASTER	4
+#define TH1520_RESET_ID_FCE_X2X_SLAVE	5
+#define TH1520_RESET_ID_G2D_APB		6
+#define TH1520_RESET_ID_G2D_ACLK	7
+#define TH1520_RESET_ID_G2D_CORE	8
+#define TH1520_RESET_ID_VDEC_APB	9
+#define TH1520_RESET_ID_VDEC_ACLK	10
+#define TH1520_RESET_ID_VDEC_CORE	11
+#define TH1520_RESET_ID_VENC_APB	12
+#define TH1520_RESET_ID_VENC_CORE	13
 
 #endif /* _DT_BINDINGS_TH1520_RESET_H */
diff --git a/include/dt-bindings/reset/toshiba,tmpv770x.h b/include/dt-bindings/reset/toshiba,tmpv770x.h
index c1007acb194..9452bef3142 100644
--- a/include/dt-bindings/reset/toshiba,tmpv770x.h
+++ b/include/dt-bindings/reset/toshiba,tmpv770x.h
@@ -36,6 +36,13 @@
 #define TMPV770X_RESET_PIPCMIF		29
 #define TMPV770X_RESET_PICKMON		30
 #define TMPV770X_RESET_SBUSCLK		31
-#define TMPV770X_NR_RESET		32
+#define TMPV770X_RESET_VIIFBS0		32
+#define TMPV770X_RESET_VIIFBS0_APB	33
+#define TMPV770X_RESET_VIIFBS0_L2ISP	34
+#define TMPV770X_RESET_VIIFBS0_L1ISP	35
+#define TMPV770X_RESET_VIIFBS1		36
+#define TMPV770X_RESET_VIIFBS1_APB	37
+#define TMPV770X_RESET_VIIFBS1_L2ISP	38
+#define TMPV770X_RESET_VIIFBS1_L1ISP	39
 
 #endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */
diff --git a/include/dt-bindings/watchdog/aspeed-wdt.h b/include/dt-bindings/watchdog/aspeed-wdt.h
index 7ae6d84b2bd..89fa31ffce2 100644
--- a/include/dt-bindings/watchdog/aspeed-wdt.h
+++ b/include/dt-bindings/watchdog/aspeed-wdt.h
@@ -89,4 +89,142 @@
 
 #define AST2600_WDT_RESET2_DEFAULT 0x03fffff1
 
+#define AST2700_WDT_RESET1_CPU		(1 << 0)
+#define AST2700_WDT_RESET1_DRAM		(1 << 1)
+#define AST2700_WDT_RESET1_SLI0		(1 << 2)
+#define AST2700_WDT_RESET1_EHCI		(1 << 3)
+#define AST2700_WDT_RESET1_HACE		(1 << 4)
+#define AST2700_WDT_RESET1_SOC_MISC0	(1 << 5)
+#define AST2700_WDT_RESET1_VIDEO	(1 << 6)
+#define AST2700_WDT_RESET1_2D_GRAPHIC	(1 << 7)
+#define AST2700_WDT_RESET1_RAVS0	(1 << 8)
+#define AST2700_WDT_RESET1_RAVS1	(1 << 9)
+#define AST2700_WDT_RESET1_GPIO0	(1 << 10)
+#define AST2700_WDT_RESET1_SSP		(1 << 11)
+#define AST2700_WDT_RESET1_TSP		(1 << 12)
+#define AST2700_WDT_RESET1_CRT		(1 << 13)
+#define AST2700_WDT_RESET1_USB20_HOST	(1 << 14)
+#define AST2700_WDT_RESET1_USB11_HOST	(1 << 15)
+#define AST2700_WDT_RESET1_UFS		(1 << 16)
+#define AST2700_WDT_RESET1_EMMC		(1 << 17)
+#define AST2700_WDT_RESET1_AHB_TO_PCIE1	(1 << 18)
+#define AST2700_WDT_RESET1_XDMA0	(1 << 22)
+#define AST2700_WDT_RESET1_MCTP1	(1 << 23)
+#define AST2700_WDT_RESET1_MCTP0	(1 << 24)
+#define AST2700_WDT_RESET1_JTAG0	(1 << 25)
+#define AST2700_WDT_RESET1_ECC		(1 << 26)
+#define AST2700_WDT_RESET1_XDMA1	(1 << 27)
+#define AST2700_WDT_RESET1_DP		(1 << 28)
+#define AST2700_WDT_RESET1_DP_MCU	(1 << 29)
+#define AST2700_WDT_RESET1_AHB_TO_PCIE0	(1 << 31)
+
+#define AST2700_WDT_RESET1_DEFAULT 0x8207ff71
+
+#define AST2700_WDT_RESET2_USB3_A_HOST	(1 << 0)
+#define AST2700_WDT_RESET2_USB3_A_VHUB3	(1 << 1)
+#define AST2700_WDT_RESET2_USB3_A_VHUB2	(1 << 2)
+#define AST2700_WDT_RESET2_USB3_B_HOST	(1 << 3)
+#define AST2700_WDT_RESET2_USB3_B_VHUB3	(1 << 4)
+#define AST2700_WDT_RESET2_USB3_B_VHUB2	(1 << 5)
+#define AST2700_WDT_RESET2_SM3		(1 << 6)
+#define AST2700_WDT_RESET2_SM4		(1 << 7)
+#define AST2700_WDT_RESET2_SHA3		(1 << 8)
+#define AST2700_WDT_RESET2_RSA		(1 << 9)
+
+#define AST2700_WDT_RESET2_DEFAULT 0x000003f6
+
+#define AST2700_WDT_RESET3_LPC0		(1 << 0)
+#define AST2700_WDT_RESET3_LPC1		(1 << 1)
+#define AST2700_WDT_RESET3_MDIO		(1 << 2)
+#define AST2700_WDT_RESET3_PECI		(1 << 3)
+#define AST2700_WDT_RESET3_PWM		(1 << 4)
+#define AST2700_WDT_RESET3_MAC0		(1 << 5)
+#define AST2700_WDT_RESET3_MAC1		(1 << 6)
+#define AST2700_WDT_RESET3_MAC2		(1 << 7)
+#define AST2700_WDT_RESET3_ADC		(1 << 8)
+#define AST2700_WDT_RESET3_SDC		(1 << 9)
+#define AST2700_WDT_RESET3_ESPI0	(1 << 10)
+#define AST2700_WDT_RESET3_ESPI1	(1 << 11)
+#define AST2700_WDT_RESET3_JTAG1	(1 << 12)
+#define AST2700_WDT_RESET3_SPI0		(1 << 13)
+#define AST2700_WDT_RESET3_SPI1		(1 << 14)
+#define AST2700_WDT_RESET3_SPI2		(1 << 15)
+#define AST2700_WDT_RESET3_I3C0		(1 << 16)
+#define AST2700_WDT_RESET3_I3C1		(1 << 17)
+#define AST2700_WDT_RESET3_I3C2		(1 << 18)
+#define AST2700_WDT_RESET3_I3C3		(1 << 19)
+#define AST2700_WDT_RESET3_I3C4		(1 << 20)
+#define AST2700_WDT_RESET3_I3C5		(1 << 21)
+#define AST2700_WDT_RESET3_I3C6		(1 << 22)
+#define AST2700_WDT_RESET3_I3C7		(1 << 23)
+#define AST2700_WDT_RESET3_I3C8		(1 << 24)
+#define AST2700_WDT_RESET3_I3C9		(1 << 25)
+#define AST2700_WDT_RESET3_I3C10	(1 << 26)
+#define AST2700_WDT_RESET3_I3C11	(1 << 27)
+#define AST2700_WDT_RESET3_I3C12	(1 << 28)
+#define AST2700_WDT_RESET3_I3C13	(1 << 29)
+#define AST2700_WDT_RESET3_I3C14	(1 << 30)
+#define AST2700_WDT_RESET3_I3C15	(1 << 31)
+
+#define AST2700_WDT_RESET3_DEFAULT 0x000093ec
+
+#define AST2700_WDT_RESET4_FMC		(1 << 0)
+#define AST2700_WDT_RESET4_SOC_MISC1	(1 << 1)
+#define AST2700_WDT_RESET4_AHB		(1 << 2)
+#define AST2700_WDT_RESET4_SLI1		(1 << 3)
+#define AST2700_WDT_RESET4_UART0	(1 << 4)
+#define AST2700_WDT_RESET4_UART1	(1 << 5)
+#define AST2700_WDT_RESET4_UART2	(1 << 6)
+#define AST2700_WDT_RESET4_UART3	(1 << 7)
+#define AST2700_WDT_RESET4_I2C_MONITOR	(1 << 8)
+#define AST2700_WDT_RESET4_HOST_TO_SPI1	(1 << 9)
+#define AST2700_WDT_RESET4_HOST_TO_SPI2	(1 << 10)
+#define AST2700_WDT_RESET4_GPIO1	(1 << 11)
+#define AST2700_WDT_RESET4_FSI		(1 << 12)
+#define AST2700_WDT_RESET4_CANBUS	(1 << 13)
+#define AST2700_WDT_RESET4_MCTP		(1 << 14)
+#define AST2700_WDT_RESET4_XDMA		(1 << 15)
+#define AST2700_WDT_RESET4_UART5	(1 << 16)
+#define AST2700_WDT_RESET4_UART6	(1 << 17)
+#define AST2700_WDT_RESET4_UART7	(1 << 18)
+#define AST2700_WDT_RESET4_UART8	(1 << 19)
+#define AST2700_WDT_RESET4_BOOT_MCU	(1 << 20)
+#define AST2700_WDT_RESET4_IO_MCU	(1 << 21)
+#define AST2700_WDT_RESET4_LTPI0	(1 << 22)
+#define AST2700_WDT_RESET4_VGA_LINK	(1 << 23)
+#define AST2700_WDT_RESET4_LTPI1	(1 << 24)
+#define AST2700_WDT_RESET4_LTPI_PHY	(1 << 25)
+#define AST2700_WDT_RESET4_ACE		(1 << 26)
+#define AST2700_WDT_RESET4_LTPI_GPIO0	(1 << 28)
+#define AST2700_WDT_RESET4_LTPI_GPIO1	(1 << 29)
+#define AST2700_WDT_RESET4_AHB_TO_PCIE1	(1 << 30)
+#define AST2700_WDT_RESET4_I3C_DMA	(1 << 31)
+
+#define AST2700_WDT_RESET4_DEFAULT 0x40303803
+
+#define AST2700_WDT_RESET5_I2C_GLOBAL	(1 << 0)
+#define AST2700_WDT_RESET5_I2C0		(1 << 1)
+#define AST2700_WDT_RESET5_I2C1		(1 << 2)
+#define AST2700_WDT_RESET5_I2C2		(1 << 3)
+#define AST2700_WDT_RESET5_I2C3		(1 << 4)
+#define AST2700_WDT_RESET5_I2C4		(1 << 5)
+#define AST2700_WDT_RESET5_I2C5		(1 << 6)
+#define AST2700_WDT_RESET5_I2C6		(1 << 7)
+#define AST2700_WDT_RESET5_I2C7		(1 << 8)
+#define AST2700_WDT_RESET5_I2C8		(1 << 9)
+#define AST2700_WDT_RESET5_I2C9		(1 << 10)
+#define AST2700_WDT_RESET5_I2C10	(1 << 11)
+#define AST2700_WDT_RESET5_I2C11	(1 << 12)
+#define AST2700_WDT_RESET5_I2C12	(1 << 13)
+#define AST2700_WDT_RESET5_I2C13	(1 << 14)
+#define AST2700_WDT_RESET5_I2C14	(1 << 15)
+#define AST2700_WDT_RESET5_I2C15	(1 << 16)
+#define AST2700_WDT_RESET5_UHCI		(1 << 17)
+#define AST2700_WDT_RESET5_USB2_C_UART	(1 << 18)
+#define AST2700_WDT_RESET5_USB2_C	(1 << 19)
+#define AST2700_WDT_RESET5_USB2_D_UART	(1 << 20)
+#define AST2700_WDT_RESET5_USB2_D	(1 << 21)
+
+#define AST2700_WDT_RESET5_DEFAULT 0x00320000
+
 #endif
-- 
cgit v1.3.1