From a6b479b7ad6d78811e6b5cc69a8704727a50fa62 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Tue, 27 May 2025 09:02:20 -0600
Subject: Squashed 'dts/upstream/' changes from 955176a4ff59..fe2d6c49bb4e

fe2d6c49bb4e Merge tag 'v6.15-dts-raw'
3109849be809 Merge tag 'soc-fixes-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
75e59270f7c5 Merge tag 'mvebu-fixes-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes
69a2cec41405 Merge tag 'sunxi-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
64a925d7605a dt-bindings: can: microchip,mcp2510: Fix $id path
50d5bacc52a4 Merge tag 'v6.15-rc7-dts-raw'
b8973c10564b Merge tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c88fc0f02e78 arm64: dts: marvell: uDPU: define pinctrl state for alarm LEDs
63756d9a84f8 Merge tag 'v6.15-rc6-dts-raw'
8de495f56dbd Merge tag 'input-for-v6.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
7346db7cb1f5 Merge tag 'imx-fixes-6.15-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
a12444223f6a arm64: dts: amazon: Fix simple-bus node name schema warnings
e605d5d7fe3d Merge tag 'asahi-soc-fixes-6.15' of https://github.com/AsahiLinux/linux into arm/fixes
fff11fe6a218 Merge tag 'riscv-sophgo-dt-fixes-for-v6.15-rc1' of https://github.com/sophgo/linux into arm/fixes
cbdc7e808a47 Merge tag 'amlogic-fixes-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes
6569e1afaabb Merge tag 'v6.15-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
bad970d505c7 arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeout
2498aef1d581 arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive mode
930a058ee559 Merge tag 'net-6.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
75e6b42a413a dt-bindings: net: ethernet-controller: Add informative text about RGMII delays
2fb1a42d2ab9 Merge tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
95bd2a8dfcd9 arm64: dts: amlogic: dreambox: fix missing clkc_audio node
84ef7812cc93 Merge tag 'v6.15-rc5-dts-raw'
724862669eee Merge tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
e56b01802fc8 riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
f6364dd1ac42 arm64: dts: rockchip: fix Sige5 RTC interrupt pin
b6c1f156299d arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp23 SoCs
40c14b9e5f5e arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCs
62bf1a9664d4 arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp21 SoCs
fccc8448c30a arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCs
ad0c99d174ea arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp25 SoCs
282b9c077aae arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCs
3755c90eab9c Merge tag 'imx-fixes-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
b4c1abf11ff1 Merge tag 'juno-fix-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixes
c7c3c68f3ce7 dt-bindings: mediatek,mt6779-keypad: Update Mattijs' email address
e4820115982e Merge tag 'v6.15-rc4-dts-raw'
5a4f16f09fb5 arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2
98e5be0c34f6 Revert "arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection"
d6354f04cfe0 arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588
22b5bf714835 arm64: dts: rockchip: Align wifi node name with bindings in CB2
f7cb03107c26 Merge tag 'char-misc-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
4acdc261f422 spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
2ebbc79f9b14 spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry
08939b65ca58 arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock
73915dad61e7 arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock
fb321fd7cecd ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock
1499bef2c3a6 ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock
a831b6c1c6b9 ARM: dts: opos6ul: add ksz8081 phy properties
3ae5c171fc05 arm64: dts: imx95: Correct the range of PCIe app-reg region
f118c5265c25 arm64: dts: imx8mp: configure GPU and NPU clocks in nominal DTSI
e281122066ea Merge tag 'v6.15-rc3-dts-raw'
1d7ab1ed4277 arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on
b0dbfc0c19d7 dt-bindings: soc: fsl: fsl,ls1028a-reset: Fix maintainer entry
775d526af58f dt-bindings: timer: renesas,tpu: remove obsolete binding
739bb43d33b7 dt-bindings: nvmem: Add compatible for MSM8960
52f7f735cf15 dt-bindings: nvmem: Add compatible for IPQ5018
aeb6cb0b5324 dt-bindings: nvmem: fixed-cell: increase bits start value to 31
3a7b208d9e79 dt-bindings: nvmem: Add compatible for MS8937
1c27fc6ffa8e dt-bindings: nvmem: qfprom: Add X1E80100 compatible
d35d917d5816 dt-bindings: nvmem: rockchip,otp: Add compatible for RK3576
759e7828fe78 dt-bindings: nvmem: rockchip,otp: add missing limits for clock-names
e73a3d952883 arm64: dts: morello: Fix-up cache nodes
8386b46f9eda arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4
6b71f5ae1a2a arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg
2ed5901a514b dt-bindings: timer: nxp,sysctr-timer: Add i.MX94 support
e58a2db4c38c dt-bindings: interrupt-controller: fsl,irqsteer: Add i.MX94 support
622ce6b1ba08 dt-bindings: display: nwl-dsi: Allow 'data-lanes' property for port@1
e0ef023c67c0 dt-bindings: xilinx: Remove myself from maintainership
0449e8973a84 Merge tag 'v6.15-rc1-dts-raw'
b2db21710501 arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433
28265b46ce50 arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi
314cea8948b0 arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down
4314a01898d6 Merge tag 'input-for-v6.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
fcf2048dc9de Merge branch 'next' into for-linus
ba6c6579c9bd Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
58f1d4c158c0 Merge tag 'rtc-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
29912193033d Merge tag 'usb-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
937ed4db2ab8 Merge tag 'tty-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
ac589474b57a Merge tag 'thermal-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
6879712ce88d Merge tag 'i3c/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
af2574352383 Merge tag 'linux-watchdog-6.15-rc1' of git://www.linux-watchdog.org/linux-watchdog
e81f3d825b82 Merge tag 'i2c-for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
bd876bc870df Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
42065dec6c72 Merge tag 'phy-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
301007542d03 Merge tag 'char-misc-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
33b10181f970 Merge tag 'mm-nonmm-stable-2025-03-30-18-23' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
d4643a038924 Merge patch series "Add some validation for vector, vector crypto and fp stuff"
cac1aa08f484 dt-bindings: rtc: max31335: Add max31331 support
26e04cf9cc79 Merge tag 'mailbox-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
576a6900f13c Merge tag 'for-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
78a2eae6cb86 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
4194f888d6d6 Merge tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
c96994fe39c1 Merge tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
a42296696853 Merge tag 'backlight-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
6d0f08e93b76 Merge tag 'leds-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
3bb45cc2ceab Merge tag 'mfd-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
72713c04060a Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
17102f25116b Merge tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
e44d9139748a Merge tag 'v6.15-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
b727a6e37d16 Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
b1ec05cb6a63 Merge tag 'drm-next-2025-03-28' of https://gitlab.freedesktop.org/drm/kernel
34c876511338 Merge tag 'for-6.15/io_uring-reg-vec-20250327' of git://git.kernel.dk/linux
ddb37d4776e9 Merge tag 'for-6.15/io_uring-rx-zc-20250325' of git://git.kernel.dk/linux
c0a3226a4218 dt-bindings: i2c: snps,designware-i2c: describe Renesas RZ/N1D variant
f8da42670dd8 Merge tag 'powerpc-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
38106689da03 dt-bindings: edac: altera: socfpga: Convert to YAML
7fa97aa2cc14 dt-bindings: pps: gpio: Correct indentation and style in DTS example
bc13b6ac45ca Merge branch 'pci/controller/xilinx-cpm'
51fe3683d562 Merge branch 'pci/controller/qcom'
14635816113e Merge branch 'pci/controller/mediatek'
c27d458c9018 Merge branch 'pci/controller/brcmstb'
910bd393ba5a Merge branch 'pci/controller/amd-mdb'
99abd782f5d4 Merge branch 'pci/controller/altera'
2b19e48fbedc Merge branch 'pci/dt-bindings'
ce77e68fec79 Merge tag 'soc-arm-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c849f132da6e Merge tag 'soc-drivers-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
253861a5926a Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
b171384a2380 Merge tag 'net-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
725971c9baeb Merge tag 'iommu-updates-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
f39cd579edb7 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
7f1c5dc0d96a Merge tag 'ata-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
1262e5915578 dt-bindings: mailbox: qcom: add compatible for MSM8226 SoC
e81c74aaf2e0 dt-bindings: mailbox: fsl,mu: Add i.MX94 compatible
f4f5865e81fd dt-bindings: mailbox: mediatek: Add support for MT8196 GCE mailbox
e054cac9ae6e Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
b03526c21450 Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next
a50392a2baf3 Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-next
e595cb4e5772 Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next
dbd546c62c5c Merge tag 'mtd/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
2eecb8cbb591 Merge tag 'platform-drivers-x86-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
9d2cd6a3b1d5 Merge tag 'nand/for-6.15' into mtd/next
bd76b77d4e2c Merge tag 'sound-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
2f3a8d13a1be Merge tag 'media/v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
01edfbe94231 Merge tag 'pmdomain-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
33e6daed2dcb Merge tag 'mmc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
f661bbffece6 Merge tag 'gpio-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
d98043246fc3 Merge tag 'hwmon-for-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
f88a116702ac Merge tag 'pwm/for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
c1e80718e7c0 Merge tag 'spi-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
903bc8c7edc1 Merge tag 'regulator-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
34d2a8ce3d44 Merge tag 'pm-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
be3477545a1b Merge tag 'for-net-next-2025-03-25' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
f46587488060 dt-bindings: thermal: Correct indentation and style in DTS example
ed91ea537f6b dt-bindings: thermal: Update for BCM74110
b56a3bd46a79 dt-bindings: thermal: tsens: Add ipq5332, ipq5424 compatible
408f714c8807 Merge tag 'irq-drivers-2025-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
2c7bdd5acc6a dt-bindings: net: bluetooth: nxp: Add support to set BD address
c878bbbc7198 dt-bindings: net: bluetooth: qualcomm: document WCN3950
3ddbb8fb8fe6 dt-bindings: net: bluetooth: nxp: Add wakeup pin properties
a4c451f881ed dt-bindings: net: qcom,ipa: Correct indentation and style in DTS example
86a6733d63fe Merge tag 'wireless-next-2025-03-20' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
8604a4e6caa1 dt-bindings: net: rockchip-dwmac: Add compatible string for RK3528
cacfdfd63704 dt-bindings: riscv: document vector crypto requirements
c9835a4f0732 dt-bindings: riscv: add vector sub-extension dependencies
b21477b0a350 dt-bindings: riscv: d requires f
a77e47812f3f dt-bindings: watchdog: sunxi: add Allwinner A523 compatible string
bf3232c697af Merge tag 'i2c-host-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
8f6d11a83a0a Merge tag 'docs-6.15' of git://git.lwn.net/linux
35477e322ba4 dt-bindings: PCI: Add common schema for devices accessible through PCI BARs
a345b6688502 Merge tag 'asoc-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
2baf484b277c Merge branch 'pm-cpufreq'
67a34184ddf2 dt-bindings: timer: Add SiFive CLINT2
2ddeb4d36e67 Merge tag 'cpufreq-arm-updates-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
f8ec1f1d1cc5 dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files
98322a22c22a dt-bindings: hwmon: Add Microchip emc2305 support
e80e09439582 media: dt-bindings: mediatek,vcodec-encoder: Drop assigned-clock properties
d8cea587c006 docs: dt-bindings: Specify ordering for properties within groups
83d44c13a32f dt-bindings: hwmon: Drop stray blank line in the header
28e3e5da1d38 dt-bindings: mfd: syscon: Add microchip,sama7d65-sfrbu
cdb8f10e1aaa dt-bindings: mfd: syscon: Add microchip,sama7d65-ddr3phy
723b3cd19dd1 dt-bindings: i2c: spacemit: add support for K1 SoC
c8e7edc109e3 dt-bindings: i2c: omap: Add mux-states property
6cd4c93c1892 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
0e19f27df8f7 Merge tag 'amlogic-arm-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
c65eff2dbcf7 Merge tag 'amlogic-arm64-dt-for-v6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
bebc6d8370bf ASoC: wm8904: Add DMIC and DRC support
23803d09fa1b dt-bindings: serial: snps-dw-apb-uart: document RZ/N1 binding without DMA
eb71e94b0058 dt-bindings: serial: snps-dw-apb-uart: Add support for rk3562
819c0d972e58 dt-bindings: serial: fsl-lpuart: support i.MX94
da1dc4f87d0d dt-bindings: serial: samsung: add exynos7870-uart compatible
0791859ab251 Merge tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
1c289ddb61bc ASoC: dt-bindings: wm8904: Add DMIC, GPIO, MIC and EQ support
64345bc61380 spi: dt-bindings: cdns,qspi-nor: Require some peripheral properties
00c70a06c714 spi: dt-bindings: cdns,qspi-nor: Deprecate the Cadence compatible alone
c7b9fed01f76 spi: dt-bindings: cdns,qspi-nor: Be more descriptive regarding what this controller is
2951fd5da291 arm64: dts: Add gpio_intc node for Amlogic A5 SoCs
b7ea7dda1e2e arm64: dts: Add gpio_intc node for Amlogic A4 SoCs
06138f903a3c Merge branches 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'rockchip', 's390', 'core', 'intel/vt-d' and 'amd/amd-vi' into next
8495ad389173 Merge tag 'dt-cleanup-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
a301f99cf614 Merge tag 'tegra-for-6.15-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
cd03551a294d dt-bindings: gpu: arm,mali-midgard: add exynos7870-mali compatible
5b84d726ddaf Merge tag 'qcom-drivers-for-6.15-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
f10573df66cb Merge tag 'qcom-drivers-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
fa143ab38af1 Merge tag 'amlogic-drivers-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers
bab3f090d9d3 Merge tag 'reset-for-v6.15' of git://git.pengutronix.de/pza/linux into soc/drivers
e13001093d96 Merge tag 'samsung-drivers-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
56c3ca45c2c7 Merge tag 'at91-soc-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm
3b1e6f959fee Merge tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi into soc/dt
75357dfed634 Merge tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
9737b7a849d5 Merge tag 'omap-for-v6.15/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
6432c5392792 Merge tag 'riscv-sophgo-dt-for-v6.15' of https://github.com/sophgo/linux into soc/dt
481e67465dc8 Merge tag 'mvebu-dt64-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
96e8744cc103 Merge tag 'v6.15-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
81ed54132fc0 Merge tag 'zynq-dt-for-6.15' of https://github.com/Xilinx/linux-xlnx into soc/dt
0a2824017157 Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt
4e48222bf65f Merge tag 'sunxi-dt-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
b831e4e9bb20 Merge tag 'at91-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
6faf8a6c4970 Merge tag 'stm32-dt-for-v6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
29c62c6339a6 dt-bindings: deprecate "snps,en-tx-lpi-clockgating" property
ac676ad15ceb ARM: dts: stm32: remove "snps,en-tx-lpi-clockgating" property
a3aeb65b5e21 riscv: dts: starfive: remove "snps,en-tx-lpi-clockgating" property
86032de3cc2d Merge tag 'ieee802154-for-net-next-2025-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next
e3ae9db04517 dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
0cb4c6d785dc dt-bindings: i2c: i2c-rk3x: Add rk3562 support
3b5a8c070c44 dt-bindings: i2c: imx-lpi2c: add i.MX94 LPI2C
ce1e60e777db dt-bindings: i2c: qup: Document interconnects
ac988bf5af32 dt-bindings: i2c: qcom,i2c-qup: Document power-domains
9bcf0325b6ae dt-bindings: i2c: exynos5: add exynos7870-hsi2c compatible
497c36ba820d dt-bindings: i2c: samsung,s3c2410: add exynos7870-i2c compatible
2ba4ea354217 dt-bindings: mtd: atmel,dataflash: convert txt to yaml
3813b6843768 dt-bindings: mtd: gpmi-nand: Add compatible string for i.MX8 chips
4ba959479642 ASoC: codecs: Add aw88166 amplifier driver
559db5bb3df6 add sof support on imx95
f42c1e48e1ea dt-bindings: hwmon: Add description for sensor HTU31
3e54d6806c68 spi: Merge up fixes
c4c47e5bb42f regulator: dt-bindings: rtq2208: Cleanup whitespace
1aae375c7c42 regulator: dt-bindings: rtq2208: Mark fixed LDO VOUT property as deprecated
6cf18ee31953 Merge patch series "riscv: Add bfloat16 instruction support"
f306f44643f3 dt-bindings: riscv: add bfloat16 ISA extension description
d1349a8d0aa7 arm64: dts: hi3660: Add property for fixing CPUIdle
8283ad10d5c2 Merge tag 'samsung-pinctrl-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
bba239dcd4d7 Merge net-next/main to resolve conflicts
ee0acddba296 dt-bindings: rtc: pcf2127: Reference spi-peripheral-props.yaml
eb3c4568ad0b dt-bindings: hwmon: ti,ina2xx: Add INA233 device
26e91a5c1c4d ASoC: dt-bindings: audio-graph-card2: add widgets and hp-det-gpios support
20f74f1fc993 ASoC: dt-bindings: support imx95's CM7 core
79ab7f994af8 Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into clk-for-6.15
1a7ee5fd2be3 dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
7665c77f7cdb dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
832929f7a52a dt-bindings: hwmon: ltc2978: add support for LT717x
7758dfded334 dt-bindings: pinctrl: qcom: Add egpio function for sa8775p
f2341866dbb8 dt-bindings: pinctrl: airoha: Add missing gpio-ranges property
9abb426254c5 dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl
d3812cbd3cf5 dt-bindings: rtc: qcom-pm8xxx: document qcom,no-alarm flag
d2d31cf30f25 dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
91922237393f Merge tag 'v6.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
49186c87530a dt-bindings: thermal: give OS some leeway in absence of critical-action
b7e2002c7f37 dt-bindings: cpufreq: cpufreq-qcom-hw: Narrow properties on SDX75, SA8775p and SM8650
d3db8a0a1e18 dt-bindings: cpufreq: cpufreq-qcom-hw: Drop redundant minItems:1
9b493bef6c64 dt-bindings: cpufreq: cpufreq-qcom-hw: Add missing constraint for interrupt-names
a0842ec452cb dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS8300 compatible
08344f6cf323 dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
b58d82c6f35a ASoC: dt-bindings: fsl,sai: Add i.MX94 support
52fcce301d62 regulator: dt-bindings: pca9450: Add nxp,pf9453 compatible string
5a327e9ff15c ASoC: dt-bindings: mediatek,mt8188-mt6359: Add mediatek,accdet
9d8dfb82b770 ASoC: dt-bindings: Add schema for "awinic,aw88166"
b21759520198 dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible
3f127f8b13cf dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema
7fdfaa5e1649 arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
e532d69208c3 arm64: dts: marvell: Use preferred node names for "simple-bus"
36438541d5f0 arm64: dts: marvell: Drop unused CP11X_TYPE define
a6ee6a6bd390 arm64: dts: marvell: Move arch timer and pmu nodes to top-level
dc3b5c12e6a4 dt-bindings: rng: rockchip,rk3588-rng: Drop unnecessary status from example
2df156046328 Merge tag 'ti-k3-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
f57059f434cd Merge tag 'imx-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
4378c7352b85 Merge tag 'imx-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
81231b09fca0 Merge tag 'imx-bindings-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
f185c678c9a4 Merge tag 'spacemit-dt-for-6.15-1' of https://github.com/spacemit-com/linux into soc/dt
c18007158dda Merge tag 'davinci-updates-for-v6.15-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into soc/dt
d24528c09c20 arm64: dts: rockchip: Fix PWM pinctrl names
2e5608c86650 arm64: dts: rockchip: fix RK3576 SCMI clock IDs
52dc545f0788 dt-bindings: clock: rk3576: add SCMI clocks
24b2d3f6703c arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
8f7a008a36a0 Merge tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
02def44715b4 Merge tag 'asahi-soc-dt-6.15-v3' of https://github.com/AsahiLinux/linux into soc/dt
50a5056a0fbc Merge tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
abd4cba3fc31 Merge tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
a8cb4de20f8e Merge tag 'tegra-for-6.15-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
920fc9d1facb arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties
7303c3977e4a arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names
bdc46b592528 arm64: dts: amd/seattle: Move and simplify fixed clocks
5767b5ef37dc arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version
f66a26fc5063 Merge tag 'renesas-dts-for-v6.15-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
f94bc208615f dt-bindings: mfd: syscon: Add the pbus-csr node for Airoha EN7581 SoC
a6586b520e84 bindings: pinctrl: ingenic: add x1600
c5f11db1dc9c dt-bindings: mfd: syscon: Add rk3528 QoS register compatible
99b871852f02 dt-bindings: mfd: atmel,sama5d2-flexcom: Add microchip,sama7d65-flexcom
cee62549c1cf dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8937
4b2dbbdb1106 dt-bindings: mfd: samsung,s2mps11: Add compatible for s2mpu05-pmic
e53b55f7425b dt-bindings: regulator: Add TI TPS65214 PMIC bindings
b70d9d3353c8 dt-bindings: regulator: Add TI TPS65215 PMIC bindings
f8f2120feff1 dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
fabf15359158 dt-bindings: mfd: stm32-timers: Add support for stm32mp25
27070527c9da Merge branches 'ib-mfd-input-leds-power-6.15', 'ib-mfd-power-6.15' and 'ib-mfd-regulator-6.15' into ibs-for-mfd-merged
3cfc089d7aee dt-bindings: can: fsl,flexcan: add i.MX94 support
e0c8c7d1cba3 dt-bindings: can: fsl,flexcan: add transceiver capabilities
867ef82b4496 dt-bindings: usb: qcom,dwc3: Synchronize minItems for interrupts and -names
4cfef97e6f55 Merge tag 'iio-for-6.15a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
2bbf5d333bbb Merge tag 'mediatek-drm-next-6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
1e57f81382d5 arm64: dts: freescale: Add support for the GOcontroll Moduline Display
5eb64fd18835 ASoC: sun4i-codec: add headphone dectection for
7818917a7583 dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
6144fc934c1d dt-bindings: reset: fix double id on rk3562-cru reset ids
cb698afb24b8 dt-bindings: spi: add compatibles for mt7988
c6d6437dbad2 dt-bindings: remoteproc: Add SM8750 MPSS
16f807a2f799 dt-bindings: power: qcom,kpss-acc-v2: add qcom,msm8916-acc compatible
9f908c3d4e3d ASoC: dt-bindings: sun4i-a10-codec: add hp-det-gpios
1cf4588d69c5 dt-bindings: connector: Add the GOcontroll Moduline module slot bindings
dcf3f572da06 dt-bindings: vendor-prefixes: add GOcontroll
fac0b8b2d03e ASoC: dt-bindings: tas2770: add compatible for TAS5770L
8af38e87bf30 ASoC: dt-bindings: tas27xx: add compatible for SN012776
7aa416c35ed5 arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7
bd4c8a1c08f9 arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
db7a99c423de arm64: dts: rockchip: Add SDHCI controller for RK3528
29d894b16a31 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
5857b1d7ade2 arm64: dts: rockchip: Remove bluetooth node from rock-3a
8464126790be arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory
208e3a0a442e dt-bindings: clock: qcom: Add compatible for QCM6490 boards
b92c36eff4bf dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
0e87b6717e3c dt-bindings: dsp: fsl,dsp: Add resets property
6cc91fdea94d dt-bindings: reset: audiomix: Add reset ids for EARC and DSP
28a2aabbb6c4 dt-bindings: pinctrl: add compatible for Allwinner A523/T527
6b4d5de72979 dt-bindings: power: Add TH1520 SoC power domains
a441545e25fc dt-bindings: firmware: thead,th1520: Add support for firmware node
ecbefc112b34 regulator: dt-bindings: add documentation for s2mpu05-pmic regulators
678f2f84e7f4 dt-bindings: net: Define interrupt constraints for DWMAC vendor bindings
228d9ce5d3bb dt-bindings: net: rockchip-dwmac: Require rockchip,grf and rockchip,php-grf
20bbb3d2c8e7 dt-bindings: firmware: imx: add property reset-controller
5ba7b84e7bf0 dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
568847bfd352 dt-bindings: display: mediatek: dpi: add power-domains example
32e09f864be1 arm64: dts: st: add stm32mp215f-dk board support
559d24b54b4e dt-bindings: stm32: document stm32mp215f-dk board
da2175c8eedc arm64: dts: st: introduce stm32mp21 SoCs family
050105727605 arm64: dts: st: add stm32mp235f-dk board support
8a79caa82a70 dt-bindings: stm32: document stm32mp235f-dk board
6abc5bf17ba1 arm64: dts: st: introduce stm32mp23 SoCs family
e95c2526d6e9 dt-bindings: stm32: add STM32MP21 and STM32MP23 compatibles for syscon
c8aa9617a955 arm64: dts: st: add stm32mp257f-dk board support
5a615c7759c9 dt-bindings: stm32: document stm32mp257f-dk board
fa94a630d90d dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support
c0aabcef7b8d dt-bindings: mmc: sunxi: add compatible strings for Allwinner A523
2486f6c1b421 dt-bindings: mmc: sunxi: Simplify compatible string listing
8ca3040b05de dt-bindings: mmc: sdhci-of-dwcmhsc: Add compatible string for RK3528
5b36bb4f4707 dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for RK3528
8462dd3e6881 dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support
d274a3df0a12 dt-bindings: mmc: rockchip-dw-mshc: Add support for rk3562
56b744861176 dt-bindings: mmc: Add support for rk3562 eMMC
eb9b6eec2dda arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7
906b8cbb8d43 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Plus
19e0533172f2 arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Plus
0bbaa0ff4c09 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Max
173563eb6666 arm64: dts: rockchip: Enable HDMI0 audio output for Orange Pi 5/5B
9895a2f169dd dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
b8f6cd67f8b3 dt-bindings: trivial-devices: Add Maxim max15301, max15303, and max20751
fc5147dfc750 dt-bindings: fsi: ibm,p9-scom: Add "ibm,fsi2pib" compatible
5f06f892eb53 Backmerge tag 'v6.14-rc6' into drm-next
fb0e8021a68f dt-bindings: iio: adc: Add i.MX94 and i.MX95 support
e15adeb19f02 dt-bindings: iio: adc: add AD7191
33496024fc8e dt-bindings: mmc: atmel,hsmci: Convert to json schema
7ab9faf87206 dt-bindings: mmc: mmc-slot: Make compatible property optional
ff4a69b28cf8 dt-bindings: mmc: fsl-imx-esdhc: Add i.MX94 support
b6c174fc7de2 dt-bindings: mmc: Change to additionalProperties to fix fail detect Unevaluated property
502377fe32de dt-bindings: mmc: samsung,exynos-dw-mshc: add exynos7870 support
d6ee3c852b25 dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5NC Versal Net host
a19185cc15d1 Merge tag 'at24-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
0677248b0e32 dt-bindings: arm-smmu: Document QCS8300 GPU SMMU
efd6b0348bfa dt-bindings: spi: add SG2044 SPI NOR controller driver
d0f43207a01a dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2
8d4b83e94b40 dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY
eeae88998b40 dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
26a91c680522 ARM: dts: stm32: Add Plymovent AQM devicetree
4c21b9c842e3 ARM: dts: stm32: Add pinmux groups for Plymovent AQM board
904f0d522b88 dt-bindings: arm: stm32: Add Plymovent AQM board
a3a3221056c9 dt-bindings: sound: convert ICS-43432 binding to YAML
2f91de2a490b ARM: dts: apalis/colibri-imx6: Add support for v1.2
9eb0618252aa ARM: dts: apalis/colibri-imx6: Enable STMPE811 TS
f758e0d13235 dt-bindings: arm: fsl: Add VAR-SOM-MX6UL SoM and Concerto board
f76216ee5bc2 ARM: dts: imx6ul: Add Variscite Concerto board support
dd6e0d48db76 ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support
b3d9184831ad arm64: dts: imx8qm-apalis: Remove compatible from SoM dtsi
517caee96f7e ARM: dts: vf610-colibri: Remove compatible from SoM dtsi
5656930f43b4 ARM: dts: imx6qdl-apalis/colibri: Remove compatible from SoM dtsi
fad232a946b4 dt-bindings: arm: fsl: drop usage of Toradex SOMs compatible alone
ea11d8d98354 arm64: dts: imx8mp: change AUDIO_AXI_CLK_ROOT freq. to 800MHz
0b17f7c82b59 arm64: dts: imx8mp: add AUDIO_AXI_CLK_ROOT to AUDIOMIX block
2bc9da478485 arm64: dts: imx93: add ddr edac support
ab9bf8d19072 arm64: dts: imx95: add ref clock for pcie nodes
1ad5ffe68e35 arm64: dts: mba8xx: Remove invalid property disable-gpio
ef030623665a ARM: dts: imx6ul-tqma6ul1: Change include order to disable fec2 node
1c284ff7a69f arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe
4456f7d29f3a arm64: dts: im8mq-librem5: move dwc3 usb port under ports
9a66f214f03d arm64: dts: mba8mx: change sound card model name
4749d122ddde arm64: dts: imx8mp-tqma8mpql-mba8mpxl: change sound card model name
5269104e27e3 arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3
71b653961ab8 dt-bindings: arm: fsl: add i.MX95 15x15 EVK board
1ebef3515785 arm64: dts: imx95: Add imx95-15x15-evk support
9726256fedee arm64: dts: imx95: Add i3c1 and i3c2
94ef2b4371a4 arm64: dts: imx95: Add #io-channel-cells = <1> for adc node
d73e4f93cd40 ARM: dts: imx53-mba53: Fix the PCA9554 compatible
acd5a974e760 ARM: dts: imx31: Use nand-controller as node name
81ad2fe2f7b5 ARM: dts: vfxxx: Fix the order of the DMA entries
5447ae84fa8f ARM: dts: tqma7: Add partitions subnode to spi-nor
1ccfa18431b4 ARM: dts: imx7-tqma7: Add vcc-supply for spi-nor
1743d93ea655 ARM: dts: tqma6ul: Add partitions subnode to spi-nor
acde6cbf9cdf ARM: dts: imx6ul-tqma6ul: Add vcc-supply for spi-nor
c3ce52f0a98e ARM: dts: imx6ul-tqma6ul: Order DT properties
83b725debc91 ARM: dts: imx6qdl-tqma6: Add partitions subnode to spi-nor
4169f66d2bb7 ARM: dts: imx6qdl-tqma6: use sw4_reg as 3.3V supply
851b1c7d93cb ARM: dts: imx6qdl-tqma6: limit PMIC SW4 to 3.3V
2cb7d799b230 ARM: dts: imx6qdl-tqma6: Order DT properties
d4c064aa4ec4 arm64: dts: imx8mp-skov: support new 7" panel board
c8cb767887b4 arm64: dts: imx8mp-skov: add revC BD500 board
ea4b50b721d7 arm64: dts: imx8mp-skov: describe I2C bus recovery for all controllers
93fe81be94fe arm64: dts: imx8mp-skov: move I2C2 pin control group into DTSI
4e3e1bd5602f arm64: dts: imx8mp-skov: add basic board as fallback
26e62120b67b dt-bindings: arm: fsl: add more compatibles for Skov i.MX8MP variants
d9eebb23bec4 arm64: dts: freescale: imx8mp-skov: operate SoC in nominal mode
1dd517527ec2 arm64: dts: freescale: imx8mp-skov: configure LDB clock automatically
9fe870aa5fbb arm64: dts: imx8mp: add fsl,nominal-mode property into nominal.dtsi
36d591413641 arm64: dts: imx8mp: Add optional nominal drive mode DTSI
04b0ce30ed9a Merge patch series "scsi: ufs: renesas: Add support for R-Car S4-8 ES1.2"
c0c684cc130f scsi: ufs: dt-bindings: renesas,ufs: Add calibration data
fc09bffd40a1 arm64: dts: imx8mp: configure GPU and NPU clocks to overdrive rate
bd3329807adb arm64: dts: freescale: ten64: add usb hub definition
4057bd794cb2 Merge tag 'drm-msm-next-2025-03-09' of https://gitlab.freedesktop.org/drm/msm into drm-next
31ae3a9262da dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
1b13b0914156 dt-bindings: dma: Convert fsl,elo*-dma to YAML
c3ed4efc2e50 dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
aa353c2ac5c5 dt-bindings: input: goodix,gt9916: Document gt9897 compatible
6eb8cce7644b dt-bindings: pwm: imx: Add i.MX93, i.MX94 and i.MX95 support
cbd6df2de511 ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC rev.200 board
3167db834dfa ARM: dts: stm32: use IRQ_TYPE_EDGE_FALLING on stm32mp157c-dk2
b83d9874fa79 dt-bindings: gpio: vf610: Add i.MX94 support
58ce3a6f5491 Merge v6.14-rc6 into usb-next
ee4310889b80 dt-bindings: phy: document Allwinner A523 USB-2.0 PHY
e2e13ecd8aa4 dt-bindings: soc: samsung: exynos-usi: Drop unnecessary status from example
13c7fa153448 dt-bindings: watchdog: fsl-imx7ulp-wdt: Add i.MX94 support
6fc9ef1dce8b ASoC: dmic: add regulator support
f33253da3ed0 dt-bindings: pwm: rockchip: Add rockchip,rk3528-pwm
df96b42ccaa5 arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D
8af8429d4741 arm64: dts: rockchip: Add SFC nodes for rk3576
460ef5b623e5 arm64: dts: rockchip: Add maskrom button to Radxa E20C
8ba64ba5cb30 arm64: dts: rockchip: Add SARADC node for RK3528
6793b56b79df arm64: dts: rockchip: Add user button to Radxa E20C
a3556ede6b48 arm64: dts: rockchip: Add leds node to Radxa E20C
4dc91efae86b arm64: dts: rockchip: Add HDMI support for rock-4d
6e03c7e28e2d arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
2bdc1b582fc5 arm64: dts: rockchip: Enable HDMI receiver on rock-5b
be8c63cd54f8 arm64: dts: rockchip: Add device tree support for HDMI RX Controller
9ee90dfd6957 arm64: dts: rockchip: Add rk3528 QoS register node
cc3c4cf475e2 dt-bindings: mfd: syscon: Add rk3528 QoS register compatible
de0d9c50f68f ASoC: dt-bindings: fsl,imx-asrc: Document audio graph port
2e3ffd78169f ASoC: dt-bindings: add regulator support to dmic codec
0946c7535fed dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop unnecessary status from example
0d08b7785cbf dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop deprecated windows
499ff8f6f00e dt-bindings: crypto: qcom,prng: document QCS615
137ebe3e9e23 dt-bindings: crypto: inside-secure,safexcel: Allow dma-coherent
19a0ed3478a5 dt-bindings: net: Add support for Sophgo SG2044 dwmac
01ec431b0809 dt-bindings: display/msm: dsi-controller-main: Add missing minItems
899bbe0128ad dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries
b6b83575709d dt-bindings: memory-controllers: qcom,ebi2: Enforce child props
7a5a115214b1 dt-bindings: memory-controllers: samsung,exynos4210-srom: Enforce child props
5cbcded3d915 arm64: tegra: p2180: Add TMP451 temperature sensor node
bb4e0081de49 arm64: tegra: p2597: Enable TCA9539 as IRQ controllers
64bca56d40df arm64: tegra: Define pinmuxing for gpio pads on Tegra210
a2afd5dbc694 arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator
3074f948c0f0 arm64: tegra: Resize aperture for the IGX PCIe C5 slot
0556e73ad468 arm64: tegra: Remove the Orin NX/Nano suspend key
5075ae527c32 dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible
b2d611510011 dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible
e25abb336b06 dt-bindings: timer: Correct indentation and style in DTS example
27659631b1ab ARM: dts: marvell: armada: Align GPIO hog name with bindings
45d76d30bd18 ARM: dts: marvell: kirkwood-openrd: Align GPIO hog name with bindings
ed88cf59518a arm64: dts: marvell: armada-8040: Align GPIO hog name with bindings
fd8985afa234 dt-bindings: Document Tegra114 HDA support
514aa1e9d711 dt-bindings: display: tegra: Document Tegra124 MIPI
6f895e2fc34b Merge branch 'for-6.15/io_uring-rx-zc' into for-6.15/io_uring-reg-vec
783a9ff2b877 arm64: dts: tesla: Change labels to lower-case
fb95fa637210 arm64: dts: exynos: gs101: Change labels to lower-case
8bb1ecf374d2 arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style
b7183e25919b arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style
d3e54c73fad8 arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags
c198a9892aee arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags
7adcaf738ea2 arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags
08a8be409da1 Merge tag 'ath-next-20250305' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
b6eb736bdac9 dt-bindings: irq: sun7i-nmi: Document the Allwinner A523 NMI controller
29c23eb9e1e4 dt-bindings: net: Add FSD EQoS device tree bindings
7fcf7786e3c1 dt-bindings: ieee802154: ca8210: Update polarity of the reset pin
63f785ba85d6 dt-bindings: i3c: silvaco: Add npcm845 compatible string
4e7d4a0a5a98 dt-bindings: i3c: dw: Add power-domains
60779b9e5efd arm64: dts: apple: t8015: Add backlight nodes
d1c2cf3d6db3 arm64: dts: apple: t8010: Add backlight nodes
c493ad2b695a arm64: dts: apple: s800-0-3: Add backlight nodes
2a527cb076cb arm64: dts: apple: t7000: Add backlight nodes
8c09890d8a3a arm64: dts: apple: s5l8960x: Add backlight nodes
644d720366d7 spi: dt-bindings: fsl-lpspi: Add i.MX94 support
43baf3d00dd4 ARM: tegra: tf101: Add al3000a illuminance sensor node
01ff58401e94 dt-bindings: display: mitsubishi,aa104xd12: Adjust allowed and required properties
76f79fd8d2e1 dt-bindings: display: mitsubishi,aa104xd12: Allow jeida-18 for data-mapping
753638f98d53 ARM: tegra: Add DSI-A and DSI-B nodes on Tegra124
0dc63e559158 ARM: tegra: Add HDA node on Tegra114
c21c9d411a7b ARM: tegra: Add ARM PMU node on Tegra114
c169b6a13648 ARM: tegra: Switch DSI-B clock parent to PLLD on Tegra114
ce08790716a2 dt-bindings: media: mediatek,vcodec: Revise description
1d7d1f1bb863 dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count
84ee1a870bac Merge tag 'mtk-dts64-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
aded2fb69436 arm64: dts: nvidia: Remove unused and undocumented "regulator-ramp-delay-scale" property
ee85d6d69363 Merge tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
9591e80db9de Merge tag 'asahi-soc-dt-6.15-v2' of https://github.com/AsahiLinux/linux into soc/dt
c078f53218f7 Merge tag 'renesas-dts-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ba3eae2fe133 Merge tag 'renesas-dt-bindings-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
3077a635de45 Merge tag 'ixp4xx-dts-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
5dc02a7bec60 Merge tag 'asahi-soc-dt-6.15' of https://github.com/AsahiLinux/linux into soc/dt
131231dc887a arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable Mali-G31
f6f80ad2a1f4 arm64: dts: renesas: r9a09g057: Add Mali-G31 GPU node
bbda080c8952 arm64: dts: rockchip: add MNT Reform 2 laptop
eb0d04e0938d dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE)
ef01ba18d719 dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon
9d39d8aa54eb dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon
2f989dc849ab dt-bindings: PCI: fsl,imx6q-pcie: Add optional DMA interrupt
f139ea2f5a06 dt-bindings: PCI: Convert fsl,mpc83xx-pcie to YAML
1dfe7500437d dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
f83683dd6f9e arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel
9595aadd9a31 arm64: dts: mediatek: mt8395-nio-12l: Prepare MIPI DSI port
9f598f6af2a3 arm64: dts: mediatek: mt8390-genio-common: Add delay codec for DMIC
b152da61f6cd arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC
7f5ef01f6c71 arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline
7cefb6741548 arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays
bd0418035afa arm64: dts: mediatek: mt8195: Add base display controller graph
67a479e22dd9 arm64: dts: airoha: en7581: Fix clock-controller address
9f3a44607c09 arm64: dts: airoha: en7581: Add more nodes to EN7581 SoC evaluation board
6d3ac809c14a arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pins
f607df354b84 arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displays
b62844c6033e arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10
70636ab4c427 dt-bindings: PCI: altera: Add binding for Agilex
5f2ac732a000 dt-bindings: qcom: geni-se: Add 'firmware-name' property for firmware loading
eb0afea35cd3 ASoC: Merge up fixes
a7fdc3022cc4 dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
09611d37a4a2 dt-bindings: media: Document bindings for HDMI RX Controller
5733784ecab2 dt-bindings: gpio: loongson: Add new loongson gpio chip compatible
bde0820c0330 dt-bindings: pinctrl: Add bindings for BCM21664 pin controller
99ef71a02c72 dt-bindings: input: matrix_keypad - add wakeup-source property
6cc85963b28f arm64: dts: ti: k3-j722s-evm: Add camera peripherals
f57767d39255 arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes
5f079de69dbc arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides
fc74dd76227a arm64: dts: ti: k3-j722s: fix pinctrl settings
5916cffba231 arm64: dts: ti: k3-am62p: fix pinctrl settings
d442b5177760 arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector
598a53f305e4 dt-bindings: remoteproc: qcom,wcnss-pil: Add support for single power-domain platforms
cda103526016 dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8926
893c449685ce dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8226
e9fa3e49686b dt-bindings: remoteproc: qcom,msm8916-mss-pil: Support platforms with one power domain
c9ba86664ced dt-bindings: remoteproc: Add SM8750 CDSP
0727f5f07392 dt-bindings: display/msm: qcom, sa8775p-mdss: Add missing eDP phy
0e759e398167 dt-bindings: remoteproc: qcom,sm6115-pas: Use recommended MBN firmware format in DTS example
ad59df2a8e47 dt-bindings: net: Convert fsl,gianfar to YAML
ecac8517df71 dt-bindings: net: fsl,gianfar-mdio: Update information about TBI
9f27542c356c dt-bindings: net: Convert fsl,gianfar-{mdio,tbi} to YAML
f3d1127d6da2 arm64: dts: rockchip: Enable hdmi display on sige5
4353815d5413 arm64: dts: rockchip: Add hdmi for rk3576
e898135e14ac arm64: dts: rockchip: Add vop for rk3576
c4a8c85028f9 ARM: dts: microchip: sama7g5: add ADC hw trigger edge type
e415d0ace351 ASoC: fsl_audmix: support audio graph card for audmix
81dd10b4d87c dt-bindings: arm: Add Coresight TMC Control Unit hardware
5ffae977c446 Merge tag 'wireless-next-2025-03-04-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
8cdbfaccfe40 dt-bindings: iio: adc: ad7380: add adaq4381-4 compatible parts
c35357650277 dt-bindings: iio: adc: Add rockchip,rk3562-saradc string
ffdcbd963d7a dt-bindings: iio: adc: Add rockchip,rk3528-saradc variant
9ca8f9827434 arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3588 boards
f8fb45ddefb3 arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3399 ROC PC PLUS
45ccbb3708d1 dt-bindings: iio: light: al3010: add al3000a support
2dcb97b015ba Add STM32MP25 SPI NOR support
663e168d3026 ASoC: dt-bindings: everest,es8328: Require reg property
5973f33d36e4 ASoC: dt-bindings: everest,es8328: Mark ES8388 compatible with ES8328
d5fdb2909430 dt-bindings: net: airoha: Add airoha,npu phandle property
4b02ac198dfd dt-bindings: net: airoha: Add the NPU node for EN7581 SoC
9bcf6ccdd87c arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
89a24fa2e923 arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
340a7d991681 dt-bindings: soc: rockchip: Add RK3528 ioc grf syscon
2484bd1527c8 dt-bindings: mtd: physmap: Ensure all properties are defined
9a114f2cbbc5 dt-bindings: mtd: mxc-nand: Document fsl,imx31-nand
33bcbf56e498 dt-bindings: gpio: mvebu: Add missing 'gpio-ranges' property and hog nodes
9a17c1dc8a52 dt-bindings: pinctrl: Add pinctrl support for RK3528
a8fac5afd00e dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
3d038aa84fac dt-bindings: display: vop2: Add rk3576 support
539c3db87e49 dt-bindings: display: vop2: Add missing rockchip,grf property for rk3566/8
fc2f169c14d8 dt-bindings: display: vop2: describe constraint SoC by SoC
a9175c1faaf6 arm64: dts: apple: Add touchbar screen nodes
0a30c2fb605b dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property
6c0991dfe309 ARM: dts: microchip: sama7d65: Add watchdog for sama7d65
3a5c0b5439e4 arm64: dts: corstone1000: Add definitions for secondary CPU cores
760344eaf4df dt-bindings: clock: imx8m: document nominal/overdrive properties
3ebf9fab8556 dt-bindings: display: Add Apple pre-DCP display controller
45f020c2ff12 dt-bindings: clock: imx8mp: add axi clock
25a9aae37c46 ASoC: dt-bindings: fsl,audmix: make 'dais' property to be optional
39ab44f1f451 ASoC: dt-bindings: fsl,audmix: Document audio graph port
751e72c4a42f ASoC: dt-bindings: fsl,sai: Document audio graph port
375185829d56 spi: dt-bindings: Introduce qcom,spi-qpic-snand
ca5abc134e5c dt-bindings: spi: Add STM32 OSPI controller
18e6b1036205 dt-bindings: PCI: amd-mdb: Add AMD Versal2 MDB PCIe Root Port Bridge
f8432e8085b8 dt-bindings: PCI: dwc: Add AMD Versal2 MDB SLCR support
f3240bd9ff15 dt-bindings: usb: samsung,exynos-dwc3: add exynos7870 support
578e6366fe17 dt-bindings: usb: dwc3: Add support for rk3562
9c7380c08c12 dt-bindings: usb: generic-xhci: Allow dma-coherent
f5355ed2d30b dt-bindings: usb: richtek,rt1711h: Add missing vbus power supply
2fecbb897235 dt-bindings: pinctrl: samsung: add exynos7870-wakeup-eint compatible
6acd675fdb2b dt-bindings: pinctrl: samsung: add exynos7870-pinctrl compatible
64247b825e83 arm64: dts: qcom: gaokun3: Add Embedded Controller node
0de83bdbd702 dt-bindings: platform: Add Huawei Matebook E Go EC
8c7e026bceb2 arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks
b0f3437e4eed arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx
7abf45296c55 dt-bindings: hwmon: gpio-fan: Add optional regulator support
ad715d63d5b9 dt-bindings: hwmon: Add UCD90320 gpio description
94282ccb3f77 dt-bindings: hwmon: ntc-thermistor: fix typo regarding the deprecation of the ntc, compatibles
37c47e53b269 dt-bindings: display: mediatek: dsc: Add MT8188 compatible
a880ab46aaf3 ARM: dts: microchip: sama7d65: Enable shutdown controller
5bf0dfe3a93e ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ceb3ca267777 ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
33d484179e01 ARM: dts: microchip: sama7d65: Add Shutdown controller support
3a833187b48a ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
cb7d22318d14 arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory
de40a5c334d5 arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory
c1de68dfb465 arm64: dts: ti: k3-am62p5-sk: Add serial alias
fc3a3408782e arm64: dts: ti: k3-am62a7-sk: Add serial alias
89fb433abb4a arm64: dts: ti: k3-am62x-sk-common: Add serial aliases
b40599be6e89 arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup
4e21f0928a3c arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA
0e6efc73fbc4 arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3
e62cc3a65c52 arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3
df13b922a34e arm64: dts: ti: k3-am62p-j722s-common-wakeup: Configure ti-sysc for wkup_uart0
d5e905102b12 arm64: dts: ti: k3-am62a7-sk: Add alias for RTC
f0a08fa6651e arm64: dts: ti: k3-j721s2-som-p0: Add flash partition details
49435c1a2a18 arm64: dts: ti: k3-am62-verdin-dahlia: add Microphone Jack to sound card
dbb5bd13ad09 arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size
e42f6f652b25 arm64: dts: ti: k3-am62p5-sk: Add boot phase tag for USB0
d6d559bbf2a6 arm64: dts: ti: k3-am62a7-sk: Add boot phase tag for USB0
26e1b575e84d dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat
c32424d952a8 dt-bindings: crypto: Convert fsl,sec-2.0 to YAML
83100c586db1 dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
839f40a5722d dt-bindings: clock: add Exynos2200 SoC
22fe2b154172 dt-bindings: iommu: qcom,iommu: Add MSM8937 IOMMU to SMMUv1 compatibles
34189497288b dt-bindings: pwm: rockchip: Add rockchip,rk3562-pwm
9afffc8f0f22 dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format
7fa643245f20 dt-bindings: gpu: Add rockchip,rk3562-mali compatible
3abda087dbf6 Merge branch 'v6.15-shared/clkids' into v6.15-clk/next
8cd451e705ff dt-bindings: clock: Add RK3562 cru
1f94b7afa565 arm64: dts: rockchip: add usb typec host support to rk3588-jaguar
05453dc67f58 dt-bindings: wireless: ath12k: Strip ath12k prefix from calibration property
da3621d60f14 dt-bindings: wireless: ath11k: Strip ath11k prefix from calibration property
6fdc1d052416 dt-bindings: wireless: ath10k: Strip ath10k prefix from calibration properties
9861592542dd dt-bindings: display/msm/gmu: Add Adreno 623 GMU
8e07cd8d79b5 arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588
4c6cdea070ff mdomain: Merge branch dt into next
af3fb092d876 dt-bindings: power: rockchip: add regulator support
1de33272f6b5 pmdomain: Merge tag 'v6.14-rc4' from Linus into next
922c569881d6 ARM: dts: microchip: fix faulty ohci/ehci node names
2a4f0bc75929 ARM: dts: microchip: usb_a9263: fix wrong vendor
22c00bf9a9ec dt-bindings: ARM: at91: add Calao USB boards
00a259802c74 dt-bindings: ARM: at91: make separate entry for Olimex board
f7ecad4dfdba arm64: dts: amlogic: g12: switch to the new PWM controller binding
e594907dbba0 arm64: dts: amlogic: axg: switch to the new PWM controller binding
0db68c194ba8 arm64: dts: amlogic: gx: switch to the new PWM controller binding
07569029f06a ARM: dts: amlogic: meson8b: switch to the new PWM controller binding
45a895b33ca6 ARM: dts: amlogic: meson8: switch to the new PWM controller binding
ecad1190684f dt-bindings: input: matrix_keypad - add missing property
7a5e2e594dcc Merge branch 'ib-amlogic-a4' into devel
84ad7c66e08d dt-bindings: pinctrl: Add support for Amlogic A4 SoC
81d115cd787a Merge branch 'ib-sophgo' into devel
2fb57a80ac82 dt-bindings: pinctrl: Add pinctrl for Sophgo SG2042 series SoC
d25e98a2e1d9 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
9d4fce6bf871 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b0f9f15fa3eb arm64: dts: rockchip: Enable HDMI1 audio output for Orange Pi 5 Ultra
cb7a017df5cc arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Ultra
7a10dcdcf5dd arm64: dts: rockchip: Add Orange Pi 5 Ultra board
bb2d35f7447a dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Ultra
c61a839ade98 arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and Ultra
f46eeb290a49 arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX
8abf4e075936 arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B
a779ebd82fb1 arm64: dts: rockchip: Add HDMI audio outputs for rk3588
b0c3cbe5b68d arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1
40f977e4d24d arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588
2f30db59cf45 arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
027b0ef80afb spi: dt-bindings: Add rk3562 support
2533797ddce2 arm64: dts: morello: Add support for fvp dts
9f5663971e1f arm64: dts: morello: Add support for soc dts
3ff25bf13939 arm64: dts: morello: Add support for common functionalities
64de0a722178 dt-bindings: arm-pmu: Add support for ARM Rainier PMU
503c66e651f9 dt-bindings: arm: Add Rainier compatibility
f67be59b2a9a dt-bindings: arm: Add Morello fvp compatibility
9cb3ba5bb59e dt-bindings: arm: Add Morello compatibility
910e9d8438ef mips: dts: ralink: mt7628a: update system controller node and its consumers
0e7913ce1f04 dt-bindings: display: panel: Add Visionox RM692E5
33660ef35f42 dt-bindings: display: panel: Add Raydium RM67200
b9abbea75728 ARM: dts: stm32: add usr3 LED node to stm32f769-disco
972663879bc7 ARM: dts: stm32: rename LEDs nodes for stm32f769-disco
f5f056e5d15d ARM: dts: stm32: add push button to stm32f746 Discovery board
9209e9fa6ca9 ARM: dts: stm32: add led to stm32f746 Discovery board
c572b069bf16 dt-bindings: dma: fsl,edma: Add i.MX94 support
421f8d787226 dt-bindings: dma: atmel: add microchip,sama7d65-dma
3630c655aafd dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock
8f22583cbe0b arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4B
175b6ab4addb docs: dt: submitting-patches: Document sending DTS patches
12f69f638472 arm64: dts: rockchip: Add UART clocks for RK3528 SoC
60741472b42e arm64: dts: rockchip: Add clock generators for RK3528 SoC
9d809a089686 Merge branch 'v6.15-shared/clkids' into v6.15-armsoc/dts64
4b92d7bf7d17 Merge branch 'v6.15-shared/clkids' into v6.15-clk/next
8768d063e732 dt-bindings: clock: Document clock and reset unit of RK3528
eb4fa305444d powerpc/microwatt: Add SMP support
eb2feccfe7cb powerpc/microwatt: Device-tree updates
b01ec0c00687 arm64: dts: apple: Add touchbar digitizer nodes
99a9210485d1 ARM: dts: stm32: Add Priva E-Measuringbox devicetree
db39291d4cd4 ARM: dts: stm32: Add thermal support for STM32MP131
736b25b842a6 dt-bindings: arm: stm32: Add Priva E-Measuringbox board
ac84513b3de1 dt-bindings: vendor-prefixes: Add prefix for Priva
153d1dded8e2 ASoC: dt-bindings: xlnx,spdif: Convert to json-schema
1dfc9272871a ASoC: dt-bindings: xlnx,audio-formatter: Convert to json-schema
c05b804fd27e ASoC: dt-bindings: xlnx,i2s: Convert to json-schema
e6b5549e2ea1 dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg'
81c7d959642a dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg'
d788495c297e dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC
ef078fa51469 dt-bindings: gpio: nxp,pcf8575: add reset GPIO
e60b526a254b dt-bindings: display: qcom,sm8650-mdss: explicitly document mdp0-mem and cpu-cfg interconnect paths
5f6c7f3a882b dt-bindings: display: qcom,sm8550-mdss: explicitly document mdp0-mem and cpu-cfg interconnect paths
564ffb04cbff dt-bindings: display/msm/dsi-phy: Add header with exposed clock IDs
dfe70ec7cf52 riscv: sophgo: dts: Add msi controller for SG2042
05d993f3a6ec dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI
a3b737ca15b2 Merge tag 'v6.14-rc4' into next
f3b5bc2ab93f dt-bindings: display/lvds-codec: add ti,sn65lvds822
b20b0aace0f0 dt-bindings: input: matrix_keypad: add settle time after enabling all columns
c6644ddbabe0 dt-bindings: input: matrix_keypad: convert to YAML
0204ceb1dac8 Enable DMIC for Genio 700/510 EVK
aaa0adb4e4ba dt-bindings: input: Correct indentation and style in DTS example
1bd35f025a98 ASoC: dt-bindings: fsl: Reference common DAI
9d01b52dd742 ASoC: dt-bindings: mediatek,mt8188-mt6359: Add DMIC backend to dai-link
4b7def7c217f Fix RK3588 power domain problems
02d8831bddbd ASoC: dt-bindings: fsl,imx-asrc: Reference common DAI properties
2756dbc5dccb ASoC: dt-bindings: fsl,easrc: Reference common DAI properties
be1e7ad12db3 Merge drm/drm-next into drm-misc-next
9876c6970616 dt-bindings: display: simple: Add BOE AV123Z7M-N17 panel
740d6f024cb4 dt-bindings: display: simple: add BOE AV101HDT-A10 panel
695f9094dd3e arm64: dts: mediatek: mt8188: Add base display controller graph
d953922a6352 arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX
4a972b5813a9 arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB
c926d7135987 dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
3479b8607126 arm64: dts: mediatek: mt8395-genio-1200-evk: add support for TCPC port
1ea007fec939 dt-bindings: usb: mtu3: Add ports property
81bb891f02a1 arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator name
c2ee67f8f91c arm64: dts: mediatek: mt8183: Switch to Elan touchscreen driver
1480b2b9c163 Merge tag 'v6.14-rc4' into drm-next
19566af01522 arm64: dts: imx8mm-phycore-som: Add overlay to disable SPI NOR flash
4d957d8455fd arm64: dts: imx8mm-phycore-som: Add no-eth phy overlay
e38b34b397ca arm64: dts: imx8mm-phycore-som: Add overlay for rproc
1d49d21dd81e arm64: dts: imx8mm-phyboard-polis: Add overlay for PEB-EVAL-01
3e8bdd2e0853 arm64: dts: imx8mm-phyboard-polis: Add support for PEB-AV-10
ea91b13eb856 arm64: dts: imx8mm-phyboard-polis: Assign missing regulator for bluetooth
884d4632d049 arm64: dts: imx8mm: move bulk of rtc properties to carrierboards
3bfc2236c593 arm64: dts: imx8mm-phygate-tauri-l: Set RTC as wakeup-source
1ca2b9c5de6b arm64: dts: imx8mm-phyboard-polis: Set RTC as wakeup-source
2a508a6ff135 arm64: dts: imx8mm-phyboard-polis: add RTC description
b9ef6209b80f arm64: dts: imx8mm-phycore-som: add descriptions to nodes
fa73714ac0c3 arm64: dts: imx8mm-phycore-som: Assign regulator for dsi to lvds bridge
b37946788b2f arm64: dts: imx8mm-phycore-som: Remove magic-packet property
8016d32846f7 arm64: dts: imx8mm-phycore-som: Fix bluetooth wakeup source
9d8e0c3c4f7c arm64: dts: imx8mm-phycore-som: Keep LDO3 on in suspend
b69b4e83993e arm64: dts: freescale: imx8mm-verdin: Remove LVDS panel and backlight
47beab578f6c arm64: dts: colibri-imx8x: Add missing gpio-line-names
20c64688c512 arm64: dts: s32g: add the eDMA nodes
a17008eb460a arm64: dts: imx95: add PCIe's msi-map and iommu-map property
13bbffb4e884 arm64: dts: imx8q: add PCIe EP overlay file for i.MX8QXP mek board
55a2bc97a378 arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP
5e82dd84d613 arm64: dts: imx8-ss-hsio: fix indentation in pcie node
6114dc137559 arm64: dts: freescale: tqma8mqnl: Add vcc-supply for spi-nor
aa74db634145 arm64: dts: freescale: tqma8mqml: Add vcc-supply for spi-nor
8ac725ad672e arm64: dts: freescale: tqma8mq: Add vcc-supply for spi-nor
0b92969081bc arm64: dts: freescale: tqma8mpql: Add vcc-supply for spi-nor
e82710a7796c arm64: dts: imx8-apalis: add clock configuration for 44.1 kHz hdmi audio
05db5bdaa953 arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
50df896ee8a8 arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
e01e9b9dd62f arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
8be8d6f5fd39 arm64: dts: imx8qxp-mek: Complete WM8960 power supplies
1f7da937625a arm64: dts: imx8qm-mek: Complete WM8960 power supplies
6cb4cf4a8959 arm64: dts: imx8dxl-evk: Complete WM8960 power supplies
a823b8504cfc arm64: dts: imx8mp-evk: Complete WM8960 power supplies
f0fb71d2bfd2 arm64: dts: tqma9352-mba93xx[cl]a: swap ethernet aliases
e6c58c4e34f5 arm64: dts: mba93xxca: Do not assert power-down pins
34a0e3de0c9d arm64: dts: freescale: imx93-tqma9352-mba93xxca: sort pinctrl nodes
b41df0cb89cc arm64: dts: mba8xx: Add PCIe support
d0a618f195f1 arm64: dts: tqma8xx: Remove GPU TODO
43419b7de367 arm64: dts: tqma8xx: enable jpeg encode and decode
8eaabcf5b237 arm64: dts: tqma8xx: Add vcc-supply for spi-nor
a1706580b459 arm64: dts: imx8-ss-hsio: Wire up DMA IRQ for PCIe
abcd89649f74 arm64: dts: imx8mn-bsh-smm-s2pro: Remove invalid audio codec clock
73b9c2a4d2cf arm64: dts: imx8mp-skov: increase I2C clock frequency for RTC
15dad674cdf5 arm64: dts: imx8mp-skov: fix phy-mode
35f9d08e683e arm64: dts: imx8mp-skov: describe mains fail detection
918eb1e7f304 arm64: dts: imx8mp-skov: configure uart1 for RS485
b1c4121e92da arm64: dts: imx8mp-skov: describe LVDS display pipeline
4f3d28e9954c arm64: dts: imx8mp-skov: describe HDMI display pipeline
74ff20266638 arm64: dts: imx8mp-skov: use I2C5 for DDC
5ee605182ffa arm64: dts: imx8mp-skov: operate CPU at 850 mV by default
b9feeafd2708 arm64: dts: imx8mp-skov: correct PMIC board limits
6a3290b43d38 arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal
afb10648ca50 arm64: dts: imx93-kontron: Fix SD card IO voltage control
7822c3bd0f88 arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal
b90dec14cbfd ARM: dts: imx7d-sdb: Complete WM8960 power supplies
96289b986803 ARM: dts: imx6ul-14x14-evk: Complete WM8960 power supplies
baa99fba4fbd scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC
e1e953869373 scsi: ufs: dt-bindings: Document Rockchip UFS host controller
af1e5d055507 dt-bindings: PCI: brcmstb: Update bindings for PCIe on BCM2712
88b7337af159 dt-bindings: interrupt-controller: Add BCM2712 MSI-X bindings
e08f82eefaa7 dt-bindings: PCI: qcom-ep: Add SAR2130P compatible
4fd2560c686b dt-bindings: PCI: qcom-ep: Consolidate DMA vs non-DMA cases
652e3a3e15ee dt-bindings: PCI: qcom-ep: Enable DMA for SM8450
ffe279433d99 dt-bindings: PCI: qcom-ep: Describe optional IOMMU
cb5305df80d2 dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property
9585b1fcf51a ASoC: dt-bindings: imx-card: Add playback-only and capture-only property
ed671a626791 dt-bindings: atmel-sysreg: Add SAMA7D65 Chip ID
6096197138a9 ARM: dts: microchip: sama7d65: Enable DMAs
e76971437b8a arm64: dts: ti: k3-j722s-evm: Fix USB2.0_MUX_SEL to select Type-C
ad4c5c253cfc ARM: dts: microchip: sama7d65: Add DMAs to sama7d65 SoC
21d60212633f ARM: dts: microchip: sama7d65: Add chipID for sama7d65
0ce77a32a2e4 arm64: dts: ti: k3-j784s4-evm-quad-port-eth-exp1: Remove duplicate hogs
b2c185c86ce6 arm64: dts: ti: k3-am62a-mcu: enable mcu domain pinmux
34a41a24c946 Merge tag 'v6.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into HEAD
1a8fe57c561b arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
53d1e146b05c ARM: dts: imx28-sps1: Fix GPIO LEDs description
10884a5224f4 ARM: dts: vf610-bk4: Use the more specific "lwn,bk4-spi"
edd698009292 arm64: dts: rockchip: disable I2C2 bus by default on RK3588 Tiger
9be02103e21d arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSI
5743a9dda2c4 arm64: dts: rockchip: enable Ethernet in Haikou carrierboard, not Puma DTSI
2420a6d5e78c arm64: dts: rockchip: add EEPROM found on RK3399 Puma Haikou
529f82cf3ce9 arm64: dts: rockchip: enable I2S0 in Haikou carrierboard, not Puma DTSI
28cf8608f8d9 arm64: dts: rockchip: disable I2C6 on Puma DTSI
a7b506f792bf arm64: dts: rockchip: move I2C6 from Haikou carrierboard to Puma DTSI
55a866e88323 arm64: dts: rockchip: move DDC bus from Haikou carrierboard to RK3399 Puma DTSI
27fd1de71a59 arm64: dts: rockchip: enable UART5 on RK3588 Tiger Haikou
6c3bb559bac0 arm64: dts: rockchip: Add Radxa ROCK 4D device tree
3544351bd438 dt-bindings: arm: rockchip: Add Radxa ROCK 4D board
d67cf6de8aac arm64: dts: rockchip: add rk3576 otp node
231a534cd743 arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapter
abbc13f77a26 arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapter
046e0c70c93b arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 Ringneck
88fdb1f81232 dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
4bb141531379 arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
9fa5a7a0ef3c arm64: dts: allwinner: rg35xx: Add no-thermistor property for battery
31b4873bc1a6 arm64: dts: allwinner: h700: Add USB Host for RG35XX-H
a8a5f54af77e arm64: dts: allwinner: h700: Add LED1 for Anbernic RG35XX
d2ec9636e0dc arm64: dts: allwinner: h700: Set cpusldo to always-on for RG35XX
0e8ebe2be1eb dt-bindings: iio: Add adis16550 bindings
6ad196cd05d5 ARM: dts: mba6ul: change sound card model name
8ae441d65592 ARM: dts: imx7-mba7: change sound card model name
69323e39dc4e ARM: dts: imx6qdl-mba6: change sound card model name
6653d0117e05 dt-bindings: crypto: qcom-qce: Document the X1E80100 crypto engine
2c0efa8b0af1 dt-bindings: rng: add binding for Rockchip RK3588 RNG
23feff06013d dt-bindings: reset: Add SCMI reset IDs for RK3588
5b54b653b964 dt-bindings: gpu: mali-bifrost: Add Allwinner H616 compatible
cd5fe0987644 dt-bindings: trivial-devices: Add ti,tps53681
2be45ede3cbe dt-bindings: net: Add Realtek MDIO controller
afae7a251c1c dt-bindings: net: Add switch ports and interrupts to RTL9300
91d08b436193 dt-bindings: net: Move realtek,rtl9301-switch to net
aaf093926eff dt-bindings: gpu: mali-bifrost: Add compatible for RZ/V2H(P) SoC
2819855d187d mips: dts: ralink: mt7620a: update system controller node and its consumers
a2166e814c84 mips: dts: ralink: rt3883: update system controller node and its consumers
339e08846279 mips: dts: ralink: rt3050: update system controller node and its consumers
d3abcf7cf3ae mips: dts: ralink: rt2880: update system controller node and its consumers
84e9b0c2fff8 dt-bindings: clock: add clock definitions for Ralink SoCs
c28b259be385 dt-bindings: arm: coresight-tmc: Add "memory-region" property
f1546685ce0f ARM: dts: renesas: r9a06g032: Fix UART dma channel order
6a6883b926ad arm64: dts: renesas: rzg2: Add boot phase tags
9abb2281477d arm64: dts: renesas: rcar: Add boot phase tags
7795d76bbbc2 ARM: dts: renesas: rcar-gen2: Add boot phase tags
9e0d9f1c47ea arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line orders
dc4f388ab13e arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for capture
7dbc206c43da arm64: dts: renesas: Add initial support for MYIR Remi Pi
ee00ebca3993 arm64: dts: renesas: r9a08g045: Add OPP table
61c8b03d8ef2 arm64: dts: renesas: r9a09g057: Enable SYS node
0815ca2096bf arm64: dts: renesas: r9a09g047: Add SYS node
c36b3a2f01df arm64: dts: renesas: r9a08g045: Enable SYS node
e6d40d0d2cfb arm64: dts: renesas: r8a779f0: Disable rswitch ports by default
44cb5b4c5426 arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
703f038f08d8 arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
6706d23f287c arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches
90d900e27288 arm64: dts: renesas: r8a779g0: Restore sort order
78dba0214fc6 arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitch
65e95070b6ba arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitch
caed2eab1bd4 arm64: dts: renesas: s4sk: Access rswitch ports via phandles
1cacb8200b69 arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles
a7c45e21fd00 arm64: dts: renesas: r8a779f0: Add labels for rswitch ports
d4ed59cf46f5 arm64: dts: renesas: Add initial device tree for Yuridenki-Shokai Kakip board
e359d28948ce arm64: dts: renesas: eagle-function-expansion: Align GPIO hog name with bindings
3d56ae096af8 arm64: dts: renesas: r8a779h0: Add VSPX instance
ae94b3852fbe arm64: dts: renesas: r8a779h0: Add FCPVX instance
ba28a5391cc6 arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog
bb86f1ab211a arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes
bdfecb224c52 arm64: dts: renesas: gray-hawk-single: Restore sort order
149c2679df26 arm64: dts: renesas: r8a779a0: Add VSPX instances
afdd241afcbc arm64: dts: renesas: r8a779a0: Add FCPVX instances
6c91cfa7eda2 arm64: dts: renesas: gray-hawk-single: Describe AVB1 and AVB2
a6305fea1136 arm64: dts: renesas: r8a779h0: Remove #address- and #size-cells from AVB[0-2]
e384ea6d2c06 arm64: dts: renesas: r8a77990: Re-add voltages to OPP table
b94a86f224ed arm64: dts: renesas: r8a774c0: Re-add voltages to OPP table
73035ca45197 mips: dts: realtek: Add restart to Cisco SG220-26P
da5e72c52240 mips: dts: realtek: Add RTL838x SoC peripherals
e1258dbdceed mips: dts: realtek: Replace uart clock property
05fddbb7ebd9 mips: dts: realtek: Correct uart interrupt-parent
a457e7128f11 mips: dts: realtek: Add SoC IRQ node for RTL838x
57bde8194b75 mips: dts: realtek: Fold rtl83xx into rtl838x
64c98fba1502 mips: dts: realtek: Add address to SoC node name
9f6b4016f45a mips: dts: realtek: Clean up CPU clocks
a015cd4a0443 mips: dts: realtek: Decouple RTL930x base DTSI
e452c3447525 MIPS: mobileye: dts: eyeq6h: Enable cluster support
4913d71e6942 dt-bindings: mips: mips-cm: Add a new compatible string for EyeQ6
0b2d5fd80af4 dt-bindings: mips: Document mti,mips-cm
a429699ec2e2 dt-bindings: ata: Convert fsl,pq-sata to YAML
ac47e5894fc3 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
93b63c5675fe media: dt-bindings: adv7180: Document the 'interrupts' property
a1c70718bc0f media: dt-bindings: aspeed,video-engine: Convert to json schema
4da9a2e40dd4 dt-bindings: media: st,stmipid02: correct lane-polarities maxItems
ae847cba005e mips: dts: ingenic: Switch to simple-audio-card,hp-det-gpios
f72623fbd64c arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI
573d01eb7714 arm64: dts: rockchip: rk356x: Add MSI controller node
a62671cb3851 dt-bindings: xilinx: Deprecate header with firmware constants
d48d272341e2 arm64: zynqmp: Use DT header for firmware constants
c2265415c9c1 dt-bindings: power: supply: axp20x-battery: Add x-powers,no-thermistor
1c2d49b11f41 dt-bindings: vendor-prefixes: Document the 'pciclass' prefix
8fe54d8c1e6a dt-bindings: trivial-devices: Add ti,tps546b24
0c947a496323 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
ea5adb18bcaf dt-bindings: mfd: Add maxim,max77705
f5071bfa82eb dt-bindings: power: supply: add maxim,max77705 charger
26b6ca520742 dt-bindings: leds: qcom-lpg: Document PM8937 PWM compatible
115f06126ec6 dt-bindings: leds: backlight: apple,dwi-bl: Add Apple DWI backlight
ec6ae18eb982 spi: dt-bindings: Convert Freescale SPI bindings to YAML
b24a6dbfc7c3 Merge tag 'linux-can-next-for-6.15-20250219' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
a17a9095c7fa ARM: dts: nxp: vf: Align GPIO hog name with bindings
90cfeb11e6bd dt-bindings: net: dsa: b53: add BCM53101 support
6df8500248bb dt-bindings: power: reset: xilinx: Make "interrupts" property optional
84dd8dd4c6b0 dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc
24ab1372bbf2 dt-bindings: input: touchscreen: Add Z2 controller
2dbbd7ff619b ASoC: dt-bindings: atmel-at91sam9g20ek: convert to json-schema
2e73e48c20e4 dt-bindings: usb: samsung,exynos-dwc3 Add exynos990 compatible
c554695fa890 USB: docs: Fix typo in aspeed-lpc.yaml
6f18dd0694b2 dt-bindings: usb: usb-device: Replace free-form 'reg' with constraints
f57d58abdd1f dt-bindings: usb: microchip,usb2514: add support for USB2512/USB2513
22c582f7410c dt-bindings: usb: microchip,usb2514: add support for vdda
bbd705c2b5f9 dt-binding: can: mcp251xfd: remove duplicate word
5ccbb5ed0811 dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support
b3155d3e94f8 dt-bindings: pinctrl: samsung: add exynos2200 compatible
b6ea4790ddc5 dt-bindings: pinctrl: samsung: add exynos2200-wakeup-eint compatible
c7b5bd42aef7 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos2200 compatible
85d161c64b09 dt-bindings: soc: samsung: exynos-pmu: add exynos2200 compatible
467349660659 dt-bindings: soc: samsung: exynos-sysreg: add sysreg compatibles for exynos2200
f3a49191d711 arm64: dts: apple: Add SPI NOR nvram partition to all devices
32fb252ce1f3 arm64: dts: apple: t600x: Add spi controller nodes
7b672e8683fb arm64: dts: apple: t8112: Add spi controller nodes
11383e8e5d7f arm64: dts: apple: t8103: Add spi controller nodes
df2301056fc8 arm64: dts: apple: t8103: Fix spi4 power domain sort order
588bf84fbfc5 riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
2260adebc79d riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
d46cea021cfc riscv: dts: starfive: fml13v01: enable pcie1
aca9a5c6177d riscv: dts: starfive: remove non-existent dac from jh7110
714ea90c3680 arm64: dts: apple: t7000: Add missing CPU p-state 7 for J96 and J97
b27dd2587832 ARM: dts: imx5: Fix the CCM interrupts description
028660f03192 ARM: dts: vfxxx: Fix the CAAM job ring node names
18d135dfe74a arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codec
1341f30d43e8 Merge drm/drm-next into drm-misc-next
4e43cbdb48d1 ARM: dts: imx53-ppd: Fix touchscreen reset-gpios
4ba7c5cec4fc ARM: dts: imx7s: Move csi-mux to below root
1d0f023c6ebe riscv: sophgo: dts: add cooling maps for Milk-V Pioneer
67fd41fa38f7 riscv: sophgo: dts: add pwm-fan for Milk-V Pioneer
af97acf23d50 dt-bindings: net: ethernet-phy: add property tx-amplitude-100base-tx-percent
3c2fcb7fd8f4 arm64: versal-net: Add description for b2197-00 revA board
51a5e958e52c dt-bindings: soc: Add new VN-X board description based on Versal NET
b3d3914cdb96 ASoC: tas2764: Random patches from the Asahi Linux
17494bd5ec3e riscv: dts: spacemit: Add Milk-V Jupiter board device tree
7154a6c8889d dt-bindings: riscv: spacemit: Add Milk-V Jupiter board compatible
b42bf3977a7b Merge commit '71f0dd5a3293d75d26d405ffbaedfdda4836af32' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next into for-6.15/io_uring-rx-zc
7faa56193b95 ASoC: dt-bindings: wlf,wm8960: add 'port' property
eaa850920663 arm64: dts: imx95-19x19-evk: add typec nodes and enable usb3 node
d145eb78bb29 arm64: dts: imx95: add usb3 related nodes
9e8c9998017c ARM: dts: mxs: Add descriptions for imx287 based btt3-[012] devices
327f79156245 dt-bindings: arm: Document the btt3 i.MX28 based board
77f03f406681 arm64: dts: imx8qm-mek: add audio-codec cs42888 and related nodes
f55a6cd37037 arm64: dts: imx8mq-librem5: remove undocument property 'extcon' for usb-pd@3f
cfac8cba2afb ARM: dts: microchip: sama7d65_curiosity: Add power monitor support
713b56b62a21 arm64: dts: exynosautov920: add CPU cache information
95afa38c66b5 ARM: dts: microchip: sama7d65: Add flexcom 10 node
11815f2bda26 ARM: dts: at91: usb_a9g20_lpw: use proper mmc node name
f2f5d8164a85 ARM: dts: at91: calao_usb: fix button nodes
4320615849bc ARM: dts: at91: use correct vendor name for Calao boards
fc606a98fb4c ARM: dts: at91: calao_usb: remove heartbeat for User LEDs
adf5d3205c13 ARM: dts: at91: calao_usb: fix wrong polarity for LED
02b371776f9f Merge 6.14-rc3 into usb-next
c79ef81e8b3f Merge 6.14-rc3 into tty-next
5d5087e055bc dt-bindings: iio: adc: Introduce ADS7138
81b74faf1bbd dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632
4800c4aaad00 arm64: dts: rockchip: Add rng node to RK3588
fb5624b3aff6 dt-bindings: iio: adc: add ad4851
29c6d2f72796 dt-bindings: iio: adc: add ad485x axi variant
2aa06934b04b arm64: dts: exynos: gs101: add ACPM protocol node
9a410d40fffc arm64: dts: exynos: gs101: add AP to APM mailbox node
f67a8cbbc893 arm64: dts: exynos: gs101: add SRAM node
fd1eea66f8ff dt-bindings: firmware: add google,gs101-acpm-ipc
0c84b9a92cd8 dt-bindings: media: clarify stm32 csi & simplify example
cb82b9a812fb arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
cafb5b1128f9 arm64: dts: exynos: gs101: align poweroff writes with downstream
b7103d0c00e2 arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes
388e7272d092 arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
89026942ddd0 dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding
11054a56eb5e arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar
fa30dcce2020 dt-bindings: soc: qcom: qcom,pmic-glink: Document SM8750 compatible
df945fcbeec5 Merge branch '20250109-qcs8300-mm-patches-new-v4-0-63e8ac268b02@quicinc.com' into clk-for-6.15
7c12a4b2f62e dt-bindings: clock: qcom: Add QCS8300 video clock controller
1f3bb677cac5 dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
d11f22ad6f0e dt-bindings: clock: qcom: Add GPU clocks for QCS8300
fd809190482c Merge branch '20250203063427.358327-2-alexeymin@postmarketos.org' into clk-for-6.15
5980968a3736 dt-bindings: clock: gcc-sdm660: Add missing SDCC resets
024211d099c3 dt-bindings: clock: gcc-sdm660: Add missing SDCC resets
b8807b3e1cb2 dt-bindings: clock: qcom,rpmcc: Add SDM429
5bce17b9c9ff pmdomain: Merge branch dt into next
82ed9883247a dt-bindings: power: add V853 ppu bindings
68169a0560d8 dt-bindings: serial: Add bindings for nvidia,tegra264-utc
668773b787ac dt-bindings: serial: Allow fsl,ns16550 with broken FIFOs
9648d88104e5 dt-bindings: usb: Add Parade PS8830 Type-C retimer bindings
0c7c8b465ec2 dt-bindings: usb: dwc3: Add a property to reserve endpoints
e939f6d880e2 Merge tag 'drm-misc-next-2025-02-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
03f675fb2209 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a1e21c6557d7 dt-bindings: imx: fsl,aips-bus: Ensure all properties are defined
9367c9acdab1 dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings
4e5d9b054e9d dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties
7aa26eec3f52 dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties
8fc192d8c786 dt-bindings: display: bridge: sn65dsi83: Add interrupt
27bd4bb30fdc dt-bindings: power: rpmpd: Fix comment for SM6375
2a0abedef196 arm64: dts: mediatek: mt8188: Add tertiary eMMC/SD/SDIO controller
58186cbc681f arm64: dts: mediatek: mt8188: Add VDO0's DSC and MERGE block nodes
9385b92b564a arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang
04c7795892af ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
e672efae7f1f ARM: dts: ixp4xx: Fix up PCI on WG302
dfe984c10836 ARM: dts: Properly assign NPE to ethA
47c38f7af771 loongarch: dts: remove non-existent DAC from 2k1000-ref
aecbe697ed9a ARM: dts: cirrus: ep7211: Align GPIO hog name with bindings
a950ae069eeb arm64: dts: exynos8895: Rename PMU nodes to fixup sorting
6aebfac1f2e6 arm64: dts: mediatek: add device-tree for Genio 510 EVK board
0a53b5690395 arm64: dts: mediatek: mt8390-genio-700-evk: Move common parts to dtsi
cd85db03d191 arm64: dts: marvell: Add missing board compatible for IEI-Puzzle-M801
37f65442ac9b arm64: dts: marvell: Fix missing/incorrect "marvell,armada3710" compatible
3f3f0055504c arm64: dts: marvell: Drop incomplete root compatible/model properties
900bc3ca59b4 dt-bindings: marvell: armada-7k-8k: Add missing 7040 and 8040 board compatibles
fdd9abb2b187 dt-bindings: marvell: armada-7k-8k: Move Armada 8KPlus to schema
42c1447c23e2 dt-bindings: marvell: armada-37xx: Add glinet,gl-mv1000 compatible
94879a4116ea arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Max
2a8407332ac4 dt-bindings: pwm: Add support for PWM nexus node
481e9de30692 riscv: dts: starfive: Unify regulator naming scheme
a93373b7988b dt-bindings: media: camss: Add qcom,sdm670-camss
909002479174 arm64: dts: rockchip: linewrap gmac assigned-clocks on Quartz64 Model A/B files a bit
8457c997e974 arm64: dts: rockchip: remove rk3588 optee node
47e426fb98b2 dt-bindings: iio: dac: adi-axi-adc: add ad7606 variant
5116c83b9333 dt-bindings: iio: adc: adi,ad4695: add SPI offload properties
3ca14f0620da dt-bindings: leds: Convert leds-tlc591xx.txt to yaml format
e96e93245d76 dt-bindings: net: rfkill-gpio: enable booting in blocked state
1bf0b9eea5fd arm64: dts: rockchip: Enable HDMI1 out for Edgeble-6TOPS Modules
b0d56064489f arm64: dts: rockchip: Enable HDMI1 on rock-5b
873d0d388c38 arm64: dts: rockchip: Add HDMI1 node on RK3588
8716e9c85925 arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
ad3eee0eda32 arm64: dts: rockchip: Enable SPDIF output on H96 Max V58
e51f476b2549 arm64: dts: rockchip: Add SPDIF nodes to RK3588(s) device trees
71a14fc267ad dt-bindings: net: smsc,lan9115: Ensure all properties are defined
5de2b7dc7768 dt-bindings: memory-controllers: samsung,exynos4210-srom: Split out child node properties
cd66a94e6d99 dt-bindings: memory-controllers: qcom,ebi2: Split out child node properties
0c6820b22794 dt-bindings: memory-controllers: Move qcom,ebi2 from bindings/bus/
94d614fdbd9a Merge tag 'spi-offload' into togreg
92fae782ee1d Documentation: Remove repeated word in docs
cf9f02118fe1 dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints
37229c163579 dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY
913df9ddc676 dt-bindings: phy: Add rk3576 hdptx phy
33ebb61a9413 dt-bindings: display: panel: Add KD110N11-51IE and 2082109QFH040022-50E
d7efe5059077 dt-bindings: ASoC: rockchip: Add compatible for RK3588 SPDIF
9dd06b8dd8ac dt-bindings: dma: convert atmel-dma.txt to YAML
b25933f5b573 dt-bindings: vendor-prefixes: Update rockchip company name
a8e1f2c3f715 arm64: dts: rockchip: add dts for Ariaboard Photonicat RK3568
0b22b27cde74 dt-bindings: arm: rockchip: Add Ariaboard Photonicat RK3568
7ce8f717740a dt-bindings: vendor-prefixes: Add prefix for Ariaboard
17038a66bb8b arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset
a7fde791ce29 arm64: dts: rockchip: add 'chassis-type' property on PineNote
acd8eab1d823 dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1
7d004cf97e38 dt-bindings: soc: renesas: Document MYIR Remi Pi board
d798bb42d18b arm64: dts: apple: t8015: Add cpufreq nodes
142ff02c87ca arm64: dts: apple: t8012: Add cpufreq nodes
423ad63e9ff5 arm64: dts: apple: t8011: Add cpufreq nodes
6fd3a983e7aa arm64: dts: apple: t8010: Add cpufreq nodes
2327e547433d arm64: dts: apple: s8001: Add cpufreq nodes
a5f95a9c11ca arm64: dts: apple: Add cpufreq nodes for S8000/S8003
d48321d9c0a2 arm64: dts: apple: t7001: Add cpufreq nodes
5af5ae6d020a arm64: dts: apple: t7000: Add cpufreq nodes
62a511b2e51a arm64: dts: apple: s5l8960x: Add cpufreq nodes
66b42d66b597 arm64: dts: apple: t8015: Add PMGR nodes
0f7c9deb5489 arm64: dts: apple: t8012: Add PMGR nodes
0f9f2a165a57 arm64: dts: apple: t8011: Add PMGR nodes
cc770ee797ee arm64: dts: apple: t8010: Add PMGR nodes
ab8f4186a843 arm64: dts: apple: s8001: Add PMGR nodes
b5e2aa91fa41 arm64: dts: apple: s800-0-3: Add PMGR nodes
262b4c2c6b63 arm64: dts: apple: t7001: Add PMGR node
4eccd0ed15e8 arm64: dts: apple: t7000: Add PMGR node
5cad2b1f1511 arm64: dts: apple: s5l8960x: Add PMGR node
3ae627f53660 dt-bindings: arm: apple: apple,pmgr-pwrstate: Add A7-A11, T2 compatibles
cf1acfdcd1ab dt-bindings: arm: apple: apple,pmgr: Add A7-A11, T2 compatibles
e6b8b4eb2893 arm64: dts: apple: Add T2 devices
3635f84149d5 dt-bindings: arm: apple: Add T2 devices
ecb90807423a arm64: dts: apple: Split s8000/s8003 SoC DTS files
0332b153fa3e dt-bindings: crypto: Add Inside Secure SafeXcel EIP-93 crypto engine
ad30fd49aa1e ARM: dts: sunxi: add support for NetCube Systems Kumquat
0463c05da755 ARM: dts: sunxi: add uart1_pe pinctrl for sun8i-v3s
64ab025e91c5 dt-bindings: arm: sunxi: Add NetCube Systems Kumquat board
135ecb1c0900 dt-bindings: vendor-prefixes: Add NetCube Systems Austria name
ba07d9983cd2 dt-bindings: iio: adf4371: add refin mode
95eb7af6dfd3 dt-bindings: iio: light: Add APDS9160 binding
32ed0be023c0 dt-bindings: iio: magnetometer: add binding for Si7210
3d902b3b97b5 riscv: sophgo: dts: add pwm controller for SG2042 SoC
c6a0c59c390f spi: dt-bindings: axi-spi-engine: add SPI offload properties
26ad965c5d62 dt-bindings: trigger-source: add generic PWM trigger source
69e102cfc84d dt-bindings: display: panel: Add compatible for CSOT PNA957QT1-1
a854ffec9ddf dt-bindings: vendor-prefixes: add csot
66fd41e84bce dt-bindings: mtd: arasan,nand-controller: Ensure all properties are defined
e0661cab113c dt-bindings: media: Add video support for QCOM SM8550 SoC
1e83da324d74 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
d30a4e7e782c Add static channel mapping between soundwire master
f9d3323c1b73 ASoC: cpcap: Implement jack headset detection
926489106ec0 This is continued work on Samsung S9(SM-9600)
0332d1781ba7 dt-bindings: media: camss: Add qcom,sm8550-camss binding
c6a4614b770b media: dt-bindings: update clocks for sc7280-camss
4c1200c39b8f Merge drm/drm-next into drm-misc-next
70de7a1b60f4 ASoC: dt-bindings: wcd937x-sdw: Add static channel mapping support
33c6fb10fda1 arm64: dts: mediatek: add support for MT8370 SoC
3d0e1130cf33 dt-bindings: arm: mediatek: add mt8370-evk board
d2d62c5d0e90 arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
6605f13b8e1b arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
f962971332b4 arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
1d392f374a7e dt-bindings: display: vop2: Add optional PLL clock properties
5ab646d63942 dt-bindings: display: rockchip: Fix label name of hdptxphy for RK3588 HDMI TX Controller
c2cc31a23d6c Revert "dt-bindings: serial: 8250: Add Airoha compatibles"
41f6c94c3fb4 ARM: dts: omap4-panda-a4: Add missing model and compatible properties
464c5f08f7cf dt-bindings: omap: Add TI Pandaboard A4 variant
66677d9f9b16 ARM: dts: ti/omap: omap4-serial: fix interrupts syntax
a6f47d7ebfcc ARM: dts: ti: omap: Align GPIO hog name with bindings
ffdbb206b0a5 arm64: dts: exynos8895-dreamlte: enable support for the touchscreen
21356aba4c79 arm64: dts: exynos8895-dreamlte: enable support for microSD storage
4b146b3f86ce arm64: dts: exynos8895: add a node for mmc
6a0044cd3e17 arm64: dts: exynos8895: define all usi nodes
2d75cfaed428 arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1
9649031bcf98 Merge branch 'for-v6.15/samsung-soc-dt-bindings' into next/dt64
5a27c5397796 arm64: dts: exynos990: Rename and sort PMU nodes
fad948b46dc1 arm64: dts: exynos990: Add CMU_PERIS and MCT nodes
f51ef9e1e5ee Merge branch 'for-v6.15/samsung-clk-dt-bindings' into next/dt64
a517cff67d7a dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi
0f0ca5993559 arm64: dts: mediatek: add display support for mt8365-evk
08a19a12abe1 arm64: dts: mediatek: add display blocks support for the MT8365 SoC
cbbc4673a9d2 arm64: dts: mediatek: mt8173: Fix some node names
5b7068d50a96 arm64: dts: mediatek: mt8173: Fix disp-pwm compatible string
3bc44bb385f8 arm64: dts: mediatek: mt8173-elm: Drop pmic's #address-cells and #size-cells
e8d00ab25c72 arm64: dts: airoha: en7581: Add default partition table for EVB board
d8075291fd7f arm64: dts: airoha: en7581: Add SNAND node
63cd70f67e52 arm64: dts: airoha: en7581: Add Clock Controller node
1e23fdb8aebc ASoC: dt-bindings: atmel,at91-ssc: Convert to YAML format
f092663478cd dt-bindings: pwm: sophgo: add PWM controller for SG2042
1f3f3de0aec6 dt-bindings: eeprom: at24: Add compatible for Giantec GT24P128E
4fba896db2e6 dt-bindings: eeprom: at24: Add compatible for Puya P24C64F
6392d4e28d8d dt-bindings: gpio: ast2400-gpio: Add hogs parsing
138b4d48b94a dt-bindings: net: faraday,ftgmac100: Add phys mode
b570187febfc riscv: dts: microchip: update pcie reg properties to new format
42dcb803b930 ASoC: dt-bindings: Add bindings for WCD934x DAIs
09c3b9df3660 dt-bindings: serial: pl011: Add optional power-domains property
4f0c7d1b5ac2 dt-bindings: serial: 8250: Add Airoha compatibles
ee81474fbc7b dt-bindings: serial: Add a new compatible string for UMS9632
9b704b0c3665 dt-bindings: clock: exynos990: Add CMU_PERIS block
a9c4ff6507a2 arm64: dts: exynos: gs101-raven: add new board file
a7bb8998ddf1 arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi
da0ca70f88e6 arm64: dts: exynos: gs101-oriole: configure simple-framebuffer
dac1e08cdece dt-bindings: arm: google: add gs101-raven
080186bec3c2 arm64: dts: exynos: gs101: disable pinctrl_gsacore node
7c74bfc98c0c ARM: zynq: Do not define address/size-cells for nand-controller
ff5e3b12865d dt-bindings: iio: accel: mc3230: document mc3510c
4fc3fd99ee16 dt-bindings: iio: Correct indentation and style in DTS example
3af3fc397fdf dt-bindings: xilinx: Remove desciption for 16550 uart
a4e34a5b5e49 dt-bindings: xilinx: Remove description for SystemACE
7f8cc3643d7a dt-bindings: xilinx: Remove uartlite from xilinx.txt
666456d4cf96 arm64: zynqmp: add clock-output-names property in clock nodes
8a33cbb41574 ARM: zynq: Remove ethernet0 alias from Microzed
8dfe6851b546 ARM: zynq: Add sdhci to alias node
9ddc09b7b0df ARM: zynq: Enable QSPIs on platforms
6d73675978fe ARM: zynq: Fix fpga region DT nodes name
6c76353caff0 ARM: zynq: Rename i2c?-gpio to i2c?-gpio-grp
15fafeb17cb9 ARM: zynq: Define rtc alias on zc702/zc706
831329e67d45 ARM: zynq: Point via nvmem0 alias to eeprom on zc702/zc706
a4f4075bb7d0 ARM: zynq: Define u-boot bootscrip addr via DT
7f8aedee7529 ARM: zynq: Wire smcc with nand/nor memories on zc770 platform
8bcb31d8083c ARM: zynq: Mark boot-phase-specific device nodes
ef23211239f5 ARM: zynq: DT: List OCM memory for all platforms
85f3e03e1434 ARM: zynq: Remove deprecated device_type property
7e6f927d6b95 ARM: zynq: Replace 'io-standard' with 'power-source' property
83abe9885c89 dt-bindings: interrupt-controller: Add risc-v,aplic hart indexes
c05988583566 ARM: dts: stm32: lxa-fairytux2: add Linux Automation GmbH FairyTux 2
f2edad670168 dt-bindings: arm: stm32: add compatible strings for Linux Automation GmbH LXA FairyTux 2
3b3bc35e81ac dt-bindings: soc: renesas: Add RZ/G3E variant SYS binding
cb2e0436ada7 dt-bindings: soc: renesas: Document Yuridenki-Shokai Kakip board
6057199eb478 dt-bindings: vendor-prefixes: Add Yuridenki-Shokai Co. Ltd.
3c4392efd5f9 dt-bindings: soc: renesas: Document more Renesas RZ/V2H SoC variants
c09fc0ef8abe arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
ec750fb661af arm64: dts: rockchip: Describe why is HWRNG disabled in RK356x base dtsi
3aee8aaf8a6c arm64: dts: rockchip: Enable HDMI on armsom-sige7
1660f72aa147 arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C
55073acc624c arm64: dts: rockchip: Add finer-grained PWM states for the fan on Rock 5C
b112f324c2a9 arm64: dts: rockchip: Enable USB OTG for Radxa ROCK Pi E
41123c761619 arm64: dts: rockchip: add support for sound output over HDMI on RK3399 Puma Haikou
edc802632427 ARM: dts: ti: davinci: Align GPIO hog name with bindings
8bdeb1cbd5b4 dt-bindings: hwmon: lm90: Add support for NCT7716, NCT7717 and NCT7718
5502124072e1 dt-bindings: hwmon: ltc2978: add support for ltm4673
eb140dbbba76 arm64: dts: imx8mp-skov-reva: Use hardware signal for SD card VSELECT
63a6c68df7cb dt-bindings: regulator: pca9450: Add properties for handling LDO5
cb0906024c41 dt-bindings: mfd: motorola-cpcap: Document audio-codec interrupts
c0cfd3272eb3 dt-bindings: display: renesas,du: add top-level constraints
dba95e8dd801 dt-bindings: display: renesas,du: narrow interrupts and resets per variants
b1ac75c9a524 dt-bindings: display: rockchip: Add rk3576 hdmi controller

git-subtree-dir: dts/upstream
git-subtree-split: fe2d6c49bb4e11ab4de4d2f9bd9234d1407c4f65
---
 include/dt-bindings/clock/mediatek,mt8188-clk.h    |   2 +-
 include/dt-bindings/clock/mediatek,mtmips-sysc.h   | 130 ++++++
 include/dt-bindings/clock/qcom,dsi-phy-28nm.h      |   9 +
 include/dt-bindings/clock/qcom,gcc-sdm660.h        |   2 +
 include/dt-bindings/clock/qcom,ipq9574-gcc.h       |   1 +
 include/dt-bindings/clock/qcom,ipq9574-nsscc.h     | 152 +++++++
 include/dt-bindings/clock/qcom,rpmcc.h             |   4 +
 include/dt-bindings/clock/rk3188-cru-common.h      |   2 +
 include/dt-bindings/clock/rockchip,rk3528-cru.h    | 453 +++++++++++++++++++++
 include/dt-bindings/clock/rockchip,rk3562-cru.h    | 379 +++++++++++++++++
 include/dt-bindings/clock/rockchip,rk3576-cru.h    |   5 +
 include/dt-bindings/clock/samsung,exynos2200-cmu.h | 431 ++++++++++++++++++++
 include/dt-bindings/clock/samsung,exynos7870-cmu.h | 324 +++++++++++++++
 include/dt-bindings/clock/samsung,exynos990.h      |  21 +
 include/dt-bindings/clock/sun50i-h616-ccu.h        |   4 +
 include/dt-bindings/clock/sun55i-a523-ccu.h        | 189 +++++++++
 include/dt-bindings/clock/sun55i-a523-r-ccu.h      |  37 ++
 include/dt-bindings/clock/xlnx-zynqmp-clk.h        |   7 +
 include/dt-bindings/iio/adc/adi,ad4695.h           |   7 +
 include/dt-bindings/pinctrl/amlogic,pinctrl.h      |  46 +++
 include/dt-bindings/pinctrl/pinctrl-sg2042.h       | 196 +++++++++
 include/dt-bindings/pinctrl/pinctrl-sg2044.h       | 221 ++++++++++
 .../dt-bindings/power/allwinner,sun8i-v853-ppu.h   |  10 +
 include/dt-bindings/power/qcom-rpmpd.h             |   2 +-
 include/dt-bindings/power/thead,th1520-power.h     |  19 +
 include/dt-bindings/reset/imx8mp-reset-audiomix.h  |  13 +
 include/dt-bindings/reset/qcom,ipq9574-nsscc.h     | 134 ++++++
 include/dt-bindings/reset/rockchip,rk3528-cru.h    | 241 +++++++++++
 include/dt-bindings/reset/rockchip,rk3562-cru.h    | 358 ++++++++++++++++
 include/dt-bindings/reset/rockchip,rk3588-cru.h    |  41 +-
 include/dt-bindings/reset/sun50i-h616-ccu.h        |   2 +
 include/dt-bindings/reset/sun55i-a523-ccu.h        |  88 ++++
 include/dt-bindings/reset/sun55i-a523-r-ccu.h      |  25 ++
 include/dt-bindings/soc/samsung,exynos-usi.h       |  17 +-
 include/dt-bindings/sound/qcom,wcd934x.h           |  16 +
 35 files changed, 3581 insertions(+), 7 deletions(-)
 create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h
 create mode 100644 include/dt-bindings/clock/qcom,dsi-phy-28nm.h
 create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
 create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h
 create mode 100644 include/dt-bindings/clock/rockchip,rk3562-cru.h
 create mode 100644 include/dt-bindings/clock/samsung,exynos2200-cmu.h
 create mode 100644 include/dt-bindings/clock/samsung,exynos7870-cmu.h
 create mode 100644 include/dt-bindings/clock/sun55i-a523-ccu.h
 create mode 100644 include/dt-bindings/clock/sun55i-a523-r-ccu.h
 create mode 100644 include/dt-bindings/pinctrl/amlogic,pinctrl.h
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2042.h
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2044.h
 create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
 create mode 100644 include/dt-bindings/power/thead,th1520-power.h
 create mode 100644 include/dt-bindings/reset/imx8mp-reset-audiomix.h
 create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
 create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h
 create mode 100644 include/dt-bindings/reset/rockchip,rk3562-cru.h
 create mode 100644 include/dt-bindings/reset/sun55i-a523-ccu.h
 create mode 100644 include/dt-bindings/reset/sun55i-a523-r-ccu.h
 create mode 100644 include/dt-bindings/sound/qcom,wcd934x.h

(limited to 'include')

diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h
index bd5cd100b79..0e87f61c90f 100644
--- a/include/dt-bindings/clock/mediatek,mt8188-clk.h
+++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h
@@ -721,6 +721,6 @@
 #define CLK_VDO1_DPINTF				58
 #define CLK_VDO1_DISP_MONITOR_DPINTF		59
 #define CLK_VDO1_26M_SLOW			60
-#define CLK_VDO1_NR_CLK				61
+#define CLK_VDO1_DPI1_HDMI			61
 
 #endif /* _DT_BINDINGS_CLK_MT8188_H */
diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
new file mode 100644
index 00000000000..a03335b0e07
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MTMIPS_H
+#define _DT_BINDINGS_CLK_MTMIPS_H
+
+/* Ralink RT-2880 clocks */
+
+#define RT2880_CLK_XTAL		0
+#define RT2880_CLK_CPU		1
+#define RT2880_CLK_BUS		2
+#define RT2880_CLK_TIMER	3
+#define RT2880_CLK_WATCHDOG	4
+#define RT2880_CLK_UART		5
+#define RT2880_CLK_I2C		6
+#define RT2880_CLK_UARTLITE	7
+#define RT2880_CLK_ETHERNET	8
+#define RT2880_CLK_WMAC		9
+
+/* Ralink RT-305X clocks */
+
+#define RT305X_CLK_XTAL		0
+#define RT305X_CLK_CPU		1
+#define RT305X_CLK_BUS		2
+#define RT305X_CLK_TIMER	3
+#define RT305X_CLK_WATCHDOG	4
+#define RT305X_CLK_UART		5
+#define RT305X_CLK_I2C		6
+#define RT305X_CLK_I2S		7
+#define RT305X_CLK_SPI1		8
+#define RT305X_CLK_SPI2		9
+#define RT305X_CLK_UARTLITE	10
+#define RT305X_CLK_ETHERNET	11
+#define RT305X_CLK_WMAC		12
+
+/* Ralink RT-3352 clocks */
+
+#define RT3352_CLK_XTAL		0
+#define RT3352_CLK_CPU		1
+#define RT3352_CLK_PERIPH	2
+#define RT3352_CLK_BUS		3
+#define RT3352_CLK_TIMER	4
+#define RT3352_CLK_WATCHDOG	5
+#define RT3352_CLK_UART		6
+#define RT3352_CLK_I2C		7
+#define RT3352_CLK_I2S		8
+#define RT3352_CLK_SPI1		9
+#define RT3352_CLK_SPI2		10
+#define RT3352_CLK_UARTLITE	11
+#define RT3352_CLK_ETHERNET	12
+#define RT3352_CLK_WMAC		13
+
+/* Ralink RT-3883 clocks */
+
+#define RT3883_CLK_XTAL		0
+#define RT3883_CLK_CPU		1
+#define RT3883_CLK_BUS		2
+#define RT3883_CLK_PERIPH	3
+#define RT3883_CLK_TIMER	4
+#define RT3883_CLK_WATCHDOG	5
+#define RT3883_CLK_UART		6
+#define RT3883_CLK_I2C		7
+#define RT3883_CLK_I2S		8
+#define RT3883_CLK_SPI1		9
+#define RT3883_CLK_SPI2		10
+#define RT3883_CLK_UARTLITE	11
+#define RT3883_CLK_ETHERNET	12
+#define RT3883_CLK_WMAC		13
+
+/* Ralink RT-5350 clocks */
+
+#define RT5350_CLK_XTAL		0
+#define RT5350_CLK_CPU		1
+#define RT5350_CLK_BUS		2
+#define RT5350_CLK_PERIPH	3
+#define RT5350_CLK_TIMER	4
+#define RT5350_CLK_WATCHDOG	5
+#define RT5350_CLK_UART		6
+#define RT5350_CLK_I2C		7
+#define RT5350_CLK_I2S		8
+#define RT5350_CLK_SPI1		9
+#define RT5350_CLK_SPI2		10
+#define RT5350_CLK_UARTLITE	11
+#define RT5350_CLK_ETHERNET	12
+#define RT5350_CLK_WMAC		13
+
+/* Ralink MT-7620 clocks */
+
+#define MT7620_CLK_XTAL		0
+#define MT7620_CLK_PLL		1
+#define MT7620_CLK_CPU		2
+#define MT7620_CLK_PERIPH	3
+#define MT7620_CLK_BUS		4
+#define MT7620_CLK_BBPPLL	5
+#define MT7620_CLK_SDHC		6
+#define MT7620_CLK_TIMER	7
+#define MT7620_CLK_WATCHDOG	8
+#define MT7620_CLK_UART		9
+#define MT7620_CLK_I2C		10
+#define MT7620_CLK_I2S		11
+#define MT7620_CLK_SPI1		12
+#define MT7620_CLK_SPI2		13
+#define MT7620_CLK_UARTLITE	14
+#define MT7620_CLK_MMC		15
+#define MT7620_CLK_WMAC		16
+
+/* Ralink MT-76X8 clocks */
+
+#define MT76X8_CLK_XTAL		0
+#define MT76X8_CLK_CPU		1
+#define MT76X8_CLK_BBPPLL	2
+#define MT76X8_CLK_PCMI2S	3
+#define MT76X8_CLK_PERIPH	4
+#define MT76X8_CLK_BUS		5
+#define MT76X8_CLK_SDHC		6
+#define MT76X8_CLK_TIMER	7
+#define MT76X8_CLK_WATCHDOG	8
+#define MT76X8_CLK_I2C		9
+#define MT76X8_CLK_I2S		10
+#define MT76X8_CLK_SPI1		11
+#define MT76X8_CLK_SPI2		12
+#define MT76X8_CLK_UART0	13
+#define MT76X8_CLK_UART1	14
+#define MT76X8_CLK_UART2	15
+#define MT76X8_CLK_MMC		16
+#define MT76X8_CLK_WMAC		17
+
+#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
diff --git a/include/dt-bindings/clock/qcom,dsi-phy-28nm.h b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h
new file mode 100644
index 00000000000..ab94d58377a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H
+#define _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H
+
+#define DSI_BYTE_PLL_CLK		0
+#define DSI_PIXEL_PLL_CLK		1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
index df8a6f3d367..74c22f67da2 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm660.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -153,5 +153,7 @@
 #define GCC_USB_30_BCR			7
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR	8
 #define GCC_MSS_RESTART			9
+#define GCC_SDCC1_BCR			10
+#define GCC_SDCC2_BCR			11
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index f238aa4794a..0e7c319897f 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -202,4 +202,5 @@
 #define GCC_PCIE1_PIPE_CLK				211
 #define GCC_PCIE2_PIPE_CLK				212
 #define GCC_PCIE3_PIPE_CLK				213
+#define GPLL0_OUT_AUX					214
 #endif
diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
new file mode 100644
index 00000000000..21a16dc0e64
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
+#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
+
+#define NSS_CC_CE_APB_CLK					0
+#define NSS_CC_CE_AXI_CLK					1
+#define NSS_CC_CE_CLK_SRC					2
+#define NSS_CC_CFG_CLK_SRC					3
+#define NSS_CC_CLC_AXI_CLK					4
+#define NSS_CC_CLC_CLK_SRC					5
+#define NSS_CC_CRYPTO_CLK					6
+#define NSS_CC_CRYPTO_CLK_SRC					7
+#define NSS_CC_CRYPTO_PPE_CLK					8
+#define NSS_CC_HAQ_AHB_CLK					9
+#define NSS_CC_HAQ_AXI_CLK					10
+#define NSS_CC_HAQ_CLK_SRC					11
+#define NSS_CC_IMEM_AHB_CLK					12
+#define NSS_CC_IMEM_CLK_SRC					13
+#define NSS_CC_IMEM_QSB_CLK					14
+#define NSS_CC_INT_CFG_CLK_SRC					15
+#define NSS_CC_NSS_CSR_CLK					16
+#define NSS_CC_NSSNOC_CE_APB_CLK				17
+#define NSS_CC_NSSNOC_CE_AXI_CLK				18
+#define NSS_CC_NSSNOC_CLC_AXI_CLK				19
+#define NSS_CC_NSSNOC_CRYPTO_CLK				20
+#define NSS_CC_NSSNOC_HAQ_AHB_CLK				21
+#define NSS_CC_NSSNOC_HAQ_AXI_CLK				22
+#define NSS_CC_NSSNOC_IMEM_AHB_CLK				23
+#define NSS_CC_NSSNOC_IMEM_QSB_CLK				24
+#define NSS_CC_NSSNOC_NSS_CSR_CLK				25
+#define NSS_CC_NSSNOC_PPE_CFG_CLK				26
+#define NSS_CC_NSSNOC_PPE_CLK					27
+#define NSS_CC_NSSNOC_UBI32_AHB0_CLK				28
+#define NSS_CC_NSSNOC_UBI32_AXI0_CLK				29
+#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK			30
+#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK			31
+#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK				32
+#define NSS_CC_PORT1_MAC_CLK					33
+#define NSS_CC_PORT1_RX_CLK					34
+#define NSS_CC_PORT1_RX_CLK_SRC					35
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC				36
+#define NSS_CC_PORT1_TX_CLK					37
+#define NSS_CC_PORT1_TX_CLK_SRC					38
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC				39
+#define NSS_CC_PORT2_MAC_CLK					40
+#define NSS_CC_PORT2_RX_CLK					41
+#define NSS_CC_PORT2_RX_CLK_SRC					42
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC				43
+#define NSS_CC_PORT2_TX_CLK					44
+#define NSS_CC_PORT2_TX_CLK_SRC					45
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC				46
+#define NSS_CC_PORT3_MAC_CLK					47
+#define NSS_CC_PORT3_RX_CLK					48
+#define NSS_CC_PORT3_RX_CLK_SRC					49
+#define NSS_CC_PORT3_RX_DIV_CLK_SRC				50
+#define NSS_CC_PORT3_TX_CLK					51
+#define NSS_CC_PORT3_TX_CLK_SRC					52
+#define NSS_CC_PORT3_TX_DIV_CLK_SRC				53
+#define NSS_CC_PORT4_MAC_CLK					54
+#define NSS_CC_PORT4_RX_CLK					55
+#define NSS_CC_PORT4_RX_CLK_SRC					56
+#define NSS_CC_PORT4_RX_DIV_CLK_SRC				57
+#define NSS_CC_PORT4_TX_CLK					58
+#define NSS_CC_PORT4_TX_CLK_SRC					59
+#define NSS_CC_PORT4_TX_DIV_CLK_SRC				60
+#define NSS_CC_PORT5_MAC_CLK					61
+#define NSS_CC_PORT5_RX_CLK					62
+#define NSS_CC_PORT5_RX_CLK_SRC					63
+#define NSS_CC_PORT5_RX_DIV_CLK_SRC				64
+#define NSS_CC_PORT5_TX_CLK					65
+#define NSS_CC_PORT5_TX_CLK_SRC					66
+#define NSS_CC_PORT5_TX_DIV_CLK_SRC				67
+#define NSS_CC_PORT6_MAC_CLK					68
+#define NSS_CC_PORT6_RX_CLK					69
+#define NSS_CC_PORT6_RX_CLK_SRC					70
+#define NSS_CC_PORT6_RX_DIV_CLK_SRC				71
+#define NSS_CC_PORT6_TX_CLK					72
+#define NSS_CC_PORT6_TX_CLK_SRC					73
+#define NSS_CC_PORT6_TX_DIV_CLK_SRC				74
+#define NSS_CC_PPE_CLK_SRC					75
+#define NSS_CC_PPE_EDMA_CFG_CLK					76
+#define NSS_CC_PPE_EDMA_CLK					77
+#define NSS_CC_PPE_SWITCH_BTQ_CLK				78
+#define NSS_CC_PPE_SWITCH_CFG_CLK				79
+#define NSS_CC_PPE_SWITCH_CLK					80
+#define NSS_CC_PPE_SWITCH_IPE_CLK				81
+#define NSS_CC_UBI0_CLK_SRC					82
+#define NSS_CC_UBI0_DIV_CLK_SRC					83
+#define NSS_CC_UBI1_CLK_SRC					84
+#define NSS_CC_UBI1_DIV_CLK_SRC					85
+#define NSS_CC_UBI2_CLK_SRC					86
+#define NSS_CC_UBI2_DIV_CLK_SRC					87
+#define NSS_CC_UBI32_AHB0_CLK					88
+#define NSS_CC_UBI32_AHB1_CLK					89
+#define NSS_CC_UBI32_AHB2_CLK					90
+#define NSS_CC_UBI32_AHB3_CLK					91
+#define NSS_CC_UBI32_AXI0_CLK					92
+#define NSS_CC_UBI32_AXI1_CLK					93
+#define NSS_CC_UBI32_AXI2_CLK					94
+#define NSS_CC_UBI32_AXI3_CLK					95
+#define NSS_CC_UBI32_CORE0_CLK					96
+#define NSS_CC_UBI32_CORE1_CLK					97
+#define NSS_CC_UBI32_CORE2_CLK					98
+#define NSS_CC_UBI32_CORE3_CLK					99
+#define NSS_CC_UBI32_INTR0_AHB_CLK				100
+#define NSS_CC_UBI32_INTR1_AHB_CLK				101
+#define NSS_CC_UBI32_INTR2_AHB_CLK				102
+#define NSS_CC_UBI32_INTR3_AHB_CLK				103
+#define NSS_CC_UBI32_NC_AXI0_CLK				104
+#define NSS_CC_UBI32_NC_AXI1_CLK				105
+#define NSS_CC_UBI32_NC_AXI2_CLK				106
+#define NSS_CC_UBI32_NC_AXI3_CLK				107
+#define NSS_CC_UBI32_UTCM0_CLK					108
+#define NSS_CC_UBI32_UTCM1_CLK					109
+#define NSS_CC_UBI32_UTCM2_CLK					110
+#define NSS_CC_UBI32_UTCM3_CLK					111
+#define NSS_CC_UBI3_CLK_SRC					112
+#define NSS_CC_UBI3_DIV_CLK_SRC					113
+#define NSS_CC_UBI_AXI_CLK_SRC					114
+#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC				115
+#define NSS_CC_UNIPHY_PORT1_RX_CLK				116
+#define NSS_CC_UNIPHY_PORT1_TX_CLK				117
+#define NSS_CC_UNIPHY_PORT2_RX_CLK				118
+#define NSS_CC_UNIPHY_PORT2_TX_CLK				119
+#define NSS_CC_UNIPHY_PORT3_RX_CLK				120
+#define NSS_CC_UNIPHY_PORT3_TX_CLK				121
+#define NSS_CC_UNIPHY_PORT4_RX_CLK				122
+#define NSS_CC_UNIPHY_PORT4_TX_CLK				123
+#define NSS_CC_UNIPHY_PORT5_RX_CLK				124
+#define NSS_CC_UNIPHY_PORT5_TX_CLK				125
+#define NSS_CC_UNIPHY_PORT6_RX_CLK				126
+#define NSS_CC_UNIPHY_PORT6_TX_CLK				127
+#define NSS_CC_XGMAC0_PTP_REF_CLK				128
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC			129
+#define NSS_CC_XGMAC1_PTP_REF_CLK				130
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC			131
+#define NSS_CC_XGMAC2_PTP_REF_CLK				132
+#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC			133
+#define NSS_CC_XGMAC3_PTP_REF_CLK				134
+#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC			135
+#define NSS_CC_XGMAC4_PTP_REF_CLK				136
+#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC			137
+#define NSS_CC_XGMAC5_PTP_REF_CLK				138
+#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC			139
+#define UBI32_PLL						140
+#define UBI32_PLL_MAIN						141
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 46309c9953b..1477a75e7f6 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -170,5 +170,9 @@
 #define RPM_SMD_BIMC_FREQ_LOG			124
 #define RPM_SMD_LN_BB_CLK_PIN			125
 #define RPM_SMD_LN_BB_A_CLK_PIN			126
+#define RPM_SMD_BB_CLK3				127
+#define RPM_SMD_BB_CLK3_A			128
+#define RPM_SMD_BB_CLK3_PIN			129
+#define RPM_SMD_BB_CLK3_A_PIN			130
 
 #endif
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index 01e14ab252a..dd988cc9d58 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -103,6 +103,8 @@
 #define PCLK_PERI		351
 #define PCLK_DDRUPCTL		352
 #define PCLK_PUBL		353
+#define PCLK_CIF0		354
+#define PCLK_CIF1		355
 
 /* hclk gates */
 #define HCLK_SDMMC		448
diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h
new file mode 100644
index 00000000000..55a448f5ed6
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+
+/* cru-clocks indices */
+#define PLL_APLL			0
+#define PLL_CPLL			1
+#define PLL_GPLL			2
+#define PLL_PPLL			3
+#define PLL_DPLL			4
+#define ARMCLK				5
+#define XIN_OSC0_HALF			6
+#define CLK_MATRIX_50M_SRC		7
+#define CLK_MATRIX_100M_SRC		8
+#define CLK_MATRIX_150M_SRC		9
+#define CLK_MATRIX_200M_SRC		10
+#define CLK_MATRIX_250M_SRC		11
+#define CLK_MATRIX_300M_SRC		12
+#define CLK_MATRIX_339M_SRC		13
+#define CLK_MATRIX_400M_SRC		14
+#define CLK_MATRIX_500M_SRC		15
+#define CLK_MATRIX_600M_SRC		16
+#define CLK_UART0_SRC			17
+#define CLK_UART0_FRAC			18
+#define SCLK_UART0			19
+#define CLK_UART1_SRC			20
+#define CLK_UART1_FRAC			21
+#define SCLK_UART1			22
+#define CLK_UART2_SRC			23
+#define CLK_UART2_FRAC			24
+#define SCLK_UART2			25
+#define CLK_UART3_SRC			26
+#define CLK_UART3_FRAC			27
+#define SCLK_UART3			28
+#define CLK_UART4_SRC			29
+#define CLK_UART4_FRAC			30
+#define SCLK_UART4			31
+#define CLK_UART5_SRC			32
+#define CLK_UART5_FRAC			33
+#define SCLK_UART5			34
+#define CLK_UART6_SRC			35
+#define CLK_UART6_FRAC			36
+#define SCLK_UART6			37
+#define CLK_UART7_SRC			38
+#define CLK_UART7_FRAC			39
+#define SCLK_UART7			40
+#define CLK_I2S0_2CH_SRC		41
+#define CLK_I2S0_2CH_FRAC		42
+#define MCLK_I2S0_2CH_SAI_SRC		43
+#define CLK_I2S3_8CH_SRC		44
+#define CLK_I2S3_8CH_FRAC		45
+#define MCLK_I2S3_8CH_SAI_SRC		46
+#define CLK_I2S1_8CH_SRC		47
+#define CLK_I2S1_8CH_FRAC		48
+#define MCLK_I2S1_8CH_SAI_SRC		49
+#define CLK_I2S2_2CH_SRC		50
+#define CLK_I2S2_2CH_FRAC		51
+#define MCLK_I2S2_2CH_SAI_SRC		52
+#define CLK_SPDIF_SRC			53
+#define CLK_SPDIF_FRAC			54
+#define MCLK_SPDIF_SRC			55
+#define DCLK_VOP_SRC0			56
+#define DCLK_VOP_SRC1			57
+#define CLK_HSM				58
+#define CLK_CORE_SRC_ACS		59
+#define CLK_CORE_SRC_PVTMUX		60
+#define CLK_CORE_SRC			61
+#define CLK_CORE			62
+#define ACLK_M_CORE_BIU			63
+#define CLK_CORE_PVTPLL_SRC		64
+#define PCLK_DBG			65
+#define SWCLKTCK			66
+#define CLK_SCANHS_CORE			67
+#define CLK_SCANHS_ACLKM_CORE		68
+#define CLK_SCANHS_PCLK_DBG		69
+#define CLK_SCANHS_PCLK_CPU_BIU		70
+#define PCLK_CPU_ROOT			71
+#define PCLK_CORE_GRF			72
+#define PCLK_DAPLITE_BIU		73
+#define PCLK_CPU_BIU			74
+#define CLK_REF_PVTPLL_CORE		75
+#define ACLK_BUS_VOPGL_ROOT		76
+#define ACLK_BUS_VOPGL_BIU		77
+#define ACLK_BUS_H_ROOT			78
+#define ACLK_BUS_H_BIU			79
+#define ACLK_BUS_ROOT			80
+#define HCLK_BUS_ROOT			81
+#define PCLK_BUS_ROOT			82
+#define ACLK_BUS_M_ROOT			83
+#define ACLK_SYSMEM_BIU			84
+#define CLK_TIMER_ROOT			85
+#define ACLK_BUS_BIU			86
+#define HCLK_BUS_BIU			87
+#define PCLK_BUS_BIU			88
+#define PCLK_DFT2APB			89
+#define PCLK_BUS_GRF			90
+#define ACLK_BUS_M_BIU			91
+#define ACLK_GIC			92
+#define ACLK_SPINLOCK			93
+#define ACLK_DMAC			94
+#define PCLK_TIMER			95
+#define CLK_TIMER0			96
+#define CLK_TIMER1			97
+#define CLK_TIMER2			98
+#define CLK_TIMER3			99
+#define CLK_TIMER4			100
+#define CLK_TIMER5			101
+#define PCLK_JDBCK_DAP			102
+#define CLK_JDBCK_DAP			103
+#define PCLK_WDT_NS			104
+#define TCLK_WDT_NS			105
+#define HCLK_TRNG_NS			106
+#define PCLK_UART0			107
+#define PCLK_DMA2DDR			108
+#define ACLK_DMA2DDR			109
+#define PCLK_PWM0			110
+#define CLK_PWM0			111
+#define CLK_CAPTURE_PWM0		112
+#define PCLK_PWM1			113
+#define CLK_PWM1			114
+#define CLK_CAPTURE_PWM1		115
+#define PCLK_SCR			116
+#define ACLK_DCF			117
+#define PCLK_INTMUX			118
+#define CLK_PPLL_I			119
+#define CLK_PPLL_MUX			120
+#define CLK_PPLL_100M_MATRIX		121
+#define CLK_PPLL_50M_MATRIX		122
+#define CLK_REF_PCIE_INNER_PHY		123
+#define CLK_REF_PCIE_100M_PHY		124
+#define ACLK_VPU_L_ROOT			125
+#define CLK_GMAC1_VPU_25M		126
+#define CLK_PPLL_125M_MATRIX		127
+#define ACLK_VPU_ROOT			128
+#define HCLK_VPU_ROOT			129
+#define PCLK_VPU_ROOT			130
+#define ACLK_VPU_BIU			131
+#define HCLK_VPU_BIU			132
+#define PCLK_VPU_BIU			133
+#define ACLK_VPU			134
+#define HCLK_VPU			135
+#define PCLK_CRU_PCIE			136
+#define PCLK_VPU_GRF			137
+#define HCLK_SFC			138
+#define SCLK_SFC			139
+#define CCLK_SRC_EMMC			140
+#define HCLK_EMMC			141
+#define ACLK_EMMC			142
+#define BCLK_EMMC			143
+#define TCLK_EMMC			144
+#define PCLK_GPIO1			145
+#define DBCLK_GPIO1			146
+#define ACLK_VPU_L_BIU			147
+#define PCLK_VPU_IOC			148
+#define HCLK_SAI_I2S0			149
+#define MCLK_SAI_I2S0			150
+#define HCLK_SAI_I2S2			151
+#define MCLK_SAI_I2S2			152
+#define PCLK_ACODEC			153
+#define MCLK_ACODEC_TX			154
+#define PCLK_GPIO3			155
+#define DBCLK_GPIO3			156
+#define PCLK_SPI1			157
+#define CLK_SPI1			158
+#define SCLK_IN_SPI1			159
+#define PCLK_UART2			160
+#define PCLK_UART5			161
+#define PCLK_UART6			162
+#define PCLK_UART7			163
+#define PCLK_I2C3			164
+#define CLK_I2C3			165
+#define PCLK_I2C5			166
+#define CLK_I2C5			167
+#define PCLK_I2C6			168
+#define CLK_I2C6			169
+#define ACLK_MAC_VPU			170
+#define PCLK_MAC_VPU			171
+#define CLK_GMAC1_RMII_VPU		172
+#define CLK_GMAC1_SRC_VPU		173
+#define PCLK_PCIE			174
+#define CLK_PCIE_AUX			175
+#define ACLK_PCIE			176
+#define HCLK_PCIE_SLV			177
+#define HCLK_PCIE_DBI			178
+#define PCLK_PCIE_PHY			179
+#define PCLK_PIPE_GRF			180
+#define CLK_PIPE_USB3OTG_COMBO		181
+#define CLK_UTMI_USB3OTG		182
+#define CLK_PCIE_PIPE_PHY		183
+#define CCLK_SRC_SDIO0			184
+#define HCLK_SDIO0			185
+#define CCLK_SRC_SDIO1			186
+#define HCLK_SDIO1			187
+#define CLK_TS_0			188
+#define CLK_TS_1			189
+#define PCLK_CAN2			190
+#define CLK_CAN2			191
+#define PCLK_CAN3			192
+#define CLK_CAN3			193
+#define PCLK_SARADC			194
+#define CLK_SARADC			195
+#define PCLK_TSADC			196
+#define CLK_TSADC			197
+#define CLK_TSADC_TSEN			198
+#define ACLK_USB3OTG			199
+#define CLK_REF_USB3OTG			200
+#define CLK_SUSPEND_USB3OTG		201
+#define ACLK_GPU_ROOT			202
+#define PCLK_GPU_ROOT			203
+#define ACLK_GPU_BIU			204
+#define PCLK_GPU_BIU			205
+#define ACLK_GPU			206
+#define CLK_GPU_PVTPLL_SRC		207
+#define ACLK_GPU_MALI			208
+#define HCLK_RKVENC_ROOT		209
+#define ACLK_RKVENC_ROOT		210
+#define PCLK_RKVENC_ROOT		211
+#define HCLK_RKVENC_BIU			212
+#define ACLK_RKVENC_BIU			213
+#define PCLK_RKVENC_BIU			214
+#define HCLK_RKVENC			215
+#define ACLK_RKVENC			216
+#define CLK_CORE_RKVENC			217
+#define HCLK_SAI_I2S1			218
+#define MCLK_SAI_I2S1			219
+#define PCLK_I2C1			220
+#define CLK_I2C1			221
+#define PCLK_I2C0			222
+#define CLK_I2C0			223
+#define CLK_UART_JTAG			224
+#define PCLK_SPI0			225
+#define CLK_SPI0			226
+#define SCLK_IN_SPI0			227
+#define PCLK_GPIO4			228
+#define DBCLK_GPIO4			229
+#define PCLK_RKVENC_IOC			230
+#define HCLK_SPDIF			231
+#define MCLK_SPDIF			232
+#define HCLK_PDM			233
+#define MCLK_PDM			234
+#define PCLK_UART1			235
+#define PCLK_UART3			236
+#define PCLK_RKVENC_GRF			237
+#define PCLK_CAN0			238
+#define CLK_CAN0			239
+#define PCLK_CAN1			240
+#define CLK_CAN1			241
+#define ACLK_VO_ROOT			242
+#define HCLK_VO_ROOT			243
+#define PCLK_VO_ROOT			244
+#define ACLK_VO_BIU			245
+#define HCLK_VO_BIU			246
+#define PCLK_VO_BIU			247
+#define HCLK_RGA2E			248
+#define ACLK_RGA2E			249
+#define CLK_CORE_RGA2E			250
+#define HCLK_VDPP			251
+#define ACLK_VDPP			252
+#define CLK_CORE_VDPP			253
+#define PCLK_VO_GRF			254
+#define PCLK_CRU			255
+#define ACLK_VOP_ROOT			256
+#define ACLK_VOP_BIU			257
+#define HCLK_VOP			258
+#define DCLK_VOP0			259
+#define DCLK_VOP1			260
+#define ACLK_VOP			261
+#define PCLK_HDMI			262
+#define CLK_SFR_HDMI			263
+#define CLK_CEC_HDMI			264
+#define CLK_SPDIF_HDMI			265
+#define CLK_HDMIPHY_TMDSSRC		266
+#define CLK_HDMIPHY_PREP		267
+#define PCLK_HDMIPHY			268
+#define HCLK_HDCP_KEY			269
+#define ACLK_HDCP			270
+#define HCLK_HDCP			271
+#define PCLK_HDCP			272
+#define HCLK_CVBS			273
+#define DCLK_CVBS			274
+#define DCLK_4X_CVBS			275
+#define ACLK_JPEG_DECODER		276
+#define HCLK_JPEG_DECODER		277
+#define ACLK_VO_L_ROOT			278
+#define ACLK_VO_L_BIU			279
+#define ACLK_MAC_VO			280
+#define PCLK_MAC_VO			281
+#define CLK_GMAC0_SRC			282
+#define CLK_GMAC0_RMII_50M		283
+#define CLK_GMAC0_TX			284
+#define CLK_GMAC0_RX			285
+#define ACLK_JPEG_ROOT			286
+#define ACLK_JPEG_BIU			287
+#define HCLK_SAI_I2S3			288
+#define MCLK_SAI_I2S3			289
+#define CLK_MACPHY			290
+#define PCLK_VCDCPHY			291
+#define PCLK_GPIO2			292
+#define DBCLK_GPIO2			293
+#define PCLK_VO_IOC			294
+#define CCLK_SRC_SDMMC0			295
+#define HCLK_SDMMC0			296
+#define PCLK_OTPC_NS			297
+#define CLK_SBPI_OTPC_NS		298
+#define CLK_USER_OTPC_NS		299
+#define CLK_HDMIHDP0			300
+#define HCLK_USBHOST			301
+#define HCLK_USBHOST_ARB		302
+#define CLK_USBHOST_OHCI		303
+#define CLK_USBHOST_UTMI		304
+#define PCLK_UART4			305
+#define PCLK_I2C4			306
+#define CLK_I2C4			307
+#define PCLK_I2C7			308
+#define CLK_I2C7			309
+#define PCLK_USBPHY			310
+#define CLK_REF_USBPHY			311
+#define HCLK_RKVDEC_ROOT		312
+#define ACLK_RKVDEC_ROOT_NDFT		313
+#define PCLK_DDRPHY_CRU			314
+#define HCLK_RKVDEC_BIU			315
+#define ACLK_RKVDEC_BIU			316
+#define ACLK_RKVDEC			317
+#define HCLK_RKVDEC			318
+#define CLK_HEVC_CA_RKVDEC		319
+#define ACLK_RKVDEC_PVTMUX_ROOT		320
+#define CLK_RKVDEC_PVTPLL_SRC		321
+#define PCLK_DDR_ROOT			322
+#define PCLK_DDR_BIU			323
+#define PCLK_DDRC			324
+#define PCLK_DDRMON			325
+#define CLK_TIMER_DDRMON		326
+#define PCLK_MSCH_BIU			327
+#define PCLK_DDR_GRF			328
+#define PCLK_DDR_HWLP			329
+#define PCLK_DDRPHY			330
+#define CLK_MSCH_BIU			331
+#define ACLK_DDR_UPCTL			332
+#define CLK_DDR_UPCTL			333
+#define CLK_DDRMON			334
+#define ACLK_DDR_SCRAMBLE		335
+#define ACLK_SPLIT			336
+#define CLK_DDRC_SRC			337
+#define CLK_DDR_PHY			338
+#define PCLK_OTPC_S			339
+#define CLK_SBPI_OTPC_S			340
+#define CLK_USER_OTPC_S			341
+#define PCLK_KEYREADER			342
+#define PCLK_BUS_SGRF			343
+#define PCLK_STIMER			344
+#define CLK_STIMER0			345
+#define CLK_STIMER1			346
+#define PCLK_WDT_S			347
+#define TCLK_WDT_S			348
+#define HCLK_TRNG_S			349
+#define HCLK_BOOTROM			350
+#define PCLK_DCF			351
+#define ACLK_SYSMEM			352
+#define HCLK_TSP			353
+#define ACLK_TSP			354
+#define CLK_CORE_TSP			355
+#define CLK_OTPC_ARB			356
+#define PCLK_OTP_MASK			357
+#define CLK_PMC_OTP			358
+#define PCLK_PMU_ROOT			359
+#define HCLK_PMU_ROOT			360
+#define PCLK_I2C2			361
+#define CLK_I2C2			362
+#define HCLK_PMU_BIU			363
+#define PCLK_PMU_BIU			364
+#define FCLK_MCU			365
+#define RTC_CLK_MCU			366
+#define PCLK_OSCCHK			367
+#define CLK_PMU_MCU_JTAG		368
+#define PCLK_PMU			369
+#define PCLK_GPIO0			370
+#define DBCLK_GPIO0			371
+#define XIN_OSC0_DIV			372
+#define CLK_DEEPSLOW			373
+#define CLK_DDR_FAIL_SAFE		374
+#define PCLK_PMU_HP_TIMER		375
+#define CLK_PMU_HP_TIMER		376
+#define CLK_PMU_32K_HP_TIMER		377
+#define PCLK_PMU_IOC			378
+#define PCLK_PMU_CRU			379
+#define PCLK_PMU_GRF			380
+#define PCLK_PMU_WDT			381
+#define TCLK_PMU_WDT			382
+#define PCLK_PMU_MAILBOX		383
+#define PCLK_SCRKEYGEN			384
+#define CLK_SCRKEYGEN			385
+#define CLK_PVTM_OSCCHK			386
+#define CLK_REFOUT			387
+#define CLK_PVTM_PMU			388
+#define PCLK_PVTM_PMU			389
+#define PCLK_PMU_SGRF			390
+#define HCLK_PMU_SRAM			391
+#define CLK_UART0			392
+#define CLK_UART1			393
+#define CLK_UART2			394
+#define CLK_UART3			395
+#define CLK_UART4			396
+#define CLK_UART5			397
+#define CLK_UART6			398
+#define CLK_UART7			399
+#define MCLK_I2S0_2CH_SAI_SRC_PRE	400
+#define MCLK_I2S1_8CH_SAI_SRC_PRE	401
+#define MCLK_I2S2_2CH_SAI_SRC_PRE	402
+#define MCLK_I2S3_8CH_SAI_SRC_PRE	403
+#define MCLK_SDPDIF_SRC_PRE		404
+
+/* scmi-clocks indices */
+#define SCMI_PCLK_KEYREADER		0
+#define SCMI_HCLK_KLAD			1
+#define SCMI_PCLK_KLAD			2
+#define SCMI_HCLK_TRNG_S		3
+#define SCMI_HCLK_CRYPTO_S		4
+#define SCMI_PCLK_WDT_S			5
+#define SCMI_TCLK_WDT_S			6
+#define SCMI_PCLK_STIMER		7
+#define SCMI_CLK_STIMER0		8
+#define SCMI_CLK_STIMER1		9
+#define SCMI_PCLK_OTP_MASK		10
+#define SCMI_PCLK_OTPC_S		11
+#define SCMI_CLK_SBPI_OTPC_S		12
+#define SCMI_CLK_USER_OTPC_S		13
+#define SCMI_CLK_PMC_OTP		14
+#define SCMI_CLK_OTPC_ARB		15
+#define SCMI_CLK_CORE_TSP		16
+#define SCMI_ACLK_TSP			17
+#define SCMI_HCLK_TSP			18
+#define SCMI_PCLK_DCF			19
+#define SCMI_CLK_DDR			20
+#define SCMI_CLK_CPU			21
+#define SCMI_CLK_GPU			22
+#define SCMI_CORE_CRYPTO		23
+#define SCMI_ACLK_CRYPTO		24
+#define SCMI_PKA_CRYPTO			25
+#define SCMI_HCLK_CRYPTO		26
+#define SCMI_CORE_CRYPTO_S		27
+#define SCMI_ACLK_CRYPTO_S		28
+#define SCMI_PKA_CRYPTO_S		29
+#define SCMI_CORE_KLAD			30
+#define SCMI_ACLK_KLAD			31
+#define SCMI_HCLK_TRNG			32
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h
new file mode 100644
index 00000000000..a5b0b153209
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h
@@ -0,0 +1,379 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_DMPLL0			0
+#define PLL_APLL			1
+#define PLL_GPLL			2
+#define PLL_VPLL			3
+#define PLL_HPLL			4
+#define PLL_CPLL			5
+#define PLL_DPLL			6
+#define PLL_DMPLL1			7
+
+/* cru clocks */
+#define ARMCLK				8
+#define CLK_GPU				9
+#define ACLK_RKNN			10
+#define CLK_DDR				11
+#define CLK_MATRIX_50M_SRC		12
+#define CLK_MATRIX_100M_SRC		13
+#define CLK_MATRIX_125M_SRC		14
+#define CLK_MATRIX_200M_SRC		15
+#define CLK_MATRIX_300M_SRC		16
+#define ACLK_TOP			17
+#define ACLK_TOP_VIO			18
+#define CLK_CAM0_OUT2IO			19
+#define CLK_CAM1_OUT2IO			20
+#define CLK_CAM2_OUT2IO			21
+#define CLK_CAM3_OUT2IO			22
+#define ACLK_BUS			23
+#define HCLK_BUS			24
+#define PCLK_BUS			25
+#define PCLK_I2C1			26
+#define PCLK_I2C2			27
+#define PCLK_I2C3			28
+#define PCLK_I2C4			29
+#define PCLK_I2C5			30
+#define CLK_I2C				31
+#define CLK_I2C1			32
+#define CLK_I2C2			33
+#define CLK_I2C3			34
+#define CLK_I2C4			35
+#define CLK_I2C5			36
+#define DCLK_BUS_GPIO			37
+#define DCLK_BUS_GPIO3			38
+#define DCLK_BUS_GPIO4			39
+#define PCLK_TIMER			40
+#define CLK_TIMER0			41
+#define CLK_TIMER1			42
+#define CLK_TIMER2			43
+#define CLK_TIMER3			44
+#define CLK_TIMER4			45
+#define CLK_TIMER5			46
+#define PCLK_STIMER			47
+#define CLK_STIMER0			48
+#define CLK_STIMER1			49
+#define PCLK_WDTNS			50
+#define CLK_WDTNS			51
+#define PCLK_GRF			52
+#define PCLK_SGRF			53
+#define PCLK_MAILBOX			54
+#define PCLK_INTC			55
+#define ACLK_BUS_GIC400			56
+#define ACLK_BUS_SPINLOCK		57
+#define ACLK_DCF			58
+#define PCLK_DCF			59
+#define FCLK_BUS_CM0_CORE		60
+#define CLK_BUS_CM0_RTC			61
+#define HCLK_ICACHE			62
+#define HCLK_DCACHE			63
+#define PCLK_TSADC			64
+#define CLK_TSADC			65
+#define CLK_TSADC_TSEN			66
+#define PCLK_DFT2APB			67
+#define CLK_SARADC_VCCIO156		68
+#define PCLK_GMAC			69
+#define ACLK_GMAC			70
+#define CLK_GMAC_125M_CRU_I		71
+#define CLK_GMAC_50M_CRU_I		72
+#define CLK_GMAC_50M_O			73
+#define CLK_GMAC_ETH_OUT2IO		74
+#define PCLK_APB2ASB_VCCIO156		75
+#define PCLK_TO_VCCIO156		76
+#define PCLK_DSIPHY			77
+#define PCLK_DSITX			78
+#define PCLK_CPU_EMA_DET		79
+#define PCLK_HASH			80
+#define PCLK_TOPCRU			81
+#define PCLK_ASB2APB_VCCIO156		82
+#define PCLK_IOC_VCCIO156		83
+#define PCLK_GPIO3_VCCIO156		84
+#define PCLK_GPIO4_VCCIO156		85
+#define PCLK_SARADC_VCCIO156		86
+#define PCLK_MAC100			87
+#define ACLK_MAC100			89
+#define CLK_MAC100_50M_MATRIX		90
+#define HCLK_CORE			91
+#define PCLK_DDR			92
+#define CLK_MSCH_BRG_BIU		93
+#define PCLK_DDR_HWLP			94
+#define PCLK_DDR_UPCTL			95
+#define PCLK_DDR_PHY			96
+#define PCLK_DDR_DFICTL			97
+#define PCLK_DDR_DMA2DDR		98
+#define PCLK_DDR_MON			99
+#define TMCLK_DDR_MON			100
+#define PCLK_DDR_GRF			101
+#define PCLK_DDR_CRU			102
+#define PCLK_SUBDDR_CRU			103
+#define CLK_GPU_PRE			104
+#define ACLK_GPU_PRE			105
+#define CLK_GPU_BRG			107
+#define CLK_NPU_PRE			108
+#define HCLK_NPU_PRE			109
+#define HCLK_RKNN			111
+#define ACLK_PERI			112
+#define HCLK_PERI			113
+#define PCLK_PERI			114
+#define PCLK_PERICRU			115
+#define HCLK_SAI0			116
+#define CLK_SAI0_SRC			117
+#define CLK_SAI0_FRAC			118
+#define CLK_SAI0			119
+#define MCLK_SAI0			120
+#define MCLK_SAI0_OUT2IO		121
+#define HCLK_SAI1			122
+#define CLK_SAI1_SRC			123
+#define CLK_SAI1_FRAC			124
+#define CLK_SAI1			125
+#define MCLK_SAI1			126
+#define MCLK_SAI1_OUT2IO		127
+#define HCLK_SAI2			128
+#define CLK_SAI2_SRC			129
+#define CLK_SAI2_FRAC			130
+#define CLK_SAI2			131
+#define MCLK_SAI2			132
+#define MCLK_SAI2_OUT2IO		133
+#define HCLK_DSM			134
+#define CLK_DSM				135
+#define HCLK_PDM			136
+#define MCLK_PDM			137
+#define HCLK_SPDIF			138
+#define CLK_SPDIF_SRC			139
+#define CLK_SPDIF_FRAC			140
+#define CLK_SPDIF			141
+#define MCLK_SPDIF			142
+#define HCLK_SDMMC0			143
+#define CCLK_SDMMC0			144
+#define HCLK_SDMMC1			145
+#define CCLK_SDMMC1			146
+#define SCLK_SDMMC0_DRV			147
+#define SCLK_SDMMC0_SAMPLE		148
+#define SCLK_SDMMC1_DRV			149
+#define SCLK_SDMMC1_SAMPLE		150
+#define HCLK_EMMC			151
+#define ACLK_EMMC			152
+#define CCLK_EMMC			153
+#define BCLK_EMMC			154
+#define TMCLK_EMMC			155
+#define SCLK_SFC			156
+#define HCLK_SFC			157
+#define HCLK_USB2HOST			158
+#define HCLK_USB2HOST_ARB		159
+#define PCLK_SPI1			160
+#define CLK_SPI1			161
+#define SCLK_IN_SPI1			162
+#define PCLK_SPI2			163
+#define CLK_SPI2			164
+#define SCLK_IN_SPI2			165
+#define PCLK_UART1			166
+#define PCLK_UART2			167
+#define PCLK_UART3			168
+#define PCLK_UART4			169
+#define PCLK_UART5			170
+#define PCLK_UART6			171
+#define PCLK_UART7			172
+#define PCLK_UART8			173
+#define PCLK_UART9			174
+#define CLK_UART1_SRC			175
+#define CLK_UART1_FRAC			176
+#define CLK_UART1			177
+#define SCLK_UART1			178
+#define CLK_UART2_SRC			179
+#define CLK_UART2_FRAC			180
+#define CLK_UART2			181
+#define SCLK_UART2			182
+#define CLK_UART3_SRC			183
+#define CLK_UART3_FRAC			184
+#define CLK_UART3			185
+#define SCLK_UART3			186
+#define CLK_UART4_SRC			187
+#define CLK_UART4_FRAC			188
+#define CLK_UART4			189
+#define SCLK_UART4			190
+#define CLK_UART5_SRC			191
+#define CLK_UART5_FRAC			192
+#define CLK_UART5			193
+#define SCLK_UART5			194
+#define CLK_UART6_SRC			195
+#define CLK_UART6_FRAC			196
+#define CLK_UART6			197
+#define SCLK_UART6			198
+#define CLK_UART7_SRC			199
+#define CLK_UART7_FRAC			200
+#define CLK_UART7			201
+#define SCLK_UART7			202
+#define CLK_UART8_SRC			203
+#define CLK_UART8_FRAC			204
+#define CLK_UART8			205
+#define SCLK_UART8			206
+#define CLK_UART9_SRC			207
+#define CLK_UART9_FRAC			208
+#define CLK_UART9			209
+#define SCLK_UART9			210
+#define PCLK_PWM1_PERI			211
+#define CLK_PWM1_PERI			212
+#define CLK_CAPTURE_PWM1_PERI		213
+#define PCLK_PWM2_PERI			214
+#define CLK_PWM2_PERI			215
+#define CLK_CAPTURE_PWM2_PERI		216
+#define PCLK_PWM3_PERI			217
+#define CLK_PWM3_PERI			218
+#define CLK_CAPTURE_PWM3_PERI		219
+#define PCLK_CAN0			220
+#define CLK_CAN0			221
+#define PCLK_CAN1			222
+#define CLK_CAN1			223
+#define ACLK_CRYPTO			224
+#define HCLK_CRYPTO			225
+#define PCLK_CRYPTO			226
+#define CLK_CORE_CRYPTO			227
+#define CLK_PKA_CRYPTO			228
+#define HCLK_KLAD			229
+#define PCLK_KEY_READER			230
+#define HCLK_RK_RNG_NS			231
+#define HCLK_RK_RNG_S			232
+#define HCLK_TRNG_NS			233
+#define HCLK_TRNG_S			234
+#define HCLK_CRYPTO_S			235
+#define PCLK_PERI_WDT			236
+#define TCLK_PERI_WDT			237
+#define ACLK_SYSMEM			238
+#define HCLK_BOOTROM			239
+#define PCLK_PERI_GRF			240
+#define ACLK_DMAC			241
+#define ACLK_RKDMAC			242
+#define PCLK_OTPC_NS			243
+#define CLK_SBPI_OTPC_NS		244
+#define CLK_USER_OTPC_NS		245
+#define PCLK_OTPC_S			246
+#define CLK_SBPI_OTPC_S			247
+#define CLK_USER_OTPC_S			248
+#define CLK_OTPC_ARB			249
+#define PCLK_OTPPHY			250
+#define PCLK_USB2PHY			251
+#define PCLK_PIPEPHY			252
+#define PCLK_SARADC			253
+#define CLK_SARADC			254
+#define PCLK_IOC_VCCIO234		255
+#define PCLK_PERI_GPIO1			256
+#define PCLK_PERI_GPIO2			257
+#define DCLK_PERI_GPIO			258
+#define DCLK_PERI_GPIO1			259
+#define DCLK_PERI_GPIO2			260
+#define ACLK_PHP			261
+#define PCLK_PHP			262
+#define ACLK_PCIE20_MST			263
+#define ACLK_PCIE20_SLV			264
+#define ACLK_PCIE20_DBI			265
+#define PCLK_PCIE20			266
+#define CLK_PCIE20_AUX			267
+#define ACLK_USB3OTG			268
+#define CLK_USB3OTG_SUSPEND		269
+#define CLK_USB3OTG_REF			270
+#define CLK_PIPEPHY_REF_FUNC		271
+#define CLK_200M_PMU			272
+#define CLK_RTC_32K			273
+#define CLK_RTC32K_FRAC			274
+#define BUSCLK_PDPMU0			275
+#define PCLK_PMU0_CRU			276
+#define PCLK_PMU0_PMU			277
+#define CLK_PMU0_PMU			278
+#define PCLK_PMU0_HP_TIMER		279
+#define CLK_PMU0_HP_TIMER		280
+#define CLK_PMU0_32K_HP_TIMER		281
+#define PCLK_PMU0_PVTM			282
+#define CLK_PMU0_PVTM			283
+#define PCLK_IOC_PMUIO			284
+#define PCLK_PMU0_GPIO0			285
+#define DBCLK_PMU0_GPIO0		286
+#define PCLK_PMU0_GRF			287
+#define PCLK_PMU0_SGRF			288
+#define CLK_DDR_FAIL_SAFE		289
+#define PCLK_PMU0_SCRKEYGEN		290
+#define PCLK_PMU1_CRU			291
+#define HCLK_PMU1_MEM			292
+#define PCLK_PMU0_I2C0			293
+#define CLK_PMU0_I2C0			294
+#define PCLK_PMU1_UART0			295
+#define CLK_PMU1_UART0_SRC		296
+#define CLK_PMU1_UART0_FRAC		297
+#define CLK_PMU1_UART0			298
+#define SCLK_PMU1_UART0			299
+#define PCLK_PMU1_SPI0			300
+#define CLK_PMU1_SPI0			301
+#define SCLK_IN_PMU1_SPI0		302
+#define PCLK_PMU1_PWM0			303
+#define CLK_PMU1_PWM0			304
+#define CLK_CAPTURE_PMU1_PWM0		305
+#define CLK_PMU1_WIFI			306
+#define FCLK_PMU1_CM0_CORE		307
+#define CLK_PMU1_CM0_RTC		308
+#define PCLK_PMU1_WDTNS			309
+#define CLK_PMU1_WDTNS			310
+#define PCLK_PMU1_MAILBOX		311
+#define CLK_PIPEPHY_DIV			312
+#define CLK_PIPEPHY_XIN24M		313
+#define CLK_PIPEPHY_REF			314
+#define CLK_24M_SSCSRC			315
+#define CLK_USB2PHY_XIN24M		316
+#define CLK_USB2PHY_REF			317
+#define CLK_MIPIDSIPHY_XIN24M		318
+#define CLK_MIPIDSIPHY_REF		319
+#define ACLK_RGA_PRE			320
+#define HCLK_RGA_PRE			321
+#define ACLK_RGA			322
+#define HCLK_RGA			323
+#define CLK_RGA_CORE			324
+#define ACLK_JDEC			325
+#define HCLK_JDEC			326
+#define ACLK_VDPU_PRE			327
+#define CLK_RKVDEC_HEVC_CA		328
+#define HCLK_VDPU_PRE			329
+#define ACLK_RKVDEC			330
+#define HCLK_RKVDEC			331
+#define CLK_RKVENC_CORE			332
+#define ACLK_VEPU_PRE			333
+#define HCLK_VEPU_PRE			334
+#define ACLK_RKVENC			335
+#define HCLK_RKVENC			336
+#define ACLK_VI				337
+#define HCLK_VI				338
+#define PCLK_VI				339
+#define ACLK_ISP			340
+#define HCLK_ISP			341
+#define CLK_ISP				342
+#define ACLK_VICAP			343
+#define HCLK_VICAP			344
+#define DCLK_VICAP			345
+#define CSIRX0_CLK_DATA			346
+#define CSIRX1_CLK_DATA			347
+#define CSIRX2_CLK_DATA			348
+#define CSIRX3_CLK_DATA			349
+#define PCLK_CSIHOST0			350
+#define PCLK_CSIHOST1			351
+#define PCLK_CSIHOST2			352
+#define PCLK_CSIHOST3			353
+#define PCLK_CSIPHY0			354
+#define PCLK_CSIPHY1			355
+#define ACLK_VO_PRE			356
+#define HCLK_VO_PRE			357
+#define ACLK_VOP			358
+#define HCLK_VOP			359
+#define DCLK_VOP			360
+#define DCLK_VOP1			361
+#define ACLK_CRYPTO_S			362
+#define PCLK_CRYPTO_S			363
+#define CLK_CORE_CRYPTO_S		364
+#define CLK_PKA_CRYPTO_S		365
+
+#endif
diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h
index 25aed298ac2..f576e61bec7 100644
--- a/include/dt-bindings/clock/rockchip,rk3576-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h
@@ -589,4 +589,9 @@
 #define PCLK_EDP_S			569
 #define ACLK_KLAD			570
 
+/* SCMI clocks, use these when changing clocks through SCMI */
+#define SCMI_ARMCLK_L			10
+#define SCMI_ARMCLK_B			11
+#define SCMI_CLK_GPU			456
+
 #endif
diff --git a/include/dt-bindings/clock/samsung,exynos2200-cmu.h b/include/dt-bindings/clock/samsung,exynos2200-cmu.h
new file mode 100644
index 00000000000..310552be0c8
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos2200-cmu.h
@@ -0,0 +1,431 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ *
+ * Device Tree binding constants for Exynos2200 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H
+#define _DT_BINDINGS_CLOCK_EXYNOS2200_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL			1
+#define CLK_FOUT_SHARED1_PLL			2
+#define CLK_FOUT_SHARED2_PLL			3
+#define CLK_FOUT_SHARED3_PLL			4
+#define CLK_FOUT_SHARED4_PLL			5
+#define CLK_FOUT_MMC_PLL			6
+#define CLK_FOUT_SHARED_MIF_PLL			7
+
+#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER	8
+#define CLK_MOUT_CMU_CP_MPLL_CLK_USER		9
+#define CLK_MOUT_CMU_AUD_AUDIF0			10
+#define CLK_MOUT_CMU_AUD_AUDIF1			11
+#define CLK_MOUT_CMU_AUD_CPU			12
+#define CLK_MOUT_CMU_CPUCL0_DBG_NOC		13
+#define CLK_MOUT_CMU_CPUCL0_SWITCH		14
+#define CLK_MOUT_CMU_CPUCL1_SWITCH		15
+#define CLK_MOUT_CMU_CPUCL2_SWITCH		16
+#define CLK_MOUT_CMU_DNC_NOC			17
+#define CLK_MOUT_CMU_DPUB_NOC			18
+#define CLK_MOUT_CMU_DPUF_NOC			19
+#define CLK_MOUT_CMU_DSP_NOC			20
+#define CLK_MOUT_CMU_DSU_SWITCH			21
+#define CLK_MOUT_CMU_G3D_SWITCH			22
+#define CLK_MOUT_CMU_GNPU_NOC			23
+#define CLK_MOUT_CMU_UFS_MMC_CARD		24
+#define CLK_MOUT_CMU_M2M_NOC			25
+#define CLK_MOUT_CMU_NOCL0_NOC			26
+#define CLK_MOUT_CMU_NOCL1A_NOC			27
+#define CLK_MOUT_CMU_NOCL1B_NOC0		28
+#define CLK_MOUT_CMU_NOCL1C_NOC			29
+#define CLK_MOUT_CMU_SDMA_NOC			30
+#define CLK_MOUT_CMU_CP_HISPEEDY_CLK		31
+#define CLK_MOUT_CMU_CP_SHARED0_CLK		32
+#define CLK_MOUT_CMU_CP_SHARED2_CLK		33
+#define CLK_MOUT_CMU_MUX_ALIVE_NOC		34
+#define CLK_MOUT_CMU_MUX_AUD_AUDIF0		35
+#define CLK_MOUT_CMU_MUX_AUD_AUDIF1		36
+#define CLK_MOUT_CMU_MUX_AUD_CPU		37
+#define CLK_MOUT_CMU_MUX_AUD_NOC		38
+#define CLK_MOUT_CMU_MUX_BRP_NOC		39
+#define CLK_MOUT_CMU_MUX_CIS_CLK0		40
+#define CLK_MOUT_CMU_MUX_CIS_CLK1		41
+#define CLK_MOUT_CMU_MUX_CIS_CLK2		42
+#define CLK_MOUT_CMU_MUX_CIS_CLK3		43
+#define CLK_MOUT_CMU_MUX_CIS_CLK4		44
+#define CLK_MOUT_CMU_MUX_CIS_CLK5		45
+#define CLK_MOUT_CMU_MUX_CIS_CLK6		46
+#define CLK_MOUT_CMU_MUX_CIS_CLK7		47
+#define CLK_MOUT_CMU_MUX_CMU_BOOST		48
+#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM		49
+#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU		50
+#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF		51
+#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC		52
+#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP		53
+#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH		54
+#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH		55
+#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH		56
+#define CLK_MOUT_CMU_MUX_CSIS_DCPHY		57
+#define CLK_MOUT_CMU_MUX_CSIS_NOC		58
+#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU		59
+#define CLK_MOUT_CMU_MUX_CSTAT_NOC		60
+#define CLK_MOUT_CMU_MUX_DNC_NOC		61
+#define CLK_MOUT_CMU_MUX_DPUB			62
+#define CLK_MOUT_CMU_MUX_DPUB_ALT		63
+#define CLK_MOUT_CMU_MUX_DPUB_DSIM		64
+#define CLK_MOUT_CMU_MUX_DPUF			65
+#define CLK_MOUT_CMU_MUX_DPUF_ALT		66
+#define CLK_MOUT_CMU_MUX_DSP_NOC		67
+#define CLK_MOUT_CMU_MUX_DSU_SWITCH		68
+#define CLK_MOUT_CMU_MUX_G3D_NOCP		69
+#define CLK_MOUT_CMU_MUX_G3D_SWITCH		70
+#define CLK_MOUT_CMU_MUX_GNPU_NOC		71
+#define CLK_MOUT_CMU_MUX_HSI0_DPGTC		72
+#define CLK_MOUT_CMU_MUX_HSI0_DPOSC		73
+#define CLK_MOUT_CMU_MUX_HSI0_NOC		74
+#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD		75
+#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD		76
+#define CLK_MOUT_CMU_MUX_HSI1_NOC		77
+#define CLK_MOUT_CMU_MUX_HSI1_PCIE		78
+#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD		79
+#define CLK_MOUT_CMU_MUX_LME_LME		80
+#define CLK_MOUT_CMU_MUX_LME_NOC		81
+#define CLK_MOUT_CMU_MUX_M2M_NOC		82
+#define CLK_MOUT_CMU_MUX_MCSC_MCSC		83
+#define CLK_MOUT_CMU_MUX_MCSC_NOC		84
+#define CLK_MOUT_CMU_MUX_MFC0_MFC0		85
+#define CLK_MOUT_CMU_MUX_MFC0_WFD		86
+#define CLK_MOUT_CMU_MUX_MFC1_MFC1		87
+#define CLK_MOUT_CMU_MUX_MIF_NOCP		88
+#define CLK_MOUT_CMU_MUX_MIF_SWITCH		89
+#define CLK_MOUT_CMU_MUX_NOCL0_NOC		90
+#define CLK_MOUT_CMU_MUX_NOCL1A_NOC		91
+#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0		92
+#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1		93
+#define CLK_MOUT_CMU_MUX_NOCL1C_NOC		94
+#define CLK_MOUT_CMU_MUX_PERIC0_IP0		95
+#define CLK_MOUT_CMU_MUX_PERIC0_IP1		96
+#define CLK_MOUT_CMU_MUX_PERIC0_NOC		97
+#define CLK_MOUT_CMU_MUX_PERIC1_IP0		98
+#define CLK_MOUT_CMU_MUX_PERIC1_IP1		99
+#define CLK_MOUT_CMU_MUX_PERIC1_NOC		100
+#define CLK_MOUT_CMU_MUX_PERIC2_IP0		101
+#define CLK_MOUT_CMU_MUX_PERIC2_IP1		102
+#define CLK_MOUT_CMU_MUX_PERIC2_NOC		103
+#define CLK_MOUT_CMU_MUX_PERIS_GIC		104
+#define CLK_MOUT_CMU_MUX_PERIS_NOC		105
+#define CLK_MOUT_CMU_MUX_SDMA_NOC		106
+#define CLK_MOUT_CMU_MUX_SSP_NOC		107
+#define CLK_MOUT_CMU_MUX_VTS_DMIC		108
+#define CLK_MOUT_CMU_MUX_YUVP_NOC		109
+#define CLK_MOUT_CMU_MUX_CMU_CMUREF		110
+#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK	111
+#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK		112
+#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK		113
+#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK		114
+#define CLK_MOUT_CMU_M2M_FRC			115
+#define CLK_MOUT_CMU_MCSC_MCSC			116
+#define CLK_MOUT_CMU_MCSC_NOC			117
+#define CLK_MOUT_CMU_MUX_M2M_FRC		118
+#define CLK_MOUT_CMU_MUX_UFS_NOC		119
+
+#define CLK_DOUT_CMU_ALIVE_NOC			120
+#define CLK_DOUT_CMU_AUD_NOC			121
+#define CLK_DOUT_CMU_BRP_NOC			122
+#define CLK_DOUT_CMU_CMU_BOOST			123
+#define CLK_DOUT_CMU_CMU_BOOST_CAM		124
+#define CLK_DOUT_CMU_CMU_BOOST_CPU		125
+#define CLK_DOUT_CMU_CMU_BOOST_MIF		126
+#define CLK_DOUT_CMU_CPUCL0_NOCP		127
+#define CLK_DOUT_CMU_CSIS_DCPHY			128
+#define CLK_DOUT_CMU_CSIS_NOC			129
+#define CLK_DOUT_CMU_CSIS_OIS_MCU		130
+#define CLK_DOUT_CMU_CSTAT_NOC			131
+#define CLK_DOUT_CMU_DPUB_DSIM			132
+#define CLK_DOUT_CMU_LME_LME			133
+#define CLK_DOUT_CMU_G3D_NOCP			134
+#define CLK_DOUT_CMU_HSI0_DPGTC			135
+#define CLK_DOUT_CMU_HSI0_DPOSC			136
+#define CLK_DOUT_CMU_HSI0_NOC			137
+#define CLK_DOUT_CMU_HSI0_USB32DRD		138
+#define CLK_DOUT_CMU_HSI1_NOC			139
+#define CLK_DOUT_CMU_HSI1_PCIE			140
+#define CLK_DOUT_CMU_UFS_UFS_EMBD		141
+#define CLK_DOUT_CMU_LME_NOC			142
+#define CLK_DOUT_CMU_MFC0_MFC0			143
+#define CLK_DOUT_CMU_MFC0_WFD			144
+#define CLK_DOUT_CMU_MFC1_MFC1			145
+#define CLK_DOUT_CMU_MIF_NOCP			146
+#define CLK_DOUT_CMU_NOCL1B_NOC1		147
+#define CLK_DOUT_CMU_PERIC0_IP0			148
+#define CLK_DOUT_CMU_PERIC0_IP1			149
+#define CLK_DOUT_CMU_PERIC0_NOC			150
+#define CLK_DOUT_CMU_PERIC1_IP0			151
+#define CLK_DOUT_CMU_PERIC1_IP1			152
+#define CLK_DOUT_CMU_PERIC1_NOC			153
+#define CLK_DOUT_CMU_PERIC2_IP0			154
+#define CLK_DOUT_CMU_PERIC2_IP1			155
+#define CLK_DOUT_CMU_PERIC2_NOC			156
+#define CLK_DOUT_CMU_PERIS_GIC			157
+#define CLK_DOUT_CMU_PERIS_NOC			158
+#define CLK_DOUT_CMU_SSP_NOC			159
+#define CLK_DOUT_CMU_VTS_DMIC			160
+#define CLK_DOUT_CMU_YUVP_NOC			161
+#define CLK_DOUT_CMU_CP_SHARED1_CLK		162
+#define CLK_DOUT_CMU_DIV_AUD_AUDIF0		163
+#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM		164
+#define CLK_DOUT_CMU_DIV_AUD_AUDIF1		165
+#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM		166
+#define CLK_DOUT_CMU_DIV_AUD_CPU		167
+#define CLK_DOUT_CMU_DIV_AUD_CPU_SM		168
+#define CLK_DOUT_CMU_DIV_CIS_CLK0		169
+#define CLK_DOUT_CMU_DIV_CIS_CLK1		170
+#define CLK_DOUT_CMU_DIV_CIS_CLK2		171
+#define CLK_DOUT_CMU_DIV_CIS_CLK3		172
+#define CLK_DOUT_CMU_DIV_CIS_CLK4		173
+#define CLK_DOUT_CMU_DIV_CIS_CLK5		174
+#define CLK_DOUT_CMU_DIV_CIS_CLK6		175
+#define CLK_DOUT_CMU_DIV_CIS_CLK7		176
+#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC		177
+#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM	178
+#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH		179
+#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM	180
+#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH		181
+#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM	182
+#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH		183
+#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM	184
+#define CLK_DOUT_CMU_DIV_DNC_NOC		185
+#define CLK_DOUT_CMU_DIV_DNC_NOC_SM		186
+#define CLK_DOUT_CMU_DIV_DPUB			187
+#define CLK_DOUT_CMU_DIV_DPUB_ALT		188
+#define CLK_DOUT_CMU_DIV_DPUF			189
+#define CLK_DOUT_CMU_DIV_DPUF_ALT		190
+#define CLK_DOUT_CMU_DIV_DSP_NOC		191
+#define CLK_DOUT_CMU_DIV_DSP_NOC_SM		192
+#define CLK_DOUT_CMU_DIV_DSU_SWITCH		193
+#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM		194
+#define CLK_DOUT_CMU_DIV_G3D_SWITCH		195
+#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM		196
+#define CLK_DOUT_CMU_DIV_GNPU_NOC		197
+#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM		198
+#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD		199
+#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM	200
+#define CLK_DOUT_CMU_DIV_M2M_NOC		201
+#define CLK_DOUT_CMU_DIV_M2M_NOC_SM		202
+#define CLK_DOUT_CMU_DIV_NOCL0_NOC		203
+#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM		204
+#define CLK_DOUT_CMU_DIV_NOCL1A_NOC		205
+#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM		206
+#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0		207
+#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM		208
+#define CLK_DOUT_CMU_DIV_NOCL1C_NOC		209
+#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM		210
+#define CLK_DOUT_CMU_DIV_SDMA_NOC		211
+#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM		212
+#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK	213
+#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM	214
+#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK		215
+#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM	216
+#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK		217
+#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM	218
+#define CLK_DOUT_CMU_UFS_NOC		219
+#define CLK_DOUT_CMU_DIV_M2M_FRC		220
+#define CLK_DOUT_CMU_DIV_M2M_FRC_SM		221
+#define CLK_DOUT_CMU_DIV_MCSC_MCSC		222
+#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM		223
+#define CLK_DOUT_CMU_DIV_MCSC_NOC		224
+#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM		225
+#define CLK_DOUT_SHARED0_DIV1			226
+#define CLK_DOUT_SHARED0_DIV2			227
+#define CLK_DOUT_SHARED0_DIV4			228
+#define CLK_DOUT_SHARED1_DIV1			229
+#define CLK_DOUT_SHARED1_DIV2			230
+#define CLK_DOUT_SHARED1_DIV4			231
+#define CLK_DOUT_SHARED2_DIV1			232
+#define CLK_DOUT_SHARED2_DIV2			233
+#define CLK_DOUT_SHARED2_DIV4			234
+#define CLK_DOUT_SHARED3_DIV1			235
+#define CLK_DOUT_SHARED3_DIV2			236
+#define CLK_DOUT_SHARED3_DIV4			237
+#define CLK_DOUT_SHARED4_DIV1			238
+#define CLK_DOUT_SHARED4_DIV2			239
+#define CLK_DOUT_SHARED4_DIV4			240
+#define CLK_DOUT_SHARED_MIF_DIV1		241
+#define CLK_DOUT_SHARED_MIF_DIV2		242
+#define CLK_DOUT_SHARED_MIF_DIV4		243
+#define CLK_DOUT_TCXO_DIV3			244
+#define CLK_DOUT_TCXO_DIV4			245
+
+/* CMU_ALIVE */
+#define CLK_MOUT_ALIVE_NOC_USER			1
+#define CLK_MOUT_ALIVE_RCO_SPMI_USER		2
+#define CLK_MOUT_RCO_ALIVE_USER			3
+#define CLK_MOUT_ALIVE_CHUB_PERI		4
+#define CLK_MOUT_ALIVE_CMGP_NOC			5
+#define CLK_MOUT_ALIVE_CMGP_PERI		6
+#define CLK_MOUT_ALIVE_DBGCORE_NOC		7
+#define CLK_MOUT_ALIVE_DNC_NOC			8
+#define CLK_MOUT_ALIVE_CHUBVTS_NOC		9
+#define CLK_MOUT_ALIVE_GNPU_NOC			10
+#define CLK_MOUT_ALIVE_GNSS_NOC			11
+#define CLK_MOUT_ALIVE_SDMA_NOC			12
+#define CLK_MOUT_ALIVE_UFD_NOC			13
+#define CLK_MOUT_ALIVE_DBGCORE_UART		14
+#define CLK_MOUT_ALIVE_NOC			15
+#define CLK_MOUT_ALIVE_PMU_SUB			16
+#define CLK_MOUT_ALIVE_SPMI			17
+#define CLK_MOUT_ALIVE_TIMER			18
+#define CLK_MOUT_ALIVE_CSIS_NOC			19
+#define CLK_MOUT_ALIVE_DSP_NOC			20
+
+#define CLK_DOUT_ALIVE_CHUB_PERI		21
+#define CLK_DOUT_ALIVE_CMGP_NOC			22
+#define CLK_DOUT_ALIVE_CMGP_PERI		23
+#define CLK_DOUT_ALIVE_DBGCORE_NOC		24
+#define CLK_DOUT_ALIVE_DNC_NOC			25
+#define CLK_DOUT_ALIVE_CHUBVTS_NOC		26
+#define CLK_DOUT_ALIVE_GNPU_NOC			27
+#define CLK_DOUT_ALIVE_SDMA_NOC			28
+#define CLK_DOUT_ALIVE_UFD_NOC			29
+#define CLK_DOUT_ALIVE_DBGCORE_UART		30
+#define CLK_DOUT_ALIVE_NOC			31
+#define CLK_DOUT_ALIVE_PMU_SUB			32
+#define CLK_DOUT_ALIVE_SPMI			33
+#define CLK_DOUT_ALIVE_CSIS_NOC			34
+#define CLK_DOUT_ALIVE_DSP_NOC			35
+
+/* CMU_PERIS */
+#define CLK_MOUT_PERIS_GIC_USER			1
+#define CLK_MOUT_PERIS_NOC_USER			2
+#define CLK_MOUT_PERIS_GIC			3
+
+#define CLK_DOUT_PERIS_OTP			4
+#define CLK_DOUT_PERIS_DDD_CTRL			5
+
+/* CMU_CMGP */
+#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER		1
+#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER	2
+#define CLK_MOUT_CMGP_I2C			3
+#define CLK_MOUT_CMGP_SPI_I2C0			4
+#define CLK_MOUT_CMGP_SPI_I2C1			5
+#define CLK_MOUT_CMGP_SPI_MS_CTRL		6
+#define CLK_MOUT_CMGP_USI0			7
+#define CLK_MOUT_CMGP_USI1			8
+#define CLK_MOUT_CMGP_USI2			9
+#define CLK_MOUT_CMGP_USI3			10
+#define CLK_MOUT_CMGP_USI4			11
+#define CLK_MOUT_CMGP_USI5			12
+#define CLK_MOUT_CMGP_USI6			13
+
+#define CLK_DOUT_CMGP_I2C			14
+#define CLK_DOUT_CMGP_SPI_I2C0			15
+#define CLK_DOUT_CMGP_SPI_I2C1			16
+#define CLK_DOUT_CMGP_SPI_MS_CTRL		17
+#define CLK_DOUT_CMGP_USI0			18
+#define CLK_DOUT_CMGP_USI1			19
+#define CLK_DOUT_CMGP_USI2			20
+#define CLK_DOUT_CMGP_USI3			21
+#define CLK_DOUT_CMGP_USI4			22
+#define CLK_DOUT_CMGP_USI5			23
+#define CLK_DOUT_CMGP_USI6			24
+
+/* CMU_HSI0 */
+#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER		1
+#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER		2
+#define CLK_MOUT_CLKCMU_HSI0_NOC_USER		3
+#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER	4
+#define CLK_MOUT_HSI0_NOC			5
+#define CLK_MOUT_HSI0_RTCCLK			6
+#define CLK_MOUT_HSI0_USB32DRD			7
+
+#define CLK_DOUT_DIV_CLK_HSI0_EUSB		8
+
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_IP0_USER		1
+#define CLK_MOUT_PERIC0_IP1_USER		2
+#define CLK_MOUT_PERIC0_NOC_USER		3
+#define CLK_MOUT_PERIC0_I2C			4
+#define CLK_MOUT_PERIC0_USI04			5
+
+#define CLK_DOUT_PERIC0_I2C			6
+#define CLK_DOUT_PERIC0_USI04			7
+
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_IP0_USER		1
+#define CLK_MOUT_PERIC1_IP1_USER		2
+#define CLK_MOUT_PERIC1_NOC_USER		3
+#define CLK_MOUT_PERIC1_I2C			4
+#define CLK_MOUT_PERIC1_SPI_MS_CTRL		5
+#define CLK_MOUT_PERIC1_UART_BT			6
+#define CLK_MOUT_PERIC1_USI07			7
+#define CLK_MOUT_PERIC1_USI07_SPI_I2C		8
+#define CLK_MOUT_PERIC1_USI08			9
+#define CLK_MOUT_PERIC1_USI08_SPI_I2C		10
+#define CLK_MOUT_PERIC1_USI09			11
+#define CLK_MOUT_PERIC1_USI10			12
+
+#define CLK_DOUT_PERIC1_I2C			13
+#define CLK_DOUT_PERIC1_SPI_MS_CTRL		14
+#define CLK_DOUT_PERIC1_UART_BT			15
+#define CLK_DOUT_PERIC1_USI07			16
+#define CLK_DOUT_PERIC1_USI07_SPI_I2C		17
+#define CLK_DOUT_PERIC1_USI08			18
+#define CLK_DOUT_PERIC1_USI08_SPI_I2C		19
+#define CLK_DOUT_PERIC1_USI09			20
+#define CLK_DOUT_PERIC1_USI10			21
+
+/* CMU_PERIC2 */
+#define CLK_MOUT_PERIC2_IP0_USER		1
+#define CLK_MOUT_PERIC2_IP1_USER		2
+#define CLK_MOUT_PERIC2_NOC_USER		3
+#define CLK_MOUT_PERIC2_I2C			4
+#define CLK_MOUT_PERIC2_SPI_MS_CTRL		5
+#define CLK_MOUT_PERIC2_UART_DBG		6
+#define CLK_MOUT_PERIC2_USI00			7
+#define CLK_MOUT_PERIC2_USI00_SPI_I2C		8
+#define CLK_MOUT_PERIC2_USI01			9
+#define CLK_MOUT_PERIC2_USI01_SPI_I2C		10
+#define CLK_MOUT_PERIC2_USI02			11
+#define CLK_MOUT_PERIC2_USI03			12
+#define CLK_MOUT_PERIC2_USI05			13
+#define CLK_MOUT_PERIC2_USI06			14
+#define CLK_MOUT_PERIC2_USI11			15
+
+#define CLK_DOUT_PERIC2_I2C			16
+#define CLK_DOUT_PERIC2_SPI_MS_CTRL		17
+#define CLK_DOUT_PERIC2_UART_DBG		18
+#define CLK_DOUT_PERIC2_USI00			19
+#define CLK_DOUT_PERIC2_USI00_SPI_I2C		20
+#define CLK_DOUT_PERIC2_USI01			21
+#define CLK_DOUT_PERIC2_USI01_SPI_I2C		22
+#define CLK_DOUT_PERIC2_USI02			23
+#define CLK_DOUT_PERIC2_USI03			24
+#define CLK_DOUT_PERIC2_USI05			25
+#define CLK_DOUT_PERIC2_USI06			26
+#define CLK_DOUT_PERIC2_USI11			27
+
+/* CMU_UFS */
+#define CLK_MOUT_UFS_MMC_CARD_USER		1
+#define CLK_MOUT_UFS_NOC_USER			2
+#define CLK_MOUT_UFS_UFS_EMBD_USER		3
+
+/* CMU_VTS */
+#define CLK_MOUT_CLKALIVE_VTS_NOC_USER		1
+#define CLK_MOUT_CLKALIVE_VTS_RCO_USER		2
+#define CLK_MOUT_CLKCMU_VTS_DMIC_USER		3
+#define CLK_MOUT_CLKVTS_AUD_DMIC1		4
+#define CLK_MOUT_CLKVTS_NOC			5
+#define CLK_MOUT_CLKVTS_DMIC_PAD		6
+
+#define CLK_DOUT_CLKVTS_AUD_DMIC0		7
+#define CLK_DOUT_CLKVTS_AUD_DMIC1		8
+#define CLK_DOUT_CLKVTS_CPU			9
+#define CLK_DOUT_CLKVTS_DMIC_IF			10
+#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2		11
+#define CLK_DOUT_CLKVTS_NOC			12
+#define CLK_DOUT_CLKVTS_SERIAL_LIF		13
+#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE		14
+
+#endif
diff --git a/include/dt-bindings/clock/samsung,exynos7870-cmu.h b/include/dt-bindings/clock/samsung,exynos7870-cmu.h
new file mode 100644
index 00000000000..57d04bbe342
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos7870-cmu.h
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Kaustabh Chakraborty <kauschluss@disroot.org>
+ *
+ * Device Tree binding constants for Exynos7870 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7870_H
+
+/* CMU_MIF */
+#define CLK_DOUT_MIF_APB				1
+#define CLK_DOUT_MIF_BUSD				2
+#define CLK_DOUT_MIF_CMU_DISPAUD_BUS			3
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK		4
+#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK		5
+#define CLK_DOUT_MIF_CMU_FSYS_BUS			6
+#define CLK_DOUT_MIF_CMU_FSYS_MMC0			7
+#define CLK_DOUT_MIF_CMU_FSYS_MMC1			8
+#define CLK_DOUT_MIF_CMU_FSYS_MMC2			9
+#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK		10
+#define CLK_DOUT_MIF_CMU_G3D_SWITCH			11
+#define CLK_DOUT_MIF_CMU_ISP_CAM			12
+#define CLK_DOUT_MIF_CMU_ISP_ISP			13
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR0			14
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR1			15
+#define CLK_DOUT_MIF_CMU_ISP_SENSOR2			16
+#define CLK_DOUT_MIF_CMU_ISP_VRA			17
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC			18
+#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL			19
+#define CLK_DOUT_MIF_CMU_PERI_BUS			20
+#define CLK_DOUT_MIF_CMU_PERI_SPI0			21
+#define CLK_DOUT_MIF_CMU_PERI_SPI1			22
+#define CLK_DOUT_MIF_CMU_PERI_SPI2			23
+#define CLK_DOUT_MIF_CMU_PERI_SPI3			24
+#define CLK_DOUT_MIF_CMU_PERI_SPI4			25
+#define CLK_DOUT_MIF_CMU_PERI_UART0			26
+#define CLK_DOUT_MIF_CMU_PERI_UART1			27
+#define CLK_DOUT_MIF_CMU_PERI_UART2			28
+#define CLK_DOUT_MIF_HSI2C				29
+#define CLK_FOUT_MIF_BUS_PLL				30
+#define CLK_FOUT_MIF_MEDIA_PLL				31
+#define CLK_FOUT_MIF_MEM_PLL				32
+#define CLK_GOUT_MIF_CMU_DISPAUD_BUS			33
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK		34
+#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK		35
+#define CLK_GOUT_MIF_CMU_FSYS_BUS			36
+#define CLK_GOUT_MIF_CMU_FSYS_MMC0			37
+#define CLK_GOUT_MIF_CMU_FSYS_MMC1			38
+#define CLK_GOUT_MIF_CMU_FSYS_MMC2			39
+#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK		40
+#define CLK_GOUT_MIF_CMU_G3D_SWITCH			41
+#define CLK_GOUT_MIF_CMU_ISP_CAM			42
+#define CLK_GOUT_MIF_CMU_ISP_ISP			43
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR0			44
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR1			45
+#define CLK_GOUT_MIF_CMU_ISP_SENSOR2			46
+#define CLK_GOUT_MIF_CMU_ISP_VRA			47
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC			48
+#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL			49
+#define CLK_GOUT_MIF_CMU_PERI_BUS			50
+#define CLK_GOUT_MIF_CMU_PERI_SPI0			51
+#define CLK_GOUT_MIF_CMU_PERI_SPI1			52
+#define CLK_GOUT_MIF_CMU_PERI_SPI2			53
+#define CLK_GOUT_MIF_CMU_PERI_SPI3			54
+#define CLK_GOUT_MIF_CMU_PERI_SPI4			55
+#define CLK_GOUT_MIF_CMU_PERI_UART0			56
+#define CLK_GOUT_MIF_CMU_PERI_UART1			57
+#define CLK_GOUT_MIF_CMU_PERI_UART2			58
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C			59
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0		60
+#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1		61
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKM			62
+#define CLK_GOUT_MIF_HSI2C_AP_PCLKS			63
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKM			64
+#define CLK_GOUT_MIF_HSI2C_CP_PCLKS			65
+#define CLK_GOUT_MIF_HSI2C_IPCLK			66
+#define CLK_GOUT_MIF_HSI2C_ITCLK			67
+#define CLK_GOUT_MIF_MUX_BUSD				68
+#define CLK_GOUT_MIF_MUX_BUS_PLL			69
+#define CLK_GOUT_MIF_MUX_BUS_PLL_CON			70
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS		71
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK		72
+#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK		73
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS			74
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0			75
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1			76
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2			77
+#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK	78
+#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM			79
+#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP			80
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0		81
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1		82
+#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2		83
+#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA			84
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC		85
+#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL		86
+#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS			87
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0			88
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1			89
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2			90
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3			91
+#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4			92
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0			93
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1			94
+#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2			95
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL			96
+#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON			97
+#define CLK_GOUT_MIF_MUX_MEM_PLL			98
+#define CLK_GOUT_MIF_MUX_MEM_PLL_CON			99
+#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS		100
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0		101
+#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1		102
+#define CLK_MOUT_MIF_BUSD				103
+#define CLK_MOUT_MIF_CMU_DISPAUD_BUS			104
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK		105
+#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK		106
+#define CLK_MOUT_MIF_CMU_FSYS_BUS			107
+#define CLK_MOUT_MIF_CMU_FSYS_MMC0			108
+#define CLK_MOUT_MIF_CMU_FSYS_MMC1			109
+#define CLK_MOUT_MIF_CMU_FSYS_MMC2			110
+#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK		111
+#define CLK_MOUT_MIF_CMU_ISP_CAM			112
+#define CLK_MOUT_MIF_CMU_ISP_ISP			113
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR0			114
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR1			115
+#define CLK_MOUT_MIF_CMU_ISP_SENSOR2			116
+#define CLK_MOUT_MIF_CMU_ISP_VRA			117
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC			118
+#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL			119
+#define CLK_MOUT_MIF_CMU_PERI_BUS			120
+#define CLK_MOUT_MIF_CMU_PERI_SPI0			121
+#define CLK_MOUT_MIF_CMU_PERI_SPI1			122
+#define CLK_MOUT_MIF_CMU_PERI_SPI2			123
+#define CLK_MOUT_MIF_CMU_PERI_SPI3			124
+#define CLK_MOUT_MIF_CMU_PERI_SPI4			125
+#define CLK_MOUT_MIF_CMU_PERI_UART0			126
+#define CLK_MOUT_MIF_CMU_PERI_UART1			127
+#define CLK_MOUT_MIF_CMU_PERI_UART2			128
+#define MIF_NR_CLK					129
+
+/* CMU_DISPAUD */
+#define CLK_DOUT_DISPAUD_APB					1
+#define CLK_DOUT_DISPAUD_DECON_ECLK				2
+#define CLK_DOUT_DISPAUD_DECON_VCLK				3
+#define CLK_DOUT_DISPAUD_MI2S					4
+#define CLK_DOUT_DISPAUD_MIXER					5
+#define CLK_FOUT_DISPAUD_AUD_PLL				6
+#define CLK_FOUT_DISPAUD_PLL					7
+#define CLK_GOUT_DISPAUD_APB_AUD				8
+#define CLK_GOUT_DISPAUD_APB_AUD_AMP				9
+#define CLK_GOUT_DISPAUD_APB_DISP				10
+#define CLK_GOUT_DISPAUD_BUS					11
+#define CLK_GOUT_DISPAUD_BUS_DISP				12
+#define CLK_GOUT_DISPAUD_BUS_PPMU				13
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN			14
+#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN			15
+#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK				16
+#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S		17
+#define CLK_GOUT_DISPAUD_DECON_ECLK				18
+#define CLK_GOUT_DISPAUD_DECON_VCLK				19
+#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI			20
+#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI			21
+#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK			22
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL				23
+#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON			24
+#define CLK_GOUT_DISPAUD_MUX_BUS_USER				25
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK				26
+#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER			27
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK				28
+#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER			29
+#define CLK_GOUT_DISPAUD_MUX_MI2S				30
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER		31
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON		32
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER		33
+#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON	34
+#define CLK_GOUT_DISPAUD_MUX_PLL				35
+#define CLK_GOUT_DISPAUD_MUX_PLL_CON				36
+#define CLK_MOUT_DISPAUD_BUS_USER				37
+#define CLK_MOUT_DISPAUD_DECON_ECLK				38
+#define CLK_MOUT_DISPAUD_DECON_ECLK_USER			39
+#define CLK_MOUT_DISPAUD_DECON_VCLK				40
+#define CLK_MOUT_DISPAUD_DECON_VCLK_USER			41
+#define CLK_MOUT_DISPAUD_MI2S					42
+#define DISPAUD_NR_CLK						43
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_USB_PLL				1
+#define CLK_GOUT_FSYS_BUSP3_HCLK			2
+#define CLK_GOUT_FSYS_MMC0_ACLK				3
+#define CLK_GOUT_FSYS_MMC1_ACLK				4
+#define CLK_GOUT_FSYS_MMC2_ACLK				5
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER	6
+#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON	7
+#define CLK_GOUT_FSYS_MUX_USB_PLL			8
+#define CLK_GOUT_FSYS_MUX_USB_PLL_CON			9
+#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0			10
+#define CLK_GOUT_FSYS_PPMU_ACLK				11
+#define CLK_GOUT_FSYS_PPMU_PCLK				12
+#define CLK_GOUT_FSYS_SROMC_HCLK			13
+#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK			14
+#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD		15
+#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL		16
+#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK		17
+#define FSYS_NR_CLK					18
+
+/* CMU_G3D */
+#define CLK_DOUT_G3D_APB		1
+#define CLK_DOUT_G3D_BUS		2
+#define CLK_FOUT_G3D_PLL		3
+#define CLK_GOUT_G3D_ASYNCS_D0_CLK	4
+#define CLK_GOUT_G3D_ASYNC_PCLKM	5
+#define CLK_GOUT_G3D_CLK		6
+#define CLK_GOUT_G3D_MUX		7
+#define CLK_GOUT_G3D_MUX_PLL		8
+#define CLK_GOUT_G3D_MUX_PLL_CON	9
+#define CLK_GOUT_G3D_MUX_SWITCH_USER	10
+#define CLK_GOUT_G3D_PPMU_ACLK		11
+#define CLK_GOUT_G3D_PPMU_PCLK		12
+#define CLK_GOUT_G3D_QE_ACLK		13
+#define CLK_GOUT_G3D_QE_PCLK		14
+#define CLK_GOUT_G3D_SYSREG_PCLK	15
+#define CLK_MOUT_G3D			16
+#define CLK_MOUT_G3D_SWITCH_USER	17
+#define G3D_NR_CLK			18
+
+/* CMU_ISP */
+#define CLK_DOUT_ISP_APB				1
+#define CLK_DOUT_ISP_CAM_HALF				2
+#define CLK_FOUT_ISP_PLL				3
+#define CLK_GOUT_ISP_CAM				4
+#define CLK_GOUT_ISP_CAM_HALF				5
+#define CLK_GOUT_ISP_ISPD				6
+#define CLK_GOUT_ISP_ISPD_PPMU				7
+#define CLK_GOUT_ISP_MUX_CAM				8
+#define CLK_GOUT_ISP_MUX_CAM_USER			9
+#define CLK_GOUT_ISP_MUX_ISP				10
+#define CLK_GOUT_ISP_MUX_ISPD				11
+#define CLK_GOUT_ISP_MUX_PLL				12
+#define CLK_GOUT_ISP_MUX_PLL_CON			13
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER	14
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON	15
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER	16
+#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON	17
+#define CLK_GOUT_ISP_MUX_USER				18
+#define CLK_GOUT_ISP_MUX_VRA				19
+#define CLK_GOUT_ISP_MUX_VRA_USER			20
+#define CLK_GOUT_ISP_VRA				21
+#define CLK_MOUT_ISP_CAM				22
+#define CLK_MOUT_ISP_CAM_USER				23
+#define CLK_MOUT_ISP_ISP				24
+#define CLK_MOUT_ISP_ISPD				25
+#define CLK_MOUT_ISP_USER				26
+#define CLK_MOUT_ISP_VRA				27
+#define CLK_MOUT_ISP_VRA_USER				28
+#define ISP_NR_CLK					29
+
+/* CMU_MFCMSCL */
+#define CLK_DOUT_MFCMSCL_APB		1
+#define CLK_GOUT_MFCMSCL_MFC		2
+#define CLK_GOUT_MFCMSCL_MSCL		3
+#define CLK_GOUT_MFCMSCL_MSCL_BI	4
+#define CLK_GOUT_MFCMSCL_MSCL_D		5
+#define CLK_GOUT_MFCMSCL_MSCL_JPEG	6
+#define CLK_GOUT_MFCMSCL_MSCL_POLY	7
+#define CLK_GOUT_MFCMSCL_MSCL_PPMU	8
+#define CLK_GOUT_MFCMSCL_MUX_MFC_USER	9
+#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER	10
+#define CLK_MOUT_MFCMSCL_MFC_USER	11
+#define CLK_MOUT_MFCMSCL_MSCL_USER	12
+#define MFCMSCL_NR_CLK			13
+
+/* CMU_PERI */
+#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK		1
+#define CLK_GOUT_PERI_GPIO2_PCLK		2
+#define CLK_GOUT_PERI_GPIO5_PCLK		3
+#define CLK_GOUT_PERI_GPIO6_PCLK		4
+#define CLK_GOUT_PERI_GPIO7_PCLK		5
+#define CLK_GOUT_PERI_HSI2C1_IPCLK		6
+#define CLK_GOUT_PERI_HSI2C2_IPCLK		7
+#define CLK_GOUT_PERI_HSI2C3_IPCLK		8
+#define CLK_GOUT_PERI_HSI2C4_IPCLK		9
+#define CLK_GOUT_PERI_HSI2C5_IPCLK		10
+#define CLK_GOUT_PERI_HSI2C6_IPCLK		11
+#define CLK_GOUT_PERI_I2C0_PCLK			12
+#define CLK_GOUT_PERI_I2C1_PCLK			13
+#define CLK_GOUT_PERI_I2C2_PCLK			14
+#define CLK_GOUT_PERI_I2C3_PCLK			15
+#define CLK_GOUT_PERI_I2C4_PCLK			16
+#define CLK_GOUT_PERI_I2C5_PCLK			17
+#define CLK_GOUT_PERI_I2C6_PCLK			18
+#define CLK_GOUT_PERI_I2C7_PCLK			19
+#define CLK_GOUT_PERI_I2C8_PCLK			20
+#define CLK_GOUT_PERI_MCT_PCLK			21
+#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK		22
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0		23
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK	24
+#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK	25
+#define CLK_GOUT_PERI_SFRIF_TMU_PCLK		26
+#define CLK_GOUT_PERI_SPI0_PCLK			27
+#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK		28
+#define CLK_GOUT_PERI_SPI1_PCLK			29
+#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK		30
+#define CLK_GOUT_PERI_SPI2_PCLK			31
+#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK		32
+#define CLK_GOUT_PERI_SPI3_PCLK			33
+#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK		34
+#define CLK_GOUT_PERI_SPI4_PCLK			35
+#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK		36
+#define CLK_GOUT_PERI_TMU_CLK			37
+#define CLK_GOUT_PERI_TMU_CPUCL0_CLK		38
+#define CLK_GOUT_PERI_TMU_CPUCL1_CLK		39
+#define CLK_GOUT_PERI_UART0_EXT_UCLK		40
+#define CLK_GOUT_PERI_UART0_PCLK		41
+#define CLK_GOUT_PERI_UART1_EXT_UCLK		42
+#define CLK_GOUT_PERI_UART1_PCLK		43
+#define CLK_GOUT_PERI_UART2_EXT_UCLK		44
+#define CLK_GOUT_PERI_UART2_PCLK		45
+#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK		46
+#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK		47
+#define PERI_NR_CLK				48
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */
diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
index 307215a3f3e..6b9df09d282 100644
--- a/include/dt-bindings/clock/samsung,exynos990.h
+++ b/include/dt-bindings/clock/samsung,exynos990.h
@@ -233,4 +233,25 @@
 #define CLK_GOUT_HSI0_CMU_HSI0_PCLK			21
 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK			22
 
+/* CMU_PERIS */
+#define CLK_MOUT_PERIS_BUS_USER			1
+#define CLK_MOUT_PERIS_CLK_PERIS_GIC		2
+#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK	3
+#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK	4
+#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK	5
+#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK	6
+#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK	7
+#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK	8
+#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK	9
+#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM	10
+#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK	11
+#define CLK_GOUT_PERIS_GIC_CLK			12
+#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK	13
+#define CLK_GOUT_PERIS_MCT_PCLK			14
+#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK		15
+#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK	16
+#define CLK_GOUT_PERIS_TMU_TOP_PCLK		17
+#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK	18
+#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK	19
+
 #endif
diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h
index ebb146ab7f8..6889405f9fe 100644
--- a/include/dt-bindings/clock/sun50i-h616-ccu.h
+++ b/include/dt-bindings/clock/sun50i-h616-ccu.h
@@ -113,5 +113,9 @@
 #define CLK_BUS_HDCP		127
 #define CLK_PLL_SYSTEM_32K	128
 #define CLK_BUS_GPADC		129
+#define CLK_TCON_LCD0		130
+#define CLK_BUS_TCON_LCD0	131
+#define CLK_TCON_LCD1		132
+#define CLK_BUS_TCON_LCD1	133
 
 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h
new file mode 100644
index 00000000000..c8259ac5ada
--- /dev/null
+++ b/include/dt-bindings/clock/sun55i-a523-ccu.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
+#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
+
+#define CLK_PLL_DDR0		0
+#define CLK_PLL_PERIPH0_4X	1
+#define CLK_PLL_PERIPH0_2X	2
+#define CLK_PLL_PERIPH0_800M	3
+#define CLK_PLL_PERIPH0_480M	4
+#define CLK_PLL_PERIPH0_600M	5
+#define CLK_PLL_PERIPH0_400M	6
+#define CLK_PLL_PERIPH0_300M	7
+#define CLK_PLL_PERIPH0_200M	8
+#define CLK_PLL_PERIPH0_160M	9
+#define CLK_PLL_PERIPH0_150M	10
+#define CLK_PLL_PERIPH1_4X	11
+#define CLK_PLL_PERIPH1_2X	12
+#define CLK_PLL_PERIPH1_800M	13
+#define CLK_PLL_PERIPH1_480M	14
+#define CLK_PLL_PERIPH1_600M	15
+#define CLK_PLL_PERIPH1_400M	16
+#define CLK_PLL_PERIPH1_300M	17
+#define CLK_PLL_PERIPH1_200M	18
+#define CLK_PLL_PERIPH1_160M	19
+#define CLK_PLL_PERIPH1_150M	20
+#define CLK_PLL_GPU		21
+#define CLK_PLL_VIDEO0_8X	22
+#define CLK_PLL_VIDEO0_4X	23
+#define CLK_PLL_VIDEO0_3X	24
+#define CLK_PLL_VIDEO1_8X	25
+#define CLK_PLL_VIDEO1_4X	26
+#define CLK_PLL_VIDEO1_3X	27
+#define CLK_PLL_VIDEO2_8X	28
+#define CLK_PLL_VIDEO2_4X	29
+#define CLK_PLL_VIDEO2_3X	30
+#define CLK_PLL_VIDEO3_8X	31
+#define CLK_PLL_VIDEO3_4X	32
+#define CLK_PLL_VIDEO3_3X	33
+#define CLK_PLL_VE		34
+#define CLK_PLL_AUDIO0_4X	35
+#define CLK_PLL_AUDIO0_2X	36
+#define CLK_PLL_AUDIO0		37
+#define CLK_PLL_NPU_4X		38
+#define CLK_PLL_NPU_2X		39
+#define CLK_PLL_NPU		40
+#define CLK_AHB			41
+#define CLK_APB0		42
+#define CLK_APB1		43
+#define CLK_MBUS		44
+#define CLK_DE			45
+#define CLK_BUS_DE		46
+#define CLK_DI			47
+#define CLK_BUS_DI		48
+#define CLK_G2D			49
+#define CLK_BUS_G2D		50
+#define CLK_GPU			51
+#define CLK_BUS_GPU		52
+#define CLK_CE			53
+#define CLK_BUS_CE		54
+#define CLK_BUS_CE_SYS		55
+#define CLK_VE			56
+#define CLK_BUS_VE		57
+#define CLK_BUS_DMA		58
+#define CLK_BUS_MSGBOX		59
+#define CLK_BUS_SPINLOCK	60
+#define CLK_HSTIMER0		61
+#define CLK_HSTIMER1		62
+#define CLK_HSTIMER2		63
+#define CLK_HSTIMER3		64
+#define CLK_HSTIMER4		65
+#define CLK_HSTIMER5		66
+#define CLK_BUS_HSTIMER		67
+#define CLK_BUS_DBG		68
+#define CLK_BUS_PWM0		69
+#define CLK_BUS_PWM1		70
+#define CLK_IOMMU		71
+#define CLK_BUS_IOMMU		72
+#define CLK_DRAM		73
+#define CLK_MBUS_DMA		74
+#define CLK_MBUS_VE		75
+#define CLK_MBUS_CE		76
+#define CLK_MBUS_CSI		77
+#define CLK_MBUS_ISP		78
+#define CLK_MBUS_EMAC1		79
+#define CLK_BUS_DRAM		80
+#define CLK_NAND0		81
+#define CLK_NAND1		82
+#define CLK_BUS_NAND		83
+#define CLK_MMC0		84
+#define CLK_MMC1		85
+#define CLK_MMC2		86
+#define CLK_BUS_SYSDAP		87
+#define CLK_BUS_MMC0		88
+#define CLK_BUS_MMC1		89
+#define CLK_BUS_MMC2		90
+#define CLK_BUS_UART0		91
+#define CLK_BUS_UART1		92
+#define CLK_BUS_UART2		93
+#define CLK_BUS_UART3		94
+#define CLK_BUS_UART4		95
+#define CLK_BUS_UART5		96
+#define CLK_BUS_UART6		97
+#define CLK_BUS_UART7		98
+#define CLK_BUS_I2C0		99
+#define CLK_BUS_I2C1		100
+#define CLK_BUS_I2C2		101
+#define CLK_BUS_I2C3		102
+#define CLK_BUS_I2C4		103
+#define CLK_BUS_I2C5		104
+#define CLK_BUS_CAN		105
+#define CLK_SPI0		106
+#define CLK_SPI1		107
+#define CLK_SPI2		108
+#define CLK_SPIFC		109
+#define CLK_BUS_SPI0		110
+#define CLK_BUS_SPI1		111
+#define CLK_BUS_SPI2		112
+#define CLK_BUS_SPIFC		113
+#define CLK_EMAC0_25M		114
+#define CLK_EMAC1_25M		115
+#define CLK_BUS_EMAC0		116
+#define CLK_BUS_EMAC1		117
+#define CLK_IR_RX		118
+#define CLK_BUS_IR_RX		119
+#define CLK_IR_TX		120
+#define CLK_BUS_IR_TX		121
+#define CLK_GPADC0		122
+#define CLK_GPADC1		123
+#define CLK_BUS_GPADC0		124
+#define CLK_BUS_GPADC1		125
+#define CLK_BUS_THS		126
+#define CLK_USB_OHCI0		127
+#define CLK_USB_OHCI1		128
+#define CLK_BUS_OHCI0		129
+#define CLK_BUS_OHCI1		130
+#define CLK_BUS_EHCI0		131
+#define CLK_BUS_EHCI1		132
+#define CLK_BUS_OTG		133
+#define CLK_BUS_LRADC		134
+#define CLK_PCIE_AUX		135
+#define CLK_BUS_DISPLAY0_TOP	136
+#define CLK_BUS_DISPLAY1_TOP	137
+#define CLK_HDMI_24M		138
+#define CLK_HDMI_CEC_32K	139
+#define CLK_HDMI_CEC		140
+#define CLK_BUS_HDMI		141
+#define CLK_MIPI_DSI0		142
+#define CLK_MIPI_DSI1		143
+#define CLK_BUS_MIPI_DSI0	144
+#define CLK_BUS_MIPI_DSI1	145
+#define CLK_TCON_LCD0		146
+#define CLK_TCON_LCD1		147
+#define CLK_TCON_LCD2		148
+#define CLK_COMBOPHY_DSI0	149
+#define CLK_COMBOPHY_DSI1	150
+#define CLK_BUS_TCON_LCD0	151
+#define CLK_BUS_TCON_LCD1	152
+#define CLK_BUS_TCON_LCD2	153
+#define CLK_TCON_TV0		154
+#define CLK_TCON_TV1		155
+#define CLK_BUS_TCON_TV0	156
+#define CLK_BUS_TCON_TV1	157
+#define CLK_EDP			158
+#define CLK_BUS_EDP		159
+#define CLK_LEDC		160
+#define CLK_BUS_LEDC		161
+#define CLK_CSI_TOP		162
+#define CLK_CSI_MCLK0		163
+#define CLK_CSI_MCLK1		164
+#define CLK_CSI_MCLK2		165
+#define CLK_CSI_MCLK3		166
+#define CLK_BUS_CSI		167
+#define CLK_ISP			168
+#define CLK_DSP			169
+#define CLK_FANOUT_24M		170
+#define CLK_FANOUT_12M		171
+#define CLK_FANOUT_16M		172
+#define CLK_FANOUT_25M		173
+#define CLK_FANOUT_27M		174
+#define CLK_FANOUT_PCLK		175
+#define CLK_FANOUT0		176
+#define CLK_FANOUT1		177
+#define CLK_FANOUT2		178
+
+#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun55i-a523-r-ccu.h b/include/dt-bindings/clock/sun55i-a523-r-ccu.h
new file mode 100644
index 00000000000..365647499b9
--- /dev/null
+++ b/include/dt-bindings/clock/sun55i-a523-r-ccu.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_
+
+#define CLK_R_AHB		0
+#define CLK_R_APB0		1
+#define CLK_R_APB1		2
+#define CLK_R_TIMER0		3
+#define CLK_R_TIMER1		4
+#define CLK_R_TIMER2		5
+#define CLK_BUS_R_TIMER		6
+#define CLK_BUS_R_TWD		7
+#define CLK_R_PWMCTRL		8
+#define CLK_BUS_R_PWMCTRL	9
+#define CLK_R_SPI		10
+#define CLK_BUS_R_SPI		11
+#define CLK_BUS_R_SPINLOCK	12
+#define CLK_BUS_R_MSGBOX	13
+#define CLK_BUS_R_UART0		14
+#define CLK_BUS_R_UART1		15
+#define CLK_BUS_R_I2C0		16
+#define CLK_BUS_R_I2C1		17
+#define CLK_BUS_R_I2C2		18
+#define CLK_BUS_R_PPU0		19
+#define CLK_BUS_R_PPU1		20
+#define CLK_BUS_R_CPU_BIST	21
+#define CLK_R_IR_RX		22
+#define CLK_BUS_R_IR_RX		23
+#define CLK_BUS_R_DMA		24
+#define CLK_BUS_R_RTC		25
+#define CLK_BUS_R_CPUCFG	26
+
+#endif /* _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
index cdc4c0b9a37..f0f7ddd3dcb 100644
--- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h
+++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
@@ -9,6 +9,13 @@
 #ifndef _DT_BINDINGS_CLK_ZYNQMP_H
 #define _DT_BINDINGS_CLK_ZYNQMP_H
 
+/*
+ * These bindings are deprecated, because they do not match the actual
+ * concept of bindings but rather contain pure firmware values.
+ * Instead include the header in the DTS source directory.
+ */
+#warning "These bindings are deprecated. Instead use the header in the DTS source directory."
+
 #define IOPLL			0
 #define RPLL			1
 #define APLL			2
diff --git a/include/dt-bindings/iio/adc/adi,ad4695.h b/include/dt-bindings/iio/adc/adi,ad4695.h
index 9fbef542bf6..fea4525d271 100644
--- a/include/dt-bindings/iio/adc/adi,ad4695.h
+++ b/include/dt-bindings/iio/adc/adi,ad4695.h
@@ -6,4 +6,11 @@
 #define AD4695_COMMON_MODE_REFGND	0xFF
 #define AD4695_COMMON_MODE_COM		0xFE
 
+#define AD4695_TRIGGER_EVENT_BUSY	0
+#define AD4695_TRIGGER_EVENT_ALERT	1
+
+#define AD4695_TRIGGER_PIN_GP0		0
+#define AD4695_TRIGGER_PIN_GP2		2
+#define AD4695_TRIGGER_PIN_GP3		3
+
 #endif /* _DT_BINDINGS_ADI_AD4695_H */
diff --git a/include/dt-bindings/pinctrl/amlogic,pinctrl.h b/include/dt-bindings/pinctrl/amlogic,pinctrl.h
new file mode 100644
index 00000000000..7d40aecc714
--- /dev/null
+++ b/include/dt-bindings/pinctrl/amlogic,pinctrl.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Xianwei Zhao <xianwei.zhao@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_PINCTRL_H
+#define _DT_BINDINGS_AMLOGIC_PINCTRL_H
+/* Normal PIN bank */
+#define AMLOGIC_GPIO_A		0
+#define AMLOGIC_GPIO_B		1
+#define AMLOGIC_GPIO_C		2
+#define AMLOGIC_GPIO_D		3
+#define AMLOGIC_GPIO_E		4
+#define AMLOGIC_GPIO_F		5
+#define AMLOGIC_GPIO_G		6
+#define AMLOGIC_GPIO_H		7
+#define AMLOGIC_GPIO_I		8
+#define AMLOGIC_GPIO_J		9
+#define AMLOGIC_GPIO_K		10
+#define AMLOGIC_GPIO_L		11
+#define AMLOGIC_GPIO_M		12
+#define AMLOGIC_GPIO_N		13
+#define AMLOGIC_GPIO_O		14
+#define AMLOGIC_GPIO_P		15
+#define AMLOGIC_GPIO_Q		16
+#define AMLOGIC_GPIO_R		17
+#define AMLOGIC_GPIO_S		18
+#define AMLOGIC_GPIO_T		19
+#define AMLOGIC_GPIO_U		20
+#define AMLOGIC_GPIO_V		21
+#define AMLOGIC_GPIO_W		22
+#define AMLOGIC_GPIO_X		23
+#define AMLOGIC_GPIO_Y		24
+#define AMLOGIC_GPIO_Z		25
+
+/* Special PIN bank */
+#define AMLOGIC_GPIO_DV		26
+#define AMLOGIC_GPIO_AO		27
+#define AMLOGIC_GPIO_CC		28
+#define AMLOGIC_GPIO_TEST_N	29
+#define AMLOGIC_GPIO_ANALOG	30
+
+#define AML_PINMUX(bank, offset, mode)	(((((bank) << 8) + (offset)) << 8) | (mode))
+
+#endif /* _DT_BINDINGS_AMLOGIC_PINCTRL_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-sg2042.h b/include/dt-bindings/pinctrl/pinctrl-sg2042.h
new file mode 100644
index 00000000000..79d5bb8e04f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-sg2042.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_SG2042_H
+#define _DT_BINDINGS_PINCTRL_SG2042_H
+
+#define PINMUX(pin, mux) \
+	(((pin) & 0xffff) | (((mux) & 0xff) << 16))
+
+#define PIN_LPC_LCLK			0
+#define PIN_LPC_LFRAME			1
+#define PIN_LPC_LAD0			2
+#define PIN_LPC_LAD1			3
+#define PIN_LPC_LAD2			4
+#define PIN_LPC_LAD3			5
+#define PIN_LPC_LDRQ0			6
+#define PIN_LPC_LDRQ1			7
+#define PIN_LPC_SERIRQ			8
+#define PIN_LPC_CLKRUN			9
+#define PIN_LPC_LPME			10
+#define PIN_LPC_LPCPD			11
+#define PIN_LPC_LSMI			12
+#define PIN_PCIE0_L0_RESET		13
+#define PIN_PCIE0_L1_RESET		14
+#define PIN_PCIE0_L0_WAKEUP		15
+#define PIN_PCIE0_L1_WAKEUP		16
+#define PIN_PCIE0_L0_CLKREQ_IN		17
+#define PIN_PCIE0_L1_CLKREQ_IN		18
+#define PIN_PCIE1_L0_RESET		19
+#define PIN_PCIE1_L1_RESET		20
+#define PIN_PCIE1_L0_WAKEUP		21
+#define PIN_PCIE1_L1_WAKEUP		22
+#define PIN_PCIE1_L0_CLKREQ_IN		23
+#define PIN_PCIE1_L1_CLKREQ_IN		24
+#define PIN_SPIF0_CLK_SEL1		25
+#define PIN_SPIF0_CLK_SEL0		26
+#define PIN_SPIF0_WP			27
+#define PIN_SPIF0_HOLD			28
+#define PIN_SPIF0_SDI			29
+#define PIN_SPIF0_CS			30
+#define PIN_SPIF0_SCK			31
+#define PIN_SPIF0_SDO			32
+#define PIN_SPIF1_CLK_SEL1		33
+#define PIN_SPIF1_CLK_SEL0		34
+#define PIN_SPIF1_WP			35
+#define PIN_SPIF1_HOLD			36
+#define PIN_SPIF1_SDI			37
+#define PIN_SPIF1_CS			38
+#define PIN_SPIF1_SCK			39
+#define PIN_SPIF1_SDO			40
+#define PIN_EMMC_WP			41
+#define PIN_EMMC_CD			42
+#define PIN_EMMC_RST			43
+#define PIN_EMMC_PWR_EN			44
+#define PIN_SDIO_CD			45
+#define PIN_SDIO_WP			46
+#define PIN_SDIO_RST			47
+#define PIN_SDIO_PWR_EN			48
+#define PIN_RGMII0_TXD0			49
+#define PIN_RGMII0_TXD1			50
+#define PIN_RGMII0_TXD2			51
+#define PIN_RGMII0_TXD3			52
+#define PIN_RGMII0_TXCTRL		53
+#define PIN_RGMII0_RXD0			54
+#define PIN_RGMII0_RXD1			55
+#define PIN_RGMII0_RXD2			56
+#define PIN_RGMII0_RXD3			57
+#define PIN_RGMII0_RXCTRL		58
+#define PIN_RGMII0_TXC			59
+#define PIN_RGMII0_RXC			60
+#define PIN_RGMII0_REFCLKO		61
+#define PIN_RGMII0_IRQ			62
+#define PIN_RGMII0_MDC			63
+#define PIN_RGMII0_MDIO			64
+#define PIN_PWM0			65
+#define PIN_PWM1			66
+#define PIN_PWM2			67
+#define PIN_PWM3			68
+#define PIN_FAN0			69
+#define PIN_FAN1			70
+#define PIN_FAN2			71
+#define PIN_FAN3			72
+#define PIN_IIC0_SDA			73
+#define PIN_IIC0_SCL			74
+#define PIN_IIC1_SDA			75
+#define PIN_IIC1_SCL			76
+#define PIN_IIC2_SDA			77
+#define PIN_IIC2_SCL			78
+#define PIN_IIC3_SDA			79
+#define PIN_IIC3_SCL			80
+#define PIN_UART0_TX			81
+#define PIN_UART0_RX			82
+#define PIN_UART0_RTS			83
+#define PIN_UART0_CTS			84
+#define PIN_UART1_TX			85
+#define PIN_UART1_RX			86
+#define PIN_UART1_RTS			87
+#define PIN_UART1_CTS			88
+#define PIN_UART2_TX			89
+#define PIN_UART2_RX			90
+#define PIN_UART2_RTS			91
+#define PIN_UART2_CTS			92
+#define PIN_UART3_TX			93
+#define PIN_UART3_RX			94
+#define PIN_UART3_RTS			95
+#define PIN_UART3_CTS			96
+#define PIN_SPI0_CS0			97
+#define PIN_SPI0_CS1			98
+#define PIN_SPI0_SDI			99
+#define PIN_SPI0_SDO			100
+#define PIN_SPI0_SCK			101
+#define PIN_SPI1_CS0			102
+#define PIN_SPI1_CS1			103
+#define PIN_SPI1_SDI			104
+#define PIN_SPI1_SDO			105
+#define PIN_SPI1_SCK			106
+#define PIN_JTAG0_TDO			107
+#define PIN_JTAG0_TCK			108
+#define PIN_JTAG0_TDI			109
+#define PIN_JTAG0_TMS			110
+#define PIN_JTAG0_TRST			111
+#define PIN_JTAG0_SRST			112
+#define PIN_JTAG1_TDO			113
+#define PIN_JTAG1_TCK			114
+#define PIN_JTAG1_TDI			115
+#define PIN_JTAG1_TMS			116
+#define PIN_JTAG1_TRST			117
+#define PIN_JTAG1_SRST			118
+#define PIN_JTAG2_TDO			119
+#define PIN_JTAG2_TCK			120
+#define PIN_JTAG2_TDI			121
+#define PIN_JTAG2_TMS			122
+#define PIN_JTAG2_TRST			123
+#define PIN_JTAG2_SRST			124
+#define PIN_GPIO0			125
+#define PIN_GPIO1			126
+#define PIN_GPIO2			127
+#define PIN_GPIO3			128
+#define PIN_GPIO4			129
+#define PIN_GPIO5			130
+#define PIN_GPIO6			131
+#define PIN_GPIO7			132
+#define PIN_GPIO8			133
+#define PIN_GPIO9			134
+#define PIN_GPIO10			135
+#define PIN_GPIO11			136
+#define PIN_GPIO12			137
+#define PIN_GPIO13			138
+#define PIN_GPIO14			139
+#define PIN_GPIO15			140
+#define PIN_GPIO16			141
+#define PIN_GPIO17			142
+#define PIN_GPIO18			143
+#define PIN_GPIO19			144
+#define PIN_GPIO20			145
+#define PIN_GPIO21			146
+#define PIN_GPIO22			147
+#define PIN_GPIO23			148
+#define PIN_GPIO24			149
+#define PIN_GPIO25			150
+#define PIN_GPIO26			151
+#define PIN_GPIO27			152
+#define PIN_GPIO28			153
+#define PIN_GPIO29			154
+#define PIN_GPIO30			155
+#define PIN_GPIO31			156
+#define PIN_MODE_SEL0			157
+#define PIN_MODE_SEL1			158
+#define PIN_MODE_SEL2			159
+#define PIN_BOOT_SEL0			160
+#define PIN_BOOT_SEL1			161
+#define PIN_BOOT_SEL2			162
+#define PIN_BOOT_SEL3			163
+#define PIN_BOOT_SEL4			164
+#define PIN_BOOT_SEL5			165
+#define PIN_BOOT_SEL6			166
+#define PIN_BOOT_SEL7			167
+#define PIN_MULTI_SCKT			168
+#define PIN_SCKT_ID0			169
+#define PIN_SCKT_ID1			170
+#define PIN_PLL_CLK_IN_MAIN		171
+#define PIN_PLL_CLK_IN_DDR_L		172
+#define PIN_PLL_CLK_IN_DDR_R		173
+#define PIN_XTAL_32K			174
+#define PIN_SYS_RST			175
+#define PIN_PWR_BUTTON			176
+#define PIN_TEST_EN			177
+#define PIN_TEST_MODE_MBIST		178
+#define PIN_TEST_MODE_SCAN		179
+#define PIN_TEST_MODE_BSD		180
+#define PIN_BISR_BYP			181
+
+#endif /* _DT_BINDINGS_PINCTRL_SG2042_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-sg2044.h b/include/dt-bindings/pinctrl/pinctrl-sg2044.h
new file mode 100644
index 00000000000..2a619f681c3
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-sg2044.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_SG2044_H
+#define _DT_BINDINGS_PINCTRL_SG2044_H
+
+#define PINMUX(pin, mux) \
+	(((pin) & 0xffff) | (((mux) & 0xff) << 16))
+
+#define PIN_IIC0_SMBSUS_IN		0
+#define PIN_IIC0_SMBSUS_OUT		1
+#define PIN_IIC0_SMBALERT		2
+#define PIN_IIC1_SMBSUS_IN		3
+#define PIN_IIC1_SMBSUS_OUT		4
+#define PIN_IIC1_SMBALERT		5
+#define PIN_IIC2_SMBSUS_IN		6
+#define PIN_IIC2_SMBSUS_OUT		7
+#define PIN_IIC2_SMBALERT		8
+#define PIN_IIC3_SMBSUS_IN		9
+#define PIN_IIC3_SMBSUS_OUT		10
+#define PIN_IIC3_SMBALERT		11
+#define PIN_PCIE0_L0_RESET		12
+#define PIN_PCIE0_L1_RESET		13
+#define PIN_PCIE0_L0_WAKEUP		14
+#define PIN_PCIE0_L1_WAKEUP		15
+#define PIN_PCIE0_L0_CLKREQ_IN		16
+#define PIN_PCIE0_L1_CLKREQ_IN		17
+#define PIN_PCIE1_L0_RESET		18
+#define PIN_PCIE1_L1_RESET		19
+#define PIN_PCIE1_L0_WAKEUP		20
+#define PIN_PCIE1_L1_WAKEUP		21
+#define PIN_PCIE1_L0_CLKREQ_IN		22
+#define PIN_PCIE1_L1_CLKREQ_IN		23
+#define PIN_PCIE2_L0_RESET		24
+#define PIN_PCIE2_L1_RESET		25
+#define PIN_PCIE2_L0_WAKEUP		26
+#define PIN_PCIE2_L1_WAKEUP		27
+#define PIN_PCIE2_L0_CLKREQ_IN		28
+#define PIN_PCIE2_L1_CLKREQ_IN		29
+#define PIN_PCIE3_L0_RESET		30
+#define PIN_PCIE3_L1_RESET		31
+#define PIN_PCIE3_L0_WAKEUP		32
+#define PIN_PCIE3_L1_WAKEUP		33
+#define PIN_PCIE3_L0_CLKREQ_IN		34
+#define PIN_PCIE3_L1_CLKREQ_IN		35
+#define PIN_PCIE4_L0_RESET		36
+#define PIN_PCIE4_L1_RESET		37
+#define PIN_PCIE4_L0_WAKEUP		38
+#define PIN_PCIE4_L1_WAKEUP		39
+#define PIN_PCIE4_L0_CLKREQ_IN		40
+#define PIN_PCIE4_L1_CLKREQ_IN		41
+#define PIN_SPIF0_CLK_SEL1		42
+#define PIN_SPIF0_CLK_SEL0		43
+#define PIN_SPIF0_WP			44
+#define PIN_SPIF0_HOLD			45
+#define PIN_SPIF0_SDI			46
+#define PIN_SPIF0_CS			47
+#define PIN_SPIF0_SCK			48
+#define PIN_SPIF0_SDO			49
+#define PIN_SPIF1_CLK_SEL1		50
+#define PIN_SPIF1_CLK_SEL0		51
+#define PIN_SPIF1_WP			52
+#define PIN_SPIF1_HOLD			53
+#define PIN_SPIF1_SDI			54
+#define PIN_SPIF1_CS			55
+#define PIN_SPIF1_SCK			56
+#define PIN_SPIF1_SDO			57
+#define PIN_EMMC_WP			58
+#define PIN_EMMC_CD			59
+#define PIN_EMMC_RST			60
+#define PIN_EMMC_PWR_EN			61
+#define PIN_SDIO_CD			62
+#define PIN_SDIO_WP			63
+#define PIN_SDIO_RST			64
+#define PIN_SDIO_PWR_EN			65
+#define PIN_RGMII0_TXD0			66
+#define PIN_RGMII0_TXD1			67
+#define PIN_RGMII0_TXD2			68
+#define PIN_RGMII0_TXD3			69
+#define PIN_RGMII0_TXCTRL		70
+#define PIN_RGMII0_RXD0			71
+#define PIN_RGMII0_RXD1			72
+#define PIN_RGMII0_RXD2			73
+#define PIN_RGMII0_RXD3			74
+#define PIN_RGMII0_RXCTRL		75
+#define PIN_RGMII0_TXC			76
+#define PIN_RGMII0_RXC			77
+#define PIN_RGMII0_REFCLKO		78
+#define PIN_RGMII0_IRQ			79
+#define PIN_RGMII0_MDC			80
+#define PIN_RGMII0_MDIO			81
+#define PIN_PWM0			82
+#define PIN_PWM1			83
+#define PIN_PWM2			84
+#define PIN_PWM3			85
+#define PIN_FAN0			86
+#define PIN_FAN1			87
+#define PIN_FAN2			88
+#define PIN_FAN3			89
+#define PIN_IIC0_SDA			90
+#define PIN_IIC0_SCL			91
+#define PIN_IIC1_SDA			92
+#define PIN_IIC1_SCL			93
+#define PIN_IIC2_SDA			94
+#define PIN_IIC2_SCL			95
+#define PIN_IIC3_SDA			96
+#define PIN_IIC3_SCL			97
+#define PIN_UART0_TX			98
+#define PIN_UART0_RX			99
+#define PIN_UART0_RTS			100
+#define PIN_UART0_CTS			101
+#define PIN_UART1_TX			102
+#define PIN_UART1_RX			103
+#define PIN_UART1_RTS			104
+#define PIN_UART1_CTS			105
+#define PIN_UART2_TX			106
+#define PIN_UART2_RX			107
+#define PIN_UART2_RTS			108
+#define PIN_UART2_CTS			109
+#define PIN_UART3_TX			110
+#define PIN_UART3_RX			111
+#define PIN_UART3_RTS			112
+#define PIN_UART3_CTS			113
+#define PIN_SPI0_CS0			114
+#define PIN_SPI0_CS1			115
+#define PIN_SPI0_SDI			116
+#define PIN_SPI0_SDO			117
+#define PIN_SPI0_SCK			118
+#define PIN_SPI1_CS0			119
+#define PIN_SPI1_CS1			120
+#define PIN_SPI1_SDI			121
+#define PIN_SPI1_SDO			122
+#define PIN_SPI1_SCK			123
+#define PIN_JTAG0_TDO			124
+#define PIN_JTAG0_TCK			125
+#define PIN_JTAG0_TDI			126
+#define PIN_JTAG0_TMS			127
+#define PIN_JTAG0_TRST			128
+#define PIN_JTAG0_SRST			129
+#define PIN_JTAG1_TDO			130
+#define PIN_JTAG1_TCK			131
+#define PIN_JTAG1_TDI			132
+#define PIN_JTAG1_TMS			133
+#define PIN_JTAG1_TRST			134
+#define PIN_JTAG1_SRST			135
+#define PIN_JTAG2_TDO			136
+#define PIN_JTAG2_TCK			137
+#define PIN_JTAG2_TDI			138
+#define PIN_JTAG2_TMS			139
+#define PIN_JTAG2_TRST			140
+#define PIN_JTAG2_SRST			141
+#define PIN_JTAG3_TDO			142
+#define PIN_JTAG3_TCK			143
+#define PIN_JTAG3_TDI			144
+#define PIN_JTAG3_TMS			145
+#define PIN_JTAG3_TRST			146
+#define PIN_JTAG3_SRST			147
+#define PIN_GPIO0			148
+#define PIN_GPIO1			149
+#define PIN_GPIO2			150
+#define PIN_GPIO3			151
+#define PIN_GPIO4			152
+#define PIN_GPIO5			153
+#define PIN_GPIO6			154
+#define PIN_GPIO7			155
+#define PIN_GPIO8			156
+#define PIN_GPIO9			157
+#define PIN_GPIO10			158
+#define PIN_GPIO11			159
+#define PIN_GPIO12			160
+#define PIN_GPIO13			161
+#define PIN_GPIO14			162
+#define PIN_GPIO15			163
+#define PIN_GPIO16			164
+#define PIN_GPIO17			165
+#define PIN_GPIO18			166
+#define PIN_GPIO19			167
+#define PIN_GPIO20			168
+#define PIN_GPIO21			169
+#define PIN_GPIO22			170
+#define PIN_GPIO23			171
+#define PIN_GPIO24			172
+#define PIN_GPIO25			173
+#define PIN_GPIO26			174
+#define PIN_GPIO27			175
+#define PIN_GPIO28			176
+#define PIN_GPIO29			177
+#define PIN_GPIO30			178
+#define PIN_GPIO31			179
+#define PIN_MODE_SEL0			180
+#define PIN_MODE_SEL1			181
+#define PIN_MODE_SEL2			182
+#define PIN_BOOT_SEL0			183
+#define PIN_BOOT_SEL1			184
+#define PIN_BOOT_SEL2			185
+#define PIN_BOOT_SEL3			186
+#define PIN_BOOT_SEL4			187
+#define PIN_BOOT_SEL5			188
+#define PIN_BOOT_SEL6			189
+#define PIN_BOOT_SEL7			190
+#define PIN_MULTI_SCKT			191
+#define PIN_SCKT_ID0			192
+#define PIN_SCKT_ID1			193
+#define PIN_PLL_CLK_IN_MAIN		194
+#define PIN_PLL_CLK_IN_DDR_0		195
+#define PIN_PLL_CLK_IN_DDR_1		196
+#define PIN_PLL_CLK_IN_DDR_2		197
+#define PIN_PLL_CLK_IN_DDR_3		198
+#define PIN_XTAL_32K			199
+#define PIN_SYS_RST			200
+#define PIN_PWR_BUTTON			201
+#define PIN_TEST_EN			202
+#define PIN_TEST_MODE_MBIST		203
+#define PIN_TEST_MODE_SCAN		204
+#define PIN_TEST_MODE_BSD		205
+#define PIN_BISR_BYP			206
+
+#endif /* _DT_BINDINGS_PINCTRL_SG2044_H */
diff --git a/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
new file mode 100644
index 00000000000..b1c18a49061
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_
+#define _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_
+
+#define PD_RISCV		0
+#define PD_NPU			1
+#define PD_VE			2
+
+#endif
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index df599bf4622..d9b7bac3095 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -65,7 +65,7 @@
 #define SM6350_MSS	4
 #define SM6350_MX	5
 
-/* SM6350 Power Domain Indexes */
+/* SM6375 Power Domain Indexes */
 #define SM6375_VDDCX		0
 #define SM6375_VDDCX_AO	1
 #define SM6375_VDDCX_VFL	2
diff --git a/include/dt-bindings/power/thead,th1520-power.h b/include/dt-bindings/power/thead,th1520-power.h
new file mode 100644
index 00000000000..8395bd1459f
--- /dev/null
+++ b/include/dt-bindings/power/thead,th1520-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Alibaba Group Holding Limited.
+ * Copyright (c) 2024 Samsung Electronics Co., Ltd.
+ * Author: Michal Wilczynski <m.wilczynski@samsung.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_TH1520_H
+#define __DT_BINDINGS_POWER_TH1520_H
+
+#define TH1520_AUDIO_PD		0
+#define TH1520_VDEC_PD		1
+#define TH1520_NPU_PD		2
+#define TH1520_VENC_PD		3
+#define TH1520_GPU_PD		4
+#define TH1520_DSP0_PD		5
+#define TH1520_DSP1_PD		6
+
+#endif
diff --git a/include/dt-bindings/reset/imx8mp-reset-audiomix.h b/include/dt-bindings/reset/imx8mp-reset-audiomix.h
new file mode 100644
index 00000000000..746c1337ed9
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mp-reset-audiomix.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef DT_BINDING_RESET_IMX8MP_AUDIOMIX_H
+#define DT_BINDING_RESET_IMX8MP_AUDIOMIX_H
+
+#define IMX8MP_AUDIOMIX_EARC_RESET	0
+#define IMX8MP_AUDIOMIX_EARC_PHY_RESET	1
+#define IMX8MP_AUDIOMIX_DSP_RUNSTALL	2
+
+#endif /* DT_BINDING_RESET_IMX8MP_AUDIOMIX_H */
diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
new file mode 100644
index 00000000000..7f152e98b99
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
+#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
+
+#define EDMA_HW_RESET                   0
+#define NSS_CC_CE_BCR			1
+#define NSS_CC_CLC_BCR			2
+#define NSS_CC_EIP197_BCR		3
+#define NSS_CC_HAQ_BCR			4
+#define NSS_CC_IMEM_BCR			5
+#define NSS_CC_MAC_BCR			6
+#define NSS_CC_PPE_BCR			7
+#define NSS_CC_UBI_BCR			8
+#define NSS_CC_UNIPHY_BCR		9
+#define UBI3_CLKRST_CLAMP_ENABLE	10
+#define UBI3_CORE_CLAMP_ENABLE		11
+#define UBI2_CLKRST_CLAMP_ENABLE	12
+#define UBI2_CORE_CLAMP_ENABLE		13
+#define UBI1_CLKRST_CLAMP_ENABLE	14
+#define UBI1_CORE_CLAMP_ENABLE		15
+#define UBI0_CLKRST_CLAMP_ENABLE	16
+#define UBI0_CORE_CLAMP_ENABLE		17
+#define NSSNOC_NSS_CSR_ARES		18
+#define NSS_CSR_ARES			19
+#define PPE_BTQ_ARES			20
+#define PPE_IPE_ARES			21
+#define PPE_ARES			22
+#define PPE_CFG_ARES			23
+#define PPE_EDMA_ARES			24
+#define PPE_EDMA_CFG_ARES		25
+#define CRY_PPE_ARES			26
+#define NSSNOC_PPE_ARES			27
+#define NSSNOC_PPE_CFG_ARES		28
+#define PORT1_MAC_ARES			29
+#define PORT2_MAC_ARES			30
+#define PORT3_MAC_ARES			31
+#define PORT4_MAC_ARES			32
+#define PORT5_MAC_ARES			33
+#define PORT6_MAC_ARES			34
+#define XGMAC0_PTP_REF_ARES		35
+#define XGMAC1_PTP_REF_ARES		36
+#define XGMAC2_PTP_REF_ARES		37
+#define XGMAC3_PTP_REF_ARES		38
+#define XGMAC4_PTP_REF_ARES		39
+#define XGMAC5_PTP_REF_ARES		40
+#define HAQ_AHB_ARES			41
+#define HAQ_AXI_ARES			42
+#define NSSNOC_HAQ_AHB_ARES		43
+#define NSSNOC_HAQ_AXI_ARES		44
+#define CE_APB_ARES			45
+#define CE_AXI_ARES			46
+#define NSSNOC_CE_APB_ARES		47
+#define NSSNOC_CE_AXI_ARES		48
+#define CRYPTO_ARES			49
+#define NSSNOC_CRYPTO_ARES		50
+#define NSSNOC_NC_AXI0_1_ARES		51
+#define UBI0_CORE_ARES			52
+#define UBI1_CORE_ARES			53
+#define UBI2_CORE_ARES			54
+#define UBI3_CORE_ARES			55
+#define NC_AXI0_ARES			56
+#define UTCM0_ARES			57
+#define NC_AXI1_ARES			58
+#define UTCM1_ARES			59
+#define NC_AXI2_ARES			60
+#define UTCM2_ARES			61
+#define NC_AXI3_ARES			62
+#define UTCM3_ARES			63
+#define NSSNOC_NC_AXI0_ARES		64
+#define AHB0_ARES			65
+#define INTR0_AHB_ARES			66
+#define AHB1_ARES			67
+#define INTR1_AHB_ARES			68
+#define AHB2_ARES			69
+#define INTR2_AHB_ARES			70
+#define AHB3_ARES			71
+#define INTR3_AHB_ARES			72
+#define NSSNOC_AHB0_ARES		73
+#define NSSNOC_INT0_AHB_ARES		74
+#define AXI0_ARES			75
+#define AXI1_ARES			76
+#define AXI2_ARES			77
+#define AXI3_ARES			78
+#define NSSNOC_AXI0_ARES		79
+#define IMEM_QSB_ARES			80
+#define NSSNOC_IMEM_QSB_ARES		81
+#define IMEM_AHB_ARES			82
+#define NSSNOC_IMEM_AHB_ARES		83
+#define UNIPHY_PORT1_RX_ARES		84
+#define UNIPHY_PORT1_TX_ARES		85
+#define UNIPHY_PORT2_RX_ARES		86
+#define UNIPHY_PORT2_TX_ARES		87
+#define UNIPHY_PORT3_RX_ARES		88
+#define UNIPHY_PORT3_TX_ARES		89
+#define UNIPHY_PORT4_RX_ARES		90
+#define UNIPHY_PORT4_TX_ARES		91
+#define UNIPHY_PORT5_RX_ARES		92
+#define UNIPHY_PORT5_TX_ARES		93
+#define UNIPHY_PORT6_RX_ARES		94
+#define UNIPHY_PORT6_TX_ARES		95
+#define PORT1_RX_ARES			96
+#define PORT1_TX_ARES			97
+#define PORT2_RX_ARES			98
+#define PORT2_TX_ARES			99
+#define PORT3_RX_ARES			100
+#define PORT3_TX_ARES			101
+#define PORT4_RX_ARES			102
+#define PORT4_TX_ARES			103
+#define PORT5_RX_ARES			104
+#define PORT5_TX_ARES			105
+#define PORT6_RX_ARES			106
+#define PORT6_TX_ARES			107
+#define PPE_FULL_RESET			108
+#define UNIPHY0_SOFT_RESET		109
+#define UNIPHY1_SOFT_RESET		110
+#define UNIPHY2_SOFT_RESET		111
+#define UNIPHY_PORT1_ARES		112
+#define UNIPHY_PORT2_ARES		113
+#define UNIPHY_PORT3_ARES		114
+#define UNIPHY_PORT4_ARES		115
+#define UNIPHY_PORT5_ARES		116
+#define UNIPHY_PORT6_ARES		117
+#define NSSPORT1_RESET			118
+#define NSSPORT2_RESET			119
+#define NSSPORT3_RESET			120
+#define NSSPORT4_RESET			121
+#define NSSPORT5_RESET			122
+#define NSSPORT6_RESET			123
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h
new file mode 100644
index 00000000000..6b024c5f2e1
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_NL2		8
+#define SRST_CORE_BIU		9
+#define SRST_CORE_CRYPTO	10
+#define SRST_P_DBG		11
+#define SRST_POT_DBG		12
+#define SRST_NT_DBG		13
+#define SRST_P_CORE_GRF		14
+#define SRST_P_DAPLITE_BIU	15
+#define SRST_P_CPU_BIU		16
+#define SRST_REF_PVTPLL_CORE	17
+#define SRST_A_BUS_VOPGL_BIU	18
+#define SRST_A_BUS_H_BIU	19
+#define SRST_A_SYSMEM_BIU	20
+#define SRST_A_BUS_BIU		21
+#define SRST_H_BUS_BIU		22
+#define SRST_P_BUS_BIU		23
+#define SRST_P_DFT2APB		24
+#define SRST_P_BUS_GRF		25
+#define SRST_A_BUS_M_BIU	26
+#define SRST_A_GIC		27
+#define SRST_A_SPINLOCK		28
+#define SRST_A_DMAC		29
+#define SRST_P_TIMER		30
+#define SRST_TIMER0		31
+#define SRST_TIMER1		32
+#define SRST_TIMER2		33
+#define SRST_TIMER3		34
+#define SRST_TIMER4		35
+#define SRST_TIMER5		36
+#define SRST_P_JDBCK_DAP	37
+#define SRST_JDBCK_DAP		38
+#define SRST_P_WDT_NS		39
+#define SRST_T_WDT_NS		40
+#define SRST_H_TRNG_NS		41
+#define SRST_P_UART0		42
+#define SRST_S_UART0		43
+#define SRST_PKA_CRYPTO		44
+#define SRST_A_CRYPTO		45
+#define SRST_H_CRYPTO		46
+#define SRST_P_DMA2DDR		47
+#define SRST_A_DMA2DDR		48
+#define SRST_P_PWM0		49
+#define SRST_PWM0		50
+#define SRST_P_PWM1		51
+#define SRST_PWM1		52
+#define SRST_P_SCR		53
+#define SRST_A_DCF		54
+#define SRST_P_INTMUX		55
+#define SRST_A_VPU_BIU		56
+#define SRST_H_VPU_BIU		57
+#define SRST_P_VPU_BIU		58
+#define SRST_A_VPU		59
+#define SRST_H_VPU		60
+#define SRST_P_CRU_PCIE		61
+#define SRST_P_VPU_GRF		62
+#define SRST_H_SFC		63
+#define SRST_S_SFC		64
+#define SRST_C_EMMC		65
+#define SRST_H_EMMC		66
+#define SRST_A_EMMC		67
+#define SRST_B_EMMC		68
+#define SRST_T_EMMC		69
+#define SRST_P_GPIO1		70
+#define SRST_DB_GPIO1		71
+#define SRST_A_VPU_L_BIU	72
+#define SRST_P_VPU_IOC		73
+#define SRST_H_SAI_I2S0		74
+#define SRST_M_SAI_I2S0		75
+#define SRST_H_SAI_I2S2		76
+#define SRST_M_SAI_I2S2		77
+#define SRST_P_ACODEC		78
+#define SRST_P_GPIO3		79
+#define SRST_DB_GPIO3		80
+#define SRST_P_SPI1		81
+#define SRST_SPI1		82
+#define SRST_P_UART2		83
+#define SRST_S_UART2		84
+#define SRST_P_UART5		85
+#define SRST_S_UART5		86
+#define SRST_P_UART6		87
+#define SRST_S_UART6		88
+#define SRST_P_UART7		89
+#define SRST_S_UART7		90
+#define SRST_P_I2C3		91
+#define SRST_I2C3		92
+#define SRST_P_I2C5		93
+#define SRST_I2C5		94
+#define SRST_P_I2C6		95
+#define SRST_I2C6		96
+#define SRST_A_MAC		97
+#define SRST_P_PCIE		98
+#define SRST_PCIE_PIPE_PHY	99
+#define SRST_PCIE_POWER_UP	100
+#define SRST_P_PCIE_PHY		101
+#define SRST_P_PIPE_GRF		102
+#define SRST_H_SDIO0		103
+#define SRST_H_SDIO1		104
+#define SRST_TS_0		105
+#define SRST_TS_1		106
+#define SRST_P_CAN2		107
+#define SRST_CAN2		108
+#define SRST_P_CAN3		109
+#define SRST_CAN3		110
+#define SRST_P_SARADC		111
+#define SRST_SARADC		112
+#define SRST_SARADC_PHY		113
+#define SRST_P_TSADC		114
+#define SRST_TSADC		115
+#define SRST_A_USB3OTG		116
+#define SRST_A_GPU_BIU		117
+#define SRST_P_GPU_BIU		118
+#define SRST_A_GPU		119
+#define SRST_REF_PVTPLL_GPU	120
+#define SRST_H_RKVENC_BIU	121
+#define SRST_A_RKVENC_BIU	122
+#define SRST_P_RKVENC_BIU	123
+#define SRST_H_RKVENC		124
+#define SRST_A_RKVENC		125
+#define SRST_CORE_RKVENC	126
+#define SRST_H_SAI_I2S1		127
+#define SRST_M_SAI_I2S1		128
+#define SRST_P_I2C1		129
+#define SRST_I2C1		130
+#define SRST_P_I2C0		131
+#define SRST_I2C0		132
+#define SRST_P_SPI0		133
+#define SRST_SPI0		134
+#define SRST_P_GPIO4		135
+#define SRST_DB_GPIO4		136
+#define SRST_P_RKVENC_IOC	137
+#define SRST_H_SPDIF		138
+#define SRST_M_SPDIF		139
+#define SRST_H_PDM		140
+#define SRST_M_PDM		141
+#define SRST_P_UART1		142
+#define SRST_S_UART1		143
+#define SRST_P_UART3		144
+#define SRST_S_UART3		145
+#define SRST_P_RKVENC_GRF	146
+#define SRST_P_CAN0		147
+#define SRST_CAN0		148
+#define SRST_P_CAN1		149
+#define SRST_CAN1		150
+#define SRST_A_VO_BIU		151
+#define SRST_H_VO_BIU		152
+#define SRST_P_VO_BIU		153
+#define SRST_H_RGA2E		154
+#define SRST_A_RGA2E		155
+#define SRST_CORE_RGA2E		156
+#define SRST_H_VDPP		157
+#define SRST_A_VDPP		158
+#define SRST_CORE_VDPP		159
+#define SRST_P_VO_GRF		160
+#define SRST_P_CRU		161
+#define SRST_A_VOP_BIU		162
+#define SRST_H_VOP		163
+#define SRST_D_VOP0		164
+#define SRST_D_VOP1		165
+#define SRST_A_VOP		166
+#define SRST_P_HDMI		167
+#define SRST_HDMI		168
+#define SRST_P_HDMIPHY		169
+#define SRST_H_HDCP_KEY		170
+#define SRST_A_HDCP		171
+#define SRST_H_HDCP		172
+#define SRST_P_HDCP		173
+#define SRST_H_CVBS		174
+#define SRST_D_CVBS_VOP		175
+#define SRST_D_4X_CVBS_VOP	176
+#define SRST_A_JPEG_DECODER	177
+#define SRST_H_JPEG_DECODER	178
+#define SRST_A_VO_L_BIU		179
+#define SRST_A_MAC_VO		180
+#define SRST_A_JPEG_BIU		181
+#define SRST_H_SAI_I2S3		182
+#define SRST_M_SAI_I2S3		183
+#define SRST_MACPHY		184
+#define SRST_P_VCDCPHY		185
+#define SRST_P_GPIO2		186
+#define SRST_DB_GPIO2		187
+#define SRST_P_VO_IOC		188
+#define SRST_H_SDMMC0		189
+#define SRST_P_OTPC_NS		190
+#define SRST_SBPI_OTPC_NS	191
+#define SRST_USER_OTPC_NS	192
+#define SRST_HDMIHDP0		193
+#define SRST_H_USBHOST		194
+#define SRST_H_USBHOST_ARB	195
+#define SRST_HOST_UTMI		196
+#define SRST_P_UART4		197
+#define SRST_S_UART4		198
+#define SRST_P_I2C4		199
+#define SRST_I2C4		200
+#define SRST_P_I2C7		201
+#define SRST_I2C7		202
+#define SRST_P_USBPHY		203
+#define SRST_USBPHY_POR		204
+#define SRST_USBPHY_OTG		205
+#define SRST_USBPHY_HOST	206
+#define SRST_P_DDRPHY_CRU	207
+#define SRST_H_RKVDEC_BIU	208
+#define SRST_A_RKVDEC_BIU	209
+#define SRST_A_RKVDEC		210
+#define SRST_H_RKVDEC		211
+#define SRST_HEVC_CA_RKVDEC	212
+#define SRST_REF_PVTPLL_RKVDEC	213
+#define SRST_P_DDR_BIU		214
+#define SRST_P_DDRC		215
+#define SRST_P_DDRMON		216
+#define SRST_TIMER_DDRMON	217
+#define SRST_P_MSCH_BIU		218
+#define SRST_P_DDR_GRF		219
+#define SRST_P_DDR_HWLP		220
+#define SRST_P_DDRPHY		221
+#define SRST_MSCH_BIU		222
+#define SRST_A_DDR_UPCTL	223
+#define SRST_DDR_UPCTL		224
+#define SRST_DDRMON		225
+#define SRST_A_DDR_SCRAMBLE	226
+#define SRST_A_SPLIT		227
+#define SRST_DDR_PHY		228
+
+#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h
new file mode 100644
index 00000000000..8df95113056
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3562-cru.h
@@ -0,0 +1,358 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
+
+/********Name=SOFTRST_CON01,Offset=0x404********/
+#define SRST_A_TOP_BIU			0
+#define SRST_A_TOP_VIO_BIU		1
+#define SRST_REF_PVTPLL_LOGIC		2
+/********Name=SOFTRST_CON03,Offset=0x40C********/
+#define SRST_NCOREPORESET0		3
+#define SRST_NCOREPORESET1		4
+#define SRST_NCOREPORESET2		5
+#define SRST_NCOREPORESET3		6
+#define SRST_NCORESET0			7
+#define SRST_NCORESET1			8
+#define SRST_NCORESET2			9
+#define SRST_NCORESET3			10
+#define SRST_NL2RESET			11
+/********Name=SOFTRST_CON04,Offset=0x410********/
+#define SRST_DAP			12
+#define SRST_P_DBG_DAPLITE		13
+#define SRST_REF_PVTPLL_CORE		14
+/********Name=SOFTRST_CON05,Offset=0x414********/
+#define SRST_A_CORE_BIU			15
+#define SRST_P_CORE_BIU			16
+#define SRST_H_CORE_BIU			17
+/********Name=SOFTRST_CON06,Offset=0x418********/
+#define SRST_A_NPU_BIU			18
+#define SRST_H_NPU_BIU			19
+#define SRST_A_RKNN			20
+#define SRST_H_RKNN			21
+#define SRST_REF_PVTPLL_NPU		22
+/********Name=SOFTRST_CON08,Offset=0x420********/
+#define SRST_A_GPU_BIU			23
+#define SRST_GPU			24
+#define SRST_REF_PVTPLL_GPU		25
+#define SRST_GPU_BRG_BIU		26
+/********Name=SOFTRST_CON09,Offset=0x424********/
+#define SRST_RKVENC_CORE		27
+#define SRST_A_VEPU_BIU			28
+#define SRST_H_VEPU_BIU			29
+#define SRST_A_RKVENC			30
+#define SRST_H_RKVENC			31
+/********Name=SOFTRST_CON10,Offset=0x428********/
+#define SRST_RKVDEC_HEVC_CA		32
+#define SRST_A_VDPU_BIU			33
+#define SRST_H_VDPU_BIU			34
+#define SRST_A_RKVDEC			35
+#define SRST_H_RKVDEC			36
+/********Name=SOFTRST_CON11,Offset=0x42C********/
+#define SRST_A_VI_BIU			37
+#define SRST_H_VI_BIU			38
+#define SRST_P_VI_BIU			39
+#define SRST_ISP			40
+#define SRST_A_VICAP			41
+#define SRST_H_VICAP			42
+#define SRST_D_VICAP			43
+#define SRST_I0_VICAP			44
+#define SRST_I1_VICAP			45
+#define SRST_I2_VICAP			46
+#define SRST_I3_VICAP			47
+/********Name=SOFTRST_CON12,Offset=0x430********/
+#define SRST_P_CSIHOST0			48
+#define SRST_P_CSIHOST1			49
+#define SRST_P_CSIHOST2			50
+#define SRST_P_CSIHOST3			51
+#define SRST_P_CSIPHY0			52
+#define SRST_P_CSIPHY1			53
+/********Name=SOFTRST_CON13,Offset=0x434********/
+#define SRST_A_VO_BIU			54
+#define SRST_H_VO_BIU			55
+#define SRST_A_VOP			56
+#define SRST_H_VOP			57
+#define SRST_D_VOP			58
+#define SRST_D_VOP1			59
+/********Name=SOFTRST_CON14,Offset=0x438********/
+#define SRST_A_RGA_BIU			60
+#define SRST_H_RGA_BIU			61
+#define SRST_A_RGA			62
+#define SRST_H_RGA			63
+#define SRST_RGA_CORE			64
+#define SRST_A_JDEC			65
+#define SRST_H_JDEC			66
+/********Name=SOFTRST_CON15,Offset=0x43C********/
+#define SRST_B_EBK_BIU			67
+#define SRST_P_EBK_BIU			68
+#define SRST_AHB2AXI_EBC		69
+#define SRST_H_EBC			70
+#define SRST_D_EBC			71
+#define SRST_H_EINK			72
+#define SRST_P_EINK			73
+/********Name=SOFTRST_CON16,Offset=0x440********/
+#define SRST_P_PHP_BIU			74
+#define SRST_A_PHP_BIU			75
+#define SRST_P_PCIE20			76
+#define SRST_PCIE20_POWERUP		77
+#define SRST_USB3OTG			78
+/********Name=SOFTRST_CON17,Offset=0x444********/
+#define SRST_PIPEPHY			79
+/********Name=SOFTRST_CON18,Offset=0x448********/
+#define SRST_A_BUS_BIU			80
+#define SRST_H_BUS_BIU			81
+#define SRST_P_BUS_BIU			82
+/********Name=SOFTRST_CON19,Offset=0x44C********/
+#define SRST_P_I2C1			83
+#define SRST_P_I2C2			84
+#define SRST_P_I2C3			85
+#define SRST_P_I2C4			86
+#define SRST_P_I2C5			87
+#define SRST_I2C1			88
+#define SRST_I2C2			89
+#define SRST_I2C3			90
+#define SRST_I2C4			91
+#define SRST_I2C5			92
+/********Name=SOFTRST_CON20,Offset=0x450********/
+#define SRST_BUS_GPIO3			93
+#define SRST_BUS_GPIO4			94
+/********Name=SOFTRST_CON21,Offset=0x454********/
+#define SRST_P_TIMER			95
+#define SRST_TIMER0			96
+#define SRST_TIMER1			97
+#define SRST_TIMER2			98
+#define SRST_TIMER3			99
+#define SRST_TIMER4			100
+#define SRST_TIMER5			101
+#define SRST_P_STIMER			102
+#define SRST_STIMER0			103
+#define SRST_STIMER1			104
+/********Name=SOFTRST_CON22,Offset=0x458********/
+#define SRST_P_WDTNS			105
+#define SRST_WDTNS			106
+#define SRST_P_GRF			107
+#define SRST_P_SGRF			108
+#define SRST_P_MAILBOX			109
+#define SRST_P_INTC			110
+#define SRST_A_BUS_GIC400		111
+#define SRST_A_BUS_GIC400_DEBUG		112
+/********Name=SOFTRST_CON23,Offset=0x45C********/
+#define SRST_A_BUS_SPINLOCK		113
+#define SRST_A_DCF			114
+#define SRST_P_DCF			115
+#define SRST_F_BUS_CM0_CORE		116
+#define SRST_T_BUS_CM0_JTAG		117
+#define SRST_H_ICACHE			118
+#define SRST_H_DCACHE			119
+/********Name=SOFTRST_CON24,Offset=0x460********/
+#define SRST_P_TSADC			120
+#define SRST_TSADC			121
+#define SRST_TSADCPHY			122
+#define SRST_P_DFT2APB			123
+/********Name=SOFTRST_CON25,Offset=0x464********/
+#define SRST_A_GMAC			124
+#define SRST_P_APB2ASB_VCCIO156		125
+#define SRST_P_DSIPHY			126
+#define SRST_P_DSITX			127
+#define SRST_P_CPU_EMA_DET		128
+#define SRST_P_HASH			129
+#define SRST_P_TOPCRU			130
+/********Name=SOFTRST_CON26,Offset=0x468********/
+#define SRST_P_ASB2APB_VCCIO156		131
+#define SRST_P_IOC_VCCIO156		132
+#define SRST_P_GPIO3_VCCIO156		133
+#define SRST_P_GPIO4_VCCIO156		134
+#define SRST_P_SARADC_VCCIO156		135
+#define SRST_SARADC_VCCIO156		136
+#define SRST_SARADC_VCCIO156_PHY	137
+/********Name=SOFTRST_CON27,Offset=0x46c********/
+#define SRST_A_MAC100			138
+
+/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
+#define SRST_P_PMU0_CRU			139
+#define SRST_P_PMU0_PMU			140
+#define SRST_PMU0_PMU			141
+#define SRST_P_PMU0_HP_TIMER		142
+#define SRST_PMU0_HP_TIMER		143
+#define SRST_PMU0_32K_HP_TIMER		144
+#define SRST_P_PMU0_PVTM		145
+#define SRST_PMU0_PVTM			146
+#define SRST_P_IOC_PMUIO		147
+#define SRST_P_PMU0_GPIO0		148
+#define SRST_PMU0_GPIO0			149
+#define SRST_P_PMU0_GRF			150
+#define SRST_P_PMU0_SGRF		151
+/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
+#define SRST_DDR_FAIL_SAFE		152
+#define SRST_P_PMU0_SCRKEYGEN		153
+/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
+#define SRST_P_PMU0_I2C0		154
+#define SRST_PMU0_I2C0			155
+
+/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
+#define SRST_P_PMU1_CRU			156
+#define SRST_H_PMU1_MEM			157
+#define SRST_H_PMU1_BIU			158
+#define SRST_P_PMU1_BIU			159
+#define SRST_P_PMU1_UART0		160
+#define SRST_S_PMU1_UART0		161
+/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
+#define SRST_P_PMU1_SPI0		162
+#define SRST_PMU1_SPI0			163
+#define SRST_P_PMU1_PWM0		164
+#define SRST_PMU1_PWM0			165
+/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
+#define SRST_F_PMU1_CM0_CORE		166
+#define SRST_T_PMU1_CM0_JTAG		167
+#define SRST_P_PMU1_WDTNS		168
+#define SRST_PMU1_WDTNS			169
+#define SRST_PMU1_MAILBOX		170
+
+/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
+#define SRST_MSCH_BRG_BIU		171
+#define SRST_P_MSCH_BIU			172
+#define SRST_P_DDR_HWLP			173
+#define SRST_P_DDR_PHY			290
+#define SRST_P_DDR_DFICTL		174
+#define SRST_P_DDR_DMA2DDR		175
+/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
+#define SRST_P_DDR_MON			176
+#define SRST_TM_DDR_MON			177
+#define SRST_P_DDR_GRF			178
+#define SRST_P_DDR_CRU			179
+#define SRST_P_SUBDDR_CRU		180
+
+/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
+#define SRST_MSCH_BIU			181
+#define SRST_DDR_PHY			182
+#define SRST_DDR_DFICTL			183
+#define SRST_DDR_SCRAMBLE		184
+#define SRST_DDR_MON			185
+#define SRST_A_DDR_SPLIT		186
+#define SRST_DDR_DMA2DDR		187
+
+/********Name=PERISOFTRST_CON01,Offset=0x30404********/
+#define SRST_A_PERI_BIU			188
+#define SRST_H_PERI_BIU			189
+#define SRST_P_PERI_BIU			190
+#define SRST_P_PERICRU			191
+/********Name=PERISOFTRST_CON02,Offset=0x30408********/
+#define SRST_H_SAI0_8CH			192
+#define SRST_M_SAI0_8CH			193
+#define SRST_H_SAI1_8CH			194
+#define SRST_M_SAI1_8CH			195
+#define SRST_H_SAI2_2CH			196
+#define SRST_M_SAI2_2CH			197
+/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
+#define SRST_H_DSM			198
+#define SRST_DSM			199
+#define SRST_H_PDM			200
+#define SRST_M_PDM			201
+#define SRST_H_SPDIF			202
+#define SRST_M_SPDIF			203
+/********Name=PERISOFTRST_CON04,Offset=0x30410********/
+#define SRST_H_SDMMC0			204
+#define SRST_H_SDMMC1			205
+#define SRST_H_EMMC			206
+#define SRST_A_EMMC			207
+#define SRST_C_EMMC			208
+#define SRST_B_EMMC			209
+#define SRST_T_EMMC			210
+#define SRST_S_SFC			211
+#define SRST_H_SFC			212
+/********Name=PERISOFTRST_CON05,Offset=0x30414********/
+#define SRST_H_USB2HOST			213
+#define SRST_H_USB2HOST_ARB		214
+#define SRST_USB2HOST_UTMI		215
+/********Name=PERISOFTRST_CON06,Offset=0x30418********/
+#define SRST_P_SPI1			216
+#define SRST_SPI1			217
+#define SRST_P_SPI2			218
+#define SRST_SPI2			219
+/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
+#define SRST_P_UART1			220
+#define SRST_P_UART2			221
+#define SRST_P_UART3			222
+#define SRST_P_UART4			223
+#define SRST_P_UART5			224
+#define SRST_P_UART6			225
+#define SRST_P_UART7			226
+#define SRST_P_UART8			227
+#define SRST_P_UART9			228
+#define SRST_S_UART1			229
+#define SRST_S_UART2			230
+/********Name=PERISOFTRST_CON08,Offset=0x30420********/
+#define SRST_S_UART3			231
+#define SRST_S_UART4			232
+#define SRST_S_UART5			233
+#define SRST_S_UART6			234
+#define SRST_S_UART7			235
+/********Name=PERISOFTRST_CON09,Offset=0x30424********/
+#define SRST_S_UART8			236
+#define SRST_S_UART9			237
+/********Name=PERISOFTRST_CON10,Offset=0x30428********/
+#define SRST_P_PWM1_PERI		238
+#define SRST_PWM1_PERI			239
+#define SRST_P_PWM2_PERI		240
+#define SRST_PWM2_PERI			241
+#define SRST_P_PWM3_PERI		242
+#define SRST_PWM3_PERI			243
+/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
+#define SRST_P_CAN0			244
+#define SRST_CAN0			245
+#define SRST_P_CAN1			246
+#define SRST_CAN1			247
+/********Name=PERISOFTRST_CON12,Offset=0x30430********/
+#define SRST_A_CRYPTO			248
+#define SRST_H_CRYPTO			249
+#define SRST_P_CRYPTO			250
+#define SRST_CORE_CRYPTO		251
+#define SRST_PKA_CRYPTO			252
+#define SRST_H_KLAD			253
+#define SRST_P_KEY_READER		254
+#define SRST_H_RK_RNG_NS		255
+#define SRST_H_RK_RNG_S			256
+#define SRST_H_TRNG_NS			257
+#define SRST_H_TRNG_S			258
+#define SRST_H_CRYPTO_S			259
+/********Name=PERISOFTRST_CON13,Offset=0x30434********/
+#define SRST_P_PERI_WDT			260
+#define SRST_T_PERI_WDT			261
+#define SRST_A_SYSMEM			262
+#define SRST_H_BOOTROM			263
+#define SRST_P_PERI_GRF			264
+#define SRST_A_DMAC			265
+#define SRST_A_RKDMAC			267
+/********Name=PERISOFTRST_CON14,Offset=0x30438********/
+#define SRST_P_OTPC_NS			268
+#define SRST_SBPI_OTPC_NS		269
+#define SRST_USER_OTPC_NS		270
+#define SRST_P_OTPC_S			271
+#define SRST_SBPI_OTPC_S		272
+#define SRST_USER_OTPC_S		273
+#define SRST_OTPC_ARB			274
+#define SRST_P_OTPPHY			275
+#define SRST_OTP_NPOR			276
+/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
+#define SRST_P_USB2PHY			277
+#define SRST_USB2PHY_POR		278
+#define SRST_USB2PHY_OTG		279
+#define SRST_USB2PHY_HOST		280
+#define SRST_P_PIPEPHY			281
+/********Name=PERISOFTRST_CON16,Offset=0x30440********/
+#define SRST_P_SARADC			282
+#define SRST_SARADC			283
+#define SRST_SARADC_PHY			284
+#define SRST_P_IOC_VCCIO234		285
+/********Name=PERISOFTRST_CON17,Offset=0x30444********/
+#define SRST_P_PERI_GPIO1		286
+#define SRST_P_PERI_GPIO2		287
+#define SRST_PERI_GPIO1			288
+#define SRST_PERI_GPIO2			289
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h
index e2fe4bd5f7f..878beae6dc3 100644
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
 /*
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd.
  * Copyright (c) 2022 Collabora Ltd.
  *
  * Author: Elaine Zhang <zhangqing@rock-chips.com>
@@ -753,4 +753,43 @@
 
 #define SRST_A_HDMIRX_BIU		660
 
+/* SCMI Secure Resets */
+
+/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */
+#define SCMI_SRST_A_SECURE_NS_BIU	10
+#define SCMI_SRST_H_SECURE_NS_BIU	11
+#define SCMI_SRST_A_SECURE_S_BIU	12
+#define SCMI_SRST_H_SECURE_S_BIU	13
+#define SCMI_SRST_P_SECURE_S_BIU	14
+#define SCMI_SRST_CRYPTO_CORE		15
+/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */
+#define SCMI_SRST_CRYPTO_PKA		16
+#define SCMI_SRST_CRYPTO_RNG		17
+#define SCMI_SRST_A_CRYPTO		18
+#define SCMI_SRST_H_CRYPTO		19
+#define SCMI_SRST_KEYLADDER_CORE	25
+#define SCMI_SRST_KEYLADDER_RNG		26
+#define SCMI_SRST_A_KEYLADDER		27
+#define SCMI_SRST_H_KEYLADDER		28
+#define SCMI_SRST_P_OTPC_S		29
+#define SCMI_SRST_OTPC_S		30
+#define SCMI_SRST_WDT_S			31
+/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */
+#define SCMI_SRST_T_WDT_S		32
+#define SCMI_SRST_H_BOOTROM		33
+#define SCMI_SRST_A_DCF			34
+#define SCMI_SRST_P_DCF			35
+#define SCMI_SRST_H_BOOTROM_NS		37
+#define SCMI_SRST_P_KEYLADDER		46
+#define SCMI_SRST_H_TRNG_S		47
+/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */
+#define SCMI_SRST_H_TRNG_NS		48
+#define SCMI_SRST_D_SDMMC_BUFFER	49
+#define SCMI_SRST_H_SDMMC		50
+#define SCMI_SRST_H_SDMMC_BUFFER	51
+#define SCMI_SRST_SDMMC			52
+#define SCMI_SRST_P_TRNG_CHK		53
+#define SCMI_SRST_TRNG_S		54
+
+
 #endif
diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
index ed177c04afd..81b1eba2a7f 100644
--- a/include/dt-bindings/reset/sun50i-h616-ccu.h
+++ b/include/dt-bindings/reset/sun50i-h616-ccu.h
@@ -67,5 +67,7 @@
 #define RST_BUS_HDCP		58
 #define RST_BUS_KEYADC		59
 #define RST_BUS_GPADC		60
+#define RST_BUS_TCON_LCD0	61
+#define RST_BUS_TCON_LCD1	62
 
 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
diff --git a/include/dt-bindings/reset/sun55i-a523-ccu.h b/include/dt-bindings/reset/sun55i-a523-ccu.h
new file mode 100644
index 00000000000..70df503f34f
--- /dev/null
+++ b/include/dt-bindings/reset/sun55i-a523-ccu.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Arm Ltd.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
+#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
+
+#define RST_MBUS		0
+#define RST_BUS_NSI		1
+#define RST_BUS_DE		2
+#define RST_BUS_DI		3
+#define RST_BUS_G2D		4
+#define RST_BUS_SYS		5
+#define RST_BUS_GPU		6
+#define RST_BUS_CE		7
+#define RST_BUS_SYS_CE		8
+#define RST_BUS_VE		9
+#define RST_BUS_DMA		10
+#define RST_BUS_MSGBOX		11
+#define RST_BUS_SPINLOCK	12
+#define RST_BUS_CPUXTIMER	13
+#define RST_BUS_DBG		14
+#define RST_BUS_PWM0		15
+#define RST_BUS_PWM1		16
+#define RST_BUS_DRAM		17
+#define RST_BUS_NAND		18
+#define RST_BUS_MMC0		19
+#define RST_BUS_MMC1		20
+#define RST_BUS_MMC2		21
+#define RST_BUS_SYSDAP		22
+#define RST_BUS_UART0		23
+#define RST_BUS_UART1		24
+#define RST_BUS_UART2		25
+#define RST_BUS_UART3		26
+#define RST_BUS_UART4		27
+#define RST_BUS_UART5		28
+#define RST_BUS_UART6		29
+#define RST_BUS_UART7		30
+#define RST_BUS_I2C0		31
+#define RST_BUS_I2C1		32
+#define RST_BUS_I2C2		33
+#define RST_BUS_I2C3		34
+#define RST_BUS_I2C4		35
+#define RST_BUS_I2C5		36
+#define RST_BUS_CAN		37
+#define RST_BUS_SPI0		38
+#define RST_BUS_SPI1		39
+#define RST_BUS_SPI2		40
+#define RST_BUS_SPIFC		41
+#define RST_BUS_EMAC0		42
+#define RST_BUS_EMAC1		43
+#define RST_BUS_IR_RX		44
+#define RST_BUS_IR_TX		45
+#define RST_BUS_GPADC0		46
+#define RST_BUS_GPADC1		47
+#define RST_BUS_THS		48
+#define RST_USB_PHY0		49
+#define RST_USB_PHY1		50
+#define RST_BUS_OHCI0		51
+#define RST_BUS_OHCI1		52
+#define RST_BUS_EHCI0		53
+#define RST_BUS_EHCI1		54
+#define RST_BUS_OTG		55
+#define RST_BUS_3		56
+#define RST_BUS_LRADC		57
+#define RST_BUS_PCIE_USB3	58
+#define RST_BUS_DISPLAY0_TOP	59
+#define RST_BUS_DISPLAY1_TOP	60
+#define RST_BUS_HDMI_MAIN	61
+#define RST_BUS_HDMI_SUB	62
+#define RST_BUS_MIPI_DSI0	63
+#define RST_BUS_MIPI_DSI1	64
+#define RST_BUS_TCON_LCD0	65
+#define RST_BUS_TCON_LCD1	66
+#define RST_BUS_TCON_LCD2	67
+#define RST_BUS_TCON_TV0	68
+#define RST_BUS_TCON_TV1	69
+#define RST_BUS_LVDS0		70
+#define RST_BUS_LVDS1		71
+#define RST_BUS_EDP		72
+#define RST_BUS_VIDEO_OUT0	73
+#define RST_BUS_VIDEO_OUT1	74
+#define RST_BUS_LEDC		75
+#define RST_BUS_CSI		76
+#define RST_BUS_ISP		77
+
+#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h
new file mode 100644
index 00000000000..dd6fbb372e1
--- /dev/null
+++ b/include/dt-bindings/reset/sun55i-a523-r-ccu.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_
+
+#define RST_BUS_R_TIMER		0
+#define RST_BUS_R_TWD		1
+#define RST_BUS_R_PWMCTRL	2
+#define RST_BUS_R_SPI		3
+#define RST_BUS_R_SPINLOCK	4
+#define RST_BUS_R_MSGBOX	5
+#define RST_BUS_R_UART0		6
+#define RST_BUS_R_UART1		7
+#define RST_BUS_R_I2C0		8
+#define RST_BUS_R_I2C1		9
+#define RST_BUS_R_I2C2		10
+#define RST_BUS_R_PPU1		11
+#define RST_BUS_R_IR_RX		12
+#define RST_BUS_R_RTC		13
+#define RST_BUS_R_CPUCFG	14
+
+#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */
diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h
index a01af169d24..b46de214dd0 100644
--- a/include/dt-bindings/soc/samsung,exynos-usi.h
+++ b/include/dt-bindings/soc/samsung,exynos-usi.h
@@ -9,9 +9,18 @@
 #ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
 #define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
 
-#define USI_V2_NONE		0
-#define USI_V2_UART		1
-#define USI_V2_SPI		2
-#define USI_V2_I2C		3
+#define USI_MODE_NONE		0
+#define USI_MODE_UART		1
+#define USI_MODE_SPI		2
+#define USI_MODE_I2C		3
+#define USI_MODE_I2C1		4
+#define USI_MODE_I2C0_1		5
+#define USI_MODE_UART_I2C1	6
+
+/* Deprecated */
+#define USI_V2_NONE		USI_MODE_NONE
+#define USI_V2_UART		USI_MODE_UART
+#define USI_V2_SPI		USI_MODE_SPI
+#define USI_V2_I2C		USI_MODE_I2C
 
 #endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */
diff --git a/include/dt-bindings/sound/qcom,wcd934x.h b/include/dt-bindings/sound/qcom,wcd934x.h
new file mode 100644
index 00000000000..8b30d34fcc8
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,wcd934x.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_SOUND_QCOM_WCD934x_H
+#define __DT_SOUND_QCOM_WCD934x_H
+
+#define AIF1_PB                 0
+#define AIF1_CAP                1
+#define AIF2_PB                 2
+#define AIF2_CAP                3
+#define AIF3_PB                 4
+#define AIF3_CAP                5
+#define AIF4_PB                 6
+#define AIF4_VIFEED             7
+#define AIF4_MAD_TX             8
+
+#endif
-- 
cgit v1.2.3