From 99c618ff261e1b68e3245ecc467e5a5a8c5e7b8d Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 15 Jan 2015 13:32:29 -0200 Subject: wandboard: Use 32bit color depth for Fusion LCD The Fusion LCD needs the 32bit color depth to properly work; the default is different on the 3.10.17 kernels and it is better to ensure it work out of box using proper default color setting. Signed-off-by: Otavio Salvador --- include/configs/wandboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 809017c5fe2..117d1f7087a 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -175,7 +175,7 @@ "if i2c probe 0x10; then " \ "setenv bootargs ${bootargs} " \ "video=mxcfb${nextcon}:dev=lcd,800x480@60," \ - "if=RGB666; " \ + "if=RGB666,bpp=32; " \ "if test 0 -eq ${nextcon}; then " \ "setenv fbmem fbmem=10M; " \ "else " \ -- cgit v1.3.1 From 834670eae0ddc3e4a809d05645f12f23ef216a41 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 Dec 2014 16:23:17 -0200 Subject: mx6sxsabresd: Remove unneeded board_late_init() Since commit 1f98e31bc0b2c37a ("imx: mx6sxsabresd: Use the pfuze common init function") board_late_init() became empty, so we can safely remove this unneeded function. Signed-off-by: Fabio Estevam --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 5 ----- include/configs/mx6sxsabresd.h | 1 - 2 files changed, 6 deletions(-) (limited to 'include') diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5cc58ac8683..a848f4103aa 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -423,11 +423,6 @@ int board_init(void) return 0; } -int board_late_init(void) -{ - return 0; -} - int checkboard(void) { puts("Board: MX6SX SABRE SDB\n"); diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index fbaae3f505b..3aae808ba9e 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -- cgit v1.3.1 From 5d6050fdb8b0aaf3d3c43b3cad68d6b8f5037f9a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 10 Dec 2014 10:15:23 +0100 Subject: arm: mx6: Add Barco platinum-picon and platinum-titanium This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese Cc: Stefano Babic Cc: Pieter Ronsijn --- arch/arm/Kconfig | 11 ++ board/barco/platinum/Kconfig | 37 ++++ board/barco/platinum/MAINTAINERS | 7 + board/barco/platinum/Makefile | 14 ++ board/barco/platinum/platinum.c | 217 +++++++++++++++++++++ board/barco/platinum/platinum.h | 88 +++++++++ board/barco/platinum/platinum_picon.c | 244 +++++++++++++++++++++++ board/barco/platinum/platinum_titanium.c | 209 ++++++++++++++++++++ board/barco/platinum/spl_picon.c | 182 ++++++++++++++++++ board/barco/platinum/spl_titanium.c | 185 ++++++++++++++++++ configs/platinum_picon_defconfig | 4 + configs/platinum_titanium_defconfig | 4 + include/configs/platinum.h | 319 +++++++++++++++++++++++++++++++ include/configs/platinum_picon.h | 31 +++ include/configs/platinum_titanium.h | 38 ++++ 15 files changed, 1590 insertions(+) create mode 100644 board/barco/platinum/Kconfig create mode 100644 board/barco/platinum/MAINTAINERS create mode 100644 board/barco/platinum/Makefile create mode 100644 board/barco/platinum/platinum.c create mode 100644 board/barco/platinum/platinum.h create mode 100644 board/barco/platinum/platinum_picon.c create mode 100644 board/barco/platinum/platinum_titanium.c create mode 100644 board/barco/platinum/spl_picon.c create mode 100644 board/barco/platinum/spl_titanium.c create mode 100644 configs/platinum_picon_defconfig create mode 100644 configs/platinum_titanium_defconfig create mode 100644 include/configs/platinum.h create mode 100644 include/configs/platinum_picon.h create mode 100644 include/configs/platinum_titanium.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03cfaa..dd35992983e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -664,6 +664,16 @@ config TARGET_OT1200 bool "Bachmann OT1200" select CPU_V7 +config TARGET_PLATINUM_PICON + bool "Support platinum-picon" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PLATINUM_TITANIUM + bool "Support platinum-titanium" + select CPU_V7 + select SUPPORT_SPL + config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 @@ -869,6 +879,7 @@ source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" +source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" source "board/bluewater/snapper9260/Kconfig" diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig new file mode 100644 index 00000000000..8bbad24c0de --- /dev/null +++ b/board/barco/platinum/Kconfig @@ -0,0 +1,37 @@ +if TARGET_PLATINUM_PICON + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_picon" + +endif + +if TARGET_PLATINUM_TITANIUM + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_titanium" + +endif diff --git a/board/barco/platinum/MAINTAINERS b/board/barco/platinum/MAINTAINERS new file mode 100644 index 00000000000..a22584b5e58 --- /dev/null +++ b/board/barco/platinum/MAINTAINERS @@ -0,0 +1,7 @@ +PLATINUM BOARD +M: Stefan Roese +S: Maintained +F: board/barco/platinum/ +F: include/configs/platinum.h +F: configs/platinum_picon_defconfig +F: configs/platinum_titanium_defconfig diff --git a/board/barco/platinum/Makefile b/board/barco/platinum/Makefile new file mode 100644 index 00000000000..abc941914ad --- /dev/null +++ b/board/barco/platinum/Makefile @@ -0,0 +1,14 @@ +# +# Copyright (C) 2014, Barco (www.barco.com) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := platinum.o +obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o + +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o +endif diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c new file mode 100644 index 00000000000..1485a4856f1 --- /dev/null +++ b/board/barco/platinum/platinum.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC3_BASE_ADDR }, +}; + +void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +int board_ehci_hcd_init(int port) +{ + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { + unsigned sd3_cd = IMX_GPIO_NR(7, 0); + gpio_direction_input(sd3_cd); + return !gpio_get_value(sd3_cd); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +void board_init_gpio(void) +{ + platinum_init_gpio(); +} + +void board_init_gpmi_nand(void) +{ + setup_gpmi_nand(); +} + +void board_init_i2c(void) +{ + platinum_setup_i2c(); +} + +void board_init_spi(void) +{ + platinum_setup_spi(); +} + +void board_init_uart(void) +{ + platinum_setup_uart(); +} + +void board_init_usb(void) +{ + platinum_init_usb(); +} + +void board_init_finished(void) +{ + platinum_init_finished(); +} + +int board_phy_config(struct phy_device *phydev) +{ + return platinum_phy_config(phydev); +} + +int board_eth_init(bd_t *bis) +{ + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + board_init_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + board_init_spi(); + + board_init_i2c(); + + board_init_gpmi_nand(); + + board_init_gpio(); + + board_init_usb(); + + board_init_finished(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_PLATINUM_BOARD "\n"); + return 0; +} + +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; + +int misc_init_r(void) +{ + add_board_boot_modes(board_boot_modes); + + return 0; +} diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h new file mode 100644 index 00000000000..8650d6d5e03 --- /dev/null +++ b/board/barco/platinum/platinum.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PLATINUM_H_ +#define _PLATINUM_H_ + +#include +#include + +/* Defines */ + +#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) + +/* Prototypes */ + +int platinum_setup_enet(void); +int platinum_setup_i2c(void); +int platinum_setup_spi(void); +int platinum_setup_uart(void); +int platinum_phy_config(struct phy_device *phydev); +int platinum_init_gpio(void); +int platinum_init_usb(void); +int platinum_init_finished(void); + +static inline void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static inline void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +#endif /* _PLATINUM_H_ */ diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c new file mode 100644 index 00000000000..b2eab766c58 --- /dev/null +++ b/board/barco/platinum/platinum_picon.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) +#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) +#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) + +#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) +#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) +#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) + +#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) +#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) +#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) + +#define GPIO_USB_RESET IMX_GPIO_NR(1, 5) + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* PHY nRESET */ +iomux_v3_cfg_t const phy_reset_pad = { + MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c0_mux_pads[] = { + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c2_mux_pads[] = { + MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + unsigned phy_reset = IMX_GPIO_NR(1, 19); + + /* First configure PHY reset GPIO pin */ + imx_iomux_v3_setup_pad(phy_reset_pad); + + /* Reconfigure enet muxing while PHY is in reset */ + gpio_direction_output(phy_reset, 0); + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + mdelay(10); + gpio_set_value(phy_reset, 1); + udelay(100); + + /* set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + return enable_fec_anatop_clock(ENET_50MHZ); +} + +int platinum_setup_i2c(void) +{ + imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, + ARRAY_SIZE(i2c0_mux_pads)); + imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, + ARRAY_SIZE(i2c2_mux_pads)); + + mdelay(10); + + /* Disable i2c mux 0 */ + gpio_direction_output(GPIO_I2C0_SEL0, 0); + gpio_direction_output(GPIO_I2C0_SEL1, 0); + gpio_direction_output(GPIO_I2C0_ENBN, 1); + + /* Disable i2c mux 1 */ + gpio_direction_output(GPIO_I2C2_SEL0, 0); + gpio_direction_output(GPIO_I2C2_SEL1, 0); + gpio_direction_output(GPIO_I2C2_ENBN, 1); + + udelay(10); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + /* Disable all leds */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x55); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* Use generic infrastructure, no specific setup */ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Reset FPGA's */ + gpio_direction_output(GPIO_IP_NCONFIG, 0); + gpio_direction_output(GPIO_HK_NCONFIG, 0); + gpio_direction_output(GPIO_LS_NCONFIG, 0); + udelay(3); + gpio_set_value(GPIO_IP_NCONFIG, 1); + gpio_set_value(GPIO_HK_NCONFIG, 1); + gpio_set_value(GPIO_LS_NCONFIG, 1); + + /* no dmd configuration yet */ + + return 0; +} + +int platinum_init_usb(void) +{ + /* Reset usb hub */ + gpio_direction_output(GPIO_USB_RESET, 0); + udelay(100); + gpio_set_value(GPIO_USB_RESET, 1); + + return 0; +} + +int platinum_init_finished(void) +{ + /* Enable led 0 */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x54); + + return 0; +} diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c new file mode 100644 index 00000000000..73a955f0194 --- /dev/null +++ b/board/barco/platinum/platinum_titanium.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + /* non mounted spi nor flash for booting */ + MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + mdelay(10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + udelay(100); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + + return 0; +} + +int platinum_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Default GPIO's */ + /* Toggle CONFIG_n to reset fpga on every boot */ + gpio_direction_output(IMX_GPIO_NR(5, 18), 0); + /* Need delay >=2uS */ + udelay(3); + gpio_set_value(IMX_GPIO_NR(5, 18), 1); + + /* Default pin 1,15 high - DLP_FLASH_WPZ */ + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + + return 0; +} + +int platinum_init_usb(void) +{ + return 0; +} + +int platinum_init_finished(void) +{ + return 0; +} diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c new file mode 100644 index 00000000000..f421c2108c9 --- /dev/null +++ b/board/barco/platinum/spl_picon.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41K256M16HA-125 */ +static struct mx6_ddr3_cfg mt41k256m16ha_125 = { + .mem_speed = 1600, + .density = 4, /* 4Gbit */ + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * Values from running the Freescale DDR stress tool via USB + */ +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x0044004E, + .p0_mpwldectrl1 = 0x001F0023, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x02480248, + .p0_mpdgctrl1 = 0x0210021C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x42444444, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36322C32, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c new file mode 100644 index 00000000000..26fe26ba2b9 --- /dev/null +++ b/board/barco/platinum/spl_titanium.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41J128M16JT-125 */ +static struct mx6_ddr3_cfg mt41j128m16jt_125 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* Write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x434b0350, + .p0_mpdgctrl1 = 0x034c0359, + .p1_mpdgctrl0 = 0x434b0350, + .p1_mpdgctrl1 = 0x03650348, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4436383b, + .p1_mprddlctl = 0x39393341, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254a36, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig new file mode 100644 index 00000000000..c3ca0400a1f --- /dev/null +++ b/configs/platinum_picon_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PLATINUM_PICON=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig new file mode 100644 index 00000000000..db8cef9cf48 --- /dev/null +++ b/configs/platinum_titanium_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PLATINUM_TITANIUM=y diff --git a/include/configs/platinum.h b/include/configs/platinum.h new file mode 100644 index 00000000000..134bb45887a --- /dev/null +++ b/include/configs/platinum.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLATINUM_CONFIG_H__ +#define __PLATINUM_CONFIG_H__ + +#define CONFIG_SYS_GENERIC_BOARD + +/* SPL */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +/* Location in NAND to read U-Boot from */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) + +#include "imx6_spl.h" /* common IMX6 SPL configuration */ +#include "mx6_common.h" +#include +#include + +/* + * Console configuration + */ + +#include +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FUSE +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_TIME +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_USB + +/* + * Hardware configuration + */ + +/* GPIO config */ +#define CONFIG_MXC_GPIO + +/* UART config */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 + +/* I2C config */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC config */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_DOS_PARTITION + +/* Ethernet config */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR + +#define CONFIG_PHYLIB + +/* USB config */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Memory config */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#ifndef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE (1024 << 20) +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifdef CONFIG_CMD_NAND + +/* NAND config */ +#define CONFIG_NAND_MXS +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 2 +#endif +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA config, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* Fuse support */ +#define CONFIG_MXC_OCOTP + +/* Environment in NAND */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (16 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#else /* CONFIG_CMD_NAND */ + +/* Environment in MMC */ +#define CONFIG_ENV_SIZE (8 << 10) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif /* CONFIG_CMD_NAND */ + +/* + * U-Boot configuration + */ + +/* Console boot messages */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Tag config */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Board startup config */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Device tree support */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + PHYS_SDRAM_SIZE - (12 << 20)) + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "run bootubi_scr" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_PREBOOT + +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MTD/UBI/UBIFS config */ +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE + +#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \ + "512k(env1),512k(env2),-(ubi)" +#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \ + "512k(env1),512k(env2),495M(ubi0)," \ + "14M(res0),2M(res1)," \ + "512k(res2),512k(res3),-(ubi1)" +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* + * Environment configuration + */ + +#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) +#define CONFIG_COMMON_ENV_UBI \ + "setubipartition=env set ubipartition ubi\0" \ + "setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0" +#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) +#define CONFIG_COMMON_ENV_UBI \ + "setubipartition=env set ubipartition ubi$boot_vol\0" \ + "setubirfs=env set ubirfs ubi0:rootfs\0" +#endif + +#define CONFIG_COMMON_ENV_MISC \ + "user=user\0" \ + "project="CONFIG_PLATINUM_PROJECT"\0" \ + "uimage=uImage\0" \ + "dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \ + "serverip=serverip\0" \ + "memaddrlinux=0x10800000\0" \ + "memaddrsrc=0x11000000\0" \ + "memaddrdtb=0x12000000\0" \ + "console=ttymxc0\0" \ + "baudrate=115200\0" \ + "boot_scr=boot.uboot\0" \ + "boot_vol=0\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" \ + "mmcfs=ext2\0" \ + "mmcrootpart=1\0" \ + \ + "setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \ + "settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \ + "settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \ + "setubifilelinux=env set ubifilelinux boot/$uimage\0" \ + "setubipfiledtb=env set ubifiledtb boot/$dtb\0" \ + "setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \ + "setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \ + "setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \ + \ + "loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \ + "loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \ + "loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \ + "loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \ + "loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \ + "$mmcfilelinux\0" \ + "loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \ + "$mmcfiledtb\0" \ + \ + "ubipart=ubi part $ubipartition\0" \ + "ubimount=ubifsmount $ubirfs\0" \ + \ + "setbootargscommon=env set bootargs $bootargs " \ + "console=$console,$baudrate enable_wait_mode=off\0" \ + "setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \ + "setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \ + "setbootargsubirfs=env set bootargs $bootargs " \ + "ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \ + "setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \ + "nfsroot=$serverip:$nfspath,v3,tcp\0" \ + "setbootargsmmcrfs=env set bootargs $bootargs " \ + "root=$mmcrootdev rootwait rw\0" \ + \ + "bootnet=run settftpfilelinux settftpfiledtb setnfspath " \ + "setbootargscommon setbootargsmtd setbootargsdhcp " \ + "setbootargsnfsrfs;" \ + "run loadtftpkernel loadtftpdtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + "bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \ + "run setubipartition setubirfs;" \ + "run setbootargscommon setbootargsmtd " \ + "setbootargsubirfs;" \ + "run loadtftpkernel loadtftpdtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + "bootubi=run setubipartition setubirfs setubifilelinux " \ + "setubipfiledtb;" \ + "run setbootargscommon setbootargsmtd " \ + "setbootargsubirfs;" \ + "run ubipart ubimount loadubikernel loadubidtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + "bootubi_scr=run setubipartition setubirfs;" \ + "run ubipart ubimount;" \ + "if ubifsload ${memaddrsrc} boot/${boot_scr}; " \ + "then source ${memaddrsrc}; else run bootubi; fi\0" \ + "bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \ + "setbootargscommon setbootargsmmcrfs;" \ + "run loadmmckernel loadmmcdtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + \ + "bootcmd="CONFIG_BOOTCOMMAND"\0" + +#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \ + CONFIG_COMMON_ENV_UBI +#endif /* __PLATINUM_CONFIG_H__ */ diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h new file mode 100644 index 00000000000..4590df5a9e9 --- /dev/null +++ b/include/configs/platinum_picon.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLATINUM_PICON_CONFIG_H__ +#define __PLATINUM_PICON_CONFIG_H__ + +#define CONFIG_PLATINUM_PICON +#define CONFIG_PLATINUM_BOARD "Barco Picon" +#define CONFIG_PLATINUM_PROJECT "picon" +#define CONFIG_PLATINUM_CPU "imx6dl" + +#define CONFIG_MX6 + +#include + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_HOSTNAME picon + +#define CONFIG_SYS_PROMPT "picon > " + +#define CONFIG_PLATFORM_ENV_SETTINGS "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ + CONFIG_PLATFORM_ENV_SETTINGS + +#endif /* __PLATINUM_PICON_CONFIG_H__ */ diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h new file mode 100644 index 00000000000..678965505f6 --- /dev/null +++ b/include/configs/platinum_titanium.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLATINUM_TITANIUM_CONFIG_H__ +#define __PLATINUM_TITANIUM_CONFIG_H__ + +#define CONFIG_PLATINUM_TITANIUM +#define CONFIG_PLATINUM_BOARD "Barco Titanium" +#define CONFIG_PLATINUM_PROJECT "titanium" +#define CONFIG_PLATINUM_CPU "imx6q" + +#define CONFIG_MX6 + +#define PHYS_SDRAM_SIZE (512 << 20) +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +#include + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 4 + +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_PHY_RESET_DELAY 1000 + +#define CONFIG_HOSTNAME titanium + +#define CONFIG_SYS_PROMPT "titanium > " + +#define CONFIG_PLATFORM_ENV_SETTINGS "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ + CONFIG_PLATFORM_ENV_SETTINGS + +#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */ -- cgit v1.3.1 From 71abf19b0f0ee1534ac8945a76606b34fea57b57 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 30 Dec 2014 17:24:00 +0800 Subject: imx:mx6sxsabresd spl support in header file Add SPL support in mx6sxsabresd header file. Signed-off-by: Peng Fan --- include/configs/mx6sxsabresd.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 3aae808ba9e..54cdd641154 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -18,6 +18,12 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" +#endif + #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -- cgit v1.3.1 From f9e89ffd16b734997e6eacb32293899ceaed49ee Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 30 Dec 2014 17:24:02 +0800 Subject: imx:mx6 add mx6sx in imx spl header file Since mx6sx's memory space is different to mx6dq, redefine the SPL related macro for mx6sx chip. Signed-off-by: Peng Fan --- include/configs/imx6_spl.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 1b9c2773beb..21c5dce0978 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -61,11 +61,19 @@ #define CONFIG_SPL_LIBDISK_SUPPORT #endif +#if defined(CONFIG_MX6SX) +#define CONFIG_SPL_BSS_START_ADDR 0x88200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ +#define CONFIG_SYS_TEXT_BASE 0x87800000 +#else #define CONFIG_SPL_BSS_START_ADDR 0x18200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x18300000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ #define CONFIG_SYS_TEXT_BASE 0x17800000 #endif +#endif #endif -- cgit v1.3.1 From 0da040bfd4b7e3cafd739d3eebf20b3bdb27245f Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Fri, 16 Jan 2015 16:47:44 +0800 Subject: imx: mx6: Change ENV offset to 512K bytes for larger u-boot image To align with other mx6 boards, change ENV offset from 384KB to 512KB position to fit a larger u-boot image. Signed-off-by: Ye.Li --- include/configs/mx6slevk.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index e6c41306a36..c567d9dbb68 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -198,7 +198,7 @@ #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #else -#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_ENV_IS_IN_MMC #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 54cdd641154..404b922d39c 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -260,7 +260,7 @@ #define FSL_QSPI_FLASH_NUM 2 #endif -#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -- cgit v1.3.1 From f77dd6d7dbe42cee2b03d1b4c8b34ceb15643174 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 19 Jan 2015 17:26:45 +0100 Subject: ot1200: make use of imx_ddr_size(..) To support different ddr3 memory sizes we should start using imx_ddr_size(..) instead of the define PHYS_SDRAM_SIZE. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 3 ++- include/configs/ot1200.h | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 93f3d651764..039e858706c 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 255c933baa4..97ee664e205 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -159,7 +159,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -- cgit v1.3.1 From 68a3664aec94c10213f082dabe4921f556bdc928 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 19 Jan 2015 17:26:48 +0100 Subject: ot1200: add SPL configuration We will only support loading u-boot.img from SPI flash stored at the offset of 64k. Signed-off-by: Christian Gmeiner --- include/configs/ot1200.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 97ee664e205..c061e93534f 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -108,6 +108,16 @@ #endif +/* SPL */ +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#define CONFIG_SPL_SPI_LOAD +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- cgit v1.3.1 From 508a6edea92877f81972a4ab04d1e2d5549030ec Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:41 +0200 Subject: arm: mx6: cm-fx6: expand boot sequence Expand boot sequence to the following order: 1) mmc boot: mmc boot script, then mmc bootm, then mmc bootz. 2) usb boot: usb boot script. 3) sata boot: sata boot script, sata bootm, sata bootz. 4) nand boot: nand bootm, then nand bootz. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- include/configs/cm_fx6.h | 127 +++++++++++++++++++++++------------------------ 1 file changed, 61 insertions(+), 66 deletions(-) (limited to 'include') diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index f7277eb1d17..d79c83bf2dc 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -103,97 +103,92 @@ #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel=uImage-cm-fx6\0" \ "autoload=no\0" \ + "kernel=uImage-cm-fx6\0" \ + "script=boot.scr\0" \ + "dtb=cm-fx6.dtb\0" \ + "bootm_low=18000000\0" \ "loadaddr=0x10800000\0" \ "fdtaddr=0x11000000\0" \ "console=ttymxc3,115200\0" \ "ethprime=FEC0\0" \ - "bootscr=boot.scr\0" \ - "bootm_low=18000000\0" \ "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ - "fdtfile=cm-fx6.dtb\0" \ "doboot=bootm ${loadaddr}\0" \ - "loadfdt=false\0" \ + "doloadfdt=false\0" \ "setboottypez=setenv kernel zImage-cm-fx6;" \ "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ - "setenv loadfdt true;\0" \ + "setenv doloadfdt true;\0" \ "setboottypem=setenv kernel uImage-cm-fx6;" \ "setenv doboot bootm ${loadaddr};" \ - "setenv loadfdt false;\0"\ - "run_eboot=echo Starting EBOOT ...; "\ - "mmc dev ${mmcdev} && " \ - "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ - "mmcdev=2\0" \ + "setenv doloadfdt false;\0"\ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ - "mmcbootscript=echo Running bootscript from mmc ...; "\ - "source ${loadaddr}\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=${mmcroot} " \ - "${video}\0" \ - "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ - "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "run doboot\0" \ - "satadev=0\0" \ "sataroot=/dev/sda2 rw rootwait\0" \ - "sataargs=setenv bootargs console=${console} " \ - "root=${sataroot} " \ - "${video}\0" \ - "loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \ - "satabootscript=echo Running bootscript from sata ...; " \ - "source ${loadaddr}\0" \ - "sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \ - "sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \ - "sataboot=echo Booting from sata ...; "\ - "run sataargs; " \ - "run doboot\0" \ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ + "${video}\0" \ + "sataargs=setenv bootargs console=${console} root=${sataroot} " \ + "${video}\0" \ "nandargs=setenv bootargs console=${console} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype} " \ "${video}\0" \ - "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 0 780000; " \ - "if ${loadfdt}; then " \ + "nandboot=if run nandloadkernel; then " \ "run nandloadfdt;" \ - "fi; " \ - "run doboot\0" \ - "boot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "if run loadmmcbootscript; then " \ - "run mmcbootscript;" \ - "else " \ - "if run mmcloadkernel; then " \ - "if ${loadfdt}; then " \ - "run mmcloadfdt;" \ - "fi;" \ - "run mmcboot;" \ - "fi;" \ - "fi;" \ + "run setboottypem;" \ + "run storagebootcmd;" \ + "run setboottypez;" \ + "run storagebootcmd;" \ + "fi;\0" \ + "run_eboot=echo Starting EBOOT ...; "\ + "mmc dev 2 && " \ + "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ + "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\ + "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\ + "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \ + "bootscript=echo Running bootscript from ${storagetype} ...;" \ + "source ${loadaddr};\0" \ + "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \ + "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ + "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ + "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ + "setupnandboot=setenv storagetype nand;\0" \ + "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \ + "storagebootcmd=echo Booting from ${storagetype} ...;" \ + "run ${storagetype}args; run doboot;\0" \ + "trybootk=if run loadkernel; then " \ + "if ${doloadfdt}; then " \ + "run loadfdt;" \ "fi;" \ - "if sata init; then " \ - "if run loadsatabootscript; then " \ - "run satabootscript;" \ - "else "\ - "if run sataloadkernel; then " \ - "if ${loadfdt}; then " \ - "run sataloadfdt; " \ - "fi;" \ - "run sataboot;" \ - "fi;" \ - "fi;" \ + "run storagebootcmd;" \ + "fi;\0" \ + "trybootsmz=if run loadscript; then " \ + "run bootscript;" \ "fi;" \ - "run nandboot\0" + "run setboottypem;" \ + "run trybootk;" \ + "run setboottypez;" \ + "run trybootk;\0" #define CONFIG_BOOTCOMMAND \ - "run setboottypem; run boot" + "run setupmmcboot;" \ + "mmc dev ${storagedev};" \ + "if mmc rescan; then " \ + "run trybootsmz;" \ + "fi;" \ + "run setupusbboot;" \ + "if usb start; then "\ + "if run loadscript; then " \ + "run bootscript;" \ + "fi;" \ + "fi;" \ + "run setupsataboot;" \ + "if sata init; then " \ + "run trybootsmz;" \ + "fi;" \ + "run setupnandboot;" \ + "run nandboot;" /* SPI */ #define CONFIG_SPI -- cgit v1.3.1 From 9fbdcf018e5f4bf78126c2f6df42d6f5bf91c946 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:45 +0200 Subject: arm: mx6: cm-fx6: increase size of malloc area Increase size of malloc area to make room for framebuffer and other such big allocations. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg --- include/configs/cm_fx6.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index d79c83bf2dc..a2e42c45923 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -276,7 +276,7 @@ /* misc */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_STACKSIZE (128 * 1024) -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #define CONFIG_OF_BOARD_SETUP -- cgit v1.3.1 From deb94d6192e7507d743aefa69a86954c0c26be82 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:46 +0200 Subject: arm: mx6: cm-fx6: add hdmi console support Add support for hdmi console. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 51 ++++++++++++++++++++++++++++++++++++++++++ include/configs/cm_fx6.h | 15 +++++++++++++ 2 files changed, 66 insertions(+) (limited to 'include') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index eb18dfc44c4..b31e1f59b6b 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -18,8 +18,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -28,6 +30,53 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_IMX_HDMI +static void cm_fx6_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = cm_fx6_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 40385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + } + }, +}; +size_t display_count = ARRAY_SIZE(displays); + +static void cm_fx6_setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); +} +#else +static inline void cm_fx6_setup_display(void) {} +#endif /* CONFIG_VIDEO_IPUV3 */ + #ifdef CONFIG_DWC_AHSATA static int cm_fx6_issd_gpios[] = { /* The order of the GPIOs in the array is important! */ @@ -516,6 +565,8 @@ int board_init(void) if (ret) printf("Warning: I2C setup failed: %d\n", ret); + cm_fx6_setup_display(); + return 0; } diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index a2e42c45923..a9f33a9e34c 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -103,6 +103,9 @@ #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" \ + "panel=HDMI\0" \ "autoload=no\0" \ "kernel=uImage-cm-fx6\0" \ "script=boot.scr\0" \ @@ -291,4 +294,16 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #define CONFIG_SPL_SPI_LOAD +/* Display */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX +#define CONFIG_VIDEO_SW_CURSOR + #endif /* __CONFIG_CM_FX6_H */ -- cgit v1.3.1 From 8015dde87876dc3f5cb600186d7ad30744a1b7dc Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:47 +0200 Subject: arm: mx6: cm-fx6: display compulab logo Add compulab logo and display it on boot. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- include/configs/cm_fx6.h | 3 +++ tools/logos/compulab.bmp | Bin 0 -> 31810 bytes 2 files changed, 3 insertions(+) create mode 100644 tools/logos/compulab.bmp (limited to 'include') diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index a9f33a9e34c..5d0d303dfcd 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -306,4 +306,7 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + #endif /* __CONFIG_CM_FX6_H */ diff --git a/tools/logos/compulab.bmp b/tools/logos/compulab.bmp new file mode 100644 index 00000000000..df5435cb596 Binary files /dev/null and b/tools/logos/compulab.bmp differ -- cgit v1.3.1 From 1c2e529243b126a15b604cadd96e5dff3ce225de Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:48 +0200 Subject: arm: mx6: cm-fx6: add support for usb keyboard Add support for usb keyboard for cm_fx6. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- include/configs/cm_fx6.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 5d0d303dfcd..49b1b0023e8 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -103,6 +103,7 @@ #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial,usbkbd\0" \ "stdout=serial,vga\0" \ "stderr=serial,vga\0" \ "panel=HDMI\0" \ @@ -193,6 +194,8 @@ "run setupnandboot;" \ "run nandboot;" +#define CONFIG_PREBOOT "usb start" + /* SPI */ #define CONFIG_SPI #define CONFIG_MXC_SPI @@ -241,6 +244,9 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_SYS_STDIO_DEREGISTER /* I2C */ #define CONFIG_CMD_I2C -- cgit v1.3.1 From 3a236a356397449bf3ad1e72221053b5a3d87b80 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:53 +0200 Subject: arm: mx6: cm-fx6: add splash screen support Add support for splash screen. The splash screen is loaded from the SPI flash and is displayed on the HDMI display. Signed-off-by: Nikita Kiryanov [grinberg@compulab.co.il: minor code and commit message updates] Signed-off-by: Igor Grinberg Cc: Stefano Babic Cc: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 17 +++++++++++++++++ include/configs/cm_fx6.h | 4 ++++ 2 files changed, 21 insertions(+) (limited to 'include') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b31e1f59b6b..b5c3ea19d36 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -27,9 +27,26 @@ #include #include "common.h" #include "../common/eeprom.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location cm_fx6_splash_locations[] = { + { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .offset = 0x100000, + }, +}; + +int splash_screen_prepare(void) +{ + return cl_splash_screen_prepare(cm_fx6_splash_locations, + ARRAY_SIZE(cm_fx6_splash_locations)); +} +#endif + #ifdef CONFIG_IMX_HDMI static void cm_fx6_enable_hdmi(struct display_info_t const *dev) { diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 49b1b0023e8..b92ba976e91 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -312,6 +312,10 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 + #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -- cgit v1.3.1 From f82eb2fa5df86b7180ea355a3cb98482f7c27269 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:54 +0200 Subject: common: convert compulab splash load code to common code Move board/compulab/common/splash.c code to common/splash_source.c to make it available for everybody. This move renames cl_splash_screen_prepare() to splash_source_load(), and the compilation of this code is conditional on CONFIG_SPLASH_SOURCE. splash_source features: * Provide a standardized way for declaring board specific splash screen locations * Provide existing routines for auto loading the splash image from the locations as declared by the board * Introduce the "splashsource" environment variable, which makes it possible to select the splash image source. cm-t35 and cm-fx6 are updated to use the modified version. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Tom Rini Cc: Igor Grinberg Cc: Anatolij Gustschin Reviewed-by: Tom Rini Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 5 +- board/compulab/cm_t35/cm_t35.c | 5 +- board/compulab/common/Makefile | 1 - board/compulab/common/common.h | 21 ----- board/compulab/common/splash.c | 165 -------------------------------------- common/Makefile | 1 + common/splash_source.c | 176 +++++++++++++++++++++++++++++++++++++++++ doc/README.splashprepare | 13 +++ include/configs/cm_fx6.h | 1 + include/configs/cm_t35.h | 1 + include/splash.h | 11 +++ 11 files changed, 209 insertions(+), 191 deletions(-) delete mode 100644 board/compulab/common/splash.c create mode 100644 common/splash_source.c (limited to 'include') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b5c3ea19d36..ae6945ba9c9 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -42,8 +43,8 @@ static struct splash_location cm_fx6_splash_locations[] = { int splash_screen_prepare(void) { - return cl_splash_screen_prepare(cm_fx6_splash_locations, - ARRAY_SIZE(cm_fx6_splash_locations)); + return splash_source_load(cm_fx6_splash_locations, + ARRAY_SIZE(cm_fx6_splash_locations)); } #endif diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 8143c05353c..c4ea8ea875f 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -69,8 +70,8 @@ struct splash_location splash_locations[] = { int splash_screen_prepare(void) { - return cl_splash_screen_prepare(splash_locations, - ARRAY_SIZE(splash_locations)); + return splash_source_load(splash_locations, + ARRAY_SIZE(splash_locations)); } /* diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index dbf0009652a..286f32731da 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -9,5 +9,4 @@ obj-y += common.o obj-$(CONFIG_SYS_I2C) += eeprom.o obj-$(CONFIG_LCD) += omap3_display.o -obj-$(CONFIG_SPLASH_SCREEN) += splash.o obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index b992965457d..8f38b79fb05 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -24,27 +24,6 @@ static inline int cl_usb_hub_init(int gpio, const char *label) static inline void cl_usb_hub_deinit(int gpio) {} #endif /* CONFIG_CMD_USB */ -enum splash_storage { - SPLASH_STORAGE_NAND, - SPLASH_STORAGE_SF, -}; - -struct splash_location { - char *name; - enum splash_storage storage; - u32 offset; /* offset from start of storage */ -}; - -#ifdef CONFIG_SPLASH_SCREEN -int cl_splash_screen_prepare(struct splash_location *locations, uint size); -#else /* !CONFIG_SPLASH_SCREEN */ -static inline int cl_splash_screen_prepare(struct splash_location *locations, - uint size) -{ - return -ENOSYS; -} -#endif /* CONFIG_SPLASH_SCREEN */ - #ifdef CONFIG_SMC911X int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, int (*reset)(int), int rst_gpio); diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c deleted file mode 100644 index 16c315ca5a5..00000000000 --- a/board/compulab/common/splash.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2014 CompuLab, Ltd. - * - * Authors: Igor Grinberg - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "common.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SPI_FLASH -static struct spi_flash *sf; -static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - if (!sf) { - sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, - CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, - CONFIG_SF_DEFAULT_MODE); - if (!sf) - return -ENODEV; - } - - return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr); -} -#else -static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - debug("%s: sf support not available\n", __func__); - return -ENOSYS; -} -#endif - -#ifdef CONFIG_CMD_NAND -static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - return nand_read_skip_bad(&nand_info[nand_curr_device], offset, - &read_size, NULL, - nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); -} -#else -static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - debug("%s: nand support not available\n", __func__); - return -ENOSYS; -} -#endif - -static int splash_storage_read(struct splash_location *location, - u32 bmp_load_addr, size_t read_size) -{ - u32 offset; - - if (!location) - return -EINVAL; - - offset = location->offset; - switch (location->storage) { - case SPLASH_STORAGE_NAND: - return splash_nand_read(bmp_load_addr, offset, read_size); - case SPLASH_STORAGE_SF: - return splash_sf_read(bmp_load_addr, offset, read_size); - default: - printf("Unknown splash location\n"); - } - - return -EINVAL; -} - -static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr) -{ - struct bmp_header *bmp_hdr; - int res; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = splash_storage_read(location, bmp_load_addr, bmp_header_size); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return splash_storage_read(location, bmp_load_addr, bmp_size); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -EFAULT; -} - -/** - * select_splash_location - return the splash location based on board support - * and env variable "splashsource". - * - * @locations: An array of supported splash locations. - * @size: Size of splash_locations array. - * - * @return: If a null set of splash locations is given, or - * splashsource env variable is set to unsupported value - * return NULL. - * If splashsource env variable is not defined - * return the first entry in splash_locations as default. - * If splashsource env variable contains a supported value - * return the location selected by splashsource. - */ -static struct splash_location *select_splash_location( - struct splash_location *locations, uint size) -{ - int i; - char *env_splashsource; - - if (!locations || size == 0) - return NULL; - - env_splashsource = getenv("splashsource"); - if (env_splashsource == NULL) - return &locations[0]; - - for (i = 0; i < size; i++) { - if (!strcmp(locations[i].name, env_splashsource)) - return &locations[i]; - } - - printf("splashsource env variable set to unsupported value\n"); - return NULL; -} - -int cl_splash_screen_prepare(struct splash_location *locations, uint size) -{ - struct splash_location *splash_location; - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -ENOENT; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -EFAULT; - } - - splash_location = select_splash_location(locations, size); - if (!splash_location) - return -EINVAL; - - return splash_load_raw(splash_location, bmp_load_addr); -} diff --git a/common/Makefile b/common/Makefile index 94554f2939e..0f1416d1e8a 100644 --- a/common/Makefile +++ b/common/Makefile @@ -196,6 +196,7 @@ obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o obj-$(CONFIG_I2C_EDID) += edid.o obj-$(CONFIG_KALLSYMS) += kallsyms.o obj-y += splash.o +obj-$(CONFIG_SPLASH_SOURCE) += splash_source.o obj-$(CONFIG_LCD) += lcd.o lcd_console.o obj-$(CONFIG_LYNXKDI) += lynxkdi.o obj-$(CONFIG_MENU) += menu.o diff --git a/common/splash_source.c b/common/splash_source.c new file mode 100644 index 00000000000..d1bb5a4baf3 --- /dev/null +++ b/common/splash_source.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPI_FLASH +static struct spi_flash *sf; +static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + if (!sf) { + sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!sf) + return -ENODEV; + } + + return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr); +} +#else +static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + debug("%s: sf support not available\n", __func__); + return -ENOSYS; +} +#endif + +#ifdef CONFIG_CMD_NAND +static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + return nand_read_skip_bad(&nand_info[nand_curr_device], offset, + &read_size, NULL, + nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); +} +#else +static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + debug("%s: nand support not available\n", __func__); + return -ENOSYS; +} +#endif + +static int splash_storage_read(struct splash_location *location, + u32 bmp_load_addr, size_t read_size) +{ + u32 offset; + + if (!location) + return -EINVAL; + + offset = location->offset; + switch (location->storage) { + case SPLASH_STORAGE_NAND: + return splash_nand_read(bmp_load_addr, offset, read_size); + case SPLASH_STORAGE_SF: + return splash_sf_read(bmp_load_addr, offset, read_size); + default: + printf("Unknown splash location\n"); + } + + return -EINVAL; +} + +static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr) +{ + struct bmp_header *bmp_hdr; + int res; + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); + + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) + goto splash_address_too_high; + + res = splash_storage_read(location, bmp_load_addr, bmp_header_size); + if (res < 0) + return res; + + bmp_hdr = (struct bmp_header *)bmp_load_addr; + bmp_size = le32_to_cpu(bmp_hdr->file_size); + + if (bmp_load_addr + bmp_size >= gd->start_addr_sp) + goto splash_address_too_high; + + return splash_storage_read(location, bmp_load_addr, bmp_size); + +splash_address_too_high: + printf("Error: splashimage address too high. Data overwrites U-Boot and/or placed beyond DRAM boundaries.\n"); + + return -EFAULT; +} + +/** + * select_splash_location - return the splash location based on board support + * and env variable "splashsource". + * + * @locations: An array of supported splash locations. + * @size: Size of splash_locations array. + * + * @return: If a null set of splash locations is given, or + * splashsource env variable is set to unsupported value + * return NULL. + * If splashsource env variable is not defined + * return the first entry in splash_locations as default. + * If splashsource env variable contains a supported value + * return the location selected by splashsource. + */ +static struct splash_location *select_splash_location( + struct splash_location *locations, uint size) +{ + int i; + char *env_splashsource; + + if (!locations || size == 0) + return NULL; + + env_splashsource = getenv("splashsource"); + if (env_splashsource == NULL) + return &locations[0]; + + for (i = 0; i < size; i++) { + if (!strcmp(locations[i].name, env_splashsource)) + return &locations[i]; + } + + printf("splashsource env variable set to unsupported value\n"); + return NULL; +} + +/** + * splash_source_load - load splash image from a supported location. + * + * Select a splash image location based on the value of splashsource environment + * variable and the board supported splash source locations, and load a + * splashimage to the address pointed to by splashimage environment variable. + * + * @locations: An array of supported splash locations. + * @size: Size of splash_locations array. + * + * @return: 0 on success, negative value on failure. + */ +int splash_source_load(struct splash_location *locations, uint size) +{ + struct splash_location *splash_location; + char *env_splashimage_value; + u32 bmp_load_addr; + + env_splashimage_value = getenv("splashimage"); + if (env_splashimage_value == NULL) + return -ENOENT; + + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); + if (bmp_load_addr == 0) { + printf("Error: bad splashimage address specified\n"); + return -EFAULT; + } + + splash_location = select_splash_location(locations, size); + if (!splash_location) + return -EINVAL; + + return splash_load_raw(splash_location, bmp_load_addr); +} diff --git a/doc/README.splashprepare b/doc/README.splashprepare index 61b4ec53eca..a0f0f3ca51f 100644 --- a/doc/README.splashprepare +++ b/doc/README.splashprepare @@ -6,3 +6,16 @@ common/splash.c. It is called as part of the splash screen display sequence. It gives the board an opportunity to prepare the splash image data before it is processed and sent to the frame buffer by U-Boot. Define your own version to use this feature. + +CONFIG_SPLASH_SOURCE + +Use the splash_source.c library. This library provides facilities to declare +board specific splash image locations, routines for loading splash image from +supported locations, and a way of controlling the selected splash location +using the "splashsource" environment variable. + +splashsource works as follows: +- If splashsource is set to a supported location name as defined by board code, + use that splash location. +- If splashsource is undefined, use the first splash location as default. +- If splashsource is set to an unsupported value, do not load a splash screen. diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index b92ba976e91..1f644950551 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -313,6 +313,7 @@ #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SOURCE #define CONFIG_CMD_BMP #define CONFIG_VIDEO_BMP_RLE8 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 9767512a5cf..b2a9f357970 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -310,6 +310,7 @@ #define CONFIG_LCD #define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SOURCE #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP #define CONFIG_SCF0403_LCD diff --git a/include/splash.h b/include/splash.h index 89ee7b22ec2..a60e8954234 100644 --- a/include/splash.h +++ b/include/splash.h @@ -22,7 +22,18 @@ #ifndef _SPLASH_H_ #define _SPLASH_H_ +enum splash_storage { + SPLASH_STORAGE_NAND, + SPLASH_STORAGE_SF, +}; +struct splash_location { + char *name; + enum splash_storage storage; + u32 offset; /* offset from start of storage */ +}; + +int splash_source_load(struct splash_location *locations, uint size); int splash_screen_prepare(void); #ifdef CONFIG_SPLASH_SCREEN_ALIGN -- cgit v1.3.1 From b4b39a7e54fa6f4aa016cf98744aa5659db75d33 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 20 Jan 2015 10:06:18 +0100 Subject: arm, imx6, aristainetos: board updates - use linux display timing settings - change backlight duty cycle 500ns - some defaultenvironment changes - change fit_addr_r to 0x14000000 as needed if MAX_LOCKDEP_SUBCLASSES in linux gets increased. - Environment now at 0xd0000 in nand flash Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 8 +- include/configs/aristainetos.h | 167 +++++++++++++++++++++----------------- 2 files changed, 97 insertions(+), 78 deletions(-) (limited to 'include') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 67ac2600552..8330bb64bda 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -321,8 +321,8 @@ static void enable_lvds(struct display_info_t const *dev) /* enable backlight PWM 3 */ if (pwm_init(2, 0, 0)) goto error; - /* duty cycle 200ns, period: 3000ns */ - if (pwm_config(2, 200, 3000)) + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(2, 500, 3000)) goto error; if (pwm_enable(2)) goto error; @@ -350,8 +350,8 @@ struct display_info_t const displays[] = { .right_margin = 88, .upper_margin = 10, .lower_margin = 10, - .hsync_len = 25, - .vsync_len = 1, + .hsync_len = 80, + .vsync_len = 25, .sync = 0, .vmode = FB_VMODE_NONINTERLACED } diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h index e6a08df4ba7..3066fd030e4 100644 --- a/include/configs/aristainetos.h +++ b/include/configs/aristainetos.h @@ -1,4 +1,5 @@ /* + * (C) Copyright 2015 * (C) Copyright 2014 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * @@ -24,8 +25,7 @@ #include #define CONFIG_MACH_TYPE 4501 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" -#define CONFIG_DEFAULT_FDT_FILE "aristainetos.dtb" +#define CONFIG_MMCROOT "/dev/mmcblk0p1" #define CONFIG_HOSTNAME aristainetos #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) @@ -81,7 +81,6 @@ #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -101,84 +100,108 @@ #define CONFIG_SYS_TEXT_BASE 0x17800000 #define CONFIG_EXTRA_ENV_SETTINGS \ - "uimage=uImage\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr_r=0x11000000\0" \ - "kernel_addr_r=0x12000000\0" \ - "kernel_file=uImage\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ + "script=u-boot.scr\0" \ + "fit_file=/boot/system.itb\0" \ + "loadaddr=0x12000000\0" \ + "fit_addr_r=0x14000000\0" \ + "uboot=/boot/u-boot.imx\0" \ + "uboot_sz=d0000\0" \ + "rescue_sys_addr=f0000\0" \ + "rescue_sys_length=f10000\0" \ + "board_type=aristainetos7@1\0" \ + "panel=lb07wv8\0" \ + "splashpos=m,m\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \ + "mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(rescue-system);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ + "default ${board_type}\0" \ + "get_env=mw ${loadaddr} 0 0x20000;" \ + "mmc rescan;" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ + "env import -t ${loadaddr}\0" \ + "default_env=mw ${loadaddr} 0 0x20000;" \ + "env export -t ${loadaddr} serial# ethaddr eth1addr " \ + "board_type panel;" \ + "env default -a;" \ + "env import -t ${loadaddr}\0" \ + "loadbootscript=" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ "mmcpart=1\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=0\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} " \ - "${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} " \ - "${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs;run loadimage loadfdt fdt_setup;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \ - "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-sato-sdk\0" \ - "nfsopts=nfsvers=3 nolock rw\0" \ - "netdev=eth0\0" \ - "fdt_setup=fdt addr ${fdt_addr_r};fdt resize;fdt chosen;fdt board\0"\ - "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "get_env=mw ${loadaddr} 0x00000000 0x20000;" \ - "tftp ${loadaddr} /tftpboot/aristainetos/env.txt;" \ - "env import -t ${loadaddr}\0" \ - "addmisc=setenv bootargs ${bootargs} maxcpus=1 loglevel=8\0" \ - "bootargs_defaults=setenv bootargs ${console} ${mtdoops} " \ - "${optargs}\0" \ - "net_args=run bootargs_defaults;setenv bootargs ${bootargs} " \ - "root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "net_nfs=run load_kernel load_fdt;run net_args addmtd addmisc;" \ - "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "uboot=/tftpboot/aristainetos/u-boot.imx\0" \ - "load_uboot=tftp ${loadaddr} ${uboot}\0" \ - "uboot_sz=c0000\0" \ - "upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ - "mw.b 10200000 0x00 ${uboot_sz};" \ - "run load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ + "run mmcargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ + "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ + "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ + "setexpr uboot_maxsize ${uboot_sz} - 400;" \ + "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ + "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ "sf write ${loadaddr} 400 ${filesize};" \ - "sf read 10200000 400 ${uboot_sz};" \ - "cmp.b ${loadaddr} 10200000 bc000\0" \ - "ubi_prep=ubi part ubi 2048;ubifsmount ubi:kernel\0" \ - "load_kernel_ubi=ubifsload ${kernel_addr_r} uImage\0" \ - "load_fdt_ubi=ubifsload ${fdt_addr_r} aristainetos.dtb\0" \ - "ubi_nfs=run ubiprep load_kernel_ubi load_fdt_ubi;" \ - "run net_args addmtd addmisc;run fdt_setup;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootfsname=rootfs\0" \ - "ubi_args=run bootargs_defaults;setenv bootargs ${bootargs} " \ - "ubi.mtd=0,2048 root=ubi0:${rootfsname} rootfstype=ubifs " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "ubi_ubi=run ubi_prep load_kernel_ubi load_fdt_ubi;" \ - "run bootargs_defaults ubi_args addmtd addmisc;" \ - "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "ubirootfs_file=/tftpboot/aristainetos/rootfs-minimal.ubifs\0" \ - "upd_ubirootfs=run ubi_prep;tftp ${loadaddr} ${ubirootfs_file};" \ - "ubi write ${loadaddr} rootfs ${filesize}\0" \ - "ksz=800000\0" \ - "rootsz=2000000\0" \ - "usersz=8000000\0" \ - "ubi_make=run ubi_prep;ubi create kernel ${ksz};" \ - "ubi create rootfs ${rootsz};ubi create userfs ${usersz}\0" + "sf read ${cmp_buf} 400 ${uboot_sz};" \ + "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ + "ubiargs=setenv bootargs console=${console},${baudrate} " \ + "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \ + "ubiboot=echo Booting from ubi ...; " \ + "run ubiargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ + "ubifsload ${fit_addr_r} /boot/system.itb; " \ + "imi ${fit_addr_r}\0 " \ + "rescueargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/ram rw\0 " \ + "rescueboot=echo Booting rescue system from NOR ...; " \ + "run rescueargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ + "${rescue_sys_length}; imi ${fit_addr_r}\0 " #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ - "run mmcboot;" \ - "else run ubi_ubi; fi" + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run mmc_load_fit; then " \ + "run mmcboot; " \ + "else " \ + "if run ubifs_load_fit; then " \ + "run ubiboot; " \ + "else " \ + "if run rescue_load_fit; then " \ + "run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT " \ + "FAILURE;" \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else " \ + "if run ubifs_load_fit; then " \ + "run ubiboot; " \ + "else " \ + "if run rescue_load_fit; then " \ + "run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ + "fi; " \ + "fi; " \ + "fi" #define CONFIG_ARP_TIMEOUT 200UL @@ -227,8 +250,8 @@ #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE #define CONFIG_ENV_SECT_SIZE (0x010000) -#define CONFIG_ENV_OFFSET (0x0c0000) -#define CONFIG_ENV_OFFSET_REDUND (0x0d0000) +#define CONFIG_ENV_OFFSET (0x0d0000) +#define CONFIG_ENV_OFFSET_REDUND (0x0e0000) #define CONFIG_OF_LIBFDT @@ -289,9 +312,6 @@ #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS -#define MTDIDS_DEFAULT "nand0=gpmi-nand" -#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:-(ubi)" - #define CONFIG_MTD_UBI_FASTMAP #define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 @@ -321,5 +341,4 @@ #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 - #endif /* __ARISTAINETOS_CONFIG_H */ -- cgit v1.3.1 From ee52f1a5fedcb261f75054352a2ef52f7a6e6dbc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 9 Jan 2015 16:59:41 +0800 Subject: pmic:pfuze add macro for setting voltage "#define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250)" This macro is for configuring SW1A/B/C Output Voltage easily. Signed-off-by: Peng Fan --- include/power/pfuze100_pmic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 11184893bfb..a00fde0168f 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -41,6 +41,8 @@ enum { * Buck Regulators */ +#define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250) + /* SW1A/B/C Output Voltage Configuration */ #define SW1x_0_300V 0 #define SW1x_0_325V 1 -- cgit v1.3.1 From ccbb18713b279f1326479cc10664d247206e9e76 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 8 Jan 2015 21:00:36 +0800 Subject: pmic:pfuz100 add switch mode and more registers Add more pfuze register offset. And switch mode definition. Signed-off-by: Peng Fan --- include/power/pfuze100_pmic.h | 53 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'include') diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index a00fde0168f..d304658b9a4 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -16,14 +16,34 @@ enum { PFUZE100_SW1ABVOL = 0x20, PFUZE100_SW1ABSTBY = 0x21, + PFUZE100_SW1ABOFF = 0x22, + PFUZE100_SW1ABMODE = 0x23, PUZE_100_SW1ABCONF = 0x24, PFUZE100_SW1CVOL = 0x2e, PFUZE100_SW1CSTBY = 0x2f, + PFUZE100_SW1COFF = 0x30, + PFUZE100_SW1CMODE = 0x31, PFUZE100_SW1CCONF = 0x32, PFUZE100_SW2VOL = 0x35, + PFUZE100_SW2STBY = 0x36, + PFUZE100_SW2OFF = 0x37, + PFUZE100_SW2MODE = 0x38, + PFUZE100_SW2CONF = 0x39, PFUZE100_SW3AVOL = 0x3c, + PFUZE100_SW3ASTBY = 0x3D, + PFUZE100_SW3AOFF = 0x3E, + PFUZE100_SW3AMODE = 0x3F, + PFUZE100_SW3ACONF = 0x40, PFUZE100_SW3BVOL = 0x43, + PFUZE100_SW3BSTBY = 0x44, + PFUZE100_SW3BOFF = 0x45, + PFUZE100_SW3BMODE = 0x46, + PFUZE100_SW3BCONF = 0x47, PFUZE100_SW4VOL = 0x4a, + PFUZE100_SW4STBY = 0x4b, + PFUZE100_SW4OFF = 0x4c, + PFUZE100_SW4MODE = 0x4d, + PFUZE100_SW4CONF = 0x4e, PFUZE100_SWBSTCON1 = 0x66, PFUZE100_VREFDDRCON = 0x6a, PFUZE100_VSNVSVOL = 0x6b, @@ -179,5 +199,38 @@ enum { #define SWBST_MODE_AUTO (2 << 2) #define SWBST_MODE_APS (2 << 3) +/* + * Regulator Mode Control + * + * OFF: The regulator is switched off and the output voltage is discharged. + * PFM: In this mode, the regulator is always in PFM mode, which is useful + * at light loads for optimized efficiency. + * PWM: In this mode, the regulator is always in PWM mode operation + * regardless of load conditions. + * APS: In this mode, the regulator moves automatically between pulse + * skipping mode and PWM mode depending on load conditions. + * + * SWxMODE[3:0] + * Normal Mode | Standby Mode | value + * OFF OFF 0x0 + * PWM OFF 0x1 + * PFM OFF 0x3 + * APS OFF 0x4 + * PWM PWM 0x5 + * PWM APS 0x6 + * APS APS 0x8 + * APS PFM 0xc + * PWM PFM 0xd + */ +#define OFF_OFF 0x0 +#define PWM_OFF 0x1 +#define PFM_OFF 0x3 +#define APS_OFF 0x4 +#define PWM_PWM 0x5 +#define PWM_APS 0x6 +#define APS_APS 0x8 +#define APS_PFM 0xc +#define PWM_PFM 0xd + int power_pfuze100_init(unsigned char bus); #endif -- cgit v1.3.1