From bf9012b808515bf1314538e8d423080951d012df Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 16 May 2017 18:39:03 +0200 Subject: MIPS: add support for Broadcom MIPS BCM6348 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- include/configs/bmips_bcm6348.h | 30 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm6348-clock.h | 22 ++++++++++++++++++++++ include/dt-bindings/reset/bcm6348-reset.h | 22 ++++++++++++++++++++++ 3 files changed, 74 insertions(+) create mode 100644 include/configs/bmips_bcm6348.h create mode 100644 include/dt-bindings/clock/bcm6348-clock.h create mode 100644 include/dt-bindings/reset/bcm6348-reset.h (limited to 'include') diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h new file mode 100644 index 00000000000..e9f53d68117 --- /dev/null +++ b/include/configs/bmips_bcm6348.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6348_H +#define __CONFIG_BMIPS_BCM6348_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h new file mode 100644 index 00000000000..5af066bb164 --- /dev/null +++ b/include/dt-bindings/clock/bcm6348-clock.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6348_H +#define __DT_BINDINGS_CLOCK_BCM6348_H + +#define BCM6348_CLK_ADSL 0 +#define BCM6348_CLK_MPI 1 +#define BCM6348_CLK_SDRAM 2 +#define BCM6348_CLK_M2M 3 +#define BCM6348_CLK_ENET 4 +#define BCM6348_CLK_SAR 5 +#define BCM6348_CLK_USBS 6 +#define BCM6348_CLK_USBH 8 +#define BCM6348_CLK_SPI 9 + +#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */ diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h new file mode 100644 index 00000000000..173937b9efe --- /dev/null +++ b/include/dt-bindings/reset/bcm6348-reset.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6348_H +#define __DT_BINDINGS_RESET_BCM6348_H + +#define BCM6348_RST_SPI 0 +#define BCM6348_RST_ENET 2 +#define BCM6348_RST_USBH 3 +#define BCM6348_RST_USBS 4 +#define BCM6348_RST_ADSL 5 +#define BCM6348_RST_DMAMEM 6 +#define BCM6348_RST_SAR 7 +#define BCM6348_RST_ACLC 8 +#define BCM6348_RST_ADSL_MIPS 10 + +#endif /* __DT_BINDINGS_RESET_BCM6348_H */ -- cgit v1.3.1 From 5e14ce2f3302651abe7873c81f2bae34937b3a63 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 16 May 2017 18:39:04 +0200 Subject: MIPS: add BMIPS Comtrend CT-5361 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/Makefile | 1 + arch/mips/dts/comtrend,ct-5361.dts | 49 ++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 ++++++++ board/comtrend/ct5361/Kconfig | 12 ++++++++ board/comtrend/ct5361/MAINTAINERS | 6 ++++ board/comtrend/ct5361/Makefile | 5 +++ board/comtrend/ct5361/ct-5361.c | 7 +++++ configs/comtrend_ct5361_ram_defconfig | 57 +++++++++++++++++++++++++++++++++++ include/configs/comtrend_ct5361.h | 20 ++++++++++++ 9 files changed, 169 insertions(+) create mode 100644 arch/mips/dts/comtrend,ct-5361.dts create mode 100644 board/comtrend/ct5361/Kconfig create mode 100644 board/comtrend/ct5361/MAINTAINERS create mode 100644 board/comtrend/ct5361/Makefile create mode 100644 board/comtrend/ct5361/ct-5361.c create mode 100644 configs/comtrend_ct5361_ram_defconfig create mode 100644 include/configs/comtrend_ct5361.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 4c02c48c111..9bab7446307 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb +dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts new file mode 100644 index 00000000000..c909a528a97 --- /dev/null +++ b/arch/mips/dts/comtrend,ct-5361.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6348.dtsi" + +/ { + model = "Comtrend CT-5361"; + compatible = "comtrend,ct-5361", "brcm,bcm6348"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "CT-5361:green:power"; + gpios = <&gpio0 0 1>; + }; + + alarm_red { + label = "CT-5361:red:alarm"; + gpios = <&gpio0 2 1>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index b7f7b1e2a5d..b9805874eac 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -65,6 +65,17 @@ config BOARD_COMTREND_AR5387UN depends on SOC_BMIPS_BCM6328 select BMIPS_SUPPORTS_BOOT_RAM +config BOARD_COMTREND_CT5361 + bool "Comtrend CT-5361" + depends on SOC_BMIPS_BCM6348 + select BMIPS_SUPPORTS_BOOT_RAM + help + Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB + of flash (CFI). + Between its different peripherals there's a BCM5325 switch with 4 + ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a + BCM4312 (miniPCI). + config BOARD_COMTREND_VR3032U bool "Comtrend VR-3032u board" depends on SOC_BMIPS_BCM63268 @@ -99,6 +110,7 @@ config BMIPS_SUPPORTS_BOOT_RAM bool source "board/comtrend/ar5387un/Kconfig" +source "board/comtrend/ct5361/Kconfig" source "board/comtrend/vr3032u/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/sfr/nb4_ser/Kconfig" diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig new file mode 100644 index 00000000000..d77d814db76 --- /dev/null +++ b/board/comtrend/ct5361/Kconfig @@ -0,0 +1,12 @@ +if BOARD_COMTREND_CT5361 + +config SYS_BOARD + default "ct5361" + +config SYS_VENDOR + default "comtrend" + +config SYS_CONFIG_NAME + default "comtrend_ct5361" + +endif diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS new file mode 100644 index 00000000000..aea737a0bbd --- /dev/null +++ b/board/comtrend/ct5361/MAINTAINERS @@ -0,0 +1,6 @@ +COMTREND CT-5361 BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/comtrend/ct-5361/ +F: include/configs/comtrend_ct5361.h +F: configs/comtrend_ct5361_ram_defconfig diff --git a/board/comtrend/ct5361/Makefile b/board/comtrend/ct5361/Makefile new file mode 100644 index 00000000000..872e80a0c17 --- /dev/null +++ b/board/comtrend/ct5361/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ct-5361.o diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/comtrend/ct5361/ct-5361.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig new file mode 100644 index 00000000000..9ec0c4158d7 --- /dev/null +++ b/configs/comtrend_ct5361_ram_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y +CONFIG_BCM6345_GPIO=y +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_COMTREND_CT5361=y +CONFIG_CFI_FLASH=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_FLASH=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y +CONFIG_SOC_BMIPS_BCM6348=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_PROMPT="CT-5361 # " +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_WDT=y +CONFIG_WDT_BCM6345=y diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h new file mode 100644 index 00000000000..099684ddd27 --- /dev/null +++ b/include/configs/comtrend_ct5361.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 -- cgit v1.3.1 From 23a2168398e1263473d362cc907b591ab8cf2eaf Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 16 May 2017 18:42:42 +0200 Subject: MIPS: add support for Broadcom MIPS BCM3380 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm3380.dtsi | 154 ++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++ include/configs/bmips_bcm3380.h | 25 +++++ include/dt-bindings/clock/bcm3380-clock.h | 23 +++++ include/dt-bindings/reset/bcm3380-reset.h | 16 ++++ 5 files changed, 230 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi create mode 100644 include/configs/bmips_bcm3380.h create mode 100644 include/dt-bindings/clock/bcm3380-clock.h create mode 100644 include/dt-bindings/reset/bcm3380-reset.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm3380.dtsi b/arch/mips/dts/brcm,bcm3380.dtsi new file mode 100644 index 00000000000..e351d5822e6 --- /dev/null +++ b/arch/mips/dts/brcm,bcm3380.dtsi @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm3380"; + + cpus { + reg = <0x14e00000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm3380-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm3380-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk0: periph-clk@14e00004 { + compatible = "brcm,bcm6345-clk"; + reg = <0x14e00004 0x4>; + #clock-cells = <1>; + }; + + periph_clk1: periph-clk@14e00008 { + compatible = "brcm,bcm6345-clk"; + reg = <0x14e00008 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + memory-controller@12000000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x12000000 0x1000>; + u-boot,dm-pre-reloc; + }; + + periph_rst0: reset-controller@14e0008c { + compatible = "brcm,bcm6345-reset"; + reg = <0x14e0008c 0x4>; + #reset-cells = <1>; + }; + + periph_rst1: reset-controller@14e00090 { + compatible = "brcm,bcm6345-reset"; + reg = <0x14e00090 0x4>; + #reset-cells = <1>; + }; + + pll_cntl: syscon@14e00094 { + compatible = "syscon"; + reg = <0x14e00094 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + wdt: watchdog@14e000dc { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e000dc 0xc>; + + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio0: gpio-controller@14e00100 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00100 0x4>, <0x14e00108 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@14e00104 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00104 0x4>, <0x14e0010c 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <3>; + + status = "disabled"; + }; + + uart0: serial@14e00200 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00200 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@14e00220 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00220 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + leds: led-controller@14e00f00 { + compatible = "brcm,bcm6328-leds"; + reg = <0x14e00f00 0x1c>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index b9805874eac..9cf8e5c1203 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -2,6 +2,7 @@ menu "Broadcom MIPS platforms" depends on ARCH_BMIPS config SYS_SOC + default "bcm3380" if SOC_BMIPS_BCM3380 default "bcm6328" if SOC_BMIPS_BCM6328 default "bcm6348" if SOC_BMIPS_BCM6348 default "bcm6358" if SOC_BMIPS_BCM6358 @@ -10,6 +11,17 @@ config SYS_SOC choice prompt "Broadcom MIPS SoC select" +config SOC_BMIPS_BCM3380 + bool "BMIPS BCM3380 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_WATCHDOG + help + This supports BMIPS BCM3380 family. + config SOC_BMIPS_BCM6328 bool "BMIPS BCM6328 family" select SUPPORTS_BIG_ENDIAN diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h new file mode 100644 index 00000000000..0c3f7f52859 --- /dev/null +++ b/include/configs/bmips_bcm3380.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM3380_H +#define __CONFIG_BMIPS_BCM3380_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/dt-bindings/clock/bcm3380-clock.h b/include/dt-bindings/clock/bcm3380-clock.h new file mode 100644 index 00000000000..00add2f226a --- /dev/null +++ b/include/dt-bindings/clock/bcm3380-clock.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from Broadcom GPL Source Code: + * Copyright (C) Broadcom Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM3380_H +#define __DT_BINDINGS_CLOCK_BCM3380_H + +#define BCM3380_CLK0_DDR 0 +#define BCM3380_CLK0_FPM 1 +#define BCM3380_CLK0_CRYPTO 2 +#define BCM3380_CLK0_EPHY 3 +#define BCM3380_CLK0_PCIE 16 +#define BCM3380_CLK0_SPI 17 +#define BCM3380_CLK0_ENET0 18 +#define BCM3380_CLK0_ENET1 19 +#define BCM3380_CLK0_PCM 27 + +#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */ diff --git a/include/dt-bindings/reset/bcm3380-reset.h b/include/dt-bindings/reset/bcm3380-reset.h new file mode 100644 index 00000000000..ddc575d92b7 --- /dev/null +++ b/include/dt-bindings/reset/bcm3380-reset.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from Broadcom GPL Source Code: + * Copyright (C) Broadcom Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM3380_H +#define __DT_BINDINGS_RESET_BCM3380_H + +#define BCM3380_RST0_SPI 0 +#define BCM3380_RST0_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM3380_H */ -- cgit v1.3.1 From c4203e1d73d8c56d64f9b92299f2f6a4547e4e4a Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 16 May 2017 18:42:43 +0200 Subject: MIPS: add BMIPS Netgear CG3100D board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/Makefile | 1 + arch/mips/dts/netgear,cg3100d.dts | 96 +++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++++ board/netgear/cg3100d/Kconfig | 12 +++++ board/netgear/cg3100d/MAINTAINERS | 6 +++ board/netgear/cg3100d/Makefile | 5 ++ board/netgear/cg3100d/cg3100d.c | 7 +++ configs/netgear_cg3100d_ram_defconfig | 56 ++++++++++++++++++++ include/configs/netgear_cg3100d.h | 15 ++++++ 9 files changed, 210 insertions(+) create mode 100644 arch/mips/dts/netgear,cg3100d.dts create mode 100644 board/netgear/cg3100d/Kconfig create mode 100644 board/netgear/cg3100d/MAINTAINERS create mode 100644 board/netgear/cg3100d/Makefile create mode 100644 board/netgear/cg3100d/cg3100d.c create mode 100644 configs/netgear_cg3100d_ram_defconfig create mode 100644 include/configs/netgear_cg3100d.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 9bab7446307..fdce645dfd2 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb +dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/netgear,cg3100d.dts b/arch/mips/dts/netgear,cg3100d.dts new file mode 100644 index 00000000000..db1e2e76164 --- /dev/null +++ b/arch/mips/dts/netgear,cg3100d.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm3380.dtsi" + +/ { + model = "Netgear CG3100D"; + compatible = "netgear,cg3100d", "brcm,bcm3380"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wifi_green { + label = "CG3100D:green:wifi"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + + wps_green { + label = "CG3100D:green:wps"; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + power_red { + label = "CG3100D:red:power"; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&leds { + status = "okay"; + + led@0 { + reg = <0>; + active-low; + label = "CG3100D:green:power"; + }; + + led@1 { + reg = <1>; + active-low; + label = "CG3100D:green:downlink"; + }; + + led@2 { + reg = <2>; + active-low; + label = "CG3100D:orange:downlink"; + }; + + led@3 { + reg = <3>; + active-low; + label = "CG3100D:green:uplink"; + }; + + led@4 { + reg = <4>; + active-low; + label = "CG3100D:orange:uplink"; + }; + + led@6 { + reg = <6>; + active-low; + label = "CG3100D:green:inet"; + }; + + led@7 { + reg = <7>; + active-low; + label = "CG3100D:green:stby"; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 9cf8e5c1203..e8494389ef1 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -98,6 +98,17 @@ config BOARD_HUAWEI_HG556A depends on SOC_BMIPS_BCM6358 select BMIPS_SUPPORTS_BOOT_RAM +config BOARD_NETGEAR_CG3100D + bool "Netgear CG3100D" + depends on SOC_BMIPS_BCM3380 + select BMIPS_SUPPORTS_BOOT_RAM + help + Netgear CG3100D boards have a BCM3380 SoC with 64 MB of RAM and 8 MB + of flash (SPI). + Between its different peripherals there's a BCM53115 switch with 4 + ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 + (miniPCIe). + config BOARD_SFR_NB4_SER bool "SFR NeufBox 4 (Sercomm)" depends on SOC_BMIPS_BCM6358 @@ -125,6 +136,7 @@ source "board/comtrend/ar5387un/Kconfig" source "board/comtrend/ct5361/Kconfig" source "board/comtrend/vr3032u/Kconfig" source "board/huawei/hg556a/Kconfig" +source "board/netgear/cg3100d/Kconfig" source "board/sfr/nb4_ser/Kconfig" endmenu diff --git a/board/netgear/cg3100d/Kconfig b/board/netgear/cg3100d/Kconfig new file mode 100644 index 00000000000..632c22d1f7a --- /dev/null +++ b/board/netgear/cg3100d/Kconfig @@ -0,0 +1,12 @@ +if BOARD_NETGEAR_CG3100D + +config SYS_BOARD + default "cg3100d" + +config SYS_VENDOR + default "netgear" + +config SYS_CONFIG_NAME + default "netgear_cg3100d" + +endif diff --git a/board/netgear/cg3100d/MAINTAINERS b/board/netgear/cg3100d/MAINTAINERS new file mode 100644 index 00000000000..f1dcb1f62fd --- /dev/null +++ b/board/netgear/cg3100d/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR CG3100D BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/netgear/cg3100d/ +F: include/configs/netgear_cg3100d.h +F: configs/netgear_cg3100d_ram_defconfig diff --git a/board/netgear/cg3100d/Makefile b/board/netgear/cg3100d/Makefile new file mode 100644 index 00000000000..b82e59ee36f --- /dev/null +++ b/board/netgear/cg3100d/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cg3100d.o diff --git a/board/netgear/cg3100d/cg3100d.c b/board/netgear/cg3100d/cg3100d.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/netgear/cg3100d/cg3100d.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig new file mode 100644 index 00000000000..a6eff10b6af --- /dev/null +++ b/configs/netgear_cg3100d_ram_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y +CONFIG_BCM6345_GPIO=y +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_NETGEAR_CG3100D=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y +CONFIG_SOC_BMIPS_BCM3380=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_NO_FLASH=y +CONFIG_SYS_PROMPT="CG3100D # " +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_WDT=y +CONFIG_WDT_BCM6345=y diff --git a/include/configs/netgear_cg3100d.h b/include/configs/netgear_cg3100d.h new file mode 100644 index 00000000000..c97d4e57ed2 --- /dev/null +++ b/include/configs/netgear_cg3100d.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP -- cgit v1.3.1 From 07661e7f5080a76e62c2b1a4b103ce23b293fbb6 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 16 May 2017 18:46:58 +0200 Subject: MIPS: add support for Broadcom MIPS BCM6338 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/brcm,bcm6338.dtsi | 118 ++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++ arch/mips/mach-bmips/include/ioremap.h | 3 +- include/configs/bmips_bcm6338.h | 30 ++++++++ include/dt-bindings/clock/bcm6338-clock.h | 19 +++++ include/dt-bindings/reset/bcm6338-reset.h | 22 ++++++ 6 files changed, 203 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/brcm,bcm6338.dtsi create mode 100644 include/configs/bmips_bcm6338.h create mode 100644 include/dt-bindings/clock/bcm6338-clock.h create mode 100644 include/dt-bindings/reset/bcm6338-reset.h (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi new file mode 100644 index 00000000000..eb51a4372bd --- /dev/null +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6338"; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6338-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; + }; + + pflash: nor@1fc00000 { + compatible = "cfi-flash"; + reg = <0x1fc00000 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@fffe0028 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0028 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@fffe021c { + compatible = "brcm,bcm6345-wdt"; + reg = <0xfffe021c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + uart0: serial@fffe0300 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0300 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + gpio: gpio-controller@fffe0404 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + memory-controller@fffe3100 { + compatible = "brcm,bcm6338-mc"; + reg = <0xfffe3100 0x38>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e8494389ef1..7071888bb38 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -4,6 +4,7 @@ menu "Broadcom MIPS platforms" config SYS_SOC default "bcm3380" if SOC_BMIPS_BCM3380 default "bcm6328" if SOC_BMIPS_BCM6328 + default "bcm6338" if SOC_BMIPS_BCM6338 default "bcm6348" if SOC_BMIPS_BCM6348 default "bcm6358" if SOC_BMIPS_BCM6358 default "bcm63268" if SOC_BMIPS_BCM63268 @@ -33,6 +34,17 @@ config SOC_BMIPS_BCM6328 help This supports BMIPS BCM6328 family including BCM63281 and BCM63283. +config SOC_BMIPS_BCM6338 + bool "BMIPS BCM6338 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6338 family. + config SOC_BMIPS_BCM6348 bool "BMIPS BCM6348 family" select SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h index d3dc0b817e5..a57f55d1b40 100644 --- a/arch/mips/mach-bmips/include/ioremap.h +++ b/arch/mips/mach-bmips/include/ioremap.h @@ -18,7 +18,8 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, static inline int is_bmips_internal_registers(phys_addr_t offset) { -#if defined(CONFIG_SOC_BMIPS_BCM6348) || \ +#if defined(CONFIG_SOC_BMIPS_BCM6338) || \ + defined(CONFIG_SOC_BMIPS_BCM6348) || \ defined(CONFIG_SOC_BMIPS_BCM6358) if (offset >= 0xfffe0000) return 1; diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h new file mode 100644 index 00000000000..52d72c87e51 --- /dev/null +++ b/include/configs/bmips_bcm6338.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6338_H +#define __CONFIG_BMIPS_BCM6338_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 120000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/include/dt-bindings/clock/bcm6338-clock.h b/include/dt-bindings/clock/bcm6338-clock.h new file mode 100644 index 00000000000..3439c10062b --- /dev/null +++ b/include/dt-bindings/clock/bcm6338-clock.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6338_H +#define __DT_BINDINGS_CLOCK_BCM6338_H + +#define BCM6338_CLK_ADSL 0 +#define BCM6338_CLK_MPI 1 +#define BCM6338_CLK_SDRAM 2 +#define BCM6338_CLK_ENET 4 +#define BCM6338_CLK_SAR 5 +#define BCM6338_CLK_SPI 9 + +#endif /* __DT_BINDINGS_CLOCK_BCM6338_H */ diff --git a/include/dt-bindings/reset/bcm6338-reset.h b/include/dt-bindings/reset/bcm6338-reset.h new file mode 100644 index 00000000000..17a5e121e8b --- /dev/null +++ b/include/dt-bindings/reset/bcm6338-reset.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6338_H +#define __DT_BINDINGS_RESET_BCM6338_H + +#define BCM6338_RST_SPI 0 +#define BCM6338_RST_ENET 2 +#define BCM6338_RST_USBH 3 +#define BCM6338_RST_USBS 4 +#define BCM6338_RST_ADSL 5 +#define BCM6338_RST_DMAMEM 6 +#define BCM6338_RST_SAR 7 +#define BCM6338_RST_ACLC 8 +#define BCM6338_RST_ADSL_MIPS 10 + +#endif /* __DT_BINDINGS_RESET_BCM6338_H */ -- cgit v1.3.1 From 8df378888774862b14e956524c7e4545b2b07411 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 16 May 2017 18:46:59 +0200 Subject: MIPS: add BMIPS Sagem F@ST1704 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- arch/mips/dts/Makefile | 1 + arch/mips/dts/sagem,f@st1704.dts | 50 ++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++++++++ board/sagem/f@st1704/Kconfig | 12 +++++++++ board/sagem/f@st1704/MAINTAINERS | 6 +++++ board/sagem/f@st1704/Makefile | 5 ++++ board/sagem/f@st1704/f@st1704.c | 7 +++++ configs/sagem_f@st1704_ram_defconfig | 52 ++++++++++++++++++++++++++++++++++++ include/configs/sagem_f@st1704.h | 15 +++++++++++ 9 files changed, 160 insertions(+) create mode 100644 arch/mips/dts/sagem,f@st1704.dts create mode 100644 board/sagem/f@st1704/Kconfig create mode 100644 board/sagem/f@st1704/MAINTAINERS create mode 100644 board/sagem/f@st1704/Makefile create mode 100644 board/sagem/f@st1704/f@st1704.c create mode 100644 configs/sagem_f@st1704_ram_defconfig create mode 100644 include/configs/sagem_f@st1704.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index fdce645dfd2..a190485ded6 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts new file mode 100644 index 00000000000..be15fe55519 --- /dev/null +++ b/arch/mips/dts/sagem,f@st1704.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6338.dtsi" + +/ { + model = "Sagem F@ST1704"; + compatible = "sagem,f@st1704", "brcm,bcm6338"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "F@ST1704:green:inet"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + + power_green { + label = "F@ST1704:green:power"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + inet_red { + label = "F@ST1704:red:inet"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 7071888bb38..fe19ced3731 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -121,6 +121,17 @@ config BOARD_NETGEAR_CG3100D ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 (miniPCIe). +config BOARD_SAGEM_FAST1704 + bool "Sagem F@ST1704" + depends on SOC_BMIPS_BCM6338 + select BMIPS_SUPPORTS_BOOT_RAM + help + Sagem F@ST1704 boards have a BCM6338 SoC with 16 MB of RAM and 4 MB + of flash (SPI). + Between its different peripherals there's a BCM5325 switch with 4 + ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM4312 + (miniPCI). + config BOARD_SFR_NB4_SER bool "SFR NeufBox 4 (Sercomm)" depends on SOC_BMIPS_BCM6358 @@ -149,6 +160,7 @@ source "board/comtrend/ct5361/Kconfig" source "board/comtrend/vr3032u/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/netgear/cg3100d/Kconfig" +source "board/sagem/f@st1704/Kconfig" source "board/sfr/nb4_ser/Kconfig" endmenu diff --git a/board/sagem/f@st1704/Kconfig b/board/sagem/f@st1704/Kconfig new file mode 100644 index 00000000000..4566fcc9c5d --- /dev/null +++ b/board/sagem/f@st1704/Kconfig @@ -0,0 +1,12 @@ +if BOARD_SAGEM_FAST1704 + +config SYS_BOARD + default "f@st1704" + +config SYS_VENDOR + default "sagem" + +config SYS_CONFIG_NAME + default "sagem_f@st1704" + +endif diff --git a/board/sagem/f@st1704/MAINTAINERS b/board/sagem/f@st1704/MAINTAINERS new file mode 100644 index 00000000000..72e1c5ccd06 --- /dev/null +++ b/board/sagem/f@st1704/MAINTAINERS @@ -0,0 +1,6 @@ +SAGEM F@ST1704 BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/sagem/f@st1704/ +F: include/configs/sagem_f@st1704.h +F: configs/sagem_f@st1704_ram_defconfig diff --git a/board/sagem/f@st1704/Makefile b/board/sagem/f@st1704/Makefile new file mode 100644 index 00000000000..a5f97f804e3 --- /dev/null +++ b/board/sagem/f@st1704/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += f@st1704.o diff --git a/board/sagem/f@st1704/f@st1704.c b/board/sagem/f@st1704/f@st1704.c new file mode 100644 index 00000000000..d181ca68a04 --- /dev/null +++ b/board/sagem/f@st1704/f@st1704.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig new file mode 100644 index 00000000000..8e89c1548c0 --- /dev/null +++ b/configs/sagem_f@st1704_ram_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y +CONFIG_BCM6345_GPIO=y +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_SAGEM_FAST1704=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y +CONFIG_SOC_BMIPS_BCM6338=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_NO_FLASH=y +CONFIG_SYS_PROMPT="F@ST1704 # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/sagem_f@st1704.h b/include/configs/sagem_f@st1704.h new file mode 100644 index 00000000000..dbc7725796c --- /dev/null +++ b/include/configs/sagem_f@st1704.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP -- cgit v1.3.1 From f530eb9e9e2194efb9f5dde2e47c2214aad1c633 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Mon, 22 May 2017 20:02:06 +0200 Subject: mips: bmips: extend baud rates support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that the uart driver has been fixed we support more baud rates. Signed-off-by: Álvaro Fernández Rojas --- include/configs/bmips_common.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index d2b05d44c8b..38bf7a272be 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -7,6 +7,10 @@ #ifndef __CONFIG_BMIPS_COMMON_H #define __CONFIG_BMIPS_COMMON_H +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } + /* RAM */ #define CONFIG_SYS_MEMTEST_START 0xa0000000 #define CONFIG_SYS_MEMTEST_END 0xa2000000 -- cgit v1.3.1