From 0a9e4e772123fe3e2bb499d7d2160c4cfd8a3a8d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 24 Jul 2009 16:34:32 -0400 Subject: unify {CONFIG_,}ENV_IS_EMBEDDED Some boards have fallen out of sync by defining CONFIG_ENV_IS_EMBEDDED manually. While it is useful to have this available to the build system, let's do it automatically rather than forcing people to opt into it. Signed-off-by: Mike Frysinger Signed-off-by: Albin Tonnerre Signed-off-by: Wolfgang Denk --- include/configs/M52277EVB.h | 1 - include/configs/M5235EVB.h | 1 - include/configs/M5272C3.h | 1 - include/configs/M5275EVB.h | 1 - include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/M54451EVB.h | 1 - include/configs/M54455EVB.h | 1 - include/configs/M5475EVB.h | 1 - include/configs/M5485EVB.h | 1 - include/configs/OXC.h | 1 - include/configs/cobra5272.h | 1 - include/configs/pcu_e.h | 1 - include/environment.h | 34 ++++++++++++++++++++++++++++------ 14 files changed, 28 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index e7db0cc108b..1801d9d7d58 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -255,7 +255,6 @@ # define CONFIG_ENV_IS_IN_FLASH 1 #endif #define CONFIG_ENV_OVERWRITE 1 -#undef CONFIG_ENV_IS_EMBEDDED /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 6b26c0bbc21..2b816ceae2b 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -222,7 +222,6 @@ * Environment is embedded in u-boot in the second sector of the flash */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 #ifdef NORFLASH_PS32BIT # define CONFIG_ENV_OFFSET (0x8000) # define CONFIG_ENV_SIZE 0x4000 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index fc73d640918..f824158a697 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -55,7 +55,6 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 #else #define CONFIG_ENV_ADDR 0xffe04000 #define CONFIG_ENV_SECT_SIZE 0x2000 diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 210bb2deff6..b3801598128 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -55,7 +55,6 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 #else #define CONFIG_ENV_ADDR 0xffe04000 #define CONFIG_ENV_SECT_SIZE 0x2000 diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index a2d17c361c5..8180c05e67f 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -231,7 +231,6 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 98d800f3105..8652a80aa11 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -231,7 +231,6 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index fa444c39eee..a5acfd28460 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -277,7 +277,6 @@ # define CONFIG_ENV_SECT_SIZE 0x8000 #endif #undef CONFIG_ENV_OVERWRITE -#undef CONFIG_ENV_IS_EMBEDDED /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 14d98d69c8a..7737284aab6 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -332,7 +332,6 @@ # define CONFIG_ENV_IS_IN_FLASH 1 #endif #undef CONFIG_ENV_OVERWRITE -#undef CONFIG_ENV_IS_EMBEDDED /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index e48de15f79a..4534002e473 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -280,7 +280,6 @@ #define CONFIG_ENV_OFFSET 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 28bf0adcf3f..971cb67bad1 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -266,7 +266,6 @@ #define CONFIG_ENV_OFFSET 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/OXC.h b/include/configs/OXC.h index 104c23f9284..74c51f46b29 100644 --- a/include/configs/OXC.h +++ b/include/configs/OXC.h @@ -196,7 +196,6 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */ #define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ #define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */ /* diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index fb32f3f3c05..1c3ea23c777 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -127,7 +127,6 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 #else #define CONFIG_ENV_ADDR 0xffe04000 #define CONFIG_ENV_SECT_SIZE 0x2000 diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 7c2bf1b0f4e..65173811706 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -231,7 +231,6 @@ #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ #define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ #else /* Final version: environment in EEPROM */ #define CONFIG_ENV_IS_IN_EEPROM 1 diff --git a/include/environment.h b/include/environment.h index 5bed32fd479..b9924fd7789 100644 --- a/include/environment.h +++ b/include/environment.h @@ -67,6 +67,10 @@ # if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND) # define CONFIG_SYS_REDUNDAND_ENVIRONMENT 1 # endif +# ifdef CONFIG_ENV_IS_EMBEDDED +# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config" +# error "it is calculated automatically for you" +# endif #endif /* CONFIG_ENV_IS_IN_FLASH */ #if defined(CONFIG_ENV_IS_IN_NAND) @@ -79,9 +83,6 @@ # ifdef CONFIG_ENV_OFFSET_REDUND # define CONFIG_SYS_REDUNDAND_ENVIRONMENT # endif -# ifdef CONFIG_ENV_IS_EMBEDDED -# define ENV_IS_EMBEDDED 1 -# endif #endif /* CONFIG_ENV_IS_IN_NAND */ #if defined(CONFIG_ENV_IS_IN_MG_DISK) @@ -91,11 +92,32 @@ # ifndef CONFIG_ENV_SIZE # error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_MG_DISK" # endif -# ifdef CONFIG_ENV_IS_EMBEDDED -# error "CONFIG_ENV_IS_EMBEDDED not supported when using CONFIG_ENV_IS_IN_MG_DISK" -# endif #endif /* CONFIG_ENV_IS_IN_MG_DISK */ +/* Embedded env is only supported for some flash types */ +#ifdef CONFIG_ENV_IS_EMBEDDED +# if !defined(CONFIG_ENV_IS_IN_FLASH) && \ + !defined(CONFIG_ENV_IS_IN_NAND) && \ + !defined(CONFIG_ENV_IS_IN_ONENAND) +# error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type" +# endif +#endif + +/* + * For the flash types where embedded env is supported, but it cannot be + * calculated automatically (i.e. NAND), take the board opt-in. + */ +#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED) +# define ENV_IS_EMBEDDED 1 +#endif + +/* The build system likes to know if the env is embedded */ +#ifdef DO_DEPS_ONLY +# ifdef ENV_IS_EMBEDDED +# define CONFIG_ENV_IS_EMBEDDED +# endif +#endif + #include "compiler.h" #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT -- cgit v1.3.1 From 5b53b29bc2e82b80b669f1d2402068c60d7fecd0 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Thu, 13 Aug 2009 10:14:21 -0500 Subject: Add support for the galaxy5200 Add support for the DEKA Research and Development galaxy5200 board The galaxy5200 is an Freescale mpc5200 based embedded industrial control board. Signed-off-by: Eric Millbrandt --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 6 + board/galaxy5200/Makefile | 50 +++++ board/galaxy5200/config.mk | 45 +++++ board/galaxy5200/galaxy5200.c | 199 ++++++++++++++++++++ include/configs/galaxy5200.h | 428 ++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 733 insertions(+) create mode 100644 board/galaxy5200/Makefile create mode 100644 board/galaxy5200/config.mk create mode 100644 board/galaxy5200/galaxy5200.c create mode 100644 include/configs/galaxy5200.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 620604c189d..85ba8d28da7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -616,6 +616,10 @@ David M smdk2410 ARM920T VCMA9 ARM920T +Eric Millbrandt + + galaxy5200 mpc5200 + Rolf Offermanns shannon SA1100 diff --git a/MAKEALL b/MAKEALL index edebaead3cb..65cd6d0f57a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -50,6 +50,7 @@ LIST_5xxx=" \ digsy_mtc \ EVAL5200 \ fo300 \ + galaxy5200 \ icecube_5100 \ icecube_5200 \ inka4x0 \ diff --git a/Makefile b/Makefile index 02393b680b2..2fa43a57a84 100644 --- a/Makefile +++ b/Makefile @@ -544,6 +544,12 @@ digsy_mtc_RAMBOOT_config: unconfig } @$(MKCONFIG) -a digsy_mtc ppc mpc5xxx digsy_mtc +galaxy5200_LOWBOOT_config \ +galaxy5200_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h + @$(MKCONFIG) -a galaxy5200 ppc mpc5xxx galaxy5200 + hmi1001_config: unconfig @$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001 diff --git a/board/galaxy5200/Makefile b/board/galaxy5200/Makefile new file mode 100644 index 00000000000..22ce8e64f29 --- /dev/null +++ b/board/galaxy5200/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/galaxy5200/config.mk b/board/galaxy5200/config.mk new file mode 100644 index 00000000000..c6398b26e26 --- /dev/null +++ b/board/galaxy5200/config.mk @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# galaxy5200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFE000000 boot low +# 0x00100000 boot from RAM (for testing only) does not work +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifdef CONFIG_galaxy5200_LOWBOOT +TEXT_BASE = 0xFE000000 +endif + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c new file mode 100644 index 00000000000..5aa9d3a6f10 --- /dev/null +++ b/board/galaxy5200/galaxy5200.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messtechnik GmbH + * + * (C) Copyright 2009 + * Eric Millbrandt, DEKA Research and Development Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start(int hi_addr) +{ + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *)MPC5XXX_CDM; + volatile struct mpc5xxx_sdram *sdram = + (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); + + /* precharge all banks */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); + +#ifdef SDRAM_DDR + /* set mode register: extended mode */ + out_be32 (&sdram->mode, (SDRAM_EMODE)); + + /* set mode register: reset DLL */ + out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000)); +#endif + + /* precharge all banks */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); + + /* auto refresh */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); + + /* set mode register */ + out_be32 (&sdram->mode, (SDRAM_MODE)); + + /* normal operation */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | hi_addr_bit)); + + /* set CDM clock enable register, set MPC5200B SDRAM bus */ + /* to reduced driver strength */ + out_be32 (&cdm->clock_enable, (0x00CFFFFF)); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make + * real use of CONFIG_SYS_SDRAM_BASE. The code does not + * work if CONFIG_SYS_SDRAM_BASE + * is something else than 0x00000000. + */ + +phys_size_t initdram(int board_type) +{ + volatile struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + volatile struct mpc5xxx_sdram *sdram = + (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + /* 256MB at 0x0 */ + out_be32 (&mm->sdram0, 0x0000001b); + /* disabled */ + out_be32 (&mm->sdram1, 0x10000000); + + /* setup config registers */ + out_be32 (&sdram->config1, SDRAM_CONFIG1); + out_be32 (&sdram->config2, SDRAM_CONFIG2); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); + sdram_start(1); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32 (&mm->sdram0, + (0x13 + __builtin_ffs(dramsize >> 20) - 1)); + } else { + /* disabled */ + out_be32 (&mm->sdram0, 0); + } + +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32(&mm->sdram0) & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = in_be32(&mm->sdram1) & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CONFIG_SYS_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard(void) +{ + puts("Board: galaxy5200\n"); + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t * bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; + debug ("init_ide_reset\n"); + + /* Configure TIMER_5 as GPIO output for ATA reset */ + /* Deassert reset */ + gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO; +} + +void ide_set_reset (int idereset) +{ + volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; + debug ("ide_reset(%d)\n", idereset); + + /* Configure TIMER_5 as GPIO output for ATA reset */ + if (idereset) { + gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO; + + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(50); + } else { + gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO; + udelay(50); + } +} +#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h new file mode 100644 index 00000000000..e9a45699685 --- /dev/null +++ b/include/configs/galaxy5200.h @@ -0,0 +1,428 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messatechnik GmbH + * + * (C) Copyright 2009 + * Jon Smirl + * + * (C) Copyright 2009 + * Eric Millbrandt, DEKA Research and Development Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_BOARDINFO "galaxy5200" + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */ + /* define gps port conf. */ + /* register later on to */ + /* enable UART function! */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_PING +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_USB +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_FAT + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFE000000) /* Boot low */ +#define CONFIG_SYS_LOWBOOT 1 +#endif +/* RAMBOOT will be defined automatically in memory section */ + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ + "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ + /* even with bootdelay=0 */ +#undef CONFIG_BOOTARGS + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to U-Boot"\ + "echo" + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CONFIG_SYS_XLB_PIPELINING 1 + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM CAT24WC32 configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ +#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_SIZE 4096 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Flash configuration + */ + +#define CONFIG_SYS_FLASH_BASE 0xfe000000 +/* + * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this + * variable defined + */ +#define CONFIG_SYS_FLASH_SIZE 0x02000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ + /* (= chip selects) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* + * Use hardware protection. This seems required, as the BDI uses hardware + * protection. Without this, U-Boot can't work with this sectors as its + * protection is software only by default. + */ +#define CONFIG_SYS_FLASH_PROTECTION 1 + +/* + * Environment settings + */ + +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ + /* beginning of the EEPROM */ +#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE + +#define CONFIG_ENV_OVERWRITE 1 + +/* + * SDRAM configuration + */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x71500F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x47770000 + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ + /* bootloader or debugger config */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM + +/* End of used area in SPRAM */ +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE + +/* Size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Chip Select configuration for NAND flash */ +#define CONFIG_SYS_CS1_START 0x20000000 +#define CONFIG_SYS_CS1_SIZE 0x90000 +#define CONFIG_SYS_CS1_CFG 0x0002d900 + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x01 +#define CONFIG_NO_AUTOLOAD 1 + +/* + * GPIO configuration + * + * GPS port configuration + * + * [29:31] = 01x + * AC97 on PSC1 + * PSC1_0 -> AC97 SDATA out + * PSC1_1 -> AC97 SDTA in + * PSC1_2 -> AC97 SYNC out + * PSC1_3 -> AC97 bitclock out + * PSC1_4 -> AC97 reset out + * + * [28] = Reserved + * + * [25:27] = 110 + * SPI on PSC2 + * PSC2_0 -> MOSI + * PSC2_1 -> MISO + * PSC2_2 -> n/a + * PSC2_3 -> CLK + * PSC2_4 -> SS + * + * [24] = Reserved + * + * [20:23] = 0001 + * USB on PSC3 + * PSC3_0 -> USB_OE OE out + * PSC3_1 -> USB_TXN Tx- out + * PSC3_2 -> USB_TXP Tx+ out + * PSC3_3 -> USB_TXD + * PSC3_4 -> USB_RXP Rx+ in + * PSC3_5 -> USB_RXN Rx- in + * PSC3_6 -> USB_PWR PortPower out + * PSC3_7 -> USB_SPEED speed out + * PSC3_8 -> USB_SUSPEND suspend + * PSC3_9 -> USB_OVRCURNT overcurrent in + * + * [18:19] = 10 + * Two UARTs + * + * [17] = 0 + * USB differential mode + * + * [16] = 1 + * PCI disabled + * + * [12:15] = 0101 + * Ethernet 100Mbit with MD + * ETH_0 -> ETH Txen + * ETH_1 -> ETH TxD0 + * ETH_2 -> ETH TxD1 + * ETH_3 -> ETH TxD2 + * ETH_4 -> ETH TxD3 + * ETH_5 -> ETH Txerr + * ETH_6 -> ETH MDC + * ETH_7 -> ETH MDIO + * ETH_8 -> ETH RxDv + * ETH_9 -> ETH RxCLK + * ETH_10 -> ETH Collision + * ETH_11 -> ETH TxD + * ETH_12 -> ETH RxD0 + * ETH_13 -> ETH RxD1 + * ETH_14 -> ETH RxD2 + * ETH_15 -> ETH RxD3 + * ETH_16 -> ETH Rxerr + * ETH_17 -> ETH CRS + * + * [9:11] = 111 + * SPI on PSC6 + * PSC6_0 -> MISO + * PSC6_1 -> SS# + * PSC6_2 -> MOSI + * PSC6_3 -> CLK + * + * [8] = 0 + * IrDA/USB 48MHz clock generated internally + * + * [6:7] = 01 + * ATA chip selects on csb_4/5 + * CSB_4 -> ATA_CS0 out + * CSB_5 -> ATA_CS1 out + * + * [5] = 1 + * PSC3_4 is used as CS6 + * + * [4] = 1 + * PSC3_5 is used as CS7 + * + * [2:3] = 00 + * No Alternatives + * + * [1] = 0 + * gpio_wkup_7 is GPIO + * + * [0] = 0 + * gpio_wkup_6 is GPIO + * + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CRC32_VERIFY 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +/* + * Various low-level settings + */ +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +/* no burst access on the LPB */ +#define CONFIG_SYS_CS_BURST 0x00000000 +/* one deadcycle for the 33MHz statemachine */ +#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 + +#define CONFIG_SYS_BOOTCS_CFG 0x0002d900 +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE + +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 + +/* + * USB settings + */ +#define CONFIG_USB_CLOCK 0x0001bbbb +/* USB is on PSC3 */ +#define CONFIG_PSC3_USB +#define CONFIG_USB_CONFIG 0x00000100 +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* + * IDE/ATA stuff Supports IDE harddisk + */ +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ +#define CONFIG_IDE_PREINIT +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 +#define CONFIG_ATAPI 1 + +/* we enable IDE and FAT support, so we also need partition support */ +#define CONFIG_DOS_PARTITION 1 + +/* + * Open Firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN +#define OF_SOC "soc5200@f0000000" +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From e84aba135ed7145299304ef550e92f08b2c99d7a Mon Sep 17 00:00:00 2001 From: Albin Tonnerre Date: Thu, 13 Aug 2009 15:31:11 +0200 Subject: Replace BCD2BIN and BIN2BCD macros with inline functions In the process, also remove backward-compatiblity macros BIN_TO_BCD and BCD_TO_BIN and update the sole board using them to use the new bin2bcd and bcd2bin instead Signed-off-by: Albin Tonnerre Acked-by: Stefan Roese Acked-by: Detlev Zundel --- board/rsdproto/rsdproto.c | 17 ++++++++--------- drivers/rtc/m41t62.c | 24 ++++++++++++------------ drivers/rtc/rtc4543.c | 28 ++++++++++++++-------------- drivers/rtc/s3c44b0_rtc.c | 42 +++++++++++++++++++++--------------------- drivers/rtc/x1205.c | 28 ++++++++++++++-------------- include/bcd.h | 19 ++++++++++++------- include/linux/mc146818rtc.h | 12 ------------ 7 files changed, 81 insertions(+), 89 deletions(-) (limited to 'include') diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c index 26edb2e4f8c..10759b79ca3 100644 --- a/board/rsdproto/rsdproto.c +++ b/board/rsdproto/rsdproto.c @@ -26,6 +26,7 @@ #include #include #include +#include /* define to initialise the SDRAM on the local bus */ #undef INIT_LOCAL_BUS_SDRAM @@ -208,16 +209,14 @@ void read_RS5C372_time (struct tm *timedate) { unsigned char buffer[8]; -#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) - if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { - timedate->tm_sec = BCD_TO_BIN (buffer[0]); - timedate->tm_min = BCD_TO_BIN (buffer[1]); - timedate->tm_hour = BCD_TO_BIN (buffer[2]); - timedate->tm_wday = BCD_TO_BIN (buffer[3]); - timedate->tm_mday = BCD_TO_BIN (buffer[4]); - timedate->tm_mon = BCD_TO_BIN (buffer[5]); - timedate->tm_year = BCD_TO_BIN (buffer[6]) + 2000; + timedate->tm_sec = bcd2bin (buffer[0]); + timedate->tm_min = bcd2bin (buffer[1]); + timedate->tm_hour = bcd2bin (buffer[2]); + timedate->tm_wday = bcd2bin (buffer[3]); + timedate->tm_mday = bcd2bin (buffer[4]); + timedate->tm_mon = bcd2bin (buffer[5]); + timedate->tm_year = bcd2bin (buffer[6]) + 2000; } else { /*printf("i2c error %02x\n", rc); */ memset (timedate, 0, sizeof (struct tm)); diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index cfe84f926be..3d7bb46b0e6 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -76,16 +76,16 @@ int rtc_get(struct rtc_time *tm) buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); - tm->tm_sec = BCD2BIN(buf[M41T62_REG_SEC] & 0x7f); - tm->tm_min = BCD2BIN(buf[M41T62_REG_MIN] & 0x7f); - tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f); - tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f); + tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f); + tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f); + tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f); + tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f); tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; - tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f); + tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f); /* assume 20YY not 19YY, and ignore the Century Bit */ /* U-Boot needs to add 1900 here */ - tm->tm_year = BCD2BIN(buf[M41T62_REG_YEAR]) + 100 + 1900; + tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900; debug("%s: tm is secs=%d, mins=%d, hours=%d, " "mday=%d, mon=%d, year=%d, wday=%d\n", @@ -109,19 +109,19 @@ int rtc_set(struct rtc_time *tm) /* Merge time-data and register flags into buf[0..7] */ buf[M41T62_REG_SSEC] = 0; buf[M41T62_REG_SEC] = - BIN2BCD(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f); + bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f); buf[M41T62_REG_MIN] = - BIN2BCD(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f); + bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f); buf[M41T62_REG_HOUR] = - BIN2BCD(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ; + bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ; buf[M41T62_REG_WDAY] = (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07); buf[M41T62_REG_DAY] = - BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); + bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); buf[M41T62_REG_MON] = - BIN2BCD(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f); + bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ - buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); + buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100); if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); diff --git a/drivers/rtc/rtc4543.c b/drivers/rtc/rtc4543.c index 242d9bcad79..b60e37d5be7 100644 --- a/drivers/rtc/rtc4543.c +++ b/drivers/rtc/rtc4543.c @@ -49,13 +49,13 @@ int rtc_get(struct rtc_time *tm) /* Read 52 bits into our buffer */ tws_read(buffer, 52); - tm->tm_sec = BCD2BIN( buffer[0] & 0x7F); - tm->tm_min = BCD2BIN( buffer[1] & 0x7F); - tm->tm_hour = BCD2BIN( buffer[2] & 0x3F); - tm->tm_wday = BCD2BIN( buffer[3] & 0x07); - tm->tm_mday = BCD2BIN((buffer[3] & 0xF0) >> 4 | (buffer[4] & 0x0F) << 4); - tm->tm_mon = BCD2BIN((buffer[4] & 0x30) >> 4 | (buffer[5] & 0x0F) << 4); - tm->tm_year = BCD2BIN((buffer[5] & 0xF0) >> 4 | (buffer[6] & 0x0F) << 4) + 2000; + tm->tm_sec = bcd2bin( buffer[0] & 0x7F); + tm->tm_min = bcd2bin( buffer[1] & 0x7F); + tm->tm_hour = bcd2bin( buffer[2] & 0x3F); + tm->tm_wday = bcd2bin( buffer[3] & 0x07); + tm->tm_mday = bcd2bin((buffer[3] & 0xF0) >> 4 | (buffer[4] & 0x0F) << 4); + tm->tm_mon = bcd2bin((buffer[4] & 0x30) >> 4 | (buffer[5] & 0x0F) << 4); + tm->tm_year = bcd2bin((buffer[5] & 0xF0) >> 4 | (buffer[6] & 0x0F) << 4) + 2000; tm->tm_yday = 0; tm->tm_isdst = 0; @@ -81,17 +81,17 @@ int rtc_set(struct rtc_time *tm) tm->tm_hour, tm->tm_min, tm->tm_sec); memset(buffer, 0, 7); - buffer[0] = BIN2BCD(tm->tm_sec); - buffer[1] = BIN2BCD(tm->tm_min); - buffer[2] = BIN2BCD(tm->tm_hour); - buffer[3] = BIN2BCD(tm->tm_wday); - tmp = BIN2BCD(tm->tm_mday); + buffer[0] = bin2bcd(tm->tm_sec); + buffer[1] = bin2bcd(tm->tm_min); + buffer[2] = bin2bcd(tm->tm_hour); + buffer[3] = bin2bcd(tm->tm_wday); + tmp = bin2bcd(tm->tm_mday); buffer[3] |= (tmp & 0x0F) << 4; buffer[4] = (tmp & 0xF0) >> 4; - tmp = BIN2BCD(tm->tm_mon); + tmp = bin2bcd(tm->tm_mon); buffer[4] |= (tmp & 0x0F) << 4; buffer[5] = (tmp & 0xF0) >> 4; - tmp = BIN2BCD(tm->tm_year % 100); + tmp = bin2bcd(tm->tm_year % 100); buffer[5] |= (tmp & 0x0F) << 4; buffer[6] = (tmp & 0xF0) >> 4; diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c index bfb744aef14..a027fb1263b 100644 --- a/drivers/rtc/s3c44b0_rtc.c +++ b/drivers/rtc/s3c44b0_rtc.c @@ -37,24 +37,24 @@ int rtc_get (struct rtc_time* tm) { RTCCON |= 1; - tm->tm_year = BCD2BIN(BCDYEAR); - tm->tm_mon = BCD2BIN(BCDMON); - tm->tm_wday = BCD2BIN(BCDDATE); - tm->tm_mday = BCD2BIN(BCDDAY); - tm->tm_hour = BCD2BIN(BCDHOUR); - tm->tm_min = BCD2BIN(BCDMIN); - tm->tm_sec = BCD2BIN(BCDSEC); + tm->tm_year = bcd2bin(BCDYEAR); + tm->tm_mon = bcd2bin(BCDMON); + tm->tm_wday = bcd2bin(BCDDATE); + tm->tm_mday = bcd2bin(BCDDAY); + tm->tm_hour = bcd2bin(BCDHOUR); + tm->tm_min = bcd2bin(BCDMIN); + tm->tm_sec = bcd2bin(BCDSEC); if (tm->tm_sec==0) { /* we have to re-read the rtc data because of the "one second deviation" problem */ /* see RTC datasheet for more info about it */ - tm->tm_year = BCD2BIN(BCDYEAR); - tm->tm_mon = BCD2BIN(BCDMON); - tm->tm_mday = BCD2BIN(BCDDAY); - tm->tm_wday = BCD2BIN(BCDDATE); - tm->tm_hour = BCD2BIN(BCDHOUR); - tm->tm_min = BCD2BIN(BCDMIN); - tm->tm_sec = BCD2BIN(BCDSEC); + tm->tm_year = bcd2bin(BCDYEAR); + tm->tm_mon = bcd2bin(BCDMON); + tm->tm_mday = bcd2bin(BCDDAY); + tm->tm_wday = bcd2bin(BCDDATE); + tm->tm_hour = bcd2bin(BCDHOUR); + tm->tm_min = bcd2bin(BCDMIN); + tm->tm_sec = bcd2bin(BCDSEC); } RTCCON &= ~1; @@ -75,13 +75,13 @@ int rtc_set (struct rtc_time* tm) tm->tm_year -= 2000; RTCCON |= 1; - BCDYEAR = BIN2BCD(tm->tm_year); - BCDMON = BIN2BCD(tm->tm_mon); - BCDDAY = BIN2BCD(tm->tm_mday); - BCDDATE = BIN2BCD(tm->tm_wday); - BCDHOUR = BIN2BCD(tm->tm_hour); - BCDMIN = BIN2BCD(tm->tm_min); - BCDSEC = BIN2BCD(tm->tm_sec); + BCDYEAR = bin2bcd(tm->tm_year); + BCDMON = bin2bcd(tm->tm_mon); + BCDDAY = bin2bcd(tm->tm_mday); + BCDDATE = bin2bcd(tm->tm_wday); + BCDHOUR = bin2bcd(tm->tm_hour); + BCDMIN = bin2bcd(tm->tm_min); + BCDSEC = bin2bcd(tm->tm_sec); RTCCON &= 1; return 0; diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index 56115b032ac..ceba7c34aca 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -116,13 +116,13 @@ int rtc_get(struct rtc_time *tm) buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); - tm->tm_sec = BCD2BIN(buf[CCR_SEC]); - tm->tm_min = BCD2BIN(buf[CCR_MIN]); - tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ - tm->tm_mday = BCD2BIN(buf[CCR_MDAY]); - tm->tm_mon = BCD2BIN(buf[CCR_MONTH]); /* mon is 0-11 */ - tm->tm_year = BCD2BIN(buf[CCR_YEAR]) - + (BCD2BIN(buf[CCR_Y2K]) * 100); + tm->tm_sec = bcd2bin(buf[CCR_SEC]); + tm->tm_min = bcd2bin(buf[CCR_MIN]); + tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ + tm->tm_mday = bcd2bin(buf[CCR_MDAY]); + tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */ + tm->tm_year = bcd2bin(buf[CCR_YEAR]) + + (bcd2bin(buf[CCR_Y2K]) * 100); tm->tm_wday = buf[CCR_WDAY]; debug("%s: tm is secs=%d, mins=%d, hours=%d, " @@ -143,21 +143,21 @@ int rtc_set(struct rtc_time *tm) tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); - buf[CCR_SEC] = BIN2BCD(tm->tm_sec); - buf[CCR_MIN] = BIN2BCD(tm->tm_min); + buf[CCR_SEC] = bin2bcd(tm->tm_sec); + buf[CCR_MIN] = bin2bcd(tm->tm_min); /* set hour and 24hr bit */ - buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL; + buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; - buf[CCR_MDAY] = BIN2BCD(tm->tm_mday); + buf[CCR_MDAY] = bin2bcd(tm->tm_mday); /* month, 1 - 12 */ - buf[CCR_MONTH] = BIN2BCD(tm->tm_mon); + buf[CCR_MONTH] = bin2bcd(tm->tm_mon); /* year, since the rtc epoch*/ - buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100); + buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); buf[CCR_WDAY] = tm->tm_wday & 0x07; - buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100); + buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100); /* this sequence is required to unlock the chip */ rtc_write(X1205_REG_SR, X1205_SR_WEL); diff --git a/include/bcd.h b/include/bcd.h index c545308125b..af4aa9c7baf 100644 --- a/include/bcd.h +++ b/include/bcd.h @@ -3,18 +3,23 @@ * at your option. */ -/* macros to translate to/from binary and binary-coded decimal (frequently - * found in RTC chips). +/* inline functions to translate to/from binary and binary-coded decimal + * (frequently found in RTC chips). */ #ifndef _BCD_H #define _BCD_H -#define BCD2BIN(val) (((val) & 0x0f) + ((val)>>4)*10) -#define BIN2BCD(val) ((((val)/10)<<4) + (val)%10) +#include -/* backwards compat */ -#define BCD_TO_BIN(val) ((val)=BCD2BIN(val)) -#define BIN_TO_BCD(val) ((val)=BIN2BCD(val)) +static inline unsigned int bcd2bin(u8 val) +{ + return ((val) & 0x0f) + ((val) >> 4) * 10; +} + +static inline u8 bin2bcd (unsigned int val) +{ + return (((val / 10) << 4) | (val % 10)); +} #endif /* _BCD_H */ diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h index 227feeb0cd2..0644d92b3ca 100644 --- a/include/linux/mc146818rtc.h +++ b/include/linux/mc146818rtc.h @@ -83,16 +83,4 @@ #define RTC_VALID RTC_REG_D # define RTC_VRT 0x80 /* valid RAM and time */ /**********************************************************************/ - -/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) - * determines if the following two #defines are needed - */ -#ifndef BCD_TO_BIN -#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) -#endif - -#ifndef BIN_TO_BCD -#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) -#endif - #endif /* _MC146818RTC_H */ -- cgit v1.3.1 From 885fc78c28fbe773bcb4edc9dd0fdac05ebb5b38 Mon Sep 17 00:00:00 2001 From: Albin Tonnerre Date: Thu, 13 Aug 2009 15:31:12 +0200 Subject: Switch from per-driver to common definition of bin2bcd and bcd2bin Signed-off-by: Albin Tonnerre Acked-by: Stefan Roese --- drivers/rtc/ds12887.c | 12 ------------ drivers/rtc/ds1306.c | 18 ------------------ drivers/rtc/ds1307.c | 13 ------------- drivers/rtc/ds1337.c | 13 ------------- drivers/rtc/ds1556.c | 12 ------------ drivers/rtc/ds164x.c | 12 ------------ drivers/rtc/ds174x.c | 12 ------------ drivers/rtc/ds3231.c | 12 ------------ drivers/rtc/isl1208.c | 12 ------------ drivers/rtc/m41t11.c | 11 ----------- drivers/rtc/m41t60.c | 10 ---------- drivers/rtc/m41t62.c | 1 - drivers/rtc/m48t35ax.c | 12 ------------ drivers/rtc/max6900.c | 10 ---------- drivers/rtc/mc146818.c | 12 ------------ drivers/rtc/mk48t59.c | 10 ---------- drivers/rtc/pcf8563.c | 12 ------------ drivers/rtc/rs5c372.c | 14 -------------- drivers/rtc/rtc4543.c | 1 - drivers/rtc/rx8025.c | 12 ------------ drivers/rtc/s3c24x0_rtc.c | 10 ---------- drivers/rtc/s3c44b0_rtc.c | 1 - drivers/rtc/x1205.c | 1 - include/rtc.h | 5 +++++ 24 files changed, 5 insertions(+), 233 deletions(-) (limited to 'include') diff --git a/drivers/rtc/ds12887.c b/drivers/rtc/ds12887.c index 25ca1333e23..486105f5edb 100644 --- a/drivers/rtc/ds12887.c +++ b/drivers/rtc/ds12887.c @@ -76,18 +76,6 @@ static void rtc_write (uchar reg, uchar val) # error Board specific rtc access functions should be supplied #endif -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - -/* ------------------------------------------------------------------------- */ - int rtc_get (struct rtc_time *tmp) { uchar sec, min, hour, mday, wday, mon, year; diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c index 75f88a9a529..288c5f8c4ac 100644 --- a/drivers/rtc/ds1306.c +++ b/drivers/rtc/ds1306.c @@ -62,9 +62,6 @@ #define RTC_USER_RAM_BASE 0x20 -static unsigned int bin2bcd (unsigned int n); -static unsigned char bcd2bin (unsigned char c); - /* ************************************************************************* */ #ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ @@ -459,19 +456,4 @@ static void rtc_write (unsigned char reg, unsigned char val) #endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ -/* ------------------------------------------------------------------------- */ - -static unsigned char bcd2bin (unsigned char n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned int bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} -/* ------------------------------------------------------------------------- */ - #endif diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 0650d915abb..079aa99e8b9 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -76,8 +76,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC @@ -195,15 +193,4 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } - -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 58e3966ec7b..a71ab5daa3f 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -77,9 +77,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin (uchar c); - /* * Get the current time from the RTC @@ -191,14 +188,4 @@ static void rtc_write (uchar reg, uchar val) i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/ds1556.c b/drivers/rtc/ds1556.c index 763d22a03b1..25a0b64934b 100644 --- a/drivers/rtc/ds1556.c +++ b/drivers/rtc/ds1556.c @@ -40,8 +40,6 @@ static uchar rtc_read( unsigned int addr ); static void rtc_write( unsigned int addr, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin(uchar c); #define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) @@ -195,14 +193,4 @@ static void rtc_write( unsigned int addr, uchar val ) *(volatile unsigned char*)(addr) = val; } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/ds164x.c b/drivers/rtc/ds164x.c index 1e96679de24..9f306d19615 100644 --- a/drivers/rtc/ds164x.c +++ b/drivers/rtc/ds164x.c @@ -41,8 +41,6 @@ static uchar rtc_read(unsigned int addr ); static void rtc_write(unsigned int addr, uchar val); -static uchar bin2bcd(unsigned int n); -static unsigned bcd2bin(uchar c); #define RTC_EPOCH 2000 /* century */ @@ -191,14 +189,4 @@ static void rtc_write( unsigned int addr, uchar val ) *(volatile unsigned char*)(addr) = val; } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/ds174x.c b/drivers/rtc/ds174x.c index 738d1185c21..5a55dc8b7ad 100644 --- a/drivers/rtc/ds174x.c +++ b/drivers/rtc/ds174x.c @@ -37,8 +37,6 @@ static uchar rtc_read( unsigned int addr ); static void rtc_write( unsigned int addr, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin(uchar c); #define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) @@ -192,14 +190,4 @@ static void rtc_write( unsigned int addr, uchar val ) out8( addr, val ); } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index ef033588a9b..134a0e4fc22 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -79,8 +79,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin (uchar c); /* @@ -186,14 +184,4 @@ static void rtc_write (uchar reg, uchar val) i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c index 71f63d5fa00..07591b7dba7 100644 --- a/drivers/rtc/isl1208.c +++ b/drivers/rtc/isl1208.c @@ -66,8 +66,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC @@ -160,13 +158,3 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } - -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} diff --git a/drivers/rtc/m41t11.c b/drivers/rtc/m41t11.c index 3a77c1b6387..e0c27e18509 100644 --- a/drivers/rtc/m41t11.c +++ b/drivers/rtc/m41t11.c @@ -45,17 +45,6 @@ #if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE) -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - - /* ------------------------------------------------------------------------- */ /* these are simple defines for the chip local to here so they aren't too diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c index e34a5f47831..632fe4b1455 100644 --- a/drivers/rtc/m41t60.c +++ b/drivers/rtc/m41t60.c @@ -36,16 +36,6 @@ #if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE) -static unsigned bcd2bin(uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd(unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - /* * Convert between century and "century bits" (CB1 and CB0). These routines * assume years are in the range 1900 - 2299. diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 3d7bb46b0e6..62c24469396 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -31,7 +31,6 @@ #include #include #include -#include #if defined(CONFIG_CMD_DATE) diff --git a/drivers/rtc/m48t35ax.c b/drivers/rtc/m48t35ax.c index 1482edd607f..29b36c171c0 100644 --- a/drivers/rtc/m48t35ax.c +++ b/drivers/rtc/m48t35ax.c @@ -37,8 +37,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ @@ -157,14 +155,4 @@ static void rtc_write (uchar reg, uchar val) ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val; } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c index 7c99c5e5b1c..74637d1988d 100644 --- a/drivers/rtc/max6900.c +++ b/drivers/rtc/max6900.c @@ -51,16 +51,6 @@ static void rtc_write (uchar reg, uchar val) udelay(2500); } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - /* ------------------------------------------------------------------------- */ int rtc_get (struct rtc_time *tmp) diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 38484ce26cf..d68b438efbc 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -35,8 +35,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin(uchar c); #define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70 #define RTC_SECONDS 0x00 @@ -168,14 +166,4 @@ static void rtc_write (uchar reg, uchar val) } #endif -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/mk48t59.c b/drivers/rtc/mk48t59.c index dabf3222b84..b1768821182 100644 --- a/drivers/rtc/mk48t59.c +++ b/drivers/rtc/mk48t59.c @@ -97,16 +97,6 @@ static void rtc_write (short reg, uchar val) # error Board specific rtc access functions should be supplied #endif -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - /* ------------------------------------------------------------------------- */ void *nvram_read(void *dest, const short src, size_t count) diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index cd9fb65c3a4..339e5f60801 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -36,8 +36,6 @@ static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin(uchar c); /* ------------------------------------------------------------------------- */ @@ -137,14 +135,4 @@ static void rtc_write (uchar reg, uchar val) i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index d6cd7c825df..90bbb4efa3c 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -67,9 +67,6 @@ static unsigned int rtc_debug = DEBUG; #define HOURS_24(n) bcd2bin((n) & 0x3F) -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin (uchar c); - static int setup_done = 0; static int @@ -291,15 +288,4 @@ rtc_reset (void) return; } -static unsigned int -bcd2bin (unsigned char n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char -bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} #endif diff --git a/drivers/rtc/rtc4543.c b/drivers/rtc/rtc4543.c index b60e37d5be7..046aa67d9aa 100644 --- a/drivers/rtc/rtc4543.c +++ b/drivers/rtc/rtc4543.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index da87394a085..64eb1cda105 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -90,8 +90,6 @@ #define rtc_read(reg) buf[((reg) + 1) & 0xf] static void rtc_write (uchar reg, uchar val); -static uchar bin2bcd (unsigned int n); -static unsigned bcd2bin (uchar c); /* * Get the current time from the RTC @@ -226,14 +224,4 @@ static void rtc_write (uchar reg, uchar val) } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - #endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */ diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 0d3372faca2..e10db9acb86 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -58,16 +58,6 @@ static inline void SetRTC_Access(RTC_ACCESS a) } } -static unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -static unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - /* ------------------------------------------------------------------------- */ int rtc_get (struct rtc_time *tmp) diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c index a027fb1263b..d087d8adbd4 100644 --- a/drivers/rtc/s3c44b0_rtc.c +++ b/drivers/rtc/s3c44b0_rtc.c @@ -32,7 +32,6 @@ #include #include #include -#include int rtc_get (struct rtc_time* tm) { diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index ceba7c34aca..7adf3770d51 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -38,7 +38,6 @@ #include #include #include -#include #if defined(CONFIG_CMD_DATE) diff --git a/include/rtc.h b/include/rtc.h index 785fbe38079..772a5488419 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -27,6 +27,11 @@ #ifndef _RTC_H_ #define _RTC_H_ +/* bcd<->bin functions are needed by almost all the RTC drivers, let's include + * it there instead of in evey single driver */ + +#include + /* * The struct used to pass data from the generic interface code to * the hardware dependend low-level code ande vice versa. Identical -- cgit v1.3.1 From d47628a6ecf80cd4584a50b6c795b90c985a48e5 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Fri, 7 Aug 2009 13:59:26 +0200 Subject: arm nomadik: activate defrag choose 4k transfer block size This chooses 4kB data size for both TFTP and NFS, as an example about how to use support for IP fragments. Signed-off-by: Alessandro Rubini Signed-off-by: Ben Warren --- include/configs/nhk8815.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 8a83d924bbd..027e8e16b37 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -138,6 +138,10 @@ #define CONFIG_SMC_USE_32_BIT #define CONFIG_BOOTFILE "uImage" +#define CONFIG_IP_DEFRAG /* Allows faster download, TFTP and NFS */ +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + /* Storage information: onenand and nand */ #define CONFIG_CMD_ONENAND #define CONFIG_MTD_ONENAND_VERIFY_WRITE -- cgit v1.3.1 From b1c0eaac110bc919e5b4e88821348e714493f266 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Tue, 25 Aug 2009 13:09:37 -0700 Subject: Convert CS8900 Ethernet driver to CONFIG_NET_MULTI API All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900 - changed CS8900_BASE to CONFIG_CS8900_BASE - changed CS8900_BUS?? to CONFIG_CS8900_BUS?? - cleaned up line lengths - modified VCMA9 command function that accesses the device - removed MAC address initialization from lib_arm/board.c Signed-off-by: Ben Warren Tested-by: Wolfgang Denk Acked-by: Wolfgang Denk --- board/altera/dk1c20/dk1c20.c | 12 ++ board/altera/dk1s10/dk1s10.c | 12 ++ board/armadillo/armadillo.c | 12 ++ board/csb226/csb226.c | 12 ++ board/ep7312/ep7312.c | 12 ++ board/freescale/mx31ads/mx31ads.c | 12 ++ board/impa7/impa7.c | 12 ++ board/lart/lart.c | 12 ++ board/mpl/vcma9/cmd_vcma9.c | 28 ++-- board/mpl/vcma9/vcma9.c | 12 ++ board/mx1ads/mx1ads.c | 12 ++ board/samsung/smdk2400/smdk2400.c | 12 ++ board/samsung/smdk2410/smdk2410.c | 12 ++ board/samsung/smdk6400/smdk6400.c | 12 ++ board/sbc2410x/sbc2410x.c | 12 ++ board/ssv/adnpesc1/adnpesc1.c | 12 ++ board/trab/trab.c | 12 ++ drivers/net/Makefile | 2 +- drivers/net/cs8900.c | 276 ++++++++++++++++++++++---------------- drivers/net/cs8900.h | 41 +++--- include/configs/ADNPESC1.h | 14 +- include/configs/DK1C20.h | 14 +- include/configs/DK1S10.h | 14 +- include/configs/VCMA9.h | 7 +- include/configs/armadillo.h | 9 +- include/configs/csb226.h | 7 +- include/configs/ep7312.h | 9 +- include/configs/impa7.h | 7 +- include/configs/lart.h | 7 +- include/configs/mx1ads.h | 7 +- include/configs/mx31ads.h | 7 +- include/configs/sbc2410x.h | 7 +- include/configs/smdk2400.h | 7 +- include/configs/smdk2410.h | 7 +- include/configs/smdk6400.h | 7 +- include/configs/trab.h | 7 +- include/netdev.h | 1 + lib_arm/board.c | 9 -- 38 files changed, 476 insertions(+), 210 deletions(-) (limited to 'include') diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c index 11c19b7eedb..0bcaa4fd147 100644 --- a/board/altera/dk1c20/dk1c20.c +++ b/board/altera/dk1c20/dk1c20.c @@ -25,6 +25,7 @@ */ #include +#include #include #if defined(CONFIG_SEVENSEG) #include "../common/sevenseg.h" @@ -79,3 +80,14 @@ int ide_preinit (void) return 0; } #endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c index 64d591e714e..fb96501da21 100644 --- a/board/altera/dk1s10/dk1s10.c +++ b/board/altera/dk1s10/dk1s10.c @@ -22,6 +22,7 @@ */ #include +#include #if defined(CONFIG_SEVENSEG) #include "../common/sevenseg.h" #endif @@ -58,3 +59,14 @@ phys_size_t initdram (int board_type) { return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c index ca5bd1d1640..a825144c5c6 100644 --- a/board/armadillo/armadillo.c +++ b/board/armadillo/armadillo.c @@ -26,6 +26,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -58,3 +59,14 @@ int dram_init (void) return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c index 80caf8b464e..0a6c13dd29b 100644 --- a/board/csb226/csb226.c +++ b/board/csb226/csb226.c @@ -24,6 +24,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -151,3 +152,14 @@ void show_boot_progress (int status) return; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/ep7312/ep7312.c b/board/ep7312/ep7312.c index 6968a5dbdd1..8ed14ad583d 100644 --- a/board/ep7312/ep7312.c +++ b/board/ep7312/ep7312.c @@ -23,6 +23,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -52,3 +53,14 @@ int dram_init (void) return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index c24c47c57f8..bc25c6deb5c 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -104,3 +105,14 @@ int checkboard (void) printf("Board: MX31ADS\n"); return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/impa7/impa7.c b/board/impa7/impa7.c index 3230dd48f07..205b1b31dde 100644 --- a/board/impa7/impa7.c +++ b/board/impa7/impa7.c @@ -23,6 +23,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -57,3 +58,14 @@ int dram_init (void) return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/lart/lart.c b/board/lart/lart.c index 8d534c8e673..a0b459f2f21 100644 --- a/board/lart/lart.c +++ b/board/lart/lart.c @@ -23,6 +23,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -62,3 +63,14 @@ int dram_init (void) return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 01607743952..0ee959507f7 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -31,7 +31,7 @@ #include "vcma9.h" #include "../common/common_util.h" -#if defined(CONFIG_DRIVER_CS8900) +#if defined(CONFIG_CS8900) #include <../drivers/net/cs8900.h> static uchar cs8900_chksum(ushort data) @@ -56,25 +56,33 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + struct eth_device *dev; + char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { print_vcma9_info(); return 0; } -#if defined(CONFIG_DRIVER_CS8900) +#if defined(CONFIG_CS8900) if (strcmp(argv[1], "cs8900") == 0) { + sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME); + dev = eth_get_dev_by_name(cs8900_name); + if (!dev) { + printf("Couldn't find CS8900 driver"); + return 0; + } if (strcmp(argv[2], "read") == 0) { uchar addr; ushort data; addr = simple_strtoul(argv[3], NULL, 16); - cs8900_e2prom_read(addr, &data); + cs8900_e2prom_read(dev, addr, &data); printf("0x%2.2X: 0x%4.4X\n", addr, data); } else if (strcmp(argv[2], "write") == 0) { uchar addr; ushort data; addr = simple_strtoul(argv[3], NULL, 16); data = simple_strtoul(argv[4], NULL, 16); - cs8900_e2prom_write(addr, data); + cs8900_e2prom_write(dev, addr, data); } else if (strcmp(argv[2], "setaddr") == 0) { uchar addr, i, csum; ushort data; uchar ethaddr[6]; @@ -83,22 +91,22 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (eth_getenv_enetaddr("ethaddr", ethaddr)) { addr = 1; data = 0x2158; - cs8900_e2prom_write(addr, data); + cs8900_e2prom_write(dev, addr, data); csum = cs8900_chksum(data); addr++; for (i = 0; i < 6; i+=2) { data = ethaddr[i+1] << 8 | ethaddr[i]; - cs8900_e2prom_write(addr, data); + cs8900_e2prom_write(dev, addr, data); csum += cs8900_chksum(data); addr++; } /* calculate header link byte */ data = 0xA100 | (addr * 2); - cs8900_e2prom_write(0, data); + cs8900_e2prom_write(dev, 0, data); csum += cs8900_chksum(data); /* write checksum word */ - cs8900_e2prom_write(addr, (0 - csum) << 8); + cs8900_e2prom_write(dev, addr, (0 - csum) << 8); } else { puts("\nplease defined 'ethaddr'\n"); } @@ -106,12 +114,12 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) uchar addr = 0, endaddr, csum; ushort data; puts("Dump of CS8900 config device: "); - cs8900_e2prom_read(addr, &data); + cs8900_e2prom_read(dev, addr, &data); if ((data & 0xE000) == 0xA000) { endaddr = (data & 0x00FF) / 2; csum = cs8900_chksum(data); for (addr = 1; addr <= endaddr; addr++) { - cs8900_e2prom_read(addr, &data); + cs8900_e2prom_read(dev, addr, &data); printf("\n0x%2.2X: 0x%4.4X", addr, data); csum += cs8900_chksum(data); } diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 2b3fad2513e..3216d6347dc 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -26,6 +26,7 @@ */ #include +#include #include #include #include @@ -349,3 +350,14 @@ void print_vcma9_info(void) Show_VCMA9_Info(s, &s[6]); } } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index ba152e2e886..f8ce2108c1c 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -24,6 +24,7 @@ */ #include +#include /*#include */ #include @@ -167,3 +168,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index 0b820706b23..2c47063e95e 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -26,6 +26,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -110,3 +111,14 @@ static int key_pressed(void) return rc; } #endif /* CONFIG_MODEM_SUPPORT */ + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index 802348d2369..25c38e67e9d 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -26,6 +26,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -121,3 +122,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index 52cd174a066..561c0c83115 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -29,6 +29,7 @@ */ #include +#include #include /* ------------------------------------------------------------------------- */ @@ -117,3 +118,14 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) } else return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 6c894a3869e..62768503ad5 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -29,6 +29,7 @@ */ #include +#include #include #if defined(CONFIG_CMD_NAND) @@ -178,3 +179,14 @@ void nand_init(void) printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); } #endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c index 9d32741499e..72810d036ae 100644 --- a/board/ssv/adnpesc1/adnpesc1.c +++ b/board/ssv/adnpesc1/adnpesc1.c @@ -22,6 +22,7 @@ */ #include +#include #include #include @@ -100,3 +101,14 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/board/trab/trab.c b/board/trab/trab.c index ddf6abf7b4c..2dccd87677c 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -24,6 +24,7 @@ /* #define DEBUG */ #include +#include #include #include #include @@ -420,3 +421,14 @@ static void tsc2000_set_brightness(void) tsc2000_write(0, 0xb, br & 0xff); } #endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1c6e402246e..f6e9f6796c6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -30,7 +30,7 @@ COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o -COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o +COBJS-$(CONFIG_CS8900) += cs8900.o COBJS-$(CONFIG_TULIP) += dc2114x.o COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o COBJS-$(CONFIG_DNET) += dnet.o diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index 5e2b3b080d0..587f7f62a76 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -1,6 +1,9 @@ /* * Cirrus Logic CS8900A Ethernet * + * (C) 2009 Ben Warren , biggerbadderben@gmail.com + * Converted to use CONFIG_NET_MULTI API + * * (C) 2003 Wolfgang Denk, wd@denx.de * Extension to synchronize ethaddr environment variable * against value in EEPROM @@ -38,220 +41,229 @@ #include #include -#include "cs8900.h" +#include #include +#include +#include "cs8900.h" #undef DEBUG /* packet page register access functions */ -#ifdef CS8900_BUS32 +#ifdef CONFIG_CS8900_BUS32 + +#define REG_WRITE(v, a) writel((v),(a)) +#define REG_READ(a) readl((a)) + /* we don't need 16 bit initialisation on 32 bit bus */ #define get_reg_init_bus(x) get_reg((x)) + #else -static unsigned short get_reg_init_bus (int regno) -{ - /* force 16 bit busmode */ - volatile unsigned char c; - c = CS8900_BUS16_0; - c = CS8900_BUS16_1; - c = CS8900_BUS16_0; - c = CS8900_BUS16_1; - c = CS8900_BUS16_0; +#define REG_WRITE(v, a) writew((v),(a)) +#define REG_READ(a) readw((a)) - CS8900_PPTR = regno; - return CS8900_PDATA; +static u16 get_reg_init_bus(struct eth_device *dev, int regno) +{ + /* force 16 bit busmode */ + volatile u8 c; + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase; + + c = readb(iob); + c = readb(iob + 1); + c = readb(iob); + c = readb(iob + 1); + c = readb(iob); + + REG_WRITE(regno, &priv->regs->pptr); + return REG_READ(&priv->regs->pdata); } #endif -static unsigned short get_reg (int regno) +static u16 get_reg(struct eth_device *dev, int regno) { - CS8900_PPTR = regno; - return CS8900_PDATA; + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + REG_WRITE(regno, &priv->regs->pptr); + return REG_READ(&priv->regs->pdata); } -static void put_reg (int regno, unsigned short val) +static void put_reg(struct eth_device *dev, int regno, u16 val) { - CS8900_PPTR = regno; - CS8900_PDATA = val; + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + REG_WRITE(regno, &priv->regs->pptr); + REG_WRITE(val, &priv->regs->pdata); } -static void eth_reset (void) +static void cs8900_reset(struct eth_device *dev) { int tmo; - unsigned short us; + u16 us; /* reset NIC */ - put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset); + put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset); /* wait for 200ms */ - udelay (200000); + udelay(200000); /* Wait until the chip is reset */ - tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; - while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0) - && tmo < get_timer (0)) + tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; + while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) & + PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0)) /*NOP*/; } -static void eth_reginit (void) +static void cs8900_reginit(struct eth_device *dev) { /* receive only error free packets addressed to this card */ - put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); + put_reg(dev, PP_RxCTL, + PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); /* do not generate any interrupts on receive operations */ - put_reg (PP_RxCFG, 0); + put_reg(dev, PP_RxCFG, 0); /* do not generate any interrupts on transmit operations */ - put_reg (PP_TxCFG, 0); + put_reg(dev, PP_TxCFG, 0); /* do not generate any interrupts on buffer operations */ - put_reg (PP_BufCFG, 0); + put_reg(dev, PP_BufCFG, 0); /* enable transmitter/receiver mode */ - put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); + put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); } -void cs8900_get_enetaddr (void) +void cs8900_get_enetaddr(struct eth_device *dev) { int i; - uchar enetaddr[6]; - - /* if the env is setup, then bail */ - if (eth_getenv_enetaddr("ethaddr", enetaddr)) - return; /* verify chip id */ - if (get_reg_init_bus (PP_ChipID) != 0x630e) + if (get_reg_init_bus(dev, PP_ChipID) != 0x630e) return; - eth_reset (); - if ((get_reg (PP_SelfSTAT) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == - (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { + cs8900_reset(dev); + if ((get_reg(dev, PP_SelfSTAT) & + (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == + (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { /* Load the MAC from EEPROM */ - for (i = 0; i < 6 / 2; i++) { - unsigned int Addr; + for (i = 0; i < 3; i++) { + u32 Addr; - Addr = get_reg (PP_IA + i * 2); - enetaddr[i * 2] = Addr & 0xFF; - enetaddr[i * 2 + 1] = Addr >> 8; + Addr = get_reg(dev, PP_IA + i * 2); + dev->enetaddr[i * 2] = Addr & 0xFF; + dev->enetaddr[i * 2 + 1] = Addr >> 8; } - - eth_setenv_enetaddr("ethaddr", enetaddr); - debug("### Set environment from HW MAC addr = \"%pM\"\n", enetaddr); } } -void eth_halt (void) +void cs8900_halt(struct eth_device *dev) { /* disable transmitter/receiver mode */ - put_reg (PP_LineCTL, 0); + put_reg(dev, PP_LineCTL, 0); /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */ - get_reg_init_bus (PP_ChipID); + get_reg_init_bus(dev, PP_ChipID); } -int eth_init (bd_t * bd) +static int cs8900_init(struct eth_device *dev, bd_t * bd) { - uchar enetaddr[6]; + uchar *enetaddr = dev->enetaddr; + u16 id; /* verify chip id */ - if (get_reg_init_bus (PP_ChipID) != 0x630e) { - printf ("CS8900 Ethernet chip not found?!\n"); - return 0; + id = get_reg_init_bus(dev, PP_ChipID); + if (id != 0x630e) { + printf ("CS8900 Ethernet chip not found: " + "ID=0x%04x instead 0x%04x\n", id, 0x630e); + return 1; } - eth_reset (); + cs8900_reset (dev); /* set the ethernet address */ - eth_getenv_enetaddr("ethaddr", enetaddr); - put_reg (PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8)); - put_reg (PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8)); - put_reg (PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8)); + put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8)); + put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8)); + put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8)); - eth_reginit (); + cs8900_reginit(dev); return 0; } /* Get a data block via Ethernet */ -int eth_rx (void) +static int cs8900_recv(struct eth_device *dev) { int i; - unsigned short rxlen; - unsigned short *addr; - unsigned short status; + u16 rxlen; + u16 *addr; + u16 status; - status = get_reg (PP_RER); + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + + status = get_reg(dev, PP_RER); if ((status & PP_RER_RxOK) == 0) return 0; - status = CS8900_RTDATA; /* stat */ - rxlen = CS8900_RTDATA; /* len */ + status = REG_READ(&priv->regs->rtdata); + rxlen = REG_READ(&priv->regs->rtdata); -#ifdef DEBUG if (rxlen > PKTSIZE_ALIGN + PKTALIGN) - printf ("packet too big!\n"); -#endif - for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0; + debug("packet too big!\n"); + for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0; i--) - *addr++ = CS8900_RTDATA; + *addr++ = REG_READ(&priv->regs->rtdata); if (rxlen & 1) - *addr++ = CS8900_RTDATA; + *addr++ = REG_READ(&priv->regs->rtdata); /* Pass the packet up to the protocol layers. */ NetReceive (NetRxPackets[0], rxlen); - return rxlen; } /* Send a data block via Ethernet. */ -int eth_send (volatile void *packet, int length) +static int cs8900_send(struct eth_device *dev, + volatile void *packet, int length) { - volatile unsigned short *addr; + volatile u16 *addr; int tmo; - unsigned short s; + u16 s; + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); retry: /* initiate a transmit sequence */ - CS8900_TxCMD = PP_TxCmd_TxStart_Full; - CS8900_TxLEN = length; + REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd); + REG_WRITE(length, &priv->regs->txlen); /* Test to see if the chip has allocated memory for the packet */ - if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { + if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { /* Oops... this should not happen! */ -#ifdef DEBUG - printf ("cs: unable to send packet; retrying...\n"); -#endif - for (tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; get_timer (0) < tmo;) + debug("cs: unable to send packet; retrying...\n"); + for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + get_timer(0) < tmo;) /*NOP*/; - eth_reset (); - eth_reginit (); + cs8900_reset(dev); + cs8900_reginit(dev); goto retry; } /* Write the contents of the packet */ /* assume even number of bytes */ for (addr = packet; length > 0; length -= 2) - CS8900_RTDATA = *addr++; + REG_WRITE(*addr++, &priv->regs->rtdata); /* wait for transfer to succeed */ - tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; - while ((s = get_reg (PP_TER) & ~0x1F) == 0) { - if (get_timer (0) >= tmo) + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) { + if (get_timer(0) >= tmo) break; } /* nothing */ ; - if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { -#ifdef DEBUG - printf ("\ntransmission error %#x\n", s); -#endif + if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { + debug("\ntransmission error %#x\n", s); } return 0; } -static void cs8900_e2prom_ready(void) +static void cs8900_e2prom_ready(struct eth_device *dev) { - while (get_reg(PP_SelfSTAT) & SI_BUSY) + while (get_reg(dev, PP_SelfSTAT) & SI_BUSY) ; } @@ -259,12 +271,13 @@ static void cs8900_e2prom_ready(void) /* read a 16-bit word out of the EEPROM */ /***********************************************************/ -int cs8900_e2prom_read(unsigned char addr, unsigned short *value) +int cs8900_e2prom_read(struct eth_device *dev, + u8 addr, u16 *value) { - cs8900_e2prom_ready(); - put_reg(PP_EECMD, EEPROM_READ_CMD | addr); - cs8900_e2prom_ready(); - *value = get_reg(PP_EEData); + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr); + cs8900_e2prom_ready(dev); + *value = get_reg(dev, PP_EEData); return 0; } @@ -274,16 +287,51 @@ int cs8900_e2prom_read(unsigned char addr, unsigned short *value) /* write a 16-bit word into the EEPROM */ /***********************************************************/ -int cs8900_e2prom_write(unsigned char addr, unsigned short value) +int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value) +{ + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EECMD, EEPROM_WRITE_EN); + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EEData, value); + put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr); + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS); + cs8900_e2prom_ready(dev); + + return 0; +} + +int cs8900_initialize(u8 dev_num, int base_addr) { - cs8900_e2prom_ready(); - put_reg(PP_EECMD, EEPROM_WRITE_EN); - cs8900_e2prom_ready(); - put_reg(PP_EEData, value); - put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr); - cs8900_e2prom_ready(); - put_reg(PP_EECMD, EEPROM_WRITE_DIS); - cs8900_e2prom_ready(); + struct eth_device *dev; + struct cs8900_priv *priv; + + dev = malloc(sizeof(*dev)); + if (!dev) { + free(dev); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + priv = malloc(sizeof(*priv)); + if (!priv) { + free(priv); + return 0; + } + memset(priv, 0, sizeof(*priv)); + priv->regs = (struct cs8900_regs *)base_addr; + + /* Load MAC address from EEPROM */ + cs8900_get_enetaddr(dev); + + dev->iobase = base_addr; + dev->priv = priv; + dev->init = cs8900_init; + dev->halt = cs8900_halt; + dev->send = cs8900_send; + dev->recv = cs8900_recv; + sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num); + eth_register(dev); return 0; } diff --git a/drivers/net/cs8900.h b/drivers/net/cs8900.h index f9c32dd65d7..23c5cb07bb5 100644 --- a/drivers/net/cs8900.h +++ b/drivers/net/cs8900.h @@ -1,6 +1,11 @@ +#ifndef CS8900_H +#define CS8900_H /* * Cirrus Logic CS8900A Ethernet * + * (C) 2009 Ben Warren , biggerbadderben@gmail.com + * Converted to use CONFIG_NET_MULTI API + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH * Marius Groeger @@ -35,33 +40,34 @@ #include #include -#ifdef CONFIG_DRIVER_CS8900 - +#define CS8900_DRIVERNAME "CS8900" /* although the registers are 16 bit, they are 32-bit aligned on the EDB7111. so we have to read them as 32-bit registers and ignore the upper 16-bits. i'm not sure if this holds for the EDB7211. */ -#ifdef CS8900_BUS16 +#ifdef CONFIG_CS8900_BUS16 /* 16 bit aligned registers, 16 bit wide */ #define CS8900_REG u16 - #define CS8900_OFF 0x02 - #define CS8900_BUS16_0 *(volatile u8 *)(CS8900_BASE+0x00) - #define CS8900_BUS16_1 *(volatile u8 *)(CS8900_BASE+0x01) -#elif defined(CS8900_BUS32) +#elif defined(CONFIG_CS8900_BUS32) /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ #define CS8900_REG u32 - #define CS8900_OFF 0x04 #else #error unknown bussize ... #endif -#define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF) -#define CS8900_TxCMD *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF) -#define CS8900_TxLEN *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF) -#define CS8900_ISQ *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF) -#define CS8900_PPTR *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF) -#define CS8900_PDATA *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF) +struct cs8900_regs { + CS8900_REG rtdata; + CS8900_REG pad0; + CS8900_REG txcmd; + CS8900_REG txlen; + CS8900_REG isq; + CS8900_REG pptr; + CS8900_REG pdata; +}; +struct cs8900_priv { + struct cs8900_regs *regs; +}; #define ISQ_RxEvent 0x04 #define ISQ_TxEvent 0x08 @@ -251,7 +257,8 @@ #define EEPROM_READ_CMD 0x0200 #define EEPROM_ERASE_CMD 0x0300 -extern int cs8900_e2prom_read(uchar, ushort *); -extern int cs8900_e2prom_write(uchar, ushort); +/* Exported functions */ +int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *); +int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort); -#endif /* CONFIG_DRIVER_CS8900 */ +#endif /* CS8900_H */ diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index b8afc172c51..2d4fc779150 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -426,15 +426,17 @@ /********************************************/ /* !!! CS8900 is __not__ tested on NIOS !!! */ /********************************************/ -#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ -#define CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* Using CS8900 */ +#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CS8900_BUS16 -#define CS8900_BUS32 1 +#undef CONFIG_CS8900_BUS16 +#define CONFIG_CS8900_BUS32 #else /* no */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 +#define CONFIG_CS8900_BUS16 +#undef CONFIG_CS8900_BUS32 #endif #else diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index 45ff2f7dbc8..cdc488b38e2 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -232,15 +232,17 @@ /********************************************/ /* !!! CS8900 is __not__ tested on NIOS !!! */ /********************************************/ -#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ -#define CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* Using CS8900 */ +#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CS8900_BUS16 -#define CS8900_BUS32 1 +#undef CONFIG_CS8900_BUS16 +#define CONFIG_CS8900_BUS32 #else /* no */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 +#define CONFIG_CS8900_BUS16 +#undef CONFIG_CS8900_BUS32 #endif #else diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index ae567a32b32..6e788610fde 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -249,15 +249,17 @@ /********************************************/ /* !!! CS8900 is __not__ tested on NIOS !!! */ /********************************************/ -#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ -#define CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* Using CS8900 */ +#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CS8900_BUS16 -#define CS8900_BUS32 1 +#undef CONFIG_CS8900_BUS16 +#define CONFIG_CS8900_BUS32 #else /* no */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 +#define CONFIG_CS8900_BUS16 +#undef CONFIG_CS8900_BUS32 #endif #else diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 60514802543..618b7f0a7e0 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -108,9 +108,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index f7eec276858..49ea3a16685 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -56,10 +56,11 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000300 /* armadillo board */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 /* armadillo board */ +#define CONFIG_CS8900_BUS16 +#undef CONFIG_CS8900_BUS32 /* * select serial console configuration diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 12bab4702a1..0661d65aba4 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -150,9 +150,10 @@ /* * Network chip */ -#define CONFIG_DRIVER_CS8900 1 -#define CS8900_BUS32 1 -#define CS8900_BASE 0x08000000 +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 +#define CONFIG_CS8900_BUS32 +#define CONFIG_CS8900_BASE 0x08000000 /* * Stack sizes diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index 630fff3903a..e151faa9655 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -47,10 +47,11 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000000 -#define CS8900_BUS16 1 -#undef CS8900_BUS32 +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000000 +#define CONFIG_CS8900_BUS16 +#undef CONFIG_CS8900_BUS32 /* * select serial console configuration diff --git a/include/configs/impa7.h b/include/configs/impa7.h index c7001cc7de8..fdfa022c0b0 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -47,9 +47,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000000 -#define CS8900_BUS32 1 +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000000 +#define CONFIG_CS8900_BUS32 /* * select serial console configuration diff --git a/include/configs/lart.h b/include/configs/lart.h index 5d6d460424d..2d3b369aae6 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -47,9 +47,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20008300 -#define CS8900_BUS16 1 +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20008300 +#define CONFIG_CS8900_BUS16 /* * select serial console configuration diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 12e567bf7d4..b2ffd3e9354 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -66,9 +66,10 @@ /* * CS8900 Ethernet drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x15000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x15000300 +#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ /* * select serial console configuration diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 363ea1ba1fe..ec1c9054034 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -109,9 +109,10 @@ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ "setenv filesize; saveenv\0" -#define CONFIG_DRIVER_CS8900 1 -#define CS8900_BASE 0xb4020300 -#define CS8900_BUS16 1 /* follow the Linux driver */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 +#define CONFIG_CS8900_BASE 0xb4020300 +#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ /* * The MX31ADS board seems to have a hardware "peculiarity" confirmed under diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index f3dc7fe9793..f2ea926f924 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -63,9 +63,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x19000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x19000300 +#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ /* * select serial console configuration diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index b712db44f48..c2341777673 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -56,9 +56,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ +#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ /* * select serial console configuration diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index a4732783d98..d340098d0bc 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -53,9 +53,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x19000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x19000300 +#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ /* * select serial console configuration diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index ddc8e7174af..f6e1221294f 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -74,9 +74,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x18800300 -#define CS8900_BUS16 1 /* follow the Linux driver */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x18800300 +#define CONFIG_CS8900_BUS16 /* follow the Linux driver */ /* * select serial console configuration diff --git a/include/configs/trab.h b/include/configs/trab.h index 7687ee6dcba..43c191b4356 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -99,9 +99,10 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CONFIG_NET_MULTI +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ +#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ diff --git a/include/netdev.h b/include/netdev.h index 50329a3f53b..a50ec67d531 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -43,6 +43,7 @@ int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ int au1x00_enet_initialize(bd_t*); int bfin_EMAC_initialize(bd_t *bis); +int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis); int davinci_emac_initialize(void); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); diff --git a/lib_arm/board.c b/lib_arm/board.c index a44d308f672..fa87d513731 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -73,10 +73,6 @@ extern void dataflash_print_info(void); const char version_string[] = U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING; -#ifdef CONFIG_DRIVER_CS8900 -extern void cs8900_get_enetaddr (void); -#endif - #ifdef CONFIG_DRIVER_RTL8019 extern void rtl8019_get_enetaddr (uchar * addr); #endif @@ -423,11 +419,6 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr); } #endif -#ifdef CONFIG_DRIVER_CS8900 - /* XXX: this needs to be moved to board init */ - cs8900_get_enetaddr (); -#endif - #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ if (getenv ("ethaddr")) { -- cgit v1.3.1 From 3a7b2c21fb08b022e3e624cd071002b4aaed1606 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Wed, 22 Jul 2009 17:13:24 +0200 Subject: Support up to 7 banks for ids as specified in JEDEC JEP106Z see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger Signed-off-by: Stefan Roese --- drivers/mtd/cfi_flash.c | 15 +++++++++-- drivers/mtd/jedec_flash.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 10 ++++++- 3 files changed, 89 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 3ca73e3caef..6eea49a11ea 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -106,6 +106,8 @@ #define ATM_CMD_SOFTLOCK_START 0x80 #define ATM_CMD_LOCK_SECT 0x40 +#define FLASH_CONTINUATION_CODE 0x7F + #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -1541,13 +1543,22 @@ static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) static void cmdset_amd_read_jedec_ids(flash_info_t *info) { + ushort bankId = 0; + uchar manuId; + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); + /* JEDEC JEP106Z specifies ID codes up to bank 7 */ + while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { + bankId += 0x100; + manuId = flash_read_uchar (info, + bankId | FLASH_OFFSET_MANUFACTURER_ID); + } + info->manufacturer_id = manuId; switch (info->chipwidth){ case FLASH_CFI_8BIT: diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index e48aceceae6..223fb711453 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -68,6 +68,17 @@ #define SST39SF010A 0x00B5 #define SST39SF020A 0x00B6 +/* MXIC */ +#define MX29LV040 0x004F + +/* WINBOND */ +#define W39L040A 0x00D6 + +/* AMIC */ +#define A29L040 0x0092 + +/* EON */ +#define EN29LV040A 0x004F /* * Unlock address sets for AMD command sets. @@ -225,6 +236,62 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x10000,8), } }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = MX29LV040, + .name = "MXIC MX29LV040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)WINB_MANUFACT, + .dev_id = W39L040A, + .name = "WINBOND W39L040A", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)AMIC_MANUFACT, + .dev_id = A29L040, + .name = "AMIC A29L040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)EON_MANUFACT, + .dev_id = EN29LV040A, + .name = "EON EN29LV040A", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, #endif #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { diff --git a/include/flash.h b/include/flash.h index b016162009f..8feca1b5fad 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,7 +46,7 @@ typedef struct { ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ - uchar manufacturer_id; /* manufacturer id */ + ushort manufacturer_id; /* manufacturer id */ ushort device_id; /* device id */ ushort device_id2; /* extended device id */ ushort ext_addr; /* extended query table address */ @@ -154,6 +154,7 @@ extern flash_info_t *flash_get_info(ulong base); * Device IDs */ +/* Manufacturers inside bank 0 have ids like 0x00xx00xx */ #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define ATM_MANUFACT 0x001F001F /* ATMEL */ @@ -166,6 +167,13 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ +#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ +#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 1 have ids like 0x01xx01xx */ +#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 2 have ids like 0x02xx02xx */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ -- cgit v1.3.1 From 88c811b153771a3d1bfe958297c69722efb278e9 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 22 Jul 2009 16:32:39 +0000 Subject: ColdFire: Fix missing _IO_BASE which caused compile error The compile error was caused by a recent patch. Affected platforms - M5253DEMO.h, M5253EVBE.h, and M54455EVB.h. Adding the _IO_BASE automatically defined to 0 in asm-m68k/io.h if it isn't set in platform configuration file. Signed-off-by: TsiChung Liew --- include/asm-m68k/io.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 50ea08751f1..531f420336c 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -28,6 +28,10 @@ #include +#ifndef _IO_BASE +#define _IO_BASE 0 +#endif + #define __raw_readb(addr) (*(volatile u8 *)(addr)) #define __raw_readw(addr) (*(volatile u16 *)(addr)) #define __raw_readl(addr) (*(volatile u32 *)(addr)) -- cgit v1.3.1 From 0d042037b3cf8693ea0f793d0c292430bfc5a95c Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Tue, 25 Aug 2009 10:30:26 -0500 Subject: galaxy5200: Cleanup typo and trailing whitespace Signed-off-by: Eric Millbrandt --- include/configs/galaxy5200.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index e9a45699685..8d530d86aa1 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -81,8 +81,8 @@ #endif /* RAMBOOT will be defined automatically in memory section */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" /* @@ -94,7 +94,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_PREBOOT "echo;" \ - "echo Welcome to U-Boot"\ + "echo Welcome to U-Boot;"\ "echo" /* @@ -376,7 +376,7 @@ #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 /* * USB settings -- cgit v1.3.1 From ce3277a6f2c082f39596d3d3d88dd0a5bc91439d Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 21 Jul 2009 11:58:04 +0900 Subject: OneNAND: Remove unused read_spareram Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park --- drivers/mtd/onenand/onenand_base.c | 4 +--- include/linux/mtd/onenand.h | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index d482437a462..368fa6ef68e 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1010,7 +1010,7 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, if (ret) break; - this->read_spareram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen); + this->read_bufferram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen); read += thislen; if (read == len) break; @@ -2104,8 +2104,6 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) if (!this->read_bufferram) this->read_bufferram = onenand_read_bufferram; - if (!this->read_spareram) - this->read_spareram = onenand_read_bufferram; if (!this->write_bufferram) this->write_bufferram = onenand_write_bufferram; diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 2597e347b4b..06f7bafeae1 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -83,10 +83,9 @@ struct onenand_chip { size_t len); int (*wait) (struct mtd_info *mtd, int state); int (*bbt_wait) (struct mtd_info *mtd, int state); + void (*unlock_all)(struct mtd_info *mtd); int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area, unsigned char *buffer, int offset, size_t count); - int (*read_spareram) (struct mtd_info *mtd, loff_t addr, int area, - unsigned char *buffer, int offset, size_t count); int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area, const unsigned char *buffer, int offset, size_t count); -- cgit v1.3.1 From ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 21 Jul 2009 11:58:04 +0900 Subject: OneNAND: Remove unused read_spareram Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park Signed-off-by: Scott Wood --- drivers/mtd/onenand/onenand_base.c | 4 +--- include/linux/mtd/onenand.h | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index d482437a462..368fa6ef68e 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1010,7 +1010,7 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, if (ret) break; - this->read_spareram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen); + this->read_bufferram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen); read += thislen; if (read == len) break; @@ -2104,8 +2104,6 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) if (!this->read_bufferram) this->read_bufferram = onenand_read_bufferram; - if (!this->read_spareram) - this->read_spareram = onenand_read_bufferram; if (!this->write_bufferram) this->write_bufferram = onenand_write_bufferram; diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 2597e347b4b..06f7bafeae1 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -83,10 +83,9 @@ struct onenand_chip { size_t len); int (*wait) (struct mtd_info *mtd, int state); int (*bbt_wait) (struct mtd_info *mtd, int state); + void (*unlock_all)(struct mtd_info *mtd); int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area, unsigned char *buffer, int offset, size_t count); - int (*read_spareram) (struct mtd_info *mtd, loff_t addr, int area, - unsigned char *buffer, int offset, size_t count); int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area, const unsigned char *buffer, int offset, size_t count); -- cgit v1.3.1 From de4250929f37e6c16860741b74546bedbe0bdaba Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 21 Jul 2009 17:13:40 +0200 Subject: 83xx, kmeter1: added NAND support Signed-off-by: Heiko Schocher Signed-off-by: Scott Wood --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kmeter1_nand.c | 135 ++++++++++++++++++++++++++++++++++++++++ include/configs/kmeter1.h | 6 ++ 3 files changed, 142 insertions(+) create mode 100644 drivers/mtd/nand/kmeter1_nand.c (limited to 'include') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 55eee3c9baf..624310306ed 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o +COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o diff --git a/drivers/mtd/nand/kmeter1_nand.c b/drivers/mtd/nand/kmeter1_nand.c new file mode 100644 index 00000000000..e8e5b7b85e8 --- /dev/null +++ b/drivers/mtd/nand/kmeter1_nand.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000) +#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000) + +#define read_mode() in_8(CONFIG_NAND_MODE_REG) +#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val) +#define read_data() in_8(CONFIG_NAND_DATA_REG) +#define write_data(val) out_8(CONFIG_NAND_DATA_REG, val) + +#define KPN_RDY2 (1 << 7) +#define KPN_RDY1 (1 << 6) +#define KPN_WPN (1 << 4) +#define KPN_CE2N (1 << 3) +#define KPN_CE1N (1 << 2) +#define KPN_ALE (1 << 1) +#define KPN_CLE (1 << 0) + +#define KPN_DEFAULT_CHIP_DELAY 50 + +static int kpn_chip_ready(void) +{ + if (read_mode() & KPN_RDY1) + return 1; + + return 0; +} + +static void kpn_wait_rdy(void) +{ + int cnt = 1000000; + + while (--cnt && !kpn_chip_ready()) + udelay(1); + + if (!cnt) + printf ("timeout while waiting for RDY\n"); +} + +static void kpn_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + u8 reg_val = read_mode(); + + if (ctrl & NAND_CTRL_CHANGE) { + reg_val = reg_val & ~(KPN_ALE + KPN_CLE); + + if (ctrl & NAND_CLE) + reg_val = reg_val | KPN_CLE; + if (ctrl & NAND_ALE) + reg_val = reg_val | KPN_ALE; + if (ctrl & NAND_NCE) + reg_val = reg_val & ~KPN_CE1N; + else + reg_val = reg_val | KPN_CE1N; + + write_mode(reg_val); + } + if (cmd != NAND_CMD_NONE) + write_data(cmd); + + /* wait until flash is ready */ + kpn_wait_rdy(); +} + +static u_char kpn_nand_read_byte(struct mtd_info *mtd) +{ + return read_data(); +} + +static void kpn_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + write_data(buf[i]); + kpn_wait_rdy(); + } +} + +static void kpn_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + buf[i] = read_data(); +} + +static int kpn_nand_dev_ready(struct mtd_info *mtd) +{ + kpn_wait_rdy(); + + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + + /* Reference hardware control function */ + nand->cmd_ctrl = kpn_nand_hwcontrol; + nand->read_byte = kpn_nand_read_byte; + nand->write_buf = kpn_nand_write_buf; + nand->read_buf = kpn_nand_read_buf; + nand->dev_ready = kpn_nand_dev_ready; + nand->chip_delay = KPN_DEFAULT_CHIP_DELAY; + + /* reset mode register */ + write_mode(KPN_CE1N + KPN_CE2N + KPN_WPN); + return 0; +} diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 869fd4ca1a7..79d8638fe28 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -324,6 +324,12 @@ #define CONFIG_SYS_DTT_HYSTERESIS 3 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE +#endif + #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif -- cgit v1.3.1 From a2c65b47effcb3d0aa23e58596538acd338ac7c5 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 10 Aug 2009 13:27:46 -0400 Subject: NAND: ADD page Parameter to all read_page/read_page_raw API's This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: Sandeep Paulraj Signed-off-by: Sneha Narnakaje Signed-off-by: Scott Wood --- drivers/mtd/nand/fsl_elbc_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 16 +++++++++------- include/linux/mtd/nand.h | 4 ++-- 3 files changed, 12 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 77a33c07811..50cb4aa9dcf 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -662,7 +662,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf) + uint8_t *buf, int page) { fsl_elbc_read_buf(mtd, buf, mtd->writesize); fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 360b0708498..ca026286f20 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -895,7 +895,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) * @buf: buffer to store read data */ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf) + uint8_t *buf, int page) { chip->read_buf(mtd, buf, mtd->writesize); chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); @@ -909,7 +909,7 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, * @buf: buffer to store read data */ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf) + uint8_t *buf, int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -919,7 +919,7 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; - chip->ecc.read_page_raw(mtd, chip, buf); + chip->ecc.read_page_raw(mtd, chip, buf, page); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) chip->ecc.calculate(mtd, p, &ecc_calc[i]); @@ -1032,7 +1032,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3 * Not for syndrome calculating ecc controllers which need a special oob layout */ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf) + uint8_t *buf, int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -1077,7 +1077,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * we need a special oob layout and handling. */ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf) + uint8_t *buf, int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -1219,11 +1219,13 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, /* Now read the page into the buffer */ if (unlikely(ops->mode == MTD_OOB_RAW)) - ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); + ret = chip->ecc.read_page_raw(mtd, chip, + bufpoi, page); else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); else - ret = chip->ecc.read_page(mtd, chip, bufpoi); + ret = chip->ecc.read_page(mtd, chip, bufpoi, + page); if (ret < 0) break; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 3e0044b94f2..d6aa392ff42 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -268,13 +268,13 @@ struct nand_ecc_ctrl { uint8_t *calc_ecc); int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf); + uint8_t *buf, int page); void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf); int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf); + uint8_t *buf, int page); int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offs, uint32_t len, -- cgit v1.3.1 From f83b7f9e8a5d1334e24506ea5953dd871596ea8a Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 10 Aug 2009 13:27:56 -0400 Subject: MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj Signed-off-by: Sneha Narnakaje Signed-off-by: Scott Wood --- drivers/mtd/nand/nand_base.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/nand.h | 1 + 2 files changed, 60 insertions(+) (limited to 'include') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ca026286f20..426bb95e9e9 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1067,6 +1067,54 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, return 0; } +/** + * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * + * Hardware ECC for large page chips, require OOB to be read first. + * For this ECC mode, the write_page method is re-used from ECC_HW. + * These methods read/write ECC from the OOB area, unlike the + * ECC_HW_SYNDROME support with multiple ECC steps, follows the + * "infix ECC" scheme and reads/writes ECC from the data area, by + * overwriting the NAND manufacturer bad block markings. + */ +static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_code = chip->buffers->ecccode; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint8_t *ecc_calc = chip->buffers->ecccalc; + + /* Read the OOB area first */ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + /** * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read * @mtd: mtd info structure @@ -2730,6 +2778,17 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.write_page_raw = nand_write_page_raw; switch (chip->ecc.mode) { + case NAND_ECC_HW_OOB_FIRST: + /* Similar to NAND_ECC_HW, but a separate read_page handle */ + if (!chip->ecc.calculate || !chip->ecc.correct || + !chip->ecc.hwctl) { + printk(KERN_WARNING "No ECC functions supplied, " + "Hardware ECC not possible\n"); + BUG(); + } + if (!chip->ecc.read_page) + chip->ecc.read_page = nand_read_page_hwecc_oob_first; + case NAND_ECC_HW: /* Use standard hwecc read page function ? */ if (!chip->ecc.read_page) diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index d6aa392ff42..cb7c19a4392 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -128,6 +128,7 @@ typedef enum { NAND_ECC_SOFT, NAND_ECC_HW, NAND_ECC_HW_SYNDROME, + NAND_ECC_HW_OOB_FIRST, } nand_ecc_modes_t; /* -- cgit v1.3.1 From 77b351cd0f20483eefa09bebebb3e0cbf5555b2c Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Tue, 18 Aug 2009 10:10:42 -0400 Subject: NAND: DaVinci: V2 Adding 4 BIT ECC support This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj Signed-off-by: Scott Wood --- drivers/mtd/nand/davinci_nand.c | 284 ++++++++++++++++++++++++++++++- include/asm-arm/arch-davinci/emif_defs.h | 10 ++ 2 files changed, 292 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 7837a8e3275..37d8b7312cf 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -47,6 +47,16 @@ #include #include +/* Definitions for 4-bit hardware ECC */ +#define NAND_TIMEOUT 10240 +#define NAND_ECC_BUSY 0xC +#define NAND_4BITECC_MASK 0x03FF03FF +#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 +#define ECC_STATE_NO_ERR 0x0 +#define ECC_STATE_TOO_MANY_ERRS 0x1 +#define ECC_STATE_ERR_CORR_COMP_P 0x2 +#define ECC_STATE_ERR_CORR_COMP_N 0x3 + static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) @@ -170,6 +180,268 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char * } #endif /* CONFIG_SYS_NAND_HW_ECC */ +#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { +/* + * TI uses a different layout for 4K page deviecs. Since the + * eccpos filed can hold only a limited number of entries, adding + * support for 4K page will result in compilation warnings + * 4K Support will be added later + */ +#ifdef CONFIG_SYS_NAND_PAGE_2K + .eccbytes = 40, + .eccpos = { + 24, 25, 26, 27, 28, + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, + 59, 60, 61, 62, 63, + }, + .oobfree = { + {.offset = 2, .length = 22, }, + }, +#endif +}; +#endif + +static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) +{ + u32 val; + + switch (mode) { + case NAND_ECC_WRITE: + case NAND_ECC_READ: + /* + * Start a new ECC calculation for reading or writing 512 bytes + * of data. + */ + val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12); + emif_regs->NANDFCR = val; + break; + case NAND_ECC_READSYN: + val = emif_regs->NAND4BITECC1; + break; + default: + break; + } +} + +static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4]) +{ + ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK; + ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK; + ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK; + ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK; + + return 0; +} + +static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd, + const uint8_t *dat, + uint8_t *ecc_code) +{ + unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }; + unsigned int const1 = 0, const2 = 0; + unsigned char count1 = 0; + + nand_davinci_4bit_readecc(mtd, hw_4ecc); + + /*Convert 10 bit ecc value to 8 bit */ + for (count1 = 0; count1 < 2; count1++) { + const2 = count1 * 5; + const1 = count1 * 2; + + /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */ + ecc_code[const2] = hw_4ecc[const1] & 0xFF; + + /* + * Take 2 bits as LSB bits from val1 (count1=0) or val5 + * (count1=1) and 6 bits from val2 (count1=0) or + * val5 (count1=1) + */ + ecc_code[const2 + 1] = + ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) & + 0xFC); + + /* + * Take 4 bits from val2 (count1=0) or val5 (count1=1) and + * 4 bits from val3 (count1=0) or val6 (count1=1) + */ + ecc_code[const2 + 2] = + ((hw_4ecc[const1] >> 22) & 0xF) | + ((hw_4ecc[const1 + 1] << 4) & 0xF0); + + /* + * Take 6 bits from val3(count1=0) or val6 (count1=1) and + * 2 bits from val4 (count1=0) or val7 (count1=1) + */ + ecc_code[const2 + 3] = + ((hw_4ecc[const1 + 1] >> 4) & 0x3F) | + ((hw_4ecc[const1 + 1] >> 10) & 0xC0); + + /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */ + ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF; + } + return 0; +} + + +static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + struct nand_chip *this = mtd->priv; + unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + int i; + unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0; + unsigned short *pspare = NULL, *pspare1 = NULL; + unsigned int numerrors, erroraddress, errorvalue; + u32 val; + + /* + * Check for an ECC where all bytes are 0xFF. If this is the case, we + * will assume we are looking at an erased page and we should ignore + * the ECC. + */ + for (i = 0; i < 10; i++) { + if (read_ecc[i] != 0xFF) + break; + } + if (i == 10) + return 0; + + /* Convert 8 bit in to 10 bit */ + pspare = (unsigned short *)&read_ecc[2]; + pspare1 = (unsigned short *)&read_ecc[0]; + + /* Take 10 bits from 0th and 1st bytes */ + ecc_10bit[0] = (*pspare1) & 0x3FF; + + /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ + ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F) + | (((pspare[0]) << 6) & 0x3C0); + + /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ + ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF; + + /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ + ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3) + | ((((pspare[1])) << 2) & 0x3FC); + + /* Take 8 bits from 5th byte and 2 bits from 6th byte */ + ecc_10bit[4] = ((pspare[1]) >> 8) + | ((((pspare[2])) << 8) & 0x300); + + /* Take 6 bits from 6th byte and 4 bits from 7th byte */ + ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF; + + /* Take 4 bits from 7th byte and 6 bits from 8th byte */ + ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF) + | ((((pspare[3])) << 4) & 0x3F0); + + /*Take 2 bits from 8th byte and 8 bits from 9th byte */ + ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF; + + /* + * Write the parity values in the NAND Flash 4-bit ECC Load register. + * Write each parity value one at a time starting from 4bit_ecc_val8 + * to 4bit_ecc_val1. + */ + for (i = 7; i >= 0; i--) + emif_regs->NAND4BITECCLOAD = ecc_10bit[i]; + + /* + * Perform a dummy read to the EMIF Revision Code and Status register. + * This is required to ensure time for syndrome calculation after + * writing the ECC values in previous step. + */ + + val = emif_regs->NANDFSR; + + /* + * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers. + * A syndrome value of 0 means no bit errors. If the syndrome is + * non-zero then go further otherwise return. + */ + nand_davinci_4bit_readecc(mtd, hw_4ecc); + + if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR && + hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR) + return 0; + + /* + * Clear any previous address calculation by doing a dummy read of an + * error address register. + */ + val = emif_regs->NANDERRADD1; + + /* + * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control + * register to 1. + */ + emif_regs->NANDFCR |= 1 << 13; + + /* + * Wait for the corr_state field (bits 8 to 11)in the + * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3. + */ + i = NAND_TIMEOUT; + do { + val = emif_regs->NANDFSR; + val &= 0xc00; + i--; + } while ((i > 0) && val); + + iserror = emif_regs->NANDFSR; + iserror &= EMIF_NANDFSR_ECC_STATE_MASK; + iserror = iserror >> 8; + + /* + * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be + * corrected (five or more errors). The number of errors + * calculated (err_num field) differs from the number of errors + * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error + * correction complete (errors on bit 8 or 9). + * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction + * complete (error exists). + */ + + if (iserror == ECC_STATE_NO_ERR) { + val = emif_regs->NANDERRVAL1; + return 0; + } else if (iserror == ECC_STATE_TOO_MANY_ERRS) { + val = emif_regs->NANDERRVAL1; + return -1; + } + + numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1; + + /* Read the error address, error value and correct */ + for (i = 0; i < numerrors; i++) { + if (i > 1) { + erroraddress = + ((emif_regs->NANDERRADD2 >> + (16 * (i & 1))) & 0x3FF); + erroraddress = ((512 + 7) - erroraddress); + errorvalue = + ((emif_regs->NANDERRVAL2 >> + (16 * (i & 1))) & 0xFF); + } else { + erroraddress = + ((emif_regs->NANDERRADD1 >> + (16 * (i & 1))) & 0x3FF); + erroraddress = ((512 + 7) - erroraddress); + errorvalue = + ((emif_regs->NANDERRVAL1 >> + (16 * (i & 1))) & 0xFF); + } + /* xor the corrupt data with error value */ + if (erroraddress < 512) + dat[erroraddress] ^= errorvalue; + } + + return numerrors; +} + static int nand_davinci_dev_ready(struct mtd_info *mtd) { return emif_regs->NANDFSR & 0x1; @@ -215,7 +487,7 @@ void davinci_nand_init(struct nand_chip *nand) { nand->chip_delay = 0; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT - nand->options = NAND_USE_FLASH_BBT; + nand->options |= NAND_USE_FLASH_BBT; #endif #ifdef CONFIG_SYS_NAND_HW_ECC nand->ecc.mode = NAND_ECC_HW; @@ -227,7 +499,15 @@ void davinci_nand_init(struct nand_chip *nand) #else nand->ecc.mode = NAND_ECC_SOFT; #endif /* CONFIG_SYS_NAND_HW_ECC */ - +#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; + nand->ecc.size = 512; + nand->ecc.bytes = 10; + nand->ecc.calculate = nand_davinci_4bit_calculate_ecc; + nand->ecc.correct = nand_davinci_4bit_correct_data; + nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc; + nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst; +#endif /* Set address of hardware control function */ nand->cmd_ctrl = nand_davinci_hwcontrol; diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index 646fc774694..c91e30c8fca 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -55,6 +55,16 @@ typedef struct { dv_reg NANDF2ECC; dv_reg NANDF3ECC; dv_reg NANDF4ECC; + u_int8_t RSVD2[60]; + dv_reg NAND4BITECCLOAD; + dv_reg NAND4BITECC1; + dv_reg NAND4BITECC2; + dv_reg NAND4BITECC3; + dv_reg NAND4BITECC4; + dv_reg NANDERRADD1; + dv_reg NANDERRADD2; + dv_reg NANDERRVAL1; + dv_reg NANDERRVAL2; } emif_registers; typedef emif_registers *emifregs; -- cgit v1.3.1 From fb3143b35eb5890ec72e79d17a6068a84a057d47 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 3 Aug 2009 20:44:55 -0500 Subject: pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_init Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala --- board/atum8548/atum8548.c | 10 +++------- board/freescale/mpc8536ds/mpc8536ds.c | 13 ++++--------- board/freescale/mpc8544ds/mpc8544ds.c | 13 ++++--------- board/freescale/mpc8548cds/mpc8548cds.c | 6 ++---- board/freescale/mpc8568mds/mpc8568mds.c | 6 ++---- board/freescale/mpc8569mds/mpc8569mds.c | 4 +--- board/freescale/mpc8572ds/mpc8572ds.c | 10 +++------- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 12 +++--------- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 6 ++---- board/freescale/p2020ds/p2020ds.c | 13 +++---------- board/sbc8548/sbc8548.c | 6 ++---- board/sbc8641d/sbc8641d.c | 6 ++---- board/tqc/tqm85xx/tqm85xx.c | 8 ++------ board/xes/common/fsl_8xxx_pci.c | 16 ++++------------ drivers/pci/fsl_pci_init.c | 6 ++++-- include/asm-ppc/fsl_pci.h | 2 +- 16 files changed, 42 insertions(+), 95 deletions(-) (limited to 'include') diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index c8085c7079c..7a02cdc5b98 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -244,9 +244,7 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", @@ -302,9 +300,8 @@ pci_init_board(void) PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf ("PCI1 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); @@ -338,9 +335,8 @@ pci_init_board(void) PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf ("PCI2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 8c5984bf5f7..9d2753e6e09 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -250,9 +250,8 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCIE3 on bus %02x - %02x\n", @@ -313,9 +312,7 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", @@ -375,9 +372,8 @@ pci_init_board(void) #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCIE2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); @@ -443,9 +439,8 @@ pci_init_board(void) #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n", hose->first_busno,hose->last_busno); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index fd59839b32b..60bde681ea5 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -166,9 +166,8 @@ pci_init_board(void) #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCIE3 on bus %02x - %02x\n", @@ -234,9 +233,7 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", @@ -296,9 +293,8 @@ pci_init_board(void) #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCIE2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); @@ -364,9 +360,8 @@ pci_init_board(void) #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n", hose->first_busno,hose->last_busno); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ac1c9b4780b..d0856c43c01 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -323,9 +323,8 @@ pci_init_board(void) table->config_device += gd->reloc_off; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK @@ -402,9 +401,8 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); first_free_busno=hose->last_busno+1; diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 8f991e537df..811bf5e524a 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -409,9 +409,8 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); } else { @@ -462,9 +461,8 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); first_free_busno=hose->last_busno+1; diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 1e7526a1aeb..45c518a7b35 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -367,10 +367,8 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, - (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf ("PCIE on bus %02x - %02x\n", hose->first_busno,hose->last_busno); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 7c86134d5f2..9d5cfd79a6a 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -220,9 +220,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCIE3 on bus %02x - %02x\n", @@ -289,9 +288,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCIE2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); @@ -345,9 +343,7 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 2ac169b7909..98896d18a04 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -280,10 +280,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno + 1; printf(" PCI-Express 1 on bus %02x - %02x\n", @@ -335,10 +333,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno + 1; printf(" PCI-Express 2 on bus %02x - %02x\n", @@ -384,10 +380,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, - (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno + 1; printf(" PCI on bus %02x - %02x\n", diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index a8b2112264e..de899e8d8a7 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -193,9 +193,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", @@ -242,9 +241,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 14de7e740c8..e2cd39c9ef1 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -254,10 +254,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno+1; printf(" PCIE2 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); @@ -327,10 +325,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno+1; printf(" PCIE3 on bus %02x - %02x\n", @@ -381,10 +377,7 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno = hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 9c05c2f1728..978d91b4f2c 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -403,9 +403,8 @@ pci_init_board(void) table->config_device += gd->reloc_off; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK @@ -486,9 +485,8 @@ pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); first_free_busno=hose->last_busno+1; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index f118a6eaa6a..6d68c8e849f 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -259,9 +259,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", @@ -302,9 +301,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index ab0e0dd8838..07a6db3b8dd 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -596,10 +596,8 @@ static inline void init_pci1(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect (hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init (hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf (" PCI on bus %02x..%02x\n", hose->first_busno, hose->last_busno); @@ -673,10 +671,8 @@ static inline void init_pcie1(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init (hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf (" PCIe on bus %02x..%02x\n", hose->first_busno, hose->last_busno); diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 025cc1802de..3a4e5236b79 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -233,10 +233,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); /* Unlock inbound PCI configuration cycles */ if (!host) @@ -289,10 +287,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int) &pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); /* Unlock inbound PCI configuration cycles */ if (!host) @@ -343,10 +339,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); /* Unlock inbound PCI configuration cycles */ if (!host) @@ -397,10 +391,8 @@ void pci_init_board(void) hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int)&pci->cfg_addr, - (int)&pci->cfg_data); - fsl_pci_init(hose); + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); /* Unlock inbound PCI configuration cycles */ if (!host) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 19cf1ce1a04..8858657b9ee 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -133,7 +133,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r) return r - rgn_base; } -void fsl_pci_init(struct pci_controller *hose) +void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) { u16 temp16; u32 temp32; @@ -144,7 +144,7 @@ void fsl_pci_init(struct pci_controller *hose) int r; int bridge; int inbound = 0; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); /* Initialize ATMU registers based on hose regions and flags */ @@ -155,6 +155,8 @@ void fsl_pci_init(struct pci_controller *hose) int neg_link_w; #endif + pci_setup_indirect(hose, cfg_addr, cfg_data); + for (r=0; rregion_count; r++) { u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */ diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index 624ca5685a9..0473b720c5f 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -21,7 +21,7 @@ #define __FSL_PCI_H_ int fsl_pci_setup_inbound_windows(struct pci_region *r); -void fsl_pci_init(struct pci_controller *hose); +void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *pci_alias, struct pci_controller *hose); -- cgit v1.3.1 From cb151aa2cf5fbb1e412fc763a3a611758f066238 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 3 Aug 2009 21:02:02 -0500 Subject: pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala --- board/atum8548/atum8548.c | 8 -------- board/freescale/mpc8536ds/mpc8536ds.c | 12 ------------ board/freescale/mpc8544ds/mpc8544ds.c | 12 ------------ board/freescale/mpc8548cds/mpc8548cds.c | 7 ------- board/freescale/mpc8568mds/mpc8568mds.c | 6 ------ board/freescale/mpc8569mds/mpc8569mds.c | 3 --- board/freescale/mpc8572ds/mpc8572ds.c | 9 --------- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 9 --------- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 6 ------ board/freescale/p2020ds/p2020ds.c | 9 --------- board/sbc8548/sbc8548.c | 11 ----------- board/sbc8641d/sbc8641d.c | 7 ------- board/tqc/tqm85xx/tqm85xx.c | 7 ------- board/xes/common/fsl_8xxx_pci.c | 12 ------------ drivers/pci/fsl_pci_init.c | 8 +++++++- include/asm-ppc/fsl_pci.h | 1 - 16 files changed, 7 insertions(+), 120 deletions(-) (limited to 'include') diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 7a02cdc5b98..85c0adc70cf 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -216,9 +216,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE, @@ -282,9 +279,6 @@ pci_init_board(void) (uint)pci ); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, @@ -320,8 +314,6 @@ pci_init_board(void) struct pci_region *r = hose->regions; if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { - r += fsl_pci_setup_inbound_windows(r); - pci_set_region(r++, CONFIG_SYS_PCI2_MEM_BASE, CONFIG_SYS_PCI2_MEM_PHYS, diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 9d2753e6e09..5bd20cee6d2 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -230,9 +230,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS, @@ -284,9 +281,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, @@ -345,9 +339,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, @@ -412,9 +403,6 @@ pci_init_board(void) (uint)pci ); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 60bde681ea5..5a47d0a008e 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -139,9 +139,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS, @@ -205,9 +202,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, @@ -266,9 +260,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, @@ -333,9 +324,6 @@ pci_init_board(void) (uint)pci ); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index d0856c43c01..9df5f822e15 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -297,10 +297,6 @@ pci_init_board(void) pci_arb ? "arbiter" : "external-arbiter" ); - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, @@ -381,9 +377,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 811bf5e524a..fe505b05c15 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -389,9 +389,6 @@ pci_init_board(void) pci_arb ? "arbiter" : "external-arbiter" ); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, @@ -441,9 +438,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 45c518a7b35..63c21dd2a38 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -347,9 +347,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 9d5cfd79a6a..59d751938e5 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -201,9 +201,6 @@ void pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS, @@ -269,9 +266,6 @@ void pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, @@ -323,9 +317,6 @@ void pci_init_board(void) } printf ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 98896d18a04..45000d92b22 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -260,9 +260,6 @@ void pci_init_board(void) if (pci->pme_msg_det) pci->pme_msg_det = 0xffffffff; - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, @@ -313,9 +310,6 @@ void pci_init_board(void) if (pci->pme_msg_det) pci->pme_msg_det = 0xffffffff; - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, @@ -360,9 +354,6 @@ void pci_init_board(void) pci_agent ? "Agent" : "Host", (uint)pci); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index de899e8d8a7..fab4fae058c 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -187,9 +187,6 @@ void pci_init_board(void) CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; @@ -235,9 +232,6 @@ void pci_init_board(void) CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index e2cd39c9ef1..3fe72cd32c3 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -235,9 +235,6 @@ void pci_init_board(void) } printf("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, @@ -306,9 +303,6 @@ void pci_init_board(void) } printf("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS, @@ -357,9 +351,6 @@ void pci_init_board(void) } printf("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 978d91b4f2c..1ae4cda8b0e 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -377,10 +377,6 @@ pci_init_board(void) pci_arb ? "arbiter" : "external-arbiter" ); - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, @@ -461,13 +457,6 @@ pci_init_board(void) } printf ("\n"); - /* inbound */ - pci_set_region(r++, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE, diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 6d68c8e849f..aabefa9a756 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -239,9 +239,6 @@ void pci_init_board(void) } debug("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, @@ -280,10 +277,6 @@ void pci_init_board(void) struct pci_controller *hose = &pci2_hose; struct pci_region *r = hose->regions; - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI2_MEM_BUS, diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 07a6db3b8dd..277edcd14e8 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -575,10 +575,6 @@ static inline void init_pci1(void) pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region (r++, CONFIG_SYS_PCI1_MEM_BASE, @@ -651,9 +647,6 @@ static inline void init_pcie1(void) } puts ("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region (r++, CONFIG_SYS_PCIE1_MEM_BASE, diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 3a4e5236b79..463588f68d8 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -213,9 +213,6 @@ void pci_init_board(void) host ? "host" : "agent", pci_arb ? "arbiter" : "external-arbiter"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, @@ -267,9 +264,6 @@ void pci_init_board(void) } printf("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE, @@ -319,9 +313,6 @@ void pci_init_board(void) } printf("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BASE, @@ -371,9 +362,6 @@ void pci_init_board(void) } printf("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BASE, diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 8858657b9ee..c40ab3086d0 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -60,7 +60,7 @@ void pciauto_config_init(struct pci_controller *hose); #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) #endif -int fsl_pci_setup_inbound_windows(struct pci_region *r) +static int fsl_pci_setup_inbound_windows(struct pci_region *r) { struct pci_region *rgn_base = r; u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1); @@ -145,6 +145,7 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) int bridge; int inbound = 0; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + struct pci_region *reg = hose->regions + hose->region_count; pci_dev_t dev = PCI_BDF(busno,0,0); /* Initialize ATMU registers based on hose regions and flags */ @@ -157,6 +158,11 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) pci_setup_indirect(hose, cfg_addr, cfg_data); + /* inbound */ + reg += fsl_pci_setup_inbound_windows(reg); + + hose->region_count = reg - hose->regions; + for (r=0; rregion_count; r++) { u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */ diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index 0473b720c5f..b2ff0e929af 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -20,7 +20,6 @@ #ifndef __FSL_PCI_H_ #define __FSL_PCI_H_ -int fsl_pci_setup_inbound_windows(struct pci_region *r); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *pci_alias, -- cgit v1.3.1 From 8295b94400449586505ffe34ec024feb3d2c8fe4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 5 Aug 2009 07:49:27 -0500 Subject: pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala --- drivers/pci/fsl_pci_init.c | 32 +++++++++++++------------------- include/pci.h | 1 + 2 files changed, 14 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index c40ab3086d0..f9c0752c425 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -137,16 +137,12 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) { u16 temp16; u32 temp32; - int busno = hose->first_busno; - int enabled; + int enabled, r, inbound = 0; u16 ltssm; - u8 temp8; - int r; - int bridge; - int inbound = 0; + u8 temp8, pcie_cap; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; struct pci_region *reg = hose->regions + hose->region_count; - pci_dev_t dev = PCI_BDF(busno,0,0); + pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); /* Initialize ATMU registers based on hose regions and flags */ volatile pot_t *po = &pci->pot[1]; /* skip 0 */ @@ -198,6 +194,9 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) } } + /* see if we are a PCIe or PCI controller */ + pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pci_register_hose(hose); pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ hose->current_busno = hose->first_busno; @@ -212,11 +211,7 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); - pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); - bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ - - if ( bridge ) { - + if (pcie_cap == PCI_CAP_ID_EXP) { pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); enabled = ltssm >= PCI_LTSSM_L0; @@ -260,14 +255,12 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) #endif hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); - } /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. */ - pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); @@ -294,7 +287,10 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) hose->last_busno = hose->current_busno; } - if ( bridge ) { /* update limit regs and subordinate busno */ + /* if we are PCIe - update limit regs and subordinate busno + * for the virtual P2P bridge + */ + if (pcie_cap == PCI_CAP_ID_EXP) { pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); } #else @@ -302,15 +298,13 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) #endif /* Clear all error indications */ - - if (bridge) + if (pcie_cap == PCI_CAP_ID_EXP) pci->pme_msg_det = 0xffffffff; pci->pedr = 0xffffffff; pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); if (temp16) { - pci_hose_write_config_word(hose, dev, - PCI_DSR, 0xffff); + pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); diff --git a/include/pci.h b/include/pci.h index aaa45543445..491f814e413 100644 --- a/include/pci.h +++ b/include/pci.h @@ -222,6 +222,7 @@ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 -- cgit v1.3.1 From ad19e7a5d2de337064ce7728d6504df9648f5d31 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 5 Aug 2009 07:59:35 -0500 Subject: pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala --- drivers/pci/fsl_pci_init.c | 225 ++++++++++++++++++++++++++++++------------ include/configs/MPC8610HPCD.h | 1 + include/configs/sbc8641d.h | 1 + 3 files changed, 164 insertions(+), 63 deletions(-) (limited to 'include') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index f9c0752c425..ee89aaae5af 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #include +#include #include /* Freescale-specific PCI config registers */ @@ -60,35 +61,98 @@ void pciauto_config_init(struct pci_controller *hose); #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) #endif -static int fsl_pci_setup_inbound_windows(struct pci_region *r) +/* Setup one inbound ATMU window. + * + * We let the caller decide what the window size should be + */ +static void set_inbound_window(volatile pit_t *pi, + struct pci_region *r, + u64 size) { - struct pci_region *rgn_base = r; - u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1); + u32 sz = (__ilog2_u64(size) - 1); + u32 flag = PIWAR_EN | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; + + out_be32(&pi->pitar, r->phys_start >> 12); + out_be32(&pi->piwbar, r->bus_start >> 12); +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&pi->piwbear, r->bus_start >> 44); +#else + out_be32(&pi->piwbear, 0); +#endif + if (r->flags & PCI_REGION_PREFETCH) + flag |= PIWAR_PF; + out_be32(&pi->piwar, flag | sz); +} + +static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, + u64 out_lo, u8 pcie_cap, + volatile pit_t *pi) +{ + struct pci_region *r = hose->regions + hose->region_count; + u64 sz = min((u64)gd->ram_size, (1ull << 32)); phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; - pci_size_t pci_sz = 1ull << __ilog2_u64(sz); + pci_size_t pci_sz; - debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", - (u64)bus_start, (u64)phys_start, (u64)pci_sz); - pci_set_region(r++, bus_start, phys_start, pci_sz, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | - PCI_REGION_PREFETCH); + /* we have no space available for inbound memory mapping */ + if (bus_start > out_lo) { + printf ("no space for inbound mapping of memory\n"); + return 0; + } - sz -= pci_sz; - bus_start += pci_sz; - phys_start += pci_sz; + /* limit size */ + if ((bus_start + sz) > out_lo) { + sz = out_lo - bus_start; + debug ("limiting size to %llx\n", sz); + } pci_sz = 1ull << __ilog2_u64(sz); - if (sz) { - debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", + /* + * we can overlap inbound/outbound windows on PCI-E since RX & TX + * links a separate + */ + if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { + debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)bus_start, (u64)phys_start, (u64)sz); + pci_set_region(r, bus_start, phys_start, sz, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | + PCI_REGION_PREFETCH); + + /* if we aren't an exact power of two match, pci_sz is smaller + * round it up to the next power of two. We report the actual + * size to pci region tracking. + */ + if (pci_sz != sz) + sz = 2ull << __ilog2_u64(sz); + + set_inbound_window(pi--, r++, sz); + sz = 0; /* make sure we dont set the R2 window */ + } else { + debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", (u64)bus_start, (u64)phys_start, (u64)pci_sz); - pci_set_region(r++, bus_start, phys_start, pci_sz, + pci_set_region(r, bus_start, phys_start, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); + set_inbound_window(pi--, r++, pci_sz); + sz -= pci_sz; bus_start += pci_sz; phys_start += pci_sz; + + pci_sz = 1ull << __ilog2_u64(sz); + if (sz) { + debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)bus_start, (u64)phys_start, (u64)pci_sz); + pci_set_region(r, bus_start, phys_start, pci_sz, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | + PCI_REGION_PREFETCH); + set_inbound_window(pi--, r++, pci_sz); + sz -= pci_sz; + bus_start += pci_sz; + phys_start += pci_sz; + } } #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) @@ -104,23 +168,25 @@ static int fsl_pci_setup_inbound_windows(struct pci_region *r) (u64)CONFIG_SYS_PCI64_MEMORY_BUS, (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); - pci_set_region(r++, + pci_set_region(r, CONFIG_SYS_PCI64_MEMORY_BUS, CONFIG_SYS_PCI_MEMORY_PHYS, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); + set_inbound_window(pi--, r++, pci_sz); #else pci_sz = 1ull << __ilog2_u64(sz); if (sz) { debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", (u64)bus_start, (u64)phys_start, (u64)pci_sz); - pci_set_region(r++, bus_start, phys_start, pci_sz, + pci_set_region(r, bus_start, phys_start, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); sz -= pci_sz; bus_start += pci_sz; phys_start += pci_sz; + set_inbound_window(pi--, r++, pci_sz); } #endif @@ -130,7 +196,9 @@ static int fsl_pci_setup_inbound_windows(struct pci_region *r) "inbound windows -- %lld remaining\n", sz); #endif - return r - rgn_base; + hose->region_count = r - hose->regions; + + return 1; } void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) @@ -146,7 +214,10 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) /* Initialize ATMU registers based on hose regions and flags */ volatile pot_t *po = &pci->pot[1]; /* skip 0 */ - volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */ + volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ + + u64 out_hi = 0, out_lo = -1ULL; + u32 pcicsrbar, pcicsrbar_sz; #ifdef DEBUG int neg_link_w; @@ -154,60 +225,81 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) pci_setup_indirect(hose, cfg_addr, cfg_data); - /* inbound */ - reg += fsl_pci_setup_inbound_windows(reg); + /* Handle setup of outbound windows first */ + for (r = 0; r < hose->region_count; r++) { + unsigned long flags = hose->regions[r].flags; + u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); - hose->region_count = reg - hose->regions; + flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; + if (flags != PCI_REGION_SYS_MEMORY) { + u64 start = hose->regions[r].bus_start; + u64 end = start + hose->regions[r].size; - for (r=0; rregion_count; r++) { - u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); - if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */ - u32 flag = PIWAR_EN | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; - pi->pitar = (hose->regions[r].phys_start >> 12); - pi->piwbar = (hose->regions[r].bus_start >> 12); -#ifdef CONFIG_SYS_PCI_64BIT - pi->piwbear = (hose->regions[r].bus_start >> 44); -#else - pi->piwbear = 0; -#endif - if (hose->regions[r].flags & PCI_REGION_PREFETCH) - flag |= PIWAR_PF; - pi->piwar = flag | sz; - pi++; - inbound = hose->regions[r].size > 0; - } else { /* Outbound */ - po->powbar = (hose->regions[r].phys_start >> 12); - po->potar = (hose->regions[r].bus_start >> 12); + out_be32(&po->powbar, hose->regions[r].phys_start >> 12); + out_be32(&po->potar, start >> 12); #ifdef CONFIG_SYS_PCI_64BIT - po->potear = (hose->regions[r].bus_start >> 44); + out_be32(&po->potear, start >> 44); #else - po->potear = 0; + out_be32(&po->potear, 0); #endif - if (hose->regions[r].flags & PCI_REGION_IO) - po->powar = POWAR_EN | sz | - POWAR_IO_READ | POWAR_IO_WRITE; - else - po->powar = POWAR_EN | sz | - POWAR_MEM_READ | POWAR_MEM_WRITE; + if (hose->regions[r].flags & PCI_REGION_IO) { + out_be32(&po->powar, POWAR_EN | sz | + POWAR_IO_READ | POWAR_IO_WRITE); + } else { + out_be32(&po->powar, POWAR_EN | sz | + POWAR_MEM_READ | POWAR_MEM_WRITE); + out_lo = min(start, out_lo); + out_hi = max(end, out_hi); + } po++; } } + debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); + + /* setup PCSRBAR/PEXCSRBAR */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); + pcicsrbar_sz = ~pcicsrbar_sz + 1; + + if (out_hi < (0x100000000ull - pcicsrbar_sz) || + (out_lo > 0x100000000ull)) + pcicsrbar = 0x100000000ull - pcicsrbar_sz; + else + pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); + + out_lo = min(out_lo, (u64)pcicsrbar); + + debug("PCICSRBAR @ 0x%x\n", pcicsrbar); + + pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, + pcicsrbar_sz, PCI_REGION_SYS_MEMORY); + hose->region_count++; /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + /* inbound */ + inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); + + for (r = 0; r < hose->region_count; r++) + debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r, + (u64)hose->regions[r].phys_start, + hose->regions[r].bus_start, + hose->regions[r].size, + hose->regions[r].flags); + pci_register_hose(hose); pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ hose->current_busno = hose->first_busno; - pci->pedr = 0xffffffff; /* Clear any errors */ - pci->peer = ~0x20140; /* Enable All Error Interupts except + out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ + out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except * - Master abort (pci) * - Master PERR (pci) * - ICCA (PCIe) */ - pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); + pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); @@ -218,14 +310,15 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) #ifdef CONFIG_FSL_PCIE_RESET if (ltssm == 1) { int i; - debug("....PCIe link error. " - "LTSSM=0x%02x.", ltssm); - pci->pdb_stat |= 0x08000000; /* assert PCIe reset */ - temp32 = pci->pdb_stat; + debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); udelay(100); debug(" Asserting PCIe reset @%x = %x\n", - &pci->pdb_stat, pci->pdb_stat); - pci->pdb_stat &= ~0x08000000; /* clear reset */ + &pci->pdb_stat, in_be32(&pci->pdb_stat)); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); asm("sync;isync"); for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { pci_hose_read_config_word(hose, dev, PCI_LTSSM, @@ -235,6 +328,12 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) "LTSSM=0x%02x.\n", ltssm); } enabled = ltssm >= PCI_LTSSM_L0; + + /* we need to re-write the bar0 since a reset will + * clear it + */ + pci_hose_write_config_dword(hose, dev, + PCI_BASE_ADDRESS_0, pcicsrbar); } #endif @@ -245,8 +344,8 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) return; } - pci->pme_msg_det = 0xffffffff; - pci->pme_msg_int_en = 0xffffffff; + out_be32(&pci->pme_msg_det, 0xffffffff); + out_be32(&pci->pme_msg_int_en, 0xffffffff); #ifdef DEBUG pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); neg_link_w = (temp16 & 0x3f0 ) >> 4; @@ -299,8 +398,8 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) /* Clear all error indications */ if (pcie_cap == PCI_CAP_ID_EXP) - pci->pme_msg_det = 0xffffffff; - pci->pedr = 0xffffffff; + out_be32(&pci->pme_msg_det, 0xffffffff); + out_be32(&pci->pedr, 0xffffffff); pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); if (temp16) { diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index a3b5c7c3d3d..44ff289f85e 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -81,6 +81,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index ef0f627b6ca..abc449d05fd 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -107,6 +107,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -- cgit v1.3.1 From 337f9fde2e9317c1d9e85a4a8955a2f14730a00f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Jul 2009 15:54:07 -0500 Subject: 85xx: Add a 36-bit physical configuration for MPC8536DS We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk Signed-off-by: Kumar Gala --- Makefile | 5 ++- include/configs/MPC8536DS.h | 82 +++++++++++++++++++++++++++++++++++++++------ 2 files changed, 76 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index 2fa43a57a84..9821ffd55e4 100644 --- a/Makefile +++ b/Makefile @@ -2440,8 +2440,11 @@ vme8349_config: unconfig ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548 +MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8536ds freescale + @mkdir -p $(obj)include + @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h + @$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale MPC8540ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9d2b8600c29..f08f5ab6a17 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MPC8536DS_36BIT +#define CONFIG_PHYS_64BIT 1 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -77,6 +81,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x7fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -87,7 +96,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) @@ -96,6 +109,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) /* DDR Setup */ +#define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ @@ -170,7 +184,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 @@ -178,7 +196,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -199,7 +217,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else #define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ @@ -254,8 +276,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000, \ @@ -368,42 +394,78 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 +#endif +#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull +#else #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull +#else #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) -- cgit v1.3.1 From bafdf9aa9dbb69d937b72db17ed5800998c59523 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 4 Aug 2009 17:38:00 -0500 Subject: 85xx: Remove unused CONFIG_CLEAR_LAW0 defines Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/configs/ATUM8548.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/sbc8548.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 7ee05e56587..91369a71e11 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -67,7 +67,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bebb9e9611a..e69ba901edc 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -69,7 +69,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index a2ff9557ce5..838b4db9ad4 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -59,7 +59,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. -- cgit v1.3.1 From 0e870980a64584a591af775bb9c9fe9450124df9 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 31 Jul 2009 12:08:14 +0530 Subject: 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- common/cmd_mp.c | 6 +-- cpu/mpc85xx/cpu.c | 21 +++++----- cpu/mpc85xx/mp.c | 6 +-- cpu/mpc85xx/release.S | 25 +++++++++++- cpu/mpc85xx/speed.c | 4 +- cpu/mpc86xx/cpu.c | 10 +++-- cpu/mpc86xx/cpu_init.c | 4 +- cpu/mpc8xxx/cpu.c | 93 +++++++++++++++++++++++++++---------------- include/asm-ppc/config.h | 7 ++++ include/asm-ppc/global_data.h | 1 + include/asm-ppc/processor.h | 5 ++- include/common.h | 2 + include/configs/MPC8572DS.h | 1 - include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/P2020DS.h | 1 - include/configs/XPEDITE5170.h | 1 - include/configs/XPEDITE5370.h | 1 - include/configs/sbc8641d.h | 1 - include/e500.h | 6 +-- lib_ppc/board.c | 3 ++ lib_ppc/bootm.c | 2 +- 22 files changed, 127 insertions(+), 75 deletions(-) (limited to 'include') diff --git a/common/cmd_mp.c b/common/cmd_mp.c index faa87001329..71e430362fd 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -34,9 +34,9 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } cpuid = simple_strtoul(argv[1], NULL, 10); - if (cpuid >= CONFIG_NUM_CPUS) { + if (cpuid >= cpu_numcores()) { printf ("Core num: %lu is out of range[0..%d]\n", - cpuid, CONFIG_NUM_CPUS - 1); + cpuid, cpu_numcores() - 1); return 1; } diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 4724f2764d3..6be98dc350c 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -54,24 +54,23 @@ int checkcpu (void) int i; svr = get_svr(); - ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); -#if (CONFIG_NUM_CPUS > 1) - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); - printf("CPU%d: ", pic->whoami); -#else - puts("CPU: "); -#endif + if (cpu_numcores() > 1) { + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); + } else { + puts("CPU: "); + } - cpu = identify_cpu(ver); - if (cpu) { - puts(cpu->name); + cpu = gd->cpu; + if (cpu->name) { + puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { @@ -104,7 +103,7 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:"); - for (i = 0; i < CONFIG_NUM_CPUS; i++) { + for (i = 0; i < cpu_numcores(); i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 76f02a4917f..2df55c71d49 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -157,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg) out_be32(&gur->devdisr, devdisr); /* release the hounds */ - up = ((1 << CONFIG_NUM_CPUS) - 1); + up = ((1 << cpu_numcores()) - 1); bpcr = in_be32(&ecm->eebpcr); bpcr |= (up << 24); out_be32(&ecm->eebpcr, bpcr); @@ -167,7 +167,7 @@ static void pq3_mp_up(unsigned long bootpg) /* wait for everyone */ while (timeout) { int i; - for (i = 0; i < CONFIG_NUM_CPUS; i++) { + for (i = 0; i < cpu_numcores(); i++) { if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) cpu_up_mask |= (1 << i); }; diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index fbefc2c31e1..2d4f219a3b7 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -1,3 +1,26 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Kumar Gala + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #include #include #include @@ -203,7 +226,7 @@ __secondary_start_page: .align L1_CACHE_SHIFT .globl __spin_table __spin_table: - .space CONFIG_NUM_CPUS*ENTRY_SIZE + .space CONFIG_MAX_CPUS*ENTRY_SIZE /* Fill in the empty space. The actual reset vector is * the last word of the page */ diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 286b6b28ef2..3ef49b456fb 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor Inc. + * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -51,7 +51,7 @@ void get_sys_info (sys_info_t * sysInfo) /* Divide before multiply to avoid integer * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; - for (i = 0; i < CONFIG_NUM_CPUS; i++) { + for (i = 0; i < cpu_numcores(); i++) { e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 32d06d20ebd..04409cec68f 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -30,6 +30,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Default board reset function */ @@ -61,12 +63,12 @@ checkcpu(void) puts("CPU: "); - cpu = identify_cpu(ver); - if (cpu) { + cpu = gd->cpu; + + if (cpu->name) puts(cpu->name); - } else { + else puts("Unknown"); - } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); puts("Core: "); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 341e815961c..5a78a9cdc74 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004,2009 Freescale Semiconductor, Inc. * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -129,7 +129,7 @@ void cpu_init_f(void) */ int cpu_init_r(void) { -#if (CONFIG_NUM_CPUS > 1) +#if defined(CONFIG_MP) setup_mp(); #endif return 0; diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index e34ef33ac26..17aed62b16f 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -35,41 +35,41 @@ DECLARE_GLOBAL_DATA_PTR; struct cpu_type cpu_type_list [] = { #if defined(CONFIG_MPC85xx) - CPU_TYPE_ENTRY(8533, 8533), - CPU_TYPE_ENTRY(8533, 8533_E), - CPU_TYPE_ENTRY(8535, 8535), - CPU_TYPE_ENTRY(8535, 8535_E), - CPU_TYPE_ENTRY(8536, 8536), - CPU_TYPE_ENTRY(8536, 8536_E), - CPU_TYPE_ENTRY(8540, 8540), - CPU_TYPE_ENTRY(8541, 8541), - CPU_TYPE_ENTRY(8541, 8541_E), - CPU_TYPE_ENTRY(8543, 8543), - CPU_TYPE_ENTRY(8543, 8543_E), - CPU_TYPE_ENTRY(8544, 8544), - CPU_TYPE_ENTRY(8544, 8544_E), - CPU_TYPE_ENTRY(8545, 8545), - CPU_TYPE_ENTRY(8545, 8545_E), - CPU_TYPE_ENTRY(8547, 8547_E), - CPU_TYPE_ENTRY(8548, 8548), - CPU_TYPE_ENTRY(8548, 8548_E), - CPU_TYPE_ENTRY(8555, 8555), - CPU_TYPE_ENTRY(8555, 8555_E), - CPU_TYPE_ENTRY(8560, 8560), - CPU_TYPE_ENTRY(8567, 8567), - CPU_TYPE_ENTRY(8567, 8567_E), - CPU_TYPE_ENTRY(8568, 8568), - CPU_TYPE_ENTRY(8568, 8568_E), - CPU_TYPE_ENTRY(8569, 8569), - CPU_TYPE_ENTRY(8569, 8569_E), - CPU_TYPE_ENTRY(8572, 8572), - CPU_TYPE_ENTRY(8572, 8572_E), - CPU_TYPE_ENTRY(P2020, P2020), - CPU_TYPE_ENTRY(P2020, P2020_E), + CPU_TYPE_ENTRY(8533, 8533, 1), + CPU_TYPE_ENTRY(8533, 8533_E, 1), + CPU_TYPE_ENTRY(8535, 8535, 1), + CPU_TYPE_ENTRY(8535, 8535_E, 1), + CPU_TYPE_ENTRY(8536, 8536, 1), + CPU_TYPE_ENTRY(8536, 8536_E, 1), + CPU_TYPE_ENTRY(8540, 8540, 1), + CPU_TYPE_ENTRY(8541, 8541, 1), + CPU_TYPE_ENTRY(8541, 8541_E, 1), + CPU_TYPE_ENTRY(8543, 8543, 1), + CPU_TYPE_ENTRY(8543, 8543_E, 1), + CPU_TYPE_ENTRY(8544, 8544, 1), + CPU_TYPE_ENTRY(8544, 8544_E, 1), + CPU_TYPE_ENTRY(8545, 8545, 1), + CPU_TYPE_ENTRY(8545, 8545_E, 1), + CPU_TYPE_ENTRY(8547, 8547_E, 1), + CPU_TYPE_ENTRY(8548, 8548, 1), + CPU_TYPE_ENTRY(8548, 8548_E, 1), + CPU_TYPE_ENTRY(8555, 8555, 1), + CPU_TYPE_ENTRY(8555, 8555_E, 1), + CPU_TYPE_ENTRY(8560, 8560, 1), + CPU_TYPE_ENTRY(8567, 8567, 1), + CPU_TYPE_ENTRY(8567, 8567_E, 1), + CPU_TYPE_ENTRY(8568, 8568, 1), + CPU_TYPE_ENTRY(8568, 8568_E, 1), + CPU_TYPE_ENTRY(8569, 8569, 1), + CPU_TYPE_ENTRY(8569, 8569_E, 1), + CPU_TYPE_ENTRY(8572, 8572, 2), + CPU_TYPE_ENTRY(8572, 8572_E, 2), + CPU_TYPE_ENTRY(P2020, P2020, 2), + CPU_TYPE_ENTRY(P2020, P2020_E, 2), #elif defined(CONFIG_MPC86xx) - CPU_TYPE_ENTRY(8610, 8610), - CPU_TYPE_ENTRY(8641, 8641), - CPU_TYPE_ENTRY(8641D, 8641D), + CPU_TYPE_ENTRY(8610, 8610, 1), + CPU_TYPE_ENTRY(8641, 8641, 2), + CPU_TYPE_ENTRY(8641D, 8641D, 2), #endif }; @@ -84,6 +84,31 @@ struct cpu_type *identify_cpu(u32 ver) return NULL; } +int cpu_numcores() { + struct cpu_type *cpu; + cpu = gd->cpu; + return cpu->num_cores; +} + +int probecpu (void) +{ + uint svr; + uint ver; + + svr = get_svr(); + ver = SVR_SOC_VER(svr); + + gd->cpu = identify_cpu(ver); + +#ifndef CONFIG_MP + if (cpu_numcores() > 1) { + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); + } +#endif + return 0; +} + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index c9ba805077e..fd7961c040c 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -38,4 +38,11 @@ #endif #endif +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) \ + || defined(CONFIG_MPC8641) +#define CONFIG_MAX_CPUS 2 +#else +#define CONFIG_MAX_CPUS 1 +#endif + #endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 244c161580e..a5747e10bde 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -91,6 +91,7 @@ typedef struct global_data { #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 lbc_clk; + void *cpu; #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ #if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 i2c1_clk; diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 28411045151..a079b2d4cb5 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1065,13 +1065,14 @@ n: struct cpu_type { char name[15]; u32 soc_ver; + u32 num_cores; }; struct cpu_type *identify_cpu(u32 ver); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) -#define CPU_TYPE_ENTRY(n, v) \ - { .name = #n, .soc_ver = SVR_##v, } +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } #else #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} diff --git a/include/common.h b/include/common.h index a6922fd7814..35f12c0b034 100644 --- a/include/common.h +++ b/include/common.h @@ -441,6 +441,8 @@ void ppcDWstore(unsigned int *addr, unsigned int *value); #endif /* $(CPU)/cpu.c */ +int cpu_numcores (void); +int probecpu (void); int checkcpu (void); int checkicache (void); int checkdcache (void); diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d0933bae9d9..55c1f29b192 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -34,7 +34,6 @@ #define CONFIG_MPC8572 1 #define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 44ff289f85e..761932800e4 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -17,7 +17,6 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ -#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bf2e359fd4a..b0ae25c2243 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -37,7 +37,6 @@ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ #define CONFIG_ADDR_MAP 1 /* Use addr map */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index ad24e0c884e..46af7b9b069 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -34,7 +34,6 @@ #define CONFIG_P2020 1 #define CONFIG_P2020DS 1 #define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 8be9fa05557..242466ae120 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -34,7 +34,6 @@ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ #define CONFIG_SYS_BOARD_NAME "XPedite5170" -#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ #define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index acb62ad1dd4..3c58ebe39b2 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -36,7 +36,6 @@ #define CONFIG_MPC8572 1 #define CONFIG_XPEDITE5370 1 #define CONFIG_SYS_BOARD_NAME "XPedite5370" -#define CONFIG_NUM_CPUS 2 /* 2 Cores */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ #define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index abc449d05fd..2865df55e98 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -41,7 +41,6 @@ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ #define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG diff --git a/include/e500.h b/include/e500.h index 84b580de1f4..f8c82661a2d 100644 --- a/include/e500.h +++ b/include/e500.h @@ -8,13 +8,9 @@ #ifndef __ASSEMBLY__ -#ifndef CONFIG_NUM_CPUS -#define CONFIG_NUM_CPUS 1 -#endif - typedef struct { - unsigned long freqProcessor[CONFIG_NUM_CPUS]; + unsigned long freqProcessor[CONFIG_MAX_CPUS]; unsigned long freqSystemBus; unsigned long freqDDRBus; unsigned long freqLocalBus; diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 6dd4d56ff32..9faf7f2a0b4 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -291,6 +291,9 @@ init_fnc_t *init_sequence[] = { board_early_init_f, #endif +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + probecpu, +#endif #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) get_clocks, /* get CPU and bus clocks (etc.) */ #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ diff --git a/lib_ppc/bootm.c b/lib_ppc/bootm.c index 83857490f35..0685a9331cb 100644 --- a/lib_ppc/bootm.c +++ b/lib_ppc/bootm.c @@ -172,7 +172,7 @@ void arch_lmb_reserve(struct lmb *lmb) static void boot_prep_linux(void) { -#if (CONFIG_NUM_CPUS > 1) +#ifdef CONFIG_MP /* if we are MP make sure to flush the dcache() to any changes are made * visibile to all other cores */ flush_dcache(); -- cgit v1.3.1 From 728ece343e8bb2a66ee977c49d455439e3b28da9 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 5 Aug 2009 13:29:24 +0530 Subject: 85xx: Add support for P2020RDB board The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 5 + board/freescale/p1_p2_rdb/Makefile | 52 ++++ board/freescale/p1_p2_rdb/config.mk | 29 ++ board/freescale/p1_p2_rdb/ddr.c | 243 +++++++++++++++ board/freescale/p1_p2_rdb/law.c | 37 +++ board/freescale/p1_p2_rdb/p1_p2_rdb.c | 222 ++++++++++++++ board/freescale/p1_p2_rdb/tlb.c | 83 +++++ board/freescale/p1_p2_rdb/u-boot.lds | 143 +++++++++ doc/README.p2020rdb | 145 +++++++++ include/asm-ppc/global_data.h | 2 +- include/configs/P1_P2_RDB.h | 556 ++++++++++++++++++++++++++++++++++ 13 files changed, 1521 insertions(+), 1 deletion(-) create mode 100644 board/freescale/p1_p2_rdb/Makefile create mode 100644 board/freescale/p1_p2_rdb/config.mk create mode 100644 board/freescale/p1_p2_rdb/ddr.c create mode 100644 board/freescale/p1_p2_rdb/law.c create mode 100644 board/freescale/p1_p2_rdb/p1_p2_rdb.c create mode 100644 board/freescale/p1_p2_rdb/tlb.c create mode 100644 board/freescale/p1_p2_rdb/u-boot.lds create mode 100644 doc/README.p2020rdb create mode 100644 include/configs/P1_P2_RDB.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 85ba8d28da7..f99eae596c1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17,6 +17,10 @@ # Board CPU # ######################################################################### +Poonam Aggrwal + + P2020RDB P2020 + Greg Allen UTX8245 MPC8245 diff --git a/MAKEALL b/MAKEALL index 65cd6d0f57a..6634f09f910 100755 --- a/MAKEALL +++ b/MAKEALL @@ -391,6 +391,7 @@ LIST_85xx=" \ MPC8572DS_36BIT \ P2020DS \ P2020DS_36BIT \ + P2020RDB \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index c24df6b0faa..b1095e8fea7 100644 --- a/Makefile +++ b/Makefile @@ -2528,6 +2528,11 @@ P2020DS_config: unconfig fi @$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale +P2020RDB_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_P2020" >>$(obj)include/config.h ; + @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile new file mode 100644 index 00000000000..910726315fd --- /dev/null +++ b/board/freescale/p1_p2_rdb/Makefile @@ -0,0 +1,52 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-y += ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk new file mode 100644 index 00000000000..abd64bbbec0 --- /dev/null +++ b/board/freescale/p1_p2_rdb/config.mk @@ -0,0 +1,29 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# p1_p2rdb board +# + +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c new file mode 100644 index 00000000000..9518392cddb --- /dev/null +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -0,0 +1,243 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); + +#define DATARATE_400MHZ 400000000 +#define DATARATE_533MHZ 533333333 +#define DATARATE_667MHZ 666666666 +#define DATARATE_800MHZ 800000000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_PD_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000000 +#define CONFIG_SYS_DDR_TIMING_5 0x00000000 + +#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322 +#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca +#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_400 0x00480432 +#define CONFIG_SYS_DDR_MODE_2_400 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100 + +#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432 +#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce +#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_533 0x00040642 +#define CONFIG_SYS_DDR_MODE_2_533 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100 + +#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 +#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 +#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_667 0x00040852 +#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00440862 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram (void) +{ + sys_info_t sysinfo; + char buf[32]; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + if(sysinfo.freqDDRBus <= DATARATE_400MHZ) + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0); + else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0); + else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0); + else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) + fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0); + else + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + dram_size = fixed_sdram(); + set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts("DDR: "); + return dram_size; +} diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c new file mode 100644 index 00000000000..12d2bf478bb --- /dev/null +++ b/board/freescale/p1_p2_rdb/law.c @@ -0,0 +1,37 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c new file mode 100644 index 00000000000..4c03468a245 --- /dev/null +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -0,0 +1,222 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define VSC7385_RST_SET 0x00080000 +#define SLIC_RST_SET 0x00040000 +#define SGMII_PHY_RST_SET 0x00020000 +#define PCIE_RST_SET 0x00010000 +#define RGMII_PHY_RST_SET 0x02000000 + +#define USB_RST_CLR 0x04000000 + +#define GPIO_DIR 0x060f0000 + +#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \ + SGMII_PHY_RST_SET | PCIE_RST_SET | \ + RGMII_PHY_RST_SET + +#define SYSCLK_MASK 0x00200000 +#define BOARDREV_MASK 0x10100000 +#define BOARDREV_B 0x10100000 +#define BOARDREV_C 0x00100000 + +#define SYSCLK_66 66666666 +#define SYSCLK_50 50000000 +#define SYSCLK_100 100000000 + +unsigned long get_board_sys_clk(ulong dummy) +{ + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 val_gpdat, sysclk_gpio, board_rev_gpio; + + val_gpdat = pgpio->gpdat; + sysclk_gpio = val_gpdat & SYSCLK_MASK; + board_rev_gpio = val_gpdat & BOARDREV_MASK; + if (board_rev_gpio == BOARDREV_C) { + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_100; + } else if (board_rev_gpio == BOARDREV_B) { + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_50; + } + return 0; +} + +#ifdef CONFIG_MMC +int board_early_init_f (void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); + return 0; +} +#endif + +int checkboard (void) +{ + u32 val_gpdat, board_rev_gpio; + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + char board_rev = 0; + struct cpu_type *cpu; + + val_gpdat = pgpio->gpdat; + board_rev_gpio = val_gpdat & BOARDREV_MASK; + if (board_rev_gpio == BOARDREV_C) + board_rev = 'C'; + else if (board_rev_gpio == BOARDREV_B) + board_rev = 'B'; + else + panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); + + cpu = gd->cpu; + printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); + setbits_be32(&pgpio->gpdir, GPIO_DIR); + +/* + * Bringing the following peripherals out of reset via GPIOs + * 0 = reset and 1 = out of reset + * GPIO12 - Reset to Ethernet Switch + * GPIO13 - Reset to SLIC/SLAC devices + * GPIO14 - Reset to SGMII_PHY_N + * GPIO15 - Reset to PCIe slots + * GPIO6 - Reset to RGMII PHY + * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset + */ + clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = 2; + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_16M, 1); + return 0; +} + + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[4]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + char *tmp; + unsigned int vscfw_addr; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } +#ifdef CONFIG_VSC7385_ENET +/* If a VSC7385 microcode image is present, then upload it. */ + if ((tmp = getenv ("vscfw_addr")) != NULL) { + vscfw_addr = simple_strtoul (tmp, NULL, 16); + printf("uploading VSC7385 microcode from %x\n", vscfw_addr); + if (vsc7385_upload_firmware((void *) vscfw_addr, + CONFIG_VSC7385_IMAGE_SIZE)) + puts("Failure uploading VSC7385 microcode.\n"); + } else + puts("No address specified for VSC7385 microcode.\n"); +#endif + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c new file mode 100644 index 00000000000..cf9bffed5f7 --- /dev/null +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -0,0 +1,83 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), + + /* *I*G - VSC7385 Switch */ + SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_1M, 1), + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb/u-boot.lds b/board/freescale/p1_p2_rdb/u-boot.lds new file mode 100644 index 00000000000..8470df7546a --- /dev/null +++ b/board/freescale/p1_p2_rdb/u-boot.lds @@ -0,0 +1,143 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/doc/README.p2020rdb b/doc/README.p2020rdb new file mode 100644 index 00000000000..8a2302fa99d --- /dev/null +++ b/doc/README.p2020rdb @@ -0,0 +1,145 @@ +Overview +-------- +P2020RDB is a Low End Dual core platform supporting the P2020 processor +of QorIQ series. P2020 is an e500 based dual core SOC. + +Building U-boot +----------- +To build the u-boot for P2020RDB: + make P2020RDB_config + make + +NOR Flash Banks +----------- +RDB board for P2020 has two flash banks. They are both present on boot. + +Booting by default is always from the boot bank at 0xef00_0000. + +Memory Map +---------- +0xef00_0000 - 0xef7f_ffff Alernate bank 8MB +0xe800_0000 - 0xefff_ffff Boot bank 8MB + +0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB +0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB + +Switch settings to boot from the NOR flash banks +------------------------------------------------ +SW4[8]=0 default NOR Flash bank +SW4[8]=1 Alternate NOR Flash bank + +Flashing Images +--------------- +To place a new u-boot image in the alternate flash bank and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot.bin + erase ef780000 ef7fffff + cp.b 1000000 ef780000 80000 + +Now to boot from the alternate bank change the SW4[8] from 0 to 1. + +To program the image in the boot flash bank: + tftp 1000000 u-boot.bin + protect off all + erase eff80000 ffffffff + cp.b 1000000 eff80000 80000 + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage.p2020rdb + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 p2020rdb.dtb + bootm 1000000 2000000 c00000 + +Implementing AMP(Asymmetric MultiProcessing) +--------------------------------------------- +1. Build kernel image for core0: + + a. $ make 85xx/p1_p2_rdb_defconfig + + b. $ make menuconfig + - un-select "Processor support"-> + "Symetric multi-processing support" + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 + +2. Build kernel image for core1: + + a. $ make 85xx/p1_p2_rdb_defconfig + + b. $ make menuconfig + - Un-select "Processor support"-> + "Symetric multi-processing support" + - Select "Advanced setup" -> + "Prompt for advanced kernel configuration options" + - Select + "Set physical address where the kernel is loaded" + and set it to 0x20000000, asssuming core1 will + start from 512MB. + - Select "Set custom page offset address" + - Select "Set custom kernel base address" + - Select "Set maximum low memory" + - "Exit" and save the selection. + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 + +3. Create dtb for core0: + + $ dtc -I dts -O dtb -f -b 0 + arch/powerpc/boot/dts/p2020rdb_camp_core0.dts > + /tftpboot/p2020rdb_camp_core0.dtb + +4. Create dtb for core1: + + $ dtc -I dts -O dtb -f -b 1 + arch/powerpc/boot/dts/p2020rdb_camp_core1.dts > + /tftpboot/p2020rdb_camp_core1.dtb + +5. Bring up two cores separately: + + a. Power on the board, under u-boot prompt: + => setenv + => setenv + => setenv bootargs root=/dev/ram rw console=ttyS0,115200 + b. Bring up core1's kernel first: + => setenv bootm_low 0x20000000 + => setenv bootm_size 0x10000000 + => tftp 21000000 uImage.core1 + => tftp 22000000 ramdiskfile + => tftp 20c00000 p2020rdb_camp_core1.dtb + => interrupts off + => bootm start 21000000 22000000 20c00000 + => bootm loados + => bootm ramdisk + => bootm fdt + => fdt boardsetup + => fdt chosen $initrd_start $initrd_end + => bootm prep + => cpu 1 release $bootm_low - $fdtaddr - + c. Bring up core0's kernel(on the same u-boot console): + => setenv bootm_low 0 + => setenv bootm_size 0x20000000 + => tftp 1000000 uImage.core0 + => tftp 2000000 ramdiskfile + => tftp c00000 p2020rdb_camp_core0.dtb + => bootm 1000000 2000000 c00000 + +Please note only core0 will run u-boot, core1 starts kernel directly +after "cpu release" command is issued. diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index a5747e10bde..db4b1eaa1e9 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -86,7 +86,7 @@ typedef struct global_data { u32 mem_sec_clk; #endif /* CONFIG_MPC8360 */ #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8536) +#if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h new file mode 100644 index 00000000000..ff4a5cb2d04 --- /dev/null +++ b/include/configs/P1_P2_RDB.h @@ -0,0 +1,556 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P1 P2 RDB board configuration file + * This file is intended to address a set of Low End and Ultra Low End + * Freescale SOCs of QorIQ series(RDB platforms). + * Currently only P2020RDB + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ +#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ + +#if defined(CONFIG_P2020) || defined(CONFIG_P1020) +#define CONFIG_MP +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ + /* CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ + /* CONFIG_SYS_IMMR */ +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) + +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_DLL + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00FF0000 + +#define CONFIG_SYS_DDR_TLB_START 9 + +/* + * Memory map + * + * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen + * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xff000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +/* NAND flash config */ +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2< " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 + +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_PCI) +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#undef CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define CONFIG_VSC7385_ENET + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET +/* The size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#endif + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#ifdef CONFIG_P2020 +#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ +#endif +#endif + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_HOSTNAME P2020RDB +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p2020rdb.dtb\0" \ + "bdev=sda1\0" \ + "jffs2nor=mtdblock3\0" \ + "norbootaddr=ef080000\0" \ + "norfdtaddr=ef040000\0" \ + "jffs2nand=mtdblock9\0" \ + "nandbootaddr=100000\0" \ + "nandfdtaddr=80000\0" \ + "nandimgsize=400000\0" \ + "nandfdtsize=80000\0" \ + "usb_phy_type=ulpi\0" \ + "vscfw_addr=ef000000\0" \ + "othbootargs=ramdisk_size=600000\0" \ + "usbfatboot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "fatload usb 0:2 $loadaddr $bootfile;" \ + "fatload usb 0:2 $fdtaddr $fdtfile;" \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ + "bootm $norbootaddr - $norfdtaddr\0" \ + "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "nand read 2000000 $nandbootaddr $nandimgsize;" \ + "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ + "bootm 2000000 - 3000000;\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 87c7661b42aa7672539b54b51d3d5c4013ec6f6c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 31 Jul 2009 12:08:27 +0530 Subject: 85xx: Added P1020 Processor Support. P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 3 ++- cpu/mpc8xxx/cpu.c | 2 ++ drivers/misc/fsl_law.c | 2 +- include/asm-ppc/processor.h | 2 ++ 4 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 88093029650..1477eace97d 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -48,8 +48,9 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o -COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o +COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 17aed62b16f..fbab9980eec 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -66,6 +66,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P1020, P1020, 2), + CPU_TYPE_ENTRY(P1020, P1020_E, 2), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index f7d454dce45..af7b7299349 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P2020) + defined(CONFIG_P2020) || defined(CONFIG_P1020) #define FSL_HW_NUM_LAWS 12 #else #error FSL_HW_NUM_LAWS not defined for this platform diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index a079b2d4cb5..5547245d5e7 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1011,6 +1011,8 @@ #define SVR_8572_E 0x80E800 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P1020 0x80E400 +#define SVR_P1020_E 0x80EC00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.3.1 From ef41f2a25c554604156b59f5945feadae2f3cb55 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 12 Aug 2009 00:10:44 -0500 Subject: 85xx: Removed BEDBUG support on P1_P2_RDB To match all other 85xx platforms we are removing BEDBUG support. Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index ff4a5cb2d04..95916417d2f 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -378,7 +378,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_SETEXPR #if defined(CONFIG_PCI) -#define CONFIG_CMD_BEDBUG #define CONFIG_CMD_NET #define CONFIG_CMD_PCI #endif -- cgit v1.3.1 From 158c6724c99368a4d8eef11ee7e3c7ad0ef03a15 Mon Sep 17 00:00:00 2001 From: Felix Radensky Date: Sat, 15 Aug 2009 15:08:37 +0300 Subject: 85xx: Fix memory test range on MPC8536DS With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END memory test hangs if run without arguments. Set them to sane values, so that all available 512MB of RAM excluding exception vectors at the bottom and u-boot code and stack at the top can be tested. Signed-off-by: Felix Radensky Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index f08f5ab6a17..4746e2ead56 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -86,8 +86,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ +#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* -- cgit v1.3.1 From 76b474e2f5a223fcabfeaa4f1c8fb699062b986c Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 18 Aug 2009 15:37:15 +0800 Subject: 85xx: Add L2SRAM Register's macro definition Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 5 +++-- include/asm-ppc/immap_85xx.h | 5 +++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 41de6942a62..c4d1a9dd9c7 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -330,11 +330,12 @@ int cpu_init_r(void) break; } - if (l2cache->l2ctl & 0x80000000) { + if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); l2srbar = l2cache->l2srbar0; #ifdef CONFIG_SYS_INIT_L2_ADDR - if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE) { + if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE + && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 0efef052143..375d80444f5 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -411,6 +411,11 @@ typedef struct ccsr_l2cache { char res15[420]; } ccsr_l2cache_t; +#define MPC85xx_L2CTL_L2E 0x80000000 +#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 +#define MPC85xx_L2ERRDIS_MBECC 0x00000008 +#define MPC85xx_L2ERRDIS_SBECC 0x00000004 + /* * DMA Registers(0x2_1000-0x2_2000) */ -- cgit v1.3.1 From 3b1f243b8dad30a646a0f056b0268519eadbc3c5 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 20 Aug 2009 18:55:35 +0530 Subject: 85xx: Added CONFIG_MAX_CPUS for P1020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index fd7961c040c..5670d06a441 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -38,8 +38,8 @@ #endif #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) \ - || defined(CONFIG_MPC8641) +#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ + defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 #else #define CONFIG_MAX_CPUS 1 -- cgit v1.3.1 From a713ba926b45da9a6f923f1ac9e60a66852e5f2d Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 20 Aug 2009 18:57:45 +0530 Subject: 85xx: Added single core members of FSL P1xx/P2xx processors series P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 4 +++- cpu/mpc8xxx/cpu.c | 8 ++++++-- drivers/misc/fsl_law.c | 3 ++- include/asm-ppc/processor.h | 8 ++++++-- 4 files changed, 17 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 1477eace97d..1bd8f3057ae 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -49,8 +49,10 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o -COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o +COBJS-$(CONFIG_P2010) += ddr-gen3.o +COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index fbab9980eec..339f6d97c2b 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -64,10 +64,14 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8572, 8572, 2), CPU_TYPE_ENTRY(8572, 8572_E, 2), - CPU_TYPE_ENTRY(P2020, P2020, 2), - CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P1011, P1011, 1), + CPU_TYPE_ENTRY(P1011, P1011_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), + CPU_TYPE_ENTRY(P2010, P2010, 1), + CPU_TYPE_ENTRY(P2010, P2010_E, 1), + CPU_TYPE_ENTRY(P2020, P2020, 2), + CPU_TYPE_ENTRY(P2020, P2020_E, 2), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index af7b7299349..147fe0a21c8 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -39,7 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P2020) || defined(CONFIG_P1020) + defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 #else #error FSL_HW_NUM_LAWS not defined for this platform diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 5547245d5e7..dcaf8c030a3 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1009,10 +1009,14 @@ #define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 #define SVR_8572_E 0x80E800 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 +#define SVR_P1011 0x80E500 +#define SVR_P1011_E 0x80ED00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 +#define SVR_P2010 0x80E300 +#define SVR_P2010_E 0x80EB00 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.3.1 From 0d3d68b25a8e7790f58530ddccbd61f9fc0245ef Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 21 Aug 2009 07:29:42 +0530 Subject: driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- drivers/pci/fsl_pci_init.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/fsl_pci.h | 26 ++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) (limited to 'include') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index ee89aaae5af..885542c1e9f 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -412,6 +412,50 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) } } +int fsl_pci_init_port(struct fsl_pci_info *pci_info, + struct pci_controller *hose, int busno) +{ + volatile ccsr_fsl_pci_t *pci; + struct pci_region *r; + + pci = (ccsr_fsl_pci_t *) pci_info->regs; + + /* on non-PCIe controllers we don't have pme_msg_det so this code + * should do nothing since the read will return 0 + */ + if (in_be32(&pci->pme_msg_det)) { + out_be32(&pci->pme_msg_det, 0xffffffff); + debug (" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + + r = hose->regions + hose->region_count; + + /* outbound memory */ + pci_set_region(r++, + pci_info->mem_bus, + pci_info->mem_phys, + pci_info->mem_size, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + pci_info->io_bus, + pci_info->io_phys, + pci_info->io_size, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + hose->first_busno = busno; + + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + + printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num, + hose->first_busno, hose->last_busno); + + return(hose->last_busno + 1); +} + /* Enable inbound PCI config cycles for agent/endpoint interface */ void fsl_pci_config_unlock(struct pci_controller *hose) { diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index b2ff0e929af..f625d19ee42 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -154,4 +154,30 @@ typedef struct ccsr_pci { char res24[252]; } ccsr_fsl_pci_t; +struct fsl_pci_info { + unsigned long regs; + pci_addr_t mem_bus; + phys_size_t mem_phys; + pci_size_t mem_size; + pci_addr_t io_bus; + phys_size_t io_phys; + pci_size_t io_size; + int pci_num; +}; + +int fsl_pci_init_port(struct fsl_pci_info *pci_info, + struct pci_controller *hose, int busno); + +#define SET_STD_PCIE_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.pci_num = num; \ +} + #endif -- cgit v1.3.1 From 33f3f34255bd7cf0be502275c59f0ff22dc50080 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 21 Aug 2009 07:29:58 +0530 Subject: 85xx: Added PCIe support for P1 P2 RDB Call fsl_pci_init_port() to initialize all the PCIe ports on the board. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/Makefile | 3 +- board/freescale/p1_p2_rdb/pci.c | 117 +++++++++++++++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 6 ++ 3 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 board/freescale/p1_p2_rdb/pci.c (limited to 'include') diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile index 910726315fd..ad1b7692913 100644 --- a/board/freescale/p1_p2_rdb/Makefile +++ b/board/freescale/p1_p2_rdb/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o +COBJS-y += ddr.o COBJS-y += law.o +COBJS-$(CONFIG_PCI) += pci.o COBJS-y += tlb.o -COBJS-y += ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c new file mode 100644 index 00000000000..174a8a7d78f --- /dev/null +++ b/board/freescale/p1_p2_rdb/pci.c @@ -0,0 +1,117 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +void pci_init_board(void) +{ + struct fsl_pci_info pci_info[2]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint devdisr = in_be32(&gur->devdisr); + uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; + int num = 0; + int first_free_busno = 0; + + int pcie_ep, pcie_configured; + + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf (" eTSEC2 is in sgmii mode.\n"); + +#ifdef CONFIG_PCIE2 + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = (host_agent == 2) || (host_agent == 4) || + (host_agent == 6) || (host_agent == 0); + pcie_configured = (io_sel == 0xE); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + puts ("\n PCIE2 connected to Slot 1 as "); + printf ("%s (base address %lx)", + pcie_ep ? "End Point": "Root Complex", pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num], + &pcie2_hose, first_free_busno); + num++; + } else { + printf (" PCIE2: disabled\n"); + } +#else + set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE1 + SET_STD_PCIE_INFO(pci_info[num], 1); + + pcie_ep = (host_agent <= 1) || (host_agent == 4) || + (host_agent == 5); + pcie_configured = (io_sel == 0xE); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + puts ("\n PCIE1 connected to Slot 2 as "); + printf ("%s (base address %lx)", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num], + &pcie1_hose, first_free_busno); + num++; + } else { + printf (" PCIE1: disabled\n"); + } +#else + set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#endif +} + +void ft_pci_board_setup(void *blob) +{ +/* According to h/w manual, PCIE2 is at lower address(0x9000) + * than PCIE1(0xa000). + * Hence PCIE2 is made to occupy the pci1 position in dts to + * keep the addresses sorted there. + * Generally the case with all FSL SOCs. + */ +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#endif +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#endif +} diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 95916417d2f..6d44d6c8ddb 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -35,6 +35,12 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -- cgit v1.3.1