From 3bc6257e8048bccec95b369fd3c946ac5d8ee9ea Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 21 Apr 2023 12:11:50 +0200 Subject: imx: support i.MX8QM DMSSE20 a1 board Add i.MX8QM DMSSE20 a1 board support U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200) Model: Advantech iMX8QM DMSSE20 Board: DMS-SE20A1 8GB Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363 Boot: USB DRAM: 8 GiB Core: 100 devices, 19 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000 Warning: ethernet@5b050000 (eth1) using random MAC address - 32:05:0c:f9:5e:10 , eth1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute --- include/configs/imx8qm_dmsse20.h | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/configs/imx8qm_dmsse20.h (limited to 'include') diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h new file mode 100644 index 00000000000..f9cda5eec7d --- /dev/null +++ b/include/configs/imx8qm_dmsse20.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2019 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ + +#ifndef __IMX8QM_DMSSE20_H +#define __IMX8QM_DMSSE20_H + +#include +#include + +/* Flat Device Tree Definitions */ + +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x5B040000 +/* FEC1 */ +#define IMX_FEC1_BASE 0x5B040000 +/* FEC2 */ +#define IMX_FEC2_BASE 0x5B050000 + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +/* Incorporate settings into the U-Boot environment */ +#define CFG_EXTRA_ENV_SETTINGS + +#define CFG_SYS_FSL_USDHC_NUM 2 + +#define CFG_SYS_SDRAM_BASE 0x080000000 +#define PHYS_SDRAM_1 0x080000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#endif /* __IMX8QM_DMSSE20_H */ -- cgit v1.3.1