From 895b54998e57a5d099c09915341dd9312e0ad7a7 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Thu, 17 Oct 2024 18:10:27 +0200 Subject: configs: khadas-vim3{l}: fix userdata size After increase boot and recovery partition userdata was not resize. so on VIM3 16GB and VIM3L `fastboot oem format` or `gpt write mmc 2 $partitions` fail because end of last partition is outside of eMMC size. Remove 64MB on userdata partitions to fix it. Fixes: ce138d9742bf ("configs: khadas-vim3{l}: Increase boot/recovery partition size") Signed-off-by: Guillaume La Roque Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20241017-adnroidv2-v1-3-781c939902c9@baylibre.com Signed-off-by: Neil Armstrong --- include/configs/khadas-vim3_android.h | 4 ++-- include/configs/khadas-vim3l_android.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h index fc89efb4c36..0e2953fe71b 100644 --- a/include/configs/khadas-vim3_android.h +++ b/include/configs/khadas-vim3_android.h @@ -24,7 +24,7 @@ "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #else #define PARTS_DEFAULT \ @@ -37,7 +37,7 @@ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #endif diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h index 5b2aed1cf62..f39a3782d66 100644 --- a/include/configs/khadas-vim3l_android.h +++ b/include/configs/khadas-vim3l_android.h @@ -24,7 +24,7 @@ "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #else #define PARTS_DEFAULT \ @@ -37,7 +37,7 @@ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -- cgit v1.3.1 From a5ed242ba6a8dbcf543b670fd8c11f1683b4baac Mon Sep 17 00:00:00 2001 From: Alexey Romanov Date: Tue, 12 Nov 2024 15:58:34 +0300 Subject: dt-bindings: remove a1 bindings from include/ We have exactly the same in upstream bindings. Signed-off-by: Alexey Romanov Link: https://lore.kernel.org/r/20241112125836.3239832-3-avromanov@salutedevices.com Signed-off-by: Neil Armstrong --- .../clock/amlogic,a1-peripherals-clkc.h | 168 --------------------- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 --- include/dt-bindings/gpio/meson-a1-gpio.h | 73 --------- include/dt-bindings/power/meson-a1-power.h | 32 ---- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 76 ---------- 5 files changed, 374 deletions(-) delete mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h delete mode 100644 include/dt-bindings/clock/amlogic,a1-pll-clkc.h delete mode 100644 include/dt-bindings/gpio/meson-a1-gpio.h delete mode 100644 include/dt-bindings/power/meson-a1-power.h delete mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h (limited to 'include') diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h deleted file mode 100644 index 06f198ee762..00000000000 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov - */ - -#ifndef __A1_PERIPHERALS_CLKC_H -#define __A1_PERIPHERALS_CLKC_H - -#define CLKID_XTAL_IN 0 -#define CLKID_FIXPLL_IN 1 -#define CLKID_USB_PHY_IN 2 -#define CLKID_USB_CTRL_IN 3 -#define CLKID_HIFIPLL_IN 4 -#define CLKID_SYSPLL_IN 5 -#define CLKID_DDS_IN 6 -#define CLKID_SYS 7 -#define CLKID_CLKTREE 8 -#define CLKID_RESET_CTRL 9 -#define CLKID_ANALOG_CTRL 10 -#define CLKID_PWR_CTRL 11 -#define CLKID_PAD_CTRL 12 -#define CLKID_SYS_CTRL 13 -#define CLKID_TEMP_SENSOR 14 -#define CLKID_AM2AXI_DIV 15 -#define CLKID_SPICC_B 16 -#define CLKID_SPICC_A 17 -#define CLKID_MSR 18 -#define CLKID_AUDIO 19 -#define CLKID_JTAG_CTRL 20 -#define CLKID_SARADC_EN 21 -#define CLKID_PWM_EF 22 -#define CLKID_PWM_CD 23 -#define CLKID_PWM_AB 24 -#define CLKID_CEC 25 -#define CLKID_I2C_S 26 -#define CLKID_IR_CTRL 27 -#define CLKID_I2C_M_D 28 -#define CLKID_I2C_M_C 29 -#define CLKID_I2C_M_B 30 -#define CLKID_I2C_M_A 31 -#define CLKID_ACODEC 32 -#define CLKID_OTP 33 -#define CLKID_SD_EMMC_A 34 -#define CLKID_USB_PHY 35 -#define CLKID_USB_CTRL 36 -#define CLKID_SYS_DSPB 37 -#define CLKID_SYS_DSPA 38 -#define CLKID_DMA 39 -#define CLKID_IRQ_CTRL 40 -#define CLKID_NIC 41 -#define CLKID_GIC 42 -#define CLKID_UART_C 43 -#define CLKID_UART_B 44 -#define CLKID_UART_A 45 -#define CLKID_SYS_PSRAM 46 -#define CLKID_RSA 47 -#define CLKID_CORESIGHT 48 -#define CLKID_AM2AXI_VAD 49 -#define CLKID_AUDIO_VAD 50 -#define CLKID_AXI_DMC 51 -#define CLKID_AXI_PSRAM 52 -#define CLKID_RAMB 53 -#define CLKID_RAMA 54 -#define CLKID_AXI_SPIFC 55 -#define CLKID_AXI_NIC 56 -#define CLKID_AXI_DMA 57 -#define CLKID_CPU_CTRL 58 -#define CLKID_ROM 59 -#define CLKID_PROC_I2C 60 -#define CLKID_DSPA_SEL 61 -#define CLKID_DSPB_SEL 62 -#define CLKID_DSPA_EN 63 -#define CLKID_DSPA_EN_NIC 64 -#define CLKID_DSPB_EN 65 -#define CLKID_DSPB_EN_NIC 66 -#define CLKID_RTC 67 -#define CLKID_CECA_32K 68 -#define CLKID_CECB_32K 69 -#define CLKID_24M 70 -#define CLKID_12M 71 -#define CLKID_FCLK_DIV2_DIVN 72 -#define CLKID_GEN 73 -#define CLKID_SARADC_SEL 74 -#define CLKID_SARADC 75 -#define CLKID_PWM_A 76 -#define CLKID_PWM_B 77 -#define CLKID_PWM_C 78 -#define CLKID_PWM_D 79 -#define CLKID_PWM_E 80 -#define CLKID_PWM_F 81 -#define CLKID_SPICC 82 -#define CLKID_TS 83 -#define CLKID_SPIFC 84 -#define CLKID_USB_BUS 85 -#define CLKID_SD_EMMC 86 -#define CLKID_PSRAM 87 -#define CLKID_DMC 88 -#define CLKID_SYS_A_SEL 89 -#define CLKID_SYS_A_DIV 90 -#define CLKID_SYS_A 91 -#define CLKID_SYS_B_SEL 92 -#define CLKID_SYS_B_DIV 93 -#define CLKID_SYS_B 94 -#define CLKID_DSPA_A_SEL 95 -#define CLKID_DSPA_A_DIV 96 -#define CLKID_DSPA_A 97 -#define CLKID_DSPA_B_SEL 98 -#define CLKID_DSPA_B_DIV 99 -#define CLKID_DSPA_B 100 -#define CLKID_DSPB_A_SEL 101 -#define CLKID_DSPB_A_DIV 102 -#define CLKID_DSPB_A 103 -#define CLKID_DSPB_B_SEL 104 -#define CLKID_DSPB_B_DIV 105 -#define CLKID_DSPB_B 106 -#define CLKID_RTC_32K_IN 107 -#define CLKID_RTC_32K_DIV 108 -#define CLKID_RTC_32K_XTAL 109 -#define CLKID_RTC_32K_SEL 110 -#define CLKID_CECB_32K_IN 111 -#define CLKID_CECB_32K_DIV 112 -#define CLKID_CECB_32K_SEL_PRE 113 -#define CLKID_CECB_32K_SEL 114 -#define CLKID_CECA_32K_IN 115 -#define CLKID_CECA_32K_DIV 116 -#define CLKID_CECA_32K_SEL_PRE 117 -#define CLKID_CECA_32K_SEL 118 -#define CLKID_DIV2_PRE 119 -#define CLKID_24M_DIV2 120 -#define CLKID_GEN_SEL 121 -#define CLKID_GEN_DIV 122 -#define CLKID_SARADC_DIV 123 -#define CLKID_PWM_A_SEL 124 -#define CLKID_PWM_A_DIV 125 -#define CLKID_PWM_B_SEL 126 -#define CLKID_PWM_B_DIV 127 -#define CLKID_PWM_C_SEL 128 -#define CLKID_PWM_C_DIV 129 -#define CLKID_PWM_D_SEL 130 -#define CLKID_PWM_D_DIV 131 -#define CLKID_PWM_E_SEL 132 -#define CLKID_PWM_E_DIV 133 -#define CLKID_PWM_F_SEL 134 -#define CLKID_PWM_F_DIV 135 -#define CLKID_SPICC_SEL 136 -#define CLKID_SPICC_DIV 137 -#define CLKID_SPICC_SEL2 138 -#define CLKID_TS_DIV 139 -#define CLKID_SPIFC_SEL 140 -#define CLKID_SPIFC_DIV 141 -#define CLKID_SPIFC_SEL2 142 -#define CLKID_USB_BUS_SEL 143 -#define CLKID_USB_BUS_DIV 144 -#define CLKID_SD_EMMC_SEL 145 -#define CLKID_SD_EMMC_DIV 146 -#define CLKID_SD_EMMC_SEL2 147 -#define CLKID_PSRAM_SEL 148 -#define CLKID_PSRAM_DIV 149 -#define CLKID_PSRAM_SEL2 150 -#define CLKID_DMC_SEL 151 -#define CLKID_DMC_DIV 152 -#define CLKID_DMC_SEL2 153 - -#endif /* __A1_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h deleted file mode 100644 index 2b660c0f2c9..00000000000 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov - */ - -#ifndef __A1_PLL_CLKC_H -#define __A1_PLL_CLKC_H - -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 -#define CLKID_FCLK_DIV2 6 -#define CLKID_FCLK_DIV3 7 -#define CLKID_FCLK_DIV5 8 -#define CLKID_FCLK_DIV7 9 -#define CLKID_HIFI_PLL 10 - -#endif /* __A1_PLL_CLKC_H */ diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h deleted file mode 100644 index 40e57a5ff1d..00000000000 --- a/include/dt-bindings/gpio/meson-a1-gpio.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Qianggui Song - */ - -#ifndef _DT_BINDINGS_MESON_A1_GPIO_H -#define _DT_BINDINGS_MESON_A1_GPIO_H - -#define GPIOP_0 0 -#define GPIOP_1 1 -#define GPIOP_2 2 -#define GPIOP_3 3 -#define GPIOP_4 4 -#define GPIOP_5 5 -#define GPIOP_6 6 -#define GPIOP_7 7 -#define GPIOP_8 8 -#define GPIOP_9 9 -#define GPIOP_10 10 -#define GPIOP_11 11 -#define GPIOP_12 12 -#define GPIOB_0 13 -#define GPIOB_1 14 -#define GPIOB_2 15 -#define GPIOB_3 16 -#define GPIOB_4 17 -#define GPIOB_5 18 -#define GPIOB_6 19 -#define GPIOX_0 20 -#define GPIOX_1 21 -#define GPIOX_2 22 -#define GPIOX_3 23 -#define GPIOX_4 24 -#define GPIOX_5 25 -#define GPIOX_6 26 -#define GPIOX_7 27 -#define GPIOX_8 28 -#define GPIOX_9 29 -#define GPIOX_10 30 -#define GPIOX_11 31 -#define GPIOX_12 32 -#define GPIOX_13 33 -#define GPIOX_14 34 -#define GPIOX_15 35 -#define GPIOX_16 36 -#define GPIOF_0 37 -#define GPIOF_1 38 -#define GPIOF_2 39 -#define GPIOF_3 40 -#define GPIOF_4 41 -#define GPIOF_5 42 -#define GPIOF_6 43 -#define GPIOF_7 44 -#define GPIOF_8 45 -#define GPIOF_9 46 -#define GPIOF_10 47 -#define GPIOF_11 48 -#define GPIOF_12 49 -#define GPIOA_0 50 -#define GPIOA_1 51 -#define GPIOA_2 52 -#define GPIOA_3 53 -#define GPIOA_4 54 -#define GPIOA_5 55 -#define GPIOA_6 56 -#define GPIOA_7 57 -#define GPIOA_8 58 -#define GPIOA_9 59 -#define GPIOA_10 60 -#define GPIOA_11 61 - -#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h deleted file mode 100644 index 8e39dfc0b62..00000000000 --- a/include/dt-bindings/power/meson-a1-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2023 SberDevices, Inc. - * Author: Alexey Romanov - */ - -#ifndef _DT_BINDINGS_MESON_A1_POWER_H -#define _DT_BINDINGS_MESON_A1_POWER_H - -#define PWRC_DSPA_ID 8 -#define PWRC_DSPB_ID 9 -#define PWRC_UART_ID 10 -#define PWRC_DMC_ID 11 -#define PWRC_I2C_ID 12 -#define PWRC_PSRAM_ID 13 -#define PWRC_ACODEC_ID 14 -#define PWRC_AUDIO_ID 15 -#define PWRC_OTP_ID 16 -#define PWRC_DMA_ID 17 -#define PWRC_SD_EMMC_ID 18 -#define PWRC_RAMA_ID 19 -#define PWRC_RAMB_ID 20 -#define PWRC_IR_ID 21 -#define PWRC_SPICC_ID 22 -#define PWRC_SPIFC_ID 23 -#define PWRC_USB_ID 24 -#define PWRC_NIC_ID 25 -#define PWRC_PDMIN_ID 26 -#define PWRC_RSA_ID 27 -#define PWRC_MAX_ID 28 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index 2c749c655e1..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen - * - * Copyright (c) 2023, SberDevices, Inc. - * Author: Alexey Romanov - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif -- cgit v1.3.1 From 827edb6c00be861bfb84391dcd0586b1402f354f Mon Sep 17 00:00:00 2001 From: Alexey Romanov Date: Tue, 12 Nov 2024 15:58:35 +0300 Subject: dt-bindings: remove axg bindings from include/ We have exactly the same in upstream bindings. Signed-off-by: Alexey Romanov Link: https://lore.kernel.org/r/20241112125836.3239832-4-avromanov@salutedevices.com Signed-off-by: Neil Armstrong --- include/dt-bindings/clock/axg-audio-clkc.h | 94 --------------------------- include/dt-bindings/clock/axg-clkc.h | 100 ----------------------------- 2 files changed, 194 deletions(-) delete mode 100644 include/dt-bindings/clock/axg-audio-clkc.h delete mode 100644 include/dt-bindings/clock/axg-clkc.h (limited to 'include') diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h deleted file mode 100644 index f561f5c5ef8..00000000000 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet - */ - -#ifndef __AXG_AUDIO_CLKC_BINDINGS_H -#define __AXG_AUDIO_CLKC_BINDINGS_H - -#define AUD_CLKID_DDR_ARB 29 -#define AUD_CLKID_PDM 30 -#define AUD_CLKID_TDMIN_A 31 -#define AUD_CLKID_TDMIN_B 32 -#define AUD_CLKID_TDMIN_C 33 -#define AUD_CLKID_TDMIN_LB 34 -#define AUD_CLKID_TDMOUT_A 35 -#define AUD_CLKID_TDMOUT_B 36 -#define AUD_CLKID_TDMOUT_C 37 -#define AUD_CLKID_FRDDR_A 38 -#define AUD_CLKID_FRDDR_B 39 -#define AUD_CLKID_FRDDR_C 40 -#define AUD_CLKID_TODDR_A 41 -#define AUD_CLKID_TODDR_B 42 -#define AUD_CLKID_TODDR_C 43 -#define AUD_CLKID_LOOPBACK 44 -#define AUD_CLKID_SPDIFIN 45 -#define AUD_CLKID_SPDIFOUT 46 -#define AUD_CLKID_RESAMPLE 47 -#define AUD_CLKID_POWER_DETECT 48 -#define AUD_CLKID_MST_A_MCLK 49 -#define AUD_CLKID_MST_B_MCLK 50 -#define AUD_CLKID_MST_C_MCLK 51 -#define AUD_CLKID_MST_D_MCLK 52 -#define AUD_CLKID_MST_E_MCLK 53 -#define AUD_CLKID_MST_F_MCLK 54 -#define AUD_CLKID_SPDIFOUT_CLK 55 -#define AUD_CLKID_SPDIFIN_CLK 56 -#define AUD_CLKID_PDM_DCLK 57 -#define AUD_CLKID_PDM_SYSCLK 58 -#define AUD_CLKID_MST_A_SCLK 79 -#define AUD_CLKID_MST_B_SCLK 80 -#define AUD_CLKID_MST_C_SCLK 81 -#define AUD_CLKID_MST_D_SCLK 82 -#define AUD_CLKID_MST_E_SCLK 83 -#define AUD_CLKID_MST_F_SCLK 84 -#define AUD_CLKID_MST_A_LRCLK 86 -#define AUD_CLKID_MST_B_LRCLK 87 -#define AUD_CLKID_MST_C_LRCLK 88 -#define AUD_CLKID_MST_D_LRCLK 89 -#define AUD_CLKID_MST_E_LRCLK 90 -#define AUD_CLKID_MST_F_LRCLK 91 -#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 -#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 -#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 -#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 -#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 -#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 -#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 -#define AUD_CLKID_TDMIN_A_SCLK 123 -#define AUD_CLKID_TDMIN_B_SCLK 124 -#define AUD_CLKID_TDMIN_C_SCLK 125 -#define AUD_CLKID_TDMIN_LB_SCLK 126 -#define AUD_CLKID_TDMOUT_A_SCLK 127 -#define AUD_CLKID_TDMOUT_B_SCLK 128 -#define AUD_CLKID_TDMOUT_C_SCLK 129 -#define AUD_CLKID_TDMIN_A_LRCLK 130 -#define AUD_CLKID_TDMIN_B_LRCLK 131 -#define AUD_CLKID_TDMIN_C_LRCLK 132 -#define AUD_CLKID_TDMIN_LB_LRCLK 133 -#define AUD_CLKID_TDMOUT_A_LRCLK 134 -#define AUD_CLKID_TDMOUT_B_LRCLK 135 -#define AUD_CLKID_TDMOUT_C_LRCLK 136 -#define AUD_CLKID_SPDIFOUT_B 151 -#define AUD_CLKID_SPDIFOUT_B_CLK 152 -#define AUD_CLKID_TDM_MCLK_PAD0 155 -#define AUD_CLKID_TDM_MCLK_PAD1 156 -#define AUD_CLKID_TDM_LRCLK_PAD0 157 -#define AUD_CLKID_TDM_LRCLK_PAD1 158 -#define AUD_CLKID_TDM_LRCLK_PAD2 159 -#define AUD_CLKID_TDM_SCLK_PAD0 160 -#define AUD_CLKID_TDM_SCLK_PAD1 161 -#define AUD_CLKID_TDM_SCLK_PAD2 162 -#define AUD_CLKID_TOP 163 -#define AUD_CLKID_TORAM 164 -#define AUD_CLKID_EQDRC 165 -#define AUD_CLKID_RESAMPLE_B 166 -#define AUD_CLKID_TOVAD 167 -#define AUD_CLKID_LOCKER 168 -#define AUD_CLKID_SPDIFIN_LB 169 -#define AUD_CLKID_FRDDR_D 170 -#define AUD_CLKID_TODDR_D 171 -#define AUD_CLKID_LOOPBACK_B 172 - -#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h deleted file mode 100644 index 93752ea107e..00000000000 --- a/include/dt-bindings/clock/axg-clkc.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Meson-AXG clock tree IDs - * - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#ifndef __AXG_CLKC_H -#define __AXG_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_AUDIO_LOCKER 16 -#define CLKID_MIPI_DSI_HOST 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC0 21 -#define CLKID_I2C 22 -#define CLKID_RNG0 23 -#define CLKID_UART0 24 -#define CLKID_MIPI_DSI_PHY 25 -#define CLKID_SPICC1 26 -#define CLKID_PCIE_A 27 -#define CLKID_PCIE_B 28 -#define CLKID_HIU_IFACE 29 -#define CLKID_ASSIST_MISC 30 -#define CLKID_SD_EMMC_B 31 -#define CLKID_SD_EMMC_C 32 -#define CLKID_DMA 33 -#define CLKID_SPI 34 -#define CLKID_AUDIO 35 -#define CLKID_ETH 36 -#define CLKID_UART1 37 -#define CLKID_G2D 38 -#define CLKID_USB0 39 -#define CLKID_USB1 40 -#define CLKID_RESET 41 -#define CLKID_USB 42 -#define CLKID_AHB_ARB0 43 -#define CLKID_EFUSE 44 -#define CLKID_BOOT_ROM 45 -#define CLKID_AHB_DATA_BUS 46 -#define CLKID_AHB_CTRL_BUS 47 -#define CLKID_USB1_DDR_BRIDGE 48 -#define CLKID_USB0_DDR_BRIDGE 49 -#define CLKID_MMC_PCLK 50 -#define CLKID_VPU_INTR 51 -#define CLKID_SEC_AHB_AHB3_BRIDGE 52 -#define CLKID_GIC 53 -#define CLKID_AO_MEDIA_CPU 54 -#define CLKID_AO_AHB_SRAM 55 -#define CLKID_AO_AHB_BUS 56 -#define CLKID_AO_IFACE 57 -#define CLKID_AO_I2C 58 -#define CLKID_SD_EMMC_B_CLK0 59 -#define CLKID_SD_EMMC_C_CLK0 60 -#define CLKID_HIFI_PLL 69 -#define CLKID_PCIE_CML_EN0 79 -#define CLKID_PCIE_CML_EN1 80 -#define CLKID_GEN_CLK 84 -#define CLKID_VPU_0_SEL 92 -#define CLKID_VPU_0 93 -#define CLKID_VPU_1_SEL 95 -#define CLKID_VPU_1 96 -#define CLKID_VPU 97 -#define CLKID_VAPB_0_SEL 99 -#define CLKID_VAPB_0 100 -#define CLKID_VAPB_1_SEL 102 -#define CLKID_VAPB_1 103 -#define CLKID_VAPB_SEL 104 -#define CLKID_VAPB 105 -#define CLKID_VCLK 106 -#define CLKID_VCLK2 107 -#define CLKID_VCLK_DIV1 122 -#define CLKID_VCLK_DIV2 123 -#define CLKID_VCLK_DIV4 124 -#define CLKID_VCLK_DIV6 125 -#define CLKID_VCLK_DIV12 126 -#define CLKID_VCLK2_DIV1 127 -#define CLKID_VCLK2_DIV2 128 -#define CLKID_VCLK2_DIV4 129 -#define CLKID_VCLK2_DIV6 130 -#define CLKID_VCLK2_DIV12 131 -#define CLKID_CTS_ENCL 133 -#define CLKID_VDIN_MEAS 136 - -#endif /* __AXG_CLKC_H */ -- cgit v1.3.1 From 1cdb4e03e684d94456dee0cc30c935d7e25b263d Mon Sep 17 00:00:00 2001 From: Alexey Romanov Date: Tue, 12 Nov 2024 15:58:36 +0300 Subject: dt-bindings: interrupt-controller: remove arm-gic.h from include/ We have exactly the same in upstream bindings. Signed-off-by: Alexey Romanov Link: https://lore.kernel.org/r/20241112125836.3239832-5-avromanov@salutedevices.com Signed-off-by: Neil Armstrong --- include/dt-bindings/interrupt-controller/arm-gic.h | 23 ---------------------- 1 file changed, 23 deletions(-) delete mode 100644 include/dt-bindings/interrupt-controller/arm-gic.h (limited to 'include') diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h deleted file mode 100644 index 35b6f69b7db..00000000000 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * This header provides constants for the ARM GIC. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H - -#include - -/* interrupt specifier cell 0 */ - -#define GIC_SPI 0 -#define GIC_PPI 1 - -/* - * Interrupt specifier cell 2. - * The flags in irq.h are valid, plus those below. - */ -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -#endif -- cgit v1.3.1 From 408af976742e6ffedf48fa42792955a633e357ed Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Mon, 11 Nov 2024 18:08:56 -0300 Subject: net: wget: add definition of struct wget_http_info The struct wget_http_info exposes the HTTP information of the last HTTP request issued by wget, and it controls whether the efi bootdevice is set, and whether the buffer size needs to be checked (lwip stack only). This information is otherwise discarded. The wget_http_info struct can be used by HTTP drivers to have more control over HTTP requests. Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt --- include/net-common.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index fd7c5e7b488..8985b81c2d2 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -506,4 +507,51 @@ int wget_with_dns(ulong dst_addr, char *uri); bool wget_validate_uri(char *uri); //int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); +/** + * enum wget_http_method - http method + */ +enum wget_http_method { + WGET_HTTP_METHOD_GET, + WGET_HTTP_METHOD_POST, + WGET_HTTP_METHOD_PATCH, + WGET_HTTP_METHOD_OPTIONS, + WGET_HTTP_METHOD_CONNECT, + WGET_HTTP_METHOD_HEAD, + WGET_HTTP_METHOD_PUT, + WGET_HTTP_METHOD_DELETE, + WGET_HTTP_METHOD_TRACE, + WGET_HTTP_METHOD_MAX +}; + +/** + * define MAX_HTTP_HEADERS_SIZE - maximum headers buffer size + * + * When receiving http headers, wget fills a buffer with up + * to MAX_HTTP_HEADERS_SIZE bytes of header information. + */ +#define MAX_HTTP_HEADERS_SIZE SZ_64K + +/** + * struct wget_http_info - wget parameters + * @method: HTTP Method. Filled by client. + * @status_code: HTTP status code. Filled by wget. + * @file_size: download size. Filled by wget. + * @buffer_size: size of client-provided buffer. Filled by client. + * @set_bootdev: set boot device with download. Filled by client. + * @check_buffer_size: check download does not exceed buffer size. + * Filled by client. + * @hdr_cont_len: content length according to headers. Filled by wget + * @headers: buffer for headers. Filled by wget. + */ +struct wget_http_info { + enum wget_http_method method; + u32 status_code; + ulong file_size; + ulong buffer_size; + bool set_bootdev; + bool check_buffer_size; + u32 hdr_cont_len; + char *headers; +}; + #endif /* __NET_COMMON_H__ */ -- cgit v1.3.1 From 1de93fda99f800aa1919268035fa2dd0e5109610 Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Mon, 11 Nov 2024 18:08:57 -0300 Subject: net: wget: Add interface to issue wget_requests using wget_http_info Declare and define a global default struct wget_http_info and an interface to issue wget requests providing a custom struct wget_http_info. This code is common to legacy wget and lwip wget. The idea is that the command wget should use the default wget_http_info and other internal u-boot code can call wget_request with their own wget_http_info struct. Signed-off-by: Adriano Cordova --- include/net-common.h | 4 ++++ net/net-common.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index 8985b81c2d2..1efb0db9ff5 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -554,4 +554,8 @@ struct wget_http_info { char *headers; }; +extern struct wget_http_info default_wget_info; +extern struct wget_http_info *wget_info; +int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info); + #endif /* __NET_COMMON_H__ */ diff --git a/net/net-common.c b/net/net-common.c index a7f767d5e9c..45288fe5f80 100644 --- a/net/net-common.c +++ b/net/net-common.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include void copy_filename(char *dst, const char *src, int size) { @@ -11,3 +12,16 @@ void copy_filename(char *dst, const char *src, int size) *dst++ = *src++; *dst = '\0'; } + +struct wget_http_info default_wget_info = { + .method = WGET_HTTP_METHOD_GET, + .set_bootdev = true, +}; + +struct wget_http_info *wget_info; + +int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info) +{ + wget_info = info ? info : &default_wget_info; + return wget_with_dns(dst_addr, uri); +} -- cgit v1.3.1 From de28a2a5f2ad93b156b39c2aee24cb5d01c7e619 Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Mon, 11 Nov 2024 18:08:59 -0300 Subject: net: wget: make wget_with_dns return value compatible with its lwip version There are two wget_with_dns functions, one in the legacy network stack and one in lwip, but the return values are not compatible. This commit modifies the legacy version of wget_with_dns so that the return values are compatible: 0 on success, otherwise a negative error. This way wget_with_dns can be called in a network stack agnostic way. Signed-off-by: Adriano Cordova --- include/net-common.h | 2 +- include/net-lwip.h | 9 --------- net/wget.c | 2 +- 3 files changed, 2 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index 1efb0db9ff5..3cd0f343744 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -495,7 +495,7 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); * * @dst_addr: destination address to download the file * @uri: uri string of target file of wget - * Return: downloaded file size, negative if failed + * Return: zero on success, negative if failed */ int wget_with_dns(ulong dst_addr, char *uri); /** diff --git a/include/net-lwip.h b/include/net-lwip.h index 1c3583f82a1..4d7f9387d1d 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -16,15 +16,6 @@ void net_lwip_remove_netif(struct netif *netif); struct netif *net_lwip_get_netif(void); int net_lwip_rx(struct udevice *udev, struct netif *netif); -/** - * wget_with_dns() - runs dns host IP address resulution before wget - * - * @dst_addr: destination address to download the file - * @uri: uri string of target file of wget - * Return: downloaded file size, negative if failed - */ - -int wget_with_dns(ulong dst_addr, char *uri); /** * wget_validate_uri() - varidate the uri * diff --git a/net/wget.c b/net/wget.c index 21f18758664..3bc2522cde5 100644 --- a/net/wget.c +++ b/net/wget.c @@ -579,7 +579,7 @@ int wget_with_dns(ulong dst_addr, char *uri) out: free(str_copy); - return ret; + return ret < 0 ? ret : 0; } #endif -- cgit v1.3.1 From e2032a0e4e55ea0958aae32f783f3a0726e34415 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 26 Oct 2024 08:09:00 -0600 Subject: global: Remove bi_sramstart/bi_sramsize These fields are currently set on exactly two platforms today, and used by only one of them. Update pic32mzdask to use CFG_SYS_SRAM* in the one location it needs it and otherwise drop this field from the bd_info struct. Signed-off-by: Tom Rini --- Kconfig | 21 --------------------- api/api_platform-powerpc.c | 1 - cmd/bdinfo.c | 4 ---- common/board_f.c | 7 ------- include/asm-generic/u-boot.h | 2 -- include/configs/pic32mzdask.h | 5 ++++- 6 files changed, 4 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index eb55f2511d9..bd63fea2e9a 100644 --- a/Kconfig +++ b/Kconfig @@ -595,27 +595,6 @@ config SYS_MEM_TOP_HIDE WARNING: Please make sure that this value is a multiple of the OS page size. -config SYS_HAS_SRAM - bool - default y if TARGET_PIC32MZDASK - default y if TARGET_DEVKIT8000 - help - Enable this to allow support for the on board SRAM. - SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. - SRAM size is controlled by CONFIG_SYS_SRAM_SIZE. - -config SYS_SRAM_BASE - hex - default 0x80000000 if TARGET_PIC32MZDASK - default 0x40200000 if TARGET_DEVKIT8000 - default 0x0 - -config SYS_SRAM_SIZE - hex - default 0x00080000 if TARGET_PIC32MZDASK - default 0x10000 if TARGET_DEVKIT8000 - default 0x0 - config SYS_MONITOR_LEN int "Maximum size in bytes reserved for U-Boot in memory" default 1048576 if X86 diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 3a04a9f691c..2c1ab043af6 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -43,7 +43,6 @@ int platform_sys_info(struct sys_info *si) platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); - platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM); return 1; } diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 4c0e2adabc3..ae9e1923eac 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -140,10 +140,6 @@ static int bdinfo_print_all(struct bd_info *bd) #endif bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params); print_bi_dram(bd); - if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) { - bdinfo_print_num_l("sramstart", (ulong)bd->bi_sramstart); - bdinfo_print_num_l("sramsize", (ulong)bd->bi_sramsize); - } bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart); bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize); bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset); diff --git a/common/board_f.c b/common/board_f.c index 98dc2591e1d..ebc934ab810 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -637,13 +637,6 @@ __weak int arch_setup_bdinfo(void) int setup_bdinfo(void) { - struct bd_info *bd = gd->bd; - - if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) { - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ - } - return arch_setup_bdinfo(); } diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 70303acd558..8c619c1b74a 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -30,8 +30,6 @@ struct bd_info { unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ #ifdef CONFIG_ARM unsigned long bi_arm_freq; /* arm frequency */ unsigned long bi_dsp_freq; /* dsp core frequency */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 0ae4fc55a97..8de930eab54 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -19,8 +19,11 @@ */ /* Initial RAM for temporary stack, global data */ #define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_SRAM_BASE 0x80000000 +#define CFG_SYS_SRAM_SIZE 0x00080000 + #define CFG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) + (CFG_SYS_SRAM_BASE + CFG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CFG_SYS_SDRAM_BASE 0x88000000 -- cgit v1.3.1 From 3fcbae5f849b2a5c36ad5ca0d90dd94191760053 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 31 Oct 2024 18:50:23 +0100 Subject: dm: sysinfo: Shorten the SYSINFO_ID prefix We are about to add a large number of new entries. Update the prefix to be a little shorter. For SMBIOS items, use SYSID_SM_ (for System Management) which is enough to distinguish it. For now at least, it seems that most items will be for SMBIOS. Signed-off-by: Simon Glass Acked-by: Raymond Mao --- board/coreboot/coreboot/sysinfo.c | 8 ++++---- board/google/chromebook_coral/coral.c | 6 +++--- board/toradex/common/tdx-common.c | 2 +- common/board_info.c | 8 ++++---- drivers/sysinfo/gazerbeam.h | 4 ++-- drivers/sysinfo/gpio.c | 4 ++-- drivers/sysinfo/rcar3.c | 2 +- drivers/sysinfo/sandbox.h | 2 +- include/sysinfo.h | 34 +++++++++++++++++----------------- lib/smbios.c | 24 ++++++++++++------------ test/dm/sysinfo-gpio.c | 12 ++++++------ 11 files changed, 53 insertions(+), 53 deletions(-) (limited to 'include') diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c index e0bdc7a5a88..d6b19530023 100644 --- a/board/coreboot/coreboot/sysinfo.c +++ b/board/coreboot/coreboot/sysinfo.c @@ -24,21 +24,21 @@ static int cb_get_str(struct udevice *dev, int id, size_t size, char *val) const char *str = NULL; switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: if (priv->t1) str = smbios_string(priv->system, priv->t1->product_name); break; - case SYSINFO_ID_BOARD_MANUFACTURER: + case SYSID_BOARD_MANUFACTURER: if (priv->t1) str = smbios_string(priv->system, priv->t1->manufacturer); break; - case SYSINFO_ID_PRIOR_STAGE_VERSION: + case SYSID_PRIOR_STAGE_VERSION: if (priv->t0) str = smbios_string(priv->bios, priv->t0->bios_ver); break; - case SYSINFO_ID_PRIOR_STAGE_DATE: + case SYSID_PRIOR_STAGE_DATE: if (priv->t0) str = smbios_string(priv->bios, priv->t0->bios_release_date); diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 3443dc91885..db96534857c 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -151,8 +151,8 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) return -ENOSYS; switch (id) { - case SYSINFO_ID_SMBIOS_SYSTEM_VERSION: - case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: { + case SYSID_SM_SYSTEM_VERSION: + case SYSID_SM_BASEBOARD_VERSION: { ret = get_skuconfig(dev); if (ret < 0) @@ -162,7 +162,7 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) sprintf(val, "rev%d", ret); break; } - case SYSINFO_ID_BOARD_MODEL: { + case SYSID_BOARD_MODEL: { int mem_config, sku_config; const char *model; diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index a6b45cdab81..3badeebd149 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -193,7 +193,7 @@ static int tdx_get_str(struct udevice *dev, int id, size_t size, char *val) int ret = -ENOTSUPP; switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: snprintf(val, size, "Toradex %04d %s %s", tdx_hw_tag.prodid, diff --git a/common/board_info.c b/common/board_info.c index 33c260b404e..dc26e1a33dd 100644 --- a/common/board_info.c +++ b/common/board_info.c @@ -18,9 +18,9 @@ static const struct to_show { const char *name; enum sysinfo_id id; } to_show[] = { - { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER}, - { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION }, - { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE }, + { "Manufacturer", SYSID_BOARD_MANUFACTURER}, + { "Prior-stage version", SYSID_PRIOR_STAGE_VERSION }, + { "Prior-stage date", SYSID_PRIOR_STAGE_DATE }, { /* sentinel */ } }; @@ -39,7 +39,7 @@ static int try_sysinfo(void) if (ret) return ret; - ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str); + ret = sysinfo_get_str(dev, SYSID_BOARD_MODEL, sizeof(str), str); if (ret) return ret; printf("Model: %s\n", str); diff --git a/drivers/sysinfo/gazerbeam.h b/drivers/sysinfo/gazerbeam.h index 6bf3c0098d1..047f365436f 100644 --- a/drivers/sysinfo/gazerbeam.h +++ b/drivers/sysinfo/gazerbeam.h @@ -8,8 +8,8 @@ #include enum { - BOARD_HWVERSION = SYSINFO_ID_BOARD_MODEL, - BOARD_MULTICHANNEL = SYSINFO_ID_USER, + BOARD_HWVERSION = SYSID_BOARD_MODEL, + BOARD_MULTICHANNEL = SYSID_USER, BOARD_VARIANT }; diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c index aaca318419b..66d2a913087 100644 --- a/drivers/sysinfo/gpio.c +++ b/drivers/sysinfo/gpio.c @@ -38,7 +38,7 @@ static int sysinfo_gpio_get_int(struct udevice *dev, int id, int *val) struct sysinfo_gpio_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: *val = priv->revision; return 0; default: @@ -51,7 +51,7 @@ static int sysinfo_gpio_get_str(struct udevice *dev, int id, size_t size, char * struct sysinfo_gpio_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: { + case SYSID_BOARD_MODEL: { const char *name = NULL; int i, ret; u32 revision; diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index 37e2cccd9af..2994df9ab1c 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -46,7 +46,7 @@ static int sysinfo_rcar_get_str(struct udevice *dev, int id, size_t size, char * struct sysinfo_rcar_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: strncpy(val, priv->boardmodel, size); val[size - 1] = '\0'; return 0; diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index d9c5804c26a..a7cbac0ce18 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -5,7 +5,7 @@ */ enum { - BOOL_CALLED_DETECT = SYSINFO_ID_USER, + BOOL_CALLED_DETECT = SYSID_USER, INT_TEST1, INT_TEST2, STR_VACATIONSPOT, diff --git a/include/sysinfo.h b/include/sysinfo.h index 8a77ef44856..027a463dc33 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -40,29 +40,29 @@ struct udevice; /** enum sysinfo_id - Standard IDs defined by U-Boot */ enum sysinfo_id { - SYSINFO_ID_NONE, + SYSID_NONE, /* For SMBIOS tables */ - SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, - SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, - SYSINFO_ID_SMBIOS_SYSTEM_VERSION, - SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, - SYSINFO_ID_SMBIOS_SYSTEM_SKU, - SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, - SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, - SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, - SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, - SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, - SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, + SYSID_SM_SYSTEM_MANUFACTURER, + SYSID_SM_SYSTEM_PRODUCT, + SYSID_SM_SYSTEM_VERSION, + SYSID_SM_SYSTEM_SERIAL, + SYSID_SM_SYSTEM_SKU, + SYSID_SM_SYSTEM_FAMILY, + SYSID_SM_BASEBOARD_MANUFACTURER, + SYSID_SM_BASEBOARD_PRODUCT, + SYSID_SM_BASEBOARD_VERSION, + SYSID_SM_BASEBOARD_SERIAL, + SYSID_SM_BASEBOARD_ASSET_TAG, /* For show_board_info() */ - SYSINFO_ID_BOARD_MODEL, - SYSINFO_ID_BOARD_MANUFACTURER, - SYSINFO_ID_PRIOR_STAGE_VERSION, - SYSINFO_ID_PRIOR_STAGE_DATE, + SYSID_BOARD_MODEL, + SYSID_BOARD_MANUFACTURER, + SYSID_PRIOR_STAGE_VERSION, + SYSID_PRIOR_STAGE_DATE, /* First value available for downstream/board used */ - SYSINFO_ID_USER = 0x1000, + SYSID_USER = 0x1000, }; struct sysinfo_ops { diff --git a/lib/smbios.c b/lib/smbios.c index 7c24ea129eb..a36d4b4e54a 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -270,7 +270,7 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop, const char *dval) { - return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE, dval); + return smbios_add_prop_si(ctx, prop, SYSID_NONE, dval); } static void smbios_set_eos(struct smbios_ctx *ctx, char *eos) @@ -393,27 +393,27 @@ static int smbios_write_type1(ulong *current, int handle, fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", - SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, + SYSID_SM_SYSTEM_MANUFACTURER, NULL); t->product_name = smbios_add_prop_si(ctx, "product", - SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, + SYSID_SM_SYSTEM_PRODUCT, NULL); t->version = smbios_add_prop_si(ctx, "version", - SYSINFO_ID_SMBIOS_SYSTEM_VERSION, + SYSID_SM_SYSTEM_VERSION, NULL); if (serial_str) { t->serial_number = smbios_add_prop(ctx, NULL, serial_str); strncpy((char *)t->uuid, serial_str, sizeof(t->uuid)); } else { t->serial_number = smbios_add_prop_si(ctx, "serial", - SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, + SYSID_SM_SYSTEM_SERIAL, NULL); } t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN; t->sku_number = smbios_add_prop_si(ctx, "sku", - SYSINFO_ID_SMBIOS_SYSTEM_SKU, NULL); + SYSID_SM_SYSTEM_SKU, NULL); t->family = smbios_add_prop_si(ctx, "family", - SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, NULL); + SYSID_SM_SYSTEM_FAMILY, NULL); len = t->length + smbios_string_table_len(ctx); *current += len; @@ -433,20 +433,20 @@ static int smbios_write_type2(ulong *current, int handle, fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", - SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, + SYSID_SM_BASEBOARD_MANUFACTURER, NULL); t->product_name = smbios_add_prop_si(ctx, "product", - SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, + SYSID_SM_BASEBOARD_PRODUCT, NULL); t->version = smbios_add_prop_si(ctx, "version", - SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, + SYSID_SM_BASEBOARD_VERSION, NULL); t->serial_number = smbios_add_prop_si(ctx, "serial", - SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, + SYSID_SM_BASEBOARD_SERIAL, NULL); t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag", - SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, + SYSID_SM_BASEBOARD_ASSET_TAG, NULL); t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; t->board_type = SMBIOS_BOARD_MOTHERBOARD; diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c index 155da3b6344..de9483c4291 100644 --- a/test/dm/sysinfo-gpio.c +++ b/test/dm/sysinfo-gpio.c @@ -29,9 +29,9 @@ static int dm_test_sysinfo_gpio(struct unit_test_state *uts) sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_DOWN); sandbox_gpio_set_flags(gpio, 17, 0); ut_assertok(sysinfo_detect(sysinfo)); - ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val)); + ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val)); ut_asserteq(19, val); - ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf), + ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf), buf)); ut_asserteq_str("rev_a", buf); @@ -43,9 +43,9 @@ static int dm_test_sysinfo_gpio(struct unit_test_state *uts) sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_UP); sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_DOWN); ut_assertok(sysinfo_detect(sysinfo)); - ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val)); + ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val)); ut_asserteq(5, val); - ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf), + ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf), buf)); ut_asserteq_str("foo", buf); @@ -57,9 +57,9 @@ static int dm_test_sysinfo_gpio(struct unit_test_state *uts) sandbox_gpio_set_flags(gpio, 16, 0); sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_UP); ut_assertok(sysinfo_detect(sysinfo)); - ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val)); + ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val)); ut_asserteq(15, val); - ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf), + ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf), buf)); ut_asserteq_str("unknown", buf); -- cgit v1.3.1 From 9063dba2d326e07682338cdb636787e99f1bf3f5 Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Mon, 11 Nov 2024 18:09:45 -0300 Subject: net: net_utils: Move ip_to_string to lib/net_utils.c The function string_to_ip is already in net_utils, which is compiled unconditionally, but ip_to_string is currently only accessible if the legacy network stack is selected. This commit puts ip_to_string in net_utils.c and removes it from the legacy network code. Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt --- include/net-common.h | 10 ++++++++++ lib/net_utils.c | 11 +++++++++++ net/net.c | 11 ----------- 3 files changed, 21 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index 3cd0f343744..b7a519e36db 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -426,6 +426,16 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr); */ struct in_addr string_to_ip(const char *s); +/** + * ip_to_string() - Convert a string to ip address + * + * Implemented in lib/net_utils.c (built unconditionally) + * + * @x: Input ip to parse + * @s: string containing the parsed ip address + */ +void ip_to_string(struct in_addr x, char *s); + /* copy a filename (allow for "..." notation, limit length) */ void copy_filename(char *dst, const char *src, int size); diff --git a/lib/net_utils.c b/lib/net_utils.c index c70fef0d991..621f6512b62 100644 --- a/lib/net_utils.c +++ b/lib/net_utils.c @@ -152,6 +152,17 @@ out_err: } #endif +void ip_to_string(struct in_addr x, char *s) +{ + x.s_addr = ntohl(x.s_addr); + sprintf(s, "%d.%d.%d.%d", + (int) ((x.s_addr >> 24) & 0xff), + (int) ((x.s_addr >> 16) & 0xff), + (int) ((x.s_addr >> 8) & 0xff), + (int) ((x.s_addr >> 0) & 0xff) + ); +} + void string_to_enetaddr(const char *addr, uint8_t *enetaddr) { char *end; diff --git a/net/net.c b/net/net.c index f47e9fbe33a..ca35704f661 100644 --- a/net/net.c +++ b/net/net.c @@ -1723,17 +1723,6 @@ int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len) return 1; } -void ip_to_string(struct in_addr x, char *s) -{ - x.s_addr = ntohl(x.s_addr); - sprintf(s, "%d.%d.%d.%d", - (int) ((x.s_addr >> 24) & 0xff), - (int) ((x.s_addr >> 16) & 0xff), - (int) ((x.s_addr >> 8) & 0xff), - (int) ((x.s_addr >> 0) & 0xff) - ); -} - void vlan_to_string(ushort x, char *s) { x = ntohs(x); -- cgit v1.3.1 From a1766d55e5766fb8fb5723bc599f7dd2cc999f6c Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sat, 23 Nov 2024 17:52:45 +0100 Subject: wdt: imx8qxp: add option to control external PMIC wdt via IMX8 SCU Driver for a PMIC watchdog timer controlled via Siemens SCU firmware extensions. Only useful on some Siemens i.MX8-based platforms as special SCFW is needed which provides the needed SCU API. Signed-off-by: Andrej Valek Signed-off-by: Heiko Schocher Reviewed-by: Alexander Sverdlin Reviewed-by: Stefan Roese --- drivers/misc/imx8/scu_api.c | 20 +++++++++++++ drivers/watchdog/Kconfig | 7 +++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/siemens_pmic_wdt.c | 59 +++++++++++++++++++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 3 ++ include/firmware/imx/sci/sci.h | 1 + 6 files changed, 91 insertions(+) create mode 100644 drivers/watchdog/siemens_pmic_wdt.c (limited to 'include') diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..a40c8badf9a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,26 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; } +int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG; + RPC_U8(&msg, 0U) = (u8)cmd; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..b39b2546e5c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -351,6 +351,13 @@ config WDT_SBSA In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. +config WDT_SIEMENS_PMIC + bool "Enable PMIC Watchdog Timer support for Siemens platforms" + depends on ARCH_IMX8 && WDT + help + Select this to enable the PMIC watchdog driver controlled via + IMX8 SCU API found on Siemens platforms. + config WDT_SL28CPLD bool "sl28cpld watchdog timer support" depends on WDT && SL28CPLD diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..9b6b1a8e8ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o +obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c new file mode 100644 index 00000000000..87e817bb5b2 --- /dev/null +++ b/drivers/watchdog/siemens_pmic_wdt.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for a PMIC watchdog timer controlled via Siemens SCU firmware + * extensions. Only useful on some Siemens i.MX8-based platforms as + * special NXP SCFW is needed which provides the needed SCU API. + * + * Copyright (C) 2024 Siemens AG + */ + +#include +#include +#include + +/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35 + +static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + /* start external watchdog via Timer API */ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_START_WDT); +} + +static int scu_wdt_stop(struct udevice *dev) +{ + /* stop external watchdog via Timer API */ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_STOP_WDT); +} + +static int scu_wdt_reset(struct udevice *dev) +{ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_PING_WDT); +} + +static int scu_wdt_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + return 0; +} + +static const struct wdt_ops scu_wdt_ops = { + .reset = scu_wdt_reset, + .start = scu_wdt_start, + .stop = scu_wdt_stop, +}; + +static const struct udevice_id scu_wdt_ids[] = { + { .compatible = "siemens,scu-wdt" }, + { } +}; + +U_BOOT_DRIVER(scu_wdt) = { + .name = "scu_wdt", + .id = UCLASS_WDT, + .of_match = scu_wdt_ids, + .probe = scu_wdt_probe, + .ops = &scu_wdt_ops, +}; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..04acc7ff95b 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -231,4 +231,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ +/* Siemens specific API extension */ +#define TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */ + #endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..588f3671103 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); /* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd); /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, -- cgit v1.3.1 From a57ef36323eb65d3d83c504f9f0a9ad831ec825c Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sat, 23 Nov 2024 17:52:46 +0100 Subject: net: fec_mxc: fix probing for imx8qxp probing on capricorn board (imx8qxp based) brings: Can't find FEC0 clk rate: -19 Cause is that when probing fec_mxc driver, fec_mii_setspeed() is called which calls fec_get_clk_rate(). fec_mii_setspeed() calls fec_get_clk_rate with NULL pointer for udev and so as in IMX8QXP case CLK_CCF is enabled udev gets searched with: uclass_get_device_by_seq(UCLASS_ETH, idx, &dev); but we do not have yet a UCLASS_ETH ! as we just probing it! Prevent this by passing udev to fec_get_clk_rate() Signed-off-by: Heiko Schocher --- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- drivers/net/fec_mxc.c | 14 +++++++------- include/netdev.h | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index b85fd806cba..1adee9a461f 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -281,7 +281,7 @@ int board_eth_init(struct bd_info *bis) setup_iomux_enet(); #ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); + bus = fec_get_miibus(NULL, base, -1); if (!bus) return -EINVAL; /* scan phy 4,5,6,7 */ diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index e9269ef5353..b543bf8c1fb 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -385,7 +385,7 @@ static int find_ethernet_phy(void) int phy_addr = -ENOENT; #ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(ENET_BASE_ADDR, -1); + bus = fec_get_miibus(NULL, ENET_BASE_ADDR, -1); if (!bus) return -ENOENT; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d6d5cb52fdd..eca681b16d1 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -160,7 +160,7 @@ static int fec_get_clk_rate(void *udev, int idx) } } -static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -182,7 +182,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret; - ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(dev, 0); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -581,7 +581,7 @@ static int fecmxc_init(struct udevice *dev) fec_reg_setup(fec); if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(dev, fec->bus->priv); /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -996,7 +996,7 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id) { struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; @@ -1018,7 +1018,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(dev, eth); return bus; } @@ -1354,10 +1354,10 @@ static int fecmxc_probe(struct udevice *dev) if (!bus) { dm_mii_bus = false; #ifdef CONFIG_FEC_MXC_MDIO_BASE - bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, + bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE, dev_seq(dev)); #else - bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); + bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev)); #endif } if (!bus) { diff --git a/include/netdev.h b/include/netdev.h index 2a06d9a261b..949245ecdec 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -117,7 +117,7 @@ static inline int pci_eth_init(struct bd_info *bis) return num; } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id); +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device; -- cgit v1.3.1 From c8b3c46bdeb9b1d98f930bbcfbcce7df7f04e1bc Mon Sep 17 00:00:00 2001 From: Enrico Leto Date: Sat, 23 Nov 2024 17:52:50 +0100 Subject: siemens: capricorn: move to cxg3 reference project with deneb board We have many HW with capricorn i.MX8X boards. The difference in u-boot is at all by the display of the LEDs. * put upstream a reference project & board for DT and defconfig * use the capricorn prefix outside the board/siemens/capricorn folder Signed-off-by: Enrico Leto Signed-off-by: Heiko Schocher --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8-capricorn-cxg3.dts | 129 +++++++++++++ arch/arm/dts/imx8-capricorn-u-boot.dtsi | 135 ++++++++++++++ arch/arm/dts/imx8-capricorn.dtsi | 181 ++++++++++++++++++ arch/arm/dts/imx8-deneb.dts | 10 - arch/arm/dts/imx8-giedi.dts | 10 - arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi | 135 -------------- arch/arm/dts/imx8qxp-capricorn.dtsi | 285 ----------------------------- arch/arm/mach-imx/imx8/Kconfig | 11 +- board/siemens/capricorn/Kconfig | 18 +- configs/capricorn_cxg3_defconfig | 134 ++++++++++++++ configs/deneb_defconfig | 133 -------------- configs/giedi_defconfig | 133 -------------- include/configs/deneb.h | 16 -- 14 files changed, 584 insertions(+), 749 deletions(-) create mode 100644 arch/arm/dts/imx8-capricorn-cxg3.dts create mode 100644 arch/arm/dts/imx8-capricorn-u-boot.dtsi create mode 100644 arch/arm/dts/imx8-capricorn.dtsi delete mode 100644 arch/arm/dts/imx8-deneb.dts delete mode 100644 arch/arm/dts/imx8-giedi.dts delete mode 100644 arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi delete mode 100644 arch/arm/dts/imx8qxp-capricorn.dtsi create mode 100644 configs/capricorn_cxg3_defconfig delete mode 100644 configs/deneb_defconfig delete mode 100644 configs/giedi_defconfig delete mode 100644 include/configs/deneb.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 042282f3723..d81a9f95977 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -935,8 +935,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb \ - imx8-deneb.dtb \ - imx8-giedi.dtb + imx8-capricorn-cxg3.dtb \ dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts new file mode 100644 index 00000000000..2f8597579f3 --- /dev/null +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8-capricorn.dtsi" + +/ { + model = "Siemens CXG3"; + + leds_default: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + run { + label = "run"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + flt { + label = "flt"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + svc { + label = "svc"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_tx { + label = "com1-tx"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_rx { + label = "com1-rx"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_tx { + label = "com2-tx"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_rx { + label = "com2-rx"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + cloud { + label = "cloud"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wlan { + label = "wlan"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + apps { + label = "apps"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg2 { + label = "dbg2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg3 { + label = "dbg3"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg4 { + label = "dbg4"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio_keys>; + + muxcgrp: imx8qxp-som { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + >; + }; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021 + >; + }; +}; diff --git a/arch/arm/dts/imx8-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi new file mode 100644 index 00000000000..cba56188f86 --- /dev/null +++ b/arch/arm/dts/imx8-capricorn-u-boot.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8qxp-u-boot.dtsi" + +&{/imx8qx-pm} { + + bootph-pre-ram; +}; + +&mu { + bootph-pre-ram; +}; + +&clk { + bootph-pre-ram; +}; + +&iomuxc { + bootph-pre-ram; +}; + +&pd_lsio { + bootph-pre-ram; +}; + +&pd_lsio_gpio0 { + bootph-pre-ram; +}; + +&pd_lsio_gpio1 { + bootph-pre-ram; +}; + +&pd_lsio_gpio2 { + bootph-pre-ram; +}; + +&pd_lsio_gpio3 { + bootph-pre-ram; +}; + +&pd_lsio_gpio4 { + bootph-pre-ram; +}; + +&pd_lsio_gpio5 { + bootph-pre-ram; +}; + +&pd_lsio_gpio6 { + bootph-pre-ram; +}; + +&pd_lsio_gpio7 { + bootph-pre-ram; +}; + +&pd_dma { + bootph-pre-ram; +}; + +&pd_dma_lpuart0 { + bootph-pre-ram; +}; + +&pd_dma_lpuart2 { + bootph-pre-ram; +}; + +&pd_conn { + bootph-pre-ram; +}; + +&pd_conn_sdch0 { + bootph-pre-ram; +}; + +&pd_conn_sdch1 { + bootph-pre-ram; +}; + +&pd_conn_sdch2 { + bootph-pre-ram; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&gpio6 { + bootph-pre-ram; +}; + +&gpio7 { + bootph-pre-ram; +}; + +&lpuart0 { + bootph-pre-ram; +}; + +&lpuart2 { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi new file mode 100644 index 00000000000..4918bf8f567 --- /dev/null +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + * + * Copyright 2019 Siemens AG + * + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" +#include "imx8-capricorn-u-boot.dtsi" + +/ { + chosen { + bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; + stdout-path = &lpuart2; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + + muxcgrp: imx8qxp-som { + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020 + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 + //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 + + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ + >; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + clock-frequency=<52000000>; + no-1-8-v; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&fec1 { + status ="disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rmii"; + + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts deleted file mode 100644 index 04c764aa941..00000000000 --- a/arch/arm/dts/imx8-deneb.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Deneb"; -}; diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts deleted file mode 100644 index 0dbfef2ee97..00000000000 --- a/arch/arm/dts/imx8-giedi.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Giedi"; -}; diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi deleted file mode 100644 index cba56188f86..00000000000 --- a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-u-boot.dtsi" - -&{/imx8qx-pm} { - - bootph-pre-ram; -}; - -&mu { - bootph-pre-ram; -}; - -&clk { - bootph-pre-ram; -}; - -&iomuxc { - bootph-pre-ram; -}; - -&pd_lsio { - bootph-pre-ram; -}; - -&pd_lsio_gpio0 { - bootph-pre-ram; -}; - -&pd_lsio_gpio1 { - bootph-pre-ram; -}; - -&pd_lsio_gpio2 { - bootph-pre-ram; -}; - -&pd_lsio_gpio3 { - bootph-pre-ram; -}; - -&pd_lsio_gpio4 { - bootph-pre-ram; -}; - -&pd_lsio_gpio5 { - bootph-pre-ram; -}; - -&pd_lsio_gpio6 { - bootph-pre-ram; -}; - -&pd_lsio_gpio7 { - bootph-pre-ram; -}; - -&pd_dma { - bootph-pre-ram; -}; - -&pd_dma_lpuart0 { - bootph-pre-ram; -}; - -&pd_dma_lpuart2 { - bootph-pre-ram; -}; - -&pd_conn { - bootph-pre-ram; -}; - -&pd_conn_sdch0 { - bootph-pre-ram; -}; - -&pd_conn_sdch1 { - bootph-pre-ram; -}; - -&pd_conn_sdch2 { - bootph-pre-ram; -}; - -&gpio0 { - bootph-pre-ram; -}; - -&gpio1 { - bootph-pre-ram; -}; - -&gpio2 { - bootph-pre-ram; -}; - -&gpio3 { - bootph-pre-ram; -}; - -&gpio4 { - bootph-pre-ram; -}; - -&gpio5 { - bootph-pre-ram; -}; - -&gpio6 { - bootph-pre-ram; -}; - -&gpio7 { - bootph-pre-ram; -}; - -&lpuart0 { - bootph-pre-ram; -}; - -&lpuart2 { - bootph-pre-ram; -}; - -&usdhc1 { - bootph-pre-ram; -}; - -&usdhc2 { - bootph-pre-ram; -}; diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8qxp-capricorn.dtsi deleted file mode 100644 index db5653ea1ff..00000000000 --- a/arch/arm/dts/imx8qxp-capricorn.dtsi +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 NXP - * - * Copyright 2019 Siemens AG - * - */ - -/dts-v1/; - -#include "fsl-imx8qxp.dtsi" -#include "imx8qxp-capricorn-u-boot.dtsi" - -/ { - model = "Siemens Giedi"; - compatible = "siemens,capricorn", "fsl,imx8qxp"; - - chosen { - bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; - stdout-path = &lpuart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - run { - label = "run"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - flt { - label = "flt"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - svc { - label = "svc"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_tx { - label = "com1-tx"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_rx { - label = "com1-rx"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_tx { - label = "com2-tx"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_rx { - label = "com2-rx"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - cloud { - label = "cloud"; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - wlan { - label = "wlan"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg1 { - label = "dbg1"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg2 { - label = "dbg2"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg3 { - label = "dbg3"; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg4 { - label = "dbg4"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - muxcgrp: imx8qxp-som { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 - SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 - SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 - SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 - SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 - SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 - SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 - SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 - SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 - SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 - SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 - SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 - >; - }; - - pinctrl_lpi2c0: lpi2c0grp { - fsl,pins = < - SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 - SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020 - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020 - SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020 - >; - }; - - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 - SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 - SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 - SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 - SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 - SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 - SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 - SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 - SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 - //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 - >; - }; - - pinctrl_fec2: fec2grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - - SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 - SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 - - SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ - >; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c0>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1>; - status = "okay"; -}; - -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - clock-frequency=<52000000>; - no-1-8-v; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&fec1 { - status ="disabled"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rmii"; - - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 59d11b3179e..9a43beda6fa 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -54,15 +54,8 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP -config TARGET_DENEB - bool "Support i.MX8QXP Capricorn Deneb board" - select BINMAN - select BOARD_LATE_INIT - select FACTORYSET - select IMX8QXP - -config TARGET_GIEDI - bool "Support i.MX8QXP Capricorn Giedi board" +config TARGET_CAPRICORN + bool "Support i.MX8QXP Capricorn board" select BINMAN select BOARD_LATE_INIT select FACTORYSET diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index c5a28ff0220..371eca346e0 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -1,19 +1,5 @@ -if TARGET_GIEDI +if TARGET_CAPRICORN -config SYS_BOARD - default "capricorn" - -config SYS_VENDOR - default "siemens" - -config SYS_CONFIG_NAME - default "giedi" - -config IMX_CONFIG - default "board/siemens/capricorn/imximage.cfg" -endif - -if TARGET_DENEB config SYS_BOARD default "capricorn" @@ -22,7 +8,7 @@ config SYS_VENDOR default "siemens" config SYS_CONFIG_NAME - default "deneb" + default "capricorn-common" config IMX_CONFIG default "board/siemens/capricorn/imximage.cfg" diff --git a/configs/capricorn_cxg3_defconfig b/configs/capricorn_cxg3_defconfig new file mode 100644 index 00000000000..d2bcc46d306 --- /dev/null +++ b/configs/capricorn_cxg3_defconfig @@ -0,0 +1,134 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_LEN=0x2800000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3" +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_TARGET_CAPRICORN=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x13e000 +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +CONFIG_SYS_BOOTM_LEN=0x800000 +CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x2000 +CONFIG_IDENT_STRING=" ##v01.06" +CONFIG_REMAKE_ELF=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2073 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MV88E61XX_SWITCH=y +CONFIG_MV88E61XX_CPU_PORT=5 +CONFIG_MV88E61XX_PHY_PORTS=0x7 +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_SPL_WDT is not set +CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig deleted file mode 100644 index 98841bb8771..00000000000 --- a/configs/deneb_defconfig +++ /dev/null @@ -1,133 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb" -CONFIG_TARGET_DENEB=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x13e000 -CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_SYS_LOAD_ADDR=0x80280000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING=" ##v01.06" -CONFIG_REMAKE_ELF=y -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_AUTOBOOT_KEYED_CTRLC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2073 -CONFIG_LOG=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set -CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_READ=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth1" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_SPL_CLK=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_MV88E61XX_SWITCH=y -CONFIG_MV88E61XX_CPU_PORT=5 -CONFIG_MV88E61XX_PHY_PORTS=0x7 -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set -CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig deleted file mode 100644 index af9c7a4aed6..00000000000 --- a/configs/giedi_defconfig +++ /dev/null @@ -1,133 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" -CONFIG_TARGET_GIEDI=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x13e000 -CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_SYS_LOAD_ADDR=0x80280000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING=" ##v01.07" -CONFIG_REMAKE_ELF=y -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_AUTOBOOT_KEYED_CTRLC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2073 -CONFIG_LOG=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set -CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_READ=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth1" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_SPL_CLK=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_MV88E61XX_SWITCH=y -CONFIG_MV88E61XX_CPU_PORT=5 -CONFIG_MV88E61XX_PHY_PORTS=0x7 -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set -CONFIG_SPL_TINY_MEMSET=y diff --git a/include/configs/deneb.h b/include/configs/deneb.h deleted file mode 100644 index f155bb8bf50..00000000000 --- a/include/configs/deneb.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Siemens AG - * - */ - -#ifndef __DENEB_H -#define __DENEB_H - -#include "capricorn-common.h" - -/* DDR3 board total DDR is 2 GB */ -#undef PHYS_SDRAM_1_SIZE -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ - -#endif /* __DENEB_H */ -- cgit v1.3.1 From 0cc0f68b7e6ce3865ba2708ffefc44c5117bf676 Mon Sep 17 00:00:00 2001 From: Enrico Leto Date: Sat, 23 Nov 2024 17:53:00 +0100 Subject: siemens: capricorn: get ram size from system controller Get the memory region information from system controller to reduce the number of platform specific headers. We were aligned on NXP mek board implementation. This need at least 1 header per memory configuration. Signed-off-by: Enrico Leto Signed-off-by: Heiko Schocher --- board/siemens/capricorn/board.c | 34 ++++++++++++++++++++++++++++++++++ include/configs/capricorn-common.h | 4 +++- 2 files changed, 37 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index decac63db3b..484e2707183 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -73,6 +73,40 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_XPL_BUILD +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + sc_faddr_t addr_start, addr_end; + sc_faddr_t sdram_1_size, sdram_2_size; + sc_err_t sc_err; + + sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end); + if (sc_err == SC_ERR_NONE) { + if (addr_end < 0x100000000) { + /* only lower RAM available */ + sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1; + sdram_2_size = 0; + } else { + /* lower RAM (2 GB) und upper RAM available */ + sdram_1_size = SZ_2G; + sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2; + } + } else { + /* Get default in case it would fail */ + sdram_1_size = PHYS_SDRAM_1_SIZE; + sdram_2_size = PHYS_SDRAM_2_SIZE; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = sdram_1_size; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = sdram_2_size; +} +#endif /* ! CONFIG_XPL_BUILD */ + #define ENET_PHY_RESET IMX_GPIO_NR(0, 3) #define ENET_TEST_1 IMX_GPIO_NR(0, 8) #define ENET_TEST_2 IMX_GPIO_NR(0, 9) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1f61b2b6af6..4d95f3fd79b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -95,7 +95,9 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -/* DDR3 board total DDR is 1 GB */ +/* Set default values to the smallest DDR we have in capricorn modules + * Use it in case the system controller would return an error + */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -- cgit v1.3.1 From 86e931535cf6c2014ef384bd7cacea94aadf1645 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Tue, 26 Nov 2024 09:06:11 +0100 Subject: configs: khadas-vim3l_android{_ab}: move on bootmeth android Actually khadas vim3l use distro command to boot android image. Move on new bootmeth android for A/B and non-A/B vim3l android. Reviewed-by: Mattijs Korpershoek Acked-by: Neil Armstrong Signed-off-by: Guillaume La Roque Link: https://lore.kernel.org/r/20241126-adnroidv2-v4-3-11636106dc69@baylibre.com Signed-off-by: Mattijs Korpershoek --- configs/khadas-vim3l_android_ab_defconfig | 7 ++++++- configs/khadas-vim3l_android_defconfig | 7 ++++++- include/configs/khadas-vim3l_android.h | 25 +++++++++++++++++++++---- include/configs/meson64_android.h | 3 --- 4 files changed, 33 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 4d7b90f2300..43db61056ba 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -35,7 +41,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 4ec27262cdc..32d57a5b909 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -34,7 +40,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h index f39a3782d66..1869249e7c9 100644 --- a/include/configs/khadas-vim3l_android.h +++ b/include/configs/khadas-vim3l_android.h @@ -41,10 +41,27 @@ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -#define EXTRA_ANDROID_ENV_SETTINGS \ - "board=vim3l\0" \ - "board_name=vim3l\0" \ +#define CFG_EXTRA_ENV_SETTINGS \ + "board=vim3l\0" \ + "board_name=vim3l\0" \ + "bootmeths=android\0" \ + "bootcmd=bootflow scan\0" \ + "adtb_idx=2\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \ + "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "dtboaddr=0x08200000\0" \ + "loadaddr=0x01080000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ -#include +#include #endif /* __CONFIG_H */ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 77364bbf9cf..37ef8b8f7a7 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -104,9 +104,6 @@ "elif test $board_name = sei610; then " \ "echo \" Reading DTB for sei610...\"; " \ "setenv dtb_index 1;" \ - "elif test $board_name = vim3l; then " \ - "echo \" Reading DTB for vim3l...\"; " \ - "setenv dtb_index 2;" \ "elif test $board_name = vim3; then " \ "echo \" Reading DTB for vim3...\"; " \ "setenv dtb_index 3;" \ -- cgit v1.3.1 From 83a6ae671680010ae52e83554c431b095fe2b5d5 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Tue, 26 Nov 2024 09:06:12 +0100 Subject: configs: khadas-vim3_android{_ab}: move on bootmeth android Actually khadas vim3 use distro command to boot android image. Move on new bootmeth android for A/B and non-A/B vim3 android. Reviewed-by: Mattijs Korpershoek Acked-by: Neil Armstrong Signed-off-by: Guillaume La Roque Link: https://lore.kernel.org/r/20241126-adnroidv2-v4-4-11636106dc69@baylibre.com Signed-off-by: Mattijs Korpershoek --- configs/khadas-vim3_android_ab_defconfig | 7 ++++++- configs/khadas-vim3_android_defconfig | 7 ++++++- include/configs/khadas-vim3_android.h | 25 +++++++++++++++++++++---- include/configs/meson64_android.h | 3 --- 4 files changed, 33 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index de5357c45cb..a078c5d363a 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -35,7 +41,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index a0d9c423c3c..b77a44ce859 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -34,7 +40,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h index 0e2953fe71b..551ab51c881 100644 --- a/include/configs/khadas-vim3_android.h +++ b/include/configs/khadas-vim3_android.h @@ -41,10 +41,27 @@ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -#define EXTRA_ANDROID_ENV_SETTINGS \ - "board=vim3\0" \ - "board_name=vim3\0" \ +#define CFG_EXTRA_ENV_SETTINGS \ + "board=vim3\0" \ + "board_name=vim3\0" \ + "bootmeths=android\0" \ + "bootcmd=bootflow scan\0" \ + "adtb_idx=3\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \ + "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "dtboaddr=0x08200000\0" \ + "loadaddr=0x01080000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ -#include +#include #endif /* __CONFIG_H */ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 37ef8b8f7a7..d6ef0a83a68 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -104,9 +104,6 @@ "elif test $board_name = sei610; then " \ "echo \" Reading DTB for sei610...\"; " \ "setenv dtb_index 1;" \ - "elif test $board_name = vim3; then " \ - "echo \" Reading DTB for vim3...\"; " \ - "setenv dtb_index 3;" \ "else " \ "echo Error: Android boot is not supported for $board_name; " \ "exit; " \ -- cgit v1.3.1 From abadcda24b100b8eb0f138085cca6595518cec85 Mon Sep 17 00:00:00 2001 From: Julien Masson Date: Thu, 21 Nov 2024 11:59:55 +0100 Subject: bootstd: android: don't read whole partition sizes The current implementation is reading the whole partition for boot and vendor_boot image which can be long following the size of the partition or the time to read blocks (driver/SoC specific). For example with mediatek mt8365 EVK board, we have a 64MiB boot partition and the boot image flashed in this partition is only 42MiB. It takes ~8-9 secs to read the boot partition. Instead we can retrieved the boot image and vendor boot image size with these new functions: - android_image_get_bootimg_size - android_image_get_vendor_bootimg_size Use these information and read only the necessary. By doing this with mt8365 EVK board, we read boot image in ~5 secs. Signed-off-by: Julien Masson Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20241121-bootmeth-android-part-sizes-v1-1-25760bbd0f08@baylibre.com Signed-off-by: Mattijs Korpershoek --- boot/bootmeth_android.c | 28 +++++++++++++++++++++++----- boot/image-android.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ include/image.h | 24 ++++++++++++++++++++++++ 3 files changed, 92 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/boot/bootmeth_android.c b/boot/bootmeth_android.c index 2aac32331d3..3a5144aaa3b 100644 --- a/boot/bootmeth_android.c +++ b/boot/bootmeth_android.c @@ -45,6 +45,8 @@ struct android_priv { enum android_boot_mode boot_mode; char *slot; u32 header_version; + u32 boot_img_size; + u32 vendor_boot_img_size; }; static int android_check(struct udevice *dev, struct bootflow_iter *iter) @@ -98,7 +100,13 @@ static int scan_boot_part(struct udevice *blk, struct android_priv *priv) return log_msg_ret("header", -ENOENT); } + if (!android_image_get_bootimg_size(buf, &priv->boot_img_size)) { + free(buf); + return log_msg_ret("get bootimg size", -EINVAL); + } + priv->header_version = ((struct andr_boot_img_hdr_v0 *)buf)->header_version; + free(buf); return 0; @@ -138,6 +146,12 @@ static int scan_vendor_boot_part(struct udevice *blk, struct android_priv *priv) free(buf); return log_msg_ret("header", -ENOENT); } + + if (!android_image_get_vendor_bootimg_size(buf, &priv->vendor_boot_img_size)) { + free(buf); + return log_msg_ret("get vendor bootimg size", -EINVAL); + } + free(buf); return 0; @@ -330,15 +344,17 @@ static int android_read_file(struct udevice *dev, struct bootflow *bflow, * @blk: Block device to read * @name: Partition name to read * @slot: Nul-terminated slot suffixed to partition name ("a\0" or "b\0") + * @image_size: Image size in bytes used when reading the partition * @addr: Address where the partition content is loaded into * Return: 0 if OK, negative errno on failure. */ static int read_slotted_partition(struct blk_desc *desc, const char *const name, - const char slot[2], ulong addr) + const char slot[2], ulong image_size, ulong addr) { struct disk_partition partition; char partname[PART_NAME_LEN]; size_t partname_len; + ulong num_blks = DIV_ROUND_UP(image_size, desc->blksz); int ret; u32 n; @@ -364,8 +380,8 @@ static int read_slotted_partition(struct blk_desc *desc, const char *const name, if (ret < 0) return log_msg_ret("part", ret); - n = blk_dread(desc, partition.start, partition.size, map_sysmem(addr, 0)); - if (n < partition.size) + n = blk_dread(desc, partition.start, num_blks, map_sysmem(addr, 0)); + if (n < num_blks) return log_msg_ret("part read", -EIO); return 0; @@ -498,12 +514,14 @@ static int boot_android_normal(struct bootflow *bflow) if (ret < 0) return log_msg_ret("read slot", ret); - ret = read_slotted_partition(desc, "boot", priv->slot, loadaddr); + ret = read_slotted_partition(desc, "boot", priv->slot, priv->boot_img_size, + loadaddr); if (ret < 0) return log_msg_ret("read boot", ret); if (priv->header_version >= 3) { - ret = read_slotted_partition(desc, "vendor_boot", priv->slot, vloadaddr); + ret = read_slotted_partition(desc, "vendor_boot", priv->slot, + priv->vendor_boot_img_size, vloadaddr); if (ret < 0) return log_msg_ret("read vendor_boot", ret); set_avendor_bootimg_addr(vloadaddr); diff --git a/boot/image-android.c b/boot/image-android.c index cd01278f211..93b54bf8d79 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -178,6 +178,51 @@ static void android_boot_image_v0_v1_v2_parse_hdr(const struct andr_boot_img_hdr data->boot_img_total_size = end - (ulong)hdr; } +bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size) +{ + struct andr_image_data data; + + if (!hdr || !boot_img_size) { + printf("hdr or boot_img_size can't be NULL\n"); + return false; + } + + if (!is_android_boot_image_header(hdr)) { + printf("Incorrect boot image header\n"); + return false; + } + + if (((struct andr_boot_img_hdr_v0 *)hdr)->header_version <= 2) + android_boot_image_v0_v1_v2_parse_hdr(hdr, &data); + else + android_boot_image_v3_v4_parse_hdr(hdr, &data); + + *boot_img_size = data.boot_img_total_size; + + return true; +} + +bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size) +{ + struct andr_image_data data; + + if (!hdr || !vendor_boot_img_size) { + printf("hdr or vendor_boot_img_size can't be NULL\n"); + return false; + } + + if (!is_android_vendor_boot_image_header(hdr)) { + printf("Incorrect vendor boot image header\n"); + return false; + } + + android_vendor_boot_image_v3_v4_parse_hdr(hdr, &data); + + *vendor_boot_img_size = data.vendor_boot_img_total_size; + + return true; +} + bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr, struct andr_image_data *data) { diff --git a/include/image.h b/include/image.h index c52fced9b40..9be5acd8158 100644 --- a/include/image.h +++ b/include/image.h @@ -1801,6 +1801,30 @@ int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); struct cipher_algo *image_get_cipher_algo(const char *full_name); struct andr_image_data; +/** + * android_image_get_bootimg_size() - Extract size of Android boot image + * + * This is used to extract the size of an Android boot image + * from boot image header. + * + * @hdr: Pointer to boot image header + * @boot_img_size: On exit returns the size in bytes of the boot image + * Return: true if succeeded, false otherwise + */ +bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size); + +/** + * android_image_get_vendor_bootimg_size() - Extract size of Android vendor-boot image + * + * This is used to extract the size of an Android vendor-boot image + * from vendor-boot image header. + * + * @hdr: Pointer to vendor-boot image header + * @vendor_boot_img_size: On exit returns the size in bytes of the vendor-boot image + * Return: true if succeeded, false otherwise + */ +bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size); + /** * android_image_get_data() - Parse Android boot images * -- cgit v1.3.1 From 9bab7d2a7c37b486ed6c368cfdfb42575ab112e4 Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:16 -0300 Subject: net: wget: let wget_with_dns work with dns disabled This was marked as TODO in the code: - Enable use of wget_with_dns even if CMD_DNS is disabled if the given uri has the ip address for the http server. - Move the check for CMD_DNS inside wget_with_dns. - Rename wget_with_dns to wget_do_request Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt Reviewed-by: Jerome Forissier --- include/net-common.h | 7 +++++-- lib/efi_loader/efi_bootmgr.c | 2 +- net/lwip/wget.c | 4 ++-- net/net-common.c | 2 +- net/wget.c | 34 ++++++++++++++++++++-------------- 5 files changed, 29 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index c5e314b360d..8fc1bac47f5 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -501,13 +501,16 @@ int dhcp_run(ulong addr, const char *fname, bool autoload); int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); /** - * wget_with_dns() - runs dns host IP address resulution before wget + * wget_do_request() - sends a wget request + * + * Sends a wget request, if DNS resolution is enabled it resolves the + * given uri. * * @dst_addr: destination address to download the file * @uri: uri string of target file of wget * Return: zero on success, negative if failed */ -int wget_with_dns(ulong dst_addr, char *uri); +int wget_do_request(ulong dst_addr, char *uri); /** * wget_validate_uri() - varidate the uri * diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 8c51a6ef2ed..c6124c590d9 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -479,7 +479,7 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp, } image_addr = hextoul(s, NULL); - err = wget_with_dns(image_addr, uridp->uri); + err = wget_do_request(image_addr, uridp->uri); if (err < 0) { ret = EFI_INVALID_PARAMETER; goto err; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index 263d6dab26c..669eded0f38 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -353,7 +353,7 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) return -1; } -int wget_with_dns(ulong dst_addr, char *uri) +int wget_do_request(ulong dst_addr, char *uri) { eth_set_current(); @@ -387,7 +387,7 @@ int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_FAILURE; wget_info = &default_wget_info; - if (wget_with_dns(dst_addr, nurl)) + if (wget_do_request(dst_addr, nurl)) return CMD_RET_FAILURE; return CMD_RET_SUCCESS; diff --git a/net/net-common.c b/net/net-common.c index 45288fe5f80..e01b0da7d7b 100644 --- a/net/net-common.c +++ b/net/net-common.c @@ -23,5 +23,5 @@ struct wget_http_info *wget_info; int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info) { wget_info = info ? info : &default_wget_info; - return wget_with_dns(dst_addr, uri); + return wget_do_request(dst_addr, uri); } diff --git a/net/wget.c b/net/wget.c index 5d70b7a82e0..f3b43b06b8b 100644 --- a/net/wget.c +++ b/net/wget.c @@ -535,8 +535,7 @@ void wget_start(void) wget_send(TCP_SYN, 0, 0, 0); } -#if (IS_ENABLED(CONFIG_CMD_DNS)) -int wget_with_dns(ulong dst_addr, char *uri) +int wget_do_request(ulong dst_addr, char *uri) { int ret; char *s, *host_name, *file_name, *str_copy; @@ -555,24 +554,32 @@ int wget_with_dns(ulong dst_addr, char *uri) s = str_copy + strlen("http://"); host_name = strsep(&s, "/"); if (!s) { - log_err("Error: invalied uri, no file path\n"); ret = -EINVAL; goto out; } file_name = s; - /* TODO: If the given uri has ip address for the http server, skip dns */ - net_dns_resolve = host_name; - net_dns_env_var = "httpserverip"; - if (net_loop(DNS) < 0) { - log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve); - ret = -EINVAL; - goto out; - } - s = env_get("httpserverip"); - if (!s) { + host_name = strsep(&host_name, ":"); + + if (string_to_ip(host_name).s_addr) { + s = host_name; + } else { +#if IS_ENABLED(CONFIG_CMD_DNS) + net_dns_resolve = host_name; + net_dns_env_var = "httpserverip"; + if (net_loop(DNS) < 0) { + ret = -EINVAL; + goto out; + } + s = env_get("httpserverip"); + if (!s) { + ret = -EINVAL; + goto out; + } +#else ret = -EINVAL; goto out; +#endif } strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name)); @@ -586,7 +593,6 @@ out: return ret < 0 ? ret : 0; } -#endif /** * wget_validate_uri() - validate the uri for wget -- cgit v1.3.1 From 5a65b2332255100daa88b183058568b003d2fd3b Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:17 -0300 Subject: efi_loader: device_path: add definition of DEVICE_PATH_SUB_TYPE_MSG_IPV4 Add definition for DEVICE_PATH_SUB_TYPE_MSG_IPV4 device path subtype. Signed-off-by: Adriano Cordova Reviewed-by: Ilias Apalodimas --- include/efi_api.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index f07d074f93b..99ee7495224 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -616,6 +616,7 @@ struct efi_device_path_acpi_path { # define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02 # define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05 # define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b +# define DEVICE_PATH_SUB_TYPE_MSG_IPV4 0x0c # define DEVICE_PATH_SUB_TYPE_MSG_UART 0x0e # define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f # define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI 0x10 @@ -691,6 +692,22 @@ struct efi_device_path_uri { u8 uri[]; } __packed; +struct efi_ipv4_address { + u8 ip_addr[4]; +}; + +struct efi_device_path_ipv4 { + struct efi_device_path dp; + struct efi_ipv4_address local_ip_address; + struct efi_ipv4_address remote_ip_address; + u16 local_port; + u16 remote_port; + u16 protocol; + u8 static_ip_address; + struct efi_ipv4_address gateway_ip_address; + struct efi_ipv4_address subnet_mask; +} __packed; + #define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04 # define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01 # define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02 -- cgit v1.3.1 From b98d2323505bcc0dfe5863f02c3f6b43d7756d8a Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:20 -0300 Subject: efi_api: add definitions for HTTP and IP4_CONFIG2 protocols Add EFI definitions for EFI_IP4_CONFIG2_PROTOCOL, EFI_HTTP_SERVICE_BINDING_PROTOCOL, and EFI_HTTP_PROTOCOL. According to UEFI spec 2.10. Signed-off-by: Adriano Cordova Reviewed-by: Ilias Apalodimas Acked-by: Ilias Apalodimas --- include/efi_api.h | 203 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index 99ee7495224..61c4eda8f8a 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -1725,6 +1725,209 @@ struct efi_pxe_base_code_protocol { struct efi_pxe_mode *mode; }; +#define EFI_IP4_CONFIG2_PROTOCOL_GUID \ + EFI_GUID(0x5b446ed1, 0xe30b, 0x4faa, \ + 0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80) + +enum efi_ip4_config2_data_type { + EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO, + EFI_IP4_CONFIG2_DATA_TYPE_POLICY, + EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + EFI_IP4_CONFIG2_DATA_TYPE_GATEWAY, + EFI_IP4_CONFIG2_DATA_TYPE_DNSSERVER, + EFI_IP4_CONFIG2_DATA_TYPE_MAXIMUM, +}; + +struct efi_ip4_config2_protocol { + efi_status_t (EFIAPI * set_data)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t data_size, + void *data); + efi_status_t (EFIAPI * get_data)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t *data_size, + void *data); + efi_status_t (EFIAPI * register_data_notify)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event); + efi_status_t (EFIAPI * unregister_data_notify)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event); +}; + +struct efi_ip4_route_table { + struct efi_ipv4_address subnet_address; + struct efi_ipv4_address subnet_mask; + struct efi_ipv4_address gateway_address; +}; + +#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32 + +struct efi_ip4_config2_interface_info { + u16 name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE]; + u8 if_type; + u32 hw_address_size; + struct efi_mac_address hw_address; + struct efi_ipv4_address station_address; + struct efi_ipv4_address subnet_mask; + u32 route_table_size; + struct efi_ip4_route_table *route_table; +}; + +enum efi_ip4_config2_policy { + EFI_IP4_CONFIG2_POLICY_STATIC, + EFI_IP4_CONFIG2_POLICY_DHCP, + EFI_IP4_CONFIG2_POLICY_MAX +}; + +struct efi_ip4_config2_manual_address { + struct efi_ipv4_address address; + struct efi_ipv4_address subnet_mask; +}; + +#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \ + EFI_GUID(0xbdc8e6af, 0xd9bc, 0x4379, \ + 0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c) + +struct efi_service_binding_protocol { + efi_status_t (EFIAPI * create_child)(struct efi_service_binding_protocol *this, + efi_handle_t *child_handle); + efi_status_t (EFIAPI * destroy_child)(struct efi_service_binding_protocol *this, + efi_handle_t child_handle); +}; + +#define EFI_HTTP_PROTOCOL_GUID \ + EFI_GUID(0x7A59B29B, 0x910B, 0x4171, \ + 0x82, 0x42, 0xA8, 0x5A, 0x0D, 0xF2, 0x5B, 0x5B) + +enum efi_http_version { + HTTPVERSION10, + HTTPVERSION11, + HTTPVERSIONUNSUPPORTED +}; + +struct efi_httpv4_access_point { + bool use_default_address; + struct efi_ipv4_address local_address; + struct efi_ipv4_address local_subnet; + u16 local_port; +}; + +union efi_http_access_point { + struct efi_httpv4_access_point *ipv4_node; + struct efi_httpv6_access_point *ipv6_node; +}; + +struct efi_http_config_data { + enum efi_http_version http_version; + u32 timeout; + bool is_ipv6; + union efi_http_access_point access_point; +}; + +enum efi_http_method { + HTTP_METHOD_GET, + HTTP_METHOD_POST, + HTTP_METHOD_PATCH, + HTTP_METHOD_OPTIONS, + HTTP_METHOD_CONNECT, + HTTP_METHOD_HEAD, + HTTP_METHOD_PUT, + HTTP_METHOD_DELETE, + HTTP_METHOD_TRACE, + HTTP_METHOD_MAX +}; + +enum efi_http_status_code { + HTTP_STATUS_UNSUPPORTED_STATUS = 0, + HTTP_STATUS_100_CONTINUE, + HTTP_STATUS_101_SWITCHING_PROTOCOLS, + HTTP_STATUS_200_OK, + HTTP_STATUS_201_CREATED, + HTTP_STATUS_202_ACCEPTED, + HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION, + HTTP_STATUS_204_NO_CONTENT, + HTTP_STATUS_205_RESET_CONTENT, + HTTP_STATUS_206_PARTIAL_CONTENT, + HTTP_STATUS_300_MULTIPLE_CHOICES, + HTTP_STATUS_301_MOVED_PERMANENTLY, + HTTP_STATUS_302_FOUND, + HTTP_STATUS_303_SEE_OTHER, + HTTP_STATUS_304_NOT_MODIFIED, + HTTP_STATUS_305_USE_PROXY, + HTTP_STATUS_307_TEMPORARY_REDIRECT, + HTTP_STATUS_400_BAD_REQUEST, + HTTP_STATUS_401_UNAUTHORIZED, + HTTP_STATUS_402_PAYMENT_REQUIRED, + HTTP_STATUS_403_FORBIDDEN, + HTTP_STATUS_404_NOT_FOUND, + HTTP_STATUS_405_METHOD_NOT_ALLOWED, + HTTP_STATUS_406_NOT_ACCEPTABLE, + HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED, + HTTP_STATUS_408_REQUEST_TIME_OUT, + HTTP_STATUS_409_CONFLICT, + HTTP_STATUS_410_GONE, + HTTP_STATUS_411_LENGTH_REQUIRED, + HTTP_STATUS_412_PRECONDITION_FAILED, + HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE, + HTTP_STATUS_414_REQUEST_URI_TOO_LARGE, + HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE, + HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED, + HTTP_STATUS_417_EXPECTATION_FAILED, + HTTP_STATUS_500_INTERNAL_SERVER_ERROR, + HTTP_STATUS_501_NOT_IMPLEMENTED, + HTTP_STATUS_502_BAD_GATEWAY, + HTTP_STATUS_503_SERVICE_UNAVAILABLE, + HTTP_STATUS_504_GATEWAY_TIME_OUT, + HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED, + HTTP_STATUS_308_PERMANENT_REDIRECT +}; + +struct efi_http_request_data { + enum efi_http_method method; + u16 *url; +}; + +struct efi_http_response_data { + enum efi_http_status_code status_code; +}; + +struct efi_http_header { + char *field_name; + char *field_value; +}; + +struct efi_http_message { + union { + struct efi_http_request_data *request; + struct efi_http_response_data *response; + } data; + efi_uintn_t header_count; + struct efi_http_header *headers; + efi_uintn_t body_length; + void *body; +}; + +struct efi_http_token { + struct efi_event *event; + efi_status_t status; + struct efi_http_message *message; +}; + +struct efi_http_protocol { + efi_status_t (EFIAPI * get_mode_data)(struct efi_http_protocol *this, + struct efi_http_config_data *data); + efi_status_t (EFIAPI * configure)(struct efi_http_protocol *this, + struct efi_http_config_data *data); + efi_status_t (EFIAPI * request)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * cancel)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * response)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * poll)(struct efi_http_protocol *this); +}; + #define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \ EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) -- cgit v1.3.1 From b20f497f22a76785f4c615af78a5b70f6ba49046 Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:21 -0300 Subject: efi_loader: efi_net: add efi_net_set_addr, efi_net_get_addr Add the functions efi_net_set_addr and efi_net_get_addr to set and get the ip address from efi code in a network agnostic way. This could also go in net_common, or be compiled conditionally for each network stack. Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt --- include/efi_loader.h | 16 ++++++ lib/efi_loader/efi_net.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 39809eac1bc..612bc42816b 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -125,6 +125,22 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, size_t buffer_size) { } #endif +#if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER) +void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw); +void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw); +#else +static inline void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) { } +static inline void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) { } +#endif + /* Maximum number of configuration tables */ #define EFI_MAX_CONFIGURATION_TABLES 16 diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 7cd536705f4..3491d4c4818 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -17,6 +17,7 @@ #include #include +#include #include static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID; @@ -997,3 +998,127 @@ out_of_resources: printf("ERROR: Out of memory\n"); return EFI_OUT_OF_RESOURCES; } + +/** + * efi_net_get_addr() - get IP address information + * + * Copy the current IP address, mask, and gateway into the + * efi_ipv4_address structs pointed to by ip, mask and gw, + * respectively. + * + * @ip: pointer to an efi_ipv4_address struct to + * be filled with the current IP address + * @mask: pointer to an efi_ipv4_address struct to + * be filled with the current network mask + * @gw: pointer to an efi_ipv4_address struct to be + * filled with the current network gateway + */ +void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) +{ +#ifdef CONFIG_NET_LWIP + char ipstr[] = "ipaddr\0\0"; + char maskstr[] = "netmask\0\0"; + char gwstr[] = "gatewayip\0\0"; + int idx; + struct in_addr tmp; + char *env; + + idx = dev_seq(eth_get_dev()); + + if (idx < 0 || idx > 99) { + log_err("unexpected idx %d\n", idx); + return; + } + + if (idx) { + sprintf(ipstr, "ipaddr%d", idx); + sprintf(maskstr, "netmask%d", idx); + sprintf(gwstr, "gatewayip%d", idx); + } + + env = env_get(ipstr); + if (env && ip) { + tmp = string_to_ip(env); + memcpy(ip, &tmp, sizeof(tmp)); + } + + env = env_get(maskstr); + if (env && mask) { + tmp = string_to_ip(env); + memcpy(mask, &tmp, sizeof(tmp)); + } + env = env_get(gwstr); + if (env && gw) { + tmp = string_to_ip(env); + memcpy(gw, &tmp, sizeof(tmp)); + } +#else + if (ip) + memcpy(ip, &net_ip, sizeof(net_ip)); + if (mask) + memcpy(mask, &net_netmask, sizeof(net_netmask)); +#endif +} + +/** + * efi_net_set_addr() - set IP address information + * + * Set the current IP address, mask, and gateway to the + * efi_ipv4_address structs pointed to by ip, mask and gw, + * respectively. + * + * @ip: pointer to new IP address + * @mask: pointer to new network mask to set + * @gw: pointer to new network gateway + */ +void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) +{ +#ifdef CONFIG_NET_LWIP + char ipstr[] = "ipaddr\0\0"; + char maskstr[] = "netmask\0\0"; + char gwstr[] = "gatewayip\0\0"; + int idx; + struct in_addr *addr; + char tmp[46]; + + idx = dev_seq(eth_get_dev()); + + if (idx < 0 || idx > 99) { + log_err("unexpected idx %d\n", idx); + return; + } + + if (idx) { + sprintf(ipstr, "ipaddr%d", idx); + sprintf(maskstr, "netmask%d", idx); + sprintf(gwstr, "gatewayip%d", idx); + } + + if (ip) { + addr = (struct in_addr *)ip; + ip_to_string(*addr, tmp); + env_set(ipstr, tmp); + } + + if (mask) { + addr = (struct in_addr *)mask; + ip_to_string(*addr, tmp); + env_set(maskstr, tmp); + } + + if (gw) { + addr = (struct in_addr *)gw; + ip_to_string(*addr, tmp); + env_set(gwstr, tmp); + } +#else + if (ip) + memcpy(&net_ip, ip, sizeof(*ip)); + if (mask) + memcpy(&net_netmask, mask, sizeof(*mask)); +#endif +} -- cgit v1.3.1 From 4b0723004b65bfaab528ce3aa669eb552e06130a Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:22 -0300 Subject: efi_loader: device_path: add support for HTTP device path Add efi_dp_from_http to form a device path from HTTP. The device path is the concatenation of the device path returned by efi_dp_from_ipv4 together with an URI node and an END node. Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- include/efi_loader.h | 1 + lib/efi_loader/efi_device_path.c | 64 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 612bc42816b..96b204dfc31 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -872,6 +872,7 @@ struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp, const char *path); struct efi_device_path *efi_dp_from_eth(void); +struct efi_device_path *efi_dp_from_http(const char *server); struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, uint64_t start_address, size_t size); diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 6fcbc91e0ba..a6d43006869 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -1021,6 +1021,70 @@ static struct efi_device_path *efi_dp_from_ipv4(struct efi_ipv4_address *ip, return dp2; } +/** + * efi_dp_from_http() - set device path from http + * + * Set the device path to an IPv4 path as provided by efi_dp_from_ipv4 + * concatenated with a device path of subtype DEVICE_PATH_SUB_TYPE_MSG_URI, + * and an END node. + * + * @server: URI of remote server + * Return: pointer to HTTP device path, NULL on error + */ +struct efi_device_path *efi_dp_from_http(const char *server) +{ + struct efi_device_path *dp1, *dp2; + struct efi_device_path_uri *uridp; + efi_uintn_t uridp_len; + char *pos; + char tmp[128]; + struct efi_ipv4_address ip; + struct efi_ipv4_address mask; + + if ((server && strlen("http://") + strlen(server) + 1 > sizeof(tmp)) || + (!server && IS_ENABLED(CONFIG_NET_LWIP))) + return NULL; + + efi_net_get_addr(&ip, &mask, NULL); + + dp1 = efi_dp_from_ipv4(&ip, &mask, NULL); + if (!dp1) + return NULL; + + strcpy(tmp, "http://"); + + if (server) { + strlcat(tmp, server, sizeof(tmp)); +#if !IS_ENABLED(CONFIG_NET_LWIP) + } + else { + ip_to_string(net_server_ip, tmp + strlen("http://")); +#endif + } + + uridp_len = sizeof(struct efi_device_path) + strlen(tmp) + 1; + uridp = efi_alloc(uridp_len + sizeof(END)); + if (!uridp) { + log_err("Out of memory\n"); + return NULL; + } + uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI; + uridp->dp.length = uridp_len; + debug("device path: setting uri device path to %s\n", tmp); + memcpy(uridp->uri, tmp, strlen(tmp) + 1); + + pos = (char *)uridp + uridp_len; + memcpy(pos, &END, sizeof(END)); + + dp2 = efi_dp_concat(dp1, (const struct efi_device_path *)uridp, 0); + + efi_free_pool(uridp); + efi_free_pool(dp1); + + return dp2; +} + /* Construct a device-path for memory-mapped image */ struct efi_device_path *efi_dp_from_mem(uint32_t memory_type, uint64_t start_address, -- cgit v1.3.1 From e55a4acb54e807c6411c4f6ab914fa2b3f55784e Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:23 -0300 Subject: efi_loader: net: set EFI bootdevice device path to HTTP when loaded from wget Set the device path of the efi boot device to an HTTP device path (as formed by efi_dp_from_http) when the next boot stage is loaded using wget (i.e., when wget is used with wget_info.set_bootdev=1). When loaded from HTTP, the device path should account for it so that the next boot stage is aware (e.g. grub only loads its http stack if it itself was loaded from http, and it checks this from its device path). Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt --- include/efi_loader.h | 5 ++++ lib/efi_loader/efi_bootbin.c | 42 ++++++++++++++++++------------ lib/efi_loader/efi_device_path.c | 5 ++-- lib/efi_loader/efi_net.c | 55 +++++++++++++++++++++++++++++++++++++++- net/lwip/wget.c | 5 ++-- net/wget.c | 2 +- 6 files changed, 91 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 96b204dfc31..0da0248db46 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -126,6 +126,10 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, #endif #if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER) +/* Call this to update the current device path of the efi net device */ +efi_status_t efi_net_set_dp(const char *dev, const char *server); +/* Call this to get the current device path of the efi net device */ +void efi_net_get_dp(struct efi_device_path **dp); void efi_net_get_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, struct efi_ipv4_address *gw); @@ -133,6 +137,7 @@ void efi_net_set_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, struct efi_ipv4_address *gw); #else +static inline void efi_net_get_dp(struct efi_device_path **dp) { } static inline void efi_net_get_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, struct efi_ipv4_address *gw) { } diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c index a87006b3c0e..b677bbc3124 100644 --- a/lib/efi_loader/efi_bootbin.c +++ b/lib/efi_loader/efi_bootbin.c @@ -93,24 +93,34 @@ void efi_set_bootdev(const char *dev, const char *devnr, const char *path, image_addr = buffer; image_size = buffer_size; +#if IS_ENABLED(CONFIG_NETDEVICES) + if (!strcmp(dev, "Net") || !strcmp(dev, "Http")) { + ret = efi_net_set_dp(dev, devnr); + if (ret != EFI_SUCCESS) + goto error; + } +#endif + ret = efi_dp_from_name(dev, devnr, path, &device, &image); - if (ret == EFI_SUCCESS) { - bootefi_device_path = device; - if (image) { - /* FIXME: image should not contain device */ - struct efi_device_path *image_tmp = image; - - efi_dp_split_file_path(image, &device, &image); - efi_free_pool(image_tmp); - } - bootefi_image_path = image; - log_debug("- boot device %pD\n", device); - if (image) - log_debug("- image %pD\n", image); - } else { - log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); - efi_clear_bootdev(); + if (ret != EFI_SUCCESS) + goto error; + + bootefi_device_path = device; + if (image) { + /* FIXME: image should not contain device */ + struct efi_device_path *image_tmp = image; + + efi_dp_split_file_path(image, &device, &image); + efi_free_pool(image_tmp); } + bootefi_image_path = image; + log_debug("- boot device %pD\n", device); + if (image) + log_debug("- image %pD\n", image); + return; +error: + log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); + efi_clear_bootdev(); } /** diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index a6d43006869..5eae6fd39cc 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -1185,8 +1185,9 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, (uintptr_t)image_addr, image_size); - } else if (IS_ENABLED(CONFIG_NETDEVICES) && !strcmp(dev, "Net")) { - dp = efi_dp_from_eth(); + } else if (IS_ENABLED(CONFIG_NETDEVICES) && + (!strcmp(dev, "Net") || !strcmp(dev, "Http"))) { + efi_net_get_dp(&dp); } else if (!strcmp(dev, "Uart")) { dp = efi_dp_from_uart(); } else { diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 3491d4c4818..e8af2e3d95e 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -32,6 +33,13 @@ static int rx_packet_idx; static int rx_packet_num; static struct efi_net_obj *netobj; +/* + * The current network device path. This device path is updated when a new + * bootfile is downloaded from the network. If then the bootfile is loaded + * as an efi image, net_dp is passed as the device path of the loaded image. + */ +static struct efi_device_path *net_dp; + /* * The notification function of this event is called in every timer cycle * to check if a new network packet has been received. @@ -902,8 +910,10 @@ efi_status_t efi_net_register(void) &netobj->net); if (r != EFI_SUCCESS) goto failure_to_add_protocol; + if (!net_dp) + efi_net_set_dp("Net", NULL); r = efi_add_protocol(&netobj->header, &efi_guid_device_path, - efi_dp_from_eth()); + net_dp); if (r != EFI_SUCCESS) goto failure_to_add_protocol; r = efi_add_protocol(&netobj->header, &efi_pxe_base_code_protocol_guid, @@ -999,6 +1009,49 @@ out_of_resources: return EFI_OUT_OF_RESOURCES; } +/** + * efi_net_set_dp() - set device path of efi net device + * + * This gets called to update the device path when a new boot + * file is downloaded + * + * @dev: dev to set the device path from + * @server: remote server address + * Return: status code + */ +efi_status_t efi_net_set_dp(const char *dev, const char *server) +{ + efi_free_pool(net_dp); + + net_dp = NULL; + if (!strcmp(dev, "Net")) + net_dp = efi_dp_from_eth(); + else if (!strcmp(dev, "Http")) + net_dp = efi_dp_from_http(server); + + if (!net_dp) + return EFI_OUT_OF_RESOURCES; + + return EFI_SUCCESS; +} + +/** + * efi_net_get_dp() - get device path of efi net device + * + * Produce a copy of the current device path + * + * @dp: copy of the current device path, or NULL on error + */ +void efi_net_get_dp(struct efi_device_path **dp) +{ + if (!dp) + return; + if (!net_dp) + efi_net_set_dp("Net", NULL); + if (net_dp) + *dp = efi_dp_dup(net_dp); +} + /** * efi_net_get_addr() - get IP address information * diff --git a/net/lwip/wget.c b/net/lwip/wget.c index 669eded0f38..c23f0640ec6 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -260,10 +260,9 @@ static void httpc_result_cb(void *arg, httpc_result_t httpc_result, printf("%u bytes transferred in %lu ms (", rx_content_len, elapsed); print_size(rx_content_len / elapsed * 1000, "/s)\n"); printf("Bytes transferred = %lu (%lx hex)\n", ctx->size, ctx->size); - if (wget_info->set_bootdev) { - efi_set_bootdev("Net", "", ctx->path, map_sysmem(ctx->saved_daddr, 0), + if (wget_info->set_bootdev) + efi_set_bootdev("Http", ctx->server_name, ctx->path, map_sysmem(ctx->saved_daddr, 0), rx_content_len); - } wget_lwip_set_file_size(rx_content_len); if (env_set_hex("filesize", rx_content_len) || env_set_hex("fileaddr", ctx->saved_daddr)) { diff --git a/net/wget.c b/net/wget.c index f3b43b06b8b..d338eaf4ef3 100644 --- a/net/wget.c +++ b/net/wget.c @@ -447,7 +447,7 @@ static void wget_handler(uchar *pkt, u16 dport, net_set_state(wget_loop_state); wget_info->file_size = net_boot_file_size; if (wget_info->method == WGET_HTTP_METHOD_GET && wget_info->set_bootdev) { - efi_set_bootdev("Net", "", image_url, + efi_set_bootdev("Http", NULL, image_url, map_sysmem(image_load_addr, 0), net_boot_file_size); env_set_hex("filesize", net_boot_file_size); -- cgit v1.3.1 From 5a5c5bf40a0ea479426ad3f5c0cbc5afa675786f Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:24 -0300 Subject: efi_loader: net: add support to send http requests and parse http headers Add network-stack agnostic way to send an http request and parse http headers from efi drivers. This uses wget as a backend and communicates with it via efi_wget_info. The function efi_net_do_request allocates a buffer on behalf of an efi application using efi_alloc and passes it to wget to receive the data. If the method is GET and the buffer is too small, it re-allocates the buffer based on the last received Content-Length header and tries again. If the method is HEAD it just issues one request. So issuing a HEAD request (to update Content-Length) and then a GET request is preferred but not required. The function efi_net_parse_headers parses a raw buffer containing an http header into an array of EFI specific 'http_header' structs. Signed-off-by: Adriano Cordova Reviewed-by: Heinrich Schuchardt --- include/efi_loader.h | 13 ++++ lib/efi_loader/efi_net.c | 155 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 0da0248db46..b6f865ca769 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -16,6 +16,7 @@ #include #include #include +#include #include struct blk_desc; @@ -136,6 +137,18 @@ void efi_net_get_addr(struct efi_ipv4_address *ip, void efi_net_set_addr(struct efi_ipv4_address *ip, struct efi_ipv4_address *mask, struct efi_ipv4_address *gw); +efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, + u32 *status_code, ulong *file_size, char *headers_buffer); +#define MAX_HTTP_HEADERS_SIZE SZ_64K +#define MAX_HTTP_HEADERS 100 +#define MAX_HTTP_HEADER_NAME 128 +#define MAX_HTTP_HEADER_VALUE 512 +struct http_header { + uchar name[MAX_HTTP_HEADER_NAME]; + uchar value[MAX_HTTP_HEADER_VALUE]; +}; + +void efi_net_parse_headers(ulong *num_headers, struct http_header *headers); #else static inline void efi_net_get_dp(struct efi_device_path **dp) { } static inline void efi_net_get_addr(struct efi_ipv4_address *ip, diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index e8af2e3d95e..368f62c5b2d 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -40,6 +41,12 @@ static struct efi_net_obj *netobj; */ static struct efi_device_path *net_dp; +static struct wget_http_info efi_wget_info = { + .set_bootdev = false, + .check_buffer_size = true, + +}; + /* * The notification function of this event is called in every timer cycle * to check if a new network packet has been received. @@ -1175,3 +1182,151 @@ void efi_net_set_addr(struct efi_ipv4_address *ip, memcpy(&net_netmask, mask, sizeof(*mask)); #endif } + +/** + * efi_net_set_buffer() - allocate a buffer of min 64K + * + * @buffer: allocated buffer + * @size: desired buffer size + * Return: status code + */ +static efi_status_t efi_net_set_buffer(void **buffer, size_t size) +{ + efi_status_t ret = EFI_SUCCESS; + + if (size < SZ_64K) + size = SZ_64K; + + efi_free_pool(*buffer); + + *buffer = efi_alloc(size); + if (!*buffer) + ret = EFI_OUT_OF_RESOURCES; + + efi_wget_info.buffer_size = (ulong)size; + + return ret; +} + +/** + * efi_net_parse_headers() - parse HTTP headers + * + * Parses the raw buffer efi_wget_info.headers into an array headers + * of efi structs http_headers. The array should be at least + * MAX_HTTP_HEADERS long. + * + * @num_headers: number of headers + * @headers: caller provided array of struct http_headers + */ +void efi_net_parse_headers(ulong *num_headers, struct http_header *headers) +{ + if (!num_headers || !headers) + return; + + // Populate info with http headers. + *num_headers = 0; + const uchar *line_start = efi_wget_info.headers; + const uchar *line_end; + ulong count; + struct http_header *current_header; + const uchar *separator; + size_t name_length, value_length; + + // Skip the first line (request or status line) + line_end = strstr(line_start, "\r\n"); + + if (line_end) + line_start = line_end + 2; + + while ((line_end = strstr(line_start, "\r\n")) != NULL) { + count = *num_headers; + if (line_start == line_end || count >= MAX_HTTP_HEADERS) + break; + current_header = headers + count; + separator = strchr(line_start, ':'); + if (separator) { + name_length = separator - line_start; + ++separator; + while (*separator == ' ') + ++separator; + value_length = line_end - separator; + if (name_length < MAX_HTTP_HEADER_NAME && + value_length < MAX_HTTP_HEADER_VALUE) { + strncpy(current_header->name, line_start, name_length); + current_header->name[name_length] = '\0'; + strncpy(current_header->value, separator, value_length); + current_header->value[value_length] = '\0'; + (*num_headers)++; + } + } + line_start = line_end + 2; + } +} + +/** + * efi_net_do_request() - issue an HTTP request using wget + * + * @url: url + * @method: HTTP method + * @buffer: data buffer + * @status_code: HTTP status code + * @file_size: file size in bytes + * @headers_buffer: headers buffer + * Return: status code + */ +efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, + u32 *status_code, ulong *file_size, char *headers_buffer) +{ + efi_status_t ret = EFI_SUCCESS; + int wget_ret; + static bool last_head; + + if (!buffer || !file_size) + return EFI_ABORTED; + + efi_wget_info.method = (enum wget_http_method)method; + efi_wget_info.headers = headers_buffer; + + switch (method) { + case HTTP_METHOD_GET: + ret = efi_net_set_buffer(buffer, last_head ? (size_t)efi_wget_info.hdr_cont_len : 0); + if (ret != EFI_SUCCESS) + goto out; + wget_ret = wget_request((ulong)*buffer, url, &efi_wget_info); + if ((ulong)efi_wget_info.hdr_cont_len > efi_wget_info.buffer_size) { + // Try again with updated buffer size + ret = efi_net_set_buffer(buffer, (size_t)efi_wget_info.hdr_cont_len); + if (ret != EFI_SUCCESS) + goto out; + if (wget_request((ulong)*buffer, url, &efi_wget_info)) { + efi_free_pool(*buffer); + ret = EFI_DEVICE_ERROR; + goto out; + } + } else if (wget_ret) { + efi_free_pool(*buffer); + ret = EFI_DEVICE_ERROR; + goto out; + } + // Pass the actual number of received bytes to the application + *file_size = efi_wget_info.file_size; + *status_code = efi_wget_info.status_code; + last_head = false; + break; + case HTTP_METHOD_HEAD: + ret = efi_net_set_buffer(buffer, 0); + if (ret != EFI_SUCCESS) + goto out; + wget_request((ulong)*buffer, url, &efi_wget_info); + *file_size = 0; + *status_code = efi_wget_info.status_code; + last_head = true; + break; + default: + ret = EFI_UNSUPPORTED; + break; + } + +out: + return ret; +} -- cgit v1.3.1 From 929363cbb35ef9943f9c02938dc23d2c78582c5f Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:25 -0300 Subject: efi_loader: efi_net: add EFI_IP4_CONFIG2_PROTOCOL Add an implementation of the EFI_IP4_CONFIG2_PROTOCOL. The protocol is attached to the handle of the efi network device. This is the same handle where snp and pxe are attached to. Signed-off-by: Adriano Cordova --- include/efi_loader.h | 3 + lib/efi_loader/Kconfig | 9 ++ lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_ipconfig.c | 214 ++++++++++++++++++++++++++++++++++++++++++ lib/efi_loader/efi_net.c | 20 +++- 5 files changed, 242 insertions(+), 5 deletions(-) create mode 100644 lib/efi_loader/efi_ipconfig.c (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index b6f865ca769..9be09a799ba 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -626,6 +626,9 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ efi_status_t efi_net_register(void); +/* Called by efi_net_register to make the ip4 config2 protocol available */ +efi_status_t efi_ipconfig_register(const efi_handle_t handle, + struct efi_ip4_config2_protocol *ip4config); /* Called by bootefi to make the watchdog available */ efi_status_t efi_watchdog_register(void); efi_status_t efi_initrd_register(void); diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index d93f28b8422..0b932df85c5 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -476,6 +476,15 @@ config EFI_RISCV_BOOT_PROTOCOL replace the transfer via the device-tree. The latter is not possible on systems using ACPI. +config EFI_IP4_CONFIG2_PROTOCOL + bool "EFI_IP4_CONFIG2_PROTOCOL support" + default y if ARCH_QEMU || SANDBOX + depends on NET || NET_LWIP + help + Provides an implementation of the EFI_IP4_CONFIG2_PROTOCOL, this + protocol can be used to set and get the current ip address and + other network information. + endmenu menu "Misc options" diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 87131ab911d..30cd1de9d60 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_EFI_ESRT) += efi_esrt.o obj-$(CONFIG_VIDEO) += efi_gop.o obj-$(CONFIG_BLK) += efi_disk.o obj-$(CONFIG_NETDEVICES) += efi_net.o +obj-$(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) += efi_ipconfig.o obj-$(CONFIG_ACPI) += efi_acpi.o obj-$(CONFIG_SMBIOS) += efi_smbios.o obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o diff --git a/lib/efi_loader/efi_ipconfig.c b/lib/efi_loader/efi_ipconfig.c new file mode 100644 index 00000000000..0b247a4c028 --- /dev/null +++ b/lib/efi_loader/efi_ipconfig.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Implementation of EFI_IP4_CONFIG2_PROTOCOL + * + */ + +#include +#include +#include +#include +#include + +static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID; + +struct efi_ip4_config2_manual_address current_http_ip; +static enum efi_ip4_config2_policy current_policy; +static char current_mac_addr[32]; + +/* EFI_IP4_CONFIG2_PROTOCOL */ + +/* + * efi_ip4_config2_set_data() - Set the configuration for the EFI IPv4 network + * stack running on the communication device + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.SetData() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to set + * @data_size: size of the buffer pointed to by data in bytes + * @data: the data buffer to set + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_set_data(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t data_size, + void *data) +{ + EFI_ENTRY("%p, %d, %zu, %p", this, data_type, data_size, data); + efi_status_t ret = EFI_SUCCESS; + + if (!this || (data && !data_size) || (!data && data_size)) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + switch (data_type) { + case EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO: + return EFI_EXIT(EFI_WRITE_PROTECTED); + case EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS: + if (current_policy != EFI_IP4_CONFIG2_POLICY_STATIC) + return EFI_EXIT(EFI_WRITE_PROTECTED); + if (!data_size && !data) { + memset((void *)¤t_http_ip, 0, + sizeof(current_http_ip)); + return EFI_EXIT(EFI_SUCCESS); + } + if (data && data_size == sizeof(struct efi_ip4_config2_manual_address)) { + memcpy((void *)¤t_http_ip, data, + sizeof(struct efi_ip4_config2_manual_address)); + efi_net_set_addr(¤t_http_ip.address, + ¤t_http_ip.subnet_mask, NULL); + return EFI_EXIT(EFI_SUCCESS); + } + return EFI_EXIT(EFI_BAD_BUFFER_SIZE); + case EFI_IP4_CONFIG2_DATA_TYPE_POLICY: + if (data && data_size == sizeof(enum efi_ip4_config2_policy)) { + current_policy = *(enum efi_ip4_config2_policy *)data; + return EFI_EXIT(EFI_SUCCESS); + } + return EFI_EXIT(EFI_BAD_BUFFER_SIZE); + + default: + return EFI_EXIT(EFI_UNSUPPORTED); + } + + return EFI_EXIT(ret); +} + +/* + * efi_ip4_config2_get_data() - Get the configuration for the EFI IPv4 network + * stack running on the communication device + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.GetData() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to get + * @data_size: size + * @data: the data buffer + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_get_data(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t *data_size, + void *data) +{ + EFI_ENTRY("%p, %d, %p, %p", this, data_type, data_size, data); + + efi_status_t ret = EFI_SUCCESS; + struct efi_ip4_config2_interface_info *info; + int tmp; + + if (!this || !data_size) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + if (*data_size && !data) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + tmp = sizeof(struct efi_ip4_config2_interface_info) + sizeof(struct efi_ip4_route_table); + + switch (data_type) { + case EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO: + if (*data_size < tmp) { + *data_size = tmp; + return EFI_EXIT(EFI_BUFFER_TOO_SMALL); + } + + info = (struct efi_ip4_config2_interface_info *)data; + memset(info, 0, sizeof(*info)); + + info->hw_address_size = 6; + memcpy(info->hw_address.mac_addr, current_mac_addr, 6); + // Set the route table size + + info->route_table_size = 0; + break; + case EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS: + if (*data_size < sizeof(struct efi_ip4_config2_manual_address)) { + *data_size = sizeof(struct efi_ip4_config2_manual_address); + return EFI_EXIT(EFI_BUFFER_TOO_SMALL); + } + + efi_net_get_addr(¤t_http_ip.address, ¤t_http_ip.subnet_mask, NULL); + memcpy(data, (void *)¤t_http_ip, + sizeof(struct efi_ip4_config2_manual_address)); + + break; + default: + return EFI_EXIT(EFI_NOT_FOUND); + } + return EFI_EXIT(ret); +} + +/* + * efi_ip4_config2_register_notify() - Register an event that is to be signaled whenever + * a configuration process on the specified configuration + * data is done + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.RegisterDataNotify() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to register the event for + * @event: the event to register + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_register_notify(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event) +{ + EFI_ENTRY("%p, %d, %p", this, data_type, event); + + return EFI_EXIT(EFI_UNSUPPORTED); +} + +/* + * efi_ip4_config2_unregister_notify() - Remove a previously registered eventfor + * the specified configuration data + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.UnregisterDataNotify() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to remove the event for + * @event: the event to unregister + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_unregister_notify(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event) +{ + EFI_ENTRY("%p, %d, %p", this, data_type, event); + + return EFI_EXIT(EFI_UNSUPPORTED); +} + +/** + * efi_ipconfig_register() - register the ip4_config2 protocol + * + */ +efi_status_t efi_ipconfig_register(const efi_handle_t handle, + struct efi_ip4_config2_protocol *ip4config) +{ + efi_status_t r = EFI_SUCCESS; + + r = efi_add_protocol(handle, &efi_ip4_config2_guid, + ip4config); + if (r != EFI_SUCCESS) { + log_err("ERROR: Failure to add protocol\n"); + return r; + } + + memcpy(current_mac_addr, eth_get_ethaddr(), 6); + + ip4config->set_data = efi_ip4_config2_set_data; + ip4config->get_data = efi_ip4_config2_get_data; + ip4config->register_data_notify = efi_ip4_config2_register_notify; + ip4config->unregister_data_notify = efi_ip4_config2_unregister_notify; + + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 368f62c5b2d..916c15999e2 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -60,11 +60,12 @@ static struct efi_event *wait_for_packet; /** * struct efi_net_obj - EFI object representing a network interface * - * @header: EFI object header - * @net: simple network protocol interface - * @net_mode: status of the network interface - * @pxe: PXE base code protocol interface - * @pxe_mode: status of the PXE base code protocol + * @header: EFI object header + * @net: simple network protocol interface + * @net_mode: status of the network interface + * @pxe: PXE base code protocol interface + * @pxe_mode: status of the PXE base code protocol + * @ip4_config2: IP4 Config2 protocol interface */ struct efi_net_obj { struct efi_object header; @@ -72,6 +73,9 @@ struct efi_net_obj { struct efi_simple_network_mode net_mode; struct efi_pxe_base_code_protocol pxe; struct efi_pxe_mode pxe_mode; +#if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) + struct efi_ip4_config2_protocol ip4_config2; +#endif }; /* @@ -999,6 +1003,12 @@ efi_status_t efi_net_register(void) return r; } +#if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) + r = efi_ipconfig_register(&netobj->header, &netobj->ip4_config2); + if (r != EFI_SUCCESS) + goto failure_to_add_protocol; +#endif + return EFI_SUCCESS; failure_to_add_protocol: printf("ERROR: Failure to add protocol\n"); -- cgit v1.3.1 From 238e0269d82f9662b27cd040e32c3543ccf3380f Mon Sep 17 00:00:00 2001 From: Adriano Cordova Date: Wed, 4 Dec 2024 00:05:26 -0300 Subject: efi_loader: efi_net: add EFI_HTTP_PROTOCOL Add an EFI HTTP driver. This commit implements the EFI_HTTP_PROTOCOL and the EFI_HTTP_SERVICE_BINDING_PROTOCOL. The latter is attached to the handle of th efi network device. This is the same handle where snp, pxe, and ipconfig are attached to. Signed-off-by: Adriano Cordova --- include/efi_loader.h | 3 + lib/efi_loader/Kconfig | 8 + lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_http.c | 548 ++++++++++++++++++++++++++++++++++++++++++++++ lib/efi_loader/efi_net.c | 20 +- 5 files changed, 578 insertions(+), 2 deletions(-) create mode 100644 lib/efi_loader/efi_http.c (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 9be09a799ba..9afbec35ebf 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -629,6 +629,9 @@ efi_status_t efi_net_register(void); /* Called by efi_net_register to make the ip4 config2 protocol available */ efi_status_t efi_ipconfig_register(const efi_handle_t handle, struct efi_ip4_config2_protocol *ip4config); +/* Called by efi_net_register to make the http protocol available */ +efi_status_t efi_http_register(const efi_handle_t handle, + struct efi_service_binding_protocol *http_service_binding); /* Called by bootefi to make the watchdog available */ efi_status_t efi_watchdog_register(void); efi_status_t efi_initrd_register(void); diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 0b932df85c5..5c73457d9b9 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -485,6 +485,14 @@ config EFI_IP4_CONFIG2_PROTOCOL protocol can be used to set and get the current ip address and other network information. +config EFI_HTTP_PROTOCOL + bool "EFI_HTTP_PROTOCOL support" + default y if ARCH_QEMU || SANDBOX + depends on WGET + help + Provides an EFI HTTP driver implementing the EFI_HTTP_PROTOCOL. and + EFI_HTTP_SERVICE_BINDING_PROTOCOL. + endmenu menu "Misc options" diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 30cd1de9d60..2a0b4172bd7 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_VIDEO) += efi_gop.o obj-$(CONFIG_BLK) += efi_disk.o obj-$(CONFIG_NETDEVICES) += efi_net.o obj-$(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) += efi_ipconfig.o +obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_http.o obj-$(CONFIG_ACPI) += efi_acpi.o obj-$(CONFIG_SMBIOS) += efi_smbios.o obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o diff --git a/lib/efi_loader/efi_http.c b/lib/efi_loader/efi_http.c new file mode 100644 index 00000000000..694e1993418 --- /dev/null +++ b/lib/efi_loader/efi_http.c @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * An HTTP driver + * + * HTTP_PROTOCOL + * HTTP_SERVICE_BINDING_PROTOCOL + * IP4_CONFIG2_PROTOCOL + */ + +#include +#include +#include +#include +#include +#include + +static const efi_guid_t efi_http_service_binding_guid = EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID; +static const efi_guid_t efi_http_guid = EFI_HTTP_PROTOCOL_GUID; + +/** + * struct efi_http_instance - EFI object representing an HTTP protocol instance + * + * @http: EFI_HTTP_PROTOCOL interface + * @handle: handle to efi object + * @configured: configuration status + * @http_load_addr: data buffer + * @file_size: size of data + * @current_offset: offset in data buffer + * @status_code: HTTP status code + * @num_headers: number of received headers + * @headers: array of headers + * @headers_buffer: raw buffer with headers + */ +struct efi_http_instance { + struct efi_http_protocol http; + efi_handle_t handle; + bool configured; + void *http_load_addr; + ulong file_size; + ulong current_offset; + u32 status_code; + ulong num_headers; + struct http_header headers[MAX_HTTP_HEADERS]; + char headers_buffer[MAX_HTTP_HEADERS_SIZE]; +}; + +static int num_instances; + +/* + * efi_u32_to_httpstatus() - convert u32 to status + * + */ +enum efi_http_status_code efi_u32_to_httpstatus(u32 status); + +/* + * efi_http_send_data() - sends data to client + * + * + * @client_buffer: client buffer to send data to + * @client_buffer_size: size of the client buffer + * @inst: HTTP instance for which to send data + * + * Return: status code + */ +static efi_status_t efi_http_send_data(void *client_buffer, + efi_uintn_t *client_buffer_size, + struct efi_http_instance *inst) +{ + efi_status_t ret = EFI_SUCCESS; + ulong total_size, transfer_size; + uchar *ptr; + + // Amount of data left; + total_size = inst->file_size; + transfer_size = total_size - inst->current_offset; + debug("efi_http: sending data to client, total size %lu\n", total_size); + // Amount of data the client is willing to receive + if (transfer_size > *client_buffer_size) + transfer_size = *client_buffer_size; + else + *client_buffer_size = transfer_size; + debug("efi_http: transfer size %lu\n", transfer_size); + if (!transfer_size) // Ok, only headers + goto out; + + if (!client_buffer) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + // Send data + ptr = (uchar *)inst->http_load_addr + inst->current_offset; + memcpy(client_buffer, ptr, transfer_size); + + inst->current_offset += transfer_size; + + // Whole file served, clean the buffer: + if (inst->current_offset == inst->file_size) { + efi_free_pool(inst->http_load_addr); + inst->http_load_addr = NULL; + inst->current_offset = 0; + inst->file_size = 0; + } + +out: + return ret; +} + +/* EFI_HTTP_PROTOCOL */ + +/* + * efi_http_get_mode_data() - Gets the current operational status. + * + * This function implements EFI_HTTP_PROTOCOL.GetModeData(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data: pointer to the buffer for operational parameters + * of this HTTP instance + * Return: status code + */ +static efi_status_t EFIAPI efi_http_get_mode_data(struct efi_http_protocol *this, + struct efi_http_config_data *data) +{ + EFI_ENTRY("%p, %p", this, data); + + efi_status_t ret = EFI_UNSUPPORTED; + + return EFI_EXIT(ret); +} + +/* + * efi_http_configure() - Initializes operational status for this + * EFI HTTP instance. + * + * This function implements EFI_HTTP_PROTOCOL.Configure(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data: pointer to the buffer for operational parameters of + * this HTTP instance + * Return: status code + */ +static efi_status_t EFIAPI efi_http_configure(struct efi_http_protocol *this, + struct efi_http_config_data *data) +{ + EFI_ENTRY("%p, %p", this, data); + + efi_status_t ret = EFI_SUCCESS; + enum efi_http_version http_version; + struct efi_httpv4_access_point *ipv4_node; + struct efi_http_instance *http_instance; + + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + http_instance = (struct efi_http_instance *)this; + + if (!data) { + efi_free_pool(http_instance->http_load_addr); + http_instance->http_load_addr = NULL; + http_instance->current_offset = 0; + http_instance->configured = false; + + goto out; + } + + if (http_instance->configured) { + ret = EFI_ALREADY_STARTED; + goto out; + } + + http_version = data->http_version; + ipv4_node = data->access_point.ipv4_node; + + if ((http_version != HTTPVERSION10 && + http_version != HTTPVERSION11) || + data->is_ipv6 || !ipv4_node) { /* Only support ipv4 */ + ret = EFI_UNSUPPORTED; + goto out; + } + + if (!ipv4_node->use_default_address) { + efi_net_set_addr((struct efi_ipv4_address *)&ipv4_node->local_address, + (struct efi_ipv4_address *)&ipv4_node->local_subnet, NULL); + } + + http_instance->current_offset = 0; + http_instance->configured = true; + +out: + return EFI_EXIT(ret); +} + +/* + * efi_http_request() - Queues an HTTP request to this HTTP instance + * + * This function implements EFI_HTTP_PROTOCOL.Request(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_request(struct efi_http_protocol *this, + struct efi_http_token *token) +{ + EFI_ENTRY("%p, %p", this, token); + + efi_status_t ret = EFI_SUCCESS; + u8 *tmp; + u8 url_8[1024]; + u16 *url_16; + enum efi_http_method current_method; + struct efi_http_instance *http_instance; + + if (!token || !this || !token->message || + !token->message->data.request) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + http_instance = (struct efi_http_instance *)this; + + if (!http_instance->configured) { + ret = EFI_NOT_STARTED; + goto out; + } + + current_method = token->message->data.request->method; + url_16 = token->message->data.request->url; + + /* Parse URL. It comes in UCS-2 encoding and follows RFC3986 */ + tmp = url_8; + utf16_utf8_strncpy((char **)&tmp, url_16, 1024); + + ret = efi_net_do_request(url_8, current_method, &http_instance->http_load_addr, + &http_instance->status_code, &http_instance->file_size, + http_instance->headers_buffer); + if (ret != EFI_SUCCESS) + goto out; + + // We have a successful request + efi_net_parse_headers(&http_instance->num_headers, http_instance->headers); + http_instance->current_offset = 0; + token->status = EFI_SUCCESS; + goto out_signal; + +out_signal: + efi_signal_event(token->event); +out: + return EFI_EXIT(ret); +} + +/* + * efi_http_cancel() - Abort an asynchronous HTTP request or response token + * + * This function implements EFI_HTTP_PROTOCOL.Cancel(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_cancel(struct efi_http_protocol *this, + struct efi_http_token *token) +{ + EFI_ENTRY("%p, %p", this, token); + + efi_status_t ret = EFI_UNSUPPORTED; + + return EFI_EXIT(ret); +} + +/* + * efi_http_response() - Queues an HTTP response to this HTTP instance + * + * This function implements EFI_HTTP_PROTOCOL.Response(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_response(struct efi_http_protocol *this, + struct efi_http_token *token) +{ + EFI_ENTRY("%p, %p", this, token); + + efi_status_t ret = EFI_SUCCESS; + struct efi_http_instance *http_instance; + struct efi_http_header **client_headers; + struct efi_http_response_data *response; + + if (!token || !this || !token->message) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + http_instance = (struct efi_http_instance *)this; + + // Set HTTP status code + if (token->message->data.response) { // TODO extra check, see spec. + response = token->message->data.response; + response->status_code = efi_u32_to_httpstatus(http_instance->status_code); + } + + client_headers = &token->message->headers; + + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + (http_instance->num_headers) * sizeof(struct efi_http_header), + (void **)client_headers); // This is deallocated by the client. + if (ret != EFI_SUCCESS) + goto out_bad_signal; + + // Send headers + token->message->header_count = http_instance->num_headers; + for (int i = 0; i < http_instance->num_headers; i++) { + (*client_headers)[i].field_name = http_instance->headers[i].name; + (*client_headers)[i].field_value = http_instance->headers[i].value; + } + + ret = efi_http_send_data(token->message->body, &token->message->body_length, http_instance); + if (ret != EFI_SUCCESS) + goto out_bad_signal; + + token->status = EFI_SUCCESS; + goto out_signal; + +out_bad_signal: + token->status = EFI_ABORTED; +out_signal: + efi_signal_event(token->event); +out: + return EFI_EXIT(ret); +} + +/* + * efi_http_poll() - Polls for incoming data packets and processes outgoing data packets + * + * This function implements EFI_HTTP_PROTOCOL.Poll(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_poll(struct efi_http_protocol *this) +{ + EFI_ENTRY("%p", this); + + efi_status_t ret = EFI_UNSUPPORTED; + + return EFI_EXIT(ret); +} + +/* EFI_HTTP_SERVICE_BINDING_PROTOCOL */ + +/* + * efi_http_service_binding_create_child() - Creates a child handle + * and installs a protocol + * + * This function implements EFI_HTTP_SERVICE_BINDING.CreateChild(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @child_handle: pointer to child handle + * Return: status code + */ +static efi_status_t EFIAPI efi_http_service_binding_create_child( + struct efi_service_binding_protocol *this, + efi_handle_t *child_handle) +{ + EFI_ENTRY("%p, %p", this, child_handle); + + efi_status_t ret = EFI_SUCCESS; + struct efi_http_instance *new_instance; + + if (!child_handle) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + new_instance = calloc(1, sizeof(struct efi_http_instance)); + if (!new_instance) { + ret = EFI_OUT_OF_RESOURCES; + goto failure_to_add_protocol; + } + + if (*child_handle) { + new_instance->handle = *child_handle; + goto install; + } + + new_instance->handle = calloc(1, sizeof(struct efi_object)); + if (!new_instance->handle) { + efi_free_pool((void *)new_instance); + ret = EFI_OUT_OF_RESOURCES; + goto failure_to_add_protocol; + } + + efi_add_handle(new_instance->handle); + *child_handle = new_instance->handle; + +install: + ret = efi_add_protocol(new_instance->handle, &efi_http_guid, + &new_instance->http); + if (ret != EFI_SUCCESS) + goto failure_to_add_protocol; + + new_instance->http.get_mode_data = efi_http_get_mode_data; + new_instance->http.configure = efi_http_configure; + new_instance->http.request = efi_http_request; + new_instance->http.cancel = efi_http_cancel; + new_instance->http.response = efi_http_response; + new_instance->http.poll = efi_http_poll; + ++num_instances; + + return EFI_EXIT(EFI_SUCCESS); + +failure_to_add_protocol: + return EFI_EXIT(ret); +} + +/* + * efi_http_service_binding_destroy_child() - Destroys a child handle with + * a protocol installed on it + * + * This function implements EFI_HTTP_SERVICE_BINDING.DestroyChild(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @child_handle: child handle + * Return: status code + */ +static efi_status_t EFIAPI efi_http_service_binding_destroy_child( + struct efi_service_binding_protocol *this, + efi_handle_t child_handle) +{ + EFI_ENTRY("%p, %p", this, child_handle); + efi_status_t ret = EFI_SUCCESS; + struct efi_http_instance *http_instance; + struct efi_handler *phandler; + void *protocol_interface; + + if (num_instances == 0) + return EFI_EXIT(EFI_NOT_FOUND); + + if (!child_handle) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + efi_search_protocol(child_handle, &efi_http_guid, &phandler); + + if (phandler) + protocol_interface = phandler->protocol_interface; + + ret = efi_delete_handle(child_handle); + if (ret != EFI_SUCCESS) + return EFI_EXIT(ret); + + http_instance = (struct efi_http_instance *)protocol_interface; + efi_free_pool(http_instance->http_load_addr); + http_instance->http_load_addr = NULL; + + free(protocol_interface); + + num_instances--; + + return EFI_EXIT(EFI_SUCCESS); +} + +/** + * efi_http_register() - register the http protocol + * + */ +efi_status_t efi_http_register(const efi_handle_t handle, + struct efi_service_binding_protocol *http_service_binding) +{ + efi_status_t r = EFI_SUCCESS; + + r = efi_add_protocol(handle, &efi_http_service_binding_guid, + http_service_binding); + if (r != EFI_SUCCESS) + goto failure_to_add_protocol; + + http_service_binding->create_child = efi_http_service_binding_create_child; + http_service_binding->destroy_child = efi_http_service_binding_destroy_child; + + return EFI_SUCCESS; +failure_to_add_protocol: + return r; +} + +enum efi_http_status_code efi_u32_to_httpstatus(u32 status) +{ + switch (status) { + case 100: return HTTP_STATUS_100_CONTINUE; + case 101: return HTTP_STATUS_101_SWITCHING_PROTOCOLS; + case 200: return HTTP_STATUS_200_OK; + case 201: return HTTP_STATUS_201_CREATED; + case 202: return HTTP_STATUS_202_ACCEPTED; + case 203: return HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION; + case 204: return HTTP_STATUS_204_NO_CONTENT; + case 205: return HTTP_STATUS_205_RESET_CONTENT; + case 206: return HTTP_STATUS_206_PARTIAL_CONTENT; + case 300: return HTTP_STATUS_300_MULTIPLE_CHOICES; + case 301: return HTTP_STATUS_301_MOVED_PERMANENTLY; + case 302: return HTTP_STATUS_302_FOUND; + case 303: return HTTP_STATUS_303_SEE_OTHER; + case 304: return HTTP_STATUS_304_NOT_MODIFIED; + case 305: return HTTP_STATUS_305_USE_PROXY; + case 307: return HTTP_STATUS_307_TEMPORARY_REDIRECT; + case 400: return HTTP_STATUS_400_BAD_REQUEST; + case 401: return HTTP_STATUS_401_UNAUTHORIZED; + case 402: return HTTP_STATUS_402_PAYMENT_REQUIRED; + case 403: return HTTP_STATUS_403_FORBIDDEN; + case 404: return HTTP_STATUS_404_NOT_FOUND; + case 405: return HTTP_STATUS_405_METHOD_NOT_ALLOWED; + case 406: return HTTP_STATUS_406_NOT_ACCEPTABLE; + case 407: return HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED; + case 408: return HTTP_STATUS_408_REQUEST_TIME_OUT; + case 409: return HTTP_STATUS_409_CONFLICT; + case 410: return HTTP_STATUS_410_GONE; + case 411: return HTTP_STATUS_411_LENGTH_REQUIRED; + case 412: return HTTP_STATUS_412_PRECONDITION_FAILED; + case 413: return HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE; + case 414: return HTTP_STATUS_414_REQUEST_URI_TOO_LARGE; + case 415: return HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE; + case 416: return HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED; + case 417: return HTTP_STATUS_417_EXPECTATION_FAILED; + case 500: return HTTP_STATUS_500_INTERNAL_SERVER_ERROR; + case 501: return HTTP_STATUS_501_NOT_IMPLEMENTED; + case 502: return HTTP_STATUS_502_BAD_GATEWAY; + case 503: return HTTP_STATUS_503_SERVICE_UNAVAILABLE; + case 504: return HTTP_STATUS_504_GATEWAY_TIME_OUT; + case 505: return HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED; + case 308: return HTTP_STATUS_308_PERMANENT_REDIRECT; + default: return HTTP_STATUS_UNSUPPORTED_STATUS; + } +} diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 916c15999e2..67593ef50c0 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -66,6 +66,7 @@ static struct efi_event *wait_for_packet; * @pxe: PXE base code protocol interface * @pxe_mode: status of the PXE base code protocol * @ip4_config2: IP4 Config2 protocol interface + * @http_service_binding: Http service binding protocol interface */ struct efi_net_obj { struct efi_object header; @@ -76,6 +77,9 @@ struct efi_net_obj { #if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) struct efi_ip4_config2_protocol ip4_config2; #endif +#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL) + struct efi_service_binding_protocol http_service_binding; +#endif }; /* @@ -1009,6 +1013,19 @@ efi_status_t efi_net_register(void) goto failure_to_add_protocol; #endif +#ifdef CONFIG_EFI_HTTP_PROTOCOL + r = efi_http_register(&netobj->header, &netobj->http_service_binding); + if (r != EFI_SUCCESS) + goto failure_to_add_protocol; + /* + * No harm on doing the following. If the PXE handle is present, the client could + * find it and try to get its IP address from it. In here the PXE handle is present + * but the PXE protocol is not yet implmenented, so we add this in the meantime. + */ + efi_net_get_addr((struct efi_ipv4_address *)&netobj->pxe_mode.station_ip, + (struct efi_ipv4_address *)&netobj->pxe_mode.subnet_mask, NULL); +#endif + return EFI_SUCCESS; failure_to_add_protocol: printf("ERROR: Failure to add protocol\n"); @@ -1207,8 +1224,6 @@ static efi_status_t efi_net_set_buffer(void **buffer, size_t size) if (size < SZ_64K) size = SZ_64K; - efi_free_pool(*buffer); - *buffer = efi_alloc(size); if (!*buffer) ret = EFI_OUT_OF_RESOURCES; @@ -1305,6 +1320,7 @@ efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buf wget_ret = wget_request((ulong)*buffer, url, &efi_wget_info); if ((ulong)efi_wget_info.hdr_cont_len > efi_wget_info.buffer_size) { // Try again with updated buffer size + efi_free_pool(*buffer); ret = efi_net_set_buffer(buffer, (size_t)efi_wget_info.hdr_cont_len); if (ret != EFI_SUCCESS) goto out; -- cgit v1.3.1 From 287a3b25bde4a340f81b0c85ca32860b6a39c1a0 Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Tue, 19 Nov 2024 06:02:56 +0530 Subject: misc: k3_avs: Add OPP_LOW voltage and frequency to vd_data J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance Points as per (7.5 Operating Performance Points) section in the Datasheet [0]. - A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM. - A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW voltage (though OPP_LOW voltage is recommended to reduce power consumption). Add OPP_LOW frequency->voltage entry to vd_data. The actual OPP voltage for the device is read from the efuse and updated in k3_avs_probe(). OPP_NOM corresponds to OPP_1 and OPP_LOW to OPP_0 efuse register fields, as described in the Datasheet [0] The register offsets and fields are described in the TRM (5.2.6.1.5 WKUP_VTM_VD_OPPVID_j Register) [1]. [0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet) [1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM) Signed-off-by: Reid Tonking Signed-off-by: Aniket Limaye --- drivers/misc/k3_avs.c | 4 ++++ include/k3-avs.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 99a18a109b7..9d950d034a5 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -501,6 +501,10 @@ static struct vd_data j721e_vd_data[] = { .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */ .clk_id = 2, /* ARM clock */ .opps = { + [AM6_OPP_LOW] = { + .volt = 0, /* voltage TBD after OPP fuse reading */ + .freq = 1000000000, + }, [AM6_OPP_NOM] = { .volt = 880000, /* TBD in DM */ .freq = 2000000000, diff --git a/include/k3-avs.h b/include/k3-avs.h index 1014d5d114d..f6f1031c9cc 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -20,6 +20,7 @@ #define NUM_OPPS 4 +#define AM6_OPP_LOW 0 #define AM6_OPP_NOM 1 #define AM6_OPP_OD 2 #define AM6_OPP_TURBO 3 -- cgit v1.3.1 From afe0ab6d3004b435cd17d3b5864de6461d68c7a0 Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Tue, 19 Nov 2024 06:02:57 +0530 Subject: misc: k3_avs: Check validity of efuse voltage data k3_avs driver checks opp_ids when probing and overwrites the voltage values in vd_data for the respective board. The new k3_avs_check_opp() can be called from board files to check the efuse data and returns 0 if valid. Also add the same check in k3_avs_program_voltage() to error out if the efuse data was not valid. Signed-off-by: Reid Tonking Signed-off-by: Aniket Limaye Reviewed-by: Manorit Chawdhry --- drivers/misc/k3_avs.c | 32 ++++++++++++++++++++++++++++++++ include/k3-avs.h | 1 + 2 files changed, 33 insertions(+) (limited to 'include') diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 9d950d034a5..0774e0a4c9e 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -121,6 +121,11 @@ static int k3_avs_program_voltage(struct k3_avs_privdata *priv, if (!vd->supply) return -ENODEV; + if (!volt) { + dev_err(priv->dev, "No efuse found for opp_%d\n", opp_id); + return -EINVAL; + } + vd->opp = opp_id; vd->flags |= VD_FLAG_INIT_DONE; @@ -192,6 +197,33 @@ static int match_opp(struct vd_data *vd, u32 freq) return -EINVAL; } +/** + * k3_check_opp: Check for presence of opp efuse + * @dev: AVS device + * @vdd_id: voltage domain ID + * @opp_id: opp id to check if voltage is present + * + * Checks to see if an opp has voltage. k3_avs probe will populate + * voltage data if efuse is present. Returns 0 if data is valid. + */ +int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id) +{ + struct k3_avs_privdata *priv = dev_get_priv(dev); + struct vd_data *vd; + int volt; + + vd = get_vd(priv, vdd_id); + if (!vd) + return -EINVAL; + + volt = vd->opps[opp_id].volt; + if (volt) + return 0; + + printf("No efuse found for opp_%d\n", opp_id); + return -EINVAL; +} + /** * k3_avs_notify_freq: Notify clock rate change towards AVS subsystem * @dev_id: Device ID for the clock to be changed diff --git a/include/k3-avs.h b/include/k3-avs.h index f6f1031c9cc..5a973e4ed45 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -27,5 +27,6 @@ int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id); int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq); +int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id); #endif -- cgit v1.3.1 From 1614347036716dd8fe55ed530cb7c0d7dc5994ed Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sun, 10 Nov 2024 12:50:20 +0100 Subject: dm: core: implement oftree variant of parse_phandle OPs Implement oftree variant of parse_phandle OPs. There is currently a very hidden and laten BUG with parse_phandle OPs that doesn't permit the support of multiple DTS in a system. One usage example if sandbox with the usage of other.dts The BUG is only present on live scenario where of_... OPs are used and it's not present when fdt... OPs are used. This is caused by an assumption made in __of_parse_phandle_with_args, with the of_find_node_by_phandle call that pass the first arg as NULL. This makes of_find_node_by_phandle use the default root node of the system and doesn't permit the usage of alternative tree. This is correct for normal system and also for the linux kernel where it's assumed a single device tree. It's problematic if other device tree needs to be used. To fix this, introduce __of_root_parse_phandle_with_args to define a root device tree for of_find_node_by_phandle. Introduce all the variant OPs for this and in ofnode, the oftree OPs following how it's done for other OPs with similar task. For FDT scenario, ofnode_from_fdtdec_phandle_args is reworked to accept a new variable, node and noffset_to_ofnode is used instead of offset_to_ofnode. This is required to support multiple FDB blob to calculate the correct of_offset of the ofnode. Signed-off-by: Christian Marangi Reviewed-by: Simon Glass --- drivers/core/of_access.c | 61 ++++++++++++++++++++++++---------- drivers/core/ofnode.c | 51 ++++++++++++++++++++++++++-- include/dm/of_access.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++++ include/dm/ofnode.h | 66 +++++++++++++++++++++++++++++++++++++ 4 files changed, 244 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 77acd766262..b11e36202c1 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -666,11 +666,12 @@ int of_property_read_string_helper(const struct device_node *np, return i <= 0 ? -ENODATA : i; } -static int __of_parse_phandle_with_args(const struct device_node *np, - const char *list_name, - const char *cells_name, - int cell_count, int index, - struct of_phandle_args *out_args) +static int __of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct of_phandle_args *out_args) { const __be32 *list, *list_end; int rc = 0, cur_index = 0; @@ -706,7 +707,7 @@ static int __of_parse_phandle_with_args(const struct device_node *np, * below. */ if (cells_name || cur_index == index) { - node = of_find_node_by_phandle(NULL, phandle); + node = of_find_node_by_phandle(root, phandle); if (!node) { dm_warn("%s: could not find phandle\n", np->full_name); @@ -783,39 +784,65 @@ static int __of_parse_phandle_with_args(const struct device_node *np, return rc; } -struct device_node *of_parse_phandle(const struct device_node *np, - const char *phandle_name, int index) +struct device_node *of_root_parse_phandle(struct device_node *root, + const struct device_node *np, + const char *phandle_name, int index) { struct of_phandle_args args; if (index < 0) return NULL; - if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0, index, - &args)) + if (__of_root_parse_phandle_with_args(root, np, phandle_name, NULL, 0, + index, &args)) return NULL; return args.np; } +int of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cell_count, int index, + struct of_phandle_args *out_args) +{ + if (index < 0) + return -EINVAL; + + return __of_root_parse_phandle_with_args(root, np, list_name, cells_name, + cell_count, index, out_args); +} + +int of_root_count_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cell_count) +{ + return __of_root_parse_phandle_with_args(root, np, list_name, cells_name, + cell_count, -1, NULL); +} + +struct device_node *of_parse_phandle(const struct device_node *np, + const char *phandle_name, int index) +{ + return of_root_parse_phandle(NULL, np, phandle_name, index); +} + int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int cell_count, int index, struct of_phandle_args *out_args) { - if (index < 0) - return -EINVAL; - - return __of_parse_phandle_with_args(np, list_name, cells_name, - cell_count, index, out_args); + return of_root_parse_phandle_with_args(NULL, np, list_name, cells_name, + cell_count, index, out_args); } int of_count_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int cell_count) { - return __of_parse_phandle_with_args(np, list_name, cells_name, - cell_count, -1, NULL); + return of_root_count_phandle_with_args(NULL, np, list_name, cells_name, + cell_count); } static void of_alias_add(struct alias_prop *ap, struct device_node *np, diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 950895e72a9..b9cc9419407 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -879,11 +879,11 @@ int ofnode_read_string_list(ofnode node, const char *property, return count; } -static void ofnode_from_fdtdec_phandle_args(struct fdtdec_phandle_args *in, +static void ofnode_from_fdtdec_phandle_args(ofnode node, struct fdtdec_phandle_args *in, struct ofnode_phandle_args *out) { assert(OF_MAX_PHANDLE_ARGS == MAX_PHANDLE_ARGS); - out->node = offset_to_ofnode(in->node); + out->node = noffset_to_ofnode(node, in->node); out->args_count = in->args_count; memcpy(out->args, in->args, sizeof(out->args)); } @@ -923,7 +923,40 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, cell_count, index, &args); if (ret) return ret; - ofnode_from_fdtdec_phandle_args(&args, out_args); + ofnode_from_fdtdec_phandle_args(node, &args, out_args); + } + + return 0; +} + +int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args) +{ + if (ofnode_is_np(node)) { + struct of_phandle_args args; + int ret; + + ret = of_root_parse_phandle_with_args(tree.np, + ofnode_to_np(node), + list_name, cells_name, + cell_count, index, + &args); + if (ret) + return ret; + ofnode_from_of_phandle_args(&args, out_args); + } else { + struct fdtdec_phandle_args args; + int ret; + + ret = fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), + list_name, cells_name, + cell_count, index, &args); + if (ret) + return ret; + ofnode_from_fdtdec_phandle_args(node, &args, out_args); } return 0; @@ -941,6 +974,18 @@ int ofnode_count_phandle_with_args(ofnode node, const char *list_name, cell_count, -1, NULL); } +int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count) +{ + if (ofnode_is_np(node)) + return of_root_count_phandle_with_args(tree.np, ofnode_to_np(node), + list_name, cells_name, cell_count); + else + return fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), list_name, cells_name, + cell_count, -1, NULL); +} + ofnode ofnode_path(const char *path) { if (of_live_active()) diff --git a/include/dm/of_access.h b/include/dm/of_access.h index de740d44674..44143a5a391 100644 --- a/include/dm/of_access.h +++ b/include/dm/of_access.h @@ -453,6 +453,92 @@ static inline int of_property_count_strings(const struct device_node *np, return of_property_read_string_helper(np, propname, NULL, 0, 0); } +/** + * of_root_parse_phandle - Resolve a phandle property to a device_node pointer + * from a root node + * @root: Pointer to root device tree node (default root node if NULL) + * @np: Pointer to device node holding phandle property + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * + * Return: + * the device_node pointer with refcount incremented. Use + * of_node_put() on it when done. + */ +struct device_node *of_root_parse_phandle(struct device_node *root, + const struct device_node *np, + const char *phandle_name, int index); + +/** + * of_root_parse_phandle_with_args() - Find a node pointed by phandle in a list + * from a root node + * + * @root: pointer to root device tree node (default root node if NULL) + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * Return: + * 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * .. code-block:: + * + * phandle1: node1 { + * #list-cells = <2>; + * }; + * phandle2: node2 { + * #list-cells = <1>; + * }; + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * }; + * + * To get a device_node of the `node2' node you may call this: + * of_root_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); + */ +int of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count, int index, + struct of_phandle_args *out_args); + +/** + * of_root_count_phandle_with_args() - Count the number of phandle in a list + * from a root node + * + * @root: pointer to root device tree node (default root node if NULL) + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * Return: + * number of phandle found, -ENOENT if @list_name does not exist, + * -EINVAL if a phandle was not found, @cells_name could not be found, + * the arguments were truncated or there were too many arguments. + * + * Returns number of phandle found on success, on error returns appropriate + * errno value. + */ +int of_root_count_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count); + /** * of_parse_phandle - Resolve a phandle property to a device_node pointer * @np: Pointer to device node holding phandle property diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 0787758926f..7ece68874ae 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -909,6 +909,72 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, int ofnode_count_phandle_with_args(ofnode node, const char *list_name, const char *cells_name, int cell_count); +/** + * oftree_parse_phandle_with_args() - Find a node pointed by phandle in a list + * from a root node + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * .. code-block:: + * + * phandle1: node1 { + * #list-cells = <2>; + * }; + * phandle2: node2 { + * #list-cells = <1>; + * }; + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * }; + * + * To get a device_node of the `node2' node you may call this: + * oftree_parse_phandle_with_args(node3, "list", "#list-cells", 0, 1, &args); + * + * @tree: device tree to use + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cell_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * Return: + * 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + */ +int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args); + +/** + * oftree_count_phandle_with_args() - Count number of phandle in a list + * from a root node + * + * This function is useful to count phandles into a list. + * Returns number of phandle on success, on error returns appropriate + * errno value. + * + * @tree: device tree to use + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cell_count: Cell count to use if @cells_name is NULL + * Return: + * number of phandle on success, -ENOENT if @list_name does not exist, + * -EINVAL if a phandle was not found, @cells_name could not be found. + */ +int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count); + /** * ofnode_path() - find a node by full path * -- cgit v1.3.1 From 2d31a2797a359e8eda95ca9e742982e67ce57ba7 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sun, 10 Nov 2024 12:50:22 +0100 Subject: dm: core: implement ofnode/tree_parse_phandle() helper Implement ofnode/tree_parse_phandle() helper as an equivalent of of_parse_phandle to handle simple single value phandle. Signed-off-by: Christian Marangi Reviewed-by: Simon Glass --- drivers/core/ofnode.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/dm/ofnode.h | 26 +++++++++++++++++++++++ 2 files changed, 84 insertions(+) (limited to 'include') diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index b9cc9419407..dc6ac069311 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -879,6 +879,64 @@ int ofnode_read_string_list(ofnode node, const char *property, return count; } +ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name, + int index) +{ + ofnode phandle; + + if (ofnode_is_np(node)) { + struct device_node *np; + + np = of_parse_phandle(ofnode_to_np(node), phandle_name, + index); + if (!np) + return ofnode_null(); + + phandle = np_to_ofnode(np); + } else { + struct fdtdec_phandle_args args; + + if (fdtdec_parse_phandle_with_args(ofnode_to_fdt(node), + ofnode_to_offset(node), + phandle_name, NULL, + 0, index, &args)) + return ofnode_null(); + + phandle = offset_to_ofnode(args.node); + } + + return phandle; +} + +ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name, + int index) +{ + ofnode phandle; + + if (ofnode_is_np(node)) { + struct device_node *np; + + np = of_root_parse_phandle(tree.np, ofnode_to_np(node), + phandle_name, index); + if (!np) + return ofnode_null(); + + phandle = np_to_ofnode(np); + } else { + struct fdtdec_phandle_args args; + + if (fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), + phandle_name, NULL, + 0, index, &args)) + return ofnode_null(); + + phandle = noffset_to_ofnode(node, args.node); + } + + return phandle; +} + static void ofnode_from_fdtdec_phandle_args(ofnode node, struct fdtdec_phandle_args *in, struct ofnode_phandle_args *out) { diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 7ece68874ae..eea6b13217c 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -847,6 +847,18 @@ int ofnode_read_string_count(ofnode node, const char *property); int ofnode_read_string_list(ofnode node, const char *property, const char ***listp); +/** + * ofnode_parse_phandle() - Resolve a phandle property to an ofnode + * + * @node: node to check + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * Return: ofnode that the phandle points to or ofnode_null() on error. + */ +ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name, + int index); + /** * ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list * @@ -909,6 +921,20 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, int ofnode_count_phandle_with_args(ofnode node, const char *list_name, const char *cells_name, int cell_count); +/** + * oftree_parse_phandle() - Resolve a phandle property to an ofnode + * from a root node + * + * @tree: device tree to use + * @node: node to check + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * Return: ofnode that the phandle points to or ofnode_null() on error. + */ +ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name, + int index); + /** * oftree_parse_phandle_with_args() - Find a node pointed by phandle in a list * from a root node -- cgit v1.3.1 From cab275c446d3a332890b2751e50636ecf38c1098 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sun, 10 Nov 2024 12:50:24 +0100 Subject: dm: core: implement phandle ofnode_options helper Implement ofnode_options phandle helper to get an ofnode from a phandle option in /options/u-boot. This helper can be useful since new DT yaml usually require to link a phandle of a node instead of referencing it by name or other indirect way. Signed-off-by: Christian Marangi Reviewed-by: Simon Glass --- drivers/core/ofnode.c | 15 +++++++++++++++ include/dm/ofnode.h | 15 +++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'include') diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index dc6ac069311..c8161827d1c 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1871,6 +1871,21 @@ const char *ofnode_options_read_str(const char *prop_name) return ofnode_read_string(uboot, prop_name); } +int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep) +{ + ofnode uboot; + + uboot = ofnode_path("/options/u-boot"); + if (!ofnode_valid(uboot)) + return -EINVAL; + + *nodep = ofnode_parse_phandle(uboot, prop_name, 0); + if (!ofnode_valid(*nodep)) + return -EINVAL; + + return 0; +} + int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset) { int ret; diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index eea6b13217c..890f0e6cf40 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1720,6 +1720,21 @@ int ofnode_options_read_int(const char *prop_name, int default_val); */ const char *ofnode_options_read_str(const char *prop_name); +/** + * ofnode_options_get_by_phandle() - Get a ofnode from phandle from the U-Boot options + * + * This reads a property from the /options/u-boot/ node of the devicetree. + * + * This only works with the control FDT. + * + * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings + * + * @prop_name: property name to look up + * @nodep: pointer to ofnode where node is stored + * Return: 0, if found, or negative error if not + */ +int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep); + /** * ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset * -- cgit v1.3.1 From dca82739b9d767d4074e990b060f0da93ba36550 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 20 Nov 2024 17:01:35 +0100 Subject: env: Switch the callback static list to Kconfig Switch the callback static list from the board configuration variable CFG_ENV_CALLBACK_LIST_STATIC to Kconfig CONFIG_ENV_CALLBACK_LIST_STATIC. Signed-off-by: Christoph Niedermaier Reviewed-by: Marek Vasut --- doc/develop/environment.rst | 4 ++-- env/Kconfig | 13 +++++++++++++ include/env_callback.h | 7 +------ 3 files changed, 16 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/doc/develop/environment.rst b/doc/develop/environment.rst index e1783462bb0..e46cd39d601 100644 --- a/doc/develop/environment.rst +++ b/doc/develop/environment.rst @@ -18,8 +18,8 @@ The callbacks are named and associated with a function using the U_BOOT_ENV_CALLBACK macro in your board or driver code. These callbacks are associated with variables in one of two ways. The -static list can be added to by defining CFG_ENV_CALLBACK_LIST_STATIC -in the board configuration to a string that defines a list of +static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC +in the board defconfig via menuconfig to a string that defines a list of associations. The list must be in the following format:: entry = variable_name[:callback_name] diff --git a/env/Kconfig b/env/Kconfig index 031cf58186a..aaf0b1fe9ac 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -21,6 +21,19 @@ config ENV_SOURCE_FILE environment is assumed to come from the ad-hoc CFG_EXTRA_ENV_SETTINGS #define +config ENV_CALLBACK_LIST_STATIC + string "Static callbacks list" + default "" + help + The environment callbacks are associated with variables in a + static list. Define this list in the following format: + + entry = variable_name[:callback_name] + list = entry[,list] + + If the callback name is not specified, then the callback is deleted. + Spaces are also allowed anywhere in the list. + config SAVEENV def_bool y if CMD_SAVEENV diff --git a/include/env_callback.h b/include/env_callback.h index bc8ff1923e1..47a31f6cf52 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -14,11 +14,6 @@ #define ENV_CALLBACK_VAR ".callbacks" -/* Board configs can define additional static callback bindings */ -#ifndef CFG_ENV_CALLBACK_LIST_STATIC -#define CFG_ENV_CALLBACK_LIST_STATIC -#endif - #ifdef CONFIG_SILENT_CONSOLE #define SILENT_CALLBACK "silent:silent," #else @@ -90,7 +85,7 @@ SILENT_CALLBACK \ "stdin:console,stdout:console,stderr:console," \ "serial#:serialno," \ - CFG_ENV_CALLBACK_LIST_STATIC + CONFIG_ENV_CALLBACK_LIST_STATIC #ifndef CONFIG_XPL_BUILD void env_callback_init(struct env_entry *var_entry); -- cgit v1.3.1 From e2cc259cbb43aafb60591edb68424f70a34c71ab Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Tue, 3 Dec 2024 10:42:33 +0100 Subject: phycore_imx8mm: Switch to using env text files Move the environment into the board directory and convert header to a txt file. In addition, this patch also applies following changes: - Change default nfsroot path to /srv/nfs due to compliance with Linux FHS 3.0. - Rename specific variables as stated in the bootstd documentation. Renamed variables: fdt_addr => fdt_addr_r fdt_file => fdtfile Signed-off-by: Yunus Bas --- board/phytec/phycore_imx8mm/phycore_imx8mm.env | 51 ++++++++++++++++++++++++++ include/configs/phycore_imx8mm.h | 46 ----------------------- 2 files changed, 51 insertions(+), 46 deletions(-) create mode 100644 board/phytec/phycore_imx8mm/phycore_imx8mm.env (limited to 'include') diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env new file mode 100644 index 00000000000..33a2595fa16 --- /dev/null +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -0,0 +1,51 @@ +console=ttymxc2,115200 +emmc_dev=2 +fdt_addr_r=0x48000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +ip_dyn=yes +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcargs= + setenv bootargs console=${console} + root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw +mmcautodetect=yes +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if run loadfdt; then + if test ${dofitboot} = 1; then + booti ${loadaddr} - ${fdt_addr_r} + else + echo WARN: Cannot load the DT; + fi; + fi; +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=2 +netargs= + setenv bootargs console=${console} root=/dev/nfs ip=dhcp + nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + run netargs; + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; +nfsroot=/srv/nfs +update_bootimg= + mmc dev ${mmcdev}; + if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then + setexpr fw_sz ${filesize} / 0x200; + mmc write ${loadaddr} ${update_offset} ${fw_sz}; + fi; +update_filename=flash.bin +update_offset=0x42 diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index e74a3f184c6..20e2ab832ee 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -20,52 +20,6 @@ /* For RAW image gives a error info not panic */ #endif -#define CFG_EXTRA_ENV_SETTINGS \ - "image=Image\0" \ - "console=ttymxc2,115200\0" \ - "fdt_addr=0x48000000\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=2\0" \ - "update_offset=0x42\0" \ - "update_filename=flash.bin\0" \ - "update_bootimg=" \ - "mmc dev ${mmcdev} ; " \ - "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ - "fi\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0 " \ - "nfsroot=/nfs\0" \ - "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" \ - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 -- cgit v1.3.1 From ff9f080e59e16550cccdcc777dc62e0e2e210ed6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 3 Dec 2024 23:42:54 +0800 Subject: imx: Support i.MX91 11x11 EVK board Add i.MX91 11x11 EVK Board support. - Four ddr scripts included w/o inline ecc feature. - SDHC/NETWORK/I2C/UART supported - PCA9451 supported, default nominal drive mode - Documentation added. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/dts/imx91-11x11-evk-u-boot.dtsi | 195 ++ arch/arm/dts/imx91-u-boot.dtsi | 92 + arch/arm/mach-imx/imx9/Kconfig | 7 + board/freescale/imx91_evk/Kconfig | 19 + board/freescale/imx91_evk/MAINTAINERS | 7 + board/freescale/imx91_evk/Makefile | 16 + board/freescale/imx91_evk/imx91_evk.c | 33 + board/freescale/imx91_evk/imx91_evk.env | 63 + board/freescale/imx91_evk/lpddr4_timing_1600mts.c | 1995 ++++++++++++++++++++ .../imx91_evk/lpddr4_timing_1600mts_ecc.c | 1995 ++++++++++++++++++++ board/freescale/imx91_evk/lpddr4_timing_2400mts.c | 1995 ++++++++++++++++++++ .../imx91_evk/lpddr4_timing_2400mts_ecc.c | 1995 ++++++++++++++++++++ board/freescale/imx91_evk/spl.c | 167 ++ configs/imx91_11x11_evk_defconfig | 145 ++ configs/imx91_11x11_evk_inline_ecc_defconfig | 146 ++ doc/board/nxp/imx91_11x11_evk.rst | 70 + doc/board/nxp/index.rst | 1 + include/configs/imx91_evk.h | 21 + 18 files changed, 8962 insertions(+) create mode 100644 arch/arm/dts/imx91-11x11-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx91-u-boot.dtsi create mode 100644 board/freescale/imx91_evk/Kconfig create mode 100644 board/freescale/imx91_evk/MAINTAINERS create mode 100644 board/freescale/imx91_evk/Makefile create mode 100644 board/freescale/imx91_evk/imx91_evk.c create mode 100644 board/freescale/imx91_evk/imx91_evk.env create mode 100644 board/freescale/imx91_evk/lpddr4_timing_1600mts.c create mode 100644 board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c create mode 100644 board/freescale/imx91_evk/lpddr4_timing_2400mts.c create mode 100644 board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c create mode 100644 board/freescale/imx91_evk/spl.c create mode 100644 configs/imx91_11x11_evk_defconfig create mode 100644 configs/imx91_11x11_evk_inline_ecc_defconfig create mode 100644 doc/board/nxp/imx91_11x11_evk.rst create mode 100644 include/configs/imx91_evk.h (limited to 'include') diff --git a/arch/arm/dts/imx91-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx91-11x11-evk-u-boot.dtsi new file mode 100644 index 00000000000..54b4d0aa3b6 --- /dev/null +++ b/arch/arm/dts/imx91-11x11-evk-u-boot.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include "imx91-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + bootph-pre-ram; + bootph-some-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&fec { + compatible = "fsl,imx91-fec", "fsl,imx93-fec", "fsl,imx8mq-fec"; + phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx91-u-boot.dtsi b/arch/arm/dts/imx91-u-boot.dtsi new file mode 100644 index 00000000000..5b639c965d6 --- /dev/null +++ b/arch/arm/dts/imx91-u-boot.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Mathieu Othacehe + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&A55_0 { + clocks = <&clk IMX93_CLK_A55_SEL>; +}; + +&binman { + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + + ddr-1d-imem-fw { + filename = "lpddr4_imem_1d_v202201.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-1d-dmem-fw { + filename = "lpddr4_dmem_1d_v202201.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-2d-imem-fw { + filename = "lpddr4_imem_2d_v202201.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-2d-dmem-fw { + filename = "lpddr4_dmem_2d_v202201.bin"; + align-end = <4>; + type = "blob-ext"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x204A0000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + u-boot-container { + filename = "u-boot-container.bin"; + + mkimage { + args = "-n u-boot-container.cfgout -T imx8image -e 0x0"; + + blob { + filename = "u-boot.bin"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + align-size = <0x400>; + align = <0x400>; + }; + + uboot: blob-ext@2 { + filename = "u-boot-container.bin"; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 4554e215f0d..54c6b117fcf 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -29,6 +29,12 @@ choice prompt "NXP i.MX9 board select" optional +config TARGET_IMX91_11X11_EVK + bool "imx91_11x11_evk" + select OF_BOARD_FIXUP + select IMX91 + imply OF_UPSTREAM + config TARGET_IMX93_9X9_QSB bool "imx93_qsb" select OF_BOARD_FIXUP @@ -56,6 +62,7 @@ config TARGET_PHYCORE_IMX93 endchoice +source "board/freescale/imx91_evk/Kconfig" source "board/freescale/imx93_evk/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" diff --git a/board/freescale/imx91_evk/Kconfig b/board/freescale/imx91_evk/Kconfig new file mode 100644 index 00000000000..caaa82b4af8 --- /dev/null +++ b/board/freescale/imx91_evk/Kconfig @@ -0,0 +1,19 @@ +if TARGET_IMX91_11X11_EVK + +config SYS_BOARD + default "imx91_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx91_evk" + +config IMX91_EVK_LPDDR4 + bool "Using LPDDR4 Timing and PMIC voltage" + default y + select IMX9_LPDDR4X + help + Select the LPDDR4 timing and 1.1V VDDQ + +endif diff --git a/board/freescale/imx91_evk/MAINTAINERS b/board/freescale/imx91_evk/MAINTAINERS new file mode 100644 index 00000000000..f7d39bfb0a3 --- /dev/null +++ b/board/freescale/imx91_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX91 11x11 EVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx91_evk/ +F: include/configs/imx91_evk.h +F: configs/imx91_11x11_evk_defconfig +F: configs/imx91_11x11_evk_inline_ecc_defconfig diff --git a/board/freescale/imx91_evk/Makefile b/board/freescale/imx91_evk/Makefile new file mode 100644 index 00000000000..a96228af959 --- /dev/null +++ b/board/freescale/imx91_evk/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx91_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX9_DRAM_INLINE_ECC +obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts_ecc.o lpddr4_timing_1600mts_ecc.o +else +obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts.o lpddr4_timing_1600mts.o +endif +endif diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c new file mode 100644 index 00000000000..83bfca2f22d --- /dev/null +++ b/board/freescale/imx91_evk/imx91_evk.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "11X11_EVK"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env new file mode 100644 index 00000000000..92486c6f74d --- /dev/null +++ b/board/freescale/imx91_evk/imx91_evk.env @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 earlycon +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r} +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if run auth_os; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if run auth_os; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c new file mode 100644 index 00000000000..45e19daa028 --- /dev/null +++ b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x02121100}, + {0x4e300104, 0xF866000C}, + {0x4e300108, 0xF2FA8088}, + {0x4e30010C, 0x0061E1A0}, + {0x4e300124, 0x0C340000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30700000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000011}, + {0x4e300254, 0x00900090}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x0F220F09}, + {0x4e300304, 0x00901008}, + {0x4e300308, 0x063C061A}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00091000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x81820A48}, + {0x4e30010C, 0x00310110}, + {0x4e300124, 0x061A0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30100000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000009}, + {0x4e300254, 0x00440044}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xb}, + {0x1200c5, 0x3}, + {0x2200c5, 0x7}, + {0x2002e, 0x1}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x190}, + {0x120008, 0xc8}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + 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+ {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x320}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x1c2}, + {0x2000c, 0x64}, + {0x2000d, 0x3e8}, + {0x2000e, 0x2c}, + {0x12000b, 0xe1}, + {0x12000c, 0x32}, + {0x12000d, 0x1f4}, + {0x12000e, 0x10}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 800mts 1D */ + .drate = 800, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1600mts = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 800, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c new file mode 100644 index 00000000000..4594ab68aa0 --- /dev/null +++ b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ef}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x02121100}, + {0x4e300104, 0xF866000C}, + {0x4e300108, 0xF2FA8088}, + {0x4e30010C, 0x0061E1A0}, + {0x4e300124, 0x0C340000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30700000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000011}, + {0x4e300254, 0x00900090}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x0F220F09}, + {0x4e300304, 0x00901008}, + {0x4e300308, 0x063C061A}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00091000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x81820A48}, + {0x4e30010C, 0x00310110}, + {0x4e300124, 0x061A0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30100000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000009}, + {0x4e300254, 0x00440044}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xb}, + {0x1200c5, 0x3}, + {0x2200c5, 0x7}, + {0x2002e, 0x1}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x190}, + {0x120008, 0xc8}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x320}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x1c2}, + {0x2000c, 0x64}, + {0x2000d, 0x3e8}, + {0x2000e, 0x2c}, + {0x12000b, 0xe1}, + {0x12000c, 0x32}, + {0x12000d, 0x1f4}, + {0x12000e, 0x10}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 800mts 1D */ + .drate = 800, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1600mts = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 800, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c new file mode 100644 index 00000000000..e0e6f5da3d6 --- /dev/null +++ b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x135C2110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E08CC}, + {0x4e30010C, 0x0061E070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00DC00DC}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00DC180C}, + {0x4e300308, 0x0C3C0927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010D1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABAC068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x006A006A}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + 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{0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c new file mode 100644 index 00000000000..811687170c3 --- /dev/null +++ b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ef}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x135C2110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E08CC}, + {0x4e30010C, 0x0061E070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00DC00DC}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00DC180C}, + {0x4e300308, 0x0C3C0927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010D1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABAC068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x006A006A}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx91_evk/spl.c b/board/freescale/imx91_evk/spl.c new file mode 100644 index 00000000000..46bde93fe3b --- /dev/null +++ b/board/freescale/imx91_evk/spl.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +extern struct dram_timing_info dram_timing_1600mts; +void spl_dram_init(void) +{ + struct dram_timing_info *ptiming = &dram_timing; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) + ptiming = &dram_timing_1600mts; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ddr_init(ptiming); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("ERROR: Get PMIC PCA9451A failed!\n"); + return ret; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); + + /* set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig new file mode 100644 index 00000000000..6ee0b448f99 --- /dev/null +++ b/configs/imx91_11x11_evk_defconfig @@ -0,0 +1,145 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="imx91_evk" +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk" +CONFIG_TARGET_IMX91_11X11_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204E0000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_TEXT_BASE=0x204A0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20498000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_CPU=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_ADC_IMX93=y +CONFIG_CLK_IMX93=y +CONFIG_CPU=y +CONFIG_CPU_IMX=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000 +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_ADP5585_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=20000 +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SHA384=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig new file mode 100644 index 00000000000..761a6666264 --- /dev/null +++ b/configs/imx91_11x11_evk_inline_ecc_defconfig @@ -0,0 +1,146 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="imx91_evk" +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk" +CONFIG_TARGET_IMX91_11X11_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204E0000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_TEXT_BASE=0x204A0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20498000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_CPU=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_ADC_IMX93=y +CONFIG_CLK_IMX93=y +CONFIG_CPU=y +CONFIG_CPU_IMX=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000 +CONFIG_IMX9_DRAM_INLINE_ECC=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_ADP5585_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ANEG_TIMEOUT=20000 +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SHA384=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/doc/board/nxp/imx91_11x11_evk.rst b/doc/board/nxp/imx91_11x11_evk.rst new file mode 100644 index 00000000000..3ec3d28c1c2 --- /dev/null +++ b/doc/board/nxp/imx91_11x11_evk.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx91_11x11_EVK +======================= + +U-Boot for the NXP i.MX91 11x11 EVK + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Get ahab-container.img +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.10 + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx91 bl31 + $ cp build/imx91/release/bl31.bin $(srctree) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin + $ chmod +x firmware-imx-8.21.bin + $ ./firmware-imx-8.21.bin + $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Get ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin + $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin + $ ./firmware-ele-imx-1.3.0-17945fc.bin + $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx91_11x11_evk_defconfig or imx91_11x11_evk_inline_ecc_defconfig + $ make + +- Inline ECC is to enable DDR ECC feature with imx91_11x11_evk_inline_ecc_defconfig + +Burn the flash.bin to MicroSD card offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc + +Boot +---- + +Set Boot switch to SD boot diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 734bab69807..8ca4b561986 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -12,6 +12,7 @@ NXP Semiconductors imx8mq_evk imx8qxp_mek imx8ulp_evk + imx91_11x11_evk imx93_9x9_qsb imx93_11x11_evk imxrt1020-evk diff --git a/include/configs/imx91_evk.h b/include/configs/imx91_evk.h new file mode 100644 index 00000000000..9c5014fd0a5 --- /dev/null +++ b/include/configs/imx91_evk.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + +#ifndef __IMX91_EVK_H +#define __IMX91_EVK_H + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif -- cgit v1.3.1 From 3344767d320b8881b6fa9a8ce5e1d9b7c852c9f1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Dec 2024 10:23:55 -0700 Subject: image: Add a prototype for fit_image_get_phase() This function exists but is not exported. Add a prototype so it can be used elsewhere. Signed-off-by: Simon Glass --- include/image.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 9be5acd8158..bb15ef69871 100644 --- a/include/image.h +++ b/include/image.h @@ -1171,6 +1171,18 @@ int fit_image_get_data_size_unciphered(const void *fit, int noffset, int fit_image_get_data_and_size(const void *fit, int noffset, const void **data, size_t *size); +/** + * fit_image_get_phase() - Get the phase from a FIT image + * + * @fit: FIT to read from + * @offset: offset node to read + * @phasep: Returns phase, if any + * Return: 0 if read OK and *phasep is value, -ENOENT if there was no phase + * property in the node, other -ve value on other error + */ +int fit_image_get_phase(const void *fit, int offset, + enum image_phase_t *phasep); + /** * fit_get_data_node() - Get verified image data for an image * @fit: Pointer to the FIT format image header -- cgit v1.3.1 From 94ad46e2ae4e2566a8cbd4b8030a6efbcb6b17ba Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Dec 2024 10:23:56 -0700 Subject: boot: Allow FIT to fall back from best-match option When the best-match feature fails to find something, use the provided config name as a fallback. The allows SPL to select a suitable config when best-match is enabled. Signed-off-by: Simon Glass --- boot/image-fit.c | 19 ++++++++++--------- include/image.h | 4 +++- 2 files changed, 13 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/boot/image-fit.c b/boot/image-fit.c index 7d56f0b5e6e..439ff51edf6 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -1729,13 +1729,13 @@ int fit_conf_find_compat(const void *fit, const void *fdt) images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); if (confs_noffset < 0 || images_noffset < 0) { debug("Can't find configurations or images nodes.\n"); - return -1; + return -EINVAL; } fdt_compat = fdt_getprop(fdt, 0, "compatible", &fdt_compat_len); if (!fdt_compat) { debug("Fdt for comparison has no \"compatible\" property.\n"); - return -1; + return -ENXIO; } /* @@ -1812,7 +1812,7 @@ int fit_conf_find_compat(const void *fit, const void *fdt) } if (!best_match_offset) { debug("No match found.\n"); - return -1; + return -ENOENT; } return best_match_offset; @@ -2095,17 +2095,18 @@ int fit_image_load(struct bootm_headers *images, ulong addr, * fit_conf_get_node() will try to find default config node */ bootstage_mark(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME); - if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) { - cfg_noffset = fit_conf_find_compat(fit, gd_fdt_blob()); - } else { - cfg_noffset = fit_conf_get_node(fit, fit_uname_config); - } - if (cfg_noffset < 0) { + ret = -ENXIO; + if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) + ret = fit_conf_find_compat(fit, gd_fdt_blob()); + if (ret < 0 && ret != -EINVAL) + ret = fit_conf_get_node(fit, fit_uname_config); + if (ret < 0) { puts("Could not find configuration node\n"); bootstage_error(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME); return -ENOENT; } + cfg_noffset = ret; fit_base_uname_config = fdt_get_name(fit, cfg_noffset, NULL); printf(" Using '%s' configuration\n", fit_base_uname_config); diff --git a/include/image.h b/include/image.h index bb15ef69871..ab96510f62c 100644 --- a/include/image.h +++ b/include/image.h @@ -1411,7 +1411,9 @@ int fit_check_format(const void *fit, ulong size); * copied into the configuration node in the FIT image. This is required to * match configurations with compressed FDTs. * - * Returns: offset to the configuration to use if one was found, -1 otherwise + * Returns: offset to the configuration to use if one was found, -EINVAL if + * there a /configurations or /images node is missing, -ENOENT if no match was + * found, -ENXIO if the FDT node has no compatible string */ int fit_conf_find_compat(const void *fit, const void *fdt); -- cgit v1.3.1 From 290d0cf0c06e128a7f7d948fd54f0b22ee95aa62 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Dec 2024 10:24:05 -0700 Subject: spl: Drop use of uintptr_t U-Boot uses ulong for addresses. It is confusing to use uintptr_t in a few places, since it makes people wonder if the types are compatible. Change the few occurences in SPL to use ulong Signed-off-by: Simon Glass --- common/spl/spl_atf.c | 36 ++++++++++++++++++------------------ common/spl/spl_fit.c | 2 +- common/spl/spl_legacy.c | 8 ++++---- include/spl.h | 28 ++++++++++++++-------------- 4 files changed, 37 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index 0397b86a33b..8bc5db77395 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -41,9 +41,9 @@ struct bl2_to_bl31_params_mem_v2 { struct entry_point_info bl31_ep_info; }; -struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { static struct bl2_to_bl31_params_mem bl31_params_mem; struct bl31_params *bl2_to_bl31_params; @@ -100,17 +100,17 @@ struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, return bl2_to_bl31_params; } -__weak struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +__weak struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { return bl2_plat_get_bl31_params_default(bl32_entry, bl33_entry, fdt_addr); } -struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { static struct bl2_to_bl31_params_mem_v2 bl31_params_mem; struct bl_params *bl_params; @@ -173,9 +173,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, return bl_params; } -__weak struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +__weak struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { return bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, fdt_addr); @@ -188,8 +188,8 @@ static inline void raw_write_daif(unsigned int daif) typedef void __noreturn (*atf_entry_t)(struct bl31_params *params, void *plat_params); -static void __noreturn bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, - uintptr_t bl33_entry, uintptr_t fdt_addr) +static void __noreturn bl31_entry(ulong bl31_entry, ulong bl32_entry, + ulong bl33_entry, ulong fdt_addr) { atf_entry_t atf_entry = (atf_entry_t)bl31_entry; void *bl31_params; @@ -238,7 +238,7 @@ static int spl_fit_images_find(void *blob, int os) return -FDT_ERR_NOTFOUND; } -uintptr_t spl_fit_images_get_entry(void *blob, int node) +ulong spl_fit_images_get_entry(void *blob, int node) { ulong val; int ret; @@ -253,10 +253,10 @@ uintptr_t spl_fit_images_get_entry(void *blob, int node) void __noreturn spl_invoke_atf(struct spl_image_info *spl_image) { - uintptr_t bl32_entry = 0; - uintptr_t bl33_entry = CONFIG_TEXT_BASE; + ulong bl32_entry = 0; + ulong bl33_entry = CONFIG_TEXT_BASE; void *blob = spl_image->fdt_addr; - uintptr_t platform_param = (uintptr_t)blob; + ulong platform_param = (ulong)blob; int node; /* diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 3160f573bfb..ef40a50082c 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -862,7 +862,7 @@ int spl_load_fit_image(struct spl_image_info *spl_image, { struct bootm_headers images; const char *fit_uname_config = NULL; - uintptr_t fdt_hack; + ulong fdt_hack; const char *uname; ulong fw_data = 0, dt_data = 0, img_data = 0; ulong fw_len = 0, dt_len = 0, img_len = 0; diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 9252b3a3de0..b3efb3e630e 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -16,11 +16,11 @@ #define LZMA_LEN (1 << 20) -static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size) +static void spl_parse_legacy_validate(ulong start, ulong size) { - uintptr_t spl_start = (uintptr_t)_start; - uintptr_t spl_end = (uintptr_t)&_image_binary_end; - uintptr_t end = start + size; + ulong spl_start = (ulong)_start; + ulong spl_end = (ulong)&_image_binary_end; + ulong end = start + size; if ((start >= spl_start && start < spl_end) || (end > spl_start && end <= spl_end) || diff --git a/include/spl.h b/include/spl.h index 269e36bb441..43b344dbc55 100644 --- a/include/spl.h +++ b/include/spl.h @@ -268,8 +268,8 @@ enum spl_sandbox_flags { struct spl_image_info { const char *name; u8 os; - uintptr_t load_addr; - uintptr_t entry_point; + ulong load_addr; + ulong entry_point; #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) void *fdt_addr; #endif @@ -951,9 +951,9 @@ void __noreturn spl_invoke_atf(struct spl_image_info *spl_image); * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_default() - prepare params for bl31. @@ -972,9 +972,9 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_v2() - return params for bl31 @@ -988,9 +988,9 @@ struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_v2_default() - prepare params for bl31. @@ -1007,9 +1007,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * spl_optee_entry - entry function for optee * -- cgit v1.3.1 From f0315babfb43c6d1f5d4ff0ea7554ec2c27bf7b1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Dec 2024 10:24:12 -0700 Subject: hash: Plumb crc8 into the hash functions Add an entry for crc8, with watchdog handling. Signed-off-by: Simon Glass --- common/hash.c | 8 ++++++++ include/u-boot/crc.h | 3 +++ lib/crc8.c | 6 ++++++ 3 files changed, 17 insertions(+) (limited to 'include') diff --git a/common/hash.c b/common/hash.c index db6925d6782..5d389420eff 100644 --- a/common/hash.c +++ b/common/hash.c @@ -304,6 +304,14 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc16_ccitt, .hash_finish = hash_finish_crc16_ccitt, }, +#if CONFIG_IS_ENABLED(CRC8) + { + .name = "crc8", + .digest_size = 1, + .chunk_size = CHUNKSZ_CRC32, + .hash_func_ws = crc8_wd_buf, + }, +#endif #if CONFIG_IS_ENABLED(CRC32) { .name = "crc32", diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 5174bd7ac41..b2badaf6a97 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -25,6 +25,9 @@ */ unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len); +void crc8_wd_buf(const unsigned char *input, unsigned int len, + unsigned char output[1], unsigned int chunk_sz); + /* lib/crc16.c - 16 bit CRC with polynomial x^16 + x^15 + x^2 + 1 */ uint16_t crc16(uint16_t crc, const unsigned char *buffer, size_t len); diff --git a/lib/crc8.c b/lib/crc8.c index 20d46d16147..811e19917b4 100644 --- a/lib/crc8.c +++ b/lib/crc8.c @@ -32,3 +32,9 @@ unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) return crc; } + +void crc8_wd_buf(const unsigned char *input, unsigned int len, + unsigned char output[1], unsigned int chunk_sz) +{ + *output = crc8(0, input, len); +} -- cgit v1.3.1 From a33185173dce550d6ecb96b7fa625bb5e2183d66 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 12 Dec 2024 21:07:26 -0600 Subject: Revert "Merge patch series "vbe: Series part E"" This reverts commit 1fdf53ace13f745fe8ad4d2d4e79eed98088d555, reversing changes made to e5aef1bbf11412eebd4c242b46adff5301353c30. I had missed that this caused too much size growth on rcar3_salvator-x. Signed-off-by: Tom Rini --- boot/Kconfig | 71 +------------------------------------------ boot/bootdev-uclass.c | 10 ++---- boot/image-fit.c | 29 +++++++----------- common/hash.c | 8 ----- common/malloc_simple.c | 3 +- common/spl/Kconfig.vpl | 17 ----------- common/spl/spl.c | 15 ++++----- common/spl/spl_atf.c | 36 +++++++++++----------- common/spl/spl_fit.c | 12 ++------ common/spl/spl_legacy.c | 8 ++--- common/spl/spl_mmc.c | 6 ++-- configs/sandbox_vpl_defconfig | 2 -- include/image.h | 16 +--------- include/spl.h | 28 ++++++++--------- include/u-boot/crc.h | 3 -- lib/Kconfig | 53 -------------------------------- lib/Makefile | 12 ++++---- lib/crc8.c | 6 ---- 18 files changed, 68 insertions(+), 267 deletions(-) (limited to 'include') diff --git a/boot/Kconfig b/boot/Kconfig index 20935a269c6..99dcedcc840 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -163,18 +163,6 @@ config SPL_FIT select SPL_HASH select SPL_OF_LIBFDT -config VPL_FIT - bool "Support Flattened Image Tree within VPL" - depends on VPL - select VPL_HASH - select VPL_OF_LIBFDT - -config TPL_FIT - bool "Support Flattened Image Tree within TPL" - depends on TPL - select TPL_HASH - select TPL_OF_LIBFDT - config SPL_FIT_PRINT bool "Support FIT printing within SPL" depends on SPL_FIT @@ -280,28 +268,6 @@ config SPL_LOAD_FIT_FULL particular it can handle selecting from multiple device tree and passing the correct one to U-Boot. -config TPL_LOAD_FIT - bool "Enable TPL loading U-Boot as a FIT (basic fitImage features)" - depends on TPL - select TPL_FIT - help - Normally with the SPL framework a legacy image is generated as part - of the build. This contains U-Boot along with information as to - where it should be loaded. This option instead enables generation - of a FIT (Flat Image Tree) which provides more flexibility. In - particular it can handle selecting from multiple device tree - and passing the correct one to U-Boot. - - This path has the following limitations: - - 1. "loadables" images, other than FDTs, which do not have a "load" - property will not be loaded. This limitation also applies to FPGA - images with the correct "compatible" string. - 2. For FPGA images, the supported "compatible" list is in the - doc/uImage.FIT/source_file_format.txt. - 3. FDTs are only loaded for images with an "os" property of "u-boot". - "linux" images are also supported with Falcon boot mode. - config SPL_FIT_IMAGE_POST_PROCESS bool "Enable post-processing of FIT artifacts after loading by the SPL" depends on SPL_LOAD_FIT @@ -326,22 +292,6 @@ config VPL_FIT select VPL_HASH select VPL_OF_LIBFDT -config VPL_LOAD_FIT - bool "Enable VPL loading U-Boot as a FIT (basic fitImage features)" - select VPL_FIT - default y - -config VPL_LOAD_FIT_FULL - bool "Enable SPL loading U-Boot as a FIT (full fitImage features)" - select VPL_FIT - help - Normally with the SPL framework a legacy image is generated as part - of the build. This contains U-Boot along with information as to - where it should be loaded. This option instead enables generation - of a FIT (Flat Image Tree) which provides more flexibility. In - particular it can handle selecting from multiple device tree - and passing the correct one to U-Boot. - config VPL_FIT_PRINT bool "Support FIT printing within VPL" depends on VPL_FIT @@ -670,15 +620,6 @@ config VPL_BOOTMETH_VBE supports selection of various firmware components, selection of an OS to boot as well as updating these using fwupd. -config TPL_BOOTMETH_VBE - bool "Bootdev support for Verified Boot for Embedded (TPL)" - depends on TPL - default y - help - Enables support for VBE boot. This is a standard boot method which - supports selection of various firmware components, seleciton of an OS to - boot as well as updating these using fwupd. - if BOOTMETH_VBE config BOOTMETH_VBE_REQUEST @@ -704,8 +645,6 @@ config SPL_BOOTMETH_VBE_REQUEST config BOOTMETH_VBE_SIMPLE bool "Bootdev support for VBE 'simple' method" default y - imply SPL_CRC8 if SPL - imply VPL_CRC8 if VPL help Enables support for VBE 'simple' boot. This allows updating a single firmware image in boot media such as MMC. It does not support any sort @@ -759,15 +698,7 @@ config VPL_BOOTMETH_VBE_SIMPLE_FW This option enabled for VPL, since it is the phase where the SPL decision is made. -config TPL_BOOTMETH_VBE_SIMPLE_FW - bool "Bootdev support for VBE 'simple' method firmware phase (TPL)" - depends on VPL - default y - help - Enables support for the firmware parts of VBE 'simple' boot, in TPL. - TPL loads a FIT containing the VPL binary and a suitable devicetree. - -endif # BOOTMETH_VBE_SIMPLE +endif # BOOTMETH_VBE config EXPO bool "Support for expos - groups of scenes displaying a UI" diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 2e61c853142..64ec4fde493 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -279,13 +278,8 @@ int bootdev_setup_for_sibling_blk(struct udevice *blk, const char *drv_name) int ret, len; len = bootdev_get_suffix_start(blk, ".blk"); - if (xpl_phase() < PHASE_BOARD_R) { - strlcpy(dev_name, blk->name, sizeof(dev_name) - 5); - strcat(dev_name, ".sib"); - } else { - snprintf(dev_name, sizeof(dev_name), "%.*s.%s", len, blk->name, - "bootdev"); - } + snprintf(dev_name, sizeof(dev_name), "%.*s.%s", len, blk->name, + "bootdev"); parent = dev_get_parent(blk); ret = device_find_child_by_name(parent, dev_name, &dev); diff --git a/boot/image-fit.c b/boot/image-fit.c index db7fb61bca9..7d56f0b5e6e 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -1729,13 +1729,13 @@ int fit_conf_find_compat(const void *fit, const void *fdt) images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); if (confs_noffset < 0 || images_noffset < 0) { debug("Can't find configurations or images nodes.\n"); - return -EINVAL; + return -1; } fdt_compat = fdt_getprop(fdt, 0, "compatible", &fdt_compat_len); if (!fdt_compat) { debug("Fdt for comparison has no \"compatible\" property.\n"); - return -ENXIO; + return -1; } /* @@ -1812,7 +1812,7 @@ int fit_conf_find_compat(const void *fit, const void *fdt) } if (!best_match_offset) { debug("No match found.\n"); - return -ENOENT; + return -1; } return best_match_offset; @@ -2095,18 +2095,17 @@ int fit_image_load(struct bootm_headers *images, ulong addr, * fit_conf_get_node() will try to find default config node */ bootstage_mark(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME); - ret = -ENXIO; - if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) - ret = fit_conf_find_compat(fit, gd_fdt_blob()); - if (ret < 0 && ret != -EINVAL) - ret = fit_conf_get_node(fit, fit_uname_config); - if (ret < 0) { + if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) { + cfg_noffset = fit_conf_find_compat(fit, gd_fdt_blob()); + } else { + cfg_noffset = fit_conf_get_node(fit, fit_uname_config); + } + if (cfg_noffset < 0) { puts("Could not find configuration node\n"); bootstage_error(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME); return -ENOENT; } - cfg_noffset = ret; fit_base_uname_config = fdt_get_name(fit, cfg_noffset, NULL); printf(" Using '%s' configuration\n", fit_base_uname_config); @@ -2226,7 +2225,6 @@ int fit_image_load(struct bootm_headers *images, ulong addr, data = map_to_sysmem(buf); load = data; if (load_op == FIT_LOAD_IGNORED) { - log_debug("load_op: not loading\n"); /* Don't load */ } else if (fit_image_get_load(fit, noffset, &load)) { if (load_op == FIT_LOAD_REQUIRED) { @@ -2263,13 +2261,10 @@ int fit_image_load(struct bootm_headers *images, ulong addr, /* Kernel images get decompressed later in bootm_load_os(). */ if (!fit_image_get_comp(fit, noffset, &comp) && comp != IH_COMP_NONE && - load_op != FIT_LOAD_IGNORED && !(image_type == IH_TYPE_KERNEL || image_type == IH_TYPE_KERNEL_NOLOAD || image_type == IH_TYPE_RAMDISK)) { ulong max_decomp_len = len * 20; - - log_debug("decompressing image\n"); if (load == data) { loadbuf = malloc(max_decomp_len); load = map_to_sysmem(loadbuf); @@ -2284,7 +2279,6 @@ int fit_image_load(struct bootm_headers *images, ulong addr, } len = load_end - load; } else if (load != data) { - log_debug("copying\n"); loadbuf = map_sysmem(load, len); memcpy(loadbuf, buf, len); } @@ -2294,9 +2288,8 @@ int fit_image_load(struct bootm_headers *images, ulong addr, " please fix your .its file!\n"); /* verify that image data is a proper FDT blob */ - if (load_op != FIT_LOAD_IGNORED && image_type == IH_TYPE_FLATDT && - fdt_check_header(loadbuf)) { - puts("Subimage data is not a FDT\n"); + if (image_type == IH_TYPE_FLATDT && fdt_check_header(loadbuf)) { + puts("Subimage data is not a FDT"); return -ENOEXEC; } diff --git a/common/hash.c b/common/hash.c index 5d389420eff..db6925d6782 100644 --- a/common/hash.c +++ b/common/hash.c @@ -304,14 +304,6 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc16_ccitt, .hash_finish = hash_finish_crc16_ccitt, }, -#if CONFIG_IS_ENABLED(CRC8) - { - .name = "crc8", - .digest_size = 1, - .chunk_size = CHUNKSZ_CRC32, - .hash_func_ws = crc8_wd_buf, - }, -#endif #if CONFIG_IS_ENABLED(CRC32) { .name = "crc32", diff --git a/common/malloc_simple.c b/common/malloc_simple.c index f0f90a095bd..5a8ec538f8f 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -26,8 +26,7 @@ static void *alloc_simple(size_t bytes, int align) log_debug("size=%lx, ptr=%lx, limit=%x: ", (ulong)bytes, new_ptr, gd->malloc_limit); if (new_ptr > gd->malloc_limit) { - log_err("alloc space exhausted ptr %lx limit %x\n", new_ptr, - gd->malloc_limit); + log_err("alloc space exhausted\n"); return NULL; } diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl index eb57dfabea5..d06f36d4ee4 100644 --- a/common/spl/Kconfig.vpl +++ b/common/spl/Kconfig.vpl @@ -222,29 +222,12 @@ config VPL_SPI_FLASH_SUPPORT lines). This enables the drivers in drivers/mtd/spi as part of a VPL build. This normally requires VPL_SPI_SUPPORT. -config VPL_SYS_MALLOC_SIMPLE - bool "Only use malloc_simple functions in the VPL" - default y - help - Say Y here to only use the *_simple malloc functions from - malloc_simple.c, rather then using the versions from dlmalloc.c; - this will make the VPL binary smaller at the cost of more heap - usage as the *_simple malloc functions do not re-use free-ed mem. - config VPL_TEXT_BASE hex "VPL Text Base" default 0x0 help The address in memory that VPL will be running from. -config VPL_MAX_SIZE - hex "Maximum size (in bytes) for the VPL stage" - default 0x2e000 if ROCKCHIP_RK3399 - default 0x0 - help - The maximum size (in bytes) of the TPL stage. This size is determined - by the amount of internal SRAM memory. - config VPL_BINMAN_SYMBOLS bool "Declare binman symbols in VPL" depends on VPL_FRAMEWORK && BINMAN diff --git a/common/spl/spl.c b/common/spl/spl.c index ad31a2f8b6c..1ceb63daf31 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -631,13 +631,10 @@ static int boot_from_devices(struct spl_image_info *spl_image, "Unsupported Boot Device!\n"); } } - if (loader) { - ret = spl_load_image(spl_image, loader); - if (!ret) { - spl_image->boot_device = bootdev; - return 0; - } - printf("Error: %d\n", ret); + if (loader && + !spl_load_image(spl_image, loader)) { + spl_image->boot_device = bootdev; + return 0; } } } @@ -836,7 +833,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) */ void preloader_console_init(void) { -#if CONFIG_IS_ENABLED(SERIAL) +#ifdef CONFIG_SPL_SERIAL gd->baudrate = CONFIG_BAUDRATE; serial_init(); /* serial communications setup */ @@ -895,7 +892,7 @@ __weak void spl_relocate_stack_check(void) */ ulong spl_relocate_stack_gd(void) { -#if CONFIG_IS_ENABLED(STACK_R) +#ifdef CONFIG_SPL_STACK_R gd_t *new_gd; ulong ptr = CONFIG_SPL_STACK_R_ADDR; diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index 8bc5db77395..0397b86a33b 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -41,9 +41,9 @@ struct bl2_to_bl31_params_mem_v2 { struct entry_point_info bl31_ep_info; }; -struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr) +struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr) { static struct bl2_to_bl31_params_mem bl31_params_mem; struct bl31_params *bl2_to_bl31_params; @@ -100,17 +100,17 @@ struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, return bl2_to_bl31_params; } -__weak struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr) +__weak struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr) { return bl2_plat_get_bl31_params_default(bl32_entry, bl33_entry, fdt_addr); } -struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr) +struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr) { static struct bl2_to_bl31_params_mem_v2 bl31_params_mem; struct bl_params *bl_params; @@ -173,9 +173,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, return bl_params; } -__weak struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr) +__weak struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr) { return bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, fdt_addr); @@ -188,8 +188,8 @@ static inline void raw_write_daif(unsigned int daif) typedef void __noreturn (*atf_entry_t)(struct bl31_params *params, void *plat_params); -static void __noreturn bl31_entry(ulong bl31_entry, ulong bl32_entry, - ulong bl33_entry, ulong fdt_addr) +static void __noreturn bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, + uintptr_t bl33_entry, uintptr_t fdt_addr) { atf_entry_t atf_entry = (atf_entry_t)bl31_entry; void *bl31_params; @@ -238,7 +238,7 @@ static int spl_fit_images_find(void *blob, int os) return -FDT_ERR_NOTFOUND; } -ulong spl_fit_images_get_entry(void *blob, int node) +uintptr_t spl_fit_images_get_entry(void *blob, int node) { ulong val; int ret; @@ -253,10 +253,10 @@ ulong spl_fit_images_get_entry(void *blob, int node) void __noreturn spl_invoke_atf(struct spl_image_info *spl_image) { - ulong bl32_entry = 0; - ulong bl33_entry = CONFIG_TEXT_BASE; + uintptr_t bl32_entry = 0; + uintptr_t bl33_entry = CONFIG_TEXT_BASE; void *blob = spl_image->fdt_addr; - ulong platform_param = (ulong)blob; + uintptr_t platform_param = (uintptr_t)blob; int node; /* diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index ac8462577ff..3160f573bfb 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -190,7 +190,7 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, /** * load_simple_fit(): load the image described in a certain FIT node * @info: points to information about the device to load data from - * @fit_offset: the offset of the FIT image on the device + * @sector: the start sector of the FIT image on the device * @ctx: points to the FIT context structure * @node: offset of the DT node describing the image to load (relative * to @fit) @@ -243,14 +243,11 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, if (!fit_image_get_data_position(fit, node, &offset)) { external_data = true; } else if (!fit_image_get_data_offset(fit, node, &offset)) { - log_debug("read offset %x = offset from fit %lx\n", - offset, (ulong)offset + ctx->ext_data_offset); offset += ctx->ext_data_offset; external_data = true; } if (external_data) { - ulong read_offset; void *src_ptr; /* External data */ @@ -273,10 +270,6 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, overhead = get_aligned_image_overhead(info, offset); size = get_aligned_image_size(info, length, offset); - read_offset = fit_offset + get_aligned_image_offset(info, - offset); - log_debug("reading from offset %x / %lx size %lx to %p: ", - offset, read_offset, size, src_ptr); if (info->read(info, fit_offset + @@ -343,7 +336,6 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, else image_info->entry_point = FDT_ERROR; } - log_debug("- done loading\n"); upl_add_image(fit, node, load_addr, length); @@ -870,7 +862,7 @@ int spl_load_fit_image(struct spl_image_info *spl_image, { struct bootm_headers images; const char *fit_uname_config = NULL; - ulong fdt_hack; + uintptr_t fdt_hack; const char *uname; ulong fw_data = 0, dt_data = 0, img_data = 0; ulong fw_len = 0, dt_len = 0, img_len = 0; diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index b3efb3e630e..9252b3a3de0 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -16,11 +16,11 @@ #define LZMA_LEN (1 << 20) -static void spl_parse_legacy_validate(ulong start, ulong size) +static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size) { - ulong spl_start = (ulong)_start; - ulong spl_end = (ulong)&_image_binary_end; - ulong end = start + size; + uintptr_t spl_start = (uintptr_t)_start; + uintptr_t spl_end = (uintptr_t)&_image_binary_end; + uintptr_t end = start + size; if ((start >= spl_start && start < spl_end) || (end > spl_start && end <= spl_end) || diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index fe4230170a0..1f696593216 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -81,10 +81,8 @@ static int spl_mmc_find_device(struct mmc **mmcp, int mmc_dev) struct uclass *uc; log_debug("Selecting MMC dev %d; seqs:\n", mmc_dev); - if (_LOG_DEBUG) { - uclass_id_foreach_dev(UCLASS_MMC, dev, uc) - log_debug("%d: %s\n", dev_seq(dev), dev->name); - } + uclass_id_foreach_dev(UCLASS_MMC, dev, uc) + log_debug("%d: %s\n", dev_seq(dev), dev->name); ret = mmc_init_device(mmc_dev); #else ret = mmc_initialize(NULL); diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 46329395ba5..84df2b85260 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -27,8 +27,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_SPL_LOAD_FIT=y -# CONFIG_TPL_BOOTMETH_VBE is not set -# CONFIG_TPL_BOOTMETH_VBE_SIMPLE_FW is not set CONFIG_UPL=y CONFIG_UPL_IN=y CONFIG_BOOTSTAGE=y diff --git a/include/image.h b/include/image.h index ab96510f62c..9be5acd8158 100644 --- a/include/image.h +++ b/include/image.h @@ -1171,18 +1171,6 @@ int fit_image_get_data_size_unciphered(const void *fit, int noffset, int fit_image_get_data_and_size(const void *fit, int noffset, const void **data, size_t *size); -/** - * fit_image_get_phase() - Get the phase from a FIT image - * - * @fit: FIT to read from - * @offset: offset node to read - * @phasep: Returns phase, if any - * Return: 0 if read OK and *phasep is value, -ENOENT if there was no phase - * property in the node, other -ve value on other error - */ -int fit_image_get_phase(const void *fit, int offset, - enum image_phase_t *phasep); - /** * fit_get_data_node() - Get verified image data for an image * @fit: Pointer to the FIT format image header @@ -1411,9 +1399,7 @@ int fit_check_format(const void *fit, ulong size); * copied into the configuration node in the FIT image. This is required to * match configurations with compressed FDTs. * - * Returns: offset to the configuration to use if one was found, -EINVAL if - * there a /configurations or /images node is missing, -ENOENT if no match was - * found, -ENXIO if the FDT node has no compatible string + * Returns: offset to the configuration to use if one was found, -1 otherwise */ int fit_conf_find_compat(const void *fit, const void *fdt); diff --git a/include/spl.h b/include/spl.h index 43b344dbc55..269e36bb441 100644 --- a/include/spl.h +++ b/include/spl.h @@ -268,8 +268,8 @@ enum spl_sandbox_flags { struct spl_image_info { const char *name; u8 os; - ulong load_addr; - ulong entry_point; + uintptr_t load_addr; + uintptr_t entry_point; #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) void *fdt_addr; #endif @@ -951,9 +951,9 @@ void __noreturn spl_invoke_atf(struct spl_image_info *spl_image); * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr); /** * bl2_plat_get_bl31_params_default() - prepare params for bl31. @@ -972,9 +972,9 @@ struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr); /** * bl2_plat_get_bl31_params_v2() - return params for bl31 @@ -988,9 +988,9 @@ struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr); /** * bl2_plat_get_bl31_params_v2_default() - prepare params for bl31. @@ -1007,9 +1007,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, - ulong bl33_entry, - ulong fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr); /** * spl_optee_entry - entry function for optee * diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index b2badaf6a97..5174bd7ac41 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -25,9 +25,6 @@ */ unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len); -void crc8_wd_buf(const unsigned char *input, unsigned int len, - unsigned char output[1], unsigned int chunk_sz); - /* lib/crc16.c - 16 bit CRC with polynomial x^16 + x^15 + x^2 + 1 */ uint16_t crc16(uint16_t crc, const unsigned char *buffer, size_t len); diff --git a/lib/Kconfig b/lib/Kconfig index 8f1a96d98c4..0b089814d14 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -728,24 +728,6 @@ config SPL_CRC8 checksum with feedback to produce an 8-bit result. The code is small and it does not require a lookup table (unlike CRC32). -config TPL_CRC8 - bool "Support CRC8 in TPL" - depends on TPL - help - Enables CRC8 support in TPL. This is not normally required. CRC8 is - a simple and fast checksumming algorithm which does a bytewise - checksum with feedback to produce an 8-bit result. The code is small - and it does not require a lookup table (unlike CRC32). - -config VPL_CRC8 - bool "Support CRC8 in VPL" - depends on VPL - help - Enables CRC8 support in VPL. This is not normally required. CRC8 is - a simple and fast checksumming algorithm which does a bytewise - checksum with feedback to produce an 8-bit result. The code is small - and it does not require a lookup table (unlike CRC32). - config SPL_CRC16 bool "Support CRC16 in SPL" depends on SPL @@ -859,36 +841,12 @@ config SPL_LZ4 fast compression and decompression speed. It belongs to the LZ77 family of byte-oriented compression schemes. -config TPL_LZ4 - bool "Enable LZ4 decompression support in TPL" - depends on TPL - help - This enables support for the LZ4 decompression algorithm in TPL. LZ4 - is a lossless data compression algorithm that is focused on - fast compression and decompression speed. It belongs to the LZ77 - family of byte-oriented compression schemes. - -config VPL_LZ4 - bool "Enable LZ4 decompression support in VPL" - depends on VPL - help - This enables support for the LZ4 decompression algorithm in VPL. LZ4 - is a lossless data compression algorithm that is focused on - fast compression and decompression speed. It belongs to the LZ77 - family of byte-oriented compression schemes. - config SPL_LZMA bool "Enable LZMA decompression support for SPL build" depends on SPL help This enables support for LZMA compression algorithm for SPL boot. -config TPL_LZMA - bool "Enable LZMA decompression support for TPL build" - depends on TPL - help - This enables support for LZMA compression algorithm for TPL boot. - config VPL_LZMA bool "Enable LZMA decompression support for VPL build" default y if LZMA @@ -907,22 +865,11 @@ config SPL_GZIP help This enables support for the GZIP compression algorithm for SPL boot. -config TPL_GZIP - bool "Enable gzip decompression support for SPL build" - select TPL_ZLIB - help - This enables support for the GZIP compression algorithm for TPL - config SPL_ZLIB bool help This enables compression lib for SPL boot. -config TPL_ZLIB - bool - help - This enables compression lib for TPL - config SPL_ZSTD bool "Enable Zstandard decompression support in SPL" depends on SPL diff --git a/lib/Makefile b/lib/Makefile index 5cb3278d2ef..d24ed629732 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -83,12 +83,12 @@ obj-$(CONFIG_$(XPL_)SHA512_LEGACY) += sha512.o obj-$(CONFIG_CRYPT_PW) += crypt/ obj-$(CONFIG_$(XPL_)ASN1_DECODER_LEGACY) += asn1_decoder.o -obj-$(CONFIG_$(PHASE_)ZLIB) += zlib/ -obj-$(CONFIG_$(PHASE_)ZSTD) += zstd/ -obj-$(CONFIG_$(PHASE_)GZIP) += gunzip.o -obj-$(CONFIG_$(PHASE_)LZO) += lzo/ -obj-$(CONFIG_$(PHASE_)LZMA) += lzma/ -obj-$(CONFIG_$(PHASE_)LZ4) += lz4_wrapper.o +obj-$(CONFIG_$(XPL_)ZLIB) += zlib/ +obj-$(CONFIG_$(XPL_)ZSTD) += zstd/ +obj-$(CONFIG_$(XPL_)GZIP) += gunzip.o +obj-$(CONFIG_$(XPL_)LZO) += lzo/ +obj-$(CONFIG_$(XPL_)LZMA) += lzma/ +obj-$(CONFIG_$(XPL_)LZ4) += lz4_wrapper.o obj-$(CONFIG_$(XPL_)LIB_RATIONAL) += rational.o diff --git a/lib/crc8.c b/lib/crc8.c index 811e19917b4..20d46d16147 100644 --- a/lib/crc8.c +++ b/lib/crc8.c @@ -32,9 +32,3 @@ unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) return crc; } - -void crc8_wd_buf(const unsigned char *input, unsigned int len, - unsigned char output[1], unsigned int chunk_sz) -{ - *output = crc8(0, input, len); -} -- cgit v1.3.1 From f9fc0b7a2e2e12ff845ea9db129c6664edc3e972 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 27 Nov 2024 13:17:35 +0100 Subject: board: phytec: k3: Add EFI capsule update support Implement EFI capsule update functionality for PHYTEC K3-based SoMs. These SoMs feature various flash device options, including eMMC, OSPI NOR, and uSD card at the board level. This update provides the necessary logic to enable EFI capsule updates across all three flash devices, ensuring flexible and robust firmware upgrade capabilities. The GUID is dynamically generated for the board, to get it: efidebug capsule esrt ======================================== ESRT: fw_resource_count=3 ESRT: fw_resource_count_max=3 ESRT: fw_resource_version=1 [entry 0]============================== ESRT: fw_class=C7D64D6D-10B2-54BC-A3BF-06A9DC3653D9 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success [entry 1]============================== ESRT: fw_class=09841C3F-F177-5D57-B1F6-754D92879205 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success [entry 2]============================== ESRT: fw_class=D11A9016-515E-503A-8872-3FF65384D0C4 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success ======================================== On the board (from uSD card containing capsule binaries at boot): load mmc 1:1 $loadaddr tiboot3-capsule.bin efidebug capsule update $loadaddr load mmc 1:1 $loadaddr tispl-capsule.bin efidebug capsule update $loadaddr load mmc 1:1 $loadaddr uboot-capsule.bin efidebug capsule update $loadaddr The binaries will be flashed to the flash device you are booted from. Signed-off-by: Wadim Egorov --- board/phytec/common/k3/board.c | 80 +++++++++++++++++++++++++++++++++++++++++ include/configs/phycore_am62x.h | 4 +++ include/configs/phycore_am64x.h | 4 +++ 3 files changed, 88 insertions(+) (limited to 'include') diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 346b2b6491a..065e446e154 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -4,15 +4,92 @@ * Author: Wadim Egorov */ +#include #include #include #include +#include #include #include #include #include "../am6_som_detection.h" +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +struct efi_fw_image fw_images[] = { + { + .fw_name = PHYCORE_AM6XX_FW_NAME_TIBOOT3, + .image_index = 1, + }, + { + .fw_name = PHYCORE_AM6XX_FW_NAME_SPL, + .image_index = 2, + }, + { + .fw_name = PHYCORE_AM6XX_FW_NAME_UBOOT, + .image_index = 3, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = NULL, + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +/** + * configure_capsule_updates() - Set up the DFU string for capsule updates + * + * Configures all three bootloader binaries for updates on the current + * booted flash device, which may be eMMC, OSPI NOR, or a uSD card. If + * booting from USB or Serial, capsule updates will be performed on the + * eMMC device. + * + * Note: Currently, eMMC hardware partitions are not differentiated; Updates + * are always applied to the first boot partition. + */ +void configure_capsule_updates(void) +{ + static char dfu_string[128] = { 0 }; + const char *dfu_raw = "tiboot3.bin raw 0x0 0x400 mmcpart 1;" + "tispl.bin raw 0x400 0x1000 mmcpart 1;" + "u-boot.img.raw raw 0x1400 0x2000 mmcpart 1"; + const char *dfu_fat = "tiboot3.bin fat 1 1;" + "tispl.bin fat 1 1;" + "u-boot.img fat 1 1"; + const char *dfu_spi = "tiboot3.bin part 1;" + "tispl.bin part 2;" + "u-boot.img part 3"; + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + snprintf(dfu_string, 128, "mmc 0=%s", dfu_raw); + break; + case BOOT_DEVICE_MMC2: + snprintf(dfu_string, 128, "mmc 1=%s", dfu_fat); + break; + case BOOT_DEVICE_SPI: + mtd_probe_devices(); + snprintf(dfu_string, 128, "mtd nor0=%s", dfu_spi); + break; + default: + snprintf(dfu_string, 128, "mmc 0=%s", dfu_raw); + break; + }; + + update_info.dfu_string = dfu_string; +} +#endif + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + #if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) int mmc_get_env_dev(void) { @@ -94,6 +171,9 @@ int board_late_init(void) } } + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + configure_capsule_updates(); + return 0; } #endif diff --git a/include/configs/phycore_am62x.h b/include/configs/phycore_am62x.h index 10b78b6f537..2bc6e7e16f9 100644 --- a/include/configs/phycore_am62x.h +++ b/include/configs/phycore_am62x.h @@ -12,4 +12,8 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM62X_TIBOOT3" +#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM62X_SPL" +#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM62X_UBOOT" + #endif /* __PHYCORE_AM62X_H */ diff --git a/include/configs/phycore_am64x.h b/include/configs/phycore_am64x.h index 9377db30a91..dd3dfa94270 100644 --- a/include/configs/phycore_am64x.h +++ b/include/configs/phycore_am64x.h @@ -12,4 +12,8 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM64X_TIBOOT3" +#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM64X_SPL" +#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM64X_UBOOT" + #endif /* __PHYCORE_AM64X_H */ -- cgit v1.3.1 From d13e67c24d167d965b8b733ed7b81712d02518e3 Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Mon, 18 Nov 2024 15:16:05 -0800 Subject: board: phytec: am62a7: Add PHYTEC phyCORE-AM62A7 SoM Add support for PHYTEC phyCORE-AM62A7 SoM. Supported features: - 2GB LPDDR4 RAM - eMMC - External SD - Ethernet - debug UART Signed-off-by: Garrett Giordano Reviewed-by: Wadim Egorov Reviewed-by: Tom Rini Reviewed-by: Bryan Brattlof --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/k3-am62a-phycore-som-binman.dtsi | 454 ++++ arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi | 2798 ++++++++++++++++++++ .../dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi | 252 ++ arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts | 137 + arch/arm/mach-k3/am62ax/Kconfig | 21 + board/phytec/phycore_am62ax/Kconfig | 37 + board/phytec/phycore_am62ax/MAINTAINERS | 14 + board/phytec/phycore_am62ax/Makefile | 6 + board/phytec/phycore_am62ax/board-cfg.yaml | 36 + board/phytec/phycore_am62ax/phycore-am62ax.c | 64 + board/phytec/phycore_am62ax/phycore_am62ax.env | 14 + board/phytec/phycore_am62ax/pm-cfg.yaml | 12 + board/phytec/phycore_am62ax/rm-cfg.yaml | 1047 ++++++++ board/phytec/phycore_am62ax/sec-cfg.yaml | 379 +++ board/phytec/phycore_am62ax/tifs-rm-cfg.yaml | 903 +++++++ configs/phycore_am62ax_a53_defconfig | 181 ++ configs/phycore_am62ax_r5_defconfig | 129 + include/configs/phycore_am62ax.h | 15 + 19 files changed, 6502 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62a-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62ax/Kconfig create mode 100644 board/phytec/phycore_am62ax/MAINTAINERS create mode 100644 board/phytec/phycore_am62ax/Makefile create mode 100644 board/phytec/phycore_am62ax/board-cfg.yaml create mode 100644 board/phytec/phycore_am62ax/phycore-am62ax.c create mode 100644 board/phytec/phycore_am62ax/phycore_am62ax.env create mode 100644 board/phytec/phycore_am62ax/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62ax/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62ax/sec-cfg.yaml create mode 100644 board/phytec/phycore_am62ax/tifs-rm-cfg.yaml create mode 100644 configs/phycore_am62ax_a53_defconfig create mode 100644 configs/phycore_am62ax_r5_defconfig create mode 100644 include/configs/phycore_am62ax.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 042282f3723..b92e5ce6d99 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1183,7 +1183,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \ k3-am625-verdin-r5.dtb \ k3-am625-r5-phycore-som-2gb.dtb -dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62A7) += \ + k3-am62a7-r5-sk.dtb \ + k3-am62a7-r5-phycore-som-2gb.dtb dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi new file mode 100644 index 00000000000..640361e0fd1 --- /dev/null +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Based on k3-am62a-sk-binman.dtsi + * + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_PHYCORE_AM62AX_R5 + +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + +&binman { + tiboot3-am62ax-hs-phycore-som.bin { + filename = "tiboot3-am62ax-hs-phycore-som.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c3a800>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62ax-hs-fs-phycore-som.bin { + filename = "tiboot3-am62ax-hs-fs-phycore-som.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c3a800>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62ax-gp-phycore-som.bin { + filename = "tiboot3-am62ax-gp-phycore-som.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x43c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = <0x67000>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x43c3a800>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; +#endif + +#ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53 + +#define SPL_AM62A7_PHYBOARD_LYRA_DTB "spl/dts/ti/k3-am62a7-phyboard-lyra-rdk.dtb" +#define AM62A7_PHYBOARD_LYRA_DTB "u-boot.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = ; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = ; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: ti-dm { + filename = "ti-dm.bin"; + }; + }; + + fdt-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am62a7_phyboard_lyra_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am62a7_phyboard_lyra_dtb: blob-ext { + filename = SPL_AM62A7_PHYBOARD_LYRA_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + firmware = "atf"; + loadables = "tee", "dm", "spl", + "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for AM62Ax board"; + }; + + fdt-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am62a7_phyboard_lyra_dtb>; + keyfile = "custMpk.pem"; + }; + am62a7_phyboard_lyra_dtb: blob-ext { + filename = AM62A7_PHYBOARD_LYRA_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + insert-template = <&ti_spl_unsigned_template>; + + fit { + images { + tifsstub-hs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { + ti-dm { + filename = "ti-dm.bin"; + }; + }; + + fdt-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + spl_am62a7_phyboard_lyra_dtb_unsigned: blob { + filename = SPL_AM62A7_PHYBOARD_LYRA_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + firmware = "atf"; + loadables = "tee", "dm", "spl", + "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + insert-template = <&u_boot_unsigned_template>; + + fit { + images { + uboot { + description = "U-Boot for AM62Ax board"; + }; + + fdt-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM62A7_PHYBOARD_LYRA_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62a7-phyboard-lyra-rdk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi b/arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi new file mode 100644 index 00000000000..00330b43fed --- /dev/null +++ b/arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi @@ -0,0 +1,2798 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * This file was generated with the + * AM62Ax SysConfig DDR Subsystem Register Configuration Tool v0.09.08 + * Fri Mar 24 2024 11:56:13 GMT-0700 (Pacific Daylight Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1866MHz + * Density (per channel): 8Gb + * Number of Ranks: 1 + */ + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004B4B +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x00720014 +#define DDRSS_CTL_51_DATA 0x09140050 +#define DDRSS_CTL_52_DATA 0x00004D22 +#define DDRSS_CTL_53_DATA 0x00720014 +#define DDRSS_CTL_54_DATA 0x09140050 +#define DDRSS_CTL_55_DATA 0x09004D22 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090F2005 +#define DDRSS_CTL_59_DATA 0x00001B13 +#define DDRSS_CTL_60_DATA 0x0E00FFCD +#define DDRSS_CTL_61_DATA 0x090F200F +#define DDRSS_CTL_62_DATA 0x00001B13 +#define DDRSS_CTL_63_DATA 0x0E00FFCD +#define DDRSS_CTL_64_DATA 0x0304200F +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x24232423 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x04464607 +#define DDRSS_CTL_69_DATA 0x03282803 +#define DDRSS_CTL_70_DATA 0x00002828 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x000E0803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x0000020B +#define DDRSS_CTL_77_DATA 0x00001C64 +#define DDRSS_CTL_78_DATA 0x0000020B +#define DDRSS_CTL_79_DATA 0x00001C64 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x00000007 +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000106 +#define DDRSS_CTL_84_DATA 0x00000386 +#define DDRSS_CTL_85_DATA 0x00000106 +#define DDRSS_CTL_86_DATA 0x00000386 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000E0005 +#define DDRSS_CTL_90_DATA 0x2608000E +#define DDRSS_CTL_91_DATA 0x0A050526 +#define DDRSS_CTL_92_DATA 0x1B0E0A03 +#define DDRSS_CTL_93_DATA 0x1B0E0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x000F000F +#define DDRSS_CTL_97_DATA 0x02190219 +#define DDRSS_CTL_98_DATA 0x02190219 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041C04 +#define DDRSS_CTL_103_DATA 0x0E0A0E0A +#define DDRSS_CTL_104_DATA 0x0A04041C +#define DDRSS_CTL_105_DATA 0x030E0A0E +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00071900 +#define DDRSS_CTL_127_DATA 0x00071900 +#define DDRSS_CTL_128_DATA 0x00071900 +#define DDRSS_CTL_129_DATA 0x00071900 +#define DDRSS_CTL_130_DATA 0x00071900 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000C6BC +#define DDRSS_CTL_133_DATA 0x00071900 +#define DDRSS_CTL_134_DATA 0x00071900 +#define DDRSS_CTL_135_DATA 0x00071900 +#define DDRSS_CTL_136_DATA 0x00071900 +#define DDRSS_CTL_137_DATA 0x00071900 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000C6BC +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00BB0176 +#define DDRSS_CTL_199_DATA 0x0E0E01D3 +#define DDRSS_CTL_200_DATA 0x000001D3 +#define DDRSS_CTL_201_DATA 0x00BB0176 +#define DDRSS_CTL_202_DATA 0x0E0E01D3 +#define DDRSS_CTL_203_DATA 0x000001D3 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000064 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000064 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000064 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000064 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000031 +#define DDRSS_CTL_231_DATA 0x000000B1 +#define DDRSS_CTL_232_DATA 0x000000B1 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x55005555 +#define DDRSS_CTL_258_DATA 0x00002755 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x074A0040 +#define DDRSS_CTL_316_DATA 0x00020038 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x0038074A +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x005E005E +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0xFFFFFFFF +#define DDRSS_CTL_327_DATA 0x00FFFF00 +#define DDRSS_CTL_328_DATA 0x0B000000 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C01 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0E081B1B +#define DDRSS_CTL_389_DATA 0x0008030E +#define DDRSS_CTL_390_DATA 0x0B12030E +#define DDRSS_CTL_391_DATA 0x0B120314 +#define DDRSS_CTL_392_DATA 0x12120814 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x07030701 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03050202 +#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_406_DATA 0x000038C8 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000FF84 +#define DDRSS_CTL_412_DATA 0x000237D0 +#define DDRSS_CTL_413_DATA 0x111F0402 +#define DDRSS_CTL_414_DATA 0x37200C0D +#define DDRSS_CTL_415_DATA 0x000038C8 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000FF84 +#define DDRSS_CTL_421_DATA 0x000237D0 +#define DDRSS_CTL_422_DATA 0x111F0402 +#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00050001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x05000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x00050500 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00001705 +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010500 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x01180118 +#define DDRSS_PI_178_DATA 0x00262601 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005E +#define DDRSS_PI_181_DATA 0x0002005E +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x0000000E +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x0000020B +#define DDRSS_PI_190_DATA 0x00001C64 +#define DDRSS_PI_191_DATA 0x0000020B +#define DDRSS_PI_192_DATA 0x04001C64 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00270027 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001B0043 +#define DDRSS_PI_210_DATA 0x001B0043 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301D3 +#define DDRSS_PI_214_DATA 0x010001D3 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01D40100 +#define DDRSS_PI_217_DATA 0x010001D4 +#define DDRSS_PI_218_DATA 0x01D401D4 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1C11090D +#define DDRSS_PI_223_DATA 0x1C110913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0021000D +#define DDRSS_PI_231_DATA 0x002101D3 +#define DDRSS_PI_232_DATA 0x000001D3 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00250204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000101 +#define DDRSS_PI_239_DATA 0x00250C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000101 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000062B +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x280F0000 +#define DDRSS_PI_249_DATA 0x24090023 +#define DDRSS_PI_250_DATA 0x0000E638 +#define DDRSS_PI_251_DATA 0x20070050 +#define DDRSS_PI_252_DATA 0x1B131B1C +#define DDRSS_PI_253_DATA 0x280F0000 +#define DDRSS_PI_254_DATA 0x24090023 +#define DDRSS_PI_255_DATA 0x0000E638 +#define DDRSS_PI_256_DATA 0x20070050 +#define DDRSS_PI_257_DATA 0x1B131B1C +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000038C8 +#define DDRSS_PI_262_DATA 0x000237D0 +#define DDRSS_PI_263_DATA 0x000038C8 +#define DDRSS_PI_264_DATA 0x000237D0 +#define DDRSS_PI_265_DATA 0x0219000F +#define DDRSS_PI_266_DATA 0x03030219 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x0000000F +#define DDRSS_PI_276_DATA 0x0005B18F +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000E94 +#define DDRSS_PI_280_DATA 0x00000219 +#define DDRSS_PI_281_DATA 0x0005B18F +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000E94 +#define DDRSS_PI_285_DATA 0x01000219 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x074A0040 +#define DDRSS_PI_289_DATA 0x00010038 +#define DDRSS_PI_290_DATA 0x074A0040 +#define DDRSS_PI_291_DATA 0x00000338 +#define DDRSS_PI_292_DATA 0x0028005D +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000064 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x000000B1 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x55000000 +#define DDRSS_PI_343_DATA 0x20162B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000064 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x000000B1 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x55000000 +#define DDRSS_PI_351_DATA 0x20162B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000031 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000064 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x000000B1 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x55000000 +#define DDRSS_PI_367_DATA 0x20162B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000064 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x000000B1 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x55000000 +#define DDRSS_PI_375_DATA 0x20162B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000031 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000064 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x000000B1 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x55000000 +#define DDRSS_PI_391_DATA 0x20162B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000064 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x000000B1 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x55000000 +#define DDRSS_PI_399_DATA 0x20162B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000031 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000064 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x000000B1 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x55000000 +#define DDRSS_PI_415_DATA 0x20162B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000064 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x000000B1 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x55000000 +#define DDRSS_PI_423_DATA 0x20162B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02040010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C32 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x011E0120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x000002DD +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x045D045D +#define DDRSS_PHY_114_DATA 0x045D045D +#define DDRSS_PHY_115_DATA 0x045D045D +#define DDRSS_PHY_116_DATA 0x045D045D +#define DDRSS_PHY_117_DATA 0x0000045D +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00B200A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02040010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C32 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x011E0120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x000002DD +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x045D045D +#define DDRSS_PHY_370_DATA 0x045D045D +#define DDRSS_PHY_371_DATA 0x045D045D +#define DDRSS_PHY_372_DATA 0x045D045D +#define DDRSS_PHY_373_DATA 0x0000045D +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00B200A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02040010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C32 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x011E0120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x000002DD +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x045D045D +#define DDRSS_PHY_626_DATA 0x045D045D +#define DDRSS_PHY_627_DATA 0x045D045D +#define DDRSS_PHY_628_DATA 0x045D045D +#define DDRSS_PHY_629_DATA 0x0000045D +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00B200A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02040010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C32 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x011E0120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x000002DD +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x045D045D +#define DDRSS_PHY_882_DATA 0x045D045D +#define DDRSS_PHY_883_DATA 0x045D045D +#define DDRSS_PHY_884_DATA 0x045D045D +#define DDRSS_PHY_885_DATA 0x0000045D +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00B200A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040006 diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi new file mode 100644 index 00000000000..41692c8f670 --- /dev/null +++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * phyCORE-AM62Ax dts file for SPLs + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62ax + */ + +#include "k3-am62a-phycore-som-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &main_timer0; + }; + + aliases { + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + memory@80000000 { + bootph-all; + }; +}; + +&cbass_main { + bootph-all; +}; + +&cbass_mcu { + bootph-all; +}; + +&cbass_wakeup { + bootph-all; +}; + +&chipid { + bootph-all; +}; + +&cpsw3g { + bootph-all; + ethernet-ports { + bootph-all; + }; +}; + +&cpsw3g_mdio { + bootph-all; +}; + +&cpsw3g_phy1 { + bootph-all; +}; + +&cpsw3g_phy3 { + bootph-all; +}; + +&cpsw_port1 { + bootph-all; +}; + +&cpsw_port2 { + bootph-all; +}; + +&dmsc { + bootph-all; +}; + +&dmss { + bootph-all; +}; + +&fss { + bootph-all; +}; + +&k3_pds { + bootph-all; +}; + +&k3_clks { + bootph-all; +}; + +&k3_reset { + bootph-all; +}; + +&main_bcdma { + bootph-all; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", + "ringrt", "cfg", "tchan", "rchan"; +}; + +&main_conf { + bootph-all; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_i2c0 { + bootph-all; +}; + +&main_i2c0_pins_default { + bootph-all; +}; + +&main_mdio1_pins_default { + bootph-all; +}; + +&main_mmc0_pins_default { + bootph-all; +}; + +&main_mmc1_pins_default { + bootph-all; +}; + +&main_pktdma { + bootph-all; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x20000>, + <0x00 0x484a0000 0x00 0x4000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan", "rflow"; +}; + +&main_pmx0 { + bootph-all; +}; + +&main_rgmii1_pins_default { + bootph-all; +}; + +&main_timer0 { + bootph-all; +}; + +&main_uart0 { + bootph-all; +}; + +&main_uart0_pins_default { + bootph-all; +}; + +&main_uart1 { + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; +}; + +&ospi0_pins_default { + bootph-all; +}; + +&ospi0 { + bootph-all; + flash@0 { + bootph-all; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00000 0x80000>; + }; + partition@80000 { + label = "ospi.tispl"; + reg = <0x080000 0x200000>; + }; + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + }; + }; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&sdhci0 { + bootph-all; +}; + +&sdhci1 { + bootph-all; +}; + +&secure_proxy_main { + bootph-all; +}; + +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; + +&vcc_3v3_mmc { + bootph-all; +}; + +&wkup_conf { + bootph-all; +}; + +&wkup_uart0 { + bootph-all; +}; diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts new file mode 100644 index 00000000000..0060c7a6934 --- /dev/null +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * phyCORE-AM62Ax dts file for R5 SPL + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62ax + */ + +#include "k3-am62a7-phyboard-lyra-rdk.dts" +#include "k3-am62a-phycore-som-ddr4-2gb.dtsi" +#include "k3-am62a-ddr.dtsi" + +#include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-pre-ram; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; + }; +}; + +&cbass_main { + bootph-pre-ram; + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x0 0x44860000 0x0 0x20000>, + <0x0 0x43600000 0x0 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-pre-ram; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_pmx0 { + bootph-pre-ram; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "okay"; + bootph-pre-ram; +}; + +&mcu_pmx0 { + status = "okay"; + bootph-pre-ram; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ + >; + bootph-pre-ram; + }; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "okay"; + bootph-pre-ram; +}; diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig index bbd5497f2ae..f8cdcdca57a 100644 --- a/arch/arm/mach-k3/am62ax/Kconfig +++ b/arch/arm/mach-k3/am62ax/Kconfig @@ -30,8 +30,29 @@ config TARGET_AM62A7_R5_EVM imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT +config TARGET_PHYCORE_AM62AX_A53 + bool "PHYTEC phyCORE-AM62Ax running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + imply OF_UPSTREAM + imply BOARD + imply SPL_BOARD + +config TARGET_PHYCORE_AM62AX_R5 + bool "PHYTEC phyCORE-AM62Ax running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + endchoice source "board/ti/am62ax/Kconfig" +source "board/phytec/phycore_am62ax/Kconfig" endif diff --git a/board/phytec/phycore_am62ax/Kconfig b/board/phytec/phycore_am62ax/Kconfig new file mode 100644 index 00000000000..516dc8e2020 --- /dev/null +++ b/board/phytec/phycore_am62ax/Kconfig @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR MIT +# +# Copyright (C) 2024 PHYTEC America LLC +# Author: Garrett Giordano + +if TARGET_PHYCORE_AM62AX_A53 + +config SYS_BOARD + default "phycore_am62ax" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_am62ax" + +source "board/phytec/common/Kconfig" + +endif + +if TARGET_PHYCORE_AM62AX_R5 + +config SYS_BOARD + default "phycore_am62ax" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_am62ax" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/phytec/common/Kconfig" + +endif diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS new file mode 100644 index 00000000000..3e4e2feff4e --- /dev/null +++ b/board/phytec/phycore_am62ax/MAINTAINERS @@ -0,0 +1,14 @@ +phyCORE-AM62ax +M: Garrett Giordano +M: Wadim Egorov +W: https://www.phytec.com/product/phycore-am62a +S: Maintained +F: arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +F: arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsit.dtsi +F: arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi +F: arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +F: board/phytec/phycore_am62ax/ +F: configs/phycore_am62ax_a53_defconfig +F: configs/phycore_am62ax_r5_defconfig +F: include/configs/phycore_am62ax.h +F: doc/board/phytec/phycore-am62ax.rst diff --git a/board/phytec/phycore_am62ax/Makefile b/board/phytec/phycore_am62ax/Makefile new file mode 100644 index 00000000000..61e7c92c1c9 --- /dev/null +++ b/board/phytec/phycore_am62ax/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR MIT +# +# Copyright (C) 2024 PHYTEC America LLC +# Author: Garrett Giordano + +obj-y += phycore-am62ax.o diff --git a/board/phytec/phycore_am62ax/board-cfg.yaml b/board/phytec/phycore_am62ax/board-cfg.yaml new file mode 100644 index 00000000000..a0930d69b88 --- /dev/null +++ b/board/phytec/phycore_am62ax/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62ax +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c new file mode 100644 index 00000000000..14b8959c07a --- /dev/null +++ b/board/phytec/phycore_am62ax/phycore-am62ax.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano + */ + +#include +#include +#include +#include + +#include "../common/am6_som_detection.h" + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 +#define CTRLMMR_USB1_PHY_CTRL 0x43004018 +#define CORE_VOLTAGE 0x80000000 + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + u32 val; + + /* Set USB0 PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB0_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Set USB1 PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB1_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB1_PHY_CTRL); + + if (IS_ENABLED(CONFIG_SPL_ETH)) + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); + + /* We have 32k crystal, so lets enable it */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); + writel(val, MCU_CTRL_LFXOSC_CTRL); + /* Add any TRIM needed for the crystal here.. */ + /* Make sure to mux up to take the SoC 32k from the crystal */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); +} +#endif diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env new file mode 100644 index 00000000000..77c5ea8d99a --- /dev/null +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -0,0 +1,14 @@ +fdtaddr=0x88000000 +loadaddr=0x82000000 +scriptaddr=0x80000000 +fdt_addr_r=0x88000000 +kernel_addr_r=0x82000000 +ramdisk_addr_r=0x88080000 +fdtoverlay_addr_r=0x89000000 + +fdtfile=CONFIG_DEFAULT_FDT_FILE +mmcdev=1 +mmcroot=2 +mmcpart=1 +console=ttyS2,115200n8 +earlycon=ns16550a,mmio32,0x02800000 diff --git a/board/phytec/phycore_am62ax/pm-cfg.yaml b/board/phytec/phycore_am62ax/pm-cfg.yaml new file mode 100644 index 00000000000..4031af2f4d3 --- /dev/null +++ b/board/phytec/phycore_am62ax/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62ax +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml new file mode 100644 index 00000000000..cbd087de797 --- /dev/null +++ b/board/phytec/phycore_am62ax/rm-cfg.yaml @@ -0,0 +1,1047 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62A +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 1064 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 16 + type: 64 + host_id: 12 + reserved: 0 + - + start_resource: 16 + num_resource: 4 + type: 64 + host_id: 35 + reserved: 0 + - + start_resource: 16 + num_resource: 4 + type: 64 + host_id: 36 + reserved: 0 + - + start_resource: 20 + num_resource: 22 + type: 64 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 16 + type: 192 + host_id: 12 + reserved: 0 + - + start_resource: 34 + num_resource: 2 + type: 192 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 320 + host_id: 12 + reserved: 0 + - + start_resource: 2 + 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type: 12738 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 12739 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 12288 + num_resource: 128 + type: 12813 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12829 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12830 + host_id: 128 + reserved: 0 diff --git a/board/phytec/phycore_am62ax/sec-cfg.yaml b/board/phytec/phycore_am62ax/sec-cfg.yaml new file mode 100644 index 00000000000..ae6939eee9a --- /dev/null +++ b/board/phytec/phycore_am62ax/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62ax +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - # 1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - # 1 + host_id: 0 + supervisor_host_id: 0 + - # 2 + host_id: 0 + supervisor_host_id: 0 + - # 3 + host_id: 0 + supervisor_host_id: 0 + - # 4 + host_id: 0 + supervisor_host_id: 0 + - # 5 + host_id: 0 + supervisor_host_id: 0 + - # 6 + host_id: 0 + supervisor_host_id: 0 + - # 7 + host_id: 0 + supervisor_host_id: 0 + - # 8 + host_id: 0 + supervisor_host_id: 0 + - # 9 + host_id: 0 + supervisor_host_id: 0 + - # 10 + host_id: 0 + supervisor_host_id: 0 + - # 11 + host_id: 0 + supervisor_host_id: 0 + - # 12 + host_id: 0 + supervisor_host_id: 0 + - # 13 + host_id: 0 + supervisor_host_id: 0 + - # 14 + host_id: 0 + supervisor_host_id: 0 + - # 15 + host_id: 0 + supervisor_host_id: 0 + - # 16 + host_id: 0 + supervisor_host_id: 0 + - # 17 + host_id: 0 + supervisor_host_id: 0 + - # 18 + host_id: 0 + supervisor_host_id: 0 + - # 19 + host_id: 0 + supervisor_host_id: 0 + - # 20 + host_id: 0 + supervisor_host_id: 0 + - # 21 + host_id: 0 + supervisor_host_id: 0 + - # 22 + host_id: 0 + supervisor_host_id: 0 + - # 23 + host_id: 0 + supervisor_host_id: 0 + - # 24 + host_id: 0 + supervisor_host_id: 0 + - # 25 + host_id: 0 + supervisor_host_id: 0 + - # 26 + host_id: 0 + supervisor_host_id: 0 + - # 27 + host_id: 0 + supervisor_host_id: 0 + - # 28 + host_id: 0 + supervisor_host_id: 0 + - # 29 + host_id: 0 + supervisor_host_id: 0 + - # 30 + host_id: 0 + supervisor_host_id: 0 + - # 31 + host_id: 0 + supervisor_host_id: 0 + - # 32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id: 0 + otp_entry: + - # 1 + host_id: 0 + host_perms: 0 + - # 2 + host_id: 0 + host_perms: 0 + - # 3 + host_id: 0 + host_perms: 0 + - # 4 + host_id: 0 + host_perms: 0 + - # 5 + host_id: 0 + host_perms: 0 + - # 6 + host_id: 0 + host_perms: 0 + - # 7 + host_id: 0 + host_perms: 0 + - # 8 + host_id: 0 + host_perms: 0 + - # 9 + host_id: 0 + host_perms: 0 + - # 10 + host_id: 0 + host_perms: 0 + - # 11 + host_id: 0 + host_perms: 0 + - # 12 + host_id: 0 + host_perms: 0 + - # 13 + host_id: 0 + host_perms: 0 + - # 14 + host_id: 0 + host_perms: 0 + - # 15 + host_id: 0 + host_perms: 0 + - # 16 + host_id: 0 + host_perms: 0 + - # 17 + host_id: 0 + host_perms: 0 + - # 18 + host_id: 0 + host_perms: 0 + - # 19 + host_id: 0 + host_perms: 0 + - # 20 + host_id: 0 + host_perms: 0 + - # 21 + host_id: 0 + host_perms: 0 + - # 22 + host_id: 0 + host_perms: 0 + - # 23 + host_id: 0 + host_perms: 0 + - # 24 + host_id: 0 + host_perms: 0 + - # 25 + host_id: 0 + host_perms: 0 + - # 26 + host_id: 0 + host_perms: 0 + - # 27 + host_id: 0 + host_perms: 0 + - # 28 + host_id: 0 + host_perms: 0 + - # 29 + host_id: 0 + host_perms: 0 + - # 30 + host_id: 0 + host_perms: 0 + - # 31 + host_id: 0 + host_perms: 0 + - # 32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..151cd599b1b --- /dev/null +++ b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml @@ -0,0 +1,903 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62AX +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 872 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1677 + host_id: 128 + reserved: 0 + - + start_resource: 54 + num_resource: 18 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 35 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 78 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - + start_resource: 80 + num_resource: 2 + type: 1678 + host_id: 128 + reserved: 0 + - + start_resource: 32 + num_resource: 12 + type: 1679 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 36 + reserved: 0 + - + start_resource: 50 + num_resource: 2 + type: 1679 + host_id: 30 + reserved: 0 + - + start_resource: 52 + num_resource: 2 + type: 1679 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1696 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1696 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1696 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1697 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1697 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 1697 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 12 + type: 1698 + host_id: 12 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 35 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 36 + reserved: 0 + - + start_resource: 18 + num_resource: 2 + type: 1698 + host_id: 30 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 1698 + host_id: 128 + reserved: 0 + - + start_resource: 6 + num_resource: 34 + type: 1802 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 36 + type: 1802 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 36 + type: 1802 + host_id: 36 + reserved: 0 + - + start_resource: 168 + num_resource: 8 + type: 1802 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 1024 + type: 1807 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 29 + type: 1808 + host_id: 128 + reserved: 0 + - + start_resource: 4608 + num_resource: 99 + type: 1809 + host_id: 128 + reserved: 0 + - + start_resource: 5120 + num_resource: 24 + type: 1810 + host_id: 128 + reserved: 0 + - + start_resource: 5632 + num_resource: 51 + type: 1811 + host_id: 128 + reserved: 0 + - + start_resource: 6144 + num_resource: 51 + type: 1812 + host_id: 128 + reserved: 0 + - + start_resource: 6656 + num_resource: 51 + type: 1813 + host_id: 128 + reserved: 0 + - + start_resource: 8192 + num_resource: 32 + type: 1814 + host_id: 128 + reserved: 0 + - + start_resource: 8704 + num_resource: 32 + type: 1815 + host_id: 128 + reserved: 0 + - + start_resource: 9216 + num_resource: 32 + type: 1816 + host_id: 128 + reserved: 0 + - + start_resource: 9728 + num_resource: 22 + type: 1817 + host_id: 128 + reserved: 0 + - + start_resource: 10240 + num_resource: 22 + type: 1818 + host_id: 128 + reserved: 0 + - + start_resource: 10752 + num_resource: 22 + type: 1819 + host_id: 128 + reserved: 0 + - + start_resource: 11264 + num_resource: 28 + type: 1820 + host_id: 128 + reserved: 0 + - + start_resource: 11776 + num_resource: 28 + type: 1821 + host_id: 128 + reserved: 0 + - + start_resource: 12288 + num_resource: 28 + type: 1822 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1936 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1936 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1936 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 30 + reserved: 0 + - + start_resource: 83 + num_resource: 8 + type: 1938 + host_id: 12 + reserved: 0 + - + start_resource: 91 + num_resource: 8 + type: 1939 + host_id: 12 + reserved: 0 + - + start_resource: 99 + num_resource: 10 + type: 1942 + host_id: 12 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 35 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 36 + reserved: 0 + - + start_resource: 112 + num_resource: 3 + type: 1942 + host_id: 30 + reserved: 0 + - + start_resource: 115 + num_resource: 3 + type: 1942 + host_id: 128 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 30 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1944 + host_id: 12 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1945 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1946 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1947 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1955 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1955 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1955 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 30 + reserved: 0 + - + start_resource: 27 + num_resource: 1 + type: 1957 + host_id: 12 + reserved: 0 + - + start_resource: 28 + num_resource: 1 + type: 1958 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1961 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1961 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1961 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1962 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 30 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 30 + reserved: 0 + - + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 + - + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12829 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12830 + host_id: 128 + reserved: 0 diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig new file mode 100644 index 00000000000..8148fd4ea7a --- /dev/null +++ b/configs/phycore_am62ax_a53_defconfig @@ -0,0 +1,181 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM62A7=y +CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_SOM_DETECTION_BLOCKS=y +CONFIG_TARGET_PHYCORE_AM62AX_A53=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-phyboard-lyra-rdk" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_ENV_OFFSET_REDUND=0x6c0000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTSTD_FULL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb" +CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62AX U-Boot A53 SPL" +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_SMC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV3028=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_SPL_DFU=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig new file mode 100644 index 00000000000..a71ebf0dc2c --- /dev/null +++ b/configs/phycore_am62ax_r5_defconfig @@ -0,0 +1,129 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62A7=y +CONFIG_TARGET_PHYCORE_AM62AX_R5=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-phycore-som-2gb" +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SIZE_LIMIT=0x3A7F0 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_DMA=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +# CONFIG_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_ESM_K3=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h new file mode 100644 index 00000000000..661ba8f73ca --- /dev/null +++ b/include/configs/phycore_am62ax.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +/* + * Configuration header file for PHYTEC phyCORE-AM62Ax + * + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano + */ + +#ifndef __PHYCORE_AM62AX_H +#define __PHYCORE_AM62AX_H + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __PHYCORE_AM62AX_H */ -- cgit v1.3.1 From a9c61ac04fdef8de7842456ff597db375f8b48d8 Mon Sep 17 00:00:00 2001 From: Gokul Praveen Date: Tue, 26 Nov 2024 16:21:30 +0530 Subject: serial: ns16550: Increase scope of ops functions Increase scope of ops functions and do some clean up for usage in device -specific UART drivers. Remove the static functionality of ops functions and migrate certain macros to header file for usage in device-specific drivers. Signed-off-by: Gokul Praveen Reviewed-by: Simon Glass --- drivers/serial/ns16550.c | 25 ++++++++----------------- include/ns16550.h | 18 ++++++++++++++++++ 2 files changed, 26 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3f6860f3916..c3b884b6d00 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -158,7 +157,7 @@ static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) #endif /* CONFIG_NS16550_DYNAMIC */ -static void ns16550_writeb(struct ns16550 *port, int offset, int value) +void ns16550_writeb(struct ns16550 *port, int offset, int value) { struct ns16550_plat *plat = port->plat; unsigned char *addr; @@ -193,13 +192,6 @@ static u32 ns16550_getfcr(struct ns16550 *port) return plat->fcr; } -/* We can clean these up once everything is moved to driver model */ -#define serial_out(value, addr) \ - ns16550_writeb(com_port, \ - (unsigned char *)addr - (unsigned char *)com_port, value) -#define serial_in(addr) \ - ns16550_readb(com_port, \ - (unsigned char *)addr - (unsigned char *)com_port) #else static u32 ns16550_getfcr(struct ns16550 *port) { @@ -214,7 +206,7 @@ int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate) return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); } -static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) +void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) { /* to keep serial format, read lcr before writing BKSE */ int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; @@ -380,7 +372,7 @@ DEBUG_UART_FUNCS #endif #if CONFIG_IS_ENABLED(DM_SERIAL) -static int ns16550_serial_putc(struct udevice *dev, const char ch) +int ns16550_serial_putc(struct udevice *dev, const char ch) { struct ns16550 *const com_port = dev_get_priv(dev); @@ -400,7 +392,7 @@ static int ns16550_serial_putc(struct udevice *dev, const char ch) return 0; } -static int ns16550_serial_pending(struct udevice *dev, bool input) +int ns16550_serial_pending(struct udevice *dev, bool input) { struct ns16550 *const com_port = dev_get_priv(dev); @@ -410,7 +402,7 @@ static int ns16550_serial_pending(struct udevice *dev, bool input) return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; } -static int ns16550_serial_getc(struct udevice *dev) +int ns16550_serial_getc(struct udevice *dev) { struct ns16550 *const com_port = dev_get_priv(dev); @@ -420,7 +412,7 @@ static int ns16550_serial_getc(struct udevice *dev) return serial_in(&com_port->rbr); } -static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) +int ns16550_serial_setbrg(struct udevice *dev, int baudrate) { struct ns16550 *const com_port = dev_get_priv(dev); struct ns16550_plat *plat = com_port->plat; @@ -433,7 +425,7 @@ static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) return 0; } -static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) +int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) { struct ns16550 *const com_port = dev_get_priv(dev); int lcr_val = UART_LCR_WLS_8; @@ -466,8 +458,7 @@ static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) return 0; } -static int ns16550_serial_getinfo(struct udevice *dev, - struct serial_device_info *info) +int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info) { struct ns16550 *const com_port = dev_get_priv(dev); struct ns16550_plat *plat = com_port->plat; diff --git a/include/ns16550.h b/include/ns16550.h index 7f481300083..5d9ff105411 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -25,6 +25,7 @@ #define __ns16550_h #include +#include #if CONFIG_IS_ENABLED(DM_SERIAL) || defined(CONFIG_NS16550_DYNAMIC) || \ defined(CONFIG_DEBUG_UART) @@ -116,6 +117,15 @@ struct ns16550 { #endif }; +#if CONFIG_IS_ENABLED(DM_SERIAL) +#define serial_out(value, addr) \ + ns16550_writeb(com_port, \ + (unsigned char *)(addr) - (unsigned char *)com_port, value) +#define serial_in(addr) \ + ns16550_readb(com_port, \ + (unsigned char *)(addr) - (unsigned char *)com_port) +#endif + #define thr rbr #define iir fcr #define dll rbr @@ -225,6 +235,14 @@ void ns16550_putc(struct ns16550 *com_port, char c); char ns16550_getc(struct ns16550 *com_port); int ns16550_tstc(struct ns16550 *com_port); void ns16550_reinit(struct ns16550 *com_port, int baud_divisor); +int ns16550_serial_putc(struct udevice *dev, const char ch); +int ns16550_serial_pending(struct udevice *dev, bool input); +int ns16550_serial_getc(struct udevice *dev); +int ns16550_serial_setbrg(struct udevice *dev, int baudrate); +int ns16550_serial_setconfig(struct udevice *dev, uint serial_config); +int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info); +void ns16550_writeb(struct ns16550 *port, int offset, int value); +void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor); /** * ns16550_calc_divisor() - calculate the divisor given clock and baud rate -- cgit v1.3.1 From 0dfb7b821c3a9a3bb1593cac0faa1a3f5e1c8181 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 29 Nov 2024 17:01:34 +0530 Subject: include: configs: j721e_evm: Increase memory offset for tiboot3.bin in HyperFlash The size of J7200 tiboot3.bin is 516KB but the memory reserved for it in HyperFlash was 512KB. This led to overlap of tiboot3.bin over tispl.bin region and break in HyperFlash boot mode. Therefore, fix this by increasing the memory allocated for tiboot3.bin to 1MB for J7200. Fixes: cf1d6867f774 ("board: ti: j7200: Introduce support for j7200 build targets") Signed-off-by: Aswath Govindraju Signed-off-by: Vaishnav Achath Signed-off-by: Anurag Dutta --- include/configs/j721e_evm.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index bdf12ee8f7e..85120629529 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -15,11 +15,14 @@ #define CFG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ -#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) +#if defined(CONFIG_TARGET_J721E_A72_EVM) #define CFG_SYS_UBOOT_BASE 0x50280000 -/* Image load address in RAM for DFU boot*/ -#else +#elif defined(CONFIG_TARGET_J7200_A72_EVM) +#define CFG_SYS_UBOOT_BASE 0x50300000 +#elif defined(CONFIG_TARGET_J721E_R5_EVM) #define CFG_SYS_UBOOT_BASE 0x50080000 +#else +#define CFG_SYS_UBOOT_BASE 0x50100000 #endif /** -- cgit v1.3.1 From 04bcc87f0dcc18c9cc6bf2bea90f8c14b44393b4 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Tue, 12 Nov 2024 15:57:38 +0100 Subject: board: add support for LicheeRV Nano The LicheeRV Nano is a small SBC using the Sophgo SG2002 RISCV SoC. Signed-off-by: Thomas Bonnefille --- arch/riscv/Kconfig | 4 +++ board/sophgo/licheerv_nano/Kconfig | 28 ++++++++++++++++++++ board/sophgo/licheerv_nano/MAINTAINERS | 5 ++++ board/sophgo/licheerv_nano/Makefile | 5 ++++ board/sophgo/licheerv_nano/board.c | 9 +++++++ configs/sipeed_licheerv_nano_defconfig | 47 ++++++++++++++++++++++++++++++++++ include/configs/licheerv_nano.h | 24 +++++++++++++++++ 7 files changed, 122 insertions(+) create mode 100644 board/sophgo/licheerv_nano/Kconfig create mode 100644 board/sophgo/licheerv_nano/MAINTAINERS create mode 100644 board/sophgo/licheerv_nano/Makefile create mode 100644 board/sophgo/licheerv_nano/board.c create mode 100644 configs/sipeed_licheerv_nano_defconfig create mode 100644 include/configs/licheerv_nano.h (limited to 'include') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 043d963f634..a73fe510f73 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_LICHEERV_NANO + bool "Support LicheeRV Nano Board" + config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -92,6 +95,7 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" +source "board/sophgo/licheerv_nano/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" diff --git a/board/sophgo/licheerv_nano/Kconfig b/board/sophgo/licheerv_nano/Kconfig new file mode 100644 index 00000000000..660d3c5d095 --- /dev/null +++ b/board/sophgo/licheerv_nano/Kconfig @@ -0,0 +1,28 @@ +if TARGET_LICHEERV_NANO + +config SYS_BOARD + default "licheerv_nano" + +config SYS_VENDOR + default "sophgo" + +config SYS_CPU + default "cv1800b" + +config SYS_CONFIG_NAME + default "licheerv_nano" + +config TEXT_BASE + default 0x80200000 + +config ENV_SIZE + default 0x20000 + +config ENV_SECT_SIZE + default 0x40000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOPHGO_CV1800B + +endif diff --git a/board/sophgo/licheerv_nano/MAINTAINERS b/board/sophgo/licheerv_nano/MAINTAINERS new file mode 100644 index 00000000000..c56060db081 --- /dev/null +++ b/board/sophgo/licheerv_nano/MAINTAINERS @@ -0,0 +1,5 @@ +LicheeRV Nano +M: Thomas Bonnefille +S: Maintained +F: board/sophgo/licheerv_nano/ +F: configs/sipeed_licheerv_nano_defconfig diff --git a/board/sophgo/licheerv_nano/Makefile b/board/sophgo/licheerv_nano/Makefile new file mode 100644 index 00000000000..59fcd5bfba9 --- /dev/null +++ b/board/sophgo/licheerv_nano/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu + +obj-y += board.o diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c new file mode 100644 index 00000000000..eaa47be1739 --- /dev/null +++ b/board/sophgo/licheerv_nano/board.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu + */ + +int board_init(void) +{ + return 0; +} diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig new file mode 100644 index 00000000000..14fefa968c6 --- /dev/null +++ b/configs/sipeed_licheerv_nano_defconfig @@ -0,0 +1,47 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x820000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 +CONFIG_DEFAULT_DEVICE_TREE="sg2002-licheerv-nano-b" +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_IDENT_STRING="licheerv_nano" +CONFIG_TARGET_LICHEERV_NANO=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_BOOTSTD_FULL=y +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +CONFIG_SD_BOOT=y +CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_PROMPT="licheerv_nano# " +# CONFIG_CMD_BOOTDEV is not set +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +# CONFIG_CMD_MII is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_SOPHGO_CV1800B=y +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_CV1800B_SPIF=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CV1800B=y diff --git a/include/configs/licheerv_nano.h b/include/configs/licheerv_nano.h new file mode 100644 index 00000000000..2ea7943f66f --- /dev/null +++ b/include/configs/licheerv_nano.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Thomas Bonnefille + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#define CFG_EXTRA_ENV_SETTINGS "consoledev=ttyS0\0" \ + "baudrate=115200\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "scriptaddr=0x80c00000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 84d3911a01783ce386883a97fcc4157039793144 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Sun, 8 Dec 2024 17:19:31 +0800 Subject: dts: starfive: Switch to using upstream DT Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b device tree as the default device tree. Drop redundant DT files from arch/riscv/dts/ and redundant clock and reset definitions from include/dt-bindings/. Since the old clock definitions is a little different from those in upstream Linux, update the clock definitions in clock drivers accordingly. Tested-by: Anand Moon Tested-by: E Shattow Acked-by: Sumit Garg Signed-off-by: Hal Feng --- arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/dts/Makefile | 1 - .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 117 ---- .../jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 117 ++++ arch/riscv/dts/jh7110-starfive-visionfive-2.dts | 11 - arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 380 ---------- arch/riscv/dts/jh7110-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110.dtsi | 761 --------------------- configs/starfive_visionfive2_defconfig | 2 +- drivers/clk/starfive/clk-jh7110-pll.c | 6 +- drivers/clk/starfive/clk-jh7110.c | 44 +- include/dt-bindings/clock/starfive,jh7110-crg.h | 258 ------- include/dt-bindings/reset/starfive,jh7110-crg.h | 183 ----- 13 files changed, 145 insertions(+), 1738 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi delete mode 100644 arch/riscv/dts/jh7110.dtsi delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h (limited to 'include') diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index e5549a01b83..9904a60dddb 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -19,6 +19,7 @@ config STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD imply MMC_SPI + imply OF_UPSTREAM imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply SIFIVE_CACHE imply SIFIVE_CCACHE diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index e054968e439..4eb7d60345e 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -8,7 +8,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi deleted file mode 100644 index 3012466b305..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "binman.dtsi" -#include "jh7110-u-boot.dtsi" -/ { - chosen { - bootph-pre-ram; - }; - - firmware { - spi0 = &qspi; - bootph-pre-ram; - }; - - config { - bootph-pre-ram; - u-boot,spl-payload-offset = <0x100000>; - }; - - memory@40000000 { - bootph-pre-ram; - }; -}; - -&uart0 { - bootph-pre-ram; -}; - -&mmc0 { - bootph-pre-ram; -}; - -&mmc1 { - bootph-pre-ram; -}; - -&qspi { - bootph-pre-ram; - - nor-flash@0 { - bootph-pre-ram; - }; -}; - -&sysgpio { - bootph-pre-ram; -}; - -&mmc0_pins { - bootph-pre-ram; - mmc0-pins-rest { - bootph-pre-ram; - }; -}; - -&mmc1_pins { - bootph-pre-ram; - mmc1-pins0 { - bootph-pre-ram; - }; - - mmc1-pins1 { - bootph-pre-ram; - }; -}; - -&i2c5_pins { - bootph-pre-ram; - i2c-pins { - bootph-pre-ram; - }; -}; - -&i2c5 { - bootph-pre-ram; - eeprom@50 { - bootph-pre-ram; - }; -}; - -&binman { - itb { - fit { - images { - fdt-1 { - description = "NAME"; - load = <0x40400000>; - compression = "none"; - - uboot_fdt_blob: blob-ext { - filename = "u-boot.dtb"; - }; - }; - }; - - configurations { - conf-1 { - fdt = "fdt-1"; - }; - }; - }; - }; - - spl-img { - filename = "spl/u-boot-spl.bin.normal.out"; - - mkimage { - args = "-T sfspl"; - - u-boot-spl { - }; - }; - }; -}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi new file mode 100644 index 00000000000..3012466b305 --- /dev/null +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ { + chosen { + bootph-pre-ram; + }; + + firmware { + spi0 = &qspi; + bootph-pre-ram; + }; + + config { + bootph-pre-ram; + u-boot,spl-payload-offset = <0x100000>; + }; + + memory@40000000 { + bootph-pre-ram; + }; +}; + +&uart0 { + bootph-pre-ram; +}; + +&mmc0 { + bootph-pre-ram; +}; + +&mmc1 { + bootph-pre-ram; +}; + +&qspi { + bootph-pre-ram; + + nor-flash@0 { + bootph-pre-ram; + }; +}; + +&sysgpio { + bootph-pre-ram; +}; + +&mmc0_pins { + bootph-pre-ram; + mmc0-pins-rest { + bootph-pre-ram; + }; +}; + +&mmc1_pins { + bootph-pre-ram; + mmc1-pins0 { + bootph-pre-ram; + }; + + mmc1-pins1 { + bootph-pre-ram; + }; +}; + +&i2c5_pins { + bootph-pre-ram; + i2c-pins { + bootph-pre-ram; + }; +}; + +&i2c5 { + bootph-pre-ram; + eeprom@50 { + bootph-pre-ram; + }; +}; + +&binman { + itb { + fit { + images { + fdt-1 { + description = "NAME"; + load = <0x40400000>; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + conf-1 { + fdt = "fdt-1"; + }; + }; + }; + }; + + spl-img { + filename = "spl/u-boot-spl.bin.normal.out"; + + mkimage { + args = "-T sfspl"; + + u-boot-spl { + }; + }; + }; +}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2.dts deleted file mode 100644 index 288ea394939..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -/dts-v1/; -#include "jh7110-starfive-visionfive-2.dtsi" - -/ { - compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; -}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi deleted file mode 100644 index e11babc1cde..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -/dts-v1/; - -#include "jh7110.dtsi" -#include -#include -/ { - aliases { - serial0 = &uart0; - spi0 = &qspi; - mmc0 = &mmc0; - mmc1 = &mmc1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - timebase-frequency = <4000000>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x2 0x0>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; - }; -}; - -&osc { - clock-frequency = <24000000>; -}; - -&rtc_osc { - clock-frequency = <32768>; -}; - -&gmac0_rmii_refin { - clock-frequency = <50000000>; -}; - -&gmac0_rgmii_rxin { - clock-frequency = <125000000>; -}; - -&gmac1_rmii_refin { - clock-frequency = <50000000>; -}; - -&gmac1_rgmii_rxin { - clock-frequency = <125000000>; -}; - -&i2stx_bclk_ext { - clock-frequency = <12288000>; -}; - -&i2stx_lrck_ext { - clock-frequency = <192000>; -}; - -&i2srx_bclk_ext { - clock-frequency = <12288000>; -}; - -&i2srx_lrck_ext { - clock-frequency = <192000>; -}; - -&tdm_ext { - clock-frequency = <49152000>; -}; - -&mclk_ext { - clock-frequency = <12288000>; -}; - -&uart0 { - reg-offset = <0>; - current-speed = <115200>; - clock-frequency = <24000000>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&i2c5 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - status = "okay"; - - pmic@36 { - compatible = "x-powers,axp15060"; - reg = <0x36>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c6 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - status = "okay"; -}; - -&sysgpio { - status = "okay"; - uart0_pins: uart0-0 { - tx-pins { - pinmux = ; - bias-disable; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pinmux = ; - bias-disable; /* external pull-up */ - drive-strength = <2>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; - - i2c0_pins: i2c0-0 { - i2c-pins { - pinmux = , - ; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c2_pins: i2c2-0 { - i2c-pins { - pinmux = , - ; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c5_pins: i2c5-0 { - i2c-pins { - pinmux = , - ; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c6_pins: i2c6-0 { - i2c-pins { - pinmux = , - ; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - mmc0_pins: mmc0-pins { - mmc0-pins-rest { - pinmux = ; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - mmc1_pins: mmc1-pins { - mmc1-pins0 { - pinmux = ; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - mmc1-pins1 { - pinmux = , - , - , - , - ; - bias-pull-up; - drive-strength = <12>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; -}; - -&mmc0 { - compatible = "snps,dw-mshc"; - max-frequency = <100000000>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - cap-mmc-hw-reset; - post-power-on-delay-ms = <200>; - status = "okay"; - -}; - -&mmc1 { - compatible = "snps,dw-mshc"; - max-frequency = <100000000>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - no-sdio; - no-mmc; - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; - cap-sd-highspeed; - post-power-on-delay-ms = <200>; - status = "okay"; -}; - -&qspi { - spi-max-frequency = <250000000>; - status = "okay"; - - nor-flash@0 { - compatible = "jedec,spi-nor"; - reg=<0>; - spi-max-frequency = <100000000>; - cdns,tshsl-ns = <1>; - cdns,tsd2d-ns = <1>; - cdns,tchsh-ns = <1>; - cdns,tslch-ns = <1>; - }; -}; - -&pcie0 { - reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie1 { - reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&aoncrg { - assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>; - assigned-clock-parents = <&osc>; - assigned-clock-rates = <0>; -}; - -&gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&gmac1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy1: ethernet-phy@1 { - reg = <0>; - }; - }; -}; diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7296f..52c1d60859a 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -62,7 +62,7 @@ <&syscrg JH7110_SYSRST_DDR_OSC>, <&syscrg JH7110_SYSRST_DDR_APB>; reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll1_out"; clock-frequency = <2133>; }; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi deleted file mode 100644 index 2cdc683d49b..00000000000 --- a/arch/riscv/dts/jh7110.dtsi +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -/dts-v1/; -#include -#include - -/ { - compatible = "starfive,jh7110"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - S7_0: cpu@0 { - compatible = "sifive,s7", "riscv"; - reg = <0>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - riscv,isa = "rv64imac_zba_zbb"; - status = "disabled"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_1: cpu@1 { - compatible = "sifive,u74-mc", "riscv"; - reg = <1>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_2: cpu@2 { - compatible = "sifive,u74-mc", "riscv"; - reg = <2>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_3: cpu@3 { - compatible = "sifive,u74-mc", "riscv"; - reg = <3>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_4: cpu@4 { - compatible = "sifive,u74-mc", "riscv"; - reg = <4>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu4_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&S7_0>; - }; - - core1 { - cpu = <&U74_1>; - }; - - core2 { - cpu = <&U74_2>; - }; - - core3 { - cpu = <&U74_3>; - }; - - core4 { - cpu = <&U74_4>; - }; - }; - }; - }; - - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 5>, - <&cpu1_intc 5>, - <&cpu2_intc 5>, - <&cpu3_intc 5>, - <&cpu4_intc 5>; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc"; - #clock-cells = <0>; - }; - - rtc_osc: rtc-oscillator { - compatible = "fixed-clock"; - clock-output-names = "rtc_osc"; - #clock-cells = <0>; - }; - - gmac0_rmii_refin: gmac0-rmii-refin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac0_rmii_refin"; - #clock-cells = <0>; - }; - - gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac0_rgmii_rxin"; - #clock-cells = <0>; - }; - - gmac1_rmii_refin: gmac1-rmii-refin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac1_rmii_refin"; - #clock-cells = <0>; - }; - - gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac1_rgmii_rxin"; - #clock-cells = <0>; - }; - - i2stx_bclk_ext: i2stx-bclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2stx_bclk_ext"; - #clock-cells = <0>; - }; - - i2stx_lrck_ext: i2stx-lrck-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2stx_lrck_ext"; - #clock-cells = <0>; - }; - - i2srx_bclk_ext: i2srx-bclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2srx_bclk_ext"; - #clock-cells = <0>; - }; - - i2srx_lrck_ext: i2srx-lrck-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2srx_lrck_ext"; - #clock-cells = <0>; - }; - - tdm_ext: tdm-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "tdm_ext"; - #clock-cells = <0>; - }; - - mclk_ext: mclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "mclk_ext"; - #clock-cells = <0>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,lpi_en; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <4>; - snps,blen = <256 128 64 32 0 0 0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clint: timer@2000000 { - compatible = "starfive,jh7110-clint", "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>; - }; - - plic: interrupt-controller@c000000 { - compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <0>; - riscv,ndev = <136>; - }; - - ccache: cache-controller@2010000 { - compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; - reg = <0x0 0x2010000 0x0 0x4000>; - interrupts = <1>, <3>, <4>, <2>; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - }; - - uart0: serial@10000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10000000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, - <&syscrg JH7110_SYSCLK_UART0_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART0_APB>, - <&syscrg JH7110_SYSRST_UART0_CORE>; - interrupts = <32>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@10010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, - <&syscrg JH7110_SYSCLK_UART1_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART1_APB>, - <&syscrg JH7110_SYSRST_UART1_CORE>; - interrupts = <33>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@10020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, - <&syscrg JH7110_SYSCLK_UART2_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART2_APB>, - <&syscrg JH7110_SYSRST_UART2_CORE>; - interrupts = <34>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c0: i2c@10030000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10030000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C0_APB>; - interrupts = <35>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@10040000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C1_APB>; - interrupts = <36>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@10050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10050000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C2_APB>; - interrupts = <37>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - stgcrg: clock-controller@10230000 { - compatible = "starfive,jh7110-stgcrg"; - reg = <0x0 0x10230000 0x0 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - stg_syscon: stg_syscon@10240000 { - compatible = "starfive,jh7110-stg-syscon","syscon"; - reg = <0x0 0x10240000 0x0 0x1000>; - }; - - uart3: serial@12000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12000000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, - <&syscrg JH7110_SYSCLK_UART3_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART3_APB>, - <&syscrg JH7110_SYSRST_UART3_CORE>; - interrupts = <45>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@12010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, - <&syscrg JH7110_SYSCLK_UART4_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART4_APB>, - <&syscrg JH7110_SYSRST_UART4_CORE>; - interrupts = <46>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@12020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, - <&syscrg JH7110_SYSCLK_UART5_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART5_APB>, - <&syscrg JH7110_SYSRST_UART5_CORE>; - interrupts = <47>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c3: i2c@12030000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12030000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C3_APB>; - interrupts = <48>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@12040000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C4_APB>; - interrupts = <49>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@12050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12050000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C5_APB>; - interrupts = <50>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@12060000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12060000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C6_APB>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - power-controller@17030000 { - compatible = "starfive,jh7110-pmu"; - reg = <0x0 0x17030000 0x0 0x10000>; - interrupts = <111>; - }; - - qspi: spi@13010000 { - compatible = "cdns,qspi-nor"; - reg = <0x0 0x13010000 0x0 0x10000 - 0x0 0x21000000 0x0 0x400000>; - clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; - clock-names = "clk_ref"; - resets = <&syscrg JH7110_SYSRST_QSPI_APB>, - <&syscrg JH7110_SYSRST_QSPI_AHB>, - <&syscrg JH7110_SYSRST_QSPI_REF>; - reset-names = "rst_apb", "rst_ahb", "rst_ref"; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - syscrg: clock-controller@13020000 { - compatible = "starfive,jh7110-syscrg"; - reg = <0x0 0x13020000 0x0 0x10000>; - clocks = <&osc>, <&gmac1_rmii_refin>, - <&gmac1_rgmii_rxin>, - <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, - <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>, - <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL1_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>; - clock-names = "osc", "gmac1_rmii_refin", - "gmac1_rgmii_rxin", - "i2stx_bclk_ext", "i2stx_lrck_ext", - "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext", - "pll0_out", "pll1_out", "pll2_out"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - sys_syscon: sys_syscon@13030000 { - compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; - reg = <0x0 0x13030000 0x0 0x1000>; - - pllclk: clock-controller { - compatible = "starfive,jh7110-pll"; - clocks = <&osc>; - #clock-cells = <1>; - }; - }; - - sysgpio: pinctrl@13040000 { - compatible = "starfive,jh7110-sys-pinctrl"; - reg = <0x0 0x13040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; - resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; - interrupts = <86>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - watchdog@13070000 { - compatible = "starfive,jh7110-wdt"; - reg = <0x0 0x13070000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, - <&syscrg JH7110_SYSCLK_WDT_CORE>; - clock-names = "apb", "core"; - resets = <&syscrg JH7110_SYSRST_WDT_APB>, - <&syscrg JH7110_SYSRST_WDT_CORE>; - }; - - mmc0: mmc@16010000 { - compatible = "starfive,jh7110-mmc"; - reg = <0x0 0x16010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, - <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; - clock-names = "biu", "ciu"; - resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; - reset-names = "reset"; - interrupts = <74>; - fifo-depth = <32>; - fifo-watermark-aligned; - data-addr = <0>; - starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; - status = "disabled"; - }; - - mmc1: mmc@16020000 { - compatible = "starfive,jh7110-mmc"; - reg = <0x0 0x16020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, - <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; - clock-names = "biu", "ciu"; - resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; - reset-names = "reset"; - interrupts = <75>; - fifo-depth = <32>; - fifo-watermark-aligned; - data-addr = <0>; - starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; - status = "disabled"; - }; - - gmac0: ethernet@16030000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; - reg = <0x0 0x16030000 0x0 0x10000>; - clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, - <&aoncrg JH7110_AONCLK_GMAC0_AHB>, - <&syscrg JH7110_SYSCLK_GMAC0_PTP>, - <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, - <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; - clock-names = "stmmaceth", "pclk", "ptp_ref", - "tx", "gtx"; - resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, - <&aoncrg JH7110_AONRST_GMAC0_AHB>; - reset-names = "stmmaceth", "ahb"; - interrupts = <7>, <6>, <5>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <8>; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; - snps,axi-config = <&stmmac_axi_setup>; - snps,tso; - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; - starfive,syscon = <&aon_syscon 0xc 0x12>; - status = "disabled"; - }; - - gmac1: ethernet@16040000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; - reg = <0x0 0x16040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, - <&syscrg JH7110_SYSCLK_GMAC1_AHB>, - <&syscrg JH7110_SYSCLK_GMAC1_PTP>, - <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, - <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; - clock-names = "stmmaceth", "pclk", "ptp_ref", - "tx", "gtx"; - resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, - <&syscrg JH7110_SYSRST_GMAC1_AHB>; - reset-names = "stmmaceth", "ahb"; - interrupts = <78>, <77>, <76>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <8>; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; - snps,axi-config = <&stmmac_axi_setup>; - snps,tso; - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; - starfive,syscon = <&sys_syscon 0x90 0x2>; - status = "disabled"; - }; - - rng: rng@1600c000 { - compatible = "starfive,jh7110-trng"; - reg = <0x0 0x1600C000 0x0 0x4000>; - clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, - <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; - clock-names = "hclk", "ahb"; - resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; - interrupts = <30>; - }; - - aoncrg: clock-controller@17000000 { - compatible = "starfive,jh7110-aoncrg"; - reg = <0x0 0x17000000 0x0 0x10000>; - clocks = <&osc>, <&rtc_osc>, - <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, - <&syscrg JH7110_SYSCLK_STG_AXIAHB>, - <&syscrg JH7110_SYSCLK_APB_BUS>, - <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; - clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", - "gmac0_rgmii_rxin", "stg_axiahb", - "apb_bus", "gmac0_gtxclk"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - aon_syscon: aon_syscon@17010000 { - compatible = "starfive,jh7110-aon-syscon","syscon"; - reg = <0x0 0x17010000 0x0 0x1000>; - }; - - aongpio: pinctrl@17020000 { - compatible = "starfive,jh7110-aon-pinctrl"; - reg = <0x0 0x17020000 0x0 0x10000>; - resets = <&aoncrg JH7110_AONRST_IOMUX>; - interrupts = <85>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcie0: pcie@2b000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x0 0x2b000000 0x0 0x1000000 - 0x9 0x40000000 0x0 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, - <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; - interrupts = <56>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, - <0x0 0x0 0x0 0x2 &plic 0x2>, - <0x0 0x0 0x0 0x3 &plic 0x3>, - <0x0 0x0 0x0 0x4 &plic 0x4>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; - bus-range = <0x0 0xff>; - clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, - <&stgcrg JH7110_STGCLK_PCIE0_TL>, - <&stgcrg JH7110_STGCLK_PCIE0_AXI>, - <&stgcrg JH7110_STGCLK_PCIE0_APB>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV>, - <&stgcrg JH7110_STGRST_PCIE0_BRG>, - <&stgcrg JH7110_STGRST_PCIE0_CORE>, - <&stgcrg JH7110_STGRST_PCIE0_APB>; - reset-names = "mst0", "slv0", "slv", "brg", - "core", "apb"; - status = "disabled"; - }; - - pcie1: pcie@2c000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x0 0x2c000000 0x0 0x1000000 - 0x9 0xc0000000 0x0 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, - <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; - interrupts = <57>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, - <0x0 0x0 0x0 0x2 &plic 0x2>, - <0x0 0x0 0x0 0x3 &plic 0x3>, - <0x0 0x0 0x0 0x4 &plic 0x4>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; - bus-range = <0x0 0xff>; - clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, - <&stgcrg JH7110_STGCLK_PCIE1_TL>, - <&stgcrg JH7110_STGCLK_PCIE1_AXI>, - <&stgcrg JH7110_STGCLK_PCIE1_APB>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV>, - <&stgcrg JH7110_STGRST_PCIE1_BRG>, - <&stgcrg JH7110_STGRST_PCIE1_CORE>, - <&stgcrg JH7110_STGRST_PCIE1_APB>; - reset-names = "mst0", "slv0", "slv", "brg", - "core", "apb"; - status = "disabled"; - }; - }; -}; diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 20f89ae6796..cb86582fd6b 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=100000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xf0000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2" +CONFIG_DEFAULT_DEVICE_TREE="starfive/jh7110-starfive-visionfive-2-v1.3b" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 6d2bfb3ecb7..f8af17227c5 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -374,13 +374,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev) if (sysreg == FDT_ADDR_T_NONE) return -EINVAL; - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT), starfive_jh7110_pll("pll0_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll0)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT), starfive_jh7110_pll("pll1_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll1)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT), starfive_jh7110_pll("pll2_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll2)); diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 191da75d7ba..6387e949d50 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -495,37 +495,37 @@ static int jh7110_stgcrg_init(struct udevice *dev) { struct jh7110_clk_priv *priv = dev_get_priv(dev); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB), starfive_clk_gate(priv->reg, "usb_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB), + OFFSET(JH7110_STGCLK_USB0_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB), starfive_clk_gate(priv->reg, "usb_utmi_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_UTMI_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI), + OFFSET(JH7110_STGCLK_USB0_UTMI_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI), starfive_clk_gate(priv->reg, "usb_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_USB_AXI))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM), + OFFSET(JH7110_STGCLK_USB0_AXI))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM), starfive_clk_gate_divider(priv->reg, "usb_lpm", "oscillator", - OFFSET(JH7110_STGCLK_USB_LPM), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB), + OFFSET(JH7110_STGCLK_USB0_LPM), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB), starfive_clk_gate_divider(priv->reg, "usb_stb", "oscillator", - OFFSET(JH7110_STGCLK_USB_STB), 3)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125), + OFFSET(JH7110_STGCLK_USB0_STB), 3)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125), starfive_clk_gate(priv->reg, "usb_app_125", "usb_125m", - OFFSET(JH7110_STGCLK_USB_APP_125))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK), + OFFSET(JH7110_STGCLK_USB0_APP_125))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK), starfive_clk_divider(priv->reg, "usb_refclk", "oscillator", - OFFSET(JH7110_STGCLK_USB_REFCLK), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI), + OFFSET(JH7110_STGCLK_USB0_REFCLK), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0), starfive_clk_gate(priv->reg, "pcie0_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE0_AXI))); + OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB), starfive_clk_gate(priv->reg, "pcie0_apb", "apb_bus", @@ -534,10 +534,10 @@ static int jh7110_stgcrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb", OFFSET(JH7110_STGCLK_PCIE0_TL))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0), starfive_clk_gate(priv->reg, "pcie1_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE1_AXI))); + OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB), starfive_clk_gate(priv->reg, "pcie1_apb", "apb_bus", @@ -548,14 +548,14 @@ static int jh7110_stgcrg_init(struct udevice *dev) OFFSET(JH7110_STGCLK_PCIE1_TL))); /* Security clocks */ - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB), starfive_clk_gate(priv->reg, "sec_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_HCLK))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), + OFFSET(JH7110_STGCLK_SEC_AHB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB), starfive_clk_gate(priv->reg, "sec_misc_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_MISCAHB))); + OFFSET(JH7110_STGCLK_SEC_MISC_AHB))); return 0; } diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h deleted file mode 100644 index b51e3829ff4..00000000000 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ - -#define JH7110_SYSCLK_PLL0_OUT 0 -#define JH7110_SYSCLK_PLL1_OUT 1 -#define JH7110_SYSCLK_PLL2_OUT 2 -#define JH7110_PLLCLK_END 3 - -#define JH7110_SYSCLK_CPU_ROOT 0 -#define JH7110_SYSCLK_CPU_CORE 1 -#define JH7110_SYSCLK_CPU_BUS 2 -#define JH7110_SYSCLK_GPU_ROOT 3 -#define JH7110_SYSCLK_PERH_ROOT 4 -#define JH7110_SYSCLK_BUS_ROOT 5 -#define JH7110_SYSCLK_NOCSTG_BUS 6 -#define JH7110_SYSCLK_AXI_CFG0 7 -#define JH7110_SYSCLK_STG_AXIAHB 8 -#define JH7110_SYSCLK_AHB0 9 -#define JH7110_SYSCLK_AHB1 10 -#define JH7110_SYSCLK_APB_BUS 11 -#define JH7110_SYSCLK_APB0 12 -#define JH7110_SYSCLK_PLL0_DIV2 13 -#define JH7110_SYSCLK_PLL1_DIV2 14 -#define JH7110_SYSCLK_PLL2_DIV2 15 -#define JH7110_SYSCLK_AUDIO_ROOT 16 -#define JH7110_SYSCLK_MCLK_INNER 17 -#define JH7110_SYSCLK_MCLK 18 -#define JH7110_SYSCLK_MCLK_OUT 19 -#define JH7110_SYSCLK_ISP_2X 20 -#define JH7110_SYSCLK_ISP_AXI 21 -#define JH7110_SYSCLK_GCLK0 22 -#define JH7110_SYSCLK_GCLK1 23 -#define JH7110_SYSCLK_GCLK2 24 -#define JH7110_SYSCLK_CORE 25 -#define JH7110_SYSCLK_CORE1 26 -#define JH7110_SYSCLK_CORE2 27 -#define JH7110_SYSCLK_CORE3 28 -#define JH7110_SYSCLK_CORE4 29 -#define JH7110_SYSCLK_DEBUG 30 -#define JH7110_SYSCLK_RTC_TOGGLE 31 -#define JH7110_SYSCLK_TRACE0 32 -#define JH7110_SYSCLK_TRACE1 33 -#define JH7110_SYSCLK_TRACE2 34 -#define JH7110_SYSCLK_TRACE3 35 -#define JH7110_SYSCLK_TRACE4 36 -#define JH7110_SYSCLK_TRACE_COM 37 -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 -#define JH7110_SYSCLK_OSC_DIV2 40 -#define JH7110_SYSCLK_PLL1_DIV4 41 -#define JH7110_SYSCLK_PLL1_DIV8 42 -#define JH7110_SYSCLK_DDR_BUS 43 -#define JH7110_SYSCLK_DDR_AXI 44 -#define JH7110_SYSCLK_GPU_CORE 45 -#define JH7110_SYSCLK_GPU_CORE_CLK 46 -#define JH7110_SYSCLK_GPU_SYS_CLK 47 -#define JH7110_SYSCLK_GPU_APB 48 -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 -#define JH7110_SYSCLK_HIFI4_CORE 54 -#define JH7110_SYSCLK_HIFI4_AXI 55 -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 -#define JH7110_SYSCLK_VOUT_SRC 58 -#define JH7110_SYSCLK_VOUT_AXI 59 -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 -#define JH7110_SYSCLK_JPEGC_AXI 65 -#define JH7110_SYSCLK_CODAJ12_AXI 66 -#define JH7110_SYSCLK_CODAJ12_CORE 67 -#define JH7110_SYSCLK_CODAJ12_APB 68 -#define JH7110_SYSCLK_VDEC_AXI 69 -#define JH7110_SYSCLK_WAVE511_AXI 70 -#define JH7110_SYSCLK_WAVE511_BPU 71 -#define JH7110_SYSCLK_WAVE511_VCE 72 -#define JH7110_SYSCLK_WAVE511_APB 73 -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 -#define JH7110_SYSCLK_VENC_AXI 77 -#define JH7110_SYSCLK_WAVE420L_AXI 78 -#define JH7110_SYSCLK_WAVE420L_BPU 79 -#define JH7110_SYSCLK_WAVE420L_VCE 80 -#define JH7110_SYSCLK_WAVE420L_APB 81 -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 -#define JH7110_SYSCLK_AXIMEM2_AXI 86 -#define JH7110_SYSCLK_QSPI_AHB 87 -#define JH7110_SYSCLK_QSPI_APB 88 -#define JH7110_SYSCLK_QSPI_REF_SRC 89 -#define JH7110_SYSCLK_QSPI_REF 90 -#define JH7110_SYSCLK_SDIO0_AHB 91 -#define JH7110_SYSCLK_SDIO1_AHB 92 -#define JH7110_SYSCLK_SDIO0_SDCARD 93 -#define JH7110_SYSCLK_SDIO1_SDCARD 94 -#define JH7110_SYSCLK_USB_125M 95 -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 -#define JH7110_SYSCLK_GMAC1_AHB 97 -#define JH7110_SYSCLK_GMAC1_AXI 98 -#define JH7110_SYSCLK_GMAC_SRC 99 -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 -#define JH7110_SYSCLK_GMAC1_PTP 102 -#define JH7110_SYSCLK_GMAC1_RX 103 -#define JH7110_SYSCLK_GMAC1_RX_INV 104 -#define JH7110_SYSCLK_GMAC1_TX 105 -#define JH7110_SYSCLK_GMAC1_TX_INV 106 -#define JH7110_SYSCLK_GMAC1_GTXC 107 -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 -#define JH7110_SYSCLK_GMAC0_PTP 109 -#define JH7110_SYSCLK_GMAC_PHY 110 -#define JH7110_SYSCLK_GMAC0_GTXC 111 -#define JH7110_SYSCLK_IOMUX_APB 112 -#define JH7110_SYSCLK_MAILBOX 113 -#define JH7110_SYSCLK_INT_CTRL_APB 114 -#define JH7110_SYSCLK_CAN0_APB 115 -#define JH7110_SYSCLK_CAN0_TIMER 116 -#define JH7110_SYSCLK_CAN0_CAN 117 -#define JH7110_SYSCLK_CAN1_APB 118 -#define JH7110_SYSCLK_CAN1_TIMER 119 -#define JH7110_SYSCLK_CAN1_CAN 120 -#define JH7110_SYSCLK_PWM_APB 121 -#define JH7110_SYSCLK_WDT_APB 122 -#define JH7110_SYSCLK_WDT_CORE 123 -#define JH7110_SYSCLK_TIMER_APB 124 -#define JH7110_SYSCLK_TIMER0 125 -#define JH7110_SYSCLK_TIMER1 126 -#define JH7110_SYSCLK_TIMER2 127 -#define JH7110_SYSCLK_TIMER3 128 -#define JH7110_SYSCLK_TEMP_APB 129 -#define JH7110_SYSCLK_TEMP_CORE 130 -#define JH7110_SYSCLK_SPI0_APB 131 -#define JH7110_SYSCLK_SPI1_APB 132 -#define JH7110_SYSCLK_SPI2_APB 133 -#define JH7110_SYSCLK_SPI3_APB 134 -#define JH7110_SYSCLK_SPI4_APB 135 -#define JH7110_SYSCLK_SPI5_APB 136 -#define JH7110_SYSCLK_SPI6_APB 137 -#define JH7110_SYSCLK_I2C0_APB 138 -#define JH7110_SYSCLK_I2C1_APB 139 -#define JH7110_SYSCLK_I2C2_APB 140 -#define JH7110_SYSCLK_I2C3_APB 141 -#define JH7110_SYSCLK_I2C4_APB 142 -#define JH7110_SYSCLK_I2C5_APB 143 -#define JH7110_SYSCLK_I2C6_APB 144 -#define JH7110_SYSCLK_UART0_APB 145 -#define JH7110_SYSCLK_UART0_CORE 146 -#define JH7110_SYSCLK_UART1_APB 147 -#define JH7110_SYSCLK_UART1_CORE 148 -#define JH7110_SYSCLK_UART2_APB 149 -#define JH7110_SYSCLK_UART2_CORE 150 -#define JH7110_SYSCLK_UART3_APB 151 -#define JH7110_SYSCLK_UART3_CORE 152 -#define JH7110_SYSCLK_UART4_APB 153 -#define JH7110_SYSCLK_UART4_CORE 154 -#define JH7110_SYSCLK_UART5_APB 155 -#define JH7110_SYSCLK_UART5_CORE 156 -#define JH7110_SYSCLK_PWMDAC_APB 157 -#define JH7110_SYSCLK_PWMDAC_CORE 158 -#define JH7110_SYSCLK_SPDIF_APB 159 -#define JH7110_SYSCLK_SPDIF_CORE 160 -#define JH7110_SYSCLK_I2STX0_APB 161 -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 -#define JH7110_SYSCLK_I2STX0_BCLK 165 -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 -#define JH7110_SYSCLK_I2STX0_LRCK 167 -#define JH7110_SYSCLK_I2STX1_APB 168 -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 -#define JH7110_SYSCLK_I2STX1_BCLK 172 -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 -#define JH7110_SYSCLK_I2STX1_LRCK 174 -#define JH7110_SYSCLK_I2SRX_APB 175 -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 -#define JH7110_SYSCLK_I2SRX_BCLK 179 -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 -#define JH7110_SYSCLK_I2SRX_LRCK 181 -#define JH7110_SYSCLK_PDM_DMIC 182 -#define JH7110_SYSCLK_PDM_APB 183 -#define JH7110_SYSCLK_TDM_AHB 184 -#define JH7110_SYSCLK_TDM_APB 185 -#define JH7110_SYSCLK_TDM_INTERNAL 186 -#define JH7110_SYSCLK_TDM_CLK_TDM 187 -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 - -#define JH7110_SYSCLK_END 190 - -#define JH7110_AONCLK_OSC_DIV4 0 -#define JH7110_AONCLK_APB_FUNC 1 -#define JH7110_AONCLK_GMAC0_AHB 2 -#define JH7110_AONCLK_GMAC0_AXI 3 -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 -#define JH7110_AONCLK_GMAC0_TX 5 -#define JH7110_AONCLK_GMAC0_TX_INV 6 -#define JH7110_AONCLK_GMAC0_RX 7 -#define JH7110_AONCLK_GMAC0_RX_INV 8 -#define JH7110_AONCLK_OTPC_APB 9 -#define JH7110_AONCLK_RTC_APB 10 -#define JH7110_AONCLK_RTC_INTERNAL 11 -#define JH7110_AONCLK_RTC_32K 12 -#define JH7110_AONCLK_RTC_CAL 13 - -#define JH7110_AONCLK_END 14 - -#define JH7110_STGCLK_HIFI4_CORE 0 -#define JH7110_STGCLK_USB_APB 1 -#define JH7110_STGCLK_USB_UTMI_APB 2 -#define JH7110_STGCLK_USB_AXI 3 -#define JH7110_STGCLK_USB_LPM 4 -#define JH7110_STGCLK_USB_STB 5 -#define JH7110_STGCLK_USB_APP_125 6 -#define JH7110_STGCLK_USB_REFCLK 7 -#define JH7110_STGCLK_PCIE0_AXI 8 -#define JH7110_STGCLK_PCIE0_APB 9 -#define JH7110_STGCLK_PCIE0_TL 10 -#define JH7110_STGCLK_PCIE1_AXI 11 -#define JH7110_STGCLK_PCIE1_APB 12 -#define JH7110_STGCLK_PCIE1_TL 13 -#define JH7110_STGCLK_PCIE01_MAIN 14 -#define JH7110_STGCLK_SEC_HCLK 15 -#define JH7110_STGCLK_SEC_MISCAHB 16 -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 -#define JH7110_STGCLK_MTRX_GRP0_STG 19 -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 -#define JH7110_STGCLK_MTRX_GRP1_STG 22 -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 -#define JH7110_STGCLK_E2_RTC 24 -#define JH7110_STGCLK_E2_CORE 25 -#define JH7110_STGCLK_E2_DBG 26 -#define JH7110_STGCLK_DMA1P_AXI 27 -#define JH7110_STGCLK_DMA1P_AHB 28 - -#define JH7110_STGCLK_END 29 - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index 1d596581da7..00000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG2APB 0 -#define JH7110_SYSRST_SYSCON 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON_PRESETN 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_TOP_HRESETN 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB_AXI 7 -#define JH7110_STGRST_USB_APB 8 -#define JH7110_STGRST_USB_UTMI_APB 9 -#define JH7110_STGRST_USB_PWRUP 10 -#define JH7110_STGRST_PCIE0_MST0 11 -#define JH7110_STGRST_PCIE0_SLV0 12 -#define JH7110_STGRST_PCIE0_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_MST0 17 -#define JH7110_STGRST_PCIE1_SLV0 18 -#define JH7110_STGRST_PCIE1_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ -- cgit v1.3.1 From 1cd239f44438b96acf24a7425aae790cd3f91d66 Mon Sep 17 00:00:00 2001 From: Kongyang Liu Date: Sun, 15 Dec 2024 13:02:41 +0800 Subject: riscv: spacemit: bananapi_f3: initial support added Add basic support for SpacemiT's Banana Pi F3 board. Update the k1.dtsi align with mainline. Note that the device tree files follow the mainline Linux source[1]. Links: https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-dt-v5-8-98263aae83be@gentoo.org/ [1] Signed-off-by: Kongyang Liu Signed-off-by: Huan Zhou Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Yixun Lan Tested-by: Marcel Ziswiler --- arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 2 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 459 +++++++++++++++++++++++++++++++++ board/spacemit/bananapi-f3/Kconfig | 25 ++ board/spacemit/bananapi-f3/MAINTAINERS | 6 + board/spacemit/bananapi-f3/Makefile | 5 + board/spacemit/bananapi-f3/board.c | 9 + configs/bananapi-f3_defconfig | 20 ++ include/configs/bananapi-f3.h | 13 + 14 files changed, 656 insertions(+) create mode 100644 arch/riscv/cpu/k1/Kconfig create mode 100644 arch/riscv/cpu/k1/Makefile create mode 100644 arch/riscv/cpu/k1/cpu.c create mode 100644 arch/riscv/cpu/k1/dram.c create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts create mode 100644 arch/riscv/dts/k1.dtsi create mode 100644 board/spacemit/bananapi-f3/Kconfig create mode 100644 board/spacemit/bananapi-f3/MAINTAINERS create mode 100644 board/spacemit/bananapi-f3/Makefile create mode 100644 board/spacemit/bananapi-f3/board.c create mode 100644 configs/bananapi-f3_defconfig create mode 100644 include/configs/bananapi-f3.h (limited to 'include') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a73fe510f73..a8f770b57b0 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_BANANAPI_F3 + bool "Support BananaPi F3 Board" + config TARGET_LICHEERV_NANO bool "Support LicheeRV Nano Board" @@ -96,6 +99,7 @@ source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" source "board/sophgo/licheerv_nano/Kconfig" +source "board/spacemit/bananapi-f3/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" @@ -108,6 +112,7 @@ source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/ast2700/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" +source "arch/riscv/cpu/k1/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig new file mode 100644 index 00000000000..d9cd8dce964 --- /dev/null +++ b/arch/riscv/cpu/k1/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024, Kongyang Liu + +config SPACEMIT_K1 + bool + select BINMAN + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/k1/Makefile b/arch/riscv/cpu/k1/Makefile new file mode 100644 index 00000000000..bad4f4cf46f --- /dev/null +++ b/arch/riscv/cpu/k1/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/k1/cpu.c b/arch/riscv/cpu/k1/cpu.c new file mode 100644 index 00000000000..41a4a1b95e6 --- /dev/null +++ b/arch/riscv/cpu/k1/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c new file mode 100644 index 00000000000..c477c15cbfb --- /dev/null +++ b/arch/riscv/cpu/k1/dram.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + /* TODO get ram size from ddr controller */ + gd->ram_size = SZ_4G; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + + if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = 0x100000000; + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + } + + return 0; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + if (gd->ram_size > SZ_2G) + return SZ_2G; + + return gd->ram_size; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + start[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + + return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +} diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 4eb7d60345e..b64fc0daf3c 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts new file mode 100644 index 00000000000..d2486f70906 --- /dev/null +++ b/arch/riscv/dts/k1-bananapi-f3.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include "k1.dtsi" +#include "binman.dtsi" + +/ { + model = "Banana Pi BPI-F3"; + compatible = "bananapi,bpi-f3", "spacemit,k1"; + + chosen { + stdout-path = "serial0"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi new file mode 100644 index 00000000000..514be453dba --- /dev/null +++ b/arch/riscv/dts/k1.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SpacemiT K1"; + compatible = "spacemit,k1"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + core1 { + cpu = <&cpu_1>; + }; + core2 { + cpu = <&cpu_2>; + }; + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + core1 { + cpu = <&cpu_5>; + }; + core2 { + cpu = <&cpu_6>; + }; + core3 { + cpu = <&cpu_7>; + }; + }; + }; + + cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cluster0_l2_cache: l2-cache0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <512>; + cache-unified; + }; + + cluster1_l2_cache: l2-cache1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <512>; + cache-unified; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + interrupts = <42>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@d4017100 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + interrupts = <44>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@d4017200 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + interrupts = <45>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@d4017300 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017300 0x0 0x100>; + interrupts = <46>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@d4017400 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017400 0x0 0x100>; + interrupts = <47>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart6: serial@d4017500 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017500 0x0 0x100>; + interrupts = <48>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart7: serial@d4017600 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017600 0x0 0x100>; + interrupts = <49>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart8: serial@d4017700 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017700 0x0 0x100>; + interrupts = <50>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart9: serial@d4017800 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017800 0x0 0x100>; + interrupts = <51>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xe0000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <159>; + }; + + clint: timer@e4000000 { + compatible = "spacemit,k1-clint", "sifive,clint0"; + reg = <0x0 0xe4000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + sec_uart1: serial@f0612000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf0612000 0x0 0x100>; + interrupts = <43>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "reserved"; /* for TEE usage */ + }; + }; +}; \ No newline at end of file diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/bananapi-f3/Kconfig new file mode 100644 index 00000000000..f89fa9af2c7 --- /dev/null +++ b/board/spacemit/bananapi-f3/Kconfig @@ -0,0 +1,25 @@ +if TARGET_BANANAPI_F3 + +config SYS_BOARD + default "bananapi-f3" + +config SYS_VENDOR + default "spacemit" + +config SYS_CPU + default "k1" + +config SYS_CONFIG_NAME + default "bananapi-f3" + +config TEXT_BASE + default 0x00200000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x00000000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SPACEMIT_K1 + +endif diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/bananapi-f3/MAINTAINERS new file mode 100644 index 00000000000..131bad03181 --- /dev/null +++ b/board/spacemit/bananapi-f3/MAINTAINERS @@ -0,0 +1,6 @@ +BananaPi F3 +M: Huan Zhou +S: Maintained +F: board/spacemit/bananapi-f3/ +F: configs/bananapi-f3_defconfig +F: doc/board/spacemit/bananapi-f3.rst diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/bananapi-f3/Makefile new file mode 100644 index 00000000000..2168698402b --- /dev/null +++ b/board/spacemit/bananapi-f3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu + +obj-y := board.o diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c new file mode 100644 index 00000000000..2631cdd49e0 --- /dev/null +++ b/board/spacemit/bananapi-f3/board.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu + */ + +int board_init(void) +{ + return 0; +} diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig new file mode 100644 index 00000000000..63636202087 --- /dev/null +++ b/configs/bananapi-f3_defconfig @@ -0,0 +1,20 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" +CONFIG_SYS_LOAD_ADDR=0x200000 +CONFIG_TARGET_BANANAPI_F3=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0xa000000 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_HUSH_PARSER=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h new file mode 100644 index 00000000000..97cf4d72df0 --- /dev/null +++ b/include/configs/bananapi-f3.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From fc37a73e667916e15e01e0f9d189da792df2b351 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 2 Nov 2024 11:49:42 -0600 Subject: fdt: Swap the signature for board_fdt_blob_setup() This returns a devicetree and updates a parameter with an error code. Swap it, since this fits better with the way U-Boot normally works. It also (more easily) allows leaving the existing pointer unchanged. No yaks were harmed in this change, but there is a very small code-size reduction. For sifive, the OF_BOARD option must be set for the function to be called, so there is no point in checking it again. Also OF_SEPARATE is defined always. Signed-off-by: Simon Glass Reviewed-by: Matthias Brugger Reviewed-by: Patrice Chotard [trini: Update total_compute] Signed-off-by: Tom Rini --- arch/arm/mach-apple/board.c | 7 +++-- arch/arm/mach-snapdragon/board.c | 9 +++--- arch/arm/mach-stm32mp/boot_params.c | 19 +++++++------ arch/sandbox/cpu/cpu.c | 34 +++++++++++------------ board/Marvell/octeontx/board-fdt.c | 12 +++----- board/Marvell/octeontx2/board-fdt.c | 12 +++----- board/Marvell/octeontx2/board.c | 3 +- board/andestech/ae350/ae350.c | 23 ++++++++------- board/armltd/total_compute/total_compute.c | 12 ++++---- board/armltd/vexpress64/vexpress64.c | 33 ++++++++++------------ board/broadcom/bcmstb/bcmstb.c | 7 +++-- board/emulation/qemu-arm/qemu-arm.c | 7 +++-- board/emulation/qemu-ppce500/qemu-ppce500.c | 12 +++----- board/emulation/qemu-riscv/qemu-riscv.c | 7 +++-- board/highbank/highbank.c | 7 +++-- board/raspberrypi/rpi/rpi.c | 13 ++++----- board/sifive/unleashed/unleashed.c | 12 ++++---- board/sifive/unmatched/unmatched.c | 11 ++++---- board/starfive/visionfive2/starfive_visionfive2.c | 11 ++++---- board/xen/xenguest_arm64/xenguest_arm64.c | 14 +++++----- board/xilinx/common/board.c | 26 +++++++++-------- include/fdtdec.h | 9 +++--- lib/fdtdec.c | 14 +++++++--- 23 files changed, 157 insertions(+), 157 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 0b6d290b8ac..2644a04a622 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -691,11 +691,12 @@ int dram_init_banksize(void) extern long fw_dtb_pointer; -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { /* Return DTB pointer passed by m1n1 */ - *err = 0; - return (void *)fw_dtb_pointer; + *fdtp = (void *)fw_dtb_pointer; + + return 0; } void build_mem_map(void) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 75a880f093c..f1319df4314 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -150,12 +150,12 @@ static void show_psci_version(void) * or for supporting quirky devices where it's easier to leave the downstream DT in place * to improve ABL compatibility. Otherwise, we use the DT provided by ABL. */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { struct fdt_header *fdt; bool internal_valid, external_valid; + int ret = 0; - *err = 0; fdt = (struct fdt_header *)get_prev_bl_fdt_addr(); external_valid = fdt && !fdt_check_header(fdt); internal_valid = !fdt_check_header(gd->fdt_blob); @@ -170,10 +170,11 @@ void *board_fdt_blob_setup(int *err) if (internal_valid) { debug("Using built in FDT\n"); + ret = -EEXIST; } else { debug("Using external FDT\n"); /* So we can use it before returning */ - gd->fdt_blob = fdt; + *fdtp = fdt; } /* @@ -182,7 +183,7 @@ void *board_fdt_blob_setup(int *err) */ qcom_parse_memory(); - return (void *)gd->fdt_blob; + return ret; } void reset_cpu(void) diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c index ebddf6a7dbc..2d058edc419 100644 --- a/arch/arm/mach-stm32mp/boot_params.c +++ b/arch/arm/mach-stm32mp/boot_params.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY LOGC_ARCH #include +#include #include #include #include @@ -16,20 +17,22 @@ * Use the saved FDT address provided by TF-A at boot time (NT_FW_CONFIG = * Non Trusted Firmware configuration file) when the pointer is valid */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { unsigned long nt_fw_dtb = get_stm32mp_bl2_dtb(); log_debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb); - *err = 0; /* use external device tree only if address is valid */ - if (nt_fw_dtb >= STM32_DDR_BASE) { - if (fdt_magic(nt_fw_dtb) == FDT_MAGIC) - return (void *)nt_fw_dtb; - log_debug("%s: DTB not found.\n", __func__); + if (nt_fw_dtb < STM32_DDR_BASE || + fdt_magic(nt_fw_dtb) != FDT_MAGIC) { + log_debug("DTB not found.\n"); + log_debug("fall back to builtin DTB, %p\n", _end); + + return -EEXIST; } - log_debug("%s: fall back to builtin DTB, %p\n", __func__, _end); - return (void *)_end; + *fdtp = (void *)nt_fw_dtb; + + return 0; } diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index d1c4dcf0764..6407193c5f1 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -368,7 +368,7 @@ static int setup_auto_tree(void *blob) return 0; } -void *board_fdt_blob_setup(int *ret) +int board_fdt_blob_setup(void **fdtp) { struct sandbox_state *state = state_get_current(); const char *fname = state->fdt_fname; @@ -378,43 +378,41 @@ void *board_fdt_blob_setup(int *ret) int fd; if (gd->fdt_blob) - return (void *)gd->fdt_blob; + return -EEXIST; blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); - *ret = 0; if (!state->fdt_fname) { err = setup_auto_tree(blob); - if (!err) - goto done; - os_printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); - *ret = -EINVAL; - goto fail; + if (err) { + os_printf("Unable to create empty FDT: %s\n", + fdt_strerror(err)); + return -EINVAL; + } + *fdtp = blob; + + return 0; } err = os_get_filesize(fname, &size); if (err < 0) { os_printf("Failed to find FDT file '%s'\n", fname); - *ret = err; - goto fail; + return err; } fd = os_open(fname, OS_O_RDONLY); if (fd < 0) { os_printf("Failed to open FDT file '%s'\n", fname); - *ret = -EACCES; - goto fail; + return -EACCES; } if (os_read(fd, blob, size) != size) { os_close(fd); os_printf("Failed to read FDT file '%s'\n", fname); - *ret = -EIO; - goto fail; + return -EIO; } os_close(fd); -done: - return blob; -fail: - return NULL; + *fdtp = blob; + + return 0; } ulong timer_get_boot_us(void) diff --git a/board/Marvell/octeontx/board-fdt.c b/board/Marvell/octeontx/board-fdt.c index 6642b167e19..9d913b959e0 100644 --- a/board/Marvell/octeontx/board-fdt.c +++ b/board/Marvell/octeontx/board-fdt.c @@ -296,13 +296,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } -/** - * Return the FDT base address that was passed by ATF - * - * Return: FDT base address received from ATF in x1 register - */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - return (void *)fdt_base_addr; + *fdtp = (void *)fdt_base_addr; + + return 0; } diff --git a/board/Marvell/octeontx2/board-fdt.c b/board/Marvell/octeontx2/board-fdt.c index 04be9fb0a9a..e5a4db00bb7 100644 --- a/board/Marvell/octeontx2/board-fdt.c +++ b/board/Marvell/octeontx2/board-fdt.c @@ -210,13 +210,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } -/** - * Return the FDT base address that was passed by ATF - * - * Return: FDT base address received from ATF in x1 register - */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - return (void *)fdt_base_addr; + *fdtp = (void *)fdt_base_addr; + + return 0; } diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 974e9eb8200..01ba53cf68d 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -234,7 +234,8 @@ static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; addr = hextoul(argv[1], NULL); - fdt = board_fdt_blob_setup(&err); + fdt = (void *)gd->fdt_blob; + err = board_fdt_blob_setup(&fdt); entry = (uboot_entry_t)addr; flush_cache((ulong)addr, 1 << 20); /* 1MiB should be enough */ dcache_disable(); diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c index 5ae5baed6ba..1d9d4a929c2 100644 --- a/board/andestech/ae350/ae350.c +++ b/board/andestech/ae350/ae350.c @@ -79,21 +79,24 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) } #define ANDES_HW_DTB_ADDRESS 0xF2000000 -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) - return (void *)(ulong)gd->arch.firmware_fdt_addr; + if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == + FDT_MAGIC) { + *fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr; + + return 0; + } } - if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) - return (void *)CONFIG_SYS_FDT_BASE; - return (void *)ANDES_HW_DTB_ADDRESS; + if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) { + *fdtp = (void *)CONFIG_SYS_FDT_BASE; + + return 0; + } - *err = -EINVAL; - return NULL; + return -EINVAL; } #ifdef CONFIG_SPL_BOARD_INIT diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 1336d2eb163..75ba3c33d56 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -37,15 +37,13 @@ struct mm_region *mem_map = total_compute_mem_map; */ unsigned long __section(".data") fw_dtb_pointer; -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) { - *err = -ENXIO; - return NULL; - } + if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) + return -ENXIO; - return (void *)fw_dtb_pointer; + *fdtp = (void *)fw_dtb_pointer; + return 0; } int misc_init_r(void) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 0119f54f0df..b5ede58757d 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -168,42 +168,37 @@ static bool is_valid_dtb(uintptr_t dtb_ptr) return fdt_subnode_offset((void *)dtb_ptr, 0, "memory") >= 0; } -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { #ifdef CONFIG_TARGET_VEXPRESS64_JUNO phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART); - *err = 0; - if (fdt_rom_addr == ~0UL) { - *err = -ENXIO; - return NULL; - } + if (fdt_rom_addr == ~0UL) + return -ENXIO; - return (void *)fdt_rom_addr; + *fdtp = (void *)fdt_rom_addr; + return 0; #endif #ifdef VEXPRESS_FDT_ADDR if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) { - *err = 0; - return (void *)VEXPRESS_FDT_ADDR; + *fdtp = (void *)VEXPRESS_FDT_ADDR; + return 0; } #endif if (is_valid_dtb(prior_stage_fdt_address[1])) { - *err = 0; - return (void *)prior_stage_fdt_address[1]; + *fdtp = (void *)prior_stage_fdt_address[1]; + return 0; } else if (is_valid_dtb(prior_stage_fdt_address[0])) { - *err = 0; - return (void *)prior_stage_fdt_address[0]; + *fdtp = (void *)prior_stage_fdt_address[0]; + return 0; } - if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) { - *err = 0; - return (void *)gd->fdt_blob; - } + if (fdt_magic(*fdtp) == FDT_MAGIC) + return 0; - *err = -ENXIO; - return NULL; + return -ENXIO; } #endif diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index bc05aecc446..e655f610c84 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -130,9 +130,10 @@ int board_late_init(void) return 0; } -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; /* Stored the DTB address there during our init */ - return (void *)prior_stage_fdt_address; + *fdtp = (void *)prior_stage_fdt_address; + + return 0; } diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index e0e18b4dfea..31f5a775137 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -149,11 +149,12 @@ int dram_init_banksize(void) return 0; } -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; /* QEMU loads a generated DTB for us at the start of RAM. */ - return (void *)CFG_SYS_SDRAM_BASE; + *fdtp = (void *)CFG_SYS_SDRAM_BASE; + + return 0; } void enable_caches(void) diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 58e5d5eb942..40d295dbf06 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -334,15 +334,11 @@ u32 cpu_mask(void) return (1 << cpu_numcores()) - 1; } -/** - * Return the virtual address of FDT that was passed by QEMU - * - * Return: virtual address of FDT received from QEMU in r3 register - */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - return get_fdt_virt(); + *fdtp = get_fdt_virt(); + + return 0; } /* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index e5193e31e37..a90222ea6a4 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -64,9 +64,10 @@ int board_fit_config_name_match(const char *name) } #endif -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; /* Stored the DTB address there during our init */ - return (void *)(ulong)gd->arch.firmware_fdt_addr; + *fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr; + + return 0; } diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index f3df83ed6c9..0ec88447384 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -97,15 +97,16 @@ int ft_board_setup(void *fdt, struct bd_info *bd) } #endif -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; /* * The ECME management processor loads the DTB from NOR flash * into DRAM (at 4KB), where it gets patched to contain the * detected memory size. */ - return (void *)0x1000; + *fdtp = (void *)0x1000; + + return 0; } static int is_highbank(void) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 9122f33d88d..c46fe4b2350 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -508,15 +508,14 @@ int board_init(void) /* * If the firmware passed a device tree use it for U-Boot. */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) { - *err = -ENXIO; - return NULL; - } + if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) + return -ENXIO; - return (void *)fw_dtb_pointer; + *fdtp = (void *)fw_dtb_pointer; + + return 0; } int copy_property(void *dst, void *src, char *path, char *property) diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index 3c5dd50c369..c1c374610c3 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -114,15 +114,15 @@ int misc_init_r(void) #endif -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (gd->arch.firmware_fdt_addr) - return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + if (gd->arch.firmware_fdt_addr) { + *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + + return 0; } - return (ulong *)_end; + return -EEXIST; } int board_init(void) diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index c8696270ba2..23e03e145ee 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -10,15 +10,14 @@ #include #include -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (gd->arch.firmware_fdt_addr) - return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + if (gd->arch.firmware_fdt_addr) { + *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + return 0; } - return (ulong *)_end; + return -EEXIST; } int board_init(void) diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index f6114602f88..3940d45b13f 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -115,15 +115,14 @@ int board_late_init(void) return 0; } -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (gd->arch.firmware_fdt_addr) - return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + if (gd->arch.firmware_fdt_addr) { + *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + return 0; } - return (ulong *)_end; + return -EEXIST; } int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 4c3b9c9e278..216a022aa15 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -44,14 +44,14 @@ int board_init(void) * x0 is the physical address of the device tree blob (dtb) in system RAM. * This is stored in rom_pointer during low level init. */ -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { - *err = 0; - if (fdt_magic(rom_pointer[0]) != FDT_MAGIC) { - *err = -ENXIO; - return NULL; - } - return (void *)rom_pointer[0]; + if (fdt_magic(rom_pointer[0]) != FDT_MAGIC) + return -ENXIO; + + *fdtp = (void *)rom_pointer[0]; + + return 0; } /* diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index a12dccd4c51..deea6c71103 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -358,17 +358,17 @@ __maybe_unused int xilinx_read_eeprom(void) } #if defined(CONFIG_OF_BOARD) -void *board_fdt_blob_setup(int *err) +int board_fdt_blob_setup(void **fdtp) { void *fdt_blob; - *err = 0; - if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) { fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; - if (fdt_magic(fdt_blob) == FDT_MAGIC) - return fdt_blob; + if (fdt_magic(fdt_blob) == FDT_MAGIC) { + *fdtp = fdt_blob; + return 0; + } } if (!IS_ENABLED(CONFIG_XPL_BUILD) && @@ -376,8 +376,10 @@ void *board_fdt_blob_setup(int *err) !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) { fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; - if (fdt_magic(fdt_blob) == FDT_MAGIC) - return fdt_blob; + if (fdt_magic(fdt_blob) == FDT_MAGIC) { + *fdtp = fdt_blob; + return 0; + } debug("DTB is not passed via %p\n", fdt_blob); } @@ -396,13 +398,15 @@ void *board_fdt_blob_setup(int *err) fdt_blob = (ulong *)_end; } - if (fdt_magic(fdt_blob) == FDT_MAGIC) - return fdt_blob; + if (fdt_magic(fdt_blob) == FDT_MAGIC) { + *fdtp = fdt_blob; + + return 0; + } debug("DTB is also not passed via %p\n", fdt_blob); - *err = -EINVAL; - return NULL; + return -EINVAL; } #endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 555c9520379..58bbd8f392e 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1191,11 +1191,12 @@ int fdtdec_resetup(int *rescan); * * The existing devicetree is available at gd->fdt_blob * - * @err: 0 on success, -EEXIST if the devicetree is already correct, or other - * internal error code if we fail to setup a DTB - * @returns new devicetree blob pointer + * @fdtp: Existing devicetree blob pointer; update this and return 0 if a + * different devicetree should be used + * Return: 0 on success, -EEXIST if the existing FDT is OK, -ve error code if we + * fail to setup a DTB */ -void *board_fdt_blob_setup(int *err); +int board_fdt_blob_setup(void **fdtp); /* * Decode the size of memory diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 60e28173c03..c5d29d4385a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1706,11 +1706,17 @@ int fdtdec_setup(void) /* Allow the board to override the fdt address. */ if (IS_ENABLED(CONFIG_OF_BOARD)) { - gd->fdt_blob = board_fdt_blob_setup(&ret); - if (!ret) + void *blob; + + blob = (void *)gd->fdt_blob; + ret = board_fdt_blob_setup(&blob); + if (ret) { + if (ret != -EEXIST) + return ret; + } else { gd->fdt_src = FDTSRC_BOARD; - else if (ret != -EEXIST) - return ret; + gd->fdt_blob = blob; + } } /* Allow the early environment to override the fdt address */ -- cgit v1.3.1 From e5178be68678e0c010cb11d107679aa8ed96e648 Mon Sep 17 00:00:00 2001 From: Evgeny Bachinin Date: Mon, 2 Dec 2024 16:45:22 +0300 Subject: sandbox: fix bloblist_finish() linker error if BLOBLIST=n Having CONFIG_OF_EMBED=y && CONFIG_BLOBLIST=n leads to the link error: ``` ld: /tmp/ccwtRVty.ltrans0.ltrans.o: in function `state_uninit': arch/sandbox/cpu/state.c:508: undefined reference to `bloblist_finish' ``` Fixes: 1c52fcca72b ("sandbox: Write out bloblist when exiting") Signed-off-by: Evgeny Bachinin Reviewed-by: Simon Glass --- include/bloblist.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/bloblist.h b/include/bloblist.h index ff32d3fecfd..f999391f74b 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -357,6 +357,7 @@ int bloblist_new(ulong addr, uint size, uint flags, uint align_log2); */ int bloblist_check(ulong addr, uint size); +#if CONFIG_IS_ENABLED(BLOBLIST) /** * bloblist_finish() - Set up the bloblist for the next U-Boot part * @@ -366,6 +367,12 @@ int bloblist_check(ulong addr, uint size); * Return: 0 */ int bloblist_finish(void); +#else +static inline int bloblist_finish(void) +{ + return 0; +} +#endif /* BLOBLIST */ /** * bloblist_get_stats() - Get information about the bloblist -- cgit v1.3.1 From 79d7b11102e31f3b92afff1c94dd9fe1a8b9a9e4 Mon Sep 17 00:00:00 2001 From: Paul HENRYS Date: Mon, 25 Nov 2024 18:47:15 +0100 Subject: aes: Allow to store randomly generated IV in the FIT When the initialisation vector is randomly generated, its value shall be stored in the FIT together with the encrypted data. The changes allow to store the IV in the FIT also in the case where the key is not stored in the DTB but retrieved somewhere else at runtime. Signed-off-by: Paul HENRYS Reviewed-by: Simon Glass --- include/image.h | 15 +++++++++++++++ lib/aes/aes-encrypt.c | 7 +++++++ tools/image-host.c | 2 +- 3 files changed, 23 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index 9be5acd8158..cfe3c971a36 100644 --- a/include/image.h +++ b/include/image.h @@ -1788,6 +1788,21 @@ struct cipher_algo { const unsigned char *data, int data_len, unsigned char **cipher, int *cipher_len); + /** + * add_cipher_data() - Add cipher data to the FIT and device tree + * + * This is used to add the ciphered data to the FIT and other cipher + * related information (key and initialization vector) to a device tree. + * + * @info: Pointer to image cipher information. + * @keydest: Pointer to a device tree where the key and IV can be + * stored. keydest can be NULL when the key is retrieved at + * runtime by another mean. + * @fit: Pointer to the FIT image. + * @node_noffset: Offset where the cipher information are stored in the + * FIT. + * return: 0 on success, a negative error code otherwise. + */ int (*add_cipher_data)(struct image_cipher_info *info, void *keydest, void *fit, int node_noffset); diff --git a/lib/aes/aes-encrypt.c b/lib/aes/aes-encrypt.c index e74e35eaa28..90e1407b4f0 100644 --- a/lib/aes/aes-encrypt.c +++ b/lib/aes/aes-encrypt.c @@ -84,6 +84,13 @@ int image_aes_add_cipher_data(struct image_cipher_info *info, void *keydest, char name[128]; int ret = 0; + if (!keydest && !info->ivname) { + /* At least, store the IV in the FIT image */ + ret = fdt_setprop(fit, node_noffset, "iv", + info->iv, info->cipher->iv_len); + goto done; + } + /* Either create or overwrite the named cipher node */ parent = fdt_subnode_offset(keydest, 0, FIT_CIPHER_NODENAME); if (parent == -FDT_ERR_NOTFOUND) { diff --git a/tools/image-host.c b/tools/image-host.c index 5e01b853c50..16389bd4880 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -535,7 +535,7 @@ fit_image_process_cipher(const char *keydir, void *keydest, void *fit, * size values * And, if needed, write the iv in the FIT file */ - if (keydest) { + if (keydest || (!keydest && !info.ivname)) { ret = info.cipher->add_cipher_data(&info, keydest, fit, node_noffset); if (ret) { fprintf(stderr, -- cgit v1.3.1 From 9922227ac5c1e51b211e4062c90db0ab5355cd97 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 19 Dec 2024 11:28:50 -0700 Subject: image: Add a prototype for fit_image_get_phase() This function exists but is not exported. Add a prototype so it can be used elsewhere. Signed-off-by: Simon Glass --- include/image.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 9be5acd8158..bb15ef69871 100644 --- a/include/image.h +++ b/include/image.h @@ -1171,6 +1171,18 @@ int fit_image_get_data_size_unciphered(const void *fit, int noffset, int fit_image_get_data_and_size(const void *fit, int noffset, const void **data, size_t *size); +/** + * fit_image_get_phase() - Get the phase from a FIT image + * + * @fit: FIT to read from + * @offset: offset node to read + * @phasep: Returns phase, if any + * Return: 0 if read OK and *phasep is value, -ENOENT if there was no phase + * property in the node, other -ve value on other error + */ +int fit_image_get_phase(const void *fit, int offset, + enum image_phase_t *phasep); + /** * fit_get_data_node() - Get verified image data for an image * @fit: Pointer to the FIT format image header -- cgit v1.3.1 From 771f0e9877efec600ebe8c4cb5bc7df549544a4e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 19 Dec 2024 11:28:51 -0700 Subject: boot: Allow FIT to fall back from best-match option When the best-match feature fails to find something, use the provided config name as a fallback. The allows SPL to select a suitable config when best-match is enabled. Signed-off-by: Simon Glass --- boot/image-fit.c | 19 ++++++++++--------- include/image.h | 4 +++- 2 files changed, 13 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/boot/image-fit.c b/boot/image-fit.c index 7d56f0b5e6e..439ff51edf6 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -1729,13 +1729,13 @@ int fit_conf_find_compat(const void *fit, const void *fdt) images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); if (confs_noffset < 0 || images_noffset < 0) { debug("Can't find configurations or images nodes.\n"); - return -1; + return -EINVAL; } fdt_compat = fdt_getprop(fdt, 0, "compatible", &fdt_compat_len); if (!fdt_compat) { debug("Fdt for comparison has no \"compatible\" property.\n"); - return -1; + return -ENXIO; } /* @@ -1812,7 +1812,7 @@ int fit_conf_find_compat(const void *fit, const void *fdt) } if (!best_match_offset) { debug("No match found.\n"); - return -1; + return -ENOENT; } return best_match_offset; @@ -2095,17 +2095,18 @@ int fit_image_load(struct bootm_headers *images, ulong addr, * fit_conf_get_node() will try to find default config node */ bootstage_mark(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME); - if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) { - cfg_noffset = fit_conf_find_compat(fit, gd_fdt_blob()); - } else { - cfg_noffset = fit_conf_get_node(fit, fit_uname_config); - } - if (cfg_noffset < 0) { + ret = -ENXIO; + if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) + ret = fit_conf_find_compat(fit, gd_fdt_blob()); + if (ret < 0 && ret != -EINVAL) + ret = fit_conf_get_node(fit, fit_uname_config); + if (ret < 0) { puts("Could not find configuration node\n"); bootstage_error(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME); return -ENOENT; } + cfg_noffset = ret; fit_base_uname_config = fdt_get_name(fit, cfg_noffset, NULL); printf(" Using '%s' configuration\n", fit_base_uname_config); diff --git a/include/image.h b/include/image.h index bb15ef69871..ab96510f62c 100644 --- a/include/image.h +++ b/include/image.h @@ -1411,7 +1411,9 @@ int fit_check_format(const void *fit, ulong size); * copied into the configuration node in the FIT image. This is required to * match configurations with compressed FDTs. * - * Returns: offset to the configuration to use if one was found, -1 otherwise + * Returns: offset to the configuration to use if one was found, -EINVAL if + * there a /configurations or /images node is missing, -ENOENT if no match was + * found, -ENXIO if the FDT node has no compatible string */ int fit_conf_find_compat(const void *fit, const void *fdt); -- cgit v1.3.1 From 7a585b9d6a30e4122f9944b792f4da8ba5196d86 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 19 Dec 2024 11:29:00 -0700 Subject: spl: Drop use of uintptr_t U-Boot uses ulong for addresses. It is confusing to use uintptr_t in a few places, since it makes people wonder if the types are compatible. Change the few occurences in SPL to use ulong Signed-off-by: Simon Glass --- common/spl/spl_atf.c | 36 ++++++++++++++++++------------------ common/spl/spl_fit.c | 2 +- common/spl/spl_legacy.c | 8 ++++---- include/spl.h | 28 ++++++++++++++-------------- 4 files changed, 37 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index 0397b86a33b..8bc5db77395 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -41,9 +41,9 @@ struct bl2_to_bl31_params_mem_v2 { struct entry_point_info bl31_ep_info; }; -struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { static struct bl2_to_bl31_params_mem bl31_params_mem; struct bl31_params *bl2_to_bl31_params; @@ -100,17 +100,17 @@ struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, return bl2_to_bl31_params; } -__weak struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +__weak struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { return bl2_plat_get_bl31_params_default(bl32_entry, bl33_entry, fdt_addr); } -struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { static struct bl2_to_bl31_params_mem_v2 bl31_params_mem; struct bl_params *bl_params; @@ -173,9 +173,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, return bl_params; } -__weak struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr) +__weak struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr) { return bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, fdt_addr); @@ -188,8 +188,8 @@ static inline void raw_write_daif(unsigned int daif) typedef void __noreturn (*atf_entry_t)(struct bl31_params *params, void *plat_params); -static void __noreturn bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, - uintptr_t bl33_entry, uintptr_t fdt_addr) +static void __noreturn bl31_entry(ulong bl31_entry, ulong bl32_entry, + ulong bl33_entry, ulong fdt_addr) { atf_entry_t atf_entry = (atf_entry_t)bl31_entry; void *bl31_params; @@ -238,7 +238,7 @@ static int spl_fit_images_find(void *blob, int os) return -FDT_ERR_NOTFOUND; } -uintptr_t spl_fit_images_get_entry(void *blob, int node) +ulong spl_fit_images_get_entry(void *blob, int node) { ulong val; int ret; @@ -253,10 +253,10 @@ uintptr_t spl_fit_images_get_entry(void *blob, int node) void __noreturn spl_invoke_atf(struct spl_image_info *spl_image) { - uintptr_t bl32_entry = 0; - uintptr_t bl33_entry = CONFIG_TEXT_BASE; + ulong bl32_entry = 0; + ulong bl33_entry = CONFIG_TEXT_BASE; void *blob = spl_image->fdt_addr; - uintptr_t platform_param = (uintptr_t)blob; + ulong platform_param = (ulong)blob; int node; /* diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 3160f573bfb..ef40a50082c 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -862,7 +862,7 @@ int spl_load_fit_image(struct spl_image_info *spl_image, { struct bootm_headers images; const char *fit_uname_config = NULL; - uintptr_t fdt_hack; + ulong fdt_hack; const char *uname; ulong fw_data = 0, dt_data = 0, img_data = 0; ulong fw_len = 0, dt_len = 0, img_len = 0; diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 9252b3a3de0..b3efb3e630e 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -16,11 +16,11 @@ #define LZMA_LEN (1 << 20) -static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size) +static void spl_parse_legacy_validate(ulong start, ulong size) { - uintptr_t spl_start = (uintptr_t)_start; - uintptr_t spl_end = (uintptr_t)&_image_binary_end; - uintptr_t end = start + size; + ulong spl_start = (ulong)_start; + ulong spl_end = (ulong)&_image_binary_end; + ulong end = start + size; if ((start >= spl_start && start < spl_end) || (end > spl_start && end <= spl_end) || diff --git a/include/spl.h b/include/spl.h index 269e36bb441..43b344dbc55 100644 --- a/include/spl.h +++ b/include/spl.h @@ -268,8 +268,8 @@ enum spl_sandbox_flags { struct spl_image_info { const char *name; u8 os; - uintptr_t load_addr; - uintptr_t entry_point; + ulong load_addr; + ulong entry_point; #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) void *fdt_addr; #endif @@ -951,9 +951,9 @@ void __noreturn spl_invoke_atf(struct spl_image_info *spl_image); * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_default() - prepare params for bl31. @@ -972,9 +972,9 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl31_params *bl2_plat_get_bl31_params_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_v2() - return params for bl31 @@ -988,9 +988,9 @@ struct bl31_params *bl2_plat_get_bl31_params_default(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * bl2_plat_get_bl31_params_v2_default() - prepare params for bl31. @@ -1007,9 +1007,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, * * Return: bl31 params structure pointer */ -struct bl_params *bl2_plat_get_bl31_params_v2_default(uintptr_t bl32_entry, - uintptr_t bl33_entry, - uintptr_t fdt_addr); +struct bl_params *bl2_plat_get_bl31_params_v2_default(ulong bl32_entry, + ulong bl33_entry, + ulong fdt_addr); /** * spl_optee_entry - entry function for optee * -- cgit v1.3.1 From 6f1b27a724b0d75bf89cc0f8be95fc3bcb4d4fe8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 19 Dec 2024 11:29:07 -0700 Subject: hash: Plumb crc8 into the hash functions Add an entry for crc8, with watchdog handling. Signed-off-by: Simon Glass Reviewed-by: Jaehoon Chung --- common/Kconfig | 8 ++++++++ common/hash.c | 8 ++++++++ include/u-boot/crc.h | 3 +++ lib/crc8.c | 6 ++++++ 4 files changed, 25 insertions(+) (limited to 'include') diff --git a/common/Kconfig b/common/Kconfig index e8d89bf6eb9..0e8c44f3f74 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -845,6 +845,14 @@ config HASH and the algorithms it supports are defined in common/hash.c. See also CMD_HASH for command-line access. +config HASH_CRC8 + bool "Make crc8 available via the hash API" + depends on HASH && CRC8 + help + Most times, the crc8() function is called directly. To make it also + available via the hash API, e.g. in hash_block(), enable this + option. + config AVB_VERIFY bool "Build Android Verified Boot operations" depends on LIBAVB diff --git a/common/hash.c b/common/hash.c index db6925d6782..8dd9da85768 100644 --- a/common/hash.c +++ b/common/hash.c @@ -304,6 +304,14 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc16_ccitt, .hash_finish = hash_finish_crc16_ccitt, }, +#if CONFIG_IS_ENABLED(CRC8) && IS_ENABLED(CONFIG_HASH_CRC8) + { + .name = "crc8", + .digest_size = 1, + .chunk_size = CHUNKSZ_CRC32, + .hash_func_ws = crc8_wd_buf, + }, +#endif #if CONFIG_IS_ENABLED(CRC32) { .name = "crc32", diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 5174bd7ac41..b2badaf6a97 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -25,6 +25,9 @@ */ unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len); +void crc8_wd_buf(const unsigned char *input, unsigned int len, + unsigned char output[1], unsigned int chunk_sz); + /* lib/crc16.c - 16 bit CRC with polynomial x^16 + x^15 + x^2 + 1 */ uint16_t crc16(uint16_t crc, const unsigned char *buffer, size_t len); diff --git a/lib/crc8.c b/lib/crc8.c index 20d46d16147..811e19917b4 100644 --- a/lib/crc8.c +++ b/lib/crc8.c @@ -32,3 +32,9 @@ unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) return crc; } + +void crc8_wd_buf(const unsigned char *input, unsigned int len, + unsigned char output[1], unsigned int chunk_sz) +{ + *output = crc8(0, input, len); +} -- cgit v1.3.1 From ddedfe1cb8b6c262990b629494165082320cc884 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Sat, 28 Dec 2024 13:46:29 +0300 Subject: net/tcp: put connection specific data into a tcp_stream structure no functional changes Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Simon Glass --- include/net/tcp.h | 37 ++++++++- net/net.c | 11 ++- net/tcp.c | 231 ++++++++++++++++++++++++++++-------------------------- net/wget.c | 3 +- 4 files changed, 163 insertions(+), 119 deletions(-) (limited to 'include') diff --git a/include/net/tcp.h b/include/net/tcp.h index c29d4ce24a7..14aee64cb1c 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -277,9 +277,40 @@ enum tcp_state { TCP_FIN_WAIT_2 }; -enum tcp_state tcp_get_tcp_state(void); -void tcp_set_tcp_state(enum tcp_state new_state); -int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, +/** + * struct tcp_stream - TCP data stream structure + * + * @state: TCP connection state + * + * @seq_init: Initial receive sequence number + * @ack_edge: Receive next + * + * @loc_timestamp: Local timestamp + * @rmt_timestamp: Remote timestamp + * + * @lost: Used for SACK + */ +struct tcp_stream { + /* TCP connection state */ + enum tcp_state state; + + u32 seq_init; + u32 ack_edge; + + /* TCP option timestamp */ + u32 loc_timestamp; + u32 rmt_timestamp; + + /* TCP sliding window control used to request re-TX */ + struct tcp_sack_v lost; +}; + +struct tcp_stream *tcp_stream_get(void); + +enum tcp_state tcp_get_tcp_state(struct tcp_stream *tcp); +void tcp_set_tcp_state(struct tcp_stream *tcp, enum tcp_state new_state); +int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, + int sport, int payload_len, u8 action, u32 tcp_seq_num, u32 tcp_ack_num); /** diff --git a/net/net.c b/net/net.c index ca35704f661..e12ac55c401 100644 --- a/net/net.c +++ b/net/net.c @@ -420,7 +420,7 @@ int net_init(void) /* Only need to setup buffer pointers once. */ first_call = 0; if (IS_ENABLED(CONFIG_PROT_TCP)) - tcp_set_tcp_state(TCP_CLOSED); + tcp_set_tcp_state(tcp_stream_get(), TCP_CLOSED); } return net_init_loop(); @@ -924,6 +924,9 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, uchar *pkt; int eth_hdr_size; int pkt_hdr_size; +#if defined(CONFIG_PROT_TCP) + struct tcp_stream *tcp; +#endif /* make sure the net_tx_packet is initialized (net_init() was called) */ assert(net_tx_packet != NULL); @@ -950,8 +953,12 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, break; #if defined(CONFIG_PROT_TCP) case IPPROTO_TCP: + tcp = tcp_stream_get(); + if (!tcp) + return -EINVAL; + pkt_hdr_size = eth_hdr_size - + tcp_set_tcp_header(pkt + eth_hdr_size, dport, sport, + + tcp_set_tcp_header(tcp, pkt + eth_hdr_size, dport, sport, payload_len, action, tcp_seq_num, tcp_ack_num); break; diff --git a/net/tcp.c b/net/tcp.c index 724536cb352..8eeb43b8796 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -24,19 +24,8 @@ #include #include -/* - * TCP sliding window control used by us to request re-TX - */ -static struct tcp_sack_v tcp_lost; - -/* TCP option timestamp */ -static u32 loc_timestamp; -static u32 rmt_timestamp; - -static u32 tcp_seq_init; -static u32 tcp_ack_edge; - static int tcp_activity_count; +static struct tcp_stream tcp_stream; /* * TCP lengths are stored as a rounded up number of 32 bit words. @@ -48,9 +37,6 @@ static int tcp_activity_count; #define SHIFT_TO_TCPHDRLEN_FIELD(x) ((x) << 4) #define GET_TCP_HDR_LEN_IN_BYTES(x) ((x) >> 2) -/* TCP connection state */ -static enum tcp_state current_tcp_state; - /* Current TCP RX packet handler */ static rxhand_tcp *tcp_packet_handler; @@ -60,22 +46,30 @@ static inline s32 tcp_seq_cmp(u32 a, u32 b) } /** - * tcp_get_tcp_state() - get current TCP state + * tcp_get_tcp_state() - get TCP stream state + * @tcp: tcp stream * - * Return: Current TCP state + * Return: TCP stream state */ -enum tcp_state tcp_get_tcp_state(void) +enum tcp_state tcp_get_tcp_state(struct tcp_stream *tcp) { - return current_tcp_state; + return tcp->state; } /** - * tcp_set_tcp_state() - set current TCP state + * tcp_set_tcp_state() - set TCP stream state + * @tcp: tcp stream * @new_state: new TCP state */ -void tcp_set_tcp_state(enum tcp_state new_state) +void tcp_set_tcp_state(struct tcp_stream *tcp, + enum tcp_state new_state) { - current_tcp_state = new_state; + tcp->state = new_state; +} + +struct tcp_stream *tcp_stream_get(void) +{ + return &tcp_stream; } static void dummy_handler(uchar *pkt, u16 dport, @@ -138,29 +132,30 @@ u16 tcp_set_pseudo_header(uchar *pkt, struct in_addr src, struct in_addr dest, /** * net_set_ack_options() - set TCP options in acknowledge packets + * @tcp: tcp stream * @b: the packet * * Return: TCP header length */ -int net_set_ack_options(union tcp_build_pkt *b) +int net_set_ack_options(struct tcp_stream *tcp, union tcp_build_pkt *b) { b->sack.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(LEN_B_TO_DW(TCP_HDR_SIZE)); b->sack.t_opt.kind = TCP_O_TS; b->sack.t_opt.len = TCP_OPT_LEN_A; - b->sack.t_opt.t_snd = htons(loc_timestamp); - b->sack.t_opt.t_rcv = rmt_timestamp; + b->sack.t_opt.t_snd = htons(tcp->loc_timestamp); + b->sack.t_opt.t_rcv = tcp->rmt_timestamp; b->sack.sack_v.kind = TCP_1_NOP; b->sack.sack_v.len = 0; if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) { - if (tcp_lost.len > TCP_OPT_LEN_2) { + if (tcp->lost.len > TCP_OPT_LEN_2) { debug_cond(DEBUG_DEV_PKT, "TCP ack opt lost.len %x\n", - tcp_lost.len); - b->sack.sack_v.len = tcp_lost.len; + tcp->lost.len); + b->sack.sack_v.len = tcp->lost.len; b->sack.sack_v.kind = TCP_V_SACK; - b->sack.sack_v.hill[0].l = htonl(tcp_lost.hill[0].l); - b->sack.sack_v.hill[0].r = htonl(tcp_lost.hill[0].r); + b->sack.sack_v.hill[0].l = htonl(tcp->lost.hill[0].l); + b->sack.sack_v.hill[0].r = htonl(tcp->lost.hill[0].r); /* * These SACK structures are initialized with NOPs to @@ -168,17 +163,17 @@ int net_set_ack_options(union tcp_build_pkt *b) * SACK structures used for both header padding and * internally. */ - b->sack.sack_v.hill[1].l = htonl(tcp_lost.hill[1].l); - b->sack.sack_v.hill[1].r = htonl(tcp_lost.hill[1].r); - b->sack.sack_v.hill[2].l = htonl(tcp_lost.hill[2].l); - b->sack.sack_v.hill[2].r = htonl(tcp_lost.hill[2].r); + b->sack.sack_v.hill[1].l = htonl(tcp->lost.hill[1].l); + b->sack.sack_v.hill[1].r = htonl(tcp->lost.hill[1].r); + b->sack.sack_v.hill[2].l = htonl(tcp->lost.hill[2].l); + b->sack.sack_v.hill[2].r = htonl(tcp->lost.hill[2].r); b->sack.sack_v.hill[3].l = TCP_O_NOP; b->sack.sack_v.hill[3].r = TCP_O_NOP; } b->sack.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(ROUND_TCPHDR_LEN(TCP_HDR_SIZE + TCP_TSOPT_SIZE + - tcp_lost.len)); + tcp->lost.len)); } else { b->sack.sack_v.kind = 0; b->sack.hdr.tcp_hlen = SHIFT_TO_TCPHDRLEN_FIELD(ROUND_TCPHDR_LEN(TCP_HDR_SIZE + @@ -194,13 +189,14 @@ int net_set_ack_options(union tcp_build_pkt *b) } /** - * net_set_ack_options() - set TCP options in SYN packets + * net_set_syn_options() - set TCP options in SYN packets + * @tcp: tcp stream * @b: the packet */ -void net_set_syn_options(union tcp_build_pkt *b) +void net_set_syn_options(struct tcp_stream *tcp, union tcp_build_pkt *b) { if (IS_ENABLED(CONFIG_PROT_TCP_SACK)) - tcp_lost.len = 0; + tcp->lost.len = 0; b->ip.hdr.tcp_hlen = 0xa0; @@ -219,14 +215,15 @@ void net_set_syn_options(union tcp_build_pkt *b) } b->ip.t_opt.kind = TCP_O_TS; b->ip.t_opt.len = TCP_OPT_LEN_A; - loc_timestamp = get_ticks(); - rmt_timestamp = 0; + tcp->loc_timestamp = get_ticks(); + tcp->rmt_timestamp = 0; b->ip.t_opt.t_snd = 0; b->ip.t_opt.t_rcv = 0; b->ip.end = TCP_O_END; } -int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, +int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, + int sport, int payload_len, u8 action, u32 tcp_seq_num, u32 tcp_ack_num) { union tcp_build_pkt *b = (union tcp_build_pkt *)pkt; @@ -249,21 +246,21 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); tcp_activity_count = 0; - net_set_syn_options(b); + net_set_syn_options(tcp, b); tcp_seq_num = 0; tcp_ack_num = 0; pkt_hdr_len = IP_TCP_O_SIZE; - if (current_tcp_state == TCP_SYN_SENT) { /* Too many SYNs */ + if (tcp->state == TCP_SYN_SENT) { /* Too many SYNs */ action = TCP_FIN; - current_tcp_state = TCP_FIN_WAIT_1; + tcp->state = TCP_FIN_WAIT_1; } else { - tcp_lost.len = TCP_OPT_LEN_2; - current_tcp_state = TCP_SYN_SENT; + tcp->lost.len = TCP_OPT_LEN_2; + tcp->state = TCP_SYN_SENT; } break; case TCP_SYN | TCP_ACK: case TCP_ACK: - pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(b); + pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(tcp, b); b->ip.hdr.tcp_flags = action; debug_cond(DEBUG_DEV_PKT, "TCP Hdr:ACK (%pI4, %pI4, s=%u, a=%u, A=%x)\n", @@ -276,20 +273,20 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); payload_len = 0; pkt_hdr_len = IP_TCP_HDR_SIZE; - current_tcp_state = TCP_FIN_WAIT_1; + tcp->state = TCP_FIN_WAIT_1; break; case TCP_RST | TCP_ACK: case TCP_RST: debug_cond(DEBUG_DEV_PKT, "TCP Hdr:RST (%pI4, %pI4, s=%u, a=%u)\n", &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); - current_tcp_state = TCP_CLOSED; + tcp->state = TCP_CLOSED; break; /* Notify connection closing */ case (TCP_FIN | TCP_ACK): case (TCP_FIN | TCP_ACK | TCP_PUSH): - if (current_tcp_state == TCP_CLOSE_WAIT) - current_tcp_state = TCP_CLOSING; + if (tcp->state == TCP_CLOSE_WAIT) + tcp->state = TCP_CLOSING; debug_cond(DEBUG_DEV_PKT, "TCP Hdr:FIN ACK PSH(%pI4, %pI4, s=%u, a=%u, A=%x)\n", @@ -297,7 +294,7 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, tcp_seq_num, tcp_ack_num, action); fallthrough; default: - pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(b); + pkt_hdr_len = IP_HDR_SIZE + net_set_ack_options(tcp, b); b->ip.hdr.tcp_flags = action | TCP_PUSH | TCP_ACK; debug_cond(DEBUG_DEV_PKT, "TCP Hdr:dft (%pI4, %pI4, s=%u, a=%u, A=%x)\n", @@ -308,9 +305,9 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, pkt_len = pkt_hdr_len + payload_len; tcp_len = pkt_len - IP_HDR_SIZE; - tcp_ack_edge = tcp_ack_num; + tcp->ack_edge = tcp_ack_num; /* TCP Header */ - b->ip.hdr.tcp_ack = htonl(tcp_ack_edge); + b->ip.hdr.tcp_ack = htonl(tcp->ack_edge); b->ip.hdr.tcp_src = htons(sport); b->ip.hdr.tcp_dst = htons(dport); b->ip.hdr.tcp_seq = htonl(tcp_seq_num); @@ -344,78 +341,79 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len, return pkt_hdr_len; } -static void tcp_update_ack_edge(void) +static void tcp_update_ack_edge(struct tcp_stream *tcp) { - if (tcp_seq_cmp(tcp_ack_edge, tcp_lost.hill[0].l) >= 0) { - tcp_ack_edge = tcp_lost.hill[0].r; + if (tcp_seq_cmp(tcp->ack_edge, tcp->lost.hill[0].l) >= 0) { + tcp->ack_edge = tcp->lost.hill[0].r; - memmove(&tcp_lost.hill[0], &tcp_lost.hill[1], + memmove(&tcp->lost.hill[0], &tcp->lost.hill[1], (TCP_SACK_HILLS - 1) * sizeof(struct sack_edges)); - tcp_lost.len -= TCP_OPT_LEN_8; - tcp_lost.hill[TCP_SACK_HILLS - 1].l = TCP_O_NOP; - tcp_lost.hill[TCP_SACK_HILLS - 1].r = TCP_O_NOP; + tcp->lost.len -= TCP_OPT_LEN_8; + tcp->lost.hill[TCP_SACK_HILLS - 1].l = TCP_O_NOP; + tcp->lost.hill[TCP_SACK_HILLS - 1].r = TCP_O_NOP; } } /** * tcp_hole() - Selective Acknowledgment (Essential for fast stream transfer) + * @tcp: tcp stream * @tcp_seq_num: TCP sequence start number * @len: the length of sequence numbers */ -void tcp_hole(u32 tcp_seq_num, u32 len) +void tcp_hole(struct tcp_stream *tcp, u32 tcp_seq_num, u32 len) { int i, j, cnt, cnt_move; - cnt = (tcp_lost.len - TCP_OPT_LEN_2) / TCP_OPT_LEN_8; + cnt = (tcp->lost.len - TCP_OPT_LEN_2) / TCP_OPT_LEN_8; for (i = 0; i < cnt; i++) { - if (tcp_seq_cmp(tcp_lost.hill[i].r, tcp_seq_num) < 0) + if (tcp_seq_cmp(tcp->lost.hill[i].r, tcp_seq_num) < 0) continue; - if (tcp_seq_cmp(tcp_lost.hill[i].l, tcp_seq_num + len) > 0) + if (tcp_seq_cmp(tcp->lost.hill[i].l, tcp_seq_num + len) > 0) break; - if (tcp_seq_cmp(tcp_lost.hill[i].l, tcp_seq_num) > 0) - tcp_lost.hill[i].l = tcp_seq_num; - if (tcp_seq_cmp(tcp_lost.hill[i].l, tcp_seq_num) < 0) { - len += tcp_seq_num - tcp_lost.hill[i].l; - tcp_seq_num = tcp_lost.hill[i].l; + if (tcp_seq_cmp(tcp->lost.hill[i].l, tcp_seq_num) > 0) + tcp->lost.hill[i].l = tcp_seq_num; + if (tcp_seq_cmp(tcp->lost.hill[i].l, tcp_seq_num) < 0) { + len += tcp_seq_num - tcp->lost.hill[i].l; + tcp_seq_num = tcp->lost.hill[i].l; } - if (tcp_seq_cmp(tcp_lost.hill[i].r, tcp_seq_num + len) >= 0) { - tcp_update_ack_edge(); + if (tcp_seq_cmp(tcp->lost.hill[i].r, tcp_seq_num + len) >= 0) { + tcp_update_ack_edge(tcp); return; } /* check overlapping with next hills */ cnt_move = 0; - tcp_lost.hill[i].r = tcp_seq_num + len; + tcp->lost.hill[i].r = tcp_seq_num + len; for (j = i + 1; j < cnt; j++) { - if (tcp_seq_cmp(tcp_lost.hill[j].l, tcp_lost.hill[i].r) > 0) + if (tcp_seq_cmp(tcp->lost.hill[j].l, tcp->lost.hill[i].r) > 0) break; - tcp_lost.hill[i].r = tcp_lost.hill[j].r; + tcp->lost.hill[i].r = tcp->lost.hill[j].r; cnt_move++; } if (cnt_move > 0) { if (cnt > i + cnt_move + 1) - memmove(&tcp_lost.hill[i + 1], - &tcp_lost.hill[i + cnt_move + 1], + memmove(&tcp->lost.hill[i + 1], + &tcp->lost.hill[i + cnt_move + 1], cnt_move * sizeof(struct sack_edges)); cnt -= cnt_move; - tcp_lost.len = TCP_OPT_LEN_2 + cnt * TCP_OPT_LEN_8; + tcp->lost.len = TCP_OPT_LEN_2 + cnt * TCP_OPT_LEN_8; for (j = cnt; j < TCP_SACK_HILLS; j++) { - tcp_lost.hill[j].l = TCP_O_NOP; - tcp_lost.hill[j].r = TCP_O_NOP; + tcp->lost.hill[j].l = TCP_O_NOP; + tcp->lost.hill[j].r = TCP_O_NOP; } } - tcp_update_ack_edge(); + tcp_update_ack_edge(tcp); return; } if (i == TCP_SACK_HILLS) { - tcp_update_ack_edge(); + tcp_update_ack_edge(tcp); return; } @@ -428,23 +426,24 @@ void tcp_hole(u32 tcp_seq_num, u32 len) } if (cnt_move > 0) - memmove(&tcp_lost.hill[i + 1], - &tcp_lost.hill[i], + memmove(&tcp->lost.hill[i + 1], + &tcp->lost.hill[i], cnt_move * sizeof(struct sack_edges)); - tcp_lost.hill[i].l = tcp_seq_num; - tcp_lost.hill[i].r = tcp_seq_num + len; - tcp_lost.len = TCP_OPT_LEN_2 + cnt * TCP_OPT_LEN_8; + tcp->lost.hill[i].l = tcp_seq_num; + tcp->lost.hill[i].r = tcp_seq_num + len; + tcp->lost.len = TCP_OPT_LEN_2 + cnt * TCP_OPT_LEN_8; - tcp_update_ack_edge(); + tcp_update_ack_edge(tcp); }; /** * tcp_parse_options() - parsing TCP options + * @tcp: tcp stream * @o: pointer to the option field. * @o_len: length of the option field. */ -void tcp_parse_options(uchar *o, int o_len) +void tcp_parse_options(struct tcp_stream *tcp, uchar *o, int o_len) { struct tcp_t_opt *tsopt; uchar *p = o; @@ -467,7 +466,7 @@ void tcp_parse_options(uchar *o, int o_len) break; case TCP_O_TS: tsopt = (struct tcp_t_opt *)p; - rmt_timestamp = tsopt->t_snd; + tcp->rmt_timestamp = tsopt->t_snd; break; } @@ -479,7 +478,8 @@ void tcp_parse_options(uchar *o, int o_len) } } -static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) +static u8 tcp_state_machine(struct tcp_stream *tcp, u8 tcp_flags, + u32 tcp_seq_num, int payload_len) { u8 tcp_fin = tcp_flags & TCP_FIN; u8 tcp_syn = tcp_flags & TCP_SYN; @@ -500,21 +500,21 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) debug_cond(DEBUG_INT_STATE, "TCP STATE ENTRY %x\n", action); if (tcp_rst) { action = TCP_DATA; - current_tcp_state = TCP_CLOSED; + tcp->state = TCP_CLOSED; net_set_state(NETLOOP_FAIL); debug_cond(DEBUG_INT_STATE, "TCP Reset %x\n", tcp_flags); return TCP_RST; } - switch (current_tcp_state) { + switch (tcp->state) { case TCP_CLOSED: debug_cond(DEBUG_INT_STATE, "TCP CLOSED %x\n", tcp_flags); if (tcp_syn) { action = TCP_SYN | TCP_ACK; - tcp_seq_init = tcp_seq_num; - tcp_ack_edge = tcp_seq_num + 1; - tcp_lost.len = TCP_OPT_LEN_2; - current_tcp_state = TCP_SYN_RECEIVED; + tcp->seq_init = tcp_seq_num; + tcp->ack_edge = tcp_seq_num + 1; + tcp->lost.len = TCP_OPT_LEN_2; + tcp->state = TCP_SYN_RECEIVED; } else if (tcp_ack || tcp_fin) { action = TCP_DATA; } @@ -525,12 +525,12 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) tcp_flags, tcp_seq_num); if (tcp_fin) { action = action | TCP_PUSH; - current_tcp_state = TCP_CLOSE_WAIT; + tcp->state = TCP_CLOSE_WAIT; } else if (tcp_ack || (tcp_syn && tcp_ack)) { action |= TCP_ACK; - tcp_seq_init = tcp_seq_num; - tcp_ack_edge = tcp_seq_num + 1; - current_tcp_state = TCP_ESTABLISHED; + tcp->seq_init = tcp_seq_num; + tcp->ack_edge = tcp_seq_num + 1; + tcp->state = TCP_ESTABLISHED; if (tcp_syn && tcp_ack) action |= TCP_PUSH; @@ -541,15 +541,15 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) case TCP_ESTABLISHED: debug_cond(DEBUG_INT_STATE, "TCP_ESTABLISHED %x\n", tcp_flags); if (payload_len > 0) { - tcp_hole(tcp_seq_num, payload_len); + tcp_hole(tcp, tcp_seq_num, payload_len); tcp_fin = TCP_DATA; /* cause standalone FIN */ } if ((tcp_fin) && (!IS_ENABLED(CONFIG_PROT_TCP_SACK) || - tcp_lost.len <= TCP_OPT_LEN_2)) { + tcp->lost.len <= TCP_OPT_LEN_2)) { action = action | TCP_FIN | TCP_PUSH | TCP_ACK; - current_tcp_state = TCP_CLOSE_WAIT; + tcp->state = TCP_CLOSE_WAIT; } else if (tcp_ack) { action = TCP_DATA; } @@ -567,7 +567,7 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_2 (%x)\n", tcp_flags); if (tcp_ack) { action = TCP_PUSH | TCP_ACK; - current_tcp_state = TCP_CLOSED; + tcp->state = TCP_CLOSED; puts("\n"); } else if (tcp_syn) { action = TCP_DATA; @@ -578,20 +578,20 @@ static u8 tcp_state_machine(u8 tcp_flags, u32 tcp_seq_num, int payload_len) case TCP_FIN_WAIT_1: debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_1 (%x)\n", tcp_flags); if (tcp_fin) { - tcp_ack_edge++; + tcp->ack_edge++; action = TCP_ACK | TCP_FIN; - current_tcp_state = TCP_FIN_WAIT_2; + tcp->state = TCP_FIN_WAIT_2; } if (tcp_syn) action = TCP_RST; if (tcp_ack) - current_tcp_state = TCP_CLOSED; + tcp->state = TCP_CLOSED; break; case TCP_CLOSING: debug_cond(DEBUG_INT_STATE, "TCP_CLOSING (%x)\n", tcp_flags); if (tcp_ack) { action = TCP_PUSH; - current_tcp_state = TCP_CLOSED; + tcp->state = TCP_CLOSED; puts("\n"); } else if (tcp_syn) { action = TCP_RST; @@ -615,6 +615,7 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) u8 tcp_action = TCP_DATA; u32 tcp_seq_num, tcp_ack_num; int tcp_hdr_len, payload_len; + struct tcp_stream *tcp; /* Verify IP header */ debug_cond(DEBUG_DEV_PKT, @@ -643,11 +644,15 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) return; } + tcp = tcp_stream_get(); + if (!tcp) + return; + tcp_hdr_len = GET_TCP_HDR_LEN_IN_BYTES(b->ip.hdr.tcp_hlen); payload_len = tcp_len - tcp_hdr_len; if (tcp_hdr_len > TCP_HDR_SIZE) - tcp_parse_options((uchar *)b + IP_TCP_HDR_SIZE, + tcp_parse_options(tcp, (uchar *)b + IP_TCP_HDR_SIZE, tcp_hdr_len - TCP_HDR_SIZE); /* * Incoming sequence and ack numbers are server's view of the numbers. @@ -657,7 +662,7 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) tcp_ack_num = ntohl(b->ip.hdr.tcp_ack); /* Packets are not ordered. Send to app as received. */ - tcp_action = tcp_state_machine(b->ip.hdr.tcp_flags, + tcp_action = tcp_state_machine(tcp, b->ip.hdr.tcp_flags, tcp_seq_num, payload_len); tcp_activity_count++; @@ -678,7 +683,7 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) } else if (tcp_action != TCP_DATA) { debug_cond(DEBUG_DEV_PKT, "TCP Action (action=%x,Seq=%u,Ack=%u,Pay=%d)\n", - tcp_action, tcp_ack_num, tcp_ack_edge, payload_len); + tcp_action, tcp_ack_num, tcp->ack_edge, payload_len); /* * Warning: Incoming Ack & Seq sequence numbers are transposed @@ -687,6 +692,6 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) net_send_tcp_packet(0, ntohs(b->ip.hdr.tcp_src), ntohs(b->ip.hdr.tcp_dst), (tcp_action & (~TCP_PUSH)), - tcp_ack_num, tcp_ack_edge); + tcp_ack_num, tcp->ack_edge); } } diff --git a/net/wget.c b/net/wget.c index d338eaf4ef3..0213e3ff51d 100644 --- a/net/wget.c +++ b/net/wget.c @@ -365,7 +365,8 @@ static void wget_handler(uchar *pkt, u16 dport, u32 tcp_seq_num, u32 tcp_ack_num, u8 action, unsigned int len) { - enum tcp_state wget_tcp_state = tcp_get_tcp_state(); + struct tcp_stream *tcp = tcp_stream_get(); + enum tcp_state wget_tcp_state = tcp_get_tcp_state(tcp); net_set_timeout_handler(wget_timeout, wget_timeout_handler); packets++; -- cgit v1.3.1 From 2b1774987031d6f30fb773bd84e91884f35fbc8d Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Sat, 28 Dec 2024 13:46:30 +0300 Subject: net/tcp: add connection info to tcp_stream structure Changes: * Avoid use net_server_ip in tcp code, use tcp_stream data instead * Ignore packets from other connections if connection already created. This prevents us from connection break caused by other tcp stream. Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Simon Glass --- include/net-legacy.h | 5 +- include/net/tcp.h | 57 ++++++++++++++++++++--- net/fastboot_tcp.c | 50 +++++++++++--------- net/net.c | 12 ++--- net/tcp.c | 129 +++++++++++++++++++++++++++++++++++++++------------ net/wget.c | 52 +++++++-------------- 6 files changed, 203 insertions(+), 102 deletions(-) (limited to 'include') diff --git a/include/net-legacy.h b/include/net-legacy.h index 1f62ebff51d..bc0f0cde9fe 100644 --- a/include/net-legacy.h +++ b/include/net-legacy.h @@ -416,6 +416,7 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, /** * net_send_tcp_packet() - Transmit TCP packet. * @payload_len: length of payload + * @dhost: Destination host * @dport: Destination TCP port * @sport: Source TCP port * @action: TCP action to be performed @@ -424,8 +425,8 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, * * Return: 0 on success, other value on failure */ -int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action, - u32 tcp_seq_num, u32 tcp_ack_num); +int net_send_tcp_packet(int payload_len, struct in_addr dhost, int dport, + int sport, u8 action, u32 tcp_seq_num, u32 tcp_ack_num); int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport, int payload_len); diff --git a/include/net/tcp.h b/include/net/tcp.h index 14aee64cb1c..f224d0cae2f 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -279,6 +279,9 @@ enum tcp_state { /** * struct tcp_stream - TCP data stream structure + * @rhost: Remote host, network byte order + * @rport: Remote port, host byte order + * @lport: Local port, host byte order * * @state: TCP connection state * @@ -291,6 +294,10 @@ enum tcp_state { * @lost: Used for SACK */ struct tcp_stream { + struct in_addr rhost; + u16 rport; + u16 lport; + /* TCP connection state */ enum tcp_state state; @@ -305,16 +312,53 @@ struct tcp_stream { struct tcp_sack_v lost; }; -struct tcp_stream *tcp_stream_get(void); +void tcp_init(void); + +typedef int tcp_incoming_filter(struct in_addr rhost, + u16 rport, u16 sport); + +/* + * This function sets user callback used to accept/drop incoming + * connections. Callback should: + * + Check TCP stream endpoint and make connection verdict + * - return non-zero value to accept connection + * - return zero to drop connection + * + * WARNING: If callback is NOT defined, all incoming connections + * will be dropped. + */ +void tcp_set_incoming_filter(tcp_incoming_filter *filter); + +/* + * tcp_stream_get -- Get or create TCP stream + * @is_new: if non-zero and no stream found, then create a new one + * @rhost: Remote host, network byte order + * @rport: Remote port, host byte order + * @lport: Local port, host byte order + * + * Returns: TCP stream structure or NULL (if not found/created) + */ +struct tcp_stream *tcp_stream_get(int is_new, struct in_addr rhost, + u16 rport, u16 lport); + +/* + * tcp_stream_connect -- Create new TCP stream for remote connection. + * @rhost: Remote host, network byte order + * @rport: Remote port, host byte order + * + * Returns: TCP new stream structure or NULL (if not created). + * Random local port will be used. + */ +struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport); + +enum tcp_state tcp_stream_get_state(struct tcp_stream *tcp); -enum tcp_state tcp_get_tcp_state(struct tcp_stream *tcp); -void tcp_set_tcp_state(struct tcp_stream *tcp, enum tcp_state new_state); -int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, - int sport, int payload_len, +int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, u8 action, u32 tcp_seq_num, u32 tcp_ack_num); /** * rxhand_tcp() - An incoming packet handler. + * @tcp: TCP stream * @pkt: pointer to the application packet * @dport: destination TCP port * @sip: source IP address @@ -324,8 +368,7 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, * @action: TCP action (SYN, ACK, FIN, etc) * @len: packet length */ -typedef void rxhand_tcp(uchar *pkt, u16 dport, - struct in_addr sip, u16 sport, +typedef void rxhand_tcp(struct tcp_stream *tcp, uchar *pkt, u32 tcp_seq_num, u32 tcp_ack_num, u8 action, unsigned int len); void tcp_set_tcp_handler(rxhand_tcp *f); diff --git a/net/fastboot_tcp.c b/net/fastboot_tcp.c index d1fccbc7238..4d34fdc5a45 100644 --- a/net/fastboot_tcp.c +++ b/net/fastboot_tcp.c @@ -8,14 +8,14 @@ #include #include -static char command[FASTBOOT_COMMAND_LEN] = {0}; -static char response[FASTBOOT_RESPONSE_LEN] = {0}; +#define FASTBOOT_TCP_PORT 5554 + +static char command[FASTBOOT_COMMAND_LEN]; +static char response[FASTBOOT_RESPONSE_LEN]; static const unsigned short handshake_length = 4; static const uchar *handshake = "FB01"; -static u16 curr_sport; -static u16 curr_dport; static u32 curr_tcp_seq_num; static u32 curr_tcp_ack_num; static unsigned int curr_request_len; @@ -25,34 +25,37 @@ static enum fastboot_tcp_state { FASTBOOT_DISCONNECTING } state = FASTBOOT_CLOSED; -static void fastboot_tcp_answer(u8 action, unsigned int len) +static void fastboot_tcp_answer(struct tcp_stream *tcp, u8 action, + unsigned int len) { const u32 response_seq_num = curr_tcp_ack_num; const u32 response_ack_num = curr_tcp_seq_num + (curr_request_len > 0 ? curr_request_len : 1); - net_send_tcp_packet(len, htons(curr_sport), htons(curr_dport), + net_send_tcp_packet(len, tcp->rhost, tcp->rport, tcp->lport, action, response_seq_num, response_ack_num); } -static void fastboot_tcp_reset(void) +static void fastboot_tcp_reset(struct tcp_stream *tcp) { - fastboot_tcp_answer(TCP_RST, 0); + fastboot_tcp_answer(tcp, TCP_RST, 0); state = FASTBOOT_CLOSED; } -static void fastboot_tcp_send_packet(u8 action, const uchar *data, unsigned int len) +static void fastboot_tcp_send_packet(struct tcp_stream *tcp, u8 action, + const uchar *data, unsigned int len) { uchar *pkt = net_get_async_tx_pkt_buf(); memset(pkt, '\0', PKTSIZE); pkt += net_eth_hdr_size() + IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; memcpy(pkt, data, len); - fastboot_tcp_answer(action, len); + fastboot_tcp_answer(tcp, action, len); memset(pkt, '\0', PKTSIZE); } -static void fastboot_tcp_send_message(const char *message, unsigned int len) +static void fastboot_tcp_send_message(struct tcp_stream *tcp, + const char *message, unsigned int len) { __be64 len_be = __cpu_to_be64(len); uchar *pkt = net_get_async_tx_pkt_buf(); @@ -63,12 +66,11 @@ static void fastboot_tcp_send_message(const char *message, unsigned int len) memcpy(pkt, &len_be, 8); pkt += 8; memcpy(pkt, message, len); - fastboot_tcp_answer(TCP_ACK | TCP_PUSH, len + 8); + fastboot_tcp_answer(tcp, TCP_ACK | TCP_PUSH, len + 8); memset(pkt, '\0', PKTSIZE); } -static void fastboot_tcp_handler_ipv4(uchar *pkt, u16 dport, - struct in_addr sip, u16 sport, +static void fastboot_tcp_handler_ipv4(struct tcp_stream *tcp, uchar *pkt, u32 tcp_seq_num, u32 tcp_ack_num, u8 action, unsigned int len) { @@ -77,8 +79,6 @@ static void fastboot_tcp_handler_ipv4(uchar *pkt, u16 dport, u8 tcp_fin = action & TCP_FIN; u8 tcp_push = action & TCP_PUSH; - curr_sport = sport; - curr_dport = dport; curr_tcp_seq_num = tcp_seq_num; curr_tcp_ack_num = tcp_ack_num; curr_request_len = len; @@ -89,17 +89,17 @@ static void fastboot_tcp_handler_ipv4(uchar *pkt, u16 dport, if (len != handshake_length || strlen(pkt) != handshake_length || memcmp(pkt, handshake, handshake_length) != 0) { - fastboot_tcp_reset(); + fastboot_tcp_reset(tcp); break; } - fastboot_tcp_send_packet(TCP_ACK | TCP_PUSH, + fastboot_tcp_send_packet(tcp, TCP_ACK | TCP_PUSH, handshake, handshake_length); state = FASTBOOT_CONNECTED; } break; case FASTBOOT_CONNECTED: if (tcp_fin) { - fastboot_tcp_answer(TCP_FIN | TCP_ACK, 0); + fastboot_tcp_answer(tcp, TCP_FIN | TCP_ACK, 0); state = FASTBOOT_DISCONNECTING; break; } @@ -111,12 +111,12 @@ static void fastboot_tcp_handler_ipv4(uchar *pkt, u16 dport, // Only single packet messages are supported ATM if (strlen(pkt) != command_size) { - fastboot_tcp_reset(); + fastboot_tcp_reset(tcp); break; } strlcpy(command, pkt, len + 1); fastboot_command_id = fastboot_handle_command(command, response); - fastboot_tcp_send_message(response, strlen(response)); + fastboot_tcp_send_message(tcp, response, strlen(response)); fastboot_handle_boot(fastboot_command_id, strncmp("OKAY", response, 4) == 0); } @@ -129,17 +129,21 @@ static void fastboot_tcp_handler_ipv4(uchar *pkt, u16 dport, memset(command, 0, FASTBOOT_COMMAND_LEN); memset(response, 0, FASTBOOT_RESPONSE_LEN); - curr_sport = 0; - curr_dport = 0; curr_tcp_seq_num = 0; curr_tcp_ack_num = 0; curr_request_len = 0; } +static int incoming_filter(struct in_addr rhost, u16 rport, u16 lport) +{ + return (lport == FASTBOOT_TCP_PORT); +} + void fastboot_tcp_start_server(void) { printf("Using %s device\n", eth_get_name()); printf("Listening for fastboot command on tcp %pI4\n", &net_ip); + tcp_set_incoming_filter(incoming_filter); tcp_set_tcp_handler(fastboot_tcp_handler_ipv4); } diff --git a/net/net.c b/net/net.c index e12ac55c401..62d1c5b1e82 100644 --- a/net/net.c +++ b/net/net.c @@ -420,7 +420,7 @@ int net_init(void) /* Only need to setup buffer pointers once. */ first_call = 0; if (IS_ENABLED(CONFIG_PROT_TCP)) - tcp_set_tcp_state(tcp_stream_get(), TCP_CLOSED); + tcp_init(); } return net_init_loop(); @@ -908,10 +908,10 @@ int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport, } #if defined(CONFIG_PROT_TCP) -int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action, - u32 tcp_seq_num, u32 tcp_ack_num) +int net_send_tcp_packet(int payload_len, struct in_addr dhost, int dport, + int sport, u8 action, u32 tcp_seq_num, u32 tcp_ack_num) { - return net_send_ip_packet(net_server_ethaddr, net_server_ip, dport, + return net_send_ip_packet(net_server_ethaddr, dhost, dport, sport, payload_len, IPPROTO_TCP, action, tcp_seq_num, tcp_ack_num); } @@ -953,12 +953,12 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, break; #if defined(CONFIG_PROT_TCP) case IPPROTO_TCP: - tcp = tcp_stream_get(); + tcp = tcp_stream_get(0, dest, dport, sport); if (!tcp) return -EINVAL; pkt_hdr_size = eth_hdr_size - + tcp_set_tcp_header(tcp, pkt + eth_hdr_size, dport, sport, + + tcp_set_tcp_header(tcp, pkt + eth_hdr_size, payload_len, action, tcp_seq_num, tcp_ack_num); break; diff --git a/net/tcp.c b/net/tcp.c index 8eeb43b8796..db708f0a2a5 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -26,6 +26,7 @@ static int tcp_activity_count; static struct tcp_stream tcp_stream; +static tcp_incoming_filter *incoming_filter; /* * TCP lengths are stored as a rounded up number of 32 bit words. @@ -40,40 +41,95 @@ static struct tcp_stream tcp_stream; /* Current TCP RX packet handler */ static rxhand_tcp *tcp_packet_handler; +#define RANDOM_PORT_START 1024 +#define RANDOM_PORT_RANGE 0x4000 + +/** + * random_port() - make port a little random (1024-17407) + * + * Return: random port number from 1024 to 17407 + * + * This keeps the math somewhat trivial to compute, and seems to work with + * all supported protocols/clients/servers + */ +static uint random_port(void) +{ + return RANDOM_PORT_START + (get_timer(0) % RANDOM_PORT_RANGE); +} + static inline s32 tcp_seq_cmp(u32 a, u32 b) { return (s32)(a - b); } /** - * tcp_get_tcp_state() - get TCP stream state + * tcp_stream_get_state() - get TCP stream state * @tcp: tcp stream * * Return: TCP stream state */ -enum tcp_state tcp_get_tcp_state(struct tcp_stream *tcp) +enum tcp_state tcp_stream_get_state(struct tcp_stream *tcp) { return tcp->state; } /** - * tcp_set_tcp_state() - set TCP stream state + * tcp_stream_set_state() - set TCP stream state * @tcp: tcp stream * @new_state: new TCP state */ -void tcp_set_tcp_state(struct tcp_stream *tcp, - enum tcp_state new_state) +static void tcp_stream_set_state(struct tcp_stream *tcp, + enum tcp_state new_state) { tcp->state = new_state; } -struct tcp_stream *tcp_stream_get(void) +void tcp_init(void) +{ + incoming_filter = NULL; + tcp_stream.state = TCP_CLOSED; +} + +void tcp_set_incoming_filter(tcp_incoming_filter *filter) +{ + incoming_filter = filter; +} + +static struct tcp_stream *tcp_stream_add(struct in_addr rhost, + u16 rport, u16 lport) +{ + struct tcp_stream *tcp = &tcp_stream; + + if (tcp->state != TCP_CLOSED) + return NULL; + + memset(tcp, 0, sizeof(struct tcp_stream)); + tcp->rhost.s_addr = rhost.s_addr; + tcp->rport = rport; + tcp->lport = lport; + tcp->state = TCP_CLOSED; + tcp->lost.len = TCP_OPT_LEN_2; + return tcp; +} + +struct tcp_stream *tcp_stream_get(int is_new, struct in_addr rhost, + u16 rport, u16 lport) { - return &tcp_stream; + struct tcp_stream *tcp = &tcp_stream; + + if (tcp->rhost.s_addr == rhost.s_addr && + tcp->rport == rport && + tcp->lport == lport) + return tcp; + + if (!is_new || !incoming_filter || + !incoming_filter(rhost, rport, lport)) + return NULL; + + return tcp_stream_add(rhost, rport, lport); } -static void dummy_handler(uchar *pkt, u16 dport, - struct in_addr sip, u16 sport, +static void dummy_handler(struct tcp_stream *tcp, uchar *pkt, u32 tcp_seq_num, u32 tcp_ack_num, u8 action, unsigned int len) { @@ -222,8 +278,7 @@ void net_set_syn_options(struct tcp_stream *tcp, union tcp_build_pkt *b) b->ip.end = TCP_O_END; } -int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, - int sport, int payload_len, +int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, u8 action, u32 tcp_seq_num, u32 tcp_ack_num) { union tcp_build_pkt *b = (union tcp_build_pkt *)pkt; @@ -243,7 +298,7 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, case TCP_SYN: debug_cond(DEBUG_DEV_PKT, "TCP Hdr:SYN (%pI4, %pI4, sq=%u, ak=%u)\n", - &net_server_ip, &net_ip, + &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num); tcp_activity_count = 0; net_set_syn_options(tcp, b); @@ -264,13 +319,13 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, b->ip.hdr.tcp_flags = action; debug_cond(DEBUG_DEV_PKT, "TCP Hdr:ACK (%pI4, %pI4, s=%u, a=%u, A=%x)\n", - &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num, + &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num, action); break; case TCP_FIN: debug_cond(DEBUG_DEV_PKT, "TCP Hdr:FIN (%pI4, %pI4, s=%u, a=%u)\n", - &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); + &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num); payload_len = 0; pkt_hdr_len = IP_TCP_HDR_SIZE; tcp->state = TCP_FIN_WAIT_1; @@ -279,7 +334,7 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, case TCP_RST: debug_cond(DEBUG_DEV_PKT, "TCP Hdr:RST (%pI4, %pI4, s=%u, a=%u)\n", - &net_server_ip, &net_ip, tcp_seq_num, tcp_ack_num); + &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num); tcp->state = TCP_CLOSED; break; /* Notify connection closing */ @@ -290,7 +345,7 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, debug_cond(DEBUG_DEV_PKT, "TCP Hdr:FIN ACK PSH(%pI4, %pI4, s=%u, a=%u, A=%x)\n", - &net_server_ip, &net_ip, + &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num, action); fallthrough; default: @@ -298,7 +353,7 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, b->ip.hdr.tcp_flags = action | TCP_PUSH | TCP_ACK; debug_cond(DEBUG_DEV_PKT, "TCP Hdr:dft (%pI4, %pI4, s=%u, a=%u, A=%x)\n", - &net_server_ip, &net_ip, + &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num, action); } @@ -308,8 +363,8 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, tcp->ack_edge = tcp_ack_num; /* TCP Header */ b->ip.hdr.tcp_ack = htonl(tcp->ack_edge); - b->ip.hdr.tcp_src = htons(sport); - b->ip.hdr.tcp_dst = htons(dport); + b->ip.hdr.tcp_src = htons(tcp->lport); + b->ip.hdr.tcp_dst = htons(tcp->rport); b->ip.hdr.tcp_seq = htonl(tcp_seq_num); /* @@ -332,10 +387,10 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int dport, b->ip.hdr.tcp_xsum = 0; b->ip.hdr.tcp_ugr = 0; - b->ip.hdr.tcp_xsum = tcp_set_pseudo_header(pkt, net_ip, net_server_ip, + b->ip.hdr.tcp_xsum = tcp_set_pseudo_header(pkt, net_ip, tcp->rhost, tcp_len, pkt_len); - net_set_ip_header((uchar *)&b->ip, net_server_ip, net_ip, + net_set_ip_header((uchar *)&b->ip, tcp->rhost, net_ip, pkt_len, IPPROTO_TCP); return pkt_hdr_len; @@ -616,19 +671,26 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) u32 tcp_seq_num, tcp_ack_num; int tcp_hdr_len, payload_len; struct tcp_stream *tcp; + struct in_addr src; /* Verify IP header */ debug_cond(DEBUG_DEV_PKT, "TCP RX in RX Sum (to=%pI4, from=%pI4, len=%d)\n", &b->ip.hdr.ip_src, &b->ip.hdr.ip_dst, pkt_len); - b->ip.hdr.ip_src = net_server_ip; + /* + * src IP address will be destroyed by TCP checksum verification + * algorithm (see tcp_set_pseudo_header()), so remember it before + * it was garbaged. + */ + src.s_addr = b->ip.hdr.ip_src.s_addr; + b->ip.hdr.ip_dst = net_ip; b->ip.hdr.ip_sum = 0; if (tcp_rx_xsum != compute_ip_checksum(b, IP_HDR_SIZE)) { debug_cond(DEBUG_DEV_PKT, "TCP RX IP xSum Error (%pI4, =%pI4, len=%d)\n", - &net_ip, &net_server_ip, pkt_len); + &net_ip, &src, pkt_len); return; } @@ -640,11 +702,14 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) pkt_len)) { debug_cond(DEBUG_DEV_PKT, "TCP RX TCP xSum Error (%pI4, %pI4, len=%d)\n", - &net_ip, &net_server_ip, tcp_len); + &net_ip, &src, tcp_len); return; } - tcp = tcp_stream_get(); + tcp = tcp_stream_get(b->ip.hdr.tcp_flags & TCP_SYN, + src, + ntohs(b->ip.hdr.tcp_src), + ntohs(b->ip.hdr.tcp_dst)); if (!tcp) return; @@ -676,9 +741,9 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) "TCP Notify (action=%x, Seq=%u,Ack=%u,Pay%d)\n", tcp_action, tcp_seq_num, tcp_ack_num, payload_len); - (*tcp_packet_handler) ((uchar *)b + pkt_len - payload_len, b->ip.hdr.tcp_dst, - b->ip.hdr.ip_src, b->ip.hdr.tcp_src, tcp_seq_num, - tcp_ack_num, tcp_action, payload_len); + (*tcp_packet_handler) (tcp, (uchar *)b + pkt_len - payload_len, + tcp_seq_num, tcp_ack_num, tcp_action, + payload_len); } else if (tcp_action != TCP_DATA) { debug_cond(DEBUG_DEV_PKT, @@ -689,9 +754,13 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) * Warning: Incoming Ack & Seq sequence numbers are transposed * here to outgoing Seq & Ack sequence numbers */ - net_send_tcp_packet(0, ntohs(b->ip.hdr.tcp_src), - ntohs(b->ip.hdr.tcp_dst), + net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, (tcp_action & (~TCP_PUSH)), tcp_ack_num, tcp->ack_edge); } } + +struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport) +{ + return tcp_stream_add(rhost, rport, random_port()); +} diff --git a/net/wget.c b/net/wget.c index 0213e3ff51d..a175533ada9 100644 --- a/net/wget.c +++ b/net/wget.c @@ -28,9 +28,8 @@ static const char bootfile3[] = " HTTP/1.0\r\n\r\n"; static const char http_eom[] = "\r\n\r\n"; static const char content_len[] = "Content-Length"; static const char linefeed[] = "\r\n"; -static struct in_addr web_server_ip; -static int our_port; static int wget_timeout_count; +struct tcp_stream *tcp; struct pkt_qd { uchar *pkt; @@ -110,22 +109,19 @@ static void wget_send_stored(void) int len = retry_len; unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len); unsigned int tcp_seq_num = retry_tcp_ack_num; - unsigned int server_port; uchar *ptr, *offset; - server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff; - switch (current_wget_state) { case WGET_CLOSED: debug_cond(DEBUG_WGET, "wget: send SYN\n"); current_wget_state = WGET_CONNECTING; - net_send_tcp_packet(0, server_port, our_port, action, + net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, action, tcp_seq_num, tcp_ack_num); packets = 0; break; case WGET_CONNECTING: pkt_q_idx = 0; - net_send_tcp_packet(0, server_port, our_port, action, + net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, action, tcp_seq_num, tcp_ack_num); ptr = net_tx_packet + net_eth_hdr_size() + @@ -149,14 +145,14 @@ static void wget_send_stored(void) memcpy(offset, &bootfile3, strlen(bootfile3)); offset += strlen(bootfile3); - net_send_tcp_packet((offset - ptr), server_port, our_port, + net_send_tcp_packet((offset - ptr), tcp->rhost, tcp->rport, tcp->lport, TCP_PUSH, tcp_seq_num, tcp_ack_num); current_wget_state = WGET_CONNECTED; break; case WGET_CONNECTED: case WGET_TRANSFERRING: case WGET_TRANSFERRED: - net_send_tcp_packet(0, server_port, our_port, action, + net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, action, tcp_seq_num, tcp_ack_num); break; } @@ -348,10 +344,8 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, /** * wget_handler() - TCP handler of wget + * @tcp: TCP stream * @pkt: pointer to the application packet - * @dport: destination TCP port - * @sip: source IP address - * @sport: source TCP port * @tcp_seq_num: TCP sequential number * @tcp_ack_num: TCP acknowledgment number * @action: TCP action (SYN, ACK, FIN, etc) @@ -360,13 +354,11 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, * In the "application push" invocation, the TCP header with all * its information is pointed to by the packet pointer. */ -static void wget_handler(uchar *pkt, u16 dport, - struct in_addr sip, u16 sport, +static void wget_handler(struct tcp_stream *tcp, uchar *pkt, u32 tcp_seq_num, u32 tcp_ack_num, u8 action, unsigned int len) { - struct tcp_stream *tcp = tcp_stream_get(); - enum tcp_state wget_tcp_state = tcp_get_tcp_state(tcp); + enum tcp_state wget_tcp_state = tcp_stream_get_state(tcp); net_set_timeout_handler(wget_timeout, wget_timeout_handler); packets++; @@ -457,26 +449,13 @@ static void wget_handler(uchar *pkt, u16 dport, } } -#define RANDOM_PORT_START 1024 -#define RANDOM_PORT_RANGE 0x4000 - -/** - * random_port() - make port a little random (1024-17407) - * - * Return: random port number from 1024 to 17407 - * - * This keeps the math somewhat trivial to compute, and seems to work with - * all supported protocols/clients/servers - */ -static unsigned int random_port(void) -{ - return RANDOM_PORT_START + (get_timer(0) % RANDOM_PORT_RANGE); -} - #define BLOCKSIZE 512 void wget_start(void) { + struct in_addr web_server_ip; + unsigned int server_port; + if (!wget_info) wget_info = &default_wget_info; @@ -523,8 +502,6 @@ void wget_start(void) wget_timeout_count = 0; current_wget_state = WGET_CLOSED; - our_port = random_port(); - /* * Zero out server ether to force arp resolution in case * the server ip for the previous u-boot command, for example dns @@ -533,6 +510,13 @@ void wget_start(void) memset(net_server_ethaddr, 0, 6); + server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff; + tcp = tcp_stream_connect(web_server_ip, server_port); + if (!tcp) { + net_set_state(NETLOOP_FAIL); + return; + } + wget_send(TCP_SYN, 0, 0, 0); } -- cgit v1.3.1 From 82bf3aafa6378f1fdb3b9e3daca74db6aac38ed3 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Sat, 28 Dec 2024 13:46:31 +0300 Subject: net/tcp: rename ack_edge and seq_init to more common rcv_nxt and irs Use the names from RFC 9293 Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Simon Glass --- include/net/tcp.h | 8 ++++---- net/tcp.c | 32 ++++++++++++++++---------------- 2 files changed, 20 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/net/tcp.h b/include/net/tcp.h index f224d0cae2f..0694af9d5b1 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -285,8 +285,8 @@ enum tcp_state { * * @state: TCP connection state * - * @seq_init: Initial receive sequence number - * @ack_edge: Receive next + * @irs: Initial receive sequence number + * @rcv_nxt: Receive next * * @loc_timestamp: Local timestamp * @rmt_timestamp: Remote timestamp @@ -301,8 +301,8 @@ struct tcp_stream { /* TCP connection state */ enum tcp_state state; - u32 seq_init; - u32 ack_edge; + u32 irs; + u32 rcv_nxt; /* TCP option timestamp */ u32 loc_timestamp; diff --git a/net/tcp.c b/net/tcp.c index db708f0a2a5..7c713a5ca56 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -360,9 +360,9 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, pkt_len = pkt_hdr_len + payload_len; tcp_len = pkt_len - IP_HDR_SIZE; - tcp->ack_edge = tcp_ack_num; + tcp->rcv_nxt = tcp_ack_num; /* TCP Header */ - b->ip.hdr.tcp_ack = htonl(tcp->ack_edge); + b->ip.hdr.tcp_ack = htonl(tcp->rcv_nxt); b->ip.hdr.tcp_src = htons(tcp->lport); b->ip.hdr.tcp_dst = htons(tcp->rport); b->ip.hdr.tcp_seq = htonl(tcp_seq_num); @@ -396,10 +396,10 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, return pkt_hdr_len; } -static void tcp_update_ack_edge(struct tcp_stream *tcp) +static void tcp_update_rcv_nxt(struct tcp_stream *tcp) { - if (tcp_seq_cmp(tcp->ack_edge, tcp->lost.hill[0].l) >= 0) { - tcp->ack_edge = tcp->lost.hill[0].r; + if (tcp_seq_cmp(tcp->rcv_nxt, tcp->lost.hill[0].l) >= 0) { + tcp->rcv_nxt = tcp->lost.hill[0].r; memmove(&tcp->lost.hill[0], &tcp->lost.hill[1], (TCP_SACK_HILLS - 1) * sizeof(struct sack_edges)); @@ -434,7 +434,7 @@ void tcp_hole(struct tcp_stream *tcp, u32 tcp_seq_num, u32 len) tcp_seq_num = tcp->lost.hill[i].l; } if (tcp_seq_cmp(tcp->lost.hill[i].r, tcp_seq_num + len) >= 0) { - tcp_update_ack_edge(tcp); + tcp_update_rcv_nxt(tcp); return; } @@ -463,12 +463,12 @@ void tcp_hole(struct tcp_stream *tcp, u32 tcp_seq_num, u32 len) } } - tcp_update_ack_edge(tcp); + tcp_update_rcv_nxt(tcp); return; } if (i == TCP_SACK_HILLS) { - tcp_update_ack_edge(tcp); + tcp_update_rcv_nxt(tcp); return; } @@ -489,7 +489,7 @@ void tcp_hole(struct tcp_stream *tcp, u32 tcp_seq_num, u32 len) tcp->lost.hill[i].r = tcp_seq_num + len; tcp->lost.len = TCP_OPT_LEN_2 + cnt * TCP_OPT_LEN_8; - tcp_update_ack_edge(tcp); + tcp_update_rcv_nxt(tcp); }; /** @@ -566,8 +566,8 @@ static u8 tcp_state_machine(struct tcp_stream *tcp, u8 tcp_flags, debug_cond(DEBUG_INT_STATE, "TCP CLOSED %x\n", tcp_flags); if (tcp_syn) { action = TCP_SYN | TCP_ACK; - tcp->seq_init = tcp_seq_num; - tcp->ack_edge = tcp_seq_num + 1; + tcp->irs = tcp_seq_num; + tcp->rcv_nxt = tcp_seq_num + 1; tcp->lost.len = TCP_OPT_LEN_2; tcp->state = TCP_SYN_RECEIVED; } else if (tcp_ack || tcp_fin) { @@ -583,8 +583,8 @@ static u8 tcp_state_machine(struct tcp_stream *tcp, u8 tcp_flags, tcp->state = TCP_CLOSE_WAIT; } else if (tcp_ack || (tcp_syn && tcp_ack)) { action |= TCP_ACK; - tcp->seq_init = tcp_seq_num; - tcp->ack_edge = tcp_seq_num + 1; + tcp->irs = tcp_seq_num; + tcp->rcv_nxt = tcp_seq_num + 1; tcp->state = TCP_ESTABLISHED; if (tcp_syn && tcp_ack) @@ -633,7 +633,7 @@ static u8 tcp_state_machine(struct tcp_stream *tcp, u8 tcp_flags, case TCP_FIN_WAIT_1: debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_1 (%x)\n", tcp_flags); if (tcp_fin) { - tcp->ack_edge++; + tcp->rcv_nxt++; action = TCP_ACK | TCP_FIN; tcp->state = TCP_FIN_WAIT_2; } @@ -748,7 +748,7 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) } else if (tcp_action != TCP_DATA) { debug_cond(DEBUG_DEV_PKT, "TCP Action (action=%x,Seq=%u,Ack=%u,Pay=%d)\n", - tcp_action, tcp_ack_num, tcp->ack_edge, payload_len); + tcp_action, tcp_ack_num, tcp->rcv_nxt, payload_len); /* * Warning: Incoming Ack & Seq sequence numbers are transposed @@ -756,7 +756,7 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) */ net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, (tcp_action & (~TCP_PUSH)), - tcp_ack_num, tcp->ack_edge); + tcp_ack_num, tcp->rcv_nxt); } } -- cgit v1.3.1 From bf962de97c375886fee0532f9d282a895d257ebb Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Sat, 28 Dec 2024 13:46:32 +0300 Subject: net/tcp: improve tcp framework, use better state machine Changes: * Fix initial send sequence always zero issue * Use state machine close to RFC 9293. This should make TCP transfers more reliable (now we can upload a huge array of data from the board to external server) * Improve TCP framework a lot. This should make tcp client code much more simple. * rewrite wget with new tcp stack * rewrite fastboot_tcp with new tcp stack It's quite hard to fix the initial send sequence (ISS) issue with the separate patch. A naive attempt to fix an issue inside the tcp_set_tcp_header() function will break tcp packet retransmit logic in wget and other clients. Example: Wget stores tcp_seq_num value before tcp_set_tcp_header() will be called and (on failure) retransmit the packet with the stored tcp_seq_num value. Thus: * the same ISS must allways be used (current case) * or tcp clients needs to generate a proper ISS when required. A proper ISS fix will require a big redesing comparable with a this one. Signed-off-by: Mikhail Kshevetskiy Reviewed-by: Simon Glass --- include/net/tcp.h | 201 ++++++++++-- include/net/wget.h | 8 - net/fastboot_tcp.c | 193 +++++------- net/net.c | 4 + net/tcp.c | 891 +++++++++++++++++++++++++++++++++++++++++------------ net/wget.c | 537 +++++++++++--------------------- 6 files changed, 1132 insertions(+), 702 deletions(-) (limited to 'include') diff --git a/include/net/tcp.h b/include/net/tcp.h index 0694af9d5b1..5022fa9dc1b 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -265,6 +265,7 @@ union tcp_build_pkt { * @TCP_CLOSING: Rec FIN, sent FIN, ACK waiting for ACK * @TCP_FIN_WAIT_1: Sent FIN waiting for response * @TCP_FIN_WAIT_2: Rec ACK from FIN sent, waiting for FIN + * @TCP_LAST_ACK: Waiting for ACK of the connection termination */ enum tcp_state { TCP_CLOSED, @@ -274,7 +275,22 @@ enum tcp_state { TCP_CLOSE_WAIT, TCP_CLOSING, TCP_FIN_WAIT_1, - TCP_FIN_WAIT_2 + TCP_FIN_WAIT_2, + TCP_LAST_ACK, +}; + +/** + * enum tcp_status - TCP stream status for connection + * @TCP_ERR_OK: no rx/tx errors + * @TCP_ERR_TOUT: rx/tx timeout happened + * @TCP_ERR_RST: connection was reset + * @TCP_ERR_IO: input/output error + */ +enum tcp_status { + TCP_ERR_OK = 0, + TCP_ERR_TOUT, + TCP_ERR_RST, + TCP_ERR_IO }; /** @@ -283,51 +299,156 @@ enum tcp_state { * @rport: Remote port, host byte order * @lport: Local port, host byte order * + * @priv: User private data (not used by tcp module) + * + * @max_retry_count: Maximum retransmit attempts (default 3) + * @initial_timeout: Timeout from initial TX to reTX (default 2 sec) + * @rx_inactiv_timeout: Maximum time from last rx till connection drop + * (default 30 sec) + * + * @on_closed: User callback, called just before destroying TCP stream + * @on_established: User callback, called when TCP stream enters + * TCP_ESTABLISHED state + * @on_rcv_nxt_update: User callback, called when all data in the segment + * [0..rx_bytes - 1] was received + * @on_snd_una_update: User callback, called when all data in the segment + * [0..tx_bytes - 1] were transferred and acknowledged + * @rx: User callback, called on receive of segment + * [rx_offs..rx_offs+len-1]. If NULL -- all incoming data + * will be ignored. User SHOULD store the segment and + * return the number of accepted bytes or negative value + * on error. + * WARNING: Previous segmengs may not be received yet + * @tx: User callback, called on transmit/retransmit of segment + * [tx_offs..tx_offs+maxlen-1]. If NULL -- no data will + * be transmitted. User SHOULD fill provided buffer and + * return the number of bytes in the buffer or negative + * value on error. + * WARNING: do not use tcp_stream_close() from this + * callback (it will break stream). Better use + * on_snd_una_update() callback for such purposes. + * + * @time_last_rx: Arrival time of last valid incoming package (ticks) + * @time_start: Timeout start time (ticks) + * @time_delta: Timeout duration (ticks) + * @time_handler Timeout handler for a stream + * * @state: TCP connection state + * @status: TCP stream status (OK or ERR) + * @rx_packets: total number of received packets + * @tx_packets: total number of transmitted packets + * + * @fin_rx: Non-zero if TCP_FIN was received + * @fin_rx_seq: TCP sequence of rx FIN bit + * @fin_tx: Non-zero if TCP_FIN was sent (or planned to send) + * @fin_tx_seq: TCP sequence of tx FIN bit + * + * @iss: Initial send sequence number + * @snd_una: Send unacknowledged + * @snd_nxt: Send next + * @snd_wnd: Send window (in bytes) + * @snd_wl1: Segment sequence number used for last window update + * @snd_wl2: Segment acknowledgment number used for last window update * * @irs: Initial receive sequence number * @rcv_nxt: Receive next + * @rcv_wnd: Receive window (in bytes) * * @loc_timestamp: Local timestamp * @rmt_timestamp: Remote timestamp * + * @rmt_win_scale: Remote window scale factor + * * @lost: Used for SACK + * + * @retry_cnt: Number of retry attempts remaining. Only SYN, FIN + * or DATA segments are tried to retransmit. + * @retry_timeout: Current retry timeout (ms) + * @retry_action: TCP flags used for sending + * @retry_seq_num: TCP sequence for retransmit + * retry_tx_len: Number of data to transmit + * @retry_tx_offs: Position in the TX stream */ struct tcp_stream { struct in_addr rhost; u16 rport; u16 lport; - /* TCP connection state */ + void *priv; + + int max_retry_count; + int initial_timeout; + int rx_inactiv_timeout; + + void (*on_closed)(struct tcp_stream *tcp); + void (*on_established)(struct tcp_stream *tcp); + void (*on_rcv_nxt_update)(struct tcp_stream *tcp, u32 rx_bytes); + void (*on_snd_una_update)(struct tcp_stream *tcp, u32 tx_bytes); + int (*rx)(struct tcp_stream *tcp, u32 rx_offs, void *buf, int len); + int (*tx)(struct tcp_stream *tcp, u32 tx_offs, void *buf, int maxlen); + + ulong time_last_rx; + ulong time_start; + ulong time_delta; + void (*time_handler)(struct tcp_stream *tcp); + enum tcp_state state; + enum tcp_status status; + u32 rx_packets; + u32 tx_packets; + + int fin_rx; + u32 fin_rx_seq; + + int fin_tx; + u32 fin_tx_seq; + + u32 iss; + u32 snd_una; + u32 snd_nxt; + u32 snd_wnd; + u32 snd_wl1; + u32 snd_wl2; u32 irs; u32 rcv_nxt; + u32 rcv_wnd; /* TCP option timestamp */ u32 loc_timestamp; u32 rmt_timestamp; + /* TCP window scale */ + u8 rmt_win_scale; + /* TCP sliding window control used to request re-TX */ struct tcp_sack_v lost; + + /* used for data retransmission */ + int retry_cnt; + int retry_timeout; + u8 retry_action; + u32 retry_seq_num; + u32 retry_tx_len; + u32 retry_tx_offs; }; void tcp_init(void); -typedef int tcp_incoming_filter(struct in_addr rhost, - u16 rport, u16 sport); - /* - * This function sets user callback used to accept/drop incoming - * connections. Callback should: + * This function sets user callback called on TCP stream creation. + * Callback should: * + Check TCP stream endpoint and make connection verdict * - return non-zero value to accept connection * - return zero to drop connection + * + Setup TCP stream callbacks like: on_closed(), on_established(), + * n_rcv_nxt_update(), on_snd_una_update(), rx() and tx(). + * + Setup other stream related data * - * WARNING: If callback is NOT defined, all incoming connections - * will be dropped. + * WARNING: User MUST setup TCP stream on_create handler. Without it + * no connection (including outgoung) will be created. */ -void tcp_set_incoming_filter(tcp_incoming_filter *filter); +void tcp_stream_set_on_create_handler(int (*on_create)(struct tcp_stream *)); /* * tcp_stream_get -- Get or create TCP stream @@ -351,27 +472,51 @@ struct tcp_stream *tcp_stream_get(int is_new, struct in_addr rhost, */ struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport); -enum tcp_state tcp_stream_get_state(struct tcp_stream *tcp); +/* + * tcp_stream_put -- Return stream to a TCP subsystem. Subsystem will + * check stream and destroy it (if stream was already + * closed). Otherwize no stream change will happen. + * @tcp: TCP stream to put + */ +void tcp_stream_put(struct tcp_stream *tcp); -int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, - u8 action, u32 tcp_seq_num, u32 tcp_ack_num); +/* + * tcp_stream_restart_rx_timer -- Restart RX inactivity timer. Usually there + * is no needs to call this function. Timer + * will be restarted on receiving of any valid + * tcp packet belonging to a stream. + * + * This function may be used to prevent connection + * break in the following case: + * - u-boot is busy with very long data processing + * - remote side waits for u-boot reply + * + * @tcp: TCP stream to put + */ +void tcp_stream_restart_rx_timer(struct tcp_stream *tcp); -/** - * rxhand_tcp() - An incoming packet handler. - * @tcp: TCP stream - * @pkt: pointer to the application packet - * @dport: destination TCP port - * @sip: source IP address - * @sport: source TCP port - * @tcp_seq_num: TCP sequential number - * @tcp_ack_num: TCP acknowledgment number - * @action: TCP action (SYN, ACK, FIN, etc) - * @len: packet length +enum tcp_state tcp_stream_get_state(struct tcp_stream *tcp); +enum tcp_status tcp_stream_get_status(struct tcp_stream *tcp); + +/* + * tcp_stream_rx_offs(), + * tcp_stream_tx_offs() -- Returns offset of first unacknowledged byte + * in receive/transmit stream correspondingly. + * The result is NOT affected by sin/fin flags. + * @tcp: TCP stream */ -typedef void rxhand_tcp(struct tcp_stream *tcp, uchar *pkt, - u32 tcp_seq_num, u32 tcp_ack_num, - u8 action, unsigned int len); -void tcp_set_tcp_handler(rxhand_tcp *f); +u32 tcp_stream_rx_offs(struct tcp_stream *tcp); +u32 tcp_stream_tx_offs(struct tcp_stream *tcp); + +/* reset tcp stream */ +void tcp_stream_reset(struct tcp_stream *tcp); +/* force TCP stream closing, do NOT use from tcp->tx callback */ +void tcp_stream_close(struct tcp_stream *tcp); + +void tcp_streams_poll(void); + +int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, + u8 action, u32 tcp_seq_num, u32 tcp_ack_num); void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int len); diff --git a/include/net/wget.h b/include/net/wget.h index 6714f7ea573..9a423b30414 100644 --- a/include/net/wget.h +++ b/include/net/wget.h @@ -8,14 +8,6 @@ */ void wget_start(void); -enum wget_state { - WGET_CLOSED, - WGET_CONNECTING, - WGET_CONNECTED, - WGET_TRANSFERRING, - WGET_TRANSFERRED -}; - #define DEBUG_WGET 0 /* Set to 1 for debug messages */ #define WGET_RETRY_COUNT 30 #define WGET_TIMEOUT 2000UL diff --git a/net/fastboot_tcp.c b/net/fastboot_tcp.c index 4d34fdc5a45..3ea25c997fc 100644 --- a/net/fastboot_tcp.c +++ b/net/fastboot_tcp.c @@ -10,140 +10,109 @@ #define FASTBOOT_TCP_PORT 5554 -static char command[FASTBOOT_COMMAND_LEN]; -static char response[FASTBOOT_RESPONSE_LEN]; - static const unsigned short handshake_length = 4; static const uchar *handshake = "FB01"; -static u32 curr_tcp_seq_num; -static u32 curr_tcp_ack_num; -static unsigned int curr_request_len; -static enum fastboot_tcp_state { - FASTBOOT_CLOSED, - FASTBOOT_CONNECTED, - FASTBOOT_DISCONNECTING -} state = FASTBOOT_CLOSED; - -static void fastboot_tcp_answer(struct tcp_stream *tcp, u8 action, - unsigned int len) -{ - const u32 response_seq_num = curr_tcp_ack_num; - const u32 response_ack_num = curr_tcp_seq_num + - (curr_request_len > 0 ? curr_request_len : 1); +static char rxbuf[sizeof(u64) + FASTBOOT_COMMAND_LEN + 1]; +static char txbuf[sizeof(u64) + FASTBOOT_RESPONSE_LEN + 1]; - net_send_tcp_packet(len, tcp->rhost, tcp->rport, tcp->lport, - action, response_seq_num, response_ack_num); -} +static u32 data_read; +static u32 tx_last_offs, tx_last_len; -static void fastboot_tcp_reset(struct tcp_stream *tcp) +static void tcp_stream_on_rcv_nxt_update(struct tcp_stream *tcp, u32 rx_bytes) { - fastboot_tcp_answer(tcp, TCP_RST, 0); - state = FASTBOOT_CLOSED; -} + u64 cmd_size; + __be64 len_be; + char saved; + int fastboot_command_id, len; + + if (!data_read && rx_bytes >= handshake_length) { + if (memcmp(rxbuf, handshake, handshake_length)) { + printf("fastboot: bad handshake\n"); + tcp_stream_close(tcp); + return; + } -static void fastboot_tcp_send_packet(struct tcp_stream *tcp, u8 action, - const uchar *data, unsigned int len) -{ - uchar *pkt = net_get_async_tx_pkt_buf(); + tx_last_offs = 0; + tx_last_len = handshake_length; + memcpy(txbuf, handshake, handshake_length); + + data_read += handshake_length; + rx_bytes -= handshake_length; + if (rx_bytes > 0) + memmove(rxbuf, rxbuf + handshake_length, rx_bytes); + return; + } - memset(pkt, '\0', PKTSIZE); - pkt += net_eth_hdr_size() + IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; - memcpy(pkt, data, len); - fastboot_tcp_answer(tcp, action, len); - memset(pkt, '\0', PKTSIZE); + if (rx_bytes < sizeof(u64)) + return; + + memcpy(&cmd_size, rxbuf, sizeof(u64)); + cmd_size = __be64_to_cpu(cmd_size); + if (rx_bytes < sizeof(u64) + cmd_size) + return; + + saved = rxbuf[sizeof(u64) + cmd_size]; + rxbuf[sizeof(u64) + cmd_size] = '\0'; + fastboot_command_id = fastboot_handle_command(rxbuf + sizeof(u64), + txbuf + sizeof(u64)); + fastboot_handle_boot(fastboot_command_id, + strncmp("OKAY", txbuf + sizeof(u64), 4) != 0); + rxbuf[sizeof(u64) + cmd_size] = saved; + + len = strlen(txbuf + sizeof(u64)); + len_be = __cpu_to_be64(len); + memcpy(txbuf, &len_be, sizeof(u64)); + + tx_last_offs += tx_last_len; + tx_last_len = len + sizeof(u64); + + data_read += sizeof(u64) + cmd_size; + rx_bytes -= sizeof(u64) + cmd_size; + if (rx_bytes > 0) + memmove(rxbuf, rxbuf + sizeof(u64) + cmd_size, rx_bytes); } -static void fastboot_tcp_send_message(struct tcp_stream *tcp, - const char *message, unsigned int len) +static int tcp_stream_rx(struct tcp_stream *tcp, u32 rx_offs, void *buf, int len) { - __be64 len_be = __cpu_to_be64(len); - uchar *pkt = net_get_async_tx_pkt_buf(); - - memset(pkt, '\0', PKTSIZE); - pkt += net_eth_hdr_size() + IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; - // Put first 8 bytes as a big endian message length - memcpy(pkt, &len_be, 8); - pkt += 8; - memcpy(pkt, message, len); - fastboot_tcp_answer(tcp, TCP_ACK | TCP_PUSH, len + 8); - memset(pkt, '\0', PKTSIZE); + memcpy(rxbuf + rx_offs - data_read, buf, len); + + return len; } -static void fastboot_tcp_handler_ipv4(struct tcp_stream *tcp, uchar *pkt, - u32 tcp_seq_num, u32 tcp_ack_num, - u8 action, unsigned int len) +static int tcp_stream_tx(struct tcp_stream *tcp, u32 tx_offs, void *buf, int maxlen) { - int fastboot_command_id; - u64 command_size; - u8 tcp_fin = action & TCP_FIN; - u8 tcp_push = action & TCP_PUSH; - - curr_tcp_seq_num = tcp_seq_num; - curr_tcp_ack_num = tcp_ack_num; - curr_request_len = len; - - switch (state) { - case FASTBOOT_CLOSED: - if (tcp_push) { - if (len != handshake_length || - strlen(pkt) != handshake_length || - memcmp(pkt, handshake, handshake_length) != 0) { - fastboot_tcp_reset(tcp); - break; - } - fastboot_tcp_send_packet(tcp, TCP_ACK | TCP_PUSH, - handshake, handshake_length); - state = FASTBOOT_CONNECTED; - } - break; - case FASTBOOT_CONNECTED: - if (tcp_fin) { - fastboot_tcp_answer(tcp, TCP_FIN | TCP_ACK, 0); - state = FASTBOOT_DISCONNECTING; - break; - } - if (tcp_push) { - // First 8 bytes is big endian message length - command_size = __be64_to_cpu(*(u64 *)pkt); - len -= 8; - pkt += 8; - - // Only single packet messages are supported ATM - if (strlen(pkt) != command_size) { - fastboot_tcp_reset(tcp); - break; - } - strlcpy(command, pkt, len + 1); - fastboot_command_id = fastboot_handle_command(command, response); - fastboot_tcp_send_message(tcp, response, strlen(response)); - fastboot_handle_boot(fastboot_command_id, - strncmp("OKAY", response, 4) == 0); - } - break; - case FASTBOOT_DISCONNECTING: - if (tcp_push) - state = FASTBOOT_CLOSED; - break; - } + /* by design: tx_offs >= tx_last_offs */ + if (tx_offs >= tx_last_offs + tx_last_len) + return 0; - memset(command, 0, FASTBOOT_COMMAND_LEN); - memset(response, 0, FASTBOOT_RESPONSE_LEN); - curr_tcp_seq_num = 0; - curr_tcp_ack_num = 0; - curr_request_len = 0; + maxlen = tx_last_offs + tx_last_len - tx_offs; + memcpy(buf, txbuf + (tx_offs - tx_last_offs), maxlen); + + return maxlen; } -static int incoming_filter(struct in_addr rhost, u16 rport, u16 lport) +static int tcp_stream_on_create(struct tcp_stream *tcp) { - return (lport == FASTBOOT_TCP_PORT); + if (tcp->lport != FASTBOOT_TCP_PORT) + return 0; + + data_read = 0; + tx_last_offs = 0; + tx_last_len = 0; + + tcp->on_rcv_nxt_update = tcp_stream_on_rcv_nxt_update; + tcp->rx = tcp_stream_rx; + tcp->tx = tcp_stream_tx; + + return 1; } void fastboot_tcp_start_server(void) { + memset(net_server_ethaddr, 0, 6); + tcp_stream_set_on_create_handler(tcp_stream_on_create); + printf("Using %s device\n", eth_get_name()); printf("Listening for fastboot command on tcp %pI4\n", &net_ip); - - tcp_set_incoming_filter(incoming_filter); - tcp_set_tcp_handler(fastboot_tcp_handler_ipv4); } diff --git a/net/net.c b/net/net.c index 62d1c5b1e82..fd634405e8a 100644 --- a/net/net.c +++ b/net/net.c @@ -652,6 +652,9 @@ restart: * errors that may have happened. */ eth_rx(); +#if defined(CONFIG_PROT_TCP) + tcp_streams_poll(); +#endif /* * Abort if ctrl-c was pressed. @@ -961,6 +964,7 @@ int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, + tcp_set_tcp_header(tcp, pkt + eth_hdr_size, payload_len, action, tcp_seq_num, tcp_ack_num); + tcp_stream_put(tcp); break; #endif default: diff --git a/net/tcp.c b/net/tcp.c index 7c713a5ca56..a2941951834 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -24,9 +24,26 @@ #include #include -static int tcp_activity_count; +/* + * The start sequence number increment for the two sequently created + * connections within the same timer tick. This number must be: + * - prime (to increase the time before the same number will be generated) + * - larger than typical MTU (to avoid similar numbers for two sequently + * created connections) + */ +#define TCP_START_SEQ_INC 2153 /* just large prime number */ + +#define TCP_SEND_RETRY 3 +#define TCP_SEND_TIMEOUT 2000UL +#define TCP_RX_INACTIVE_TIMEOUT 30000UL +#define TCP_RCV_WND_SIZE (PKTBUFSRX * TCP_MSS) + +#define TCP_PACKET_OK 0 +#define TCP_PACKET_DROP 1 + static struct tcp_stream tcp_stream; -static tcp_incoming_filter *incoming_filter; + +static int (*tcp_stream_on_create)(struct tcp_stream *tcp); /* * TCP lengths are stored as a rounded up number of 32 bit words. @@ -35,12 +52,10 @@ static tcp_incoming_filter *incoming_filter; */ #define LEN_B_TO_DW(x) ((x) >> 2) #define ROUND_TCPHDR_LEN(x) (LEN_B_TO_DW((x) + 3)) +#define ROUND_TCPHDR_BYTES(x) (((x) + 3) & ~3) #define SHIFT_TO_TCPHDRLEN_FIELD(x) ((x) << 4) #define GET_TCP_HDR_LEN_IN_BYTES(x) ((x) >> 2) -/* Current TCP RX packet handler */ -static rxhand_tcp *tcp_packet_handler; - #define RANDOM_PORT_START 1024 #define RANDOM_PORT_RANGE 0x4000 @@ -62,6 +77,22 @@ static inline s32 tcp_seq_cmp(u32 a, u32 b) return (s32)(a - b); } +static inline u32 tcp_get_start_seq(void) +{ + static u32 tcp_seq_inc; + u32 tcp_seq; + + tcp_seq = (get_timer(0) & 0xffffffff) + tcp_seq_inc; + tcp_seq_inc += TCP_START_SEQ_INC; + + return tcp_seq; +} + +static inline ulong msec_to_ticks(ulong msec) +{ + return msec * CONFIG_SYS_HZ / 1000; +} + /** * tcp_stream_get_state() - get TCP stream state * @tcp: tcp stream @@ -84,31 +115,90 @@ static void tcp_stream_set_state(struct tcp_stream *tcp, tcp->state = new_state; } -void tcp_init(void) +/** + * tcp_stream_get_status() - get TCP stream status + * @tcp: tcp stream + * + * Return: TCP stream status + */ +enum tcp_status tcp_stream_get_status(struct tcp_stream *tcp) { - incoming_filter = NULL; - tcp_stream.state = TCP_CLOSED; + return tcp->status; } -void tcp_set_incoming_filter(tcp_incoming_filter *filter) +/** + * tcp_stream_set_status() - set TCP stream state + * @tcp: tcp stream + * @new_satus: new TCP stream status + */ +static void tcp_stream_set_status(struct tcp_stream *tcp, + enum tcp_status new_status) { - incoming_filter = filter; + tcp->status = new_status; } -static struct tcp_stream *tcp_stream_add(struct in_addr rhost, - u16 rport, u16 lport) +void tcp_stream_restart_rx_timer(struct tcp_stream *tcp) { - struct tcp_stream *tcp = &tcp_stream; - - if (tcp->state != TCP_CLOSED) - return NULL; + tcp->time_last_rx = get_timer(0); +} +static void tcp_stream_init(struct tcp_stream *tcp, + struct in_addr rhost, u16 rport, u16 lport) +{ memset(tcp, 0, sizeof(struct tcp_stream)); tcp->rhost.s_addr = rhost.s_addr; tcp->rport = rport; tcp->lport = lport; tcp->state = TCP_CLOSED; tcp->lost.len = TCP_OPT_LEN_2; + tcp->rcv_wnd = TCP_RCV_WND_SIZE; + tcp->max_retry_count = TCP_SEND_RETRY; + tcp->initial_timeout = TCP_SEND_TIMEOUT; + tcp->rx_inactiv_timeout = TCP_RX_INACTIVE_TIMEOUT; + tcp_stream_restart_rx_timer(tcp); +} + +static void tcp_stream_destroy(struct tcp_stream *tcp) +{ + if (tcp->on_closed) + tcp->on_closed(tcp); + memset(tcp, 0, sizeof(struct tcp_stream)); +} + +void tcp_init(void) +{ + static int initialized; + struct tcp_stream *tcp = &tcp_stream; + + tcp_stream_on_create = NULL; + if (!initialized) { + initialized = 1; + memset(tcp, 0, sizeof(struct tcp_stream)); + } + + tcp_stream_set_state(tcp, TCP_CLOSED); + tcp_stream_set_status(tcp, TCP_ERR_RST); + tcp_stream_destroy(tcp); +} + +void tcp_stream_set_on_create_handler(int (*on_create)(struct tcp_stream *)) +{ + tcp_stream_on_create = on_create; +} + +static struct tcp_stream *tcp_stream_add(struct in_addr rhost, + u16 rport, u16 lport) +{ + struct tcp_stream *tcp = &tcp_stream; + + if (!tcp_stream_on_create || + tcp->state != TCP_CLOSED) + return NULL; + + tcp_stream_init(tcp, rhost, rport, lport); + if (!tcp_stream_on_create(tcp)) + return NULL; + return tcp; } @@ -122,30 +212,226 @@ struct tcp_stream *tcp_stream_get(int is_new, struct in_addr rhost, tcp->lport == lport) return tcp; - if (!is_new || !incoming_filter || - !incoming_filter(rhost, rport, lport)) - return NULL; + return is_new ? tcp_stream_add(rhost, rport, lport) : NULL; +} - return tcp_stream_add(rhost, rport, lport); +void tcp_stream_put(struct tcp_stream *tcp) +{ + if (tcp->state == TCP_CLOSED) + tcp_stream_destroy(tcp); } -static void dummy_handler(struct tcp_stream *tcp, uchar *pkt, - u32 tcp_seq_num, u32 tcp_ack_num, - u8 action, unsigned int len) +u32 tcp_stream_rx_offs(struct tcp_stream *tcp) { + u32 ret; + + switch (tcp->state) { + case TCP_CLOSED: + case TCP_SYN_SENT: + case TCP_SYN_RECEIVED: + return 0; + default: + break; + } + + ret = tcp->rcv_nxt - tcp->irs - 1; + if (tcp->fin_rx && tcp->rcv_nxt == tcp->fin_rx_seq) + ret--; + + return ret; } -/** - * tcp_set_tcp_handler() - set a handler to receive data - * @f: handler - */ -void tcp_set_tcp_handler(rxhand_tcp *f) +u32 tcp_stream_tx_offs(struct tcp_stream *tcp) +{ + u32 ret; + + switch (tcp->state) { + case TCP_CLOSED: + case TCP_SYN_SENT: + case TCP_SYN_RECEIVED: + return 0; + default: + break; + } + + ret = tcp->snd_una - tcp->iss - 1; + if (tcp->fin_tx && tcp->snd_una == tcp->fin_tx_seq + 1) + ret--; + + return ret; +} + +static void tcp_stream_set_time_handler(struct tcp_stream *tcp, ulong msec, + void (*handler)(struct tcp_stream *)) +{ + if (!msec) { + tcp->time_handler = NULL; + return; + } + + tcp->time_handler = handler; + tcp->time_start = get_timer(0); + tcp->time_delta = msec_to_ticks(msec); +} + +static void tcp_send_packet(struct tcp_stream *tcp, u8 action, + u32 tcp_seq_num, u32 tcp_ack_num, u32 tx_len) +{ + tcp->tx_packets++; + net_send_tcp_packet(tx_len, tcp->rhost, tcp->rport, + tcp->lport, action, tcp_seq_num, + tcp_ack_num); +} + +static void tcp_send_repeat(struct tcp_stream *tcp) +{ + uchar *ptr; + u32 tcp_opts_size; + int ret; + + if (!tcp->retry_cnt) { + puts("\nTCP: send retry counter exceeded\n"); + tcp_send_packet(tcp, TCP_RST, tcp->retry_seq_num, + tcp->rcv_nxt, 0); + tcp_stream_set_status(tcp, TCP_ERR_TOUT); + tcp_stream_set_state(tcp, TCP_CLOSED); + tcp_stream_destroy(tcp); + return; + } + tcp->retry_cnt--; + tcp->retry_timeout += tcp->initial_timeout; + + if (tcp->retry_tx_len > 0) { + tcp_opts_size = ROUND_TCPHDR_BYTES(TCP_TSOPT_SIZE + + tcp->lost.len); + ptr = net_tx_packet + net_eth_hdr_size() + + IP_TCP_HDR_SIZE + tcp_opts_size; + + if (tcp->retry_tx_len > TCP_MSS - tcp_opts_size) + tcp->retry_tx_len = TCP_MSS - tcp_opts_size; + + /* refill packet data */ + ret = tcp->tx(tcp, tcp->retry_tx_offs, ptr, tcp->retry_tx_len); + if (ret < 0) { + puts("\nTCP: send failure\n"); + tcp_send_packet(tcp, TCP_RST, tcp->retry_seq_num, + tcp->rcv_nxt, 0); + tcp_stream_set_status(tcp, TCP_ERR_IO); + tcp_stream_set_state(tcp, TCP_CLOSED); + tcp_stream_destroy(tcp); + return; + } + } + tcp_send_packet(tcp, tcp->retry_action, tcp->retry_seq_num, + tcp->rcv_nxt, tcp->retry_tx_len); + + tcp_stream_set_time_handler(tcp, tcp->retry_timeout, tcp_send_repeat); +} + +static void tcp_send_packet_with_retry(struct tcp_stream *tcp, u8 action, + u32 tcp_seq_num, u32 tx_len, u32 tx_offs) +{ + tcp->retry_cnt = tcp->max_retry_count; + tcp->retry_timeout = tcp->initial_timeout; + tcp->retry_action = action; + tcp->retry_seq_num = tcp_seq_num; + tcp->retry_tx_len = tx_len; + tcp->retry_tx_offs = tx_offs; + + tcp_send_packet(tcp, action, tcp_seq_num, tcp->rcv_nxt, tx_len); + tcp_stream_set_time_handler(tcp, tcp->retry_timeout, tcp_send_repeat); +} + +static inline u8 tcp_stream_fin_needed(struct tcp_stream *tcp, u32 tcp_seq_num) +{ + return (tcp->fin_tx && (tcp_seq_num == tcp->fin_tx_seq)) ? TCP_FIN : 0; +} + +static void tcp_steam_tx_try(struct tcp_stream *tcp) { - debug_cond(DEBUG_INT_STATE, "--- net_loop TCP handler set (%p)\n", f); - if (!f) - tcp_packet_handler = dummy_handler; - else - tcp_packet_handler = f; + uchar *ptr; + int tx_len; + u32 tx_offs, tcp_opts_size; + + if (tcp->state != TCP_ESTABLISHED || + tcp->time_handler || + !tcp->tx) + return; + + tcp_opts_size = ROUND_TCPHDR_BYTES(TCP_TSOPT_SIZE + tcp->lost.len); + tx_len = TCP_MSS - tcp_opts_size; + if (tcp->fin_tx) { + /* do not try to send beyonds FIN packet limits */ + if (tcp_seq_cmp(tcp->snd_una, tcp->fin_tx_seq) >= 0) + return; + + tx_len = tcp->fin_tx_seq - tcp->snd_una; + if (tx_len > TCP_MSS - tcp_opts_size) + tx_len = TCP_MSS - tcp_opts_size; + } + + tx_offs = tcp_stream_tx_offs(tcp); + ptr = net_tx_packet + net_eth_hdr_size() + + IP_TCP_HDR_SIZE + tcp_opts_size; + + /* fill packet data and adjust size */ + tx_len = tcp->tx(tcp, tx_offs, ptr, tx_len); + if (tx_len < 0) { + puts("\nTCP: send failure\n"); + tcp_send_packet(tcp, TCP_RST, tcp->retry_seq_num, + tcp->rcv_nxt, 0); + tcp_stream_set_status(tcp, TCP_ERR_IO); + tcp_stream_set_state(tcp, TCP_CLOSED); + tcp_stream_destroy(tcp); + return; + } + if (!tx_len) + return; + + if (tcp_seq_cmp(tcp->snd_una + tx_len, tcp->snd_nxt) > 0) + tcp->snd_nxt = tcp->snd_una + tx_len; + + tcp_send_packet_with_retry(tcp, TCP_ACK | TCP_PUSH, + tcp->snd_una, tx_len, tx_offs); +} + +static void tcp_stream_poll(struct tcp_stream *tcp, ulong time) +{ + ulong delta; + void (*handler)(struct tcp_stream *tcp); + + if (tcp->state == TCP_CLOSED) + return; + + /* handle rx inactivity timeout */ + delta = msec_to_ticks(tcp->rx_inactiv_timeout); + if (time - tcp->time_last_rx >= delta) { + puts("\nTCP: rx inactivity timeout exceeded\n"); + tcp_stream_reset(tcp); + tcp_stream_set_status(tcp, TCP_ERR_TOUT); + tcp_stream_destroy(tcp); + return; + } + + /* handle retransmit timeout */ + if (tcp->time_handler && + time - tcp->time_start >= tcp->time_delta) { + handler = tcp->time_handler; + tcp->time_handler = NULL; + handler(tcp); + } + + tcp_steam_tx_try(tcp); +} + +void tcp_streams_poll(void) +{ + ulong time; + struct tcp_stream *tcp; + + time = get_timer(0); + tcp = &tcp_stream; + tcp_stream_poll(tcp, time); } /** @@ -240,7 +526,6 @@ int net_set_ack_options(struct tcp_stream *tcp, union tcp_build_pkt *b) * This returns the actual rounded up length of the * TCP header to add to the total packet length */ - return GET_TCP_HDR_LEN_IN_BYTES(b->sack.hdr.tcp_hlen); } @@ -300,18 +585,8 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, "TCP Hdr:SYN (%pI4, %pI4, sq=%u, ak=%u)\n", &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num); - tcp_activity_count = 0; net_set_syn_options(tcp, b); - tcp_seq_num = 0; - tcp_ack_num = 0; pkt_hdr_len = IP_TCP_O_SIZE; - if (tcp->state == TCP_SYN_SENT) { /* Too many SYNs */ - action = TCP_FIN; - tcp->state = TCP_FIN_WAIT_1; - } else { - tcp->lost.len = TCP_OPT_LEN_2; - tcp->state = TCP_SYN_SENT; - } break; case TCP_SYN | TCP_ACK: case TCP_ACK: @@ -328,21 +603,16 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num); payload_len = 0; pkt_hdr_len = IP_TCP_HDR_SIZE; - tcp->state = TCP_FIN_WAIT_1; break; case TCP_RST | TCP_ACK: case TCP_RST: debug_cond(DEBUG_DEV_PKT, "TCP Hdr:RST (%pI4, %pI4, s=%u, a=%u)\n", &tcp->rhost, &net_ip, tcp_seq_num, tcp_ack_num); - tcp->state = TCP_CLOSED; break; /* Notify connection closing */ case (TCP_FIN | TCP_ACK): case (TCP_FIN | TCP_ACK | TCP_PUSH): - if (tcp->state == TCP_CLOSE_WAIT) - tcp->state = TCP_CLOSING; - debug_cond(DEBUG_DEV_PKT, "TCP Hdr:FIN ACK PSH(%pI4, %pI4, s=%u, a=%u, A=%x)\n", &tcp->rhost, &net_ip, @@ -382,7 +652,7 @@ int tcp_set_tcp_header(struct tcp_stream *tcp, uchar *pkt, int payload_len, * it is, then the u-boot tftp or nfs kernel netboot should be * considered. */ - b->ip.hdr.tcp_win = htons(PKTBUFSRX * TCP_MSS >> TCP_SCALE); + b->ip.hdr.tcp_win = htons(tcp->rcv_wnd >> TCP_SCALE); b->ip.hdr.tcp_xsum = 0; b->ip.hdr.tcp_ugr = 0; @@ -501,6 +771,7 @@ void tcp_hole(struct tcp_stream *tcp, u32 tcp_seq_num, u32 len) void tcp_parse_options(struct tcp_stream *tcp, uchar *o, int o_len) { struct tcp_t_opt *tsopt; + struct tcp_scale *wsopt; uchar *p = o; /* @@ -515,10 +786,13 @@ void tcp_parse_options(struct tcp_stream *tcp, uchar *o, int o_len) case TCP_O_END: return; case TCP_O_MSS: - case TCP_O_SCL: case TCP_P_SACK: case TCP_V_SACK: break; + case TCP_O_SCL: + wsopt = (struct tcp_scale *)p; + tcp->rmt_win_scale = wsopt->scale; + break; case TCP_O_TS: tsopt = (struct tcp_t_opt *)p; tcp->rmt_timestamp = tsopt->t_snd; @@ -533,129 +807,344 @@ void tcp_parse_options(struct tcp_stream *tcp, uchar *o, int o_len) } } -static u8 tcp_state_machine(struct tcp_stream *tcp, u8 tcp_flags, - u32 tcp_seq_num, int payload_len) +static int tcp_seg_in_wnd(struct tcp_stream *tcp, + u32 tcp_seq_num, int payload_len) { - u8 tcp_fin = tcp_flags & TCP_FIN; - u8 tcp_syn = tcp_flags & TCP_SYN; - u8 tcp_rst = tcp_flags & TCP_RST; - u8 tcp_push = tcp_flags & TCP_PUSH; - u8 tcp_ack = tcp_flags & TCP_ACK; - u8 action = TCP_DATA; + if (!payload_len && !tcp->rcv_wnd) { + if (tcp_seq_num == tcp->rcv_nxt) + return 1; + } + if (!payload_len && tcp->rcv_wnd > 0) { + if (tcp_seq_cmp(tcp->rcv_nxt, tcp_seq_num) <= 0 && + tcp_seq_cmp(tcp_seq_num, tcp->rcv_nxt + tcp->rcv_wnd) < 0) + return 1; + } + if (payload_len > 0 && tcp->rcv_wnd > 0) { + if (tcp_seq_cmp(tcp->rcv_nxt, tcp_seq_num) <= 0 && + tcp_seq_cmp(tcp_seq_num, tcp->rcv_nxt + tcp->rcv_wnd) < 0) + return 1; + tcp_seq_num += payload_len - 1; + if (tcp_seq_cmp(tcp->rcv_nxt, tcp_seq_num) <= 0 && + tcp_seq_cmp(tcp_seq_num, tcp->rcv_nxt + tcp->rcv_wnd) < 0) + return 1; + } + + return 0; +} + +static int tcp_rx_check_ack_num(struct tcp_stream *tcp, u32 tcp_seq_num, + u32 tcp_ack_num, u32 tcp_win_size) +{ + u32 old_offs, new_offs; + u8 action; + + switch (tcp->state) { + case TCP_SYN_RECEIVED: + if (tcp_seq_cmp(tcp->snd_una, tcp_ack_num) >= 0 || + tcp_seq_cmp(tcp_ack_num, tcp->snd_nxt) > 0) { + // segment acknowledgment is not acceptable + tcp_send_packet(tcp, TCP_RST, tcp_ack_num, 0, 0); + return TCP_PACKET_DROP; + } + tcp_stream_set_state(tcp, TCP_ESTABLISHED); + tcp->snd_wnd = tcp_win_size; + tcp->snd_wl1 = tcp_seq_num; + tcp->snd_wl2 = tcp_ack_num; + + if (tcp->on_established) + tcp->on_established(tcp); + + fallthrough; + + case TCP_ESTABLISHED: + case TCP_FIN_WAIT_1: + case TCP_FIN_WAIT_2: + case TCP_CLOSE_WAIT: + case TCP_CLOSING: + if (tcp_seq_cmp(tcp_ack_num, tcp->snd_nxt) > 0) { + // ACK acks something not yet sent + action = tcp_stream_fin_needed(tcp, tcp->snd_una) | TCP_ACK; + tcp_send_packet(tcp, action, tcp->snd_una, tcp->rcv_nxt, 0); + return TCP_PACKET_DROP; + } + + if (tcp_seq_cmp(tcp->snd_una, tcp_ack_num) < 0) { + old_offs = tcp_stream_tx_offs(tcp); + tcp->snd_una = tcp_ack_num; + new_offs = tcp_stream_tx_offs(tcp); + if (tcp->time_handler && + tcp_seq_cmp(tcp->snd_una, tcp->retry_seq_num) > 0) { + tcp_stream_set_time_handler(tcp, 0, NULL); + } + if (tcp->on_snd_una_update && + old_offs != new_offs) + tcp->on_snd_una_update(tcp, new_offs); + } + + if (tcp_seq_cmp(tcp->snd_una, tcp_ack_num) <= 0) { + if (tcp_seq_cmp(tcp->snd_wl1, tcp_seq_num) < 0 || + (tcp->snd_wl1 == tcp_seq_num && + tcp_seq_cmp(tcp->snd_wl2, tcp_seq_num) <= 0)) { + tcp->snd_wnd = tcp_win_size; + tcp->snd_wl1 = tcp_seq_num; + tcp->snd_wl2 = tcp_ack_num; + } + } + + if (tcp->state == TCP_FIN_WAIT_1) { + if (tcp->snd_una == tcp->snd_nxt) + tcp_stream_set_state(tcp, TCP_FIN_WAIT_2); + } + + if (tcp->state == TCP_CLOSING) { + if (tcp->snd_una == tcp->snd_nxt) + tcp_stream_set_state(tcp, TCP_CLOSED); + } + return TCP_PACKET_OK; + + case TCP_LAST_ACK: + if (tcp_ack_num == tcp->snd_nxt) + tcp_stream_set_state(tcp, TCP_CLOSED); + return TCP_PACKET_OK; + + default: + return TCP_PACKET_DROP; + } +} + +static int tcp_rx_user_data(struct tcp_stream *tcp, u32 tcp_seq_num, + char *buf, int len) +{ + int tmp_len; + u32 buf_offs, old_offs, new_offs; + u8 action; + + if (!len) + return TCP_PACKET_OK; + + switch (tcp->state) { + case TCP_ESTABLISHED: + case TCP_FIN_WAIT_1: + case TCP_FIN_WAIT_2: + break; + default: + return TCP_PACKET_DROP; + } + + tmp_len = len; + old_offs = tcp_stream_rx_offs(tcp); + buf_offs = tcp_seq_num - tcp->irs - 1; + if (tcp->rx) { + tmp_len = tcp->rx(tcp, buf_offs, buf, len); + if (tmp_len < 0) { + puts("\nTCP: receive failure\n"); + tcp_send_packet(tcp, TCP_RST, tcp->snd_una, + tcp->rcv_nxt, 0); + tcp_stream_set_status(tcp, TCP_ERR_IO); + tcp_stream_set_state(tcp, TCP_CLOSED); + tcp_stream_destroy(tcp); + return TCP_PACKET_DROP; + } + } + if (tmp_len) + tcp_hole(tcp, tcp_seq_num, tmp_len); + + new_offs = tcp_stream_rx_offs(tcp); + if (tcp->on_rcv_nxt_update && old_offs != new_offs) + tcp->on_rcv_nxt_update(tcp, new_offs); + + action = tcp_stream_fin_needed(tcp, tcp->snd_una) | TCP_ACK; + tcp_send_packet(tcp, action, tcp->snd_una, tcp->rcv_nxt, 0); + + return TCP_PACKET_OK; +} + +void tcp_rx_state_machine(struct tcp_stream *tcp, + union tcp_build_pkt *b, unsigned int pkt_len) +{ + int tcp_len = pkt_len - IP_HDR_SIZE; + u32 tcp_seq_num, tcp_ack_num, tcp_win_size; + int tcp_hdr_len, payload_len; + u8 tcp_flags, action; + + tcp_hdr_len = GET_TCP_HDR_LEN_IN_BYTES(b->ip.hdr.tcp_hlen); + payload_len = tcp_len - tcp_hdr_len; + + if (tcp_hdr_len > TCP_HDR_SIZE) + tcp_parse_options(tcp, (uchar *)b + IP_TCP_HDR_SIZE, + tcp_hdr_len - TCP_HDR_SIZE); /* - * tcp_flags are examined to determine TX action in a given state - * tcp_push is interpreted to mean "inform the app" - * urg, ece, cer and nonce flags are not supported. - * - * exe and crw are use to signal and confirm knowledge of congestion. - * This TCP only sends a file request and acks. If it generates - * congestion, the network is broken. + * Incoming sequence and ack numbers are server's view of the numbers. + * The app must swap the numbers when responding. */ - debug_cond(DEBUG_INT_STATE, "TCP STATE ENTRY %x\n", action); - if (tcp_rst) { - action = TCP_DATA; - tcp->state = TCP_CLOSED; - net_set_state(NETLOOP_FAIL); - debug_cond(DEBUG_INT_STATE, "TCP Reset %x\n", tcp_flags); - return TCP_RST; - } + tcp_seq_num = ntohl(b->ip.hdr.tcp_seq); + tcp_ack_num = ntohl(b->ip.hdr.tcp_ack); + tcp_win_size = ntohs(b->ip.hdr.tcp_win) << tcp->rmt_win_scale; - switch (tcp->state) { + tcp_flags = b->ip.hdr.tcp_flags; + +// printf("pkt: seq=%d, ack=%d, flags=%x, len=%d\n", +// tcp_seq_num - tcp->irs, tcp_ack_num - tcp->iss, tcp_flags, pkt_len); +// printf("tcp: rcv_nxt=%d, snd_una=%d, snd_nxt=%d\n\n", +// tcp->rcv_nxt - tcp->irs, tcp->snd_una - tcp->iss, tcp->snd_nxt - tcp->iss); + + switch (tcp->state) { case TCP_CLOSED: - debug_cond(DEBUG_INT_STATE, "TCP CLOSED %x\n", tcp_flags); - if (tcp_syn) { - action = TCP_SYN | TCP_ACK; - tcp->irs = tcp_seq_num; - tcp->rcv_nxt = tcp_seq_num + 1; - tcp->lost.len = TCP_OPT_LEN_2; - tcp->state = TCP_SYN_RECEIVED; - } else if (tcp_ack || tcp_fin) { - action = TCP_DATA; + if (tcp_flags & TCP_RST) + return; + + if (tcp_flags & TCP_ACK) { + tcp_send_packet(tcp, TCP_RST, tcp_ack_num, 0, 0); + return; } - break; - case TCP_SYN_RECEIVED: + + if (!(tcp_flags & TCP_SYN)) + return; + + tcp->irs = tcp_seq_num; + tcp->rcv_nxt = tcp->irs + 1; + + tcp->iss = tcp_get_start_seq(); + tcp->snd_una = tcp->iss; + tcp->snd_nxt = tcp->iss + 1; + tcp->snd_wnd = tcp_win_size; + + tcp_stream_restart_rx_timer(tcp); + + tcp_stream_set_state(tcp, TCP_SYN_RECEIVED); + tcp_send_packet_with_retry(tcp, TCP_SYN | TCP_ACK, + tcp->iss, 0, 0); + return; + case TCP_SYN_SENT: - debug_cond(DEBUG_INT_STATE, "TCP_SYN_SENT | TCP_SYN_RECEIVED %x, %u\n", - tcp_flags, tcp_seq_num); - if (tcp_fin) { - action = action | TCP_PUSH; - tcp->state = TCP_CLOSE_WAIT; - } else if (tcp_ack || (tcp_syn && tcp_ack)) { - action |= TCP_ACK; - tcp->irs = tcp_seq_num; - tcp->rcv_nxt = tcp_seq_num + 1; - tcp->state = TCP_ESTABLISHED; - - if (tcp_syn && tcp_ack) - action |= TCP_PUSH; - } else { - action = TCP_DATA; + if (!(tcp_flags & TCP_ACK)) + return; + + if (tcp_seq_cmp(tcp_ack_num, tcp->iss) <= 0 || + tcp_seq_cmp(tcp_ack_num, tcp->snd_nxt) > 0) { + if (!(tcp_flags & TCP_RST)) + tcp_send_packet(tcp, TCP_RST, tcp_ack_num, 0, 0); + return; } - break; + + if (tcp_flags & TCP_RST) { + tcp_stream_set_status(tcp, TCP_ERR_RST); + tcp_stream_set_state(tcp, TCP_CLOSED); + return; + } + + if (!(tcp_flags & TCP_SYN)) + return; + + /* stop retransmit of SYN */ + tcp_stream_set_time_handler(tcp, 0, NULL); + + tcp->irs = tcp_seq_num; + tcp->rcv_nxt = tcp->irs + 1; + tcp->snd_una = tcp_ack_num; + + tcp_stream_restart_rx_timer(tcp); + + /* our SYN has been ACKed */ + tcp_stream_set_state(tcp, TCP_ESTABLISHED); + + if (tcp->on_established) + tcp->on_established(tcp); + + action = tcp_stream_fin_needed(tcp, tcp->snd_una) | TCP_ACK; + tcp_send_packet(tcp, action, tcp->snd_una, tcp->rcv_nxt, 0); + tcp_rx_user_data(tcp, tcp_seq_num, + ((char *)b) + pkt_len - payload_len, + payload_len); + return; + + case TCP_SYN_RECEIVED: case TCP_ESTABLISHED: - debug_cond(DEBUG_INT_STATE, "TCP_ESTABLISHED %x\n", tcp_flags); - if (payload_len > 0) { - tcp_hole(tcp, tcp_seq_num, payload_len); - tcp_fin = TCP_DATA; /* cause standalone FIN */ + case TCP_FIN_WAIT_1: + case TCP_FIN_WAIT_2: + case TCP_CLOSE_WAIT: + case TCP_CLOSING: + case TCP_LAST_ACK: + if (!tcp_seg_in_wnd(tcp, tcp_seq_num, payload_len)) { + if (tcp_flags & TCP_RST) + return; + action = tcp_stream_fin_needed(tcp, tcp->snd_una) | TCP_ACK; + tcp_send_packet(tcp, action, tcp->snd_una, tcp->rcv_nxt, 0); + return; } - if ((tcp_fin) && - (!IS_ENABLED(CONFIG_PROT_TCP_SACK) || - tcp->lost.len <= TCP_OPT_LEN_2)) { - action = action | TCP_FIN | TCP_PUSH | TCP_ACK; - tcp->state = TCP_CLOSE_WAIT; - } else if (tcp_ack) { - action = TCP_DATA; + tcp_stream_restart_rx_timer(tcp); + + if (tcp_flags & TCP_RST) { + tcp_stream_set_status(tcp, TCP_ERR_RST); + tcp_stream_set_state(tcp, TCP_CLOSED); + return; } - if (tcp_syn) - action = TCP_ACK + TCP_RST; - else if (tcp_push) - action = action | TCP_PUSH; - break; - case TCP_CLOSE_WAIT: - debug_cond(DEBUG_INT_STATE, "TCP_CLOSE_WAIT (%x)\n", tcp_flags); - action = TCP_DATA; - break; - case TCP_FIN_WAIT_2: - debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_2 (%x)\n", tcp_flags); - if (tcp_ack) { - action = TCP_PUSH | TCP_ACK; - tcp->state = TCP_CLOSED; - puts("\n"); - } else if (tcp_syn) { - action = TCP_DATA; - } else if (tcp_fin) { - action = TCP_DATA; + if (tcp_flags & TCP_SYN) { + tcp_send_packet(tcp, TCP_RST, tcp_ack_num, 0, 0); + tcp_stream_set_status(tcp, TCP_ERR_RST); + tcp_stream_set_state(tcp, TCP_CLOSED); + return; } - break; - case TCP_FIN_WAIT_1: - debug_cond(DEBUG_INT_STATE, "TCP_FIN_WAIT_1 (%x)\n", tcp_flags); - if (tcp_fin) { - tcp->rcv_nxt++; - action = TCP_ACK | TCP_FIN; - tcp->state = TCP_FIN_WAIT_2; + + if (!(tcp_flags & TCP_ACK)) + return; + + if (tcp_rx_check_ack_num(tcp, tcp_seq_num, tcp_ack_num, + tcp_win_size) == TCP_PACKET_DROP) { + return; } - if (tcp_syn) - action = TCP_RST; - if (tcp_ack) - tcp->state = TCP_CLOSED; - break; - case TCP_CLOSING: - debug_cond(DEBUG_INT_STATE, "TCP_CLOSING (%x)\n", tcp_flags); - if (tcp_ack) { - action = TCP_PUSH; - tcp->state = TCP_CLOSED; - puts("\n"); - } else if (tcp_syn) { - action = TCP_RST; - } else if (tcp_fin) { - action = TCP_DATA; + + if (tcp_rx_user_data(tcp, tcp_seq_num, + ((char *)b) + pkt_len - payload_len, + payload_len) == TCP_PACKET_DROP) { + return; + } + + if (tcp_flags & TCP_FIN) { + tcp->fin_rx = 1; + tcp->fin_rx_seq = tcp_seq_num + payload_len + 1; + tcp_hole(tcp, tcp_seq_num + payload_len, 1); + action = tcp_stream_fin_needed(tcp, tcp->snd_una) | TCP_ACK; + tcp_send_packet(tcp, action, tcp->snd_una, tcp->rcv_nxt, 0); + } + + if (tcp->fin_rx && + tcp->fin_rx_seq == tcp->rcv_nxt) { + /* all rx data were processed */ + switch (tcp->state) { + case TCP_ESTABLISHED: + tcp_stream_set_state(tcp, TCP_LAST_ACK); + tcp_send_packet_with_retry(tcp, TCP_ACK | TCP_FIN, + tcp->snd_nxt, 0, 0); + tcp->snd_nxt++; + break; + + case TCP_FIN_WAIT_1: + if (tcp_ack_num == tcp->snd_nxt) + tcp_stream_set_state(tcp, TCP_CLOSED); + else + tcp_stream_set_state(tcp, TCP_CLOSING); + break; + + case TCP_FIN_WAIT_2: + tcp_stream_set_state(tcp, TCP_CLOSED); + break; + + default: + break; + } + } + + if (tcp->state == TCP_FIN_WAIT_1 && + tcp_stream_fin_needed(tcp, tcp->snd_una)) { + /* all tx data were acknowledged */ + tcp_send_packet_with_retry(tcp, TCP_ACK | TCP_FIN, + tcp->snd_una, 0, 0); } - break; } - return action; } /** @@ -667,9 +1156,6 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) { int tcp_len = pkt_len - IP_HDR_SIZE; u16 tcp_rx_xsum = b->ip.hdr.ip_sum; - u8 tcp_action = TCP_DATA; - u32 tcp_seq_num, tcp_ack_num; - int tcp_hdr_len, payload_len; struct tcp_stream *tcp; struct in_addr src; @@ -713,54 +1199,59 @@ void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int pkt_len) if (!tcp) return; - tcp_hdr_len = GET_TCP_HDR_LEN_IN_BYTES(b->ip.hdr.tcp_hlen); - payload_len = tcp_len - tcp_hdr_len; + tcp->rx_packets++; + tcp_rx_state_machine(tcp, b, pkt_len); + tcp_stream_put(tcp); +} - if (tcp_hdr_len > TCP_HDR_SIZE) - tcp_parse_options(tcp, (uchar *)b + IP_TCP_HDR_SIZE, - tcp_hdr_len - TCP_HDR_SIZE); - /* - * Incoming sequence and ack numbers are server's view of the numbers. - * The app must swap the numbers when responding. - */ - tcp_seq_num = ntohl(b->ip.hdr.tcp_seq); - tcp_ack_num = ntohl(b->ip.hdr.tcp_ack); +struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport) +{ + struct tcp_stream *tcp; - /* Packets are not ordered. Send to app as received. */ - tcp_action = tcp_state_machine(tcp, b->ip.hdr.tcp_flags, - tcp_seq_num, payload_len); + tcp = tcp_stream_add(rhost, rport, random_port()); + if (!tcp) + return NULL; - tcp_activity_count++; - if (tcp_activity_count > TCP_ACTIVITY) { - puts("| "); - tcp_activity_count = 0; - } + tcp->iss = tcp_get_start_seq(); + tcp->snd_una = tcp->iss; + tcp->snd_nxt = tcp->iss + 1; - if ((tcp_action & TCP_PUSH) || payload_len > 0) { - debug_cond(DEBUG_DEV_PKT, - "TCP Notify (action=%x, Seq=%u,Ack=%u,Pay%d)\n", - tcp_action, tcp_seq_num, tcp_ack_num, payload_len); + tcp_stream_set_state(tcp, TCP_SYN_SENT); + tcp_send_packet_with_retry(tcp, TCP_SYN, tcp->snd_una, 0, 0); - (*tcp_packet_handler) (tcp, (uchar *)b + pkt_len - payload_len, - tcp_seq_num, tcp_ack_num, tcp_action, - payload_len); + return tcp; +} - } else if (tcp_action != TCP_DATA) { - debug_cond(DEBUG_DEV_PKT, - "TCP Action (action=%x,Seq=%u,Ack=%u,Pay=%d)\n", - tcp_action, tcp_ack_num, tcp->rcv_nxt, payload_len); - - /* - * Warning: Incoming Ack & Seq sequence numbers are transposed - * here to outgoing Seq & Ack sequence numbers - */ - net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, - (tcp_action & (~TCP_PUSH)), - tcp_ack_num, tcp->rcv_nxt); - } +void tcp_stream_reset(struct tcp_stream *tcp) +{ + if (tcp->state == TCP_CLOSED) + return; + + tcp_stream_set_time_handler(tcp, 0, NULL); + tcp_send_packet(tcp, TCP_RST, tcp->snd_una, 0, 0); + tcp_stream_set_status(tcp, TCP_ERR_RST); + tcp_stream_set_state(tcp, TCP_CLOSED); } -struct tcp_stream *tcp_stream_connect(struct in_addr rhost, u16 rport) +void tcp_stream_close(struct tcp_stream *tcp) { - return tcp_stream_add(rhost, rport, random_port()); + switch (tcp->state) { + case TCP_SYN_SENT: + tcp_stream_reset(tcp); + break; + case TCP_SYN_RECEIVED: + case TCP_ESTABLISHED: + tcp->fin_tx = 1; + tcp->fin_tx_seq = tcp->snd_nxt; + if (tcp_stream_fin_needed(tcp, tcp->snd_una)) { + /* all tx data were acknowledged */ + tcp_send_packet_with_retry(tcp, TCP_ACK | TCP_FIN, + tcp->snd_una, 0, 0); + } + tcp_stream_set_state(tcp, TCP_FIN_WAIT_1); + tcp->snd_nxt++; + break; + default: + break; + } } diff --git a/net/wget.c b/net/wget.c index a175533ada9..0b082c61947 100644 --- a/net/wget.c +++ b/net/wget.c @@ -22,48 +22,26 @@ DECLARE_GLOBAL_DATA_PTR; /* The default, change with environment variable 'httpdstp' */ #define SERVER_PORT 80 -static const char bootfileGET[] = "GET "; -static const char bootfileHEAD[] = "HEAD "; -static const char bootfile3[] = " HTTP/1.0\r\n\r\n"; -static const char http_eom[] = "\r\n\r\n"; -static const char content_len[] = "Content-Length"; -static const char linefeed[] = "\r\n"; -static int wget_timeout_count; -struct tcp_stream *tcp; - -struct pkt_qd { - uchar *pkt; - unsigned int tcp_seq_num; - unsigned int len; -}; +#define HASHES_PER_LINE 65 -/* - * This is a control structure for out of order packets received. - * The actual packet bufers are in the kernel space, and are - * expected to be overwritten by the downloaded image. - */ -#define PKTQ_SZ (PKTBUFSRX / 4) -static struct pkt_qd pkt_q[PKTQ_SZ]; -static int pkt_q_idx; -static unsigned long content_length; -static unsigned int packets; +#define HTTP_MAX_HDR_LEN 2048 -static unsigned int initial_data_seq_num; -static unsigned int next_data_seq_num; +#define HTTP_STATUS_BAD 0 +#define HTTP_STATUS_OK 200 -static enum wget_state current_wget_state; +static const char http_proto[] = "HTTP/1.0"; +static const char http_eom[] = "\r\n\r\n"; +static const char content_len[] = "Content-Length:"; +static const char linefeed[] = "\r\n"; +static struct in_addr web_server_ip; +static unsigned int server_port; +static unsigned long content_length; +static u32 http_hdr_size, max_rx_pos; +static int wget_tsize_num_hash; static char *image_url; -static unsigned int wget_timeout = WGET_TIMEOUT; - static enum net_loop_state wget_loop_state; -/* Timeout retry parameters */ -static u8 retry_action; /* actions for TCP retry */ -static unsigned int retry_tcp_ack_num; /* TCP retry acknowledge number*/ -static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */ -static int retry_len; /* TCP retry length */ - /** * store_block() - store block in memory * @src: source of data @@ -73,7 +51,6 @@ static int retry_len; /* TCP retry length */ static inline int store_block(uchar *src, unsigned int offset, unsigned int len) { ulong store_addr = image_load_addr + offset; - ulong newsize = offset + len; uchar *ptr; if (CONFIG_IS_ENABLED(LMB) && wget_info->set_bootdev) { @@ -89,372 +66,217 @@ static inline int store_block(uchar *src, unsigned int offset, unsigned int len) memcpy(ptr, src, len); unmap_sysmem(ptr); - if (net_boot_file_size < (offset + len)) - net_boot_file_size = newsize; - return 0; } -/** - * wget_send_stored() - wget response dispatcher - * - * WARNING, This, and only this, is the place in wget.c where - * SEQUENCE NUMBERS are swapped between incoming (RX) - * and outgoing (TX). - * Procedure wget_handler() is correct for RX traffic. - */ -static void wget_send_stored(void) +static void show_block_marker(u32 packets) { - u8 action = retry_action; - int len = retry_len; - unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len); - unsigned int tcp_seq_num = retry_tcp_ack_num; - uchar *ptr, *offset; - - switch (current_wget_state) { - case WGET_CLOSED: - debug_cond(DEBUG_WGET, "wget: send SYN\n"); - current_wget_state = WGET_CONNECTING; - net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, action, - tcp_seq_num, tcp_ack_num); - packets = 0; - break; - case WGET_CONNECTING: - pkt_q_idx = 0; - net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, action, - tcp_seq_num, tcp_ack_num); - - ptr = net_tx_packet + net_eth_hdr_size() + - IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; - offset = ptr; - - switch (wget_info->method) { - case WGET_HTTP_METHOD_HEAD: - memcpy(offset, &bootfileHEAD, strlen(bootfileHEAD)); - offset += strlen(bootfileHEAD); - break; - case WGET_HTTP_METHOD_GET: - default: - memcpy(offset, &bootfileGET, strlen(bootfileGET)); - offset += strlen(bootfileGET); - break; - } + int cnt; - memcpy(offset, image_url, strlen(image_url)); - offset += strlen(image_url); + if (content_length != -1) { + if (net_boot_file_size > content_length) + content_length = net_boot_file_size; - memcpy(offset, &bootfile3, strlen(bootfile3)); - offset += strlen(bootfile3); - net_send_tcp_packet((offset - ptr), tcp->rhost, tcp->rport, tcp->lport, - TCP_PUSH, tcp_seq_num, tcp_ack_num); - current_wget_state = WGET_CONNECTED; - break; - case WGET_CONNECTED: - case WGET_TRANSFERRING: - case WGET_TRANSFERRED: - net_send_tcp_packet(0, tcp->rhost, tcp->rport, tcp->lport, action, - tcp_seq_num, tcp_ack_num); - break; + cnt = net_boot_file_size * 50 / content_length; + while (wget_tsize_num_hash < cnt) { + putc('#'); + wget_tsize_num_hash++; + } + } else { + if ((packets % 10) == 0) + putc('#'); + else if (((packets + 1) % (10 * HASHES_PER_LINE)) == 0) + puts("\n"); } } -static void wget_send(u8 action, unsigned int tcp_seq_num, - unsigned int tcp_ack_num, int len) +static void tcp_stream_on_closed(struct tcp_stream *tcp) { - retry_action = action; - retry_tcp_ack_num = tcp_ack_num; - retry_tcp_seq_num = tcp_seq_num; - retry_len = len; + if (tcp->status != TCP_ERR_OK) + wget_loop_state = NETLOOP_FAIL; + + net_set_state(wget_loop_state); + if (wget_loop_state != NETLOOP_SUCCESS) { + net_boot_file_size = 0; + if (wget_info->status_code == HTTP_STATUS_OK) { + wget_info->status_code = HTTP_STATUS_BAD; + wget_info->hdr_cont_len = 0; + if (wget_info->headers) + wget_info->headers[0] = 0; + } + printf("\nwget: Transfer Fail, TCP status - %d\n", tcp->status); + return; + } - wget_send_stored(); + printf("\nPackets received %d, Transfer Successful\n", tcp->rx_packets); + wget_info->file_size = net_boot_file_size; + if (wget_info->method == WGET_HTTP_METHOD_GET && wget_info->set_bootdev) { + efi_set_bootdev("Http", NULL, image_url, + map_sysmem(image_load_addr, 0), + net_boot_file_size); + env_set_hex("filesize", net_boot_file_size); + } } -void wget_fail(char *error_message, unsigned int tcp_seq_num, - unsigned int tcp_ack_num, u8 action) +static void tcp_stream_on_rcv_nxt_update(struct tcp_stream *tcp, u32 rx_bytes) { - printf("wget: Transfer Fail - %s\n", error_message); - net_set_timeout_handler(0, NULL); - wget_send(action, tcp_seq_num, tcp_ack_num, 0); -} + char *pos, *tail; + uchar saved, *ptr; + int reply_len; -/* - * Interfaces of U-BOOT - */ -static void wget_timeout_handler(void) -{ - if (++wget_timeout_count > WGET_RETRY_COUNT) { - puts("\nRetry count exceeded; starting again\n"); - wget_send(TCP_RST, 0, 0, 0); - net_start_again(); - } else { - puts("T "); - net_set_timeout_handler(wget_timeout + - WGET_TIMEOUT * wget_timeout_count, - wget_timeout_handler); - wget_send_stored(); + if (http_hdr_size) { + net_boot_file_size = rx_bytes - http_hdr_size; + show_block_marker(tcp->rx_packets); + return; } -} -#define PKT_QUEUE_OFFSET 0x20000 -#define PKT_QUEUE_PACKET_SIZE 0x800 + ptr = map_sysmem(image_load_addr, rx_bytes + 1); -static void wget_fill_info(const uchar *pkt, int hlen) -{ - const char *first_space; - const char *second_space; - char *pos, *end; - - if (wget_info->headers) { - if (hlen < MAX_HTTP_HEADERS_SIZE) - strncpy(wget_info->headers, pkt, hlen); - else - hlen = 0; - wget_info->headers[hlen] = 0; + saved = ptr[rx_bytes]; + ptr[rx_bytes] = '\0'; + pos = strstr((char *)ptr, http_eom); + ptr[rx_bytes] = saved; + + if (!pos) { + if (rx_bytes < HTTP_MAX_HDR_LEN && + tcp->state == TCP_ESTABLISHED) + goto end; + + printf("ERROR: misssed HTTP header\n"); + tcp_stream_close(tcp); + goto end; } - //Get status code - first_space = strchr(pkt, ' '); - if (!first_space) { - wget_info->status_code = -1; - return; + http_hdr_size = pos - (char *)ptr + strlen(http_eom); + *pos = '\0'; + + if (wget_info->headers && http_hdr_size < MAX_HTTP_HEADERS_SIZE) + strcpy(wget_info->headers, ptr); + + /* check for HTTP proto */ + if (strncasecmp((char *)ptr, "HTTP/", 5)) { + debug_cond(DEBUG_WGET, "wget: Connected Bad Xfer " + "(no HTTP Status Line found)\n"); + tcp_stream_close(tcp); + goto end; } - second_space = strchr(first_space + 1, ' '); - if (!second_space) { - wget_info->status_code = -1; - return; + /* get HTTP reply len */ + pos = strstr((char *)ptr, linefeed); + if (pos) + reply_len = pos - (char *)ptr; + else + reply_len = http_hdr_size - strlen(http_eom); + + pos = strchr((char *)ptr, ' '); + if (!pos || pos - (char *)ptr > reply_len) { + debug_cond(DEBUG_WGET, "wget: Connected Bad Xfer " + "(no HTTP Status Code found)\n"); + tcp_stream_close(tcp); + goto end; } - wget_info->status_code = (u32)simple_strtoul(first_space + 1, &end, 10); + wget_info->status_code = (u32)simple_strtoul(pos + 1, &tail, 10); + if (tail == pos + 1 || *tail != ' ') { + debug_cond(DEBUG_WGET, "wget: Connected Bad Xfer " + "(bad HTTP Status Code)\n"); + tcp_stream_close(tcp); + goto end; + } - if (second_space != end) - wget_info->status_code = -1; + debug_cond(DEBUG_WGET, + "wget: HTTP Status Code %d\n", wget_info->status_code); + + if (wget_info->status_code != HTTP_STATUS_OK) { + debug_cond(DEBUG_WGET, "wget: Connected Bad Xfer\n"); + tcp_stream_close(tcp); + goto end; + } - pos = strstr((char *)pkt, content_len); + debug_cond(DEBUG_WGET, "wget: Connctd pkt %p hlen %x\n", + ptr, http_hdr_size); + content_length = -1; + pos = strstr((char *)ptr, content_len); if (pos) { - pos += sizeof(content_len) + 1; + pos += strlen(content_len) + 1; while (*pos == ' ') pos++; - content_length = simple_strtoul(pos, &end, 10); + content_length = simple_strtoul(pos, &tail, 10); + if (*tail != '\r' && *tail != '\n' && *tail != '\0') + content_length = -1; + } + + if (content_length >= 0) { debug_cond(DEBUG_WGET, "wget: Connected Len %lu\n", content_length); wget_info->hdr_cont_len = content_length; } -} -static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, - u8 action, unsigned int tcp_ack_num, unsigned int len) -{ - uchar *pkt_in_q; - char *pos; - int hlen, i; - uchar *ptr1; - - pkt[len] = '\0'; - pos = strstr((char *)pkt, http_eom); + net_boot_file_size = rx_bytes - http_hdr_size; + memmove(ptr, ptr + http_hdr_size, max_rx_pos + 1 - http_hdr_size); + wget_loop_state = NETLOOP_SUCCESS; - if (!pos) { - debug_cond(DEBUG_WGET, - "wget: Connected, data before Header %p\n", pkt); - pkt_in_q = (void *)image_load_addr + PKT_QUEUE_OFFSET + - (pkt_q_idx * PKT_QUEUE_PACKET_SIZE); - - ptr1 = map_sysmem((ulong)pkt_in_q, len); - memcpy(ptr1, pkt, len); - unmap_sysmem(ptr1); - - pkt_q[pkt_q_idx].pkt = pkt_in_q; - pkt_q[pkt_q_idx].tcp_seq_num = tcp_seq_num; - pkt_q[pkt_q_idx].len = len; - pkt_q_idx++; +end: + unmap_sysmem(ptr); +} - if (pkt_q_idx >= PKTQ_SZ) { - printf("wget: Fatal error, queue overrun!\n"); - net_set_state(NETLOOP_FAIL); +static int tcp_stream_rx(struct tcp_stream *tcp, u32 rx_offs, void *buf, int len) +{ + if ((max_rx_pos == (u32)(-1)) || (max_rx_pos < rx_offs + len - 1)) + max_rx_pos = rx_offs + len - 1; - return; - } - } else { - debug_cond(DEBUG_WGET, "wget: Connected HTTP Header %p\n", pkt); - /* sizeof(http_eom) - 1 is the string length of (http_eom) */ - hlen = pos - (char *)pkt + sizeof(http_eom) - 1; - pos = strstr((char *)pkt, linefeed); - if (pos > 0) - i = pos - (char *)pkt; - else - i = hlen; - printf("%.*s", i, pkt); - - current_wget_state = WGET_TRANSFERRING; - - initial_data_seq_num = tcp_seq_num + hlen; - next_data_seq_num = tcp_seq_num + len; - - wget_fill_info(pkt, hlen); - debug_cond(DEBUG_WGET, - "wget: HTTP Status Code %d\n", wget_info->status_code); + store_block(buf, rx_offs - http_hdr_size, len); - if (wget_info->status_code != 200) { - debug_cond(DEBUG_WGET, - "wget: Connected Bad Xfer\n"); - wget_loop_state = NETLOOP_FAIL; - wget_send(action, tcp_seq_num, tcp_ack_num, len); - } else { - debug_cond(DEBUG_WGET, - "wget: Connected Pkt %p hlen %x\n", - pkt, hlen); - - net_boot_file_size = 0; - - if (len > hlen) { - if (store_block(pkt + hlen, 0, len - hlen) != 0) { - wget_loop_state = NETLOOP_FAIL; - wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action); - net_set_state(NETLOOP_FAIL); - return; - } - } - - for (i = 0; i < pkt_q_idx; i++) { - int err; - - ptr1 = map_sysmem((ulong)pkt_q[i].pkt, - pkt_q[i].len); - err = store_block(ptr1, - pkt_q[i].tcp_seq_num - - initial_data_seq_num, - pkt_q[i].len); - unmap_sysmem(ptr1); - debug_cond(DEBUG_WGET, - "wget: Conncted pkt Q %p len %x\n", - pkt_q[i].pkt, pkt_q[i].len); - if (err) { - wget_loop_state = NETLOOP_FAIL; - wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action); - net_set_state(NETLOOP_FAIL); - return; - } - } - } - } - wget_send(action, tcp_seq_num, tcp_ack_num, len); + return len; } -/** - * wget_handler() - TCP handler of wget - * @tcp: TCP stream - * @pkt: pointer to the application packet - * @tcp_seq_num: TCP sequential number - * @tcp_ack_num: TCP acknowledgment number - * @action: TCP action (SYN, ACK, FIN, etc) - * @len: packet length - * - * In the "application push" invocation, the TCP header with all - * its information is pointed to by the packet pointer. - */ -static void wget_handler(struct tcp_stream *tcp, uchar *pkt, - u32 tcp_seq_num, u32 tcp_ack_num, - u8 action, unsigned int len) +static int tcp_stream_tx(struct tcp_stream *tcp, u32 tx_offs, void *buf, int maxlen) { - enum tcp_state wget_tcp_state = tcp_stream_get_state(tcp); + int ret; + const char *method; - net_set_timeout_handler(wget_timeout, wget_timeout_handler); - packets++; + if (tx_offs) + return 0; - switch (current_wget_state) { - case WGET_CLOSED: - debug_cond(DEBUG_WGET, "wget: Handler: Error!, State wrong\n"); - break; - case WGET_CONNECTING: - debug_cond(DEBUG_WGET, - "wget: Connecting In len=%x, Seq=%u, Ack=%u\n", - len, tcp_seq_num, tcp_ack_num); - if (!len) { - if (wget_tcp_state == TCP_ESTABLISHED) { - debug_cond(DEBUG_WGET, - "wget: Cting, send, len=%x\n", len); - wget_send(action, tcp_seq_num, tcp_ack_num, - len); - } else { - printf("%.*s", len, pkt); - wget_fail("wget: Handler Connected Fail\n", - tcp_seq_num, tcp_ack_num, action); - } - } + switch (wget_info->method) { + case WGET_HTTP_METHOD_HEAD: + method = "HEAD"; break; - case WGET_CONNECTED: - debug_cond(DEBUG_WGET, "wget: Connected seq=%u, len=%x\n", - tcp_seq_num, len); - if (!len) { - wget_fail("Image not found, no data returned\n", - tcp_seq_num, tcp_ack_num, action); - } else { - wget_connected(pkt, tcp_seq_num, action, tcp_ack_num, len); - } + case WGET_HTTP_METHOD_GET: + default: + method = "GET"; break; - case WGET_TRANSFERRING: - debug_cond(DEBUG_WGET, - "wget: Transferring, seq=%x, ack=%x,len=%x\n", - tcp_seq_num, tcp_ack_num, len); + } - if (next_data_seq_num != tcp_seq_num) { - debug_cond(DEBUG_WGET, "wget: seq=%x packet was lost\n", next_data_seq_num); - return; - } - next_data_seq_num = tcp_seq_num + len; + ret = snprintf(buf, maxlen, "%s %s %s\r\n\r\n", + method, image_url, http_proto); - if (store_block(pkt, tcp_seq_num - initial_data_seq_num, len) != 0) { - wget_fail("wget: store error\n", - tcp_seq_num, tcp_ack_num, action); - net_set_state(NETLOOP_FAIL); - return; - } + return ret; +} - switch (wget_tcp_state) { - case TCP_FIN_WAIT_2: - wget_send(TCP_ACK, tcp_seq_num, tcp_ack_num, len); - fallthrough; - case TCP_SYN_SENT: - case TCP_SYN_RECEIVED: - case TCP_CLOSING: - case TCP_FIN_WAIT_1: - case TCP_CLOSED: - net_set_state(NETLOOP_FAIL); - break; - case TCP_ESTABLISHED: - wget_send(TCP_ACK, tcp_seq_num, tcp_ack_num, - len); - wget_loop_state = NETLOOP_SUCCESS; - break; - case TCP_CLOSE_WAIT: /* End of transfer */ - current_wget_state = WGET_TRANSFERRED; - wget_send(action | TCP_ACK | TCP_FIN, - tcp_seq_num, tcp_ack_num, len); - break; - } - break; - case WGET_TRANSFERRED: - printf("Packets received %d, Transfer Successful\n", packets); - net_set_state(wget_loop_state); - wget_info->file_size = net_boot_file_size; - if (wget_info->method == WGET_HTTP_METHOD_GET && wget_info->set_bootdev) { - efi_set_bootdev("Http", NULL, image_url, - map_sysmem(image_load_addr, 0), - net_boot_file_size); - env_set_hex("filesize", net_boot_file_size); - } - break; - } +static int tcp_stream_on_create(struct tcp_stream *tcp) +{ + if (tcp->rhost.s_addr != web_server_ip.s_addr || + tcp->rport != server_port) + return 0; + + tcp->max_retry_count = WGET_RETRY_COUNT; + tcp->initial_timeout = WGET_TIMEOUT; + tcp->on_closed = tcp_stream_on_closed; + tcp->on_rcv_nxt_update = tcp_stream_on_rcv_nxt_update; + tcp->rx = tcp_stream_rx; + tcp->tx = tcp_stream_tx; + + return 1; } #define BLOCKSIZE 512 void wget_start(void) { - struct in_addr web_server_ip; - unsigned int server_port; + struct tcp_stream *tcp; if (!wget_info) wget_info = &default_wget_info; @@ -496,12 +318,6 @@ void wget_start(void) debug_cond(DEBUG_WGET, "\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr); - net_set_timeout_handler(wget_timeout, wget_timeout_handler); - tcp_set_tcp_handler(wget_handler); - - wget_timeout_count = 0; - current_wget_state = WGET_CLOSED; - /* * Zero out server ether to force arp resolution in case * the server ip for the previous u-boot command, for example dns @@ -510,14 +326,27 @@ void wget_start(void) memset(net_server_ethaddr, 0, 6); + max_rx_pos = (u32)(-1); + net_boot_file_size = 0; + http_hdr_size = 0; + wget_tsize_num_hash = 0; + wget_loop_state = NETLOOP_FAIL; + + wget_info->status_code = HTTP_STATUS_BAD; + wget_info->file_size = 0; + wget_info->hdr_cont_len = 0; + if (wget_info->headers) + wget_info->headers[0] = 0; + server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff; + tcp_stream_set_on_create_handler(tcp_stream_on_create); tcp = tcp_stream_connect(web_server_ip, server_port); if (!tcp) { + printf("No free tcp streams\n"); net_set_state(NETLOOP_FAIL); return; } - - wget_send(TCP_SYN, 0, 0, 0); + tcp_stream_put(tcp); } int wget_do_request(ulong dst_addr, char *uri) -- cgit v1.3.1 From 2fd7a04e7c172a2918d74d348fa70c4d0b91e6ce Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 14 Dec 2024 23:45:11 +0100 Subject: arm64: renesas: Align configuration headers Align R-Car Gen2/Gen3/Gen4 configuration header file to look basically the same way across these three SoC generations. There are subtle difference between the remaining bits in those files across SoC generations, but the common bits are now aligned. There is not much left in those headers either, most of the configuration is now converted to Kconfig. Specifically for R-Car Gen3, GIC registers have been moved to architecture specific header file rcar-gen3-base.h , the rest of the changes here are comment changes and indentation changes. Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/include/mach/rcar-gen3-base.h | 5 +++++ include/configs/rcar-gen2-common.h | 10 ++++++---- include/configs/rcar-gen3-common.h | 19 ++++++------------- include/configs/rcar-gen4-common.h | 8 +++----- 4 files changed, 20 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h index 5e2e9eca452..7b4f5f0c651 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h @@ -67,6 +67,11 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C +/* GICv3 */ +/* Distributor Registers */ +#define GICD_BASE 0xF1010000 +#define GICC_BASE 0xF1020000 + /* PFC */ #define PFC_PUEN5 0xE6060414 #define PUEN_SSI_SDATA4 BIT(17) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 67c9faeca57..020e79ca2a8 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * include/configs/rcar-gen2-common.h + * This file is R-Car Gen2 common configuration file. * - * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2013-2024 Renesas Electronics Corporation */ #ifndef __RCAR_GEN2_COMMON_H @@ -10,14 +11,15 @@ #include -/* console */ -#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } +/* Memory */ #define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ -#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) #endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 3f0831a901c..bedb1c0843e 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -3,7 +3,7 @@ * include/configs/rcar-gen3-common.h * This file is R-Car Gen3 common configuration file. * - * Copyright (C) 2015-2017 Renesas Electronics Corporation + * Copyright (C) 2015-2024 Renesas Electronics Corporation */ #ifndef __RCAR_GEN3_COMMON_H @@ -11,24 +11,17 @@ #include -/* boot option */ +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* console */ -#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } - -/* MEMORY */ +/* Memory */ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) -/* ENV setting */ - -#define CFG_EXTRA_ENV_SETTINGS \ +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h index 37a37c013df..1a00adb79d1 100644 --- a/include/configs/rcar-gen4-common.h +++ b/include/configs/rcar-gen4-common.h @@ -3,7 +3,7 @@ * include/configs/rcar-gen4-common.h * This file is R-Car Gen4 common configuration file. * - * Copyright (C) 2021 Renesas Electronics Corporation + * Copyright (C) 2021-2024 Renesas Electronics Corporation */ #ifndef __RCAR_GEN4_COMMON_H @@ -12,7 +12,7 @@ #include /* Console */ -#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 } +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 } /* Memory */ #define DRAM_RSV_SIZE 0x08000000 @@ -20,10 +20,8 @@ #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) -/* PHY needs a longer autoneg timeout */ - /* Environment setting */ -#define CFG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __RCAR_GEN4_COMMON_H */ -- cgit v1.3.1 From 22db5b213703e7ae17b8b2496393253b3664bdd5 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 10 Dec 2024 20:25:50 -0600 Subject: lmb: Improve kernel-doc comments Fix warnings from kernel-doc script. Improve and unify overall style of kernel-doc comments in lmb source files. Move all kernel-doc comments for public functions into the header, as recommended in U-Boot documentation [1]: Non-trivial functions should have a comment which describes what they do. If it is an exported function, put the comment in the header file so the API is in one place. If it is a static function, put it in the C file. This also takes care of existing duplication. While at it, do a bit of cosmetic cleanups as well. No functional change. [1] doc/develop/codingstyle.rst Signed-off-by: Sam Protsenko Acked-by: Ilias Apalodimas --- include/lmb.h | 125 ++++++++++++++++++++++++++++++++++------------------------ lib/lmb.c | 55 -------------------------- 2 files changed, 74 insertions(+), 106 deletions(-) (limited to 'include') diff --git a/include/lmb.h b/include/lmb.h index f221f0cce8f..03d5fac6aa7 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -1,6 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Logical memory blocks. + * + * Copyright (C) 2001 Peter Bergner, IBM Corp. + */ + #ifndef _LINUX_LMB_H #define _LINUX_LMB_H + #ifdef __KERNEL__ #include @@ -8,21 +15,15 @@ #include #include -/* - * Logical memory blocks. - * - * Copyright (C) 2001 Peter Bergner, IBM Corp. - */ - -#define LMB_ALLOC_ANYWHERE 0 -#define LMB_ALIST_INITIAL_SIZE 4 +#define LMB_ALLOC_ANYWHERE 0 +#define LMB_ALIST_INITIAL_SIZE 4 /** - * enum lmb_flags - definition of memory region attributes - * @LMB_NONE: no special request - * @LMB_NOMAP: don't add to mmu configuration - * @LMB_NOOVERWRITE: the memory region cannot be overwritten/re-reserved - * @LMB_NONOTIFY: do not notify other modules of changes to this memory region + * enum lmb_flags - Definition of memory region attributes + * @LMB_NONE: No special request + * @LMB_NOMAP: Don't add to MMU configuration + * @LMB_NOOVERWRITE: The memory region cannot be overwritten/re-reserved + * @LMB_NONOTIFY: Do not notify other modules of changes to this memory region */ enum lmb_flags { LMB_NONE = 0, @@ -32,11 +33,10 @@ enum lmb_flags { }; /** - * struct lmb_region - Description of one region. - * - * @base: Base address of the region. - * @size: Size of the region - * @flags: memory region attributes + * struct lmb_region - Description of one region + * @base: Base address of the region + * @size: Size of the region + * @flags: Memory region attributes */ struct lmb_region { phys_addr_t base; @@ -46,10 +46,9 @@ struct lmb_region { /** * struct lmb - The LMB structure - * - * @free_mem: List of free memory regions - * @used_mem: List of used/reserved memory regions - * @test: Is structure being used for LMB tests + * @free_mem: List of free memory regions + * @used_mem: List of used/reserved memory regions + * @test: Is structure being used for LMB tests */ struct lmb { struct alist free_mem; @@ -58,51 +57,77 @@ struct lmb { }; /** - * lmb_init() - Initialise the LMB module + * lmb_init() - Initialise the LMB module. + * + * Return: 0 on success, negative error code on failure. * * Initialise the LMB lists needed for keeping the memory map. There - * are two lists, in form of alloced list data structure. One for the + * are two lists, in form of allocated list data structure. One for the * available memory, and one for the used memory. Initialise the two * lists as part of board init. Add memory to the available memory * list and reserve common areas by adding them to the used memory * list. - * - * Return: 0 on success, -ve on error */ int lmb_init(void); /** - * lmb_add_memory() - Add memory range for LMB allocations + * lmb_add_memory() - Add memory range for LMB allocations. * * Add the entire available memory range to the pool of memory that * can be used by the LMB module for allocations. - * - * Return: None */ void lmb_add_memory(void); long lmb_add(phys_addr_t base, phys_size_t size); -long lmb_reserve(phys_addr_t base, phys_size_t size); + /** - * lmb_reserve_flags - Reserve one region with a specific flags bitfield. + * lmb_reserve() - Reserve a memory region (with no special flags) + * @base: Base address of the memory region + * @size: Size of the memory region * - * @base: base address of the memory region - * @size: size of the memory region - * @flags: flags for the memory region - * Return: 0 if OK, > 0 for coalesced region or a negative error code. + * Return: 0 on success, negative error code on failure. + */ +long lmb_reserve(phys_addr_t base, phys_size_t size); + +/** + * lmb_reserve_flags() - Reserve one region with a specific flags bitfield + * @base: Base address of the memory region + * @size: Size of the memory region + * @flags: Flags for the memory region + * + * Return: + * * %0 - Added successfully, or it's already added (only if LMB_NONE) + * * %-EEXIST - The region is already added, and flags != LMB_NONE + * * %-1 - Failure */ long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags); + phys_addr_t lmb_alloc(phys_size_t size, ulong align); phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size); phys_size_t lmb_get_free_size(phys_addr_t addr); +/** + * lmb_alloc_base_flags() - Allocate specified memory region with specified + * attributes + * @size: Size of the region requested + * @align: Alignment of the memory region requested + * @max_addr: Maximum address of the requested region + * @flags: Memory region attributes to be set + * + * Allocate a region of memory with the attributes specified through the + * parameter. The max_addr parameter is used to specify the maximum address + * below which the requested region should be allocated. + * + * Return: Base address on success, 0 on error. + */ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, phys_addr_t max_addr, uint flags); /** - * lmb_alloc_addr_flags() - Allocate specified memory address with specified attributes + * lmb_alloc_addr_flags() - Allocate specified memory address with specified + * attributes * @base: Base Address requested * @size: Size of the region requested * @flags: Memory region attributes to be set @@ -111,20 +136,21 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, * parameter. The base parameter is used to specify the base address * of the requested region. * - * Return: base address on success, 0 on error + * Return: Base address on success, 0 on error. */ phys_addr_t lmb_alloc_addr_flags(phys_addr_t base, phys_size_t size, uint flags); /** - * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set + * lmb_is_reserved_flags() - Test if address is in reserved region with flag + * bits set + * @addr: Address to be tested + * @flags: Bitmap with bits to be tested * * The function checks if a reserved region comprising @addr exists which has * all flag bits set which are set in @flags. * - * @addr: address to be tested - * @flags: bitmap with bits to be tested - * Return: 1 if matching reservation exists, 0 otherwise + * Return: 1 if matching reservation exists, 0 otherwise. */ int lmb_is_reserved_flags(phys_addr_t addr, int flags); @@ -134,9 +160,7 @@ int lmb_is_reserved_flags(phys_addr_t addr, int flags); * @size: Size of the region to be freed * @flags: Memory region attributes * - * Free up a region of memory. - * - * Return: 0 if successful, -1 on failure + * Return: 0 on success, negative error code on failure. */ long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags); @@ -160,7 +184,7 @@ static inline int lmb_read_check(phys_addr_t addr, phys_size_t len) * io_lmb_setup() - Initialize LMB struct * @io_lmb: IO LMB to initialize * - * Returns: 0 on success, negative error code on failure + * Return: 0 on success, negative error code on failure. */ int io_lmb_setup(struct lmb *io_lmb); @@ -178,12 +202,13 @@ void io_lmb_teardown(struct lmb *io_lmb); * * Add the IOVA space [base, base + size] to be managed by io_lmb. * - * Returns: 0 if the region addition was successful, -1 on failure + * Return: 0 on success, negative error code on failure. */ long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size); /** - * io_lmb_alloc() - Allocate specified IO memory address with specified alignment + * io_lmb_alloc() - Allocate specified IO memory address with specified + * alignment * @io_lmb: LMB to alloc from * @size: Size of the region requested * @align: Required address and size alignment @@ -191,7 +216,7 @@ long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size); * Allocate a region of IO memory. The base parameter is used to specify the * base address of the requested region. * - * Return: base IO address on success, 0 on error + * Return: Base IO address on success, 0 on error. */ phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align); @@ -201,9 +226,7 @@ phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align); * @base: Base Address of region to be freed * @size: Size of the region to be freed * - * Free up a region of IOVA space. - * - * Return: 0 if successful, -1 on failure + * Return: 0 on success, negative error code on failure. */ long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size); diff --git a/lib/lmb.c b/lib/lmb.c index 40f03151929..f9880a8dc62 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -601,14 +601,6 @@ static __maybe_unused void lmb_reserve_common_spl(void) } } -/** - * lmb_add_memory() - Add memory range for LMB allocations - * - * Add the entire available memory range to the pool of memory that - * can be used by the LMB module for allocations. - * - * Return: None - */ void lmb_add_memory(void) { int i; @@ -665,16 +657,6 @@ long lmb_add(phys_addr_t base, phys_size_t size) return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE); } -/** - * lmb_free_flags() - Free up a region of memory - * @base: Base Address of region to be freed - * @size: Size of the region to be freed - * @flags: Memory region attributes - * - * Free up a region of memory. - * - * Return: 0 if successful, negative error code on failure - */ long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags) { @@ -782,19 +764,6 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr) return alloc; } -/** - * lmb_alloc_base_flags() - Allocate specified memory region with specified attributes - * @size: Size of the region requested - * @align: Alignment of the memory region requested - * @max_addr: Maximum address of the requested region - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. The max_addr parameter is used to specify the maximum address - * below which the requested region should be allocated. - * - * Return: base address on success, 0 on error - */ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, phys_addr_t max_addr, uint flags) { @@ -843,18 +812,6 @@ phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size) return _lmb_alloc_addr(base, size, LMB_NONE); } -/** - * lmb_alloc_addr_flags() - Allocate specified memory address with specified attributes - * @base: Base Address requested - * @size: Size of the region requested - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. The base parameter is used to specify the base address - * of the requested region. - * - * Return: base address on success, 0 on error - */ phys_addr_t lmb_alloc_addr_flags(phys_addr_t base, phys_size_t size, uint flags) { @@ -927,18 +884,6 @@ static int lmb_setup(bool test) return 0; } -/** - * lmb_init() - Initialise the LMB module - * - * Initialise the LMB lists needed for keeping the memory map. There - * are two lists, in form of alloced list data structure. One for the - * available memory, and one for the used memory. Initialise the two - * lists as part of board init. Add memory to the available memory - * list and reserve common areas by adding them to the used memory - * list. - * - * Return: 0 on success, -ve on error - */ int lmb_init(void) { int ret; -- cgit v1.3.1 From 3d56c06551d7a54870cfdf8c639b3ff35521b87f Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 09:02:31 +0200 Subject: lmb: Move enum lmb_flags to a u32 LMB flags is not an enum anymore. It's currently used as a bitmask in various places of our code. So make it a u32 which is more appropriate when dealing with masks. Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Signed-off-by: Ilias Apalodimas --- boot/image-fdt.c | 4 ++-- include/lmb.h | 27 +++++++++++++-------------- lib/lmb.c | 18 +++++++++--------- test/cmd/bdinfo.c | 2 +- 4 files changed, 25 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 73c43c30684..cda7c3aa9e3 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -68,7 +68,7 @@ static const struct legacy_img_hdr *image_get_fdt(ulong fdt_addr) } #endif -static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags) +static void boot_fdt_reserve_region(u64 addr, u64 size, u32 flags) { long ret; @@ -100,7 +100,7 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) int i, total, ret; int nodeoffset, subnode; struct fdt_resource res; - enum lmb_flags flags; + u32 flags; if (fdt_check_header(fdt_blob) != 0) return; diff --git a/include/lmb.h b/include/lmb.h index 03d5fac6aa7..3b911d5d839 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -19,18 +19,17 @@ #define LMB_ALIST_INITIAL_SIZE 4 /** - * enum lmb_flags - Definition of memory region attributes - * @LMB_NONE: No special request - * @LMB_NOMAP: Don't add to MMU configuration - * @LMB_NOOVERWRITE: The memory region cannot be overwritten/re-reserved - * @LMB_NONOTIFY: Do not notify other modules of changes to this memory region - */ -enum lmb_flags { - LMB_NONE = 0, - LMB_NOMAP = BIT(1), - LMB_NOOVERWRITE = BIT(2), - LMB_NONOTIFY = BIT(3), -}; + * DOC: Memory region attribute flags. + * + * %LMB_NONE: No special request + * %LMB_NOMAP: Don't add to MMU configuration + * %LMB_NOOVERWRITE: The memory region cannot be overwritten/re-reserved + * %LMB_NONOTIFY: Do not notify other modules of changes to this memory region + */ +#define LMB_NONE 0 +#define LMB_NOMAP BIT(0) +#define LMB_NOOVERWRITE BIT(1) +#define LMB_NONOTIFY BIT(2) /** * struct lmb_region - Description of one region @@ -41,7 +40,7 @@ enum lmb_flags { struct lmb_region { phys_addr_t base; phys_size_t size; - enum lmb_flags flags; + u32 flags; }; /** @@ -101,7 +100,7 @@ long lmb_reserve(phys_addr_t base, phys_size_t size); * * %-1 - Failure */ long lmb_reserve_flags(phys_addr_t base, phys_size_t size, - enum lmb_flags flags); + u32 flags); phys_addr_t lmb_alloc(phys_size_t size, ulong align); phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); diff --git a/lib/lmb.c b/lib/lmb.c index b9c26cb02e1..edecdb8e9cb 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -188,7 +188,7 @@ static long lmb_resize_regions(struct alist *lmb_rgn_lst, * * %-1 - Failure */ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, - phys_size_t size, enum lmb_flags flags) + phys_size_t size, u32 flags) { unsigned long coalesced = 0; long ret, i; @@ -201,7 +201,7 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, for (i = 0; i < lmb_rgn_lst->count; i++) { phys_addr_t rgnbase = rgn[i].base; phys_size_t rgnsize = rgn[i].size; - enum lmb_flags rgnflags = rgn[i].flags; + u32 rgnflags = rgn[i].flags; ret = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); if (ret > 0) { @@ -430,14 +430,14 @@ long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size) static struct lmb lmb; -static bool lmb_should_notify(enum lmb_flags flags) +static bool lmb_should_notify(u32 flags) { return !lmb.test && !(flags & LMB_NONOTIFY) && CONFIG_IS_ENABLED(EFI_LOADER); } static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op, - enum lmb_flags flags) + u32 flags) { u64 efi_addr; u64 pages; @@ -470,7 +470,7 @@ static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op, return 0; } -static void lmb_print_region_flags(enum lmb_flags flags) +static void lmb_print_region_flags(u32 flags) { const char * const flag_str[] = { "none", "no-map", "no-overwrite", "no-notify" }; @@ -495,7 +495,7 @@ static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name) { struct lmb_region *rgn = lmb_rgn_lst->data; unsigned long long base, size, end; - enum lmb_flags flags; + u32 flags; int i; printf(" %s.count = %#x\n", name, lmb_rgn_lst->count); @@ -669,7 +669,7 @@ long lmb_free(phys_addr_t base, phys_size_t size) return lmb_free_flags(base, size, LMB_NONE); } -long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags) +long lmb_reserve_flags(phys_addr_t base, phys_size_t size, u32 flags) { long ret = 0; struct alist *lmb_rgn_lst = &lmb.used_mem; @@ -687,7 +687,7 @@ long lmb_reserve(phys_addr_t base, phys_size_t size) } static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, - phys_addr_t max_addr, enum lmb_flags flags) + phys_addr_t max_addr, u32 flags) { int ret; long i, rgn; @@ -774,7 +774,7 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, } static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, - enum lmb_flags flags) + u32 flags) { long rgn; struct lmb_region *lmb_memory = lmb.free_mem.data; diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index bb419ab2394..014391b38ac 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -104,7 +104,7 @@ static int lmb_test_dump_region(struct unit_test_state *uts, { struct lmb_region *rgn = lmb_rgn_lst->data; unsigned long long base, size, end; - enum lmb_flags flags; + u32 flags; int i; ut_assert_nextline(" %s.count = %#x", name, lmb_rgn_lst->count); -- cgit v1.3.1 From 900a8951c3b6035c25632438ebc7240cbc77883c Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 09:02:32 +0200 Subject: lmb: Remove lmb_reserve_flags() lmb_reserve() is just calling lmb_reserve_flags() with LMB_NONE. There's not much we gain from this abstraction. So let's remove the latter, add the flags argument to lmb_reserve() and make the code a bit easier to follow. Reviewed-by: Tom Rini Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Signed-off-by: Ilias Apalodimas --- arch/powerpc/cpu/mpc85xx/mp.c | 2 +- arch/powerpc/lib/misc.c | 2 +- boot/bootm.c | 3 ++- boot/image-board.c | 2 +- boot/image-fdt.c | 6 +++--- cmd/booti.c | 2 +- cmd/bootz.c | 2 +- cmd/load.c | 2 +- include/lmb.h | 14 ++----------- lib/lmb.c | 28 ++++++++++--------------- test/lib/lmb.c | 48 +++++++++++++++++++++---------------------- 11 files changed, 48 insertions(+), 63 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index bed465cb2cb..8918a401fac 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -412,7 +412,7 @@ void cpu_mp_lmb_reserve(void) { u32 bootpg = determine_mp_bootpg(NULL); - lmb_reserve(bootpg, 4096); + lmb_reserve(bootpg, 4096, LMB_NONE); } void setup_mp(void) diff --git a/arch/powerpc/lib/misc.c b/arch/powerpc/lib/misc.c index 4cd23b3406d..7e303419624 100644 --- a/arch/powerpc/lib/misc.c +++ b/arch/powerpc/lib/misc.c @@ -40,7 +40,7 @@ int arch_misc_init(void) printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", size, (unsigned long long)bootm_size); - lmb_reserve(base, bootm_size - size); + lmb_reserve(base, bootm_size - size, LMB_NONE); } #ifdef CONFIG_MP diff --git a/boot/bootm.c b/boot/bootm.c index 16a43d519a8..854ac7ec738 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -696,7 +696,8 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) } if (CONFIG_IS_ENABLED(LMB)) - lmb_reserve(images->os.load, (load_end - images->os.load)); + lmb_reserve(images->os.load, (load_end - images->os.load), + LMB_NONE); return 0; } diff --git a/boot/image-board.c b/boot/image-board.c index b726bd6b303..070ada00718 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -562,7 +562,7 @@ int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, debug(" in-place initrd\n"); *initrd_start = rd_data; *initrd_end = rd_data + rd_len; - lmb_reserve(rd_data, rd_len); + lmb_reserve(rd_data, rd_len, LMB_NONE); } else { if (initrd_high) *initrd_start = (ulong)lmb_alloc_base(rd_len, diff --git a/boot/image-fdt.c b/boot/image-fdt.c index cda7c3aa9e3..d717f669072 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -72,7 +72,7 @@ static void boot_fdt_reserve_region(u64 addr, u64 size, u32 flags) { long ret; - ret = lmb_reserve_flags(addr, size, flags); + ret = lmb_reserve(addr, size, flags); if (!ret) { debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, @@ -184,7 +184,7 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) if (desired_addr == ~0UL) { /* All ones means use fdt in place */ of_start = fdt_blob; - lmb_reserve(map_to_sysmem(of_start), of_len); + lmb_reserve(map_to_sysmem(of_start), of_len, LMB_NONE); disable_relocation = 1; } else if (desired_addr) { addr = lmb_alloc_base(of_len, 0x1000, desired_addr); @@ -675,7 +675,7 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb) /* Create a new LMB reservation */ if (CONFIG_IS_ENABLED(LMB) && lmb) - lmb_reserve(map_to_sysmem(blob), of_size); + lmb_reserve(map_to_sysmem(blob), of_size, LMB_NONE); #if defined(CONFIG_ARCH_KEYSTONE) if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) diff --git a/cmd/booti.c b/cmd/booti.c index 43e79e87201..1a57fe91397 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -87,7 +87,7 @@ static int booti_start(struct bootm_info *bmi) images->os.start = relocated_addr; images->os.end = relocated_addr + image_size; - lmb_reserve(images->ep, le32_to_cpu(image_size)); + lmb_reserve(images->ep, le32_to_cpu(image_size), LMB_NONE); /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/bootz.c b/cmd/bootz.c index 787203f5bd7..99318ff213f 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -56,7 +56,7 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, if (ret != 0) return 1; - lmb_reserve(images->ep, zi_end - zi_start); + lmb_reserve(images->ep, zi_end - zi_start, LMB_NONE); /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/load.c b/cmd/load.c index 20d802502ae..899bb4f598e 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -179,7 +179,7 @@ static ulong load_serial(long offset) { void *dst; - ret = lmb_reserve(store_addr, binlen); + ret = lmb_reserve(store_addr, binlen, LMB_NONE); if (ret) { printf("\nCannot overwrite reserved area (%08lx..%08lx)\n", store_addr, store_addr + binlen); diff --git a/include/lmb.h b/include/lmb.h index 3b911d5d839..3abe24deb56 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -80,16 +80,7 @@ void lmb_add_memory(void); long lmb_add(phys_addr_t base, phys_size_t size); /** - * lmb_reserve() - Reserve a memory region (with no special flags) - * @base: Base address of the memory region - * @size: Size of the memory region - * - * Return: 0 on success, negative error code on failure. - */ -long lmb_reserve(phys_addr_t base, phys_size_t size); - -/** - * lmb_reserve_flags() - Reserve one region with a specific flags bitfield + * lmb_reserve() - Reserve one region with a specific flags bitfield * @base: Base address of the memory region * @size: Size of the memory region * @flags: Flags for the memory region @@ -99,8 +90,7 @@ long lmb_reserve(phys_addr_t base, phys_size_t size); * * %-EEXIST - The region is already added, and flags != LMB_NONE * * %-1 - Failure */ -long lmb_reserve_flags(phys_addr_t base, phys_size_t size, - u32 flags); +long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags); phys_addr_t lmb_alloc(phys_size_t size, ulong align); phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); diff --git a/lib/lmb.c b/lib/lmb.c index edecdb8e9cb..fd0e91981ad 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -553,12 +553,11 @@ static void lmb_reserve_uboot_region(void) if (bank_end > end) bank_end = end - 1; - lmb_reserve_flags(rsv_start, bank_end - rsv_start + 1, - LMB_NOOVERWRITE); + lmb_reserve(rsv_start, bank_end - rsv_start + 1, LMB_NOOVERWRITE); if (gd->flags & GD_FLG_SKIP_RELOC) - lmb_reserve_flags((phys_addr_t)(uintptr_t)_start, - gd->mon_len, LMB_NOOVERWRITE); + lmb_reserve((phys_addr_t)(uintptr_t)_start, + gd->mon_len, LMB_NOOVERWRITE); break; } @@ -584,7 +583,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) if (IS_ENABLED(CONFIG_SPL_STACK_R_ADDR)) { rsv_start = gd->start_addr_sp - 16384; rsv_size = 16384; - lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE); + lmb_reserve(rsv_start, rsv_size, LMB_NOOVERWRITE); } if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) { @@ -592,7 +591,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) rsv_start = (phys_addr_t)(uintptr_t)__bss_start; rsv_size = (phys_addr_t)(uintptr_t)__bss_end - (phys_addr_t)(uintptr_t)__bss_start; - lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE); + lmb_reserve(rsv_start, rsv_size, LMB_NOOVERWRITE); } } @@ -624,11 +623,11 @@ void lmb_add_memory(void) * allocated */ if (bd->bi_dram[i].start >= ram_top) - lmb_reserve_flags(bd->bi_dram[i].start, size, - LMB_NOOVERWRITE); + lmb_reserve(bd->bi_dram[i].start, size, + LMB_NOOVERWRITE); else if (bank_end > ram_top) - lmb_reserve_flags(ram_top, bank_end - ram_top, - LMB_NOOVERWRITE); + lmb_reserve(ram_top, bank_end - ram_top, + LMB_NOOVERWRITE); } } } @@ -669,7 +668,7 @@ long lmb_free(phys_addr_t base, phys_size_t size) return lmb_free_flags(base, size, LMB_NONE); } -long lmb_reserve_flags(phys_addr_t base, phys_size_t size, u32 flags) +long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags) { long ret = 0; struct alist *lmb_rgn_lst = &lmb.used_mem; @@ -681,11 +680,6 @@ long lmb_reserve_flags(phys_addr_t base, phys_size_t size, u32 flags) return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags); } -long lmb_reserve(phys_addr_t base, phys_size_t size) -{ - return lmb_reserve_flags(base, size, LMB_NONE); -} - static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, u32 flags) { @@ -790,7 +784,7 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, lmb_memory[rgn].size, base + size - 1, 1)) { /* ok, reserve the memory */ - if (!lmb_reserve_flags(base, size, flags)) + if (!lmb_reserve(base, size, flags)) return base; } } diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 48c3c966f8f..3c3e862ffa0 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -117,7 +117,7 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, } /* reserve 64KiB somewhere */ - ret = lmb_reserve(alloc_64k_addr, 0x10000); + ret = lmb_reserve(alloc_64k_addr, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); @@ -264,7 +264,7 @@ static int test_bigblock(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(ret, 0); /* reserve 64KiB in the middle of RAM */ - ret = lmb_reserve(alloc_64k_addr, 0x10000); + ret = lmb_reserve(alloc_64k_addr, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); @@ -466,35 +466,35 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts) ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); - ret = lmb_reserve(0x40010000, 0x10000); + ret = lmb_reserve(0x40010000, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); /* allocate overlapping region should return the coalesced count */ - ret = lmb_reserve(0x40011000, 0x10000); + ret = lmb_reserve(0x40011000, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000, 0, 0, 0, 0); /* allocate 3nd region */ - ret = lmb_reserve(0x40030000, 0x10000); + ret = lmb_reserve(0x40030000, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40010000, 0x11000, 0x40030000, 0x10000, 0, 0); /* allocate 2nd region , This should coalesced all region into one */ - ret = lmb_reserve(0x40020000, 0x10000); + ret = lmb_reserve(0x40020000, 0x10000, LMB_NONE); ut_assert(ret >= 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x30000, 0, 0, 0, 0); /* allocate 2nd region, which should be added as first region */ - ret = lmb_reserve(0x40000000, 0x8000); + ret = lmb_reserve(0x40000000, 0x8000, LMB_NONE); ut_assert(ret >= 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x8000, 0x40010000, 0x30000, 0, 0); /* allocate 3rd region, coalesce with first and overlap with second */ - ret = lmb_reserve(0x40008000, 0x10000); + ret = lmb_reserve(0x40008000, 0x10000, LMB_NONE); ut_assert(ret >= 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x40000, 0, 0, 0, 0); @@ -550,11 +550,11 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(ret, 0); /* reserve 3 blocks */ - ret = lmb_reserve(alloc_addr_a, 0x10000); + ret = lmb_reserve(alloc_addr_a, 0x10000, LMB_NONE); ut_asserteq(ret, 0); - ret = lmb_reserve(alloc_addr_b, 0x10000); + ret = lmb_reserve(alloc_addr_b, 0x10000, LMB_NONE); ut_asserteq(ret, 0); - ret = lmb_reserve(alloc_addr_c, 0x10000); + ret = lmb_reserve(alloc_addr_c, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, alloc_addr_a, 0x10000, alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); @@ -680,11 +680,11 @@ static int test_get_unreserved_size(struct unit_test_state *uts, ut_asserteq(ret, 0); /* reserve 3 blocks */ - ret = lmb_reserve(alloc_addr_a, 0x10000); + ret = lmb_reserve(alloc_addr_a, 0x10000, LMB_NONE); ut_asserteq(ret, 0); - ret = lmb_reserve(alloc_addr_b, 0x10000); + ret = lmb_reserve(alloc_addr_b, 0x10000, LMB_NONE); ut_asserteq(ret, 0); - ret = lmb_reserve(alloc_addr_c, 0x10000); + ret = lmb_reserve(alloc_addr_c, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, alloc_addr_a, 0x10000, alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); @@ -747,19 +747,19 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) ut_asserteq(ret, 0); /* reserve, same flag */ - ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40010000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); /* reserve again, same flag */ - ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40010000, 0x10000, LMB_NOMAP); ut_asserteq(ret, -EEXIST); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); /* reserve again, new flag */ - ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NONE); + ret = lmb_reserve(0x40010000, 0x10000, LMB_NONE); ut_asserteq(ret, -1); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); @@ -767,20 +767,20 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) ut_asserteq(lmb_is_nomap(&used[0]), 1); /* merge after */ - ret = lmb_reserve_flags(0x40020000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40020000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x20000, 0, 0, 0, 0); /* merge before */ - ret = lmb_reserve_flags(0x40000000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40000000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x30000, 0, 0, 0, 0); ut_asserteq(lmb_is_nomap(&used[0]), 1); - ret = lmb_reserve_flags(0x40030000, 0x10000, LMB_NONE); + ret = lmb_reserve(0x40030000, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000, 0x40030000, 0x10000, 0, 0); @@ -789,7 +789,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) ut_asserteq(lmb_is_nomap(&used[1]), 0); /* test that old API use LMB_NONE */ - ret = lmb_reserve(0x40040000, 0x10000); + ret = lmb_reserve(0x40040000, 0x10000, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000, 0x40030000, 0x20000, 0, 0); @@ -797,18 +797,18 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) ut_asserteq(lmb_is_nomap(&used[0]), 1); ut_asserteq(lmb_is_nomap(&used[1]), 0); - ret = lmb_reserve_flags(0x40070000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40070000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40070000, 0x10000); - ret = lmb_reserve_flags(0x40050000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40050000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 4, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40050000, 0x10000); /* merge with 2 adjacent regions */ - ret = lmb_reserve_flags(0x40060000, 0x10000, LMB_NOMAP); + ret = lmb_reserve(0x40060000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40050000, 0x30000); -- cgit v1.3.1 From 400c34db8957bbe49b15dcc0310697f829c63e01 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 09:02:33 +0200 Subject: lmb: Rename free_mem to available_mem free_mem is a misnomer. We never update it with the free memory for LMB. Instead, it describes all available memory and is checked against used_mem to decide whether an area is free or not. So let's rename this field to better match its usage. Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Signed-off-by: Ilias Apalodimas --- include/lmb.h | 4 ++-- lib/lmb.c | 34 +++++++++++++++++----------------- test/cmd/bdinfo.c | 2 +- test/lib/lmb.c | 2 +- 4 files changed, 21 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/lmb.h b/include/lmb.h index 3abe24deb56..18030c610ab 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -45,12 +45,12 @@ struct lmb_region { /** * struct lmb - The LMB structure - * @free_mem: List of free memory regions + * @available_mem: List of memory available to LMB * @used_mem: List of used/reserved memory regions * @test: Is structure being used for LMB tests */ struct lmb { - struct alist free_mem; + struct alist available_mem; struct alist used_mem; bool test; }; diff --git a/lib/lmb.c b/lib/lmb.c index fd0e91981ad..da960e422ad 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -350,7 +350,7 @@ int io_lmb_setup(struct lmb *io_lmb) { int ret; - ret = alist_init(&io_lmb->free_mem, sizeof(struct lmb_region), + ret = alist_init(&io_lmb->available_mem, sizeof(struct lmb_region), (uint)LMB_ALIST_INITIAL_SIZE); if (!ret) { log_debug("Unable to initialise the list for LMB free IOVA\n"); @@ -371,13 +371,13 @@ int io_lmb_setup(struct lmb *io_lmb) void io_lmb_teardown(struct lmb *io_lmb) { - alist_uninit(&io_lmb->free_mem); + alist_uninit(&io_lmb->available_mem); alist_uninit(&io_lmb->used_mem); } long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size) { - return lmb_add_region_flags(&io_lmb->free_mem, base, size, LMB_NONE); + return lmb_add_region_flags(&io_lmb->available_mem, base, size, LMB_NONE); } /* derived and simplified from _lmb_alloc_base() */ @@ -387,9 +387,9 @@ phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align) phys_addr_t base = 0; phys_addr_t res_base; struct lmb_region *lmb_used = io_lmb->used_mem.data; - struct lmb_region *lmb_memory = io_lmb->free_mem.data; + struct lmb_region *lmb_memory = io_lmb->available_mem.data; - for (i = io_lmb->free_mem.count - 1; i >= 0; i--) { + for (i = io_lmb->available_mem.count - 1; i >= 0; i--) { phys_addr_t lmbbase = lmb_memory[i].base; phys_size_t lmbsize = lmb_memory[i].size; @@ -515,7 +515,7 @@ static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name) void lmb_dump_all_force(void) { printf("lmb_dump_all:\n"); - lmb_dump_region(&lmb.free_mem, "memory"); + lmb_dump_region(&lmb.available_mem, "memory"); lmb_dump_region(&lmb.used_mem, "reserved"); } @@ -642,7 +642,7 @@ static long lmb_add_region(struct alist *lmb_rgn_lst, phys_addr_t base, long lmb_add(phys_addr_t base, phys_size_t size) { long ret; - struct alist *lmb_rgn_lst = &lmb.free_mem; + struct alist *lmb_rgn_lst = &lmb.available_mem; ret = lmb_add_region(lmb_rgn_lst, base, size); if (ret) @@ -688,9 +688,9 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t base = 0; phys_addr_t res_base; struct lmb_region *lmb_used = lmb.used_mem.data; - struct lmb_region *lmb_memory = lmb.free_mem.data; + struct lmb_region *lmb_memory = lmb.available_mem.data; - for (i = lmb.free_mem.count - 1; i >= 0; i--) { + for (i = lmb.available_mem.count - 1; i >= 0; i--) { phys_addr_t lmbbase = lmb_memory[i].base; phys_size_t lmbsize = lmb_memory[i].size; @@ -771,10 +771,10 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) { long rgn; - struct lmb_region *lmb_memory = lmb.free_mem.data; + struct lmb_region *lmb_memory = lmb.available_mem.data; /* Check if the requested address is in one of the memory regions */ - rgn = lmb_overlaps_region(&lmb.free_mem, base, size); + rgn = lmb_overlaps_region(&lmb.available_mem, base, size); if (rgn >= 0) { /* * Check if the requested end address is in the same memory @@ -813,10 +813,10 @@ phys_size_t lmb_get_free_size(phys_addr_t addr) int i; long rgn; struct lmb_region *lmb_used = lmb.used_mem.data; - struct lmb_region *lmb_memory = lmb.free_mem.data; + struct lmb_region *lmb_memory = lmb.available_mem.data; /* check if the requested address is in the memory regions */ - rgn = lmb_overlaps_region(&lmb.free_mem, addr, 1); + rgn = lmb_overlaps_region(&lmb.available_mem, addr, 1); if (rgn >= 0) { for (i = 0; i < lmb.used_mem.count; i++) { if (addr < lmb_used[i].base) { @@ -830,8 +830,8 @@ phys_size_t lmb_get_free_size(phys_addr_t addr) } } /* if we come here: no reserved ranges above requested addr */ - return lmb_memory[lmb.free_mem.count - 1].base + - lmb_memory[lmb.free_mem.count - 1].size - addr; + return lmb_memory[lmb.available_mem.count - 1].base + + lmb_memory[lmb.available_mem.count - 1].size - addr; } return 0; } @@ -854,7 +854,7 @@ static int lmb_setup(bool test) { bool ret; - ret = alist_init(&lmb.free_mem, sizeof(struct lmb_region), + ret = alist_init(&lmb.available_mem, sizeof(struct lmb_region), (uint)LMB_ALIST_INITIAL_SIZE); if (!ret) { log_debug("Unable to initialise the list for LMB free memory\n"); @@ -914,7 +914,7 @@ int lmb_push(struct lmb *store) void lmb_pop(struct lmb *store) { - alist_uninit(&lmb.free_mem); + alist_uninit(&lmb.available_mem); alist_uninit(&lmb.used_mem); lmb = *store; } diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 014391b38ac..76429485708 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -131,7 +131,7 @@ static int lmb_test_dump_all(struct unit_test_state *uts) struct lmb *lmb = lmb_get(); ut_assert_nextline("lmb_dump_all:"); - ut_assertok(lmb_test_dump_region(uts, &lmb->free_mem, "memory")); + ut_assertok(lmb_test_dump_region(uts, &lmb->available_mem, "memory")); ut_assertok(lmb_test_dump_region(uts, &lmb->used_mem, "reserved")); return 0; diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 3c3e862ffa0..6e870274fed 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -65,7 +65,7 @@ static int setup_lmb_test(struct unit_test_state *uts, struct lmb *store, ut_assertok(lmb_push(store)); lmb = lmb_get(); - *mem_lstp = &lmb->free_mem; + *mem_lstp = &lmb->available_mem; *used_lstp = &lmb->used_mem; return 0; -- cgit v1.3.1 From 15e0c5e390ffac7682193b7e1a615898b569deb1 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 09:02:35 +0200 Subject: lmb: Remove lmb_alloc_addr_flags() lmb_alloc_addr() is just calling lmb_alloc_addr_flags() with LMB_NONE There's not much we gain from this abstraction, so let's remove the latter, add a flags argument to lmb_alloc_addr() and make the code a bit easier to follow. Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Signed-off-by: Ilias Apalodimas --- fs/fs.c | 2 +- include/lmb.h | 10 ++++------ lib/efi_loader/efi_memory.c | 2 +- lib/lmb.c | 15 ++------------- test/lib/lmb.c | 34 +++++++++++++++++----------------- 5 files changed, 25 insertions(+), 38 deletions(-) (limited to 'include') diff --git a/fs/fs.c b/fs/fs.c index 21a23efd932..99ddcc5e37b 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -554,7 +554,7 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, lmb_dump_all(); - if (lmb_alloc_addr(addr, read_len) == addr) + if (lmb_alloc_addr(addr, read_len, LMB_NONE) == addr) return 0; log_err("** Reading file would overwrite reserved memory **\n"); diff --git a/include/lmb.h b/include/lmb.h index 18030c610ab..e38af036a0d 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -94,7 +94,6 @@ long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags); phys_addr_t lmb_alloc(phys_size_t size, ulong align); phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); -phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size); phys_size_t lmb_get_free_size(phys_addr_t addr); /** @@ -115,8 +114,8 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, phys_addr_t max_addr, uint flags); /** - * lmb_alloc_addr_flags() - Allocate specified memory address with specified - * attributes + * lmb_alloc_addr() - Allocate specified memory address with specified attributes + * * @base: Base Address requested * @size: Size of the region requested * @flags: Memory region attributes to be set @@ -127,8 +126,7 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, * * Return: Base address on success, 0 on error. */ -phys_addr_t lmb_alloc_addr_flags(phys_addr_t base, phys_size_t size, - uint flags); +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, uint flags); /** * lmb_is_reserved_flags() - Test if address is in reserved region with flag @@ -166,7 +164,7 @@ void lmb_pop(struct lmb *store); static inline int lmb_read_check(phys_addr_t addr, phys_size_t len) { - return lmb_alloc_addr(addr, len) == addr ? 0 : -1; + return lmb_alloc_addr(addr, len, LMB_NONE) == addr ? 0 : -1; } /** diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index edd7da7d8c6..34e2b9e18ef 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -490,7 +490,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, return EFI_NOT_FOUND; addr = map_to_sysmem((void *)(uintptr_t)*memory); - addr = (u64)lmb_alloc_addr_flags(addr, len, flags); + addr = (u64)lmb_alloc_addr(addr, len, flags); if (!addr) return EFI_NOT_FOUND; break; diff --git a/lib/lmb.c b/lib/lmb.c index 659581f13f2..ffad7ec12eb 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -761,8 +761,7 @@ phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, return alloc; } -static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, - u32 flags) +static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) { long rgn; struct lmb_region *lmb_memory = lmb.available_mem.data; @@ -786,17 +785,7 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, return 0; } -/* - * Try to allocate a specific address range: must be in defined memory but not - * reserved - */ -phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size) -{ - return _lmb_alloc_addr(base, size, LMB_NONE); -} - -phys_addr_t lmb_alloc_addr_flags(phys_addr_t base, phys_size_t size, - uint flags) +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, uint flags) { return _lmb_alloc_addr(base, size, flags); } diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 6e870274fed..971614fd831 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -530,21 +530,21 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(ret, 0); /* Try to allocate a page twice */ - b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(b, alloc_addr_a); - b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(b, 0); - b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(b, alloc_addr_a); - b = lmb_alloc_addr_flags(alloc_addr_a, 0x2000, LMB_NONE); + b = lmb_alloc_addr(alloc_addr_a, 0x2000, LMB_NONE); ut_asserteq(b, alloc_addr_a); ret = lmb_free(alloc_addr_a, 0x2000); ut_asserteq(ret, 0); - b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(b, alloc_addr_a); - b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(b, 0); - b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(b, 0); ret = lmb_free(alloc_addr_a, 0x1000); ut_asserteq(ret, 0); @@ -560,22 +560,22 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); /* allocate blocks */ - a = lmb_alloc_addr(ram, alloc_addr_a - ram); + a = lmb_alloc_addr(ram, alloc_addr_a - ram, LMB_NONE); ut_asserteq(a, ram); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, ram, 0x8010000, alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); b = lmb_alloc_addr(alloc_addr_a + 0x10000, - alloc_addr_b - alloc_addr_a - 0x10000); + alloc_addr_b - alloc_addr_a - 0x10000, LMB_NONE); ut_asserteq(b, alloc_addr_a + 0x10000); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x10010000, alloc_addr_c, 0x10000, 0, 0); c = lmb_alloc_addr(alloc_addr_b + 0x10000, - alloc_addr_c - alloc_addr_b - 0x10000); + alloc_addr_c - alloc_addr_b - 0x10000, LMB_NONE); ut_asserteq(c, alloc_addr_b + 0x10000); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); d = lmb_alloc_addr(alloc_addr_c + 0x10000, - ram_end - alloc_addr_c - 0x10000); + ram_end - alloc_addr_c - 0x10000, LMB_NONE); ut_asserteq(d, alloc_addr_c + 0x10000); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size, 0, 0, 0, 0); @@ -591,7 +591,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) /* allocate at 3 points in free range */ - d = lmb_alloc_addr(ram_end - 4, 4); + d = lmb_alloc_addr(ram_end - 4, 4, LMB_NONE); ut_asserteq(d, ram_end - 4); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000, d, 4, 0, 0); @@ -600,7 +600,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); - d = lmb_alloc_addr(ram_end - 128, 4); + d = lmb_alloc_addr(ram_end - 128, 4, LMB_NONE); ut_asserteq(d, ram_end - 128); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000, d, 4, 0, 0); @@ -609,7 +609,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); - d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4); + d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4, LMB_NONE); ut_asserteq(d, alloc_addr_c + 0x10000); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004, 0, 0, 0, 0); @@ -624,18 +624,18 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000, 0x10010000, 0, 0, 0, 0); - d = lmb_alloc_addr(ram, 4); + d = lmb_alloc_addr(ram, 4, LMB_NONE); ut_asserteq(d, ram); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, d, 4, ram + 0x8000000, 0x10010000, 0, 0); /* check that allocating outside memory fails */ if (ram_end != 0) { - ret = lmb_alloc_addr(ram_end, 1); + ret = lmb_alloc_addr(ram_end, 1, LMB_NONE); ut_asserteq(ret, 0); } if (ram != 0) { - ret = lmb_alloc_addr(ram - 1, 1); + ret = lmb_alloc_addr(ram - 1, 1, LMB_NONE); ut_asserteq(ret, 0); } -- cgit v1.3.1 From 3075708017dc2d1b735ed7c9556da6ff5070f14f Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 09:02:36 +0200 Subject: lmb: Remove lmb_alloc_base_flags() lmb_alloc_base() is just calling lmb_alloc_base_flags() with LMB_NONE. There's not much we gain from this abstraction, so let's remove the former add the flags argument to lmb_alloc_base() and make the code a bit easier to follow. Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Signed-off-by: Ilias Apalodimas --- boot/image-board.c | 18 +++++++++++------- boot/image-fdt.c | 5 +++-- include/lmb.h | 7 +++---- lib/efi_loader/efi_memory.c | 4 ++-- lib/lmb.c | 19 +++---------------- test/lib/lmb.c | 8 ++++---- 6 files changed, 26 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/boot/image-board.c b/boot/image-board.c index 070ada00718..4e86a9a2271 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -565,9 +565,11 @@ int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, lmb_reserve(rd_data, rd_len, LMB_NONE); } else { if (initrd_high) - *initrd_start = (ulong)lmb_alloc_base(rd_len, - 0x1000, - initrd_high); + *initrd_start = + (ulong)lmb_alloc_base(rd_len, + 0x1000, + initrd_high, + LMB_NONE); else *initrd_start = (ulong)lmb_alloc(rd_len, 0x1000); @@ -839,7 +841,8 @@ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) barg = IF_ENABLED_INT(CONFIG_SYS_BOOT_GET_CMDLINE, CONFIG_SYS_BARGSIZE); cmdline = (char *)(ulong)lmb_alloc_base(barg, 0xf, - env_get_bootm_mapsize() + env_get_bootm_low()); + env_get_bootm_mapsize() + env_get_bootm_low(), + LMB_NONE); if (!cmdline) return -1; @@ -872,9 +875,10 @@ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) int boot_get_kbd(struct bd_info **kbd) { *kbd = (struct bd_info *)(ulong)lmb_alloc_base(sizeof(struct bd_info), - 0xf, - env_get_bootm_mapsize() + - env_get_bootm_low()); + 0xf, + env_get_bootm_mapsize() + + env_get_bootm_low(), + LMB_NONE); if (!*kbd) return -1; diff --git a/boot/image-fdt.c b/boot/image-fdt.c index d717f669072..9d1598b1a93 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -187,7 +187,8 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) lmb_reserve(map_to_sysmem(of_start), of_len, LMB_NONE); disable_relocation = 1; } else if (desired_addr) { - addr = lmb_alloc_base(of_len, 0x1000, desired_addr); + addr = lmb_alloc_base(of_len, 0x1000, desired_addr, + LMB_NONE); of_start = map_sysmem(addr, of_len); if (of_start == NULL) { puts("Failed using fdt_high value for Device Tree"); @@ -216,7 +217,7 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) * for LMB allocation. */ usable = min(start + size, low + mapsize); - addr = lmb_alloc_base(of_len, 0x1000, usable); + addr = lmb_alloc_base(of_len, 0x1000, usable, LMB_NONE); of_start = map_sysmem(addr, of_len); /* Allocation succeeded, use this block. */ if (of_start != NULL) diff --git a/include/lmb.h b/include/lmb.h index e38af036a0d..a0e666a1f7c 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -93,11 +93,10 @@ long lmb_add(phys_addr_t base, phys_size_t size); long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags); phys_addr_t lmb_alloc(phys_size_t size, ulong align); -phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); phys_size_t lmb_get_free_size(phys_addr_t addr); /** - * lmb_alloc_base_flags() - Allocate specified memory region with specified + * lmb_alloc_base() - Allocate specified memory region with specified * attributes * @size: Size of the region requested * @align: Alignment of the memory region requested @@ -110,8 +109,8 @@ phys_size_t lmb_get_free_size(phys_addr_t addr); * * Return: Base address on success, 0 on error. */ -phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, - phys_addr_t max_addr, uint flags); +phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, + uint flags); /** * lmb_alloc_addr() - Allocate specified memory address with specified attributes diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 34e2b9e18ef..1212772471e 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -472,7 +472,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, switch (type) { case EFI_ALLOCATE_ANY_PAGES: /* Any page */ - addr = (u64)lmb_alloc_base_flags(len, EFI_PAGE_SIZE, + addr = (u64)lmb_alloc_base(len, EFI_PAGE_SIZE, LMB_ALLOC_ANYWHERE, flags); if (!addr) return EFI_OUT_OF_RESOURCES; @@ -480,7 +480,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, case EFI_ALLOCATE_MAX_ADDRESS: /* Max address */ addr = map_to_sysmem((void *)(uintptr_t)*memory); - addr = (u64)lmb_alloc_base_flags(len, EFI_PAGE_SIZE, addr, + addr = (u64)lmb_alloc_base(len, EFI_PAGE_SIZE, addr, flags); if (!addr) return EFI_OUT_OF_RESOURCES; diff --git a/lib/lmb.c b/lib/lmb.c index ffad7ec12eb..bdaaa634abd 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -731,24 +731,11 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t lmb_alloc(phys_size_t size, ulong align) { - return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE); + return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, LMB_NONE); } -phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr) -{ - phys_addr_t alloc; - - alloc = _lmb_alloc_base(size, align, max_addr, LMB_NONE); - - if (alloc == 0) - printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n", - (ulong)size, (ulong)max_addr); - - return alloc; -} - -phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align, - phys_addr_t max_addr, uint flags) +phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, + uint flags) { phys_addr_t alloc; diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 971614fd831..fcb5f1af532 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -128,7 +128,7 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr, 0x10000, ram_end - 4, 4, 0, 0); /* alloc below end of reserved region -> below reserved region */ - b = lmb_alloc_base(4, 1, alloc_64k_end); + b = lmb_alloc_base(4, 1, alloc_64k_end, LMB_NONE); ut_asserteq(b, alloc_64k_addr - 4); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 4, 0x10000 + 4, ram_end - 4, 4, 0, 0); @@ -138,7 +138,7 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, ut_asserteq(c, ram_end - 8); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 4, 0x10000 + 4, ram_end - 8, 8, 0, 0); - d = lmb_alloc_base(4, 1, alloc_64k_end); + d = lmb_alloc_base(4, 1, alloc_64k_end, LMB_NONE); ut_asserteq(d, alloc_64k_addr - 8); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0); @@ -163,7 +163,7 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, ram_end - 8, 4); /* allocate again to ensure we get the same address */ - b2 = lmb_alloc_base(4, 1, alloc_64k_end); + b2 = lmb_alloc_base(4, 1, alloc_64k_end, LMB_NONE); ut_asserteq(b, b2); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); @@ -363,7 +363,7 @@ static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram, ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); /* allocate a block with base*/ - b = lmb_alloc_base(alloc_size, align, ram_end); + b = lmb_alloc_base(alloc_size, align, ram_end, LMB_NONE); ut_assert(a == b); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + ram_size - alloc_size_aligned, -- cgit v1.3.1 From 1a25191bc1381f320a359a5dc9c835dde4658175 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 09:02:37 +0200 Subject: lmb: Rename _lmb_alloc_addr() to lmb_alloc_addr_flags() lmb_alloc_addr_flags() is a wrapper for _lmb_alloc_addr() and it's the only function using it. Rename _lmb_alloc_addr() to lmb_alloc_addr_flags() and remove the wrapper. Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Signed-off-by: Ilias Apalodimas --- include/lmb.h | 2 +- lib/lmb.c | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/lmb.h b/include/lmb.h index a0e666a1f7c..d9d7435a431 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -125,7 +125,7 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, * * Return: Base address on success, 0 on error. */ -phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, uint flags); +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags); /** * lmb_is_reserved_flags() - Test if address is in reserved region with flag diff --git a/lib/lmb.c b/lib/lmb.c index bdaaa634abd..7ca44591e1d 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -748,7 +748,7 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, return alloc; } -static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) { long rgn; struct lmb_region *lmb_memory = lmb.available_mem.data; @@ -772,11 +772,6 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags return 0; } -phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, uint flags) -{ - return _lmb_alloc_addr(base, size, flags); -} - /* Return number of bytes from a given address that are free */ phys_size_t lmb_get_free_size(phys_addr_t addr) { -- cgit v1.3.1 From c3e425ead43b9d6c387673f0c09100535584b038 Mon Sep 17 00:00:00 2001 From: "J. Neuschäfer" Date: Thu, 12 Dec 2024 18:05:47 +0100 Subject: powerpc: Introduce and enforce assembler checks on GPR usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC general-purpose registers are historically specified as plain numbers (0-31), which makes them hard to distinguish from immediates. For this reason, include/ppc_asm.tmpl defines aliases named r0-r31. This can still lead to uncaught mistakes if a register is used in place of a number. Instead of (e.g.) 5 use %r5, which will result in an assembler warning if used as a number. Turn these warnings into errors by passing `--fatal-warnings` to the assembler. I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig (MPC85xx) that this patch results in the same machine code. Signed-off-by: J. Neuschäfer --- arch/powerpc/config.mk | 2 +- include/ppc_asm.tmpl | 66 +++++++++++++++++++++++++------------------------- 2 files changed, 34 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index dd0124cace1..6e30df6504e 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -8,7 +8,7 @@ LDFLAGS_FINAL += --bss-plt PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ -fdata-sections -mcall-linux -PF_CPPFLAGS_POWERPC := $(call cc-option,-fno-ira-hoist-pressure,) +PF_CPPFLAGS_POWERPC := $(call cc-option,-fno-ira-hoist-pressure,) $(call cc-option,-Xassembler --fatal-warnings,) PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 $(PF_CPPFLAGS_POWERPC) KBUILD_LDFLAGS += -m32 -melf32ppclinux diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index db7b1668d99..0b858c41e32 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -45,40 +45,40 @@ /*************************************************************************** - * Register names + * Register names. The %r1 offers some error-checking in GNU as. */ -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 +#define r0 %r0 +#define r1 %r1 +#define r2 %r2 +#define r3 %r3 +#define r4 %r4 +#define r5 %r5 +#define r6 %r6 +#define r7 %r7 +#define r8 %r8 +#define r9 %r9 +#define r10 %r10 +#define r11 %r11 +#define r12 %r12 +#define r13 %r13 +#define r14 %r14 +#define r15 %r15 +#define r16 %r16 +#define r17 %r17 +#define r18 %r18 +#define r19 %r19 +#define r20 %r20 +#define r21 %r21 +#define r22 %r22 +#define r23 %r23 +#define r24 %r24 +#define r25 %r25 +#define r26 %r26 +#define r27 %r27 +#define r28 %r28 +#define r29 %r29 +#define r30 %r30 +#define r31 %r31 #if defined(CONFIG_MPC8xx) -- cgit v1.3.1 From 623f5cf517ae0e0f6f7132ac6411ea0a8dd9b3f7 Mon Sep 17 00:00:00 2001 From: Evgeny Bachinin Date: Wed, 11 Dec 2024 01:39:57 +0300 Subject: fdtdec: encapsulate dtb_dt_embedded() within Patch keeps the access to dtb_dt_embedded() within fdtdec API, by means of new API function introduction. This new function is a common place for updating appropriate global_data fields for OF_EMBED case. Also, the consequence of the patch is movement of '___dtb_dt_*begin' symbols' declaration from header file, because nobody used symbols outside the lib/fdtdec.c. Signed-off-by: Evgeny Bachinin Suggested-by: Simon Glass Reviewed-by: Simon Glass --- common/board_r.c | 4 ++-- include/fdtdec.h | 24 +++++++----------------- lib/fdtdec.c | 26 ++++++++++++++++++++++++-- 3 files changed, 33 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/common/board_r.c b/common/board_r.c index 88dc756b2a5..3c6a4c1f5df 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -155,11 +155,11 @@ static int initr_reloc_global_data(void) /* * For CONFIG_OF_EMBED case the FDT is embedded into ELF, available by - * __dtb_dt_begin. After U-boot ELF self-relocation to RAM top address + * __dtb_dt_begin. After U-Boot ELF self-relocation to RAM top address * it is worth to update fdt_blob in global_data */ if (IS_ENABLED(CONFIG_OF_EMBED)) - gd->fdt_blob = dtb_dt_embedded(); + fdtdec_setup_embed(); #ifdef CONFIG_EFI_LOADER /* diff --git a/include/fdtdec.h b/include/fdtdec.h index 555c9520379..88eeb512978 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -136,23 +136,6 @@ struct fdt_pci_addr { u32 phys_lo; }; -extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ -extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ - -/* Get a pointer to the embedded devicetree, if there is one, else NULL */ -static inline u8 *dtb_dt_embedded(void) -{ -#ifdef CONFIG_OF_EMBED -# ifdef CONFIG_XPL_BUILD - return __dtb_dt_spl_begin; -# else - return __dtb_dt_begin; -# endif -#else - return NULL; -#endif -} - /** * Compute the size of a resource. * @@ -1155,6 +1138,13 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, const char *name, const char **compatibles, unsigned int count, unsigned long flags); +/** + * fdtdec_setup_embed - pick up embedded DTS + * + * Should be invoked under CONFIG_OF_EMBED guard. + */ +void fdtdec_setup_embed(void); + /** * Set up the device tree ready for use */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index b0655988029..9cb94a15844 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -93,6 +93,23 @@ static const char *const fdt_src_name[] = { [FDTSRC_BLOBLIST] = "bloblist", }; +extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ +extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ + +/* Get a pointer to the embedded devicetree, if there is one, else NULL */ +static u8 *dtb_dt_embedded(void) +{ +#ifdef CONFIG_OF_EMBED +# ifdef CONFIG_XPL_BUILD + return __dtb_dt_spl_begin; +# else + return __dtb_dt_begin; +# endif +#else + return NULL; +#endif +} + const char *fdtdec_get_srcname(void) { return fdt_src_name[gd->fdt_src]; @@ -1664,6 +1681,12 @@ static void setup_multi_dtb_fit(void) } } +void fdtdec_setup_embed(void) +{ + gd->fdt_blob = dtb_dt_embedded(); + gd->fdt_src = FDTSRC_EMBED; +} + int fdtdec_setup(void) { int ret = -ENOENT; @@ -1699,8 +1722,7 @@ int fdtdec_setup(void) gd->fdt_blob = fdt_find_separate(); gd->fdt_src = FDTSRC_SEPARATE; } else { /* embed dtb in ELF file for testing / development */ - gd->fdt_blob = dtb_dt_embedded(); - gd->fdt_src = FDTSRC_EMBED; + fdtdec_setup_embed(); } } -- cgit v1.3.1 From 99145eec2dca317da6b48d0f8fdd602001f87e61 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 16 Dec 2024 18:07:35 +0000 Subject: x86: select CONFIG_64BIT for X86_64 Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to static analysis tools. Introduce CONFIG_SPL_64BIT and select it for architectures other than x86 with 64 bit builds. Do not select it for x86 builds as x86 uses a 32 bit SPL. Ensure that when limits are set they use CONFIG_64BIT for U-Boot proper and CONFIG_SPL_64BIT for SPL. This is to allow for the 32 bit SPL build used by x86. Signed-off-by: Dan Carpenter Signed-off-by: Andrew Goodbody --- arch/Kconfig | 8 ++++++++ arch/arm/Kconfig | 1 + arch/mips/Kconfig | 4 ++++ arch/riscv/Kconfig | 1 + arch/sandbox/Kconfig | 1 + arch/x86/Kconfig | 1 + common/bloblist.c | 13 ++++++++----- include/limits.h | 3 ++- 8 files changed, 26 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/Kconfig b/arch/Kconfig index 6258788f53f..bb2e7bedd10 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -37,6 +37,14 @@ config 32BIT config 64BIT bool + help + Indicates that U-Boot proper will be built for a 64 bit + architecture. + +config SPL_64BIT + bool + help + Indicates that SPL will be built for a 64 bit architecture. config SYS_CACHELINE_SIZE int diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7282c4123b0..055762b0b9d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -7,6 +7,7 @@ config SYS_ARCH config ARM64 bool select 64BIT + select SPL_64BIT if SPL select PHYS_64BIT select SYS_CACHE_SHIFT_6 imply SPL_SEPARATE_BSS diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 38577af43d0..7ea439e857c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -211,6 +211,7 @@ config CPU_MIPS64_R1 bool "MIPS64 Release 1" depends on SUPPORTS_CPU_MIPS64_R1 select 64BIT + select SPL_64BIT if SPL help Choose this option to build a kernel for release 1 through 5 of the MIPS64 architecture. @@ -219,6 +220,7 @@ config CPU_MIPS64_R2 bool "MIPS64 Release 2" depends on SUPPORTS_CPU_MIPS64_R2 select 64BIT + select SPL_64BIT if SPL help Choose this option to build a kernel for release 2 through 5 of the MIPS64 architecture. @@ -227,6 +229,7 @@ config CPU_MIPS64_R6 bool "MIPS64 Release 6" depends on SUPPORTS_CPU_MIPS64_R6 select 64BIT + select SPL_64BIT if SPL help Choose this option to build a kernel for release 6 or later of the MIPS64 architecture. @@ -235,6 +238,7 @@ config CPU_MIPS64_OCTEON bool "Marvell Octeon series of CPUs" depends on SUPPORTS_CPU_MIPS64_OCTEON select 64BIT + select SPL_64BIT if SPL help Choose this option for Marvell Octeon CPUs. These CPUs are between MIPS64 R5 and R6 with other extensions. diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 043d963f634..abb7a984c48 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -120,6 +120,7 @@ config ARCH_RV32I config ARCH_RV64I bool "RV64I" select 64BIT + select SPL_64BIT if SPL select PHYS_64BIT help Choose this option to target the RV64I base integer instruction set. diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index db29ca14bdf..4c169034d9a 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -47,6 +47,7 @@ config HOST_32BIT config HOST_64BIT def_bool $(cc-define,_LP64) select 64BIT + select SPL_64BIT if SPL config HOST_HAS_SDL def_bool $(success,sdl2-config --version) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 23a1e21b29e..006a59d6fa6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -44,6 +44,7 @@ endchoice config X86_64 bool + select 64BIT config SPL_X86_64 bool diff --git a/common/bloblist.c b/common/bloblist.c index ec6ff7a5a93..110bb9dc44a 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -576,14 +576,17 @@ int bloblist_maybe_init(void) int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig) { - ulong version = BLOBLIST_REGCONV_VER; + u64 version = BLOBLIST_REGCONV_VER; ulong sigval; - sigval = (IS_ENABLED(CONFIG_64BIT)) ? - ((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_64) - 1)) | - ((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_64)) : - ((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_32) - 1)) | + if ((IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_SPL_BUILD)) || + (IS_ENABLED(CONFIG_SPL_64BIT) && IS_ENABLED(CONFIG_SPL_BUILD))) { + sigval = ((BLOBLIST_MAGIC & ((1ULL << BLOBLIST_REGCONV_SHIFT_64) - 1)) | + ((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_64)); + } else { + sigval = ((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_32) - 1)) | ((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_32)); + } if (rzero || rsig != sigval || rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) { diff --git a/include/limits.h b/include/limits.h index 4700cc7a59f..1d0bbf69be7 100644 --- a/include/limits.h +++ b/include/limits.h @@ -9,7 +9,8 @@ #define UINT32_MAX 0xffffffffU #define UINT64_MAX 0xffffffffffffffffULL -#ifdef CONFIG_64BIT +#if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD)) #define UINTPTR_MAX UINT64_MAX #else #define UINTPTR_MAX UINT32_MAX -- cgit v1.3.1 From 60a684e0a9f341d96c30ce0e1e472d7a203c85aa Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Fri, 13 Dec 2024 13:45:36 +0100 Subject: trace: add support for 'trace wipe' Implement a 'trace wipe' command to delete the currently accumulated trace data. This comes handy when someone needs to trace a particular command. For example: => trace pause; trace wipe => trace resume; dhcp; trace pause => trace stats => trace calls 0x02100000 0x10000000 => tftpput $profbase $profoffset 192.168.0.16:trace.bin Signed-off-by: Jerome Forissier Reviewed-by: Ilias Apalodimas --- cmd/trace.c | 5 +++++ include/trace.h | 2 ++ lib/trace.c | 47 +++++++++++++++++++++++++++++++++-------------- 3 files changed, 40 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/cmd/trace.c b/cmd/trace.c index 937e6a682ad..d36008720db 100644 --- a/cmd/trace.c +++ b/cmd/trace.c @@ -100,6 +100,10 @@ int do_trace(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) case 's': trace_print_stats(); break; + case 'w': + if (trace_wipe()) + return CMD_RET_FAILURE; + break; default: return CMD_RET_USAGE; } @@ -113,6 +117,7 @@ U_BOOT_CMD( "stats - display tracing statistics\n" "trace pause - pause tracing\n" "trace resume - resume tracing\n" + "trace wipe - wipe traces\n" "trace funclist [ ] - dump function list into buffer\n" "trace calls [ ] " "- dump function call trace into buffer" diff --git a/include/trace.h b/include/trace.h index 763d6d1255a..782eaae2fc2 100644 --- a/include/trace.h +++ b/include/trace.h @@ -100,6 +100,8 @@ void trace_set_enabled(int enabled); int trace_early_init(void); +int trace_clear(void); + /** * Init the trace system * diff --git a/lib/trace.c b/lib/trace.c index cabbe47b58a..def9f912c92 100644 --- a/lib/trace.c +++ b/lib/trace.c @@ -351,14 +351,8 @@ static int get_func_count(void) return gd->mon_len / FUNC_SITE_SIZE; } -/** - * trace_init() - initialize the tracing system and enable it - * - * @buff: Pointer to trace buffer - * @buff_size: Size of trace buffer - * Return: 0 if ok - */ -int notrace trace_init(void *buff, size_t buff_size) +static int notrace trace_init_(void *buff, size_t buff_size, bool copy_early, + bool enable) { int func_count = get_func_count(); size_t needed; @@ -368,7 +362,7 @@ int notrace trace_init(void *buff, size_t buff_size) return func_count; trace_save_gd(); - if (!was_disabled) { + if (copy_early) { #ifdef CONFIG_TRACE_EARLY ulong used, count; char *end; @@ -394,9 +388,6 @@ int notrace trace_init(void *buff, size_t buff_size) } puts("\n"); memcpy(buff, hdr, used); -#else - puts("trace: already enabled\n"); - return -EALREADY; #endif } hdr = (struct trace_hdr *)buff; @@ -419,13 +410,41 @@ int notrace trace_init(void *buff, size_t buff_size) hdr->ftrace_size = (buff_size - needed) / sizeof(*hdr->ftrace); hdr->depth_limit = CONFIG_TRACE_CALL_DEPTH_LIMIT; - puts("trace: enabled\n"); - trace_enabled = 1; + printf("trace: initialized, %senabled\n", enable ? "" : "not "); + trace_enabled = enable; trace_inited = 1; return 0; } +/** + * trace_init() - initialize the tracing system and enable it + * + * @buff: Pointer to trace buffer + * @buff_size: Size of trace buffer + * Return: 0 if ok + */ +int notrace trace_init(void *buff, size_t buff_size) +{ + /* If traces are enabled already, we may have early traces to copy */ + return trace_init_(buff, buff_size, trace_enabled, true); +} + +/** + * trace_clear() - clear accumulated traced data + * + * May be called with tracing enabled or disabled. + */ +int notrace trace_clear(void) +{ + bool was_enabled = trace_enabled; + + if (trace_enabled) + trace_enabled = 0; + return trace_init_(gd->trace_buff, CONFIG_TRACE_BUFFER_SIZE, + false, was_enabled); +} + #ifdef CONFIG_TRACE_EARLY /** * trace_early_init() - initialize the tracing system for early tracing -- cgit v1.3.1 From dc5ff7443ee58f091e276e30ad84ea6006ee5af6 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 19 Nov 2024 11:09:07 +0100 Subject: net: correct the description of ip_to_string() The output of ip_to_string() is a string. Signed-off-by: Heinrich Schuchardt --- include/net-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index 8fc1bac47f5..29d31f37263 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -427,7 +427,7 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr); struct in_addr string_to_ip(const char *s); /** - * ip_to_string() - Convert a string to ip address + * ip_to_string() - Convert an IPv4 address to a string * * Implemented in lib/net_utils.c (built unconditionally) * -- cgit v1.3.1