From c46305a829af36db255caa8fb5d28f5a6529978c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 20 Oct 2017 12:17:03 -0200 Subject: imx: Fix regression with CONFIG_DM_MMC=y MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When CONFIG_DM_MMC=y, CONFIG_BLK should be selected, otherwise the SD/eMMC card cannot be used. Also, select CONFIG_DM_USB=y when CONFIG_USB=y to avoid build failure. Tested on mx6slevk, mx7dsabresd and mx6ullevk. Signed-off-by: Fabio Estevam Reviewed-by: Jaehoon Chung Tested-by: Adam Ford Tested-by: Sébastien Szymanski Tested-by: Jagan Teki Reviewed-by: Jagan Teki --- include/configs/opos6uldev.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index d01898465bc..04fc602ce44 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -17,6 +17,7 @@ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_GPIO #undef CONFIG_DM_MMC +#undef CONFIG_BLK #define CONFIG_MXC_UART_BASE UART1_BASE #endif -- cgit v1.3.1 From c0f432c377805b57d67c09b0f7374d5c6510b09c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 17 Oct 2017 13:59:19 +0200 Subject: configs: vf610: increase maximum size and enforce correct limit On Vybrid SoCs U-Boot gets loaded into GFX SRAM which is 512KiB. Currently 32KiB is reserved for the IMX header. However, this is not reflected in the size limit. In v2017.11-rc2 the actual size limit (512KiB-32KiB) has been reached for Colibri VF61, which lead to a successful build of U-Boot but not a working binary. The IMX header is much smaller than 32KiB, typically around 1KiB. Decrease the reserved size to 4KiB and specify the correct U-Boot size limit. Apply this new base address and limit for all Vybrid based boards. Signed-off-by: Stefan Agner --- include/configs/colibri_vf.h | 4 ++-- include/configs/pcm052.h | 4 ++-- include/configs/vf610twr.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 8166aa4afb1..bf3bbffe248 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -75,8 +75,8 @@ #define CONFIG_FDTADDR 0x84000000 /* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_SYS_TEXT_BASE 0x3f408000 -#define CONFIG_BOARD_SIZE_LIMIT 524288 +#define CONFIG_SYS_TEXT_BASE 0x3f401000 +#define CONFIG_BOARD_SIZE_LIMIT 520192 #define SD_BOOTCMD \ "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 8144a83db25..060928bd30d 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -89,8 +89,8 @@ #define CONFIG_LOADADDR 0x82000000 /* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_SYS_TEXT_BASE 0x3f408000 -#define CONFIG_BOARD_SIZE_LIMIT 524288 +#define CONFIG_SYS_TEXT_BASE 0x3f401000 +#define CONFIG_BOARD_SIZE_LIMIT 520192 /* if no target-specific extra environment settings were defined by the target, define an empty one */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 3430f27c40d..ddfcd6f6184 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -79,8 +79,8 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_SYS_TEXT_BASE 0x3f408000 -#define CONFIG_BOARD_SIZE_LIMIT 524288 +#define CONFIG_SYS_TEXT_BASE 0x3f401000 +#define CONFIG_BOARD_SIZE_LIMIT 520192 /* * We do have 128MB of memory on the Vybrid Tower board. Leave the last -- cgit v1.3.1 From e1f0715f64769920c1c3ec73f8f3bd9889a279ce Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 14 Oct 2017 09:17:54 -0300 Subject: wandboard: Add support for the MX6QP variant Add support for the latest MX6QP wandboard variant. Based on Richard Hu's work from Technexion's U-Boot tree. Signed-off-by: Fabio Estevam --- arch/arm/include/asm/arch-mx6/imx-regs.h | 3 + board/wandboard/spl.c | 125 ++++++++++++++++++++++++++++++- board/wandboard/wandboard.c | 6 +- include/configs/wandboard.h | 2 + 4 files changed, 132 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 86e267087ad..624ccecfd60 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -346,6 +346,9 @@ #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #endif + +#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000) + /* Only for i.MX6SX */ #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 00c75d06826..d6f568bb926 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; #define IMX6DQ_DRIVE_STRENGTH 0x30 #define IMX6SDL_DRIVE_STRENGTH 0x28 +#define IMX6QP_DRIVE_STRENGTH 0x28 /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { @@ -63,6 +64,36 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, }; +/* configure MX6QP mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = { + .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH, + .dram_cas = IMX6QP_DRIVE_STRENGTH, + .dram_ras = IMX6QP_DRIVE_STRENGTH, + .dram_reset = IMX6QP_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm0 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm1 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm2 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm3 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm4 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm5 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm6 = IMX6QP_DRIVE_STRENGTH, + .dram_dqm7 = IMX6QP_DRIVE_STRENGTH, +}; + /* configure MX6Q/DUAL mmdc GRP io registers */ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { .grp_ddr_type = 0x000c0000, @@ -81,6 +112,24 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, }; +/* configure MX6QP mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6QP_DRIVE_STRENGTH, + .grp_ctlds = IMX6QP_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6QP_DRIVE_STRENGTH, + .grp_b1ds = IMX6QP_DRIVE_STRENGTH, + .grp_b2ds = IMX6QP_DRIVE_STRENGTH, + .grp_b3ds = IMX6QP_DRIVE_STRENGTH, + .grp_b4ds = IMX6QP_DRIVE_STRENGTH, + .grp_b5ds = IMX6QP_DRIVE_STRENGTH, + .grp_b6ds = IMX6QP_DRIVE_STRENGTH, + .grp_b7ds = IMX6QP_DRIVE_STRENGTH, +}; + /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, @@ -260,15 +309,87 @@ static void ccgr_init(void) writel(0x00C03F3F, &ccm->CCGR0); writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); + writel(0x3FF03000, &ccm->CCGR3); writel(0x00FFF300, &ccm->CCGR4); writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); } +static void spl_dram_init_imx6qp_lpddr3(void) +{ + /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */ + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + /* Calibrations - ZQ */ + writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); + /* write leveling */ + writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c); + writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810); + writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c); + writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810); + /* + * DQS gating, read delay, write delay calibration values + * based on calibration compare of 0x00ffff00 + */ + writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c); + writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840); + writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c); + writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840); + writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848); + writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848); + writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850); + writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); + writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0); + writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0); + writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8); + writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8); + /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */ + writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004); + writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008); + writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c); + writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010); + writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014); + writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018); + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c); + writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030); + writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040); + writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400); + writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000); + writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890); + /* add NOC DDR configuration */ + writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008); + writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c); + writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038); + writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014); + writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028); + writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c); + writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020); + writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818); + writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818); + writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404); + writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c); +} + static void spl_dram_init(void) { - if (is_cpu_type(MXC_CPU_MX6SOLO)) { + if (is_mx6dqp()) { + mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs); + spl_dram_init_imx6qp_lpddr3(); + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); } else if (is_cpu_type(MXC_CPU_MX6DL)) { diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 6d2609ce119..051560fb016 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -512,7 +512,9 @@ int board_late_init(void) #endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_mx6dq()) + if (is_mx6dqp()) + env_set("board_rev", "MX6QP"); + else if (is_mx6dq()) env_set("board_rev", "MX6Q"); else env_set("board_rev", "MX6DL"); @@ -534,7 +536,7 @@ int board_init(void) #if defined(CONFIG_VIDEO_IPUV3) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); - if (is_mx6dq()) { + if (is_mx6dq() || is_mx6dqp()) { setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); } else { diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index ba88d02b88b..8fdfc0277d5 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -109,6 +109,8 @@ "fi; " \ "fi\0" \ "findfdt="\ + "if test $board_name = D1 && test $board_rev = MX6QP ; then " \ + "setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \ "if test $board_name = D1 && test $board_rev = MX6Q ; then " \ "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \ "if test $board_name = D1 && test $board_rev = MX6DL ; then " \ -- cgit v1.3.1 From 506abdb4ee9664cc0d6d1321e96f7fb8dae72eb9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 22 Oct 2017 10:22:40 +0200 Subject: ARM: imx6: Enable UMS and DFU on DHCOM i.MX6 PDK Enable UMS and DFU, so that the eMMC can be accessed via the USB gadget port on the board. Signed-off-by: Marek Vasut Cc: Stefano Babic --- board/dhelectronics/dh_imx6/dh_imx6.c | 10 ++-------- configs/dh_imx6_defconfig | 8 ++++++++ include/configs/dh_imx6.h | 12 ++++++++++++ 3 files changed, 22 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index c76da4d2af9..b00d0e4b6d8 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -252,17 +252,11 @@ static void setup_usb(void) } int board_usb_phy_mode(int port) -{ - return USB_INIT_HOST; -} - -/* Use only Port 1 == DHCOM USB Host 1 */ -int board_ehci_hcd_init(int port) { if (port == 1) - return 0; + return USB_INIT_HOST; else - return -ENODEV; + return USB_INIT_DEVICE; } int board_ehci_power(int port, int on) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 5d9eda8c7db..175f9fa28cd 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -19,6 +19,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y +CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -27,6 +28,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_SATA=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -47,4 +49,10 @@ CONFIG_NETDEVICES=y CONFIG_FEC_MXC=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="dh" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT=y diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 0595f60e32d..11a01d476fb 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -115,6 +115,18 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ + +/* USB Gadget (DFU, UMS) */ +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB IDs */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#endif #endif /* Watchdog */ -- cgit v1.3.1