From 0d12f77ce5307956b13a568e6848a91d4d9d48eb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 1 Feb 2025 16:02:45 +0200 Subject: power: pmic: add the basic CPCAP PMIC support The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC whose main purpose was power control. It was used in a wide variety of Motorola products, both Tegra and OMAP based. The most notable devices using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. Signed-off-by: Svyatoslav Ryhel --- include/power/cpcap.h | 238 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) create mode 100644 include/power/cpcap.h (limited to 'include') diff --git a/include/power/cpcap.h b/include/power/cpcap.h new file mode 100644 index 00000000000..ecc0ece6518 --- /dev/null +++ b/include/power/cpcap.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _CPCAP_H_ +#define _CPCAP_H_ + +#define CPCAP_VENDOR_ST 0 +#define CPCAP_VENDOR_TI 1 + +#define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1) +#define CPCAP_REVISION_MINOR(r) ((r) & 0xf) + +#define CPCAP_REVISION_1_0 0x08 +#define CPCAP_REVISION_1_1 0x09 +#define CPCAP_REVISION_2_0 0x10 +#define CPCAP_REVISION_2_1 0x11 +#define CPCAP_REVISION_3_1 0x19 + +/* CPCAP registers */ +#define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */ +#define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */ +#define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */ +#define CPCAP_REG_INT4 0x000c /* Interrupt 4 */ +#define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */ +#define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */ +#define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */ +#define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */ +#define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */ +#define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */ +#define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */ +#define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */ +#define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */ +#define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */ +#define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */ +#define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */ +#define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */ +#define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */ +#define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */ +#define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */ + +#define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */ +#define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */ +#define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */ +#define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */ +#define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */ +#define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */ + +#define CPCAP_REG_PC1 0x021c /* Power Cut 1 */ +#define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */ +#define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */ +#define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */ +#define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */ +#define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */ +#define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */ +#define CPCAP_REG_PF 0x0238 /* Print Format */ + +#define CPCAP_REG_SCC 0x0400 /* System Clock Control */ +#define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */ +#define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */ +#define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */ +#define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */ +#define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */ +#define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */ +#define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */ +#define CPCAP_REG_DAY 0x0420 /* Day */ +#define CPCAP_REG_DAYA 0x0424 /* Day Alarm */ +#define CPCAP_REG_VAL1 0x0428 /* Validity 1 */ +#define CPCAP_REG_VAL2 0x042c /* Validity 2 */ + +#define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */ +#define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */ +#define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */ +#define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */ +#define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */ +#define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */ +#define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */ +#define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */ +#define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */ +#define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */ +#define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */ +#define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */ +#define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */ +#define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */ +#define CPCAP_REG_VDACC 0x0638 /* VDAC Control */ +#define CPCAP_REG_VDIGC 0x063c /* VDIG Control */ +#define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */ +#define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */ +#define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */ +#define CPCAP_REG_VPLLC 0x064c /* VPLL Control */ +#define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */ +#define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */ +#define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */ +#define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */ +#define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */ +#define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */ +#define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */ +#define CPCAP_REG_VUSBC 0x066c /* VUSB Control */ +#define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */ +#define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */ +#define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */ +#define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */ +#define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */ + +#define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */ +#define CPCAP_REG_CC 0x0804 /* Codec Control */ +#define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */ +#define CPCAP_REG_SDAC 0x080c /* Stereo DAC */ +#define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */ +#define CPCAP_REG_TXI 0x0814 /* TX Inputs */ +#define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */ +#define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */ +#define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */ +#define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */ +#define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */ +#define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */ +#define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */ +#define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */ +#define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */ +#define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */ +#define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */ +#define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */ + +#define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */ +#define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */ +#define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */ +#define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */ +#define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */ +#define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */ +#define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */ +#define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */ +#define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */ +#define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */ + +#define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */ +#define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */ +#define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */ +#define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */ +#define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */ +#define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */ +#define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */ +#define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */ +#define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */ +#define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */ +#define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */ +#define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */ + +#define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */ +#define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */ +#define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */ +#define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */ +#define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */ +#define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */ +#define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */ +#define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */ +#define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */ +#define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */ +#define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */ +#define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */ +#define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */ +#define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */ +#define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */ +#define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */ +#define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */ +#define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */ +#define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */ +#define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */ +#define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */ +#define CPCAP_REG_USBD 0x0e60 /* USB Debug */ +#define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */ +#define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */ +#define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */ + +#define CPCAP_REG_VMC 0x0eac /* Video Mux Control */ +#define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */ +#define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */ + +#define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */ + +#define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */ + +#define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */ + +#define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */ + +#define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */ + +#define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */ + +#define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */ +#define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */ +#define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */ +#define CPCAP_REG_REDC 0x100c /* Red Triode Control */ +#define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */ +#define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */ +#define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */ +#define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */ +#define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */ +#define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */ + +#define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */ +#define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */ +#define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */ +#define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */ + +#define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */ + +#define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */ +#define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */ +#define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */ +#define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */ + +#define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */ + +#define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */ +#define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */ +#define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */ +#define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */ + +#define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */ +#define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */ +#define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */ +#define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */ +#define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */ +#define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */ +#define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */ +#define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */ +#define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */ +#define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */ +#define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */ + +#define CPCAP_REG_TEST 0x7c00 /* Test */ + +#define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */ + +#define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */ + +#endif /* _CPCAP_H_ */ -- cgit v1.3.1 From 4dc27f964403e4e0dcc894d388050dd13503b6d7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 17 Mar 2025 20:49:22 +0200 Subject: power: regulator: add regulator support for CPCAP PMIC The driver provides regulator set/get voltage and enable/disable functions for CPCAP PMIC. Signed-off-by: Svyatoslav Ryhel --- drivers/power/pmic/cpcap.c | 35 ++++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/cpcap_regulator.c | 275 ++++++++++++++++++++++++++++++ include/power/cpcap.h | 135 +++++++++++++++ 5 files changed, 455 insertions(+) create mode 100644 drivers/power/regulator/cpcap_regulator.c (limited to 'include') diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c index 4923255f0a7..f2076afff43 100644 --- a/drivers/power/pmic/cpcap.c +++ b/drivers/power/pmic/cpcap.c @@ -12,6 +12,12 @@ #include #include +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "sw", .driver = CPCAP_SW_DRIVER }, + { .prefix = "v", .driver = CPCAP_LDO_DRIVER }, + { }, +}; + static int cpcap_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { u8 buf[4]; @@ -47,6 +53,34 @@ static int cpcap_read(struct udevice *dev, uint reg, uint8_t *buff, int len) return ret; } +static int cpcap_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children; + + /* Regulator device node of PMIC */ + regulators_node = dev_read_subnode(dev, "regulator"); + if (!ofnode_valid(regulators_node)) { + log_err("%s regulator subnode not found!\n", dev->name); + return -ENXIO; + } + + /* Actual regulators container */ + regulators_node = ofnode_find_subnode(regulators_node, "regulators"); + if (!ofnode_valid(regulators_node)) { + log_err("%s regulators subnode not found!\n", dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + log_err("%s - no child found\n", dev->name); + + return dm_scan_fdt_dev(dev); +} + static int cpcap_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); @@ -85,6 +119,7 @@ U_BOOT_DRIVER(pmic_cpcap) = { .name = "cpcap_pmic", .id = UCLASS_PMIC, .of_match = cpcap_ids, + .bind = cpcap_bind, .probe = cpcap_probe, .ops = &cpcap_ops, }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bab68317cfa..bec2d2d7d49 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -493,3 +493,12 @@ config REGULATOR_RZG2L_USBPHY Enable this option to support controlling the VBUS supply in the USB PHY peripheral of the Renesas RZ/G2L SoC. This option is required in order to use the USB OTG port. + +config DM_REGULATOR_CPCAP + bool "Enable driver for CPCAP PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_CPCAP + ---help--- + Enable implementation of driver-model regulator uclass features for + REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching + (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP + PMIC and implements get/set api for voltage and state. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index cb6d5b29986..99affa235f3 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o +obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c new file mode 100644 index 00000000000..04cd6651374 --- /dev/null +++ b/drivers/power/regulator/cpcap_regulator.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2025 Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include + +/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */ +#define CPCAP_BIT_VSDIO_SEL BIT(15) +#define CPCAP_BIT_VDIG_SEL BIT(14) +#define CPCAP_BIT_VCAM_SEL BIT(13) +#define CPCAP_BIT_SW6_SEL BIT(12) +#define CPCAP_BIT_SW5_SEL BIT(11) +#define CPCAP_BIT_SW4_SEL BIT(10) +#define CPCAP_BIT_SW3_SEL BIT(9) +#define CPCAP_BIT_SW2_SEL BIT(8) +#define CPCAP_BIT_SW1_SEL BIT(7) + +/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */ +#define CPCAP_BIT_VUSBINT2_SEL BIT(15) +#define CPCAP_BIT_VUSBINT1_SEL BIT(14) +#define CPCAP_BIT_VVIB_SEL BIT(13) +#define CPCAP_BIT_VWLAN1_SEL BIT(12) +#define CPCAP_BIT_VRF1_SEL BIT(11) +#define CPCAP_BIT_VHVIO_SEL BIT(10) +#define CPCAP_BIT_VDAC_SEL BIT(9) +#define CPCAP_BIT_VUSB_SEL BIT(8) +#define CPCAP_BIT_VSIM_SEL BIT(7) +#define CPCAP_BIT_VRFREF_SEL BIT(6) +#define CPCAP_BIT_VPLL_SEL BIT(5) +#define CPCAP_BIT_VFUSE_SEL BIT(4) +#define CPCAP_BIT_VCSI_SEL BIT(3) +#define CPCAP_BIT_SPARE_14_2 BIT(2) +#define CPCAP_BIT_VWLAN2_SEL BIT(1) +#define CPCAP_BIT_VRF2_SEL BIT(0) +#define CPCAP_BIT_NONE 0 + +/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */ +#define CPCAP_BIT_VAUDIO_SEL BIT(0) + +/* + * Off mode configuration bit. Used currently only by SW5 on omap4. There's + * the following comment in Motorola Linux kernel tree for it: + * + * When set in the regulator mode, the regulator assignment will be changed + * to secondary when the regulator is disabled. The mode will be set back to + * primary when the regulator is turned on. + */ +#define CPCAP_REG_OFF_MODE_SEC BIT(15) + +#define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \ + _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl, \ + _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) { \ + .reg = CPCAP_REG_##_reg, \ + .assignment_reg = CPCAP_REG_##_assignment_reg, \ + .assignment_mask = CPCAP_BIT_##_assignment_mask, \ + .mode_mask = _mode_mask, \ + .volt_mask = _volt_mask, \ + .volt_shft = _volt_shft, \ + .mode_val = _mode_val, \ + .off_mode_val = _off_mode_val, \ + .val_tbl_sz = ARRAY_SIZE(_val_tbl), \ + .val_tbl = _val_tbl, \ + .mode_cntr = _mode_cntr, \ + .volt_trans_time = _volt_trans_time, \ + .turn_on_time = _turn_on_time, \ + .bit_offset_from_cpcap_lowest_voltage = _bit_offset, \ +} + +static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = { + /* BUCK */ + [CPCAP_SW1] = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f, + 0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c), + [CPCAP_SW2] = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f, + 0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + [CPCAP_SW3] = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003, + 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0), + [CPCAP_SW4] = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f, + 0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + [CPCAP_SW5] = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000, + 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0), + [CPCAP_SW6] = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000, + 0, 0, 0, unknown_val_tbl, 0, 0, 0, 0), + /* LDO */ + [CPCAP_VCAM] = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030, + 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0), + [CPCAP_VCSI] = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010, + 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0), + [CPCAP_VDAC] = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030, + 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0), + [CPCAP_VDIG] = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030, + 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0), + [CPCAP_VFUSE] = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f, + 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0), + [CPCAP_VHVIO] = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000, + 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0), + [CPCAP_VSDIO] = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038, + 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0), + [CPCAP_VPLL] = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018, + 3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0), + [CPCAP_VRF1] = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002, + 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0), + [CPCAP_VRF2] = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008, + 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0), + [CPCAP_VRFREF] = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008, + 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0), + [CPCAP_VWLAN1] = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010, + 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0), + [CPCAP_VWLAN2] = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0, + 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0), + [CPCAP_VSIM] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008, + 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0), + [CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008, + 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0), + [CPCAP_VVIB] = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c, + 2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0), + [CPCAP_VUSB] = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040, + 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0), + [CPCAP_VAUDIO] = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001, + 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0), +}; + +static int cpcap_regulator_get_value(struct udevice *dev) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int value, volt_shift = regulator->volt_shft; + + value = pmic_reg_read(dev->parent, regulator->reg); + if (value < 0) + return value; + + if (!(value & regulator->mode_mask)) + return 0; + + value &= regulator->volt_mask; + value -= regulator->bit_offset_from_cpcap_lowest_voltage; + + return regulator->val_tbl[value >> volt_shift]; +} + +static int cpcap_regulator_set_value(struct udevice *dev, int uV) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int value, ret, volt_shift = regulator->volt_shft; + + if (dev->driver_data == CPCAP_VRF1) { + if (uV > 2500000) + value = 0; + else + value = regulator->volt_mask; + } else { + for (value = 0; value < regulator->val_tbl_sz; value++) + if (regulator->val_tbl[value] >= uV) + break; + + if (value >= regulator->val_tbl_sz) + value = regulator->val_tbl_sz; + + value <<= volt_shift; + value += regulator->bit_offset_from_cpcap_lowest_voltage; + } + + ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask, + value); + if (ret) + return ret; + + if (regulator->volt_trans_time) + udelay(regulator->volt_trans_time); + + return 0; +} + +static int cpcap_regulator_get_enable(struct udevice *dev) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int value; + + value = pmic_reg_read(dev->parent, regulator->reg); + if (value < 0) + return value; + + return (value & regulator->mode_mask) ? 1 : 0; +} + +static int cpcap_regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int ret; + + if (enable) { + ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask, + regulator->mode_val); + if (ret) + return ret; + } + + if (regulator->mode_val & CPCAP_REG_OFF_MODE_SEC) { + ret = pmic_clrsetbits(dev->parent, regulator->assignment_reg, + regulator->assignment_mask, + enable ? 0 : regulator->assignment_mask); + if (ret) + return ret; + } + + if (!enable) { + ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask, + regulator->off_mode_val); + if (ret) + return ret; + } + + if (regulator->turn_on_time) + udelay(regulator->turn_on_time); + + return 0; +} + +static int cpcap_regulator_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + int id; + + for (id = 0; id < CPCAP_REGULATORS_COUNT; id++) + if (cpcap_regulator_to_name[id]) + if (!strcmp(dev->name, cpcap_regulator_to_name[id])) + break; + + switch (id) { + case CPCAP_SW1 ... CPCAP_SW6: + uc_pdata->type = REGULATOR_TYPE_BUCK; + break; + + case CPCAP_VCAM ... CPCAP_VAUDIO: + uc_pdata->type = REGULATOR_TYPE_LDO; + break; + + default: + log_err("CPCAP: Invalid regulator ID\n"); + return -ENODEV; + } + + dev->driver_data = id; + return 0; +} + +static const struct dm_regulator_ops cpcap_regulator_ops = { + .get_value = cpcap_regulator_get_value, + .set_value = cpcap_regulator_set_value, + .get_enable = cpcap_regulator_get_enable, + .set_enable = cpcap_regulator_set_enable, +}; + +U_BOOT_DRIVER(cpcap_sw) = { + .name = CPCAP_SW_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &cpcap_regulator_ops, + .probe = cpcap_regulator_probe, +}; + +U_BOOT_DRIVER(cpcap_ldo) = { + .name = CPCAP_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &cpcap_regulator_ops, + .probe = cpcap_regulator_probe, +}; diff --git a/include/power/cpcap.h b/include/power/cpcap.h index ecc0ece6518..bb0e28cec55 100644 --- a/include/power/cpcap.h +++ b/include/power/cpcap.h @@ -235,4 +235,139 @@ #define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */ +/* Drivers name */ +#define CPCAP_LDO_DRIVER "cpcap_ldo" +#define CPCAP_SW_DRIVER "cpcap_sw" + +enum cpcap_regulator_id { + CPCAP_SW1, + CPCAP_SW2, + CPCAP_SW3, + CPCAP_SW4, + CPCAP_SW5, + CPCAP_SW6, + CPCAP_VCAM, + CPCAP_VCSI, + CPCAP_VDAC, + CPCAP_VDIG, + CPCAP_VFUSE, + CPCAP_VHVIO, + CPCAP_VSDIO, + CPCAP_VPLL, + CPCAP_VRF1, + CPCAP_VRF2, + CPCAP_VRFREF, + CPCAP_VWLAN1, + CPCAP_VWLAN2, + CPCAP_VSIM, + CPCAP_VSIMCARD, + CPCAP_VVIB, + CPCAP_VUSB, + CPCAP_VAUDIO, + CPCAP_REGULATORS_COUNT, +}; + +static const char * const cpcap_regulator_to_name[] = { + /* BUCK */ + [CPCAP_SW1] = "sw1", + [CPCAP_SW2] = "sw2", + [CPCAP_SW3] = "sw3", + [CPCAP_SW4] = "sw4", + [CPCAP_SW5] = "sw5", + [CPCAP_SW6] = "sw6", + /* LDO */ + [CPCAP_VCAM] = "vcam", + [CPCAP_VCSI] = "vcsi", + [CPCAP_VDAC] = "vdac", + [CPCAP_VDIG] = "vdig", + [CPCAP_VFUSE] = "vfuse", + [CPCAP_VHVIO] = "vhvio", + [CPCAP_VSDIO] = "vsdio", + [CPCAP_VPLL] = "vpll", + [CPCAP_VRF1] = "vrf1", + [CPCAP_VRF2] = "vrf2", + [CPCAP_VRFREF] = "vrfref", + [CPCAP_VWLAN1] = "vwlan1", + [CPCAP_VWLAN2] = "vwlan2", + [CPCAP_VSIM] = "vsim", + [CPCAP_VSIMCARD] = "vsimcard", + [CPCAP_VVIB] = "vvib", + [CPCAP_VUSB] = "vusb", + [CPCAP_VAUDIO] = "vaudio", +}; + +static const u32 unknown_val_tbl[] = { 0, }; +static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, + 812500, 825000, 837500, 850000, 862500, + 875000, 887500, 900000, 912500, 925000, + 937500, 950000, 962500, 975000, 987500, + 1000000, 1012500, 1025000, 1037500, + 1050000, 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, 1137500, + 1150000, 1162500, 1175000, 1187500, + 1200000, 1212500, 1225000, 1237500, + 1250000, 1262500, 1275000, 1287500, + 1300000, 1312500, 1325000, 1337500, + 1350000, 1362500, 1375000, 1387500, + 1400000, 1412500, 1425000, 1437500, + 1450000, 1462500, 1475000 }; +static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, + 962500, 975000, 987500, 1000000, 1012500, + 1025000, 1037500, 1050000, 1062500, + 1075000, 1087500, 1100000, 1112500, + 1125000, 1137500, 1150000, 1162500, + 1175000, 1187500, 1200000, 1212500, + 1225000, 1237500, 1250000, 1262500, + 1275000, 1287500, 1300000, 1312500, + 1325000, 1337500, 1350000, 1362500, + 1375000, 1387500, 1400000, 1412500, + 1425000, 1437500, 1450000, 1462500, + 1475000 }; +static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; +static const u32 sw5_val_tbl[] = { 0, 5050000 }; +static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; +static const u32 vcsi_val_tbl[] = { 1200000, 1800000 }; +static const u32 vdac_val_tbl[] = { 1200000, 1500000, 1800000, 2500000 }; +static const u32 vdig_val_tbl[] = { 1200000, 1350000, 1500000, 1875000 }; +static const u32 vfuse_val_tbl[] = { 1500000, 1600000, 1700000, 1800000, 1900000, + 2000000, 2100000, 2200000, 2300000, 2400000, + 2500000, 2600000, 2700000, 3150000 }; +static const u32 vhvio_val_tbl[] = { 2775000 }; +static const u32 vsdio_val_tbl[] = { 1500000, 1600000, 1800000, 2600000, + 2700000, 2800000, 2900000, 3000000 }; +static const u32 vpll_val_tbl[] = { 1200000, 1300000, 1400000, 1800000 }; +static const u32 vrf1_val_tbl[] = { 2775000, 2500000 }; /* Yes, this is correct */ +static const u32 vrf2_val_tbl[] = { 0, 2775000 }; +static const u32 vrfref_val_tbl[] = { 2500000, 2775000 }; +static const u32 vwlan1_val_tbl[] = { 1800000, 1900000 }; +static const u32 vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, 3300000 }; +static const u32 vsim_val_tbl[] = { 1800000, 2900000 }; +static const u32 vsimcard_val_tbl[] = { 1800000, 2900000 }; +static const u32 vvib_val_tbl[] = { 1300000, 1800000, 2000000, 3000000 }; +static const u32 vusb_val_tbl[] = { 0, 3300000 }; +static const u32 vaudio_val_tbl[] = { 0, 2775000 }; + +struct cpcap_regulator_data { + u16 reg; + u16 assignment_reg; + u16 assignment_mask; + u16 mode_mask; + u16 volt_mask; + u8 volt_shft; + u16 mode_val; + u16 off_mode_val; + u32 val_tbl_sz; + const u32 *val_tbl; + u32 mode_cntr; + u32 volt_trans_time; /* in micro seconds */ + u32 turn_on_time; /* in micro seconds */ + + /* + * Bit difference between lowest value in val_tbl and start of voltage + * table setting in cpcap. Use this for switchers that have many too + * many voltages to list in val_tbl. + */ + u32 bit_offset_from_cpcap_lowest_voltage; +}; + #endif /* _CPCAP_H_ */ -- cgit v1.3.1 From 645350ed4b56f822b6da798c0cec101c3b1e4893 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 3 Dec 2023 19:34:49 +0200 Subject: board: motorola: add Atrix 4G MB860 and Droid X2 MB870 support The Motorola Atrix 4G (MB860) and Droid X2 (MB870) both featured a dual-core NVIDIA Tegra 2 AP20H processor clocked at 1GHz, coupled with 1GB of DDR2 RAM. Storage consisted of 16GB of internal flash memory, expandable via microSD. The display was a 4.0-inch TFT LCD with a resolution of 960x540 pixels (qHD). The devices originally ran on Android up to 2.3 (Gingerbread). Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 2 + arch/arm/dts/tegra20-motorola-daytona.dts | 9 + arch/arm/dts/tegra20-motorola-mot.dtsi | 490 ++++++++++++++++++++++++++++++ arch/arm/dts/tegra20-motorola-olympus.dts | 9 + arch/arm/mach-tegra/tegra20/Kconfig | 5 + board/motorola/mot/Kconfig | 12 + board/motorola/mot/MAINTAINERS | 7 + board/motorola/mot/Makefile | 9 + board/motorola/mot/configs/daytona.config | 2 + board/motorola/mot/configs/olympus.config | 2 + board/motorola/mot/mot-spl.c | 58 ++++ board/motorola/mot/mot.env | 15 + configs/mot_defconfig | 93 ++++++ doc/board/index.rst | 1 + doc/board/motorola/index.rst | 9 + doc/board/motorola/mot.rst | 104 +++++++ include/configs/mot.h | 25 ++ 17 files changed, 852 insertions(+) create mode 100644 arch/arm/dts/tegra20-motorola-daytona.dts create mode 100644 arch/arm/dts/tegra20-motorola-mot.dtsi create mode 100644 arch/arm/dts/tegra20-motorola-olympus.dts create mode 100644 board/motorola/mot/Kconfig create mode 100644 board/motorola/mot/MAINTAINERS create mode 100644 board/motorola/mot/Makefile create mode 100644 board/motorola/mot/configs/daytona.config create mode 100644 board/motorola/mot/configs/olympus.config create mode 100644 board/motorola/mot/mot-spl.c create mode 100644 board/motorola/mot/mot.env create mode 100644 configs/mot_defconfig create mode 100644 doc/board/motorola/index.rst create mode 100644 doc/board/motorola/mot.rst create mode 100644 include/configs/mot.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 080ea522ed5..341bac1afc5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra20-asus-tf101g.dtb \ tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ + tegra20-motorola-daytona.dtb \ + tegra20-motorola-olympus.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ tegra20-seaboard.dtb \ diff --git a/arch/arm/dts/tegra20-motorola-daytona.dts b/arch/arm/dts/tegra20-motorola-daytona.dts new file mode 100644 index 00000000000..1be8887a332 --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-daytona.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-motorola-mot.dtsi" + +/ { + model = "Motorola Droid X2 (MB870)"; + compatible = "motorola,daytona", "nvidia,tegra20"; +}; diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi new file mode 100644 index 00000000000..f00707c2859 --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include "tegra20.dtsi" + +/ { + chosen { + stdout-path = &uartb; + }; + + aliases { + i2c0 = &gen1_i2c; + + spi0 = &cpcap_spi; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel { + compatible = "motorola,mot-panel"; + + reset-gpios = <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_5v0_panel>; + vddio-supply = <&vdd_1v8_vio>; + + backlight = <&backlight>; + }; + }; + }; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = ; + output-low; + }; + + usb-mux-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + crt { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + displaya { + nvidia,pins = "lcsn", "ld0", "ld1", "ld3", + "ld5", "ld6", "ld7", "ld8", + "ld9", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", + "lpp", "lsc0", "lpw1", "lsda", + "lspi"; + nvidia,function = "displaya"; + }; + + gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "gmb", "gmd", "gpu"; + nvidia,function = "gmi"; + }; + + hdmi { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2c1 { + nvidia,pins = "i2cp", "rm"; + nvidia,function = "i2c1"; + }; + + i2c2 { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + kbc { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + osc { + nvidia,pins = "cdev1", "cdev2"; + nvidia,function = "osc"; + }; + + owr { + nvidia,pins = "owc", "uac"; + nvidia,function = "owr"; + }; + + pcie { + nvidia,pins = "gpv"; + nvidia,function = "pcie"; + }; + + pwr-on { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rsvd4 { + nvidia,pins = "lvp0", "lvp1", "lvs", "lsc0", + "ld10", "ld11", "lm1", "ld2", + "ld4", "ldc"; + nvidia,function = "rsvd4"; + }; + + rtck { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + sdio3 { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + + sdio4 { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + spdif { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spi2 { + nvidia,pins = "spia", "spib", "spic", "spig", + "spih"; + nvidia,function = "spi2"; + }; + + spi3 { + nvidia,pins = "lm0", "lpw0", "lpw2", "lsc1"; + nvidia,function = "spi3"; + }; + + uarta { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + + uartc { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + uartd { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + ulpi { + nvidia,pins = "uab"; + nvidia,function = "ulpi"; + }; + + vi { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "dte"; + nvidia,function = "vi"; + }; + + vi-sensor-clk { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + conf-lcsn { + nvidia,pins = "lcsn", "lpw1", "lsck", "lsda", + "lsdi", "ldc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-ata { + nvidia,pins = "ata", "atb", "atc", "ddc", + "gmc", "gpu", "kbca", "kbcb", + "kbcc", "kbcd", "kbce", "kbcf", + "lm1", "lvp0", "owc", "sdb", + "sdc", "sdd", "sdio1", "uaa", + "uad", "uca", "ucb", "pmce", + "lvs"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-cdev1 { + nvidia,pins = "cdev1", "crtp", "csus", "pta"; + nvidia,pull = ; + }; + + conf-atd { + nvidia,pins = "atd", "ate", "cdev2", "dte", + "gma", "gmb", "gmd", "gme", + "gpu7", "gpv", "hdint", "i2cp", + "irrx", "irtx", "pmc", "rm", + "slxa", "slxc", "slxd", "slxk", + "spdi", "spdo", "spid", "spie", + "spif", "uda", "ck32", "ddrc", + "pmca", "pmcb", "pmcc", "pmcd", + "xm2c", "xm2d"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", + "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", + "lpp", "lpw0", "lpw2", "lsc0", + "lsc1", "lspi", "lvp1"; + nvidia,tristate = ; + }; + + conf-dap1 { + nvidia,pins = "dap1", "dap2", "dap3", "dap4"; + nvidia,pull = ; + }; + + conf-dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "dtf"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-spi2 { + nvidia,pins = "spia", "spib", "spic", "spig", + "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + }; + }; + + uartb: serial@70006040 { + clocks = <&tegra_car 7>; + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + backlight: led-controller@38 { + compatible = "ti,lm3532"; + reg = <0x38>; + + enable-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight_led: led@0 { + reg = <0>; + + led-sources = <2>; + led-max-microamp = <26600>; + + ti,led-mode = <0>; + ti,linear-mapping-mode; + + label = ":backlight"; + }; + }; + }; + + cpcap_spi: spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + + pmic: cpcap@0 { + compatible = "motorola,cpcap"; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + + spi-cs-high; + spi-max-frequency = <8000000>; + + power_button: button { + compatible = "motorola,cpcap-pwrbutton"; + + interrupt-parent = <&pmic>; + interrupts = <23 IRQ_TYPE_NONE>; + + linux,code = ; + }; + + regulator { + compatible = "motorola,mot-cpcap-regulator"; + + regulators { + /* SW1 is vdd_cpu */ + /* SW2 is vdd_core */ + + vdd_1v8_vio: sw3 { + regulator-name = "vdd_1v8_vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SW4 is vdd_aon (rtc) */ + + vcore_emmc: vsdio { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: vcsi { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: vsimcard { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + avdd_3v3_periph: vusb { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + micro_usb: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&avdd_3v3_periph>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>; + timeout-ms = <500>; + }; + + vdd_5v0_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_disp"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(F, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_usd: regulator-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_usd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(F, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra20-motorola-olympus.dts b/arch/arm/dts/tegra20-motorola-olympus.dts new file mode 100644 index 00000000000..bba5513d6bf --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-olympus.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-motorola-mot.dtsi" + +/ { + model = "Motorola Atrix 4G (MB860)"; + compatible = "motorola,olympus", "nvidia,tegra20"; +}; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index e2735d93e28..63678376840 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -29,6 +29,10 @@ config TARGET_MEDCOM_WIDE bool "Avionic Design Medcom-Wide board" select BOARD_LATE_INIT +config TARGET_MOT + bool "Motorola Tegra20 board" + select BOARD_LATE_INIT + config TARGET_PAZ00 bool "Paz00 board" select BOARD_LATE_INIT @@ -76,6 +80,7 @@ config SYS_SOC source "board/nvidia/harmony/Kconfig" source "board/avionic-design/medcom-wide/Kconfig" +source "board/motorola/mot/Kconfig" source "board/compal/paz00/Kconfig" source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" diff --git a/board/motorola/mot/Kconfig b/board/motorola/mot/Kconfig new file mode 100644 index 00000000000..8b76165ade7 --- /dev/null +++ b/board/motorola/mot/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MOT + +config SYS_BOARD + default "mot" + +config SYS_VENDOR + default "motorola" + +config SYS_CONFIG_NAME + default "mot" + +endif diff --git a/board/motorola/mot/MAINTAINERS b/board/motorola/mot/MAINTAINERS new file mode 100644 index 00000000000..2aff81a8781 --- /dev/null +++ b/board/motorola/mot/MAINTAINERS @@ -0,0 +1,7 @@ +MOT BOARD +M: Svyatoslav Ryhel +S: Maintained +F: board/motorola/mot/ +F: configs/mot_defconfig +F: doc/board/motorola/mot.rst +F: include/configs/mot.h diff --git a/board/motorola/mot/Makefile b/board/motorola/mot/Makefile new file mode 100644 index 00000000000..f1073c2f287 --- /dev/null +++ b/board/motorola/mot/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation +# +# (C) Copyright 2025 +# Svyatoslav Ryhel + +obj-$(CONFIG_XPL_BUILD) += mot-spl.o diff --git a/board/motorola/mot/configs/daytona.config b/board/motorola/mot/configs/daytona.config new file mode 100644 index 00000000000..0b6131b77c9 --- /dev/null +++ b/board/motorola/mot/configs/daytona.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-daytona" +CONFIG_SYS_PROMPT="Tegra20 (Daytona) # " diff --git a/board/motorola/mot/configs/olympus.config b/board/motorola/mot/configs/olympus.config new file mode 100644 index 00000000000..57aa60160dd --- /dev/null +++ b/board/motorola/mot/configs/olympus.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus" +CONFIG_SYS_PROMPT="Tegra20 (Olympus) # " diff --git a/board/motorola/mot/mot-spl.c b/board/motorola/mot/mot-spl.c new file mode 100644 index 00000000000..a86e5233ac1 --- /dev/null +++ b/board/motorola/mot/mot-spl.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T20 Motorola Atrix 4G and Droid X2 SPL stage configuration + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include + +/* + * Unlike all other supported Tegra devices and most known Tegra devices, the + * both Atrix 4G and Droid X2 have no hardware way to enter APX/RCM mode, which + * may lead to a dangerous situation when, if BCT is set correctly and the + * bootloader is faulty, the device will hang in a permanent brick state. + * Exiting from this state can be done only by disassembling the device and + * shortening testpad to the ground. + * + * To prevent this or to minimize the probability of such an accident, it was + * proposed to add the RCM rebooting hook as early into SPL as possible since + * SPL is much more robust and has minimal changes that can break bootflow. + * + * gpio_early_init_uart() function was chosen as it is the earliest function + * exposed for setup by the device. Hook performs a check for volume up + * button state and triggers RCM if it is pressed. + */ +void gpio_early_init_uart(void) +{ + int value; + + /* Configure pinmux for PR0 */ + pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_KBC); + pinmux_set_pullupdown(PMUX_PINGRP_KBCA, PMUX_PULL_UP); + pinmux_tristate_disable(PMUX_PINGRP_KBCA); + + /* Configure pinmux for PQ0 */ + pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_KBC); + pinmux_set_pullupdown(PMUX_PINGRP_KBCC, PMUX_PULL_UP); + pinmux_tristate_disable(PMUX_PINGRP_KBCC); + + /* Hog column 0 (PQ0) low - active */ + spl_gpio_output(NULL, TEGRA_GPIO(Q, 0), 0); + udelay(500); + + spl_gpio_input(NULL, TEGRA_GPIO(R, 0)); + value = spl_gpio_get_value(NULL, TEGRA_GPIO(R, 0)); + + /* Enter RCM if button is pressed */ + if (!value) { + tegra_pmc_writel(2, PMC_SCRATCH0); + tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL); + } +} diff --git a/board/motorola/mot/mot.env b/board/motorola/mot/mot.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/motorola/mot/mot.env @@ -0,0 +1,15 @@ +#include + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/mot_defconfig b/configs/mot_defconfig new file mode 100644 index 00000000000..40b4feeeb90 --- /dev/null +++ b/configs/mot_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x00110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="mot" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus" +CONFIG_SPL_STACK=0xffffc +CONFIG_SPL_TEXT_BASE=0x00108000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_TEGRA20=y +CONFIG_TARGET_MOT=y +CONFIG_TEGRA_ENABLE_UARTB=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2085 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra20 (Mot) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x11000000 +CONFIG_FASTBOOT_BUF_SIZE=0x5000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_GPIO_HOG=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_CPCAP_POWER_BUTTON=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_CPCAP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_CPCAP=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_POWEROFF_GPIO=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Motorola" +CONFIG_USB_GADGET_VENDOR_NUM=0x22b8 +CONFIG_USB_GADGET_PRODUCT_NUM=0x708c +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_MOT=y +CONFIG_BACKLIGHT_LM3532=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 7ad1137c94a..9ce436af5f9 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -41,6 +41,7 @@ Board-specific doc mediatek/index microchip/index microsoft/index + motorola/index nxp/index openpiton/index ouya/index diff --git a/doc/board/motorola/index.rst b/doc/board/motorola/index.rst new file mode 100644 index 00000000000..9666ff2f4ab --- /dev/null +++ b/doc/board/motorola/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Motorola +======== + +.. toctree:: + :maxdepth: 2 + + mot diff --git a/doc/board/motorola/mot.rst b/doc/board/motorola/mot.rst new file mode 100644 index 00000000000..d0f89bcd357 --- /dev/null +++ b/doc/board/motorola/mot.rst @@ -0,0 +1,104 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Motorola Atrix 4G (MB860) and Droid X2 (MB870) +============================================================= + +``DISCLAMER!`` Moving your device to use U-Boot assumes replacement of the +vendor bootloader. Vendor Android firmwares will no longer be able to run on +the device. This replacement IS reversible if you have backups. + +Quick Start +----------- + +- Prerequisites +- Build U-Boot +- Process U-Boot +- Flashing U-Boot into the eMMC +- Boot +- Self Upgrading + +Prerequisites +------------- + +In order to work with RCM/APX mode, both devices require a factory cable which +is made by routing 5V to the ID pin of a micro-USB cable (5v is applied to both +ID and dedicated 5v). This way, the host PC can detect the device in RCM mode, +and the device can operate without a battery. + +Build U-Boot +------------ + +Device support is implemented by applying config fragment to a generic +board defconfig. Valid fragments are ``daytona.config`` and ``olympus.config``. + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make mot_defconfig olympus.config # For Atrix 4G + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Process U-Boot +-------------- + +``DISCLAMER!`` All questions related to the re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. You need to know your device +individual SBK to continue. + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev olympus --sbk --split + +where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` + +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. + +Flashing U-Boot into the eMMC +----------------------------- + +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently +U-Boot supports bootmenu entry fastboot, which allows to write a processed copy +of U-Boot permanently into eMMC. + +While pre-loading U-Boot, hold the ``volume down`` button which will trigger +the bootmenu. There, select ``fastboot`` using the volume and power buttons. +After, on host PC, do: + +.. code-block:: bash + + $ fastboot flash 0.1 bct.img + $ fastboot flash 0.2 ebt.img + $ fastboot reboot + +Device will reboot. + +Boot +---- + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while booting, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console +and update bootloader (check the next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows +the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card +and insert it into the device. Enter bootmenu, choose update the bootloader +option with the Power button and U-Boot should update itself. Once the process +is completed, U-Boot will ask to press any button to reboot. diff --git a/include/configs/mot.h b/include/configs/mot.h new file mode 100644 index 00000000000..63931e90dda --- /dev/null +++ b/include/configs/mot.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Motorola Mot" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE + +/* Tegra common post configuration overwrites text env in the board */ +#define BOARD_EXTRA_ENV_SETTINGS \ + "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 11bf63c23028f54d299a24c494242a11dcb387c7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 09:33:17 +0300 Subject: ARM: tegra: board: set CFG_SYS_NS16550_COM1 according to TEGRA_ENABLE_UART Link CFG_SYS_NS16550_COM1 value to chosen CONFIG_TEGRA_ENABLE_UART Tegra wide. Remove all CFG_SYS_NS16550_COM1 from device headers. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/board.c | 5 +++++ include/configs/apalis-tk1.h | 3 --- include/configs/apalis_t30.h | 1 - include/configs/beaver.h | 3 --- include/configs/cardhu.h | 3 --- include/configs/cei-tk1-som.h | 3 --- include/configs/colibri_t20.h | 4 ---- include/configs/colibri_t30.h | 1 - include/configs/dalmore.h | 3 --- include/configs/endeavoru.h | 3 --- include/configs/grouper.h | 3 --- include/configs/harmony.h | 9 --------- include/configs/ideapad-yoga-11.h | 3 --- include/configs/jetson-tk1.h | 3 --- include/configs/medcom-wide.h | 3 --- include/configs/mocha.h | 3 --- include/configs/mot.h | 3 --- include/configs/nyan-big.h | 3 --- include/configs/ouya.h | 3 --- include/configs/paz00.h | 3 --- include/configs/picasso.h | 3 --- include/configs/plutux.h | 3 --- include/configs/qc750.h | 3 --- include/configs/seaboard.h | 3 --- include/configs/surface-rt.h | 3 --- include/configs/tec-ng.h | 3 --- include/configs/tec.h | 3 --- include/configs/transformer-t20.h | 3 --- include/configs/transformer-t30.h | 3 --- include/configs/trimslice.h | 3 --- include/configs/venice2.h | 3 --- include/configs/ventana.h | 3 --- include/configs/x3-t30.h | 3 --- 33 files changed, 5 insertions(+), 99 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 7ca56a3b081..8c946f0f117 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -236,18 +236,23 @@ void board_init_uart_f(void) int uart_ids = 0; /* bit mask of which UART ids to enable */ #ifdef CONFIG_TEGRA_ENABLE_UARTA +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE uart_ids |= UARTA; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTB +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE uart_ids |= UARTB; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTC +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTC_BASE uart_ids |= UARTC; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTD +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE uart_ids |= UARTD; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTE_BASE uart_ids |= UARTE; #endif setup_uarts(uart_ids); diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 4c690a17856..dbb9881f6ab 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -12,9 +12,6 @@ #include "tegra124-common.h" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 87a679efde6..c806ad0d9da 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -20,7 +20,6 @@ * Apalis UART3: NVIDIA UARTB * Apalis UART4: NVIDIA UARTC */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/beaver.h b/include/configs/beaver.h index e622b7127e3..229b766eefa 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 3412b883cbb..c33c96a5eb4 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index fbd38b77fe5..7b09441258c 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -18,9 +18,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "CEI tk1-som" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index bc616d14368..d96a87c059e 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -9,10 +9,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 1f474669a73..0c93f377361 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -21,7 +21,6 @@ * Colibri UART-B: NVIDIA UARTD * Colibri UART-C: NVIDIA UARTB */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 095554157fa..82911eb6165 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 33d0021ec13..20ffda0d251 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "HTC One X" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h index b6ef6ff2ecb..834e249d148 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -11,9 +11,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index cae7acdb70b..793fdffb277 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -13,15 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" -/* Board-specific serial config */ - -/* UARTD: keyboard satellite board UART, default */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA_ENABLE_UARTA -/* UARTA: debug board UART */ -#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE -#endif - /* NAND support */ /* Environment in NAND (which is 512M), aligned to start of last sector */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h index c4e6b2a647c..0f98f890ef7 100644 --- a/include/configs/ideapad-yoga-11.h +++ b/include/configs/ideapad-yoga-11.h @@ -11,9 +11,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 9858f8ff2b5..2fb1c353ff8 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 8dbe741278a..7694a2fc84c 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* NAND support */ /* Environment in NAND, aligned to start of last sector */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h index 1c2eb906085..a84d599ccc9 100644 --- a/include/configs/mocha.h +++ b/include/configs/mocha.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE #define CFG_PRAM 0x38400 /* 225 MB */ #endif diff --git a/include/configs/mot.h b/include/configs/mot.h index 63931e90dda..28b8d504769 100644 --- a/include/configs/mot.h +++ b/include/configs/mot.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Motorola Mot" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE - /* Tegra common post configuration overwrites text env in the board */ #define BOARD_EXTRA_ENV_SETTINGS \ "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index c04d402deb0..84db4bc3bca 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h index cc86c1002e3..a9f05ae5d01 100644 --- a/include/configs/ouya.h +++ b/include/configs/ouya.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Ouya Game Console" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 950b3217642..2d8d1f652bb 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Compal Paz00" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/picasso.h b/include/configs/picasso.h index a58c7e5f353..0b08a562018 100644 --- a/include/configs/picasso.h +++ b/include/configs/picasso.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 30bfce9f503..5d7e85d9284 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* NAND support */ /* Environment in NAND, aligned to start of last sector */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h index ad9f9146bb7..f226d5a4c08 100644 --- a/include/configs/qc750.h +++ b/include/configs/qc750.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Wexler QC750" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 8e98620422d..79de9f83876 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ /* NAND support */ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h index 1f0837e179b..58be786ca77 100644 --- a/include/configs/surface-rt.h +++ b/include/configs/surface-rt.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 5e49abb49fa..4e610164fa3 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -12,9 +12,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 05dd7c96f61..cb10c0397f9 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* NAND support */ /* Environment in NAND, aligned to start of last sector */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h index 6a3d9b24036..1876d2cdc69 100644 --- a/include/configs/transformer-t20.h +++ b/include/configs/transformer-t20.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Transformer" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h index 792b958a302..37828d3a9d9 100644 --- a/include/configs/transformer-t30.h +++ b/include/configs/transformer-t30.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Transformer" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 7d1ff2afd14..c4f6defddbc 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* SPI */ /* Environment in SPI */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 353b5ea67c1..fa001afdc0f 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 1d9c60ca7c6..7a6e0254545 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index c152af9b7e2..286de6a3af4 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "LG X3 Board" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ -- cgit v1.3.1 From ee3462160cf2fdf29b44ef83df0265a19c37bc0a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 16:44:24 +0300 Subject: ARM: tegra: convert CFG_TEGRA_BOARD_STRING into Kconfig option Convert CFG_TEGRA_BOARD_STRING into Kconfig option and move it into device board Kconfig. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/board2.c | 2 +- board/acer/picasso/Kconfig | 4 ++++ board/asus/grouper/Kconfig | 4 ++++ board/asus/transformer-t20/Kconfig | 4 ++++ board/asus/transformer-t30/Kconfig | 4 ++++ board/avionic-design/medcom-wide/Kconfig | 4 ++++ board/avionic-design/plutux/Kconfig | 4 ++++ board/avionic-design/tec-ng/Kconfig | 4 ++++ board/avionic-design/tec/Kconfig | 4 ++++ board/cei/cei-tk1-som/Kconfig | 4 ++++ board/compal/paz00/Kconfig | 4 ++++ board/compulab/trimslice/Kconfig | 4 ++++ board/htc/endeavoru/Kconfig | 4 ++++ board/lenovo/ideapad-yoga-11/Kconfig | 4 ++++ board/lg/x3-t30/Kconfig | 4 ++++ board/microsoft/surface-rt/Kconfig | 4 ++++ board/motorola/mot/Kconfig | 4 ++++ board/nvidia/beaver/Kconfig | 4 ++++ board/nvidia/cardhu/Kconfig | 4 ++++ board/nvidia/dalmore/Kconfig | 4 ++++ board/nvidia/harmony/Kconfig | 4 ++++ board/nvidia/jetson-tk1/Kconfig | 4 ++++ board/nvidia/nyan-big/Kconfig | 4 ++++ board/nvidia/p2371-0000/Kconfig | 4 ++++ board/nvidia/p2371-2180/Kconfig | 4 ++++ board/nvidia/p2571/Kconfig | 4 ++++ board/nvidia/p2771-0000/Kconfig | 4 ++++ board/nvidia/p3450-0000/Kconfig | 4 ++++ board/nvidia/seaboard/Kconfig | 4 ++++ board/nvidia/venice2/Kconfig | 4 ++++ board/nvidia/ventana/Kconfig | 4 ++++ board/ouya/ouya/Kconfig | 4 ++++ board/wexler/qc750/Kconfig | 4 ++++ board/xiaomi/mocha/Kconfig | 4 ++++ include/configs/beaver.h | 4 ---- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 4 ---- include/configs/dalmore.h | 6 ------ include/configs/endeavoru.h | 4 ---- include/configs/grouper.h | 4 ---- include/configs/harmony.h | 8 -------- include/configs/ideapad-yoga-11.h | 4 ---- include/configs/jetson-tk1.h | 4 ---- include/configs/medcom-wide.h | 8 -------- include/configs/mocha.h | 3 --- include/configs/mot.h | 3 --- include/configs/nyan-big.h | 4 ---- include/configs/ouya.h | 4 ---- include/configs/p2371-0000.h | 8 -------- include/configs/p2371-2180.h | 8 -------- include/configs/p2571.h | 8 -------- include/configs/p2771-0000.h | 6 ------ include/configs/p3450-0000.h | 7 ------- include/configs/paz00.h | 6 ------ include/configs/picasso.h | 4 ---- include/configs/plutux.h | 8 -------- include/configs/qc750.h | 4 ---- include/configs/seaboard.h | 10 ---------- include/configs/surface-rt.h | 4 ---- include/configs/tec-ng.h | 4 ---- include/configs/tec.h | 8 -------- include/configs/transformer-t20.h | 4 ---- include/configs/transformer-t30.h | 4 ---- include/configs/trimslice.h | 9 --------- include/configs/venice2.h | 6 ------ include/configs/ventana.h | 6 ------ include/configs/x3-t30.h | 4 ---- 67 files changed, 133 insertions(+), 183 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 6e9ef68caf9..68534dcbb22 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -96,7 +96,7 @@ int checkboard(void) { int board_id = tegra_board_id(); - printf("Board: %s", CFG_TEGRA_BOARD_STRING); + printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); if (board_id != -1) printf(", ID: %d\n", board_id); printf("\n"); diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig index 73c0aa08508..c801bd26c7c 100644 --- a/board/acer/picasso/Kconfig +++ b/board/acer/picasso/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "picasso" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Acer Iconia Tab A500" + endif diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig index f935cce4225..5f25680d916 100644 --- a/board/asus/grouper/Kconfig +++ b/board/asus/grouper/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "grouper" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Google Nexus 7 (2012)" + endif diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig index d5fe4128289..2bf42825270 100644 --- a/board/asus/transformer-t20/Kconfig +++ b/board/asus/transformer-t20/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "transformer-t20" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Transformer T20" + endif diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig index 915436ba6c5..04278f139dc 100644 --- a/board/asus/transformer-t30/Kconfig +++ b/board/asus/transformer-t30/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "transformer-t30" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Transformer T30" + endif diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig index 267647cb41f..741fc258b3a 100644 --- a/board/avionic-design/medcom-wide/Kconfig +++ b/board/avionic-design/medcom-wide/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "medcom-wide" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Medcom-Wide" + endif diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig index 09a3ac940da..57324dc19e7 100644 --- a/board/avionic-design/plutux/Kconfig +++ b/board/avionic-design/plutux/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "plutux" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Plutux" + endif diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig index 36a0cec1be1..34e2729fd60 100644 --- a/board/avionic-design/tec-ng/Kconfig +++ b/board/avionic-design/tec-ng/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "tec-ng" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Tamonten™ NG Evaluation Carrier" + endif diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig index bc9751b1086..56b417950eb 100644 --- a/board/avionic-design/tec/Kconfig +++ b/board/avionic-design/tec/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "tec" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Tamonten Evaluation Carrier" + endif diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig index 5fcb51f2f26..32ff61ac44d 100644 --- a/board/cei/cei-tk1-som/Kconfig +++ b/board/cei/cei-tk1-som/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "cei-tk1-som" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "CEI tk1-som" + endif diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig index 30ba11d360a..0ddac85be12 100644 --- a/board/compal/paz00/Kconfig +++ b/board/compal/paz00/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "paz00" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Compal Paz00" + endif diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig index 35769140347..b26c2970fe4 100644 --- a/board/compulab/trimslice/Kconfig +++ b/board/compulab/trimslice/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "trimslice" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Compulab Trimslice" + endif diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig index 0b72c4a687d..f0967376647 100644 --- a/board/htc/endeavoru/Kconfig +++ b/board/htc/endeavoru/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "endeavoru" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "HTC One X" + endif diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig index 67644409fc1..670a5bb700c 100644 --- a/board/lenovo/ideapad-yoga-11/Kconfig +++ b/board/lenovo/ideapad-yoga-11/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ideapad-yoga-11" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Lenovo Ideapad Yoga 11" + endif diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig index 53b6ab3e93c..5a3a67d9f3b 100644 --- a/board/lg/x3-t30/Kconfig +++ b/board/lg/x3-t30/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "x3-t30" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "LG X3 Board" + endif diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig index 9e66897f6b1..7c8f67f21cb 100644 --- a/board/microsoft/surface-rt/Kconfig +++ b/board/microsoft/surface-rt/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "surface-rt" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Microsoft Surface RT" + endif diff --git a/board/motorola/mot/Kconfig b/board/motorola/mot/Kconfig index 8b76165ade7..3f6f03e95b5 100644 --- a/board/motorola/mot/Kconfig +++ b/board/motorola/mot/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mot" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Motorola Mot" + endif diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig index 23f7c945f57..be461214223 100644 --- a/board/nvidia/beaver/Kconfig +++ b/board/nvidia/beaver/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "beaver" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Beaver" + endif diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig index 63ace66aa78..8a98ace70b5 100644 --- a/board/nvidia/cardhu/Kconfig +++ b/board/nvidia/cardhu/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "cardhu" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Cardhu" + endif diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig index 96eaa01cf87..643e082ec06 100644 --- a/board/nvidia/dalmore/Kconfig +++ b/board/nvidia/dalmore/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "dalmore" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Dalmore" + endif diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig index 328c94677da..1f2bfdfe5d8 100644 --- a/board/nvidia/harmony/Kconfig +++ b/board/nvidia/harmony/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "harmony" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Harmony" + endif diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig index d90a74ea382..7a2ffd83c84 100644 --- a/board/nvidia/jetson-tk1/Kconfig +++ b/board/nvidia/jetson-tk1/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "jetson-tk1" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Jetson TK1" + endif diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig index 341c8d75c21..b239d69f5e5 100644 --- a/board/nvidia/nyan-big/Kconfig +++ b/board/nvidia/nyan-big/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "nyan-big" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Google/NVIDIA Nyan-big" + endif diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig index f94be12be1a..28e9f39045c 100644 --- a/board/nvidia/p2371-0000/Kconfig +++ b/board/nvidia/p2371-0000/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2371-0000" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2371-0000" + endif diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig index 8622bdaa16b..ffb412229c1 100644 --- a/board/nvidia/p2371-2180/Kconfig +++ b/board/nvidia/p2371-2180/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2371-2180" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2371-2180" + endif diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig index 7bc48748408..1fc1978c639 100644 --- a/board/nvidia/p2571/Kconfig +++ b/board/nvidia/p2571/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2571" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2571" + endif diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig index 1b1116f0209..52a22b79734 100644 --- a/board/nvidia/p2771-0000/Kconfig +++ b/board/nvidia/p2771-0000/Kconfig @@ -13,4 +13,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2771-0000" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2771-0000" + endif diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig index 7a08cd88675..48a94e24d54 100644 --- a/board/nvidia/p3450-0000/Kconfig +++ b/board/nvidia/p3450-0000/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p3450-0000" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P3450-0000" + endif diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig index 0924bde480f..df62519c652 100644 --- a/board/nvidia/seaboard/Kconfig +++ b/board/nvidia/seaboard/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "seaboard" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Seaboard" + endif diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig index 6905f0014ea..7bd51c7a278 100644 --- a/board/nvidia/venice2/Kconfig +++ b/board/nvidia/venice2/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "venice2" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Venice2" + endif diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig index c1ad7b76712..ea1146f75b7 100644 --- a/board/nvidia/ventana/Kconfig +++ b/board/nvidia/ventana/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ventana" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Ventana" + endif diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig index 6bab40ce933..2db127f3e14 100644 --- a/board/ouya/ouya/Kconfig +++ b/board/ouya/ouya/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ouya" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Ouya Game Console" + endif diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig index 45a1e5e057b..29943358b84 100644 --- a/board/wexler/qc750/Kconfig +++ b/board/wexler/qc750/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "qc750" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Wexler QC750" + endif diff --git a/board/xiaomi/mocha/Kconfig b/board/xiaomi/mocha/Kconfig index 25c61d4169e..bb53cc56161 100644 --- a/board/xiaomi/mocha/Kconfig +++ b/board/xiaomi/mocha/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mocha" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Xiaomi Mocha" + endif diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 229b766eefa..21b37b78a30 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -9,10 +9,6 @@ #include #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index c33c96a5eb4..7fc2d85f7bd 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -9,10 +9,6 @@ #include #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 7b09441258c..aa4057d6da0 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -14,10 +14,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "CEI tk1-som" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 82911eb6165..0946588230d 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -9,12 +9,6 @@ #include #include "tegra114-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 20ffda0d251..8cb3e414af2 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "HTC One X" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h index 834e249d148..aacbcf12658 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -7,10 +7,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 793fdffb277..beecb70cd0c 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -9,14 +9,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" - -/* NAND support */ - -/* Environment in NAND (which is 512M), aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h index 0f98f890ef7..aacbcf12658 100644 --- a/include/configs/ideapad-yoga-11.h +++ b/include/configs/ideapad-yoga-11.h @@ -7,10 +7,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 2fb1c353ff8..e4ee5ce6be8 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -10,10 +10,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 7694a2fc84c..becff398a56 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -10,14 +10,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h index a84d599ccc9..7255f31baec 100644 --- a/include/configs/mocha.h +++ b/include/configs/mocha.h @@ -10,9 +10,6 @@ #include "tegra124-common.h" -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" - #ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE #define CFG_PRAM 0x38400 /* 225 MB */ #endif diff --git a/include/configs/mot.h b/include/configs/mot.h index 28b8d504769..018672cb28f 100644 --- a/include/configs/mot.h +++ b/include/configs/mot.h @@ -10,9 +10,6 @@ #include #include "tegra20-common.h" -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Motorola Mot" - /* Tegra common post configuration overwrites text env in the board */ #define BOARD_EXTRA_ENV_SETTINGS \ "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 84db4bc3bca..808cd908972 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -10,10 +10,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h index a9f05ae5d01..381941760e3 100644 --- a/include/configs/ouya.h +++ b/include/configs/ouya.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Ouya Game Console" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index a29d7135d0b..79240bd8ed0 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -10,14 +10,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 0b077aba659..24f3a7030e8 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -10,14 +10,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 5155aa7b1dd..0dbb45e7c2a 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -10,14 +10,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2571" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* _P2571_H */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index fc1b7c0302d..914c68ffdf9 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -9,12 +9,6 @@ #include #include "tegra186-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index 1138c1d306f..c5a74e8f8fe 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -9,13 +9,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" - -/* Board-specific serial config */ - -/* General networking support */ #include "tegra-common-post.h" #endif /* _P3450_0000_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 2d8d1f652bb..ec123804545 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -11,12 +11,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Compal Paz00" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h index 0b08a562018..4b6837dc000 100644 --- a/include/configs/picasso.h +++ b/include/configs/picasso.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 5d7e85d9284..becff398a56 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -10,14 +10,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h index f226d5a4c08..2acafb488b1 100644 --- a/include/configs/qc750.h +++ b/include/configs/qc750.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Wexler QC750" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 79de9f83876..4a2c6623ac1 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -10,16 +10,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* NAND support */ - -/* Max number of NAND devices */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h index 58be786ca77..39f7dddf3d4 100644 --- a/include/configs/surface-rt.h +++ b/include/configs/surface-rt.h @@ -9,10 +9,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 4e610164fa3..3d6cb0b5257 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -8,10 +8,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index cb10c0397f9..becff398a56 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -10,14 +10,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h index 1876d2cdc69..b82c6e34c8f 100644 --- a/include/configs/transformer-t20.h +++ b/include/configs/transformer-t20.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h index 37828d3a9d9..8cb3e414af2 100644 --- a/include/configs/transformer-t30.h +++ b/include/configs/transformer-t30.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index c4f6defddbc..beecb70cd0c 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -9,15 +9,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" - -/* SPI */ - -/* Environment in SPI */ -/* 1MiB flash, environment located as high as possible */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index fa001afdc0f..bbebe53d17e 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -10,12 +10,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 7a6e0254545..00f9909b122 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -9,12 +9,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index 286de6a3af4..8cb3e414af2 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "LG X3 Board" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ -- cgit v1.3.1 From 9ee12daa591b8adefa8ae221295a85e2ee467742 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 17:18:18 +0300 Subject: ARM: tegra: replace per-device config headers with generic Tegra Most device headers contain SoC specific part and common Tegra post part. Add a generic header which can be used by any Tegra device of one of the supported SoC generations (T20, T30, T114, T124 or T210) without need in device specific configuration. Signed-off-by: Svyatoslav Ryhel --- board/acer/picasso/Kconfig | 2 +- board/asus/grouper/Kconfig | 2 +- board/asus/transformer-t20/Kconfig | 2 +- board/asus/transformer-t30/Kconfig | 2 +- board/avionic-design/medcom-wide/Kconfig | 2 +- board/avionic-design/plutux/Kconfig | 2 +- board/avionic-design/tec-ng/Kconfig | 2 +- board/avionic-design/tec/Kconfig | 2 +- board/cei/cei-tk1-som/Kconfig | 2 +- board/compal/paz00/Kconfig | 2 +- board/compulab/trimslice/Kconfig | 2 +- board/htc/endeavoru/Kconfig | 2 +- board/lenovo/ideapad-yoga-11/Kconfig | 2 +- board/lg/x3-t30/Kconfig | 2 +- board/microsoft/surface-rt/Kconfig | 2 +- board/nvidia/beaver/Kconfig | 2 +- board/nvidia/cardhu/Kconfig | 2 +- board/nvidia/dalmore/Kconfig | 2 +- board/nvidia/harmony/Kconfig | 2 +- board/nvidia/jetson-tk1/Kconfig | 2 +- board/nvidia/nyan-big/Kconfig | 2 +- board/nvidia/p2371-0000/Kconfig | 2 +- board/nvidia/p2371-2180/Kconfig | 2 +- board/nvidia/p2571/Kconfig | 2 +- board/nvidia/p2771-0000/Kconfig | 2 +- board/nvidia/p3450-0000/Kconfig | 2 +- board/nvidia/seaboard/Kconfig | 2 +- board/nvidia/venice2/Kconfig | 2 +- board/nvidia/ventana/Kconfig | 2 +- board/ouya/ouya/Kconfig | 2 +- board/toradex/apalis_t30/Kconfig | 2 +- board/toradex/apalis_t30/apalis_t30.env | 9 ++++++++ board/toradex/colibri_t20/Kconfig | 2 +- board/toradex/colibri_t30/Kconfig | 2 +- board/toradex/colibri_t30/colibri_t30.env | 8 ++++++++ board/wexler/qc750/Kconfig | 2 +- include/configs/apalis_t30.h | 26 ----------------------- include/configs/beaver.h | 14 ------------- include/configs/cardhu.h | 14 ------------- include/configs/cei-tk1-som.h | 19 ----------------- include/configs/colibri_t20.h | 14 ------------- include/configs/colibri_t30.h | 27 ------------------------ include/configs/dalmore.h | 14 ------------- include/configs/endeavoru.h | 16 --------------- include/configs/grouper.h | 12 ----------- include/configs/harmony.h | 14 ------------- include/configs/ideapad-yoga-11.h | 12 ----------- include/configs/jetson-tk1.h | 15 -------------- include/configs/medcom-wide.h | 15 -------------- include/configs/nyan-big.h | 15 -------------- include/configs/ouya.h | 16 --------------- include/configs/p2371-0000.h | 15 -------------- include/configs/p2371-2180.h | 15 -------------- include/configs/p2571.h | 15 -------------- include/configs/p2771-0000.h | 14 ------------- include/configs/p3450-0000.h | 14 ------------- include/configs/paz00.h | 16 --------------- include/configs/picasso.h | 16 --------------- include/configs/plutux.h | 15 -------------- include/configs/qc750.h | 16 --------------- include/configs/seaboard.h | 15 -------------- include/configs/surface-rt.h | 14 ------------- include/configs/tec-ng.h | 13 ------------ include/configs/tec.h | 15 -------------- include/configs/tegra.h | 34 +++++++++++++++++++++++++++++++ include/configs/transformer-t20.h | 16 --------------- include/configs/transformer-t30.h | 16 --------------- include/configs/trimslice.h | 14 ------------- include/configs/venice2.h | 15 -------------- include/configs/ventana.h | 14 ------------- include/configs/x3-t30.h | 16 --------------- 71 files changed, 85 insertions(+), 561 deletions(-) delete mode 100644 include/configs/apalis_t30.h delete mode 100644 include/configs/beaver.h delete mode 100644 include/configs/cardhu.h delete mode 100644 include/configs/cei-tk1-som.h delete mode 100644 include/configs/colibri_t20.h delete mode 100644 include/configs/colibri_t30.h delete mode 100644 include/configs/dalmore.h delete mode 100644 include/configs/endeavoru.h delete mode 100644 include/configs/grouper.h delete mode 100644 include/configs/harmony.h delete mode 100644 include/configs/ideapad-yoga-11.h delete mode 100644 include/configs/jetson-tk1.h delete mode 100644 include/configs/medcom-wide.h delete mode 100644 include/configs/nyan-big.h delete mode 100644 include/configs/ouya.h delete mode 100644 include/configs/p2371-0000.h delete mode 100644 include/configs/p2371-2180.h delete mode 100644 include/configs/p2571.h delete mode 100644 include/configs/p2771-0000.h delete mode 100644 include/configs/p3450-0000.h delete mode 100644 include/configs/paz00.h delete mode 100644 include/configs/picasso.h delete mode 100644 include/configs/plutux.h delete mode 100644 include/configs/qc750.h delete mode 100644 include/configs/seaboard.h delete mode 100644 include/configs/surface-rt.h delete mode 100644 include/configs/tec-ng.h delete mode 100644 include/configs/tec.h create mode 100644 include/configs/tegra.h delete mode 100644 include/configs/transformer-t20.h delete mode 100644 include/configs/transformer-t30.h delete mode 100644 include/configs/trimslice.h delete mode 100644 include/configs/venice2.h delete mode 100644 include/configs/ventana.h delete mode 100644 include/configs/x3-t30.h (limited to 'include') diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig index c801bd26c7c..879b778aa53 100644 --- a/board/acer/picasso/Kconfig +++ b/board/acer/picasso/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "acer" config SYS_CONFIG_NAME - default "picasso" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig index 5f25680d916..3bd712b274c 100644 --- a/board/asus/grouper/Kconfig +++ b/board/asus/grouper/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "asus" config SYS_CONFIG_NAME - default "grouper" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig index 2bf42825270..3e80d38d590 100644 --- a/board/asus/transformer-t20/Kconfig +++ b/board/asus/transformer-t20/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "asus" config SYS_CONFIG_NAME - default "transformer-t20" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig index 04278f139dc..34fd6f200f8 100644 --- a/board/asus/transformer-t30/Kconfig +++ b/board/asus/transformer-t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "asus" config SYS_CONFIG_NAME - default "transformer-t30" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig index 741fc258b3a..54474b5061a 100644 --- a/board/avionic-design/medcom-wide/Kconfig +++ b/board/avionic-design/medcom-wide/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "medcom-wide" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig index 57324dc19e7..35b19dd2ea0 100644 --- a/board/avionic-design/plutux/Kconfig +++ b/board/avionic-design/plutux/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "plutux" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig index 34e2729fd60..8782e7a2a67 100644 --- a/board/avionic-design/tec-ng/Kconfig +++ b/board/avionic-design/tec-ng/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "tec-ng" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig index 56b417950eb..12cc4e1f4d0 100644 --- a/board/avionic-design/tec/Kconfig +++ b/board/avionic-design/tec/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "tec" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig index 32ff61ac44d..9b944730e63 100644 --- a/board/cei/cei-tk1-som/Kconfig +++ b/board/cei/cei-tk1-som/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "cei" config SYS_CONFIG_NAME - default "cei-tk1-som" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig index 0ddac85be12..7fa47fc8c77 100644 --- a/board/compal/paz00/Kconfig +++ b/board/compal/paz00/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "compal" config SYS_CONFIG_NAME - default "paz00" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig index b26c2970fe4..226ebc228a8 100644 --- a/board/compulab/trimslice/Kconfig +++ b/board/compulab/trimslice/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "compulab" config SYS_CONFIG_NAME - default "trimslice" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig index f0967376647..ef50da9be45 100644 --- a/board/htc/endeavoru/Kconfig +++ b/board/htc/endeavoru/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "htc" config SYS_CONFIG_NAME - default "endeavoru" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig index 670a5bb700c..cd4aa32d86d 100644 --- a/board/lenovo/ideapad-yoga-11/Kconfig +++ b/board/lenovo/ideapad-yoga-11/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "lenovo" config SYS_CONFIG_NAME - default "ideapad-yoga-11" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig index 5a3a67d9f3b..d2cdf860db4 100644 --- a/board/lg/x3-t30/Kconfig +++ b/board/lg/x3-t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "lg" config SYS_CONFIG_NAME - default "x3-t30" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig index 7c8f67f21cb..6afddb9b363 100644 --- a/board/microsoft/surface-rt/Kconfig +++ b/board/microsoft/surface-rt/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "microsoft" config SYS_CONFIG_NAME - default "surface-rt" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig index be461214223..fe36d475b30 100644 --- a/board/nvidia/beaver/Kconfig +++ b/board/nvidia/beaver/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "beaver" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig index 8a98ace70b5..92de3f2e669 100644 --- a/board/nvidia/cardhu/Kconfig +++ b/board/nvidia/cardhu/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "cardhu" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig index 643e082ec06..8da3499b9f5 100644 --- a/board/nvidia/dalmore/Kconfig +++ b/board/nvidia/dalmore/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "dalmore" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig index 1f2bfdfe5d8..eedee71cac9 100644 --- a/board/nvidia/harmony/Kconfig +++ b/board/nvidia/harmony/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "harmony" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig index 7a2ffd83c84..9eeb55f639d 100644 --- a/board/nvidia/jetson-tk1/Kconfig +++ b/board/nvidia/jetson-tk1/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "jetson-tk1" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig index b239d69f5e5..65fef3c063f 100644 --- a/board/nvidia/nyan-big/Kconfig +++ b/board/nvidia/nyan-big/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "nyan-big" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig index 28e9f39045c..e2770781a25 100644 --- a/board/nvidia/p2371-0000/Kconfig +++ b/board/nvidia/p2371-0000/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2371-0000" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig index ffb412229c1..8d97dc354b6 100644 --- a/board/nvidia/p2371-2180/Kconfig +++ b/board/nvidia/p2371-2180/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2371-2180" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig index 1fc1978c639..1d41e9d68f4 100644 --- a/board/nvidia/p2571/Kconfig +++ b/board/nvidia/p2571/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2571" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig index 52a22b79734..199e04da07e 100644 --- a/board/nvidia/p2771-0000/Kconfig +++ b/board/nvidia/p2771-0000/Kconfig @@ -11,7 +11,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2771-0000" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig index 48a94e24d54..9235c2a0c35 100644 --- a/board/nvidia/p3450-0000/Kconfig +++ b/board/nvidia/p3450-0000/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p3450-0000" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig index df62519c652..a6baeeb7f87 100644 --- a/board/nvidia/seaboard/Kconfig +++ b/board/nvidia/seaboard/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "seaboard" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig index 7bd51c7a278..9ebaa2fa413 100644 --- a/board/nvidia/venice2/Kconfig +++ b/board/nvidia/venice2/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "venice2" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig index ea1146f75b7..b8654c24e0b 100644 --- a/board/nvidia/ventana/Kconfig +++ b/board/nvidia/ventana/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "ventana" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig index 2db127f3e14..c698f730412 100644 --- a/board/ouya/ouya/Kconfig +++ b/board/ouya/ouya/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "ouya" config SYS_CONFIG_NAME - default "ouya" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig index 9cd497091d6..6260f8eb7f4 100644 --- a/board/toradex/apalis_t30/Kconfig +++ b/board/toradex/apalis_t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "apalis_t30" + default "tegra" config TDX_CFG_BLOCK default y diff --git a/board/toradex/apalis_t30/apalis_t30.env b/board/toradex/apalis_t30/apalis_t30.env index a8f2904bcd7..85d0a05d0e1 100644 --- a/board/toradex/apalis_t30/apalis_t30.env +++ b/board/toradex/apalis_t30/apalis_t30.env @@ -1,6 +1,15 @@ uboot_hwpart=1 uboot_blk=0 +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ + set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig index a43acddb801..8a7295a41e2 100644 --- a/board/toradex/colibri_t20/Kconfig +++ b/board/toradex/colibri_t20/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "colibri_t20" + default "tegra" config TDX_CFG_BLOCK default y diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig index 68ef82b099d..643309fe856 100644 --- a/board/toradex/colibri_t30/Kconfig +++ b/board/toradex/colibri_t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "colibri_t30" + default "tegra" config TDX_CFG_BLOCK default y diff --git a/board/toradex/colibri_t30/colibri_t30.env b/board/toradex/colibri_t30/colibri_t30.env index a8f2904bcd7..87919fbf155 100644 --- a/board/toradex/colibri_t30/colibri_t30.env +++ b/board/toradex/colibri_t30/colibri_t30.env @@ -1,6 +1,14 @@ uboot_hwpart=1 uboot_blk=0 +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ + set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig index 29943358b84..b449720a8b3 100644 --- a/board/wexler/qc750/Kconfig +++ b/board/wexler/qc750/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "wexler" config SYS_CONFIG_NAME - default "qc750" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h deleted file mode 100644 index c806ad0d9da..00000000000 --- a/include/configs/apalis_t30.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014-2016 Marcel Ziswiler - * - * Configuration settings for the Toradex Apalis T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* - * Board-specific serial config - * - * Apalis UART1: NVIDIA UARTA - * Apalis UART2: NVIDIA UARTD - * Apalis UART3: NVIDIA UARTB - * Apalis UART4: NVIDIA UARTC - */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h deleted file mode 100644 index 21b37b78a30..00000000000 --- a/include/configs/beaver.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h deleted file mode 100644 index 7fc2d85f7bd..00000000000 --- a/include/configs/cardhu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h deleted file mode 100644 index aa4057d6da0..00000000000 --- a/include/configs/cei-tk1-som.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (c) Copyright 2016, Data61 - * Commonwealth Scientific and Industrial Research Organisation (CSIRO) - * - * Based on jetson-tk1.h which is: - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h deleted file mode 100644 index d96a87c059e..00000000000 --- a/include/configs/colibri_t20.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Lucas Stach - * - * Configuration settings for the Toradex Colibri T20 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h deleted file mode 100644 index 0c93f377361..00000000000 --- a/include/configs/colibri_t30.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013-2016 Stefan Agner - * - * Configuration settings for the Toradex Colibri T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* High-level configuration options */ - -/* - * Board-specific serial config - * - * Colibri UART-A: NVIDIA UARTA - * Colibri UART-B: NVIDIA UARTD - * Colibri UART-C: NVIDIA UARTB - */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h deleted file mode 100644 index 0946588230d..00000000000 --- a/include/configs/dalmore.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra114-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h deleted file mode 100644 index 8cb3e414af2..00000000000 --- a/include/configs/endeavoru.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h deleted file mode 100644 index aacbcf12658..00000000000 --- a/include/configs/grouper.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h deleted file mode 100644 index beecb70cd0c..00000000000 --- a/include/configs/harmony.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h deleted file mode 100644 index aacbcf12658..00000000000 --- a/include/configs/ideapad-yoga-11.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h deleted file mode 100644 index e4ee5ce6be8..00000000000 --- a/include/configs/jetson-tk1.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h deleted file mode 100644 index becff398a56..00000000000 --- a/include/configs/medcom-wide.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h deleted file mode 100644 index 808cd908972..00000000000 --- a/include/configs/nyan-big.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h deleted file mode 100644 index 381941760e3..00000000000 --- a/include/configs/ouya.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2025 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h deleted file mode 100644 index 79240bd8ed0..00000000000 --- a/include/configs/p2371-0000.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2371_0000_H -#define _P2371_0000_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h deleted file mode 100644 index 24f3a7030e8..00000000000 --- a/include/configs/p2371-2180.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2371_2180_H -#define _P2371_2180_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h deleted file mode 100644 index 0dbb45e7c2a..00000000000 --- a/include/configs/p2571.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2571_H -#define _P2571_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P2571_H */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h deleted file mode 100644 index 914c68ffdf9..00000000000 --- a/include/configs/p2771-0000.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013-2016, NVIDIA CORPORATION. - */ - -#ifndef _P2771_0000_H -#define _P2771_0000_H - -#include - -#include "tegra186-common.h" -#include "tegra-common-post.h" - -#endif diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h deleted file mode 100644 index c5a74e8f8fe..00000000000 --- a/include/configs/p3450-0000.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018-2019 NVIDIA Corporation. - */ - -#ifndef _P3450_0000_H -#define _P3450_0000_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P3450_0000_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h deleted file mode 100644 index ec123804545..00000000000 --- a/include/configs/paz00.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h deleted file mode 100644 index 4b6837dc000..00000000000 --- a/include/configs/picasso.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * (C) Copyright 2024 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h deleted file mode 100644 index becff398a56..00000000000 --- a/include/configs/plutux.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h deleted file mode 100644 index 2acafb488b1..00000000000 --- a/include/configs/qc750.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2023 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h deleted file mode 100644 index 4a2c6623ac1..00000000000 --- a/include/configs/seaboard.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h deleted file mode 100644 index 39f7dddf3d4..00000000000 --- a/include/configs/surface-rt.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * Copyright (c) 2021, Open Surface RT - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h deleted file mode 100644 index 3d6cb0b5257..00000000000 --- a/include/configs/tec-ng.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h deleted file mode 100644 index becff398a56..00000000000 --- a/include/configs/tec.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tegra.h b/include/configs/tegra.h new file mode 100644 index 00000000000..77bc38930d2 --- /dev/null +++ b/include/configs/tegra.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + * + * Generic device header which can be used with SYS_CONFIG_NAME + * for any Tegra device (T20, T30, T114, T124, T186 or T210). + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#ifdef CONFIG_TEGRA20 +#include "tegra20-common.h" +#elif CONFIG_TEGRA30 +#include "tegra30-common.h" +#elif CONFIG_TEGRA114 +#include "tegra114-common.h" +#elif CONFIG_TEGRA124 +#include "tegra124-common.h" +#elif CONFIG_TEGRA186 +#include "tegra186-common.h" +#elif CONFIG_TEGRA210 +#include "tegra210-common.h" +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h deleted file mode 100644 index b82c6e34c8f..00000000000 --- a/include/configs/transformer-t20.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h deleted file mode 100644 index 8cb3e414af2..00000000000 --- a/include/configs/transformer-t30.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h deleted file mode 100644 index beecb70cd0c..00000000000 --- a/include/configs/trimslice.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h deleted file mode 100644 index bbebe53d17e..00000000000 --- a/include/configs/venice2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h deleted file mode 100644 index 00f9909b122..00000000000 --- a/include/configs/ventana.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h deleted file mode 100644 index 8cb3e414af2..00000000000 --- a/include/configs/x3-t30.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 00d4996a82a459706109f4146cf6ac12e1477c7e Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 14 Mar 2023 18:24:51 +0200 Subject: board: asus: transformer: add ASUS Transformer Pad TF701T support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ASUS Transformer Pad TF701T is an Android tablet computer made by ASUS, successor to the ASUS Transformer Pad Infinity. The tablet includes a Tegra 4 T114 processor clocked at 1.9 GHz, and an upgraded 2560×1600 pixel resolution screen, increasing the pixel density to 300 PPI and a mobile dock. Transformers (t114) board derives from Nvidia Macallan development board. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra114-asus-tf701t.dts | 1245 ++++++++++++++++++++ arch/arm/mach-tegra/tegra114/Kconfig | 5 + board/asus/transformer-t114/Kconfig | 16 + board/asus/transformer-t114/MAINTAINERS | 8 + board/asus/transformer-t114/Makefile | 10 + board/asus/transformer-t114/transformer-t114-spl.c | 42 + board/asus/transformer-t114/transformer-t114.c | 57 + board/asus/transformer-t114/transformer-t114.env | 15 + configs/tf701t_defconfig | 89 ++ doc/board/asus/index.rst | 1 + doc/board/asus/transformer_t114.rst | 74 ++ include/configs/transformer-t114.h | 19 + 13 files changed, 1582 insertions(+) create mode 100644 arch/arm/dts/tegra114-asus-tf701t.dts create mode 100644 board/asus/transformer-t114/Kconfig create mode 100644 board/asus/transformer-t114/MAINTAINERS create mode 100644 board/asus/transformer-t114/Makefile create mode 100644 board/asus/transformer-t114/transformer-t114-spl.c create mode 100644 board/asus/transformer-t114/transformer-t114.c create mode 100644 board/asus/transformer-t114/transformer-t114.env create mode 100644 configs/tf701t_defconfig create mode 100644 doc/board/asus/transformer_t114.rst create mode 100644 include/configs/transformer-t114.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 341bac1afc5..c0bae4dd9e2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-ouya.dtb \ tegra30-tec-ng.dtb \ tegra30-wexler-qc750.dtb \ + tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ diff --git a/arch/arm/dts/tegra114-asus-tf701t.dts b/arch/arm/dts/tegra114-asus-tf701t.dts new file mode 100644 index 00000000000..2505b9bb726 --- /dev/null +++ b/arch/arm/dts/tegra114-asus-tf701t.dts @@ -0,0 +1,1245 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "ASUS Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + nvidia,ganged-mode = <&dsib>; + + panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&dvdd_1v8_lcd>; + backlight = <&backlight>; + }; + }; + + dsib: dsi@54400000 { + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-power { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-reset { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-host-wake { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-3v3-com { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-A pinmux */ + uarta-cts { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uarta-rts { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GNSS UART-B pinmux */ + uartb-cts { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-rts { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-shutdown { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-dev-wake { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-pcm-dap4-out { + nvidia,pins = "dap4_fs_pp4", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-pcm-dap4-in { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D pinmux */ + uartd-cts { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartd-rts { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MicroSD pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + microsd-pwr { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EMMC pinmux */ + sdmmc4-clk-cmd { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + + /* SPI pinmux */ + spi1-out { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1-in { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2 { + nvidia,pins = "ulpi_data4_po5", + "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi4-out { + nvidia,pins = "gmi_ad6_pg6", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi4-in { + nvidia,pins = "gmi_ad5_pg5", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO keys pinmux */ + hall-switch { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lineout-switch { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + power-key { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + volume-keys { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + nct-irq { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mpu-irq { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi-hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi-en { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LED pinmux */ + backlight-pwm { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + backlight-en { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Touchscreen pinmux */ + touch-irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-pwr { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-vio { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUDIO pinmux */ + audio-ldo1 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp-detect { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s0-in { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s0-out { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s1-in { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s1-out { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s2-in { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s2-out { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AsusEC pinmux */ + ec-irq { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ec-req { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hotplug-i2c { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ps2-irq { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kbd-irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dvfs-pin { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Core pinmux */ + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys-clk-req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* ULPI pinmux */ + ulpi-data0-6 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data1-5 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data2-3 { + nvidia,pins = "ulpi_data2_po3", + "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT V */ + pv0-gpio { + nvidia,pins = "pv0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1-gpio { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT U */ + pu0-gpio { + nvidia,pins = "pu0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2-gpio { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWM pinmux */ + pwm0 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwm1 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EXTPERIPH pinmux */ + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1-req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GMI pinmux */ + gmi-wp-n { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-adv { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-ad1 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad2-ad3 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-iordy { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-a18 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wait { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-p { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs2-ad { + nvidia,pins = "gmi_cs2_n_pk3", + "gmi_ad14_ph6", + "gmi_ad15_ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs4-clk { + nvidia,pins = "gmi_cs4_n_pk2", + "gmi_clk_lb"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad11 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs1-oe { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad13 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-rst-n { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT CC */ + pcc-gpio { + nvidia,pins = "pcc1", "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT BB */ + pbb3-gpio { + nvidia,pins = "pbb3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4-5-6-gpio { + nvidia,pins = "pbb4", "pbb5", "pbb6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7-gpio { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC pinmux */ + kb-r0-c1 { + nvidia,pins = "kb_row0_pr0", + "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-r8-c3 { + nvidia,pins = "kb_row8_ps0", + "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* VI pinmux */ + cam-mclk { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUD pinmux */ + gpio-x4-aud { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x1-aud { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + usb-vbus { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: smps9 { + regulator-name = "vdd_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo2 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + dvdd_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 5f0f909dd3b..fb88696ae41 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,11 +8,16 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_TRANSFORMER_T114 + bool "ASUS Tegra114 Transformer board" + select BOARD_LATE_INIT + endchoice config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/asus/transformer-t114/Kconfig" endif diff --git a/board/asus/transformer-t114/Kconfig b/board/asus/transformer-t114/Kconfig new file mode 100644 index 00000000000..2560c35846e --- /dev/null +++ b/board/asus/transformer-t114/Kconfig @@ -0,0 +1,16 @@ +if TARGET_TRANSFORMER_T114 + +config SYS_BOARD + default "transformer-t114" + +config SYS_VENDOR + default "asus" + +config SYS_CONFIG_NAME + default "transformer-t114" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Transformer T114" + +endif diff --git a/board/asus/transformer-t114/MAINTAINERS b/board/asus/transformer-t114/MAINTAINERS new file mode 100644 index 00000000000..2e8f01b98df --- /dev/null +++ b/board/asus/transformer-t114/MAINTAINERS @@ -0,0 +1,8 @@ +TRANSFORMER T114 BOARD +M: Svyatoslav Ryhel +S: Maintained +F: arch/arm/dts/tegra114-asus-tf701t.dts +F: board/asus/transformer-t114/ +F: configs/tf701t_defconfig +F: doc/board/asus/transformer_t114.rst +F: include/configs/transformer-t114.h diff --git a/board/asus/transformer-t114/Makefile b/board/asus/transformer-t114/Makefile new file mode 100644 index 00000000000..37dda5fea92 --- /dev/null +++ b/board/asus/transformer-t114/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# +# Copyright (c) 2023, Svyatoslav Ryhel +# + +obj-$(CONFIG_XPL_BUILD) += transformer-t114-spl.o + +obj-y += transformer-t114.o diff --git a/board/asus/transformer-t114/transformer-t114-spl.c b/board/asus/transformer-t114/transformer-t114-spl.c new file mode 100644 index 00000000000..ceddff36dfc --- /dev/null +++ b/board/asus/transformer-t114/transformer-t114-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T114 Transformers SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/asus/transformer-t114/transformer-t114.c b/board/asus/transformer-t114/transformer-t114.c new file mode 100644 index 00000000000..cca64b51e75 --- /dev/null +++ b/board/asus/transformer-t114/transformer-t114.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +/* T114 Transformers derive from Macallan board */ + +#include +#include +#include +#include + +#ifdef CONFIG_MMC_SDHCI_TEGRA + +#define TPS65913_I2C_ADDRESS 0x58 +#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb +#define GPIO_4 BIT(0) +#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe +#define DVFS2 BIT(1) +#define DVFS1 BIT(0) + +/* We are using this function only till palmas pinctrl driver is available */ +void pin_mux_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("%s: cannot find PMIC I2C chip\n", __func__); + return; + } + + /* GPIO4 function has to be GPIO */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2, + GPIO_4, 0); + + /* DVFS1 is enabled, DVFS2 is disabled */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3, + DVFS2 | DVFS1, DVFS1); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/asus/transformer-t114/transformer-t114.env b/board/asus/transformer-t114/transformer-t114.env new file mode 100644 index 00000000000..f7278b8661e --- /dev/null +++ b/board/asus/transformer-t114/transformer-t114.env @@ -0,0 +1,15 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Hall Sensor +button_cmd_1=poweroff + +fastboot_partition_alias_boot=CAC +fastboot_partition_alias_root=UDA + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:e; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/tf701t_defconfig b/configs/tf701t_defconfig new file mode 100644 index 00000000000..69bc945568d --- /dev/null +++ b/configs/tf701t_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_SYS_MALLOC_LEN=0x2500000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="transformer-t114" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra114-asus-tf701t" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA114=y +CONFIG_TARGET_TRANSFORMER_T114=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2086 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra114 (Transformer) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_TEGRA_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_PALMAS_GPIO=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_PALMAS=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASUS" +CONFIG_USB_GADGET_VENDOR_NUM=0x0b05 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_FONT_8X16 is not set +CONFIG_VIDEO_FONT_16X32=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst index 2cac04ce04a..a9ba7a5ac53 100644 --- a/doc/board/asus/index.rst +++ b/doc/board/asus/index.rst @@ -9,3 +9,4 @@ ASUS grouper transformer_t20 transformer_t30 + transformer_t114 diff --git a/doc/board/asus/transformer_t114.rst b/doc/board/asus/transformer_t114.rst new file mode 100644 index 00000000000..3e42b5dd9a3 --- /dev/null +++ b/doc/board/asus/transformer_t114.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the ASUS Transformer device family +============================================= + +Quick Start +----------- + +- Build U-Boot +- Boot U-Boot by loading it into RAM (coldboot) +- Chainloading U-Boot from the vendor bootloader +- Boot + +Build U-Boot +------------ + +U-Boot can be built in two forms: U-Boot with SPL, which is used for booting +by loading directly into RAM and U-Boot without SPL, which can be flashed +and chainloaded from the vendor bootloader. + +To build U-Boot with SPL proseed: + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make tf701t_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +file, ready for cold booting by loading into RAM. + +To build U-Boot without SPL adjust tf701t_defconfig: + +.. code-block:: + + CONFIG_TEXT_BASE=0x80A00000 + CONFIG_SKIP_LOWLEVEL_INIT=y + # CONFIG_OF_BOARD_SETUP is not set + CONFIG_TEGRA_SUPPORT_NON_SECURE=y + +After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file, +ready for booting with fastboot boot or which can be further processed into +a flashable boot.img. + +Boot U-Boot by loading it into RAM (coldboot) +--------------------------------------------- + +Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing +``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir. +This method requires constant access to the host PC or payloader and can fully +eliminate influence of the vendor bootloader onto the boot process. + +.. code-block:: bash + + $ ./run_bootloader.sh -s T114 -t ./bct/tf701t.bct + +Chainloading U-Boot from the vendor bootloader +---------------------------------------------- + +``u-boot-dtb.bin`` has to be further packed into Android boot image form, +where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should +not be included. Then the generated boot image can be flashed into the /boot +partition of the tablet using vendor bootloader's fastboot and will act as +the bootloader of the last stage. + +Boot +---- +In both cases after U-Boot obtains control it performs search of extlinux.conf +first on the dock USB device is available, then on MicroSD card if available +and lastly on eMMC. If none of the devices above are present, then the device +is turned off. + +If during boot of U-Boot Volume Down button is pressed, the device will enter +U-Boot bootmenu. diff --git a/include/configs/transformer-t114.h b/include/configs/transformer-t114.h new file mode 100644 index 00000000000..2fbf3417691 --- /dev/null +++ b/include/configs/transformer-t114.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2023, Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra114-common.h" + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x20000 /* 128 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From b12931d7dedd4130b2e795525431b60ffac6541f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 29 Jun 2023 10:10:26 +0300 Subject: board: nvidia: tegratab: add Nvidia Tegra Note 7 support The Tegra Note 7 is a mini tablet computer and the second Tegra 4 based mobile device designed by Nvidia that runs the Android operating system. The Tegra Note has a 7" IPS display with 1280 x 800 (217 ppi) resolution. The 1 GB of RAM and 16 GB of internal memory can be supplemented with a microSDXC card giving up to 64 GB of additional storage. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra114-nvidia-tegratab.dts | 1041 +++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra114/Kconfig | 5 + board/nvidia/tegratab/Kconfig | 16 + board/nvidia/tegratab/MAINTAINERS | 8 + board/nvidia/tegratab/Makefile | 10 + board/nvidia/tegratab/tegratab-spl.c | 42 ++ board/nvidia/tegratab/tegratab.c | 56 ++ board/nvidia/tegratab/tegratab.env | 15 + configs/tegratab_defconfig | 84 +++ doc/board/index.rst | 1 + doc/board/nvidia/index.rst | 9 + doc/board/nvidia/tegratab.rst | 74 ++ include/configs/tegratab.h | 19 + 14 files changed, 1381 insertions(+) create mode 100644 arch/arm/dts/tegra114-nvidia-tegratab.dts create mode 100644 board/nvidia/tegratab/Kconfig create mode 100644 board/nvidia/tegratab/MAINTAINERS create mode 100644 board/nvidia/tegratab/Makefile create mode 100644 board/nvidia/tegratab/tegratab-spl.c create mode 100644 board/nvidia/tegratab/tegratab.c create mode 100644 board/nvidia/tegratab/tegratab.env create mode 100644 configs/tegratab_defconfig create mode 100644 doc/board/nvidia/index.rst create mode 100644 doc/board/nvidia/tegratab.rst create mode 100644 include/configs/tegratab.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c0bae4dd9e2..57d3dd98ffb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-wexler-qc750.dtb \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ + tegra114-nvidia-tegratab.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ diff --git a/arch/arm/dts/tegra114-nvidia-tegratab.dts b/arch/arm/dts/tegra114-nvidia-tegratab.dts new file mode 100644 index 00000000000..f65772a8e01 --- /dev/null +++ b/arch/arm/dts/tegra114-nvidia-tegratab.dts @@ -0,0 +1,1041 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra Note 7"; + compatible = "nvidia,tegratab", "nvidia,tegra114"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + nvidia,180-rotation; + }; + + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + vdd-supply = <&avdd_3v3_lcd>; + vcc-supply = <&dvdd_1v8_lcd>; + + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* ULPI pinmux */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data3 { + nvidia,pins = "ulpi_data3_po4", + "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI1 pinmux */ + ulpi-clk { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-dir { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1-pins { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-dout { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-din { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-din { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-dout { + nvidia,pins = "dap4_fs_pp4", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC1 pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-wp-n { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-clk-lb { + nvidia,pins = "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EXTPERIPH pinmux */ + clk1-req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-req { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-req-pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dvfs-pinmux { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi-irq { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* UARTA pinmux */ + uarta-out { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uarta-in { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTB pinmux */ + uart2-cts-rts { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTC pinmux */ + uart3-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTD pinmux */ + gmi-a17 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-a18 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartd-out { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT U */ + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1-2 { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GMI section */ + gmi-wp-n-pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_adv_n_pk0", + "gmi_cs0_n_pj0", + "gmi_wr_n_pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-iordy-pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wait-pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-clk-pk1 { + nvidia,pins = "gmi_clk_pk1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs2-n-pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs4-n-pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad1-pg1 { + nvidia,pins = "gmi_ad1_pg1", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad2-pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_oe_n_pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad8-ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad9 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad12-ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad13-ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad15-ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-p-pj3 { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-clk-lb { + nvidia,pins = "gmi_clk_lb"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* VI_ALT3 pinmux */ + cam-mclk { + nvidia,pins = "pbb0", "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + port-bb { + nvidia,pins = "pbb3", "pbb4", "pbb5", + "pbb6", "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + port-cc { + nvidia,pins = "pcc1", "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC pinmux */ + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row2-pr2 { + nvidia,pins = "kb_row2_pr2", + "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row3-pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row4-pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row5_pr5", + "kb_row6_pr6", + "kb_col3_pq3", + "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row7-pr7 { + nvidia,pins = "kb_row7_pr7", + "kb_col2_pq2", + "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row8-ps0 { + nvidia,pins = "kb_row8_ps0", + "kb_col1_pq1", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE pinmux */ + sys-clk-req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0", + "gmi_cs1_n_pj2"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUD pinmux */ + gpio-x1-aud-px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud-px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x4-aud-px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x5_aud_px5", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud-px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w2-aud-pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w3-aud-pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + usb-vbus-en { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + avdd_3v3_lcd: smps6 { + regulator-name = "vdd_lcd_hv"; + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + regulator-boot-on; + }; + + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: smps9 { + regulator-name = "vdd_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo2 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + dvdd_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index fb88696ae41..98f1d0e71c1 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,6 +8,10 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_TEGRATAB + bool "NVIDIA Tegra114 TegraTab evaluation board" + select BOARD_LATE_INIT + config TARGET_TRANSFORMER_T114 bool "ASUS Tegra114 Transformer board" select BOARD_LATE_INIT @@ -18,6 +22,7 @@ config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/nvidia/tegratab/Kconfig" source "board/asus/transformer-t114/Kconfig" endif diff --git a/board/nvidia/tegratab/Kconfig b/board/nvidia/tegratab/Kconfig new file mode 100644 index 00000000000..8bd7cfd87b8 --- /dev/null +++ b/board/nvidia/tegratab/Kconfig @@ -0,0 +1,16 @@ +if TARGET_TEGRATAB + +config SYS_BOARD + default "tegratab" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "tegratab" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA TegraTab" + +endif diff --git a/board/nvidia/tegratab/MAINTAINERS b/board/nvidia/tegratab/MAINTAINERS new file mode 100644 index 00000000000..bfd9eae8658 --- /dev/null +++ b/board/nvidia/tegratab/MAINTAINERS @@ -0,0 +1,8 @@ +TEGRATAB BOARD +M: Svyatoslav Ryhel +S: Maintained +F: arch/arm/dts/tegra114-nvidia-tegratab.dts +F: board/nvidia/tegratab/ +F: configs/tegratab_defconfig +F: doc/board/nvidia/tegratab.rst +F: include/configs/tegratab.h diff --git a/board/nvidia/tegratab/Makefile b/board/nvidia/tegratab/Makefile new file mode 100644 index 00000000000..183a0ba0319 --- /dev/null +++ b/board/nvidia/tegratab/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# +# Copyright (c) 2023, Svyatoslav Ryhel +# + +obj-$(CONFIG_XPL_BUILD) += tegratab-spl.o + +obj-y += tegratab.o diff --git a/board/nvidia/tegratab/tegratab-spl.c b/board/nvidia/tegratab/tegratab-spl.c new file mode 100644 index 00000000000..423b3070910 --- /dev/null +++ b/board/nvidia/tegratab/tegratab-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TegraTab SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/nvidia/tegratab/tegratab.c b/board/nvidia/tegratab/tegratab.c new file mode 100644 index 00000000000..775e5be9cfa --- /dev/null +++ b/board/nvidia/tegratab/tegratab.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include +#include + +#ifdef CONFIG_MMC_SDHCI_TEGRA + +#define TPS65913_I2C_ADDRESS 0x58 +#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb +#define GPIO_4 BIT(0) +#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe +#define DVFS2 BIT(1) +#define DVFS1 BIT(0) + +/* We are using this function only till palmas pinctrl driver is available */ +void pin_mux_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("%s: cannot find PMIC I2C chip\n", __func__); + return; + } + + /* GPIO4 function has to be GPIO */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2, + GPIO_4, 0); + + /* DVFS1 is enabled, DVFS2 is disabled */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3, + DVFS2 | DVFS1, DVFS1); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes and memory reserves */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + fdt_del_node_and_alias(blob, "/reserved-memory/bootloader-firmware@b7e00000"); + + return 0; +} +#endif diff --git a/board/nvidia/tegratab/tegratab.env b/board/nvidia/tegratab/tegratab.env new file mode 100644 index 00000000000..b2ba4f4354c --- /dev/null +++ b/board/nvidia/tegratab/tegratab.env @@ -0,0 +1,15 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Hall Sensor +button_cmd_1=poweroff + +fastboot_partition_alias_boot=CAC +fastboot_partition_alias_root=UDA + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:c; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/tegratab_defconfig b/configs/tegratab_defconfig new file mode 100644 index 00000000000..f0f83218ba5 --- /dev/null +++ b/configs/tegratab_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_SYS_MALLOC_LEN=0x2500000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="tegratab" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra114-nvidia-tegratab" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA114=y +CONFIG_TARGET_TEGRATAB=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2086 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra114 (TegraTab) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_TEGRA_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_PALMAS_GPIO=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_PALMAS=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_LG_LD070WX3=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 9ce436af5f9..3c5a2c7d1cf 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc microchip/index microsoft/index motorola/index + nvidia/index nxp/index openpiton/index ouya/index diff --git a/doc/board/nvidia/index.rst b/doc/board/nvidia/index.rst new file mode 100644 index 00000000000..7c105445559 --- /dev/null +++ b/doc/board/nvidia/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NVIDIA +====== + +.. toctree:: + :maxdepth: 2 + + tegratab diff --git a/doc/board/nvidia/tegratab.rst b/doc/board/nvidia/tegratab.rst new file mode 100644 index 00000000000..c6d97ce3828 --- /dev/null +++ b/doc/board/nvidia/tegratab.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Nvidia Tegra Note 7 +================================== + +Quick Start +----------- + +- Build U-Boot +- Boot U-Boot by loading it into RAM (coldboot) +- Chainloading U-Boot from the vendor bootloader +- Boot + +Build U-Boot +------------ + +U-Boot can be built in two forms: U-Boot with SPL, which is used for booting +by loading directly into RAM and U-Boot without SPL, which can be flashed +and chainloaded from the vendor bootloader. + +To build U-Boot with SPL proseed: + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make tegratab_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +file, ready for cold booting by loading into RAM. + +To build U-Boot without SPL adjust tegratab_defconfig: + +.. code-block:: + + CONFIG_TEXT_BASE=0x80A00000 + CONFIG_SKIP_LOWLEVEL_INIT=y + # CONFIG_OF_BOARD_SETUP is not set + CONFIG_TEGRA_SUPPORT_NON_SECURE=y + +After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file, +ready for booting with fastboot boot or which can be further processed into +a flashable boot.img. + +Boot U-Boot by loading it into RAM (coldboot) +--------------------------------------------- + +Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing +``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir. +This method requires constant access to the host PC or payloader and can fully +eliminate influence of the vendor bootloader onto the boot process. + +.. code-block:: bash + + $ ./run_bootloader.sh -s T114 -t ./bct/tegratab.bct + +Chainloading U-Boot from the vendor bootloader +---------------------------------------------- + +``u-boot-dtb.bin`` has to be further packed into Android boot image form, +where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should +not be included. Then the generated boot image can be flashed into the /boot +partition of the tablet using vendor bootloader's fastboot and will act as +the bootloader of the last stage. + +Boot +---- +In both cases after U-Boot obtains control it performs search of extlinux.conf +first on the dock USB device is available, then on MicroSD card if available +and lastly on eMMC. If none of the devices above are present, then the device +is turned off. + +If during boot of U-Boot Volume Down button is pressed, the device will enter +U-Boot bootmenu. diff --git a/include/configs/tegratab.h b/include/configs/tegratab.h new file mode 100644 index 00000000000..afab01ec09c --- /dev/null +++ b/include/configs/tegratab.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2023, Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra114-common.h" + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x21c00 /* 135 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.3.1