From e863f7f051687b682b948bf5c5493c8b60463113 Mon Sep 17 00:00:00 2001 From: Anton Schubert Date: Wed, 15 Jul 2015 14:50:05 +0200 Subject: arm: mvebu: add Armada XP SATA support This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Signed-off-by: Anton Schubert Tested-by: Stefan Roese Cc: Luka Perkov --- include/configs/db-mv784mp-gp.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'include') diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index c33a58895a6..aeddbf93d6e 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -27,6 +27,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE #define CONFIG_CMD_PING #define CONFIG_CMD_SF #define CONFIG_CMD_SPI @@ -60,6 +61,34 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST +/* SATA support */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE + +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO + +#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 + +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 + +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS + +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 + +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_CMD_IDE */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- cgit v1.2.3 From ff9112df8b643ad989e8673452c75e073f3c9ff3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 25 Mar 2015 12:51:18 +0100 Subject: arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory With the upcoming addition of the Armada 38x DDR support, which is not compatible to the Armada XP DDR init code, we need to introduce a new directory infrastructure. To support multiple Marvell DDR controller. This will be the new structure: drivers/ddr/marvell/axp Supporting Armada XP (AXP) devices (and perhaps Armada 370) drivers/ddr/marvell/a38x Supporting Armada 38x devices (and perhaps Armada 39x) Signed-off-by: Stefan Roese --- include/configs/db-mv784mp-gp.h | 2 +- include/configs/maxbcm.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index aeddbf93d6e..41e6fdcb526 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -138,7 +138,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_SPD_EEPROM 0x4e #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 4826044857d..0fb117f9d36 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -108,7 +108,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ -- cgit v1.2.3 From 9e30b31d20f0b793465d07f056b3d9885f578c0d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 25 Mar 2015 13:35:15 +0100 Subject: arm: mvebu: db-88f6820: Add SPL support with DDR init code This patch adds SPL support for the Marvell DB-88F6820-GP board. With this change, the bin_hdr from the original Marvell U-boot is not needed any more on this board. The sources from bin_hdr (SERDES/PHY and DDR setup) are now integrated in mainline U-Boot. And this patch enables them for this board. Signed-off-by: Stefan Roese --- include/configs/db-88f6820-gp.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'include') diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index a429107a9af..73b323605e3 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -11,6 +11,7 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_ARMADA_38X #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ #define CONFIG_SYS_L2_PL310 @@ -108,6 +109,40 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR_A38X +#define CONFIG_DDR3 + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- cgit v1.2.3